[LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading

Duncan Sands baldrick at free.fr
Mon Dec 12 13:15:22 PST 2011

Hi Stepan, it was never really decided how to represent v2i5 in memory
(bitpacked?), and the code generators just don't support it right now.

> Hi all. The question about 'load' instruction.
> When we promote
> v2i5 = load<addr>  ;<MemoryVT = v2i5>
> to
> v2i64 = load<addr>  ;<MemoryVT = v2i5>
> should we insert vector shuffling that moves second v2i5 item to the
> second v2i64 item?

This question doesn't make any sense to me.  The operation should result
in the first i5 being in the low 5 bits of the first i64, and the second
i5 being in the low 5 bits of the second i64.  That's the definition of
this extending load operation.  Talking about shuffling only makes sense
in terms of a particular implementation of this operation, and I'm not
sure what you have in mind.

Ciao, Duncan.

> Or it is still depends from target?
> Thanks.
> -Stepan.
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