[LLVMdev] [LLVM, llc] TypeLegalization, DAGCombining, vectors loading

[Stepan Dyatkovskiy]

Hi all. The question about 'load' instruction.
When we promote
v2i5 = load <addr> ; <MemoryVT = v2i5>
to
v2i64 = load <addr> ;<MemoryVT = v2i5>

should we insert vector shuffling that moves second v2i5 item to the 
second v2i64 item?

Or it is still depends from target?

Thanks.

-Stepan.