[LLVMdev] disabling combining load/stores in optimizer.

[Chris Lattner]

On Aug 4, 2009, at 9:51 AM, Alireza.Moshtaghi at microchip.com wrote:

>
>>> So I think it should be at the discretion of port to enable or
> disable
>>> such optimizations as needed.
>>
>> While that it a valid approach in general, it is completely at odds
>> with the approach that the LLVM codebase has taken.  The general LLVM
>> philosophy is that all optimizations should be as aggressive as
>> possible at whatever they do, and it is then the responsibility of  
>> the
>> target to lower what the optimizers produce into something legal for
>> that machine.
>>
>> Contravention of that design philosophy in a major portion of the
>> optimization suite is unlikely at best, to be honest.
>>
>
> I can see the benefits of this approach at a macro-level, however at
> micro-level the impact is visible especially in embedded targets with
> limited memory and register resources (such as pic16)

Is this actually causing a performance problem in practice?  If so,  
please show the generated and desired code for a tiny testcase.   
Instead of talking theory, please give an example.

-Chris