[LLVMdev] disabling combining load/stores in optimizer.

[Alireza.Moshtaghi at microchip.com]

> > So I think it should be at the discretion of port to enable or
disable
> > such optimizations as needed.
> 
> While that it a valid approach in general, it is completely at odds
> with the approach that the LLVM codebase has taken.  The general LLVM
> philosophy is that all optimizations should be as aggressive as
> possible at whatever they do, and it is then the responsibility of the
> target to lower what the optimizers produce into something legal for
> that machine.
> 
> Contravention of that design philosophy in a major portion of the
> optimization suite is unlikely at best, to be honest.
> 

I can see the benefits of this approach at a macro-level, however at
micro-level the impact is visible especially in embedded targets with
limited memory and register resources (such as pic16)
We see the impact not only wrto code quality but also compile time (to
recover the damage that the optimizer has done). The other problem is
that our port never seem to be stable because as such generic
optimizations get added, something new will break in our port and as
more and more higher end targets are being ported to llvm I expect more
and more optimizations be added that are at odds with our port.
That is why we are asking for a way to at least have some control on
such optimizations.

A.