[LLVMdev] Dump instruction list prior register allocation

[nkavv at physics.auth.gr]

Hi there,

I have a question on the LLVM internals.

Is it possible to dump an InstructionList (i.e. a (possibly) naively scheduled
assembly) prior register allocation? Does LLVM use infinite (virtual) registers
similar to MachSUIF? This is, of course, meant for a given target in contrast
to MachSUIF that features the SUIFvm ISA as low-level IR and such a dump is
possible at this point.

Plus:

How do things progress towards LLVM following release. Is Oct 31, a probable
date for the release? What about LLVM-TV, is it going to be included.


Nikolaos Kavvadias
<nkavv-at-physics-dot-auth-dot-gr>