[LLVMdev] Some backend questions

[Vladimir Prus]

Chris Lattner wrote:

> The ultimate solution is to use a pattern matching instruction selector
> (which we are working on).  In the meantime, depending on how RISCy your
> target is, it's pretty easy to get reasonable code with few special cases.
> Usually this is enough:
>
> ... visitAdd(Instruction &I) {
>
>   if (ConstantInt *C = dyn_cast<Constant>(I.getOperand(1))) {
>     // handle add r, i
>   } else {
>     // handle general 'add r,r' case.
>   }
> }
>
> In particular, I *strongly* recommend getting a working code generator
> first, even if it creates mind boggling ugly code... then make it generate
> great code.

Thanks, advice taken.

> > > BTW, what architecture are you targetting?
> >
> > That's NM6403 -- an DSP produced by one russian company
> > (http://module.ru). As I've already said, my interest is in my PhD
> > research -- I plan to run some analysis on LLVM representation and
> > assembler for that processor, so it would be more convenient if assembler
> > is produced by LLVM, and not the standard compiler.
>
> Ohhh, sounds great.  From a brief look through their data sheets, it looks
> like it's a pretty RISCy processor, but has some snazzy addressing modes
> with pre/post in/decrements.  

Yes. It's my impression that most DSPs have such "snazzy" addressing modes ;-)

> I assume that you're planning on only 
> targetting the RISC core and not the vector copro?

Right. It would be experemely hard to generate efficient code for the vector 
unit.

- Volodya