[LLVMdev] Some backend questions

[Chris Lattner]

On Mon, 7 Jun 2004, Vladimir Prus wrote:
> > If you do this (which I recommend for the first step), you'll notice that
> > it produces pretty horrible code, as all immediates are copied into
> > registers before they are used.  In other words, instead of getting:
> >
> >   R2 = add R1, 17
> >
> > You'll get:
> >
> >   R3 = mov 17
> >   R2 = add R2, R3
>
> Right... that's what alarmed me in the first place. I though about something
> code which create immediate operand from constant and virtual register from
> Value* which really points to Instruction*. There should also be some
> mechanism to avoid creating two immediate operands, if target does not allow
> that.

The ultimate solution is to use a pattern matching instruction selector
(which we are working on).  In the meantime, depending on how RISCy your
target is, it's pretty easy to get reasonable code with few special cases.
Usually this is enough:

... visitAdd(Instruction &I) {

  if (ConstantInt *C = dyn_cast<Constant>(I.getOperand(1))) {
    // handle add r, i
  } else {
    // handle general 'add r,r' case.
  }
}

In particular, I *strongly* recommend getting a working code generator
first, even if it creates mind boggling ugly code... then make it generate
great code.

> > BTW, what architecture are you targetting?
>
> That's NM6403 -- an DSP produced by one russian company (http://module.ru).
> As I've already said, my interest is in my PhD research -- I plan to run some
> analysis on LLVM representation and assembler for that processor, so it would
> be more convenient if assembler is produced by LLVM, and not the standard
> compiler.

Ohhh, sounds great.  From a brief look through their data sheets, it looks
like it's a pretty RISCy processor, but has some snazzy addressing modes
with pre/post in/decrements.  I assume that you're planning on only
targetting the RISC core and not the vector copro?

-Chris

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