[llvm] [Mips] Introduce ABI-specific register names and accessors (PR #224284)

[Jiaxun Yang via llvm-commits]

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@@ -84,74 +103,76 @@ class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
 
 let Namespace = "Mips" in {
   // General Purpose Registers
+  // TODO: Use R0-R31/R0_64-R31_64 record names without changing MIR names.
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FlyGoat wrote:

> To expand on the idea of of being able to use ABI register names, have you given any thought to adding ABI specific aliases on TableGen and C++ levels?

For C++ code I believe ABI specfic getters should be prefered. For TableGen I believe most of them are not ABI aware so we should use register index instead.

https://github.com/llvm/llvm-project/pull/224284