[llvm] [Mips] Introduce ABI-specific register names and accessors (PR #224284)

[Anton Rapetov via llvm-commits]

================
@@ -84,74 +103,76 @@ class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
 
 let Namespace = "Mips" in {
   // General Purpose Registers
+  // TODO: Use R0-R31/R0_64-R31_64 record names without changing MIR names.
----------------
willir wrote:

Hi @FlyGoat : Is your proposal is to change all TableGen names to R#?

https://github.com/llvm/llvm-project/pull/224284