[llvm] [Mips] Introduce ABI-specific register names and accessors (PR #224284)

[Jiaxun Yang via llvm-commits]

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@@ -84,74 +103,76 @@ class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
 
 let Namespace = "Mips" in {
   // General Purpose Registers
+  // TODO: Use R0-R31/R0_64-R31_64 record names without changing MIR names.
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FlyGoat wrote:

> I would highly recommend doing what we've done for RISC-V and using the numbered register names for things like MIR. Printing an ABI name that doesn't match the current ABI would be way too confusing, and having different register names between ABIs sounds like unnecessary complexity.

Unfortunately, the current behavior is exactly that: we can end up printing an ABI register name that doesn't match the current ABI.

I do think having meaningful register names in MIR is quite useful for debugging, though.

I made a draft implementation here: https://github.com/llvm/llvm-project/pull/228017. It doesn't seem too unreasonable complexity-wise.


https://github.com/llvm/llvm-project/pull/224284