[llvm] [AMDGPU][Codegen] Legalize 16bit register class in sdag (PR #220275)

[Matt Arsenault via llvm-commits]

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@@ -4781,6 +4781,283 @@ bool AMDGPUDAGToDAGISel::isUniformLoad(const SDNode *N) const {
                ->isMemOpHasNoClobberedMemOperand(N)));
 }
 
+const TargetRegisterClass *
+AMDGPUDAGToDAGISel::inferDefRegClass(SDNode *N) const {
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arsenm wrote:

getOperandRegClass should already handle this 

https://github.com/llvm/llvm-project/pull/220275