[llvm] [AMDGPU][Codegen] Legalize 16bit register class in sdag (PR #220275)

[Matt Arsenault via llvm-commits]

================
@@ -6540,6 +6540,15 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
         .addImm(AMDGPU::sub0_sub1)
         .addReg(Low64, RegState::Kill)
         .addImm(AMDGPU::sub2_sub3);
+  } else if (Size == 16 && ST.useRealTrue16Insts() && Opcode == AMDGPU::COPY) {
----------------
arsenm wrote:

This should be a separate change with a mir test 

https://github.com/llvm/llvm-project/pull/220275