[llvm] [AMDGPU] Scale the frame register in place when lowering scalar frame indices (PR #221972)

[Pankaj Dwivedi via llvm-commits]

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@@ -1924,6 +1933,66 @@ void SIFrameLowering::determinePrologEpilogSGPRSaves(
   }
 }
 
+// Match an instruction whose frame index eliminateFrameIndex has to materialize
+// into a scavenged SGPR while SCC is live.
+static bool hasScalarFrameIndexWithLiveSCC(const SIInstrInfo &TII,
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PankajDwivedi-25 wrote:

Agree, Updated.

https://github.com/llvm/llvm-project/pull/221972