[llvm] [AMDGPU] Scale the frame register in place when lowering scalar frame indices (PR #221972)

[Pankaj Dwivedi via llvm-commits]

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@@ -610,14 +611,17 @@ bool SILowerSGPRSpills::run(MachineFunction &MF) {
     MadeChange = true;
   }
 
-  if (SpilledToVirtVGPRLanes) {
+  // Frame index elimination may need the register to keep SCC alive across an
+  // SGPR spill to memory, and nothing can free one up after this point.
+  if (SpilledToVirtVGPRLanes || TFI->mayNeedExecCopyForScalarFrameIndex(MF)) {
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PankajDwivedi-25 wrote:

I have updated the patch.

https://github.com/llvm/llvm-project/pull/221972