[llvm] [AMDGPU] Scale the frame register in place when lowering scalar frame indices (PR #221972)

[Pankaj Dwivedi via llvm-commits]

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@@ -1924,6 +1933,66 @@ void SIFrameLowering::determinePrologEpilogSGPRSaves(
   }
 }
 
+// Match an instruction whose frame index eliminateFrameIndex has to materialize
+// into a scavenged SGPR while SCC is live.
+static bool hasScalarFrameIndexWithLiveSCC(const SIInstrInfo &TII,
+                                           const SIRegisterInfo &TRI,
+                                           const MachineInstr &MI) {
+  if (TII.isMUBUF(MI))
+    return false;
+
+  // A move reuses its own destination instead of scavenging. Keep in sync with
+  // the IsCopy handling in SIRegisterInfo::eliminateFrameIndex.
+  unsigned Opcode = MI.getOpcode();
+  if (Opcode == AMDGPU::S_MOV_B32 || Opcode == AMDGPU::V_MOV_B32_e32 ||
+      Opcode == AMDGPU::V_MOV_B32_e64)
+    return false;
+
+  bool HasScalarFrameIndex = false;
+  for (unsigned OpNo = 0, E = MI.getNumExplicitOperands(); OpNo != E; ++OpNo) {
+    if (!MI.getOperand(OpNo).isFI())
+      continue;
+    const TargetRegisterClass *RC = TII.getRegClass(MI.getDesc(), OpNo);
+    if (RC && SIRegisterInfo::isSGPRClass(RC)) {
+      HasScalarFrameIndex = true;
+      break;
+    }
+  }
+
+  if (!HasScalarFrameIndex)
+    return false;
+
+  // The spill and the reload land on either side of MI. An indefinite answer is
+  // not worth a register: the spill still reports rather than miscompiles.
+  const MachineBasicBlock &MBB = *MI.getParent();
+  MachineBasicBlock::const_iterator I(MI);
+  return MBB.computeRegisterLiveness(&TRI, AMDGPU::SCC, I) ==
+             MachineBasicBlock::LQR_Live ||
+         MBB.computeRegisterLiveness(&TRI, AMDGPU::SCC, std::next(I)) ==
+             MachineBasicBlock::LQR_Live;
+}
+
+bool SIFrameLowering::mayNeedExecCopyForScalarFrameIndex(
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PankajDwivedi-25 wrote:

I have updated the patch to handle this locally.

https://github.com/llvm/llvm-project/pull/221972