[llvm] [RISCV] Align Expand Pseudo Pass Names (PR #218277)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 23 12:06:47 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Sam Elliott (lenary)
<details>
<summary>Changes</summary>
There are four passes, each with different names/arguments. This change aligns the names and arguments as much as possible, and renames the pass files to match.
Some of the changes in RISCV.h look strange because I reordered the passes to be together.
---
Patch is 51.41 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/218277.diff
21 Files Affected:
- (modified) llvm/lib/Target/RISCV/CMakeLists.txt (+4-4)
- (modified) llvm/lib/Target/RISCV/RISCV.h (+24-23)
- (modified) llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp (+4-4)
- (renamed) llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp (+31-32)
- (renamed) llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp (+20-20)
- (renamed) llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp (+30-27)
- (renamed) llvm/lib/Target/RISCV/RISCVExpandPseudoPreRA.cpp (+20-21)
- (modified) llvm/lib/Target/RISCV/RISCVPassRegistry.def (+8-7)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+8-8)
- (modified) llvm/test/CodeGen/RISCV/O0-pipeline.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/O3-pipeline.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/expand-atomic-pseudo.mir (+4-4)
- (modified) llvm/test/CodeGen/RISCV/expand-pseudo.mir (+4-4)
- (modified) llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir (+1-1)
- (modified) llvm/test/CodeGen/RISCV/mir-target-flags.ll (+4-4)
- (modified) llvm/test/CodeGen/RISCV/postra-expand-pseudo.mir (+4-4)
- (modified) llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir (+4-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/aliases.mir (+2-2)
- (modified) llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp (+1-1)
``````````diff
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index b26a2deb89ef4..a3423acbde89c 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -37,9 +37,11 @@ add_llvm_target(RISCVCodeGen
RISCVCodeGenPrepare.cpp
RISCVConstantPoolValue.cpp
RISCVDeadRegisterDefinitions.cpp
- RISCVExpandAtomicPseudoInsts.cpp
+ RISCVExpandPseudoAtomics.cpp
RISCVExpandPseudoBase.cpp
- RISCVExpandPseudoInsts.cpp
+ RISCVExpandPseudoPostRA.cpp
+ RISCVExpandPseudoPreEmit.cpp
+ RISCVExpandPseudoPreRA.cpp
RISCVFoldMemOffset.cpp
RISCVFrameLowering.cpp
RISCVGatherScatterLowering.cpp
@@ -60,8 +62,6 @@ add_llvm_target(RISCVCodeGen
RISCVMergeBaseOffset.cpp
RISCVMoveMerger.cpp
RISCVOptWInstrs.cpp
- RISCVPostRAExpandPseudoInsts.cpp
- RISCVPreRAExpandPseudoInsts.cpp
RISCVPromoteConstant.cpp
RISCVPushPopOptimizer.cpp
RISCVQCRelaxMarking.cpp
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 355fe8c60b65e..9d443c06715f5 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -110,52 +110,53 @@ void initializeRISCVFoldMemOffsetLegacyPass(PassRegistry &);
FunctionPass *createRISCVMergeBaseOffsetOptPass();
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
-class RISCVExpandPseudoPass
- : public RequiredPassInfoMixin<RISCVExpandPseudoPass> {
+class RISCVExpandPseudoPreRAPass
+ : public RequiredPassInfoMixin<RISCVExpandPseudoPreRAPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().setIsSSA();
+ }
};
-FunctionPass *createRISCVExpandPseudoLegacyPass();
-void initializeRISCVExpandPseudoLegacyPass(PassRegistry &);
+FunctionPass *createRISCVExpandPseudoPreRALegacyPass();
+void initializeRISCVExpandPseudoPreRALegacyPass(PassRegistry &);
-class RISCVPreRAExpandPseudoPass
- : public RequiredPassInfoMixin<RISCVPreRAExpandPseudoPass> {
+class RISCVExpandPseudoPostRAPass
+ : public RequiredPassInfoMixin<RISCVExpandPseudoPostRAPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
- MachineFunctionProperties getRequiredProperties() const {
- return MachineFunctionProperties().setIsSSA();
- }
};
-FunctionPass *createRISCVPreRAExpandPseudoLegacyPass();
-void initializeRISCVPreRAExpandPseudoLegacyPass(PassRegistry &);
+FunctionPass *createRISCVExpandPseudoPostRALegacyPass();
+void initializeRISCVExpandPseudoPostRALegacyPass(PassRegistry &);
-class RISCVExpandAtomicPseudoPass
- : public RequiredPassInfoMixin<RISCVExpandAtomicPseudoPass> {
+class RISCVExpandPseudoPreEmitPass
+ : public RequiredPassInfoMixin<RISCVExpandPseudoPreEmitPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};
-FunctionPass *createRISCVExpandAtomicPseudoLegacyPass();
-void initializeRISCVExpandAtomicPseudoLegacyPass(PassRegistry &);
+FunctionPass *createRISCVExpandPseudoPreEmitLegacyPass();
+void initializeRISCVExpandPseudoPreEmitLegacyPass(PassRegistry &);
-FunctionPass *createRISCVInsertVSETVLIPass();
-void initializeRISCVInsertVSETVLIPass(PassRegistry &);
-extern char &RISCVInsertVSETVLIID;
-
-class RISCVPostRAExpandPseudoPass
- : public RequiredPassInfoMixin<RISCVPostRAExpandPseudoPass> {
+class RISCVExpandPseudoAtomicsPass
+ : public RequiredPassInfoMixin<RISCVExpandPseudoAtomicsPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};
-FunctionPass *createRISCVPostRAExpandPseudoLegacyPass();
-void initializeRISCVPostRAExpandPseudoLegacyPass(PassRegistry &);
+FunctionPass *createRISCVExpandPseudoAtomicsLegacyPass();
+void initializeRISCVExpandPseudoAtomicsLegacyPass(PassRegistry &);
+
+FunctionPass *createRISCVInsertVSETVLIPass();
+void initializeRISCVInsertVSETVLIPass(PassRegistry &);
+extern char &RISCVInsertVSETVLIID;
+
FunctionPass *createRISCVInsertReadWriteCSRPass();
void initializeRISCVInsertReadWriteCSRPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
index 6aead1f6fec58..5f012f20a502c 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
@@ -123,7 +123,7 @@ void RISCVCodeGenPassBuilder::addMachineSSAOptimization(
}
void RISCVCodeGenPassBuilder::addPreRegAlloc(PassManagerWrapper &PMW) {
- addMachineFunctionPass(RISCVPreRAExpandPseudoPass(), PMW);
+ addMachineFunctionPass(RISCVExpandPseudoPreRAPass(), PMW);
if (getOptLevel() != CodeGenOptLevel::None) {
// TODO: RISCVMergeBaseOffsetOptPass
// TODO: RISCVPreAllocZilsdOptPass
@@ -145,7 +145,7 @@ void RISCVCodeGenPassBuilder::addPostRegAlloc(PassManagerWrapper &PMW) {
}
void RISCVCodeGenPassBuilder::addPreSched2(PassManagerWrapper &PMW) {
- addMachineFunctionPass(RISCVPostRAExpandPseudoPass(), PMW);
+ addMachineFunctionPass(RISCVExpandPseudoPostRAPass(), PMW);
addMachineFunctionPass(MachineKCFIPass(), PMW);
if (getOptLevel() != CodeGenOptLevel::None) {
@@ -176,7 +176,7 @@ void RISCVCodeGenPassBuilder::addPreEmitPass2(PassManagerWrapper &PMW) {
// TODO: RISCVMoveMergePass
// TODO: RISCVPushPopOptimizationPass
}
- addMachineFunctionPass(RISCVExpandPseudoPass(), PMW);
+ addMachineFunctionPass(RISCVExpandPseudoPreEmitPass(), PMW);
// Add QC Relaxation Markers as late as possible, and only for RV32
if (getOptLevel() != CodeGenOptLevel::None &&
@@ -184,7 +184,7 @@ void RISCVCodeGenPassBuilder::addPreEmitPass2(PassManagerWrapper &PMW) {
// TODO: RISCVQCRelaxMarkingPass
}
- addMachineFunctionPass(RISCVExpandAtomicPseudoPass(), PMW);
+ addMachineFunctionPass(RISCVExpandPseudoAtomicsPass(), PMW);
// KCFI indirect call checks are lowered to a bundle.
addMachineFunctionPass(
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp
similarity index 94%
rename from llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
rename to llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp
index 02fc4f7147ee8..bb62f607cbb6d 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp
@@ -1,4 +1,4 @@
-//===-- RISCVExpandAtomicPseudoInsts.cpp - Expand atomic pseudo instrs. ---===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -23,12 +23,11 @@
using namespace llvm;
-#define RISCV_EXPAND_ATOMIC_PSEUDO_NAME \
- "RISC-V atomic pseudo instruction expansion pass"
+#define RISCV_EXPAND_PSEUDO_ATOMICS_NAME "RISC-V Pseudo Instruction Expansion - Atomics"
namespace {
-class RISCVExpandAtomicPseudoImpl final : public RISCVExpandPseudoImplBase {
+class RISCVExpandPseudoAtomicsImpl final : public RISCVExpandPseudoImplBase {
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const override;
@@ -83,24 +82,24 @@ class RISCVExpandAtomicPseudoImpl final : public RISCVExpandPseudoImplBase {
MachineBasicBlock *&LoopHeadBNETarget) const;
};
-class RISCVExpandAtomicPseudoLegacy : public MachineFunctionPass {
+class RISCVExpandPseudoAtomicsLegacy : public MachineFunctionPass {
public:
static char ID;
- RISCVExpandAtomicPseudoLegacy() : MachineFunctionPass(ID) {}
+ RISCVExpandPseudoAtomicsLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override {
- return RISCVExpandAtomicPseudoImpl().run(MF);
+ return RISCVExpandPseudoAtomicsImpl().run(MF);
}
StringRef getPassName() const override {
- return RISCV_EXPAND_ATOMIC_PSEUDO_NAME;
+ return RISCV_EXPAND_PSEUDO_ATOMICS_NAME;
}
};
} // anonymous namespace
-bool RISCVExpandAtomicPseudoImpl::expandMI(
+bool RISCVExpandPseudoAtomicsImpl::expandMI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const {
// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
@@ -205,7 +204,7 @@ bool RISCVExpandAtomicPseudoImpl::expandMI(
}
unsigned
-RISCVExpandAtomicPseudoImpl::getLRForRMW32(AtomicOrdering Ordering) const {
+RISCVExpandPseudoAtomicsImpl::getLRForRMW32(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
@@ -227,7 +226,7 @@ RISCVExpandAtomicPseudoImpl::getLRForRMW32(AtomicOrdering Ordering) const {
}
unsigned
-RISCVExpandAtomicPseudoImpl::getSCForRMW32(AtomicOrdering Ordering) const {
+RISCVExpandPseudoAtomicsImpl::getSCForRMW32(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
@@ -249,7 +248,7 @@ RISCVExpandAtomicPseudoImpl::getSCForRMW32(AtomicOrdering Ordering) const {
}
unsigned
-RISCVExpandAtomicPseudoImpl::getLRForRMW64(AtomicOrdering Ordering) const {
+RISCVExpandPseudoAtomicsImpl::getLRForRMW64(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
@@ -271,7 +270,7 @@ RISCVExpandAtomicPseudoImpl::getLRForRMW64(AtomicOrdering Ordering) const {
}
unsigned
-RISCVExpandAtomicPseudoImpl::getSCForRMW64(AtomicOrdering Ordering) const {
+RISCVExpandPseudoAtomicsImpl::getSCForRMW64(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
@@ -292,7 +291,7 @@ RISCVExpandAtomicPseudoImpl::getSCForRMW64(AtomicOrdering Ordering) const {
}
}
-unsigned RISCVExpandAtomicPseudoImpl::getLRForRMW(AtomicOrdering Ordering,
+unsigned RISCVExpandPseudoAtomicsImpl::getLRForRMW(AtomicOrdering Ordering,
int Width) const {
if (Width == 32)
return getLRForRMW32(Ordering);
@@ -301,7 +300,7 @@ unsigned RISCVExpandAtomicPseudoImpl::getLRForRMW(AtomicOrdering Ordering,
llvm_unreachable("Unexpected LR width\n");
}
-unsigned RISCVExpandAtomicPseudoImpl::getSCForRMW(AtomicOrdering Ordering,
+unsigned RISCVExpandPseudoAtomicsImpl::getSCForRMW(AtomicOrdering Ordering,
int Width) const {
if (Width == 32)
return getSCForRMW32(Ordering);
@@ -310,7 +309,7 @@ unsigned RISCVExpandAtomicPseudoImpl::getSCForRMW(AtomicOrdering Ordering,
llvm_unreachable("Unexpected SC width\n");
}
-void RISCVExpandAtomicPseudoImpl::doAtomicBinOpExpansion(
+void RISCVExpandPseudoAtomicsImpl::doAtomicBinOpExpansion(
MachineInstr &MI, MachineBasicBlock *LoopMBB, AtomicRMWInst::BinOp BinOp,
int Width) const {
DebugLoc DL = MI.getDebugLoc();
@@ -399,7 +398,7 @@ void RISCVExpandAtomicPseudoImpl::doAtomicBinOpExpansion(
.addMBB(LoopMBB);
}
-void RISCVExpandAtomicPseudoImpl::insertMaskedMerge(
+void RISCVExpandPseudoAtomicsImpl::insertMaskedMerge(
DebugLoc DL, MachineBasicBlock *MBB, Register DestReg, Register OldValReg,
Register NewValReg, Register MaskReg, Register ScratchReg) const {
assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique");
@@ -420,7 +419,7 @@ void RISCVExpandAtomicPseudoImpl::insertMaskedMerge(
.addReg(ScratchReg);
}
-void RISCVExpandAtomicPseudoImpl::doMaskedAtomicBinOpExpansion(
+void RISCVExpandPseudoAtomicsImpl::doMaskedAtomicBinOpExpansion(
MachineInstr &MI, MachineBasicBlock *LoopMBB, AtomicRMWInst::BinOp BinOp,
int Width) const {
DebugLoc DL = MI.getDebugLoc();
@@ -483,7 +482,7 @@ void RISCVExpandAtomicPseudoImpl::doMaskedAtomicBinOpExpansion(
.addMBB(LoopMBB);
}
-bool RISCVExpandAtomicPseudoImpl::expandAtomicBinOp(
+bool RISCVExpandPseudoAtomicsImpl::expandAtomicBinOp(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
MachineBasicBlock::iterator &NextMBBI) const {
@@ -518,7 +517,7 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicBinOp(
return true;
}
-void RISCVExpandAtomicPseudoImpl::insertSext(DebugLoc DL,
+void RISCVExpandPseudoAtomicsImpl::insertSext(DebugLoc DL,
MachineBasicBlock *MBB,
Register ValReg,
Register ShamtReg) const {
@@ -530,7 +529,7 @@ void RISCVExpandAtomicPseudoImpl::insertSext(DebugLoc DL,
.addReg(ShamtReg);
}
-void RISCVExpandAtomicPseudoImpl::doAtomicMinMaxOpExpansion(
+void RISCVExpandPseudoAtomicsImpl::doAtomicMinMaxOpExpansion(
MachineInstr &MI, MachineBasicBlock *LoopHeadMBB,
MachineBasicBlock *LoopIfBodyMBB, MachineBasicBlock *LoopTailMBB,
AtomicRMWInst::BinOp BinOp, int Width) const {
@@ -600,7 +599,7 @@ void RISCVExpandAtomicPseudoImpl::doAtomicMinMaxOpExpansion(
.addMBB(LoopHeadMBB);
}
-void RISCVExpandAtomicPseudoImpl::doMaskedAtomicMinMaxOpExpansion(
+void RISCVExpandPseudoAtomicsImpl::doMaskedAtomicMinMaxOpExpansion(
MachineInstr &MI, MachineBasicBlock *LoopHeadMBB,
MachineBasicBlock *LoopIfBodyMBB, MachineBasicBlock *LoopTailMBB,
AtomicRMWInst::BinOp BinOp, int Width) const {
@@ -684,7 +683,7 @@ void RISCVExpandAtomicPseudoImpl::doMaskedAtomicMinMaxOpExpansion(
.addMBB(LoopHeadMBB);
}
-bool RISCVExpandAtomicPseudoImpl::expandAtomicMinMaxOp(
+bool RISCVExpandPseudoAtomicsImpl::expandAtomicMinMaxOp(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
MachineBasicBlock::iterator &NextMBBI) const {
@@ -745,7 +744,7 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicMinMaxOp(
// On success, returns true and deletes the matching BNE or AND+BNE, sets the
// LoopHeadBNETarget argument to the target that should be used within the
// loop head, and removes that block as a successor to MBB.
-bool RISCVExpandAtomicPseudoImpl::tryToFoldBNEOnCmpXchgResult(
+bool RISCVExpandPseudoAtomicsImpl::tryToFoldBNEOnCmpXchgResult(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
Register CmpValReg, Register MaskReg,
MachineBasicBlock *&LoopHeadBNETarget) const {
@@ -799,7 +798,7 @@ bool RISCVExpandAtomicPseudoImpl::tryToFoldBNEOnCmpXchgResult(
return true;
}
-bool RISCVExpandAtomicPseudoImpl::expandAtomicCmpXchg(
+bool RISCVExpandPseudoAtomicsImpl::expandAtomicCmpXchg(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsMasked,
int Width, MachineBasicBlock::iterator &NextMBBI) const {
MachineInstr &MI = *MBBI;
@@ -901,19 +900,19 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicCmpXchg(
return true;
}
-char RISCVExpandAtomicPseudoLegacy::ID = 0;
+char RISCVExpandPseudoAtomicsLegacy::ID = 0;
-INITIALIZE_PASS(RISCVExpandAtomicPseudoLegacy, "riscv-expand-atomic-pseudo",
- RISCV_EXPAND_ATOMIC_PSEUDO_NAME, false, false)
+INITIALIZE_PASS(RISCVExpandPseudoAtomicsLegacy, "riscv-expand-pseudo-atomics",
+ RISCV_EXPAND_PSEUDO_ATOMICS_NAME, false, false)
-FunctionPass *llvm::createRISCVExpandAtomicPseudoLegacyPass() {
- return new RISCVExpandAtomicPseudoLegacy();
+FunctionPass *llvm::createRISCVExpandPseudoAtomicsLegacyPass() {
+ return new RISCVExpandPseudoAtomicsLegacy();
}
PreservedAnalyses
-RISCVExpandAtomicPseudoPass::run(MachineFunction &MF,
+RISCVExpandPseudoAtomicsPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
- bool Changed = RISCVExpandAtomicPseudoImpl().run(MF);
+ bool Changed = RISCVExpandPseudoAtomicsImpl().run(MF);
if (!Changed)
return PreservedAnalyses::all();
return getMachineFunctionPassPreservedAnalyses();
diff --git a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
similarity index 86%
rename from llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
rename to llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
index f3ade17e4fdb9..c833c1c7ee3c2 100644
--- a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
@@ -1,4 +1,4 @@
-//===-- RISCVPostRAExpandPseudoInsts.cpp - Expand pseudo instrs ----===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -21,12 +21,12 @@
using namespace llvm;
-#define RISCV_POST_RA_EXPAND_PSEUDO_NAME \
- "RISC-V post-regalloc pseudo instruction expansion pass"
+#define RISCV_EXPAND_PSEUDO_POST_RA_NAME \
+ "RISC-V Pseudo Instruction Expansion - Post-RA"
namespace {
-class RISCVPostRAExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
+class RISCVExpandPseudoPostRAImpl final : public RISCVExpandPseudoImplBase {
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const override;
@@ -43,14 +43,14 @@ class RISCVPostRAExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
MachineBasicBlock::iterator MBBI) const;
};
-class RISCVPostRAExpandPseudoLegacy : public MachineFunctionPass {
+class RISCVExpandPseudoPostRALegacy : public MachineFunctionPass {
public:
static char ID;
- RISCVPostRAExpandPseudoLegacy() : MachineFunctionPass(ID) {}
+ RISCVExpandPseudoPostRALegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override {
- return RISCVPostRAExpandPseudoImpl().run(MF);
+ return RISCVExpandPseudoPostRAImpl().run(MF);
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
@@ -59,13 +59,13 @@ class RISCVPostRAExpandPseudoLegacy : public MachineFunctionPass {
}
StringRef getPassName() const override {
- return RISCV_POST_RA_EXPAND_PSEUDO_NAME;
+ return RISCV_EXPAND_PSEUDO_POST_RA_NAME;
}
};
} // anonymous namespace
-bool RISCVPostRAExpandPseudoImpl::expandMI(
+bool RISCVExpandPseudoPostRAImpl::expandMI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const {
switch (MBBI->getOpcode()) {
@@ -82,7 +82,7 @@ bool RISCVPostRAExpandPseudoImpl::expandMI(
return false;
}
-bool RISCVPostRAExpandPseudoImpl::expandMovImm(
+bool RISCVExpandPseudoPostRAImpl::expandMovImm(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
@@ -99,7 +99,7 @@ bool RISCVPostRAExpandPseudoImpl::expandMovImm(
return true;
}
-bool RISCVPostRAExpandPseudoImpl::expandMovAddr(
+bool RISCVExpandPseudoPostRAImpl::expandMovAddr(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
@@ -119,7 +119,7 @@ bool RISCVPostRAExpandPseudoImpl::expandMovAddr(
return true;
}
-bool RISCVPostRAExpandPseudoImpl::expandAddUpperImm(
+bool RISCVExpandPseudoPostRAImpl::expandAddUpperImm(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
@@ -155,7 +155,7 @@ static void transferImpOps(const MachineInstr &OldMI, MachineInstrBuilder &MI) {
}
// Expand PseudoMERGE to MERGE, MVM, or MVMN.
-bool RISCVPostRAExpandPseudoImpl::expandMERGE(
+bool RISCVExpandPseudoPostRAImpl::expandMERGE(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
@@ -210,19 +210,19 @@ bool RISCVPostRAExpandPseudoImpl::expandMERGE(
return true;
}
-char RISCVPostRAExpandPseudoLegacy::ID = 0;
+char RISCVExpandPseudoPostRALegacy::ID = 0;
-INITIALIZE_PASS(RISCVPostRAExpandPseudoLegacy, "riscv-post-ra-expand-pseudo",
- RISCV_POST_RA_EXPAND_PSEUDO_NAME, false, false)
+INITIALIZE_PASS(RISCVExpandPseudoPostRALegacy, "riscv-expand-pseudo-post-ra",
+ RI...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/218277
More information about the llvm-commits
mailing list