[llvm] [RISCV] Align Expand Pseudo Pass Names (PR #218277)
Sam Elliott via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 23 12:06:08 PDT 2026
https://github.com/lenary created https://github.com/llvm/llvm-project/pull/218277
There are four passes, each with different names/arguments. This change aligns the names and arguments as much as possible, and renames the pass files to match.
Some of the changes in RISCV.h look strange because I reordered the passes to be together.
>From 1b96eed27afa3492f10ff6b0aea40c688c8deecf Mon Sep 17 00:00:00 2001
From: Sam Elliott <aelliott at qti.qualcomm.com>
Date: Sat, 22 Aug 2026 16:51:05 -0700
Subject: [PATCH] [RISCV] Align Expand Pseudo Pass Names
There are four passes, each with different names/arguments. This change
aligns the names and arguments as much as possible, and renames the
pass files to match.
---
llvm/lib/Target/RISCV/CMakeLists.txt | 8 +--
llvm/lib/Target/RISCV/RISCV.h | 47 +++++++-------
.../Target/RISCV/RISCVCodeGenPassBuilder.cpp | 8 +--
...Insts.cpp => RISCVExpandPseudoAtomics.cpp} | 63 +++++++++----------
...oInsts.cpp => RISCVExpandPseudoPostRA.cpp} | 40 ++++++------
...Insts.cpp => RISCVExpandPseudoPreEmit.cpp} | 57 +++++++++--------
...doInsts.cpp => RISCVExpandPseudoPreRA.cpp} | 41 ++++++------
llvm/lib/Target/RISCV/RISCVPassRegistry.def | 15 ++---
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 16 ++---
llvm/test/CodeGen/RISCV/O0-pipeline.ll | 8 +--
llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll | 8 +--
llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll | 8 +--
llvm/test/CodeGen/RISCV/O3-pipeline.ll | 8 +--
.../CodeGen/RISCV/expand-atomic-pseudo.mir | 8 +--
llvm/test/CodeGen/RISCV/expand-pseudo.mir | 8 +--
.../CodeGen/RISCV/frame-base-addr-reuse.mir | 2 +-
llvm/test/CodeGen/RISCV/mir-target-flags.ll | 8 +--
.../CodeGen/RISCV/postra-expand-pseudo.mir | 8 +--
.../CodeGen/RISCV/prera-expand-pseudo.mir | 8 +--
llvm/test/CodeGen/RISCV/rvv/aliases.mir | 4 +-
llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp | 2 +-
21 files changed, 189 insertions(+), 186 deletions(-)
rename llvm/lib/Target/RISCV/{RISCVExpandAtomicPseudoInsts.cpp => RISCVExpandPseudoAtomics.cpp} (94%)
rename llvm/lib/Target/RISCV/{RISCVPostRAExpandPseudoInsts.cpp => RISCVExpandPseudoPostRA.cpp} (86%)
rename llvm/lib/Target/RISCV/{RISCVExpandPseudoInsts.cpp => RISCVExpandPseudoPreEmit.cpp} (92%)
rename llvm/lib/Target/RISCV/{RISCVPreRAExpandPseudoInsts.cpp => RISCVExpandPseudoPreRA.cpp} (84%)
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index b26a2deb89ef4..a3423acbde89c 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -37,9 +37,11 @@ add_llvm_target(RISCVCodeGen
RISCVCodeGenPrepare.cpp
RISCVConstantPoolValue.cpp
RISCVDeadRegisterDefinitions.cpp
- RISCVExpandAtomicPseudoInsts.cpp
+ RISCVExpandPseudoAtomics.cpp
RISCVExpandPseudoBase.cpp
- RISCVExpandPseudoInsts.cpp
+ RISCVExpandPseudoPostRA.cpp
+ RISCVExpandPseudoPreEmit.cpp
+ RISCVExpandPseudoPreRA.cpp
RISCVFoldMemOffset.cpp
RISCVFrameLowering.cpp
RISCVGatherScatterLowering.cpp
@@ -60,8 +62,6 @@ add_llvm_target(RISCVCodeGen
RISCVMergeBaseOffset.cpp
RISCVMoveMerger.cpp
RISCVOptWInstrs.cpp
- RISCVPostRAExpandPseudoInsts.cpp
- RISCVPreRAExpandPseudoInsts.cpp
RISCVPromoteConstant.cpp
RISCVPushPopOptimizer.cpp
RISCVQCRelaxMarking.cpp
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 355fe8c60b65e..9d443c06715f5 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -110,52 +110,53 @@ void initializeRISCVFoldMemOffsetLegacyPass(PassRegistry &);
FunctionPass *createRISCVMergeBaseOffsetOptPass();
void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
-class RISCVExpandPseudoPass
- : public RequiredPassInfoMixin<RISCVExpandPseudoPass> {
+class RISCVExpandPseudoPreRAPass
+ : public RequiredPassInfoMixin<RISCVExpandPseudoPreRAPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().setIsSSA();
+ }
};
-FunctionPass *createRISCVExpandPseudoLegacyPass();
-void initializeRISCVExpandPseudoLegacyPass(PassRegistry &);
+FunctionPass *createRISCVExpandPseudoPreRALegacyPass();
+void initializeRISCVExpandPseudoPreRALegacyPass(PassRegistry &);
-class RISCVPreRAExpandPseudoPass
- : public RequiredPassInfoMixin<RISCVPreRAExpandPseudoPass> {
+class RISCVExpandPseudoPostRAPass
+ : public RequiredPassInfoMixin<RISCVExpandPseudoPostRAPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
- MachineFunctionProperties getRequiredProperties() const {
- return MachineFunctionProperties().setIsSSA();
- }
};
-FunctionPass *createRISCVPreRAExpandPseudoLegacyPass();
-void initializeRISCVPreRAExpandPseudoLegacyPass(PassRegistry &);
+FunctionPass *createRISCVExpandPseudoPostRALegacyPass();
+void initializeRISCVExpandPseudoPostRALegacyPass(PassRegistry &);
-class RISCVExpandAtomicPseudoPass
- : public RequiredPassInfoMixin<RISCVExpandAtomicPseudoPass> {
+class RISCVExpandPseudoPreEmitPass
+ : public RequiredPassInfoMixin<RISCVExpandPseudoPreEmitPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};
-FunctionPass *createRISCVExpandAtomicPseudoLegacyPass();
-void initializeRISCVExpandAtomicPseudoLegacyPass(PassRegistry &);
+FunctionPass *createRISCVExpandPseudoPreEmitLegacyPass();
+void initializeRISCVExpandPseudoPreEmitLegacyPass(PassRegistry &);
-FunctionPass *createRISCVInsertVSETVLIPass();
-void initializeRISCVInsertVSETVLIPass(PassRegistry &);
-extern char &RISCVInsertVSETVLIID;
-
-class RISCVPostRAExpandPseudoPass
- : public RequiredPassInfoMixin<RISCVPostRAExpandPseudoPass> {
+class RISCVExpandPseudoAtomicsPass
+ : public RequiredPassInfoMixin<RISCVExpandPseudoAtomicsPass> {
public:
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};
-FunctionPass *createRISCVPostRAExpandPseudoLegacyPass();
-void initializeRISCVPostRAExpandPseudoLegacyPass(PassRegistry &);
+FunctionPass *createRISCVExpandPseudoAtomicsLegacyPass();
+void initializeRISCVExpandPseudoAtomicsLegacyPass(PassRegistry &);
+
+FunctionPass *createRISCVInsertVSETVLIPass();
+void initializeRISCVInsertVSETVLIPass(PassRegistry &);
+extern char &RISCVInsertVSETVLIID;
+
FunctionPass *createRISCVInsertReadWriteCSRPass();
void initializeRISCVInsertReadWriteCSRPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
index 6aead1f6fec58..5f012f20a502c 100644
--- a/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
+++ b/llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp
@@ -123,7 +123,7 @@ void RISCVCodeGenPassBuilder::addMachineSSAOptimization(
}
void RISCVCodeGenPassBuilder::addPreRegAlloc(PassManagerWrapper &PMW) {
- addMachineFunctionPass(RISCVPreRAExpandPseudoPass(), PMW);
+ addMachineFunctionPass(RISCVExpandPseudoPreRAPass(), PMW);
if (getOptLevel() != CodeGenOptLevel::None) {
// TODO: RISCVMergeBaseOffsetOptPass
// TODO: RISCVPreAllocZilsdOptPass
@@ -145,7 +145,7 @@ void RISCVCodeGenPassBuilder::addPostRegAlloc(PassManagerWrapper &PMW) {
}
void RISCVCodeGenPassBuilder::addPreSched2(PassManagerWrapper &PMW) {
- addMachineFunctionPass(RISCVPostRAExpandPseudoPass(), PMW);
+ addMachineFunctionPass(RISCVExpandPseudoPostRAPass(), PMW);
addMachineFunctionPass(MachineKCFIPass(), PMW);
if (getOptLevel() != CodeGenOptLevel::None) {
@@ -176,7 +176,7 @@ void RISCVCodeGenPassBuilder::addPreEmitPass2(PassManagerWrapper &PMW) {
// TODO: RISCVMoveMergePass
// TODO: RISCVPushPopOptimizationPass
}
- addMachineFunctionPass(RISCVExpandPseudoPass(), PMW);
+ addMachineFunctionPass(RISCVExpandPseudoPreEmitPass(), PMW);
// Add QC Relaxation Markers as late as possible, and only for RV32
if (getOptLevel() != CodeGenOptLevel::None &&
@@ -184,7 +184,7 @@ void RISCVCodeGenPassBuilder::addPreEmitPass2(PassManagerWrapper &PMW) {
// TODO: RISCVQCRelaxMarkingPass
}
- addMachineFunctionPass(RISCVExpandAtomicPseudoPass(), PMW);
+ addMachineFunctionPass(RISCVExpandPseudoAtomicsPass(), PMW);
// KCFI indirect call checks are lowered to a bundle.
addMachineFunctionPass(
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp
similarity index 94%
rename from llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
rename to llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp
index 02fc4f7147ee8..bb62f607cbb6d 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp
@@ -1,4 +1,4 @@
-//===-- RISCVExpandAtomicPseudoInsts.cpp - Expand atomic pseudo instrs. ---===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -23,12 +23,11 @@
using namespace llvm;
-#define RISCV_EXPAND_ATOMIC_PSEUDO_NAME \
- "RISC-V atomic pseudo instruction expansion pass"
+#define RISCV_EXPAND_PSEUDO_ATOMICS_NAME "RISC-V Pseudo Instruction Expansion - Atomics"
namespace {
-class RISCVExpandAtomicPseudoImpl final : public RISCVExpandPseudoImplBase {
+class RISCVExpandPseudoAtomicsImpl final : public RISCVExpandPseudoImplBase {
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const override;
@@ -83,24 +82,24 @@ class RISCVExpandAtomicPseudoImpl final : public RISCVExpandPseudoImplBase {
MachineBasicBlock *&LoopHeadBNETarget) const;
};
-class RISCVExpandAtomicPseudoLegacy : public MachineFunctionPass {
+class RISCVExpandPseudoAtomicsLegacy : public MachineFunctionPass {
public:
static char ID;
- RISCVExpandAtomicPseudoLegacy() : MachineFunctionPass(ID) {}
+ RISCVExpandPseudoAtomicsLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override {
- return RISCVExpandAtomicPseudoImpl().run(MF);
+ return RISCVExpandPseudoAtomicsImpl().run(MF);
}
StringRef getPassName() const override {
- return RISCV_EXPAND_ATOMIC_PSEUDO_NAME;
+ return RISCV_EXPAND_PSEUDO_ATOMICS_NAME;
}
};
} // anonymous namespace
-bool RISCVExpandAtomicPseudoImpl::expandMI(
+bool RISCVExpandPseudoAtomicsImpl::expandMI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const {
// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
@@ -205,7 +204,7 @@ bool RISCVExpandAtomicPseudoImpl::expandMI(
}
unsigned
-RISCVExpandAtomicPseudoImpl::getLRForRMW32(AtomicOrdering Ordering) const {
+RISCVExpandPseudoAtomicsImpl::getLRForRMW32(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
@@ -227,7 +226,7 @@ RISCVExpandAtomicPseudoImpl::getLRForRMW32(AtomicOrdering Ordering) const {
}
unsigned
-RISCVExpandAtomicPseudoImpl::getSCForRMW32(AtomicOrdering Ordering) const {
+RISCVExpandPseudoAtomicsImpl::getSCForRMW32(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
@@ -249,7 +248,7 @@ RISCVExpandAtomicPseudoImpl::getSCForRMW32(AtomicOrdering Ordering) const {
}
unsigned
-RISCVExpandAtomicPseudoImpl::getLRForRMW64(AtomicOrdering Ordering) const {
+RISCVExpandPseudoAtomicsImpl::getLRForRMW64(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
@@ -271,7 +270,7 @@ RISCVExpandAtomicPseudoImpl::getLRForRMW64(AtomicOrdering Ordering) const {
}
unsigned
-RISCVExpandAtomicPseudoImpl::getSCForRMW64(AtomicOrdering Ordering) const {
+RISCVExpandPseudoAtomicsImpl::getSCForRMW64(AtomicOrdering Ordering) const {
switch (Ordering) {
default:
llvm_unreachable("Unexpected AtomicOrdering");
@@ -292,7 +291,7 @@ RISCVExpandAtomicPseudoImpl::getSCForRMW64(AtomicOrdering Ordering) const {
}
}
-unsigned RISCVExpandAtomicPseudoImpl::getLRForRMW(AtomicOrdering Ordering,
+unsigned RISCVExpandPseudoAtomicsImpl::getLRForRMW(AtomicOrdering Ordering,
int Width) const {
if (Width == 32)
return getLRForRMW32(Ordering);
@@ -301,7 +300,7 @@ unsigned RISCVExpandAtomicPseudoImpl::getLRForRMW(AtomicOrdering Ordering,
llvm_unreachable("Unexpected LR width\n");
}
-unsigned RISCVExpandAtomicPseudoImpl::getSCForRMW(AtomicOrdering Ordering,
+unsigned RISCVExpandPseudoAtomicsImpl::getSCForRMW(AtomicOrdering Ordering,
int Width) const {
if (Width == 32)
return getSCForRMW32(Ordering);
@@ -310,7 +309,7 @@ unsigned RISCVExpandAtomicPseudoImpl::getSCForRMW(AtomicOrdering Ordering,
llvm_unreachable("Unexpected SC width\n");
}
-void RISCVExpandAtomicPseudoImpl::doAtomicBinOpExpansion(
+void RISCVExpandPseudoAtomicsImpl::doAtomicBinOpExpansion(
MachineInstr &MI, MachineBasicBlock *LoopMBB, AtomicRMWInst::BinOp BinOp,
int Width) const {
DebugLoc DL = MI.getDebugLoc();
@@ -399,7 +398,7 @@ void RISCVExpandAtomicPseudoImpl::doAtomicBinOpExpansion(
.addMBB(LoopMBB);
}
-void RISCVExpandAtomicPseudoImpl::insertMaskedMerge(
+void RISCVExpandPseudoAtomicsImpl::insertMaskedMerge(
DebugLoc DL, MachineBasicBlock *MBB, Register DestReg, Register OldValReg,
Register NewValReg, Register MaskReg, Register ScratchReg) const {
assert(OldValReg != ScratchReg && "OldValReg and ScratchReg must be unique");
@@ -420,7 +419,7 @@ void RISCVExpandAtomicPseudoImpl::insertMaskedMerge(
.addReg(ScratchReg);
}
-void RISCVExpandAtomicPseudoImpl::doMaskedAtomicBinOpExpansion(
+void RISCVExpandPseudoAtomicsImpl::doMaskedAtomicBinOpExpansion(
MachineInstr &MI, MachineBasicBlock *LoopMBB, AtomicRMWInst::BinOp BinOp,
int Width) const {
DebugLoc DL = MI.getDebugLoc();
@@ -483,7 +482,7 @@ void RISCVExpandAtomicPseudoImpl::doMaskedAtomicBinOpExpansion(
.addMBB(LoopMBB);
}
-bool RISCVExpandAtomicPseudoImpl::expandAtomicBinOp(
+bool RISCVExpandPseudoAtomicsImpl::expandAtomicBinOp(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
MachineBasicBlock::iterator &NextMBBI) const {
@@ -518,7 +517,7 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicBinOp(
return true;
}
-void RISCVExpandAtomicPseudoImpl::insertSext(DebugLoc DL,
+void RISCVExpandPseudoAtomicsImpl::insertSext(DebugLoc DL,
MachineBasicBlock *MBB,
Register ValReg,
Register ShamtReg) const {
@@ -530,7 +529,7 @@ void RISCVExpandAtomicPseudoImpl::insertSext(DebugLoc DL,
.addReg(ShamtReg);
}
-void RISCVExpandAtomicPseudoImpl::doAtomicMinMaxOpExpansion(
+void RISCVExpandPseudoAtomicsImpl::doAtomicMinMaxOpExpansion(
MachineInstr &MI, MachineBasicBlock *LoopHeadMBB,
MachineBasicBlock *LoopIfBodyMBB, MachineBasicBlock *LoopTailMBB,
AtomicRMWInst::BinOp BinOp, int Width) const {
@@ -600,7 +599,7 @@ void RISCVExpandAtomicPseudoImpl::doAtomicMinMaxOpExpansion(
.addMBB(LoopHeadMBB);
}
-void RISCVExpandAtomicPseudoImpl::doMaskedAtomicMinMaxOpExpansion(
+void RISCVExpandPseudoAtomicsImpl::doMaskedAtomicMinMaxOpExpansion(
MachineInstr &MI, MachineBasicBlock *LoopHeadMBB,
MachineBasicBlock *LoopIfBodyMBB, MachineBasicBlock *LoopTailMBB,
AtomicRMWInst::BinOp BinOp, int Width) const {
@@ -684,7 +683,7 @@ void RISCVExpandAtomicPseudoImpl::doMaskedAtomicMinMaxOpExpansion(
.addMBB(LoopHeadMBB);
}
-bool RISCVExpandAtomicPseudoImpl::expandAtomicMinMaxOp(
+bool RISCVExpandPseudoAtomicsImpl::expandAtomicMinMaxOp(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
AtomicRMWInst::BinOp BinOp, bool IsMasked, int Width,
MachineBasicBlock::iterator &NextMBBI) const {
@@ -745,7 +744,7 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicMinMaxOp(
// On success, returns true and deletes the matching BNE or AND+BNE, sets the
// LoopHeadBNETarget argument to the target that should be used within the
// loop head, and removes that block as a successor to MBB.
-bool RISCVExpandAtomicPseudoImpl::tryToFoldBNEOnCmpXchgResult(
+bool RISCVExpandPseudoAtomicsImpl::tryToFoldBNEOnCmpXchgResult(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register DestReg,
Register CmpValReg, Register MaskReg,
MachineBasicBlock *&LoopHeadBNETarget) const {
@@ -799,7 +798,7 @@ bool RISCVExpandAtomicPseudoImpl::tryToFoldBNEOnCmpXchgResult(
return true;
}
-bool RISCVExpandAtomicPseudoImpl::expandAtomicCmpXchg(
+bool RISCVExpandPseudoAtomicsImpl::expandAtomicCmpXchg(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, bool IsMasked,
int Width, MachineBasicBlock::iterator &NextMBBI) const {
MachineInstr &MI = *MBBI;
@@ -901,19 +900,19 @@ bool RISCVExpandAtomicPseudoImpl::expandAtomicCmpXchg(
return true;
}
-char RISCVExpandAtomicPseudoLegacy::ID = 0;
+char RISCVExpandPseudoAtomicsLegacy::ID = 0;
-INITIALIZE_PASS(RISCVExpandAtomicPseudoLegacy, "riscv-expand-atomic-pseudo",
- RISCV_EXPAND_ATOMIC_PSEUDO_NAME, false, false)
+INITIALIZE_PASS(RISCVExpandPseudoAtomicsLegacy, "riscv-expand-pseudo-atomics",
+ RISCV_EXPAND_PSEUDO_ATOMICS_NAME, false, false)
-FunctionPass *llvm::createRISCVExpandAtomicPseudoLegacyPass() {
- return new RISCVExpandAtomicPseudoLegacy();
+FunctionPass *llvm::createRISCVExpandPseudoAtomicsLegacyPass() {
+ return new RISCVExpandPseudoAtomicsLegacy();
}
PreservedAnalyses
-RISCVExpandAtomicPseudoPass::run(MachineFunction &MF,
+RISCVExpandPseudoAtomicsPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
- bool Changed = RISCVExpandAtomicPseudoImpl().run(MF);
+ bool Changed = RISCVExpandPseudoAtomicsImpl().run(MF);
if (!Changed)
return PreservedAnalyses::all();
return getMachineFunctionPassPreservedAnalyses();
diff --git a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
similarity index 86%
rename from llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
rename to llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
index f3ade17e4fdb9..c833c1c7ee3c2 100644
--- a/llvm/lib/Target/RISCV/RISCVPostRAExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
@@ -1,4 +1,4 @@
-//===-- RISCVPostRAExpandPseudoInsts.cpp - Expand pseudo instrs ----===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -21,12 +21,12 @@
using namespace llvm;
-#define RISCV_POST_RA_EXPAND_PSEUDO_NAME \
- "RISC-V post-regalloc pseudo instruction expansion pass"
+#define RISCV_EXPAND_PSEUDO_POST_RA_NAME \
+ "RISC-V Pseudo Instruction Expansion - Post-RA"
namespace {
-class RISCVPostRAExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
+class RISCVExpandPseudoPostRAImpl final : public RISCVExpandPseudoImplBase {
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const override;
@@ -43,14 +43,14 @@ class RISCVPostRAExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
MachineBasicBlock::iterator MBBI) const;
};
-class RISCVPostRAExpandPseudoLegacy : public MachineFunctionPass {
+class RISCVExpandPseudoPostRALegacy : public MachineFunctionPass {
public:
static char ID;
- RISCVPostRAExpandPseudoLegacy() : MachineFunctionPass(ID) {}
+ RISCVExpandPseudoPostRALegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override {
- return RISCVPostRAExpandPseudoImpl().run(MF);
+ return RISCVExpandPseudoPostRAImpl().run(MF);
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
@@ -59,13 +59,13 @@ class RISCVPostRAExpandPseudoLegacy : public MachineFunctionPass {
}
StringRef getPassName() const override {
- return RISCV_POST_RA_EXPAND_PSEUDO_NAME;
+ return RISCV_EXPAND_PSEUDO_POST_RA_NAME;
}
};
} // anonymous namespace
-bool RISCVPostRAExpandPseudoImpl::expandMI(
+bool RISCVExpandPseudoPostRAImpl::expandMI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const {
switch (MBBI->getOpcode()) {
@@ -82,7 +82,7 @@ bool RISCVPostRAExpandPseudoImpl::expandMI(
return false;
}
-bool RISCVPostRAExpandPseudoImpl::expandMovImm(
+bool RISCVExpandPseudoPostRAImpl::expandMovImm(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
@@ -99,7 +99,7 @@ bool RISCVPostRAExpandPseudoImpl::expandMovImm(
return true;
}
-bool RISCVPostRAExpandPseudoImpl::expandMovAddr(
+bool RISCVExpandPseudoPostRAImpl::expandMovAddr(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
@@ -119,7 +119,7 @@ bool RISCVPostRAExpandPseudoImpl::expandMovAddr(
return true;
}
-bool RISCVPostRAExpandPseudoImpl::expandAddUpperImm(
+bool RISCVExpandPseudoPostRAImpl::expandAddUpperImm(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
@@ -155,7 +155,7 @@ static void transferImpOps(const MachineInstr &OldMI, MachineInstrBuilder &MI) {
}
// Expand PseudoMERGE to MERGE, MVM, or MVMN.
-bool RISCVPostRAExpandPseudoImpl::expandMERGE(
+bool RISCVExpandPseudoPostRAImpl::expandMERGE(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
@@ -210,19 +210,19 @@ bool RISCVPostRAExpandPseudoImpl::expandMERGE(
return true;
}
-char RISCVPostRAExpandPseudoLegacy::ID = 0;
+char RISCVExpandPseudoPostRALegacy::ID = 0;
-INITIALIZE_PASS(RISCVPostRAExpandPseudoLegacy, "riscv-post-ra-expand-pseudo",
- RISCV_POST_RA_EXPAND_PSEUDO_NAME, false, false)
+INITIALIZE_PASS(RISCVExpandPseudoPostRALegacy, "riscv-expand-pseudo-post-ra",
+ RISCV_EXPAND_PSEUDO_POST_RA_NAME, false, false)
-FunctionPass *llvm::createRISCVPostRAExpandPseudoLegacyPass() {
- return new RISCVPostRAExpandPseudoLegacy();
+FunctionPass *llvm::createRISCVExpandPseudoPostRALegacyPass() {
+ return new RISCVExpandPseudoPostRALegacy();
}
PreservedAnalyses
-RISCVPostRAExpandPseudoPass::run(MachineFunction &MF,
+RISCVExpandPseudoPostRAPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
- bool Changed = RISCVPostRAExpandPseudoImpl().run(MF);
+ bool Changed = RISCVExpandPseudoPostRAImpl().run(MF);
if (!Changed)
return PreservedAnalyses::all();
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
similarity index 92%
rename from llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
rename to llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
index 1c6d12494e2aa..d3c4cce206977 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
@@ -1,4 +1,4 @@
-//===-- RISCVExpandPseudoInsts.cpp - Expand pseudo instructions -----------===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -22,11 +22,12 @@
using namespace llvm;
-#define RISCV_EXPAND_PSEUDO_NAME "RISC-V pseudo instruction expansion pass"
+#define RISCV_EXPAND_PSEUDO_PRE_EMIT_NAME \
+ "RISC-V Pseudo Instruction Expansion - Pre-Emit"
namespace {
-class RISCVExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
+class RISCVExpandPseudoPreEmitImpl final : public RISCVExpandPseudoImplBase {
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const override;
@@ -60,22 +61,24 @@ class RISCVExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
MachineBasicBlock::iterator MBBI) const;
};
-class RISCVExpandPseudoLegacy : public MachineFunctionPass {
+class RISCVExpandPseudoPreEmitLegacy : public MachineFunctionPass {
public:
static char ID;
- RISCVExpandPseudoLegacy() : MachineFunctionPass(ID) {}
+ RISCVExpandPseudoPreEmitLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override {
- return RISCVExpandPseudoImpl().run(MF);
+ return RISCVExpandPseudoPreEmitImpl().run(MF);
}
- StringRef getPassName() const override { return RISCV_EXPAND_PSEUDO_NAME; }
+ StringRef getPassName() const override {
+ return RISCV_EXPAND_PSEUDO_PRE_EMIT_NAME;
+ }
};
} // anonymous namespace
-bool RISCVExpandPseudoImpl::expandMI(
+bool RISCVExpandPseudoPreEmitImpl::expandMI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const {
// RISCVInstrInfo::getInstSizeInBytes expects that the total size of the
@@ -169,7 +172,7 @@ bool RISCVExpandPseudoImpl::expandMI(
return false;
}
-bool RISCVExpandPseudoImpl::expandCCOp(
+bool RISCVExpandPseudoPreEmitImpl::expandCCOp(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const {
// First try expanding to a Conditional Move rather than a branch+mv
@@ -298,7 +301,7 @@ bool RISCVExpandPseudoImpl::expandCCOp(
return true;
}
-bool RISCVExpandPseudoImpl::expandCCOpToCMov(
+bool RISCVExpandPseudoPreEmitImpl::expandCCOpToCMov(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
MachineInstr &MI = *MBBI;
DebugLoc DL = MI.getDebugLoc();
@@ -425,9 +428,9 @@ bool RISCVExpandPseudoImpl::expandCCOpToCMov(
return true;
}
-bool RISCVExpandPseudoImpl::expandVMSET_VMCLR(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned Opcode) const {
+bool RISCVExpandPseudoPreEmitImpl::expandVMSET_VMCLR(
+ MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+ unsigned Opcode) const {
DebugLoc DL = MBBI->getDebugLoc();
Register DstReg = MBBI->getOperand(0).getReg();
const MCInstrDesc &Desc = TII->get(Opcode);
@@ -438,7 +441,7 @@ bool RISCVExpandPseudoImpl::expandVMSET_VMCLR(MachineBasicBlock &MBB,
return true;
}
-bool RISCVExpandPseudoImpl::expandMV_FPR16INX(
+bool RISCVExpandPseudoPreEmitImpl::expandMV_FPR16INX(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
@@ -455,7 +458,7 @@ bool RISCVExpandPseudoImpl::expandMV_FPR16INX(
return true;
}
-bool RISCVExpandPseudoImpl::expandMV_FPR32INX(
+bool RISCVExpandPseudoPreEmitImpl::expandMV_FPR32INX(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
@@ -475,7 +478,7 @@ bool RISCVExpandPseudoImpl::expandMV_FPR32INX(
// This function expands the PseudoRV32ZdinxSD for storing a double-precision
// floating-point value into memory by generating an equivalent instruction
// sequence for RV32.
-bool RISCVExpandPseudoImpl::expandRV32ZdinxStore(
+bool RISCVExpandPseudoPreEmitImpl::expandRV32ZdinxStore(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
@@ -524,7 +527,7 @@ bool RISCVExpandPseudoImpl::expandRV32ZdinxStore(
// This function expands PseudoRV32ZdinxLoad for loading a double-precision
// floating-point value from memory into an equivalent instruction sequence for
// RV32.
-bool RISCVExpandPseudoImpl::expandRV32ZdinxLoad(
+bool RISCVExpandPseudoPreEmitImpl::expandRV32ZdinxLoad(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
const TargetRegisterInfo *TRI = STI->getRegisterInfo();
@@ -582,7 +585,7 @@ bool RISCVExpandPseudoImpl::expandRV32ZdinxLoad(
return true;
}
-bool RISCVExpandPseudoImpl::expandPseudoReadVLENBViaVSETVLIX0(
+bool RISCVExpandPseudoPreEmitImpl::expandPseudoReadVLENBViaVSETVLIX0(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
DebugLoc DL = MBBI->getDebugLoc();
Register Dst = MBBI->getOperand(0).getReg();
@@ -600,7 +603,7 @@ bool RISCVExpandPseudoImpl::expandPseudoReadVLENBViaVSETVLIX0(
return true;
}
-bool RISCVExpandPseudoImpl::expandPseudoClearFPR64(
+bool RISCVExpandPseudoPreEmitImpl::expandPseudoClearFPR64(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
const DebugLoc &DL = MBBI->getDebugLoc();
Register Dst = MBBI->getOperand(0).getReg();
@@ -617,19 +620,19 @@ bool RISCVExpandPseudoImpl::expandPseudoClearFPR64(
return true;
}
-char RISCVExpandPseudoLegacy::ID = 0;
+char RISCVExpandPseudoPreEmitLegacy::ID = 0;
-INITIALIZE_PASS(RISCVExpandPseudoLegacy, "riscv-expand-pseudo",
- RISCV_EXPAND_PSEUDO_NAME, false, false)
+INITIALIZE_PASS(RISCVExpandPseudoPreEmitLegacy, "riscv-expand-pseudo-pre-emit",
+ RISCV_EXPAND_PSEUDO_PRE_EMIT_NAME, false, false)
-FunctionPass *llvm::createRISCVExpandPseudoLegacyPass() {
- return new RISCVExpandPseudoLegacy();
+FunctionPass *llvm::createRISCVExpandPseudoPreEmitLegacyPass() {
+ return new RISCVExpandPseudoPreEmitLegacy();
}
PreservedAnalyses
-RISCVExpandPseudoPass::run(MachineFunction &MF,
- MachineFunctionAnalysisManager &MFAM) {
- bool Changed = RISCVExpandPseudoImpl().run(MF);
+RISCVExpandPseudoPreEmitPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ bool Changed = RISCVExpandPseudoPreEmitImpl().run(MF);
if (!Changed)
return PreservedAnalyses::all();
return getMachineFunctionPassPreservedAnalyses();
diff --git a/llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoPreRA.cpp
similarity index 84%
rename from llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp
rename to llvm/lib/Target/RISCV/RISCVExpandPseudoPreRA.cpp
index e6da34192b8ca..46eb63dff68f6 100644
--- a/llvm/lib/Target/RISCV/RISCVPreRAExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoPreRA.cpp
@@ -21,12 +21,11 @@
using namespace llvm;
-#define RISCV_PRERA_EXPAND_PSEUDO_NAME \
- "RISC-V Pre-RA pseudo instruction expansion pass"
+#define RISCV_EXPAND_PSEUDO_PRE_RA_NAME "RISC-V Pseudo Instruction Expansion - Pre-RA"
namespace {
-class RISCVPreRAExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
+class RISCVExpandPseudoPreRAImpl final : public RISCVExpandPseudoImplBase {
bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const override;
@@ -50,14 +49,14 @@ class RISCVPreRAExpandPseudoImpl final : public RISCVExpandPseudoImplBase {
MachineBasicBlock::iterator MBBI) const;
};
-class RISCVPreRAExpandPseudoLegacy : public MachineFunctionPass {
+class RISCVExpandPseudoPreRALegacy : public MachineFunctionPass {
public:
static char ID;
- RISCVPreRAExpandPseudoLegacy() : MachineFunctionPass(ID) {}
+ RISCVExpandPseudoPreRALegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override {
- return RISCVPreRAExpandPseudoImpl().run(MF);
+ return RISCVExpandPseudoPreRAImpl().run(MF);
}
MachineFunctionProperties getRequiredProperties() const override {
@@ -69,13 +68,13 @@ class RISCVPreRAExpandPseudoLegacy : public MachineFunctionPass {
MachineFunctionPass::getAnalysisUsage(AU);
}
StringRef getPassName() const override {
- return RISCV_PRERA_EXPAND_PSEUDO_NAME;
+ return RISCV_EXPAND_PSEUDO_PRE_RA_NAME;
}
};
} // anonymous namespace
-bool RISCVPreRAExpandPseudoImpl::expandMI(
+bool RISCVExpandPseudoPreRAImpl::expandMI(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
MachineBasicBlock::iterator &NextMBBI) const {
@@ -95,7 +94,7 @@ bool RISCVPreRAExpandPseudoImpl::expandMI(
return false;
}
-bool RISCVPreRAExpandPseudoImpl::expandAuipcInstPair(
+bool RISCVExpandPseudoPreRAImpl::expandAuipcInstPair(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned FlagsHi,
unsigned SecondOpcode) const {
MachineFunction *MF = MBB.getParent();
@@ -126,29 +125,29 @@ bool RISCVPreRAExpandPseudoImpl::expandAuipcInstPair(
return true;
}
-bool RISCVPreRAExpandPseudoImpl::expandLoadLocalAddress(
+bool RISCVExpandPseudoPreRAImpl::expandLoadLocalAddress(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
return expandAuipcInstPair(MBB, MBBI, RISCVII::MO_PCREL_HI, RISCV::ADDI);
}
-bool RISCVPreRAExpandPseudoImpl::expandLoadGlobalAddress(
+bool RISCVExpandPseudoPreRAImpl::expandLoadGlobalAddress(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
return expandAuipcInstPair(MBB, MBBI, RISCVII::MO_GOT_HI, SecondOpcode);
}
-bool RISCVPreRAExpandPseudoImpl::expandLoadTLSIEAddress(
+bool RISCVExpandPseudoPreRAImpl::expandLoadTLSIEAddress(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
return expandAuipcInstPair(MBB, MBBI, RISCVII::MO_TLS_GOT_HI, SecondOpcode);
}
-bool RISCVPreRAExpandPseudoImpl::expandLoadTLSGDAddress(
+bool RISCVExpandPseudoPreRAImpl::expandLoadTLSGDAddress(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
return expandAuipcInstPair(MBB, MBBI, RISCVII::MO_TLS_GD_HI, RISCV::ADDI);
}
-bool RISCVPreRAExpandPseudoImpl::expandLoadTLSDescAddress(
+bool RISCVExpandPseudoPreRAImpl::expandLoadTLSDescAddress(
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
MachineFunction *MF = MBB.getParent();
MachineInstr &MI = *MBBI;
@@ -192,20 +191,20 @@ bool RISCVPreRAExpandPseudoImpl::expandLoadTLSDescAddress(
return true;
}
-char RISCVPreRAExpandPseudoLegacy::ID = 0;
+char RISCVExpandPseudoPreRALegacy::ID = 0;
-INITIALIZE_PASS(RISCVPreRAExpandPseudoLegacy, "riscv-pre-ra-expand-pseudo",
- RISCV_PRERA_EXPAND_PSEUDO_NAME, false, false)
+INITIALIZE_PASS(RISCVExpandPseudoPreRALegacy, "riscv-expand-pseudo-pre-ra",
+ RISCV_EXPAND_PSEUDO_PRE_RA_NAME, false, false)
-FunctionPass *llvm::createRISCVPreRAExpandPseudoLegacyPass() {
- return new RISCVPreRAExpandPseudoLegacy();
+FunctionPass *llvm::createRISCVExpandPseudoPreRALegacyPass() {
+ return new RISCVExpandPseudoPreRALegacy();
}
PreservedAnalyses
-RISCVPreRAExpandPseudoPass::run(MachineFunction &MF,
+RISCVExpandPseudoPreRAPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
MFPropsModifier _(*this, MF);
- bool Changed = RISCVPreRAExpandPseudoImpl().run(MF);
+ bool Changed = RISCVExpandPseudoPreRAImpl().run(MF);
if (!Changed)
return PreservedAnalyses::all();
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index 64005fe762d90..f2e9d14701ebc 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -33,16 +33,17 @@ FUNCTION_PASS("riscv-zacas-abi-fix", RISCVZacasABIFixPass(this))
#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS)
#endif
MACHINE_FUNCTION_PASS("riscv-asm-printer", RISCVAsmPrinterPass())
-MACHINE_FUNCTION_PASS("riscv-expand-atomic-pseudo",
- RISCVExpandAtomicPseudoPass())
-MACHINE_FUNCTION_PASS("riscv-expand-pseudo", RISCVExpandPseudoPass())
+MACHINE_FUNCTION_PASS("riscv-expand-pseudo-atomics",
+ RISCVExpandPseudoAtomicsPass())
+MACHINE_FUNCTION_PASS("riscv-expand-pseudo-post-ra",
+ RISCVExpandPseudoPostRAPass())
+MACHINE_FUNCTION_PASS("riscv-expand-pseudo-pre-emit",
+ RISCVExpandPseudoPreEmitPass())
+MACHINE_FUNCTION_PASS("riscv-expand-pseudo-pre-ra",
+ RISCVExpandPseudoPreRAPass())
MACHINE_FUNCTION_PASS("riscv-fold-mem-offset", RISCVFoldMemOffsetPass())
MACHINE_FUNCTION_PASS("riscv-isel", RISCVISelDAGToDAGPass(*this, getOptLevel()))
MACHINE_FUNCTION_PASS("riscv-opt-w-instrs", RISCVOptWInstrsPass())
-MACHINE_FUNCTION_PASS("riscv-post-ra-expand-pseudo",
- RISCVPostRAExpandPseudoPass())
-MACHINE_FUNCTION_PASS("riscv-pre-ra-expand-pseudo",
- RISCVPreRAExpandPseudoPass())
MACHINE_FUNCTION_PASS("riscv-vector-peephole", RISCVVectorPeepholePass())
MACHINE_FUNCTION_PASS("riscv-vl-optimizer", RISCVVLOptimizerPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 19898e99f882f..83fbc7006cd85 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -130,12 +130,12 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVGatherScatterLoweringLegacyPass(*PR);
initializeRISCVCodeGenPrepareLegacyPass(*PR);
initializeRISCVZacasABIFixLegacyPass(*PR);
- initializeRISCVPostRAExpandPseudoLegacyPass(*PR);
+ initializeRISCVExpandPseudoPostRALegacyPass(*PR);
initializeRISCVMergeBaseOffsetOptPass(*PR);
initializeRISCVOptWInstrsLegacyPass(*PR);
initializeRISCVFoldMemOffsetLegacyPass(*PR);
- initializeRISCVPreRAExpandPseudoLegacyPass(*PR);
- initializeRISCVExpandPseudoLegacyPass(*PR);
+ initializeRISCVExpandPseudoPreRALegacyPass(*PR);
+ initializeRISCVExpandPseudoPreEmitLegacyPass(*PR);
initializeRISCVVectorPeepholeLegacyPass(*PR);
initializeRISCVVLOptimizerLegacyPass(*PR);
initializeRISCVVMV0EliminationPass(*PR);
@@ -148,7 +148,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVIndirectBranchTrackingPass(*PR);
initializeRISCVLoadStoreOptPass(*PR);
initializeRISCVPreAllocZilsdOptPass(*PR);
- initializeRISCVExpandAtomicPseudoLegacyPass(*PR);
+ initializeRISCVExpandPseudoAtomicsLegacyPass(*PR);
initializeRISCVRedundantCopyEliminationPass(*PR);
initializeRISCVAsmPrinterPass(*PR);
initializeRISCVPromoteConstantPass(*PR);
@@ -555,7 +555,7 @@ bool RISCVPassConfig::addGlobalInstructionSelect() {
}
void RISCVPassConfig::addPreSched2() {
- addPass(createRISCVPostRAExpandPseudoLegacyPass());
+ addPass(createRISCVExpandPseudoPostRALegacyPass());
// Emit KCFI checks for indirect calls.
addPass(createKCFIPass());
@@ -589,7 +589,7 @@ void RISCVPassConfig::addPreEmitPass2() {
// ensuring return instruction is detected correctly.
addPass(createRISCVPushPopOptimizationPass());
}
- addPass(createRISCVExpandPseudoLegacyPass());
+ addPass(createRISCVExpandPseudoPreEmitLegacyPass());
// Add QC Relaxation Markers as late as possible, and only for RV32
if (TM->getOptLevel() != CodeGenOptLevel::None &&
@@ -599,7 +599,7 @@ void RISCVPassConfig::addPreEmitPass2() {
// Schedule the expansion of AMOs at the last possible moment, avoiding the
// possibility for other passes to break the requirements for forward
// progress in the LR/SC block.
- addPass(createRISCVExpandAtomicPseudoLegacyPass());
+ addPass(createRISCVExpandPseudoAtomicsLegacyPass());
// KCFI indirect call checks are lowered to a bundle.
addPass(createUnpackMachineBundlesLegacy([&](const MachineFunction &MF) {
@@ -635,7 +635,7 @@ void RISCVPassConfig::addMachineSSAOptimization() {
}
void RISCVPassConfig::addPreRegAlloc() {
- addPass(createRISCVPreRAExpandPseudoLegacyPass());
+ addPass(createRISCVExpandPseudoPreRALegacyPass());
if (TM->getOptLevel() != CodeGenOptLevel::None) {
addPass(createRISCVMergeBaseOffsetOptPass());
// Add Zilsd pre-allocation load/store optimization
diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
index 847a8bd96c6d6..95175e013a4b8 100644
--- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll
@@ -40,7 +40,7 @@
; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Local Stack Slot Allocation
-; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Pseudo Instruction Expansion - Pre-RA
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
; CHECK-NEXT: RISC-V Insert Write VXRM Pass
; CHECK-NEXT: RISC-V Landing Pad Setup
@@ -57,7 +57,7 @@
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
; CHECK-NEXT: Post-RA pseudo instruction expansion pass
-; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Pseudo Instruction Expansion - Post-RA
; CHECK-NEXT: Insert KCFI indirect call checks
; CHECK-NEXT: Analyze Machine Code For Garbage Collection
; CHECK-NEXT: Insert fentry calls
@@ -75,8 +75,8 @@
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Stack Frame Layout Analysis
-; CHECK-NEXT: RISC-V pseudo instruction expansion pass
-; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Pseudo Instruction Expansion - Pre-Emit
+; CHECK-NEXT: RISC-V Pseudo Instruction Expansion - Atomics
; CHECK-NEXT: Unpack machine instruction bundles
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
diff --git a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
index 7262f52086129..79dedf6e85751 100644
--- a/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O1-newpm-pipeline.ll
@@ -60,7 +60,7 @@
; CHECK-NEXT: peephole-opt
; CHECK-NEXT: dead-mi-elimination
; RV64-NEXT: riscv-opt-w-instrs
-; CHECK-NEXT: riscv-pre-ra-expand-pseudo
+; CHECK-NEXT: riscv-expand-pseudo-pre-ra
; CHECK-NEXT: detect-dead-lanes
; CHECK-NEXT: init-undef
; CHECK-NEXT: process-imp-defs
@@ -87,7 +87,7 @@
; CHECK-NEXT: tailduplication
; CHECK-NEXT: machine-cp
; CHECK-NEXT: post-ra-pseudos
-; CHECK-NEXT: riscv-post-ra-expand-pseudo
+; CHECK-NEXT: riscv-expand-pseudo-post-ra
; CHECK-NEXT: kcfi
; CHECK-NEXT: post-RA-sched
; CHECK-NEXT: block-placement
@@ -104,8 +104,8 @@
; CHECK-NEXT: function
; CHECK-NEXT: machine-function
; CHECK-NEXT: stack-frame-layout
-; CHECK-NEXT: riscv-expand-pseudo
-; CHECK-NEXT: riscv-expand-atomic-pseudo
+; CHECK-NEXT: riscv-expand-pseudo-pre-emit
+; CHECK-NEXT: riscv-expand-pseudo-atomics
; CHECK-NEXT: unpack-mi-bundles
; CHECK-NEXT: verify
; CHECK-NEXT: riscv-asm-printer
diff --git a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
index 0765b1193f885..8b3e08a05be76 100644
--- a/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-newpm-pipeline.ll
@@ -60,7 +60,7 @@
; CHECK-NEXT: peephole-opt
; CHECK-NEXT: dead-mi-elimination
; RV64-NEXT: riscv-opt-w-instrs
-; CHECK-NEXT: riscv-pre-ra-expand-pseudo
+; CHECK-NEXT: riscv-expand-pseudo-pre-ra
; CHECK-NEXT: detect-dead-lanes
; CHECK-NEXT: init-undef
; CHECK-NEXT: process-imp-defs
@@ -87,7 +87,7 @@
; CHECK-NEXT: tailduplication
; CHECK-NEXT: machine-cp
; CHECK-NEXT: post-ra-pseudos
-; CHECK-NEXT: riscv-post-ra-expand-pseudo
+; CHECK-NEXT: riscv-expand-pseudo-post-ra
; CHECK-NEXT: kcfi
; CHECK-NEXT: post-RA-sched
; CHECK-NEXT: block-placement
@@ -105,8 +105,8 @@
; CHECK-NEXT: function
; CHECK-NEXT: machine-function
; CHECK-NEXT: stack-frame-layout
-; CHECK-NEXT: riscv-expand-pseudo
-; CHECK-NEXT: riscv-expand-atomic-pseudo
+; CHECK-NEXT: riscv-expand-pseudo-pre-emit
+; CHECK-NEXT: riscv-expand-pseudo-atomics
; CHECK-NEXT: unpack-mi-bundles
; CHECK-NEXT: verify
; CHECK-NEXT: riscv-asm-printer
diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
index 03ac475468b71..12a74cd16ddcc 100644
--- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll
+++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll
@@ -142,7 +142,7 @@
; CHECK-NEXT: Peephole Optimizations
; CHECK-NEXT: Remove dead machine instructions
; RV64-NEXT: RISC-V Optimize W Instructions
-; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Pseudo Instruction Expansion - Pre-RA
; CHECK-NEXT: RISC-V Merge Base Offset
; CHECK-NEXT: MachineDominator Tree Construction
; CHECK-NEXT: RISC-V pre-allocation Zilsd load/store optimization
@@ -201,7 +201,7 @@
; CHECK-NEXT: Tail Duplication
; CHECK-NEXT: Machine Copy Propagation Pass
; CHECK-NEXT: Post-RA pseudo instruction expansion pass
-; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Pseudo Instruction Expansion - Post-RA
; CHECK-NEXT: Insert KCFI indirect call checks
; CHECK-NEXT: RISC-V Load / Store Optimizer
; CHECK-NEXT: MachineDominator Tree Construction
@@ -233,9 +233,9 @@
; CHECK-NEXT: Stack Frame Layout Analysis
; CHECK-NEXT: RISC-V Zcmp move merging pass
; CHECK-NEXT: RISC-V Zcmp Push/Pop optimization pass
-; CHECK-NEXT: RISC-V pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Pseudo Instruction Expansion - Pre-Emit
; RV32-NEXT: RISC-V QC Relaxation Marking
-; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
+; CHECK-NEXT: RISC-V Pseudo Instruction Expansion - Atomics
; CHECK-NEXT: Unpack machine instruction bundles
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
diff --git a/llvm/test/CodeGen/RISCV/expand-atomic-pseudo.mir b/llvm/test/CodeGen/RISCV/expand-atomic-pseudo.mir
index c6681ed842e09..c400cdaa7c8e9 100644
--- a/llvm/test/CodeGen/RISCV/expand-atomic-pseudo.mir
+++ b/llvm/test/CodeGen/RISCV/expand-atomic-pseudo.mir
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=riscv32 -mattr=+a -run-pass=riscv-expand-atomic-pseudo \
+# RUN: llc -mtriple=riscv32 -mattr=+a -run-pass=riscv-expand-pseudo-atomics \
# RUN: %s -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+a -run-pass=riscv-expand-atomic-pseudo \
+# RUN: llc -mtriple=riscv64 -mattr=+a -run-pass=riscv-expand-pseudo-atomics \
# RUN: %s -o - | FileCheck %s
-# RUN: llc -mtriple=riscv32 -mattr=+a -passes=riscv-expand-atomic-pseudo \
+# RUN: llc -mtriple=riscv32 -mattr=+a -passes=riscv-expand-pseudo-atomics \
# RUN: %s -o - | FileCheck %s
-# RUN: llc -mtriple=riscv64 -mattr=+a -passes=riscv-expand-atomic-pseudo \
+# RUN: llc -mtriple=riscv64 -mattr=+a -passes=riscv-expand-pseudo-atomics \
# RUN: %s -o - | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/expand-pseudo.mir b/llvm/test/CodeGen/RISCV/expand-pseudo.mir
index 82c265224edd4..87f4a8cfe9f58 100644
--- a/llvm/test/CodeGen/RISCV/expand-pseudo.mir
+++ b/llvm/test/CodeGen/RISCV/expand-pseudo.mir
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=riscv-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+d -run-pass=riscv-expand-pseudo-pre-emit %s -o - \
# RUN: | FileCheck %s --check-prefixes=RV32
-# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=riscv-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+d -run-pass=riscv-expand-pseudo-pre-emit %s -o - \
# RUN: | FileCheck %s --check-prefixes=RV64
-# RUN: llc -mtriple=riscv32 -mattr=+d -passes=riscv-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv32 -mattr=+d -passes=riscv-expand-pseudo-pre-emit %s -o - \
# RUN: | FileCheck %s --check-prefixes=RV32
-# RUN: llc -mtriple=riscv64 -mattr=+d -passes=riscv-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv64 -mattr=+d -passes=riscv-expand-pseudo-pre-emit %s -o - \
# RUN: | FileCheck %s --check-prefixes=RV64
--- |
diff --git a/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir b/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
index ddc33162e12cb..8d4098b95e94e 100644
--- a/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
+++ b/llvm/test/CodeGen/RISCV/frame-base-addr-reuse.mir
@@ -5,7 +5,7 @@
# RUN: | FileCheck -check-prefix=RV64 %s
# RUN: llc -mtriple=riscv64 \
# RUN: -run-pass=prolog-epilog -run-pass=machine-latecleanup \
-# RUN: -run-pass=riscv-post-ra-expand-pseudo -o - %s \
+# RUN: -run-pass=riscv-expand-pseudo-post-ra -o - %s \
# RUN: | FileCheck -check-prefix=RV64-EXPAND %s
# RUN: llc -mtriple=riscv32 \
# RUN: -run-pass=prolog-epilog -run-pass=machine-latecleanup -o - %s \
diff --git a/llvm/test/CodeGen/RISCV/mir-target-flags.ll b/llvm/test/CodeGen/RISCV/mir-target-flags.ll
index d311f09a996ec..a0dc118a94a65 100644
--- a/llvm/test/CodeGen/RISCV/mir-target-flags.ll
+++ b/llvm/test/CodeGen/RISCV/mir-target-flags.ll
@@ -1,11 +1,11 @@
; RUN: llc -mtriple=riscv32 --code-model=small \
-; RUN: -stop-after riscv-pre-ra-expand-pseudo %s -o %t.mir
-; RUN: llc -mtriple=riscv32 -run-pass riscv-expand-pseudo %t.mir -o - | \
+; RUN: -stop-after riscv-expand-pseudo-pre-ra %s -o %t.mir
+; RUN: llc -mtriple=riscv32 -run-pass riscv-expand-pseudo-pre-emit %t.mir -o - | \
; RUN: FileCheck %s -check-prefix=RV32-SMALL
;
; RUN: llc -mtriple=riscv32 --code-model=medium --relocation-model=pic \
-; RUN: -stop-after riscv-pre-ra-expand-pseudo %s -o %t.mir
-; RUN: llc -mtriple=riscv32 -run-pass riscv-expand-pseudo %t.mir -o - | \
+; RUN: -stop-after riscv-expand-pseudo-pre-ra %s -o %t.mir
+; RUN: llc -mtriple=riscv32 -run-pass riscv-expand-pseudo-pre-emit %t.mir -o - | \
; RUN: FileCheck %s -check-prefix=RV32-MED
; This tests the RISC-V-specific serialization and deserialization of
diff --git a/llvm/test/CodeGen/RISCV/postra-expand-pseudo.mir b/llvm/test/CodeGen/RISCV/postra-expand-pseudo.mir
index 07905a3214fcd..76d8e87699952 100644
--- a/llvm/test/CodeGen/RISCV/postra-expand-pseudo.mir
+++ b/llvm/test/CodeGen/RISCV/postra-expand-pseudo.mir
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=riscv32 -run-pass=riscv-post-ra-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=riscv-expand-pseudo-post-ra %s -o - \
# RUN: | FileCheck %s
-# RUN: llc -mtriple=riscv64 -run-pass=riscv-post-ra-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=riscv-expand-pseudo-post-ra %s -o - \
# RUN: | FileCheck %s
-# RUN: llc -mtriple=riscv32 -passes=riscv-post-ra-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv32 -passes=riscv-expand-pseudo-post-ra %s -o - \
# RUN: | FileCheck %s
-# RUN: llc -mtriple=riscv64 -passes=riscv-post-ra-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv64 -passes=riscv-expand-pseudo-post-ra %s -o - \
# RUN: | FileCheck %s
--- |
diff --git a/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir b/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir
index dc239a41373a4..f352d4cf3c89c 100644
--- a/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir
+++ b/llvm/test/CodeGen/RISCV/prera-expand-pseudo.mir
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=riscv32 -run-pass=riscv-pre-ra-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv32 -run-pass=riscv-expand-pseudo-pre-ra %s -o - \
# RUN: | FileCheck %s --check-prefixes=RV32
-# RUN: llc -mtriple=riscv64 -run-pass=riscv-pre-ra-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv64 -run-pass=riscv-expand-pseudo-pre-ra %s -o - \
# RUN: | FileCheck %s --check-prefixes=RV64
-# RUN: llc -mtriple=riscv32 -passes=riscv-pre-ra-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv32 -passes=riscv-expand-pseudo-pre-ra %s -o - \
# RUN: | FileCheck %s --check-prefixes=RV32
-# RUN: llc -mtriple=riscv64 -passes=riscv-pre-ra-expand-pseudo %s -o - \
+# RUN: llc -mtriple=riscv64 -passes=riscv-expand-pseudo-pre-ra %s -o - \
# RUN: | FileCheck %s --check-prefixes=RV64
--- |
diff --git a/llvm/test/CodeGen/RISCV/rvv/aliases.mir b/llvm/test/CodeGen/RISCV/rvv/aliases.mir
index f39b0c73d0943..a997a4383bc1f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/aliases.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/aliases.mir
@@ -1,5 +1,5 @@
-# RUN: llc -mtriple riscv32 -mattr=+v -start-after riscv-expand-pseudo -o - %s | FileCheck %s
-# RUN: llc -mtriple riscv64 -mattr=+v -start-after riscv-expand-pseudo -o - %s | FileCheck %s
+# RUN: llc -mtriple riscv32 -mattr=+v -start-after riscv-expand-pseudo-pre-emit -o - %s | FileCheck %s
+# RUN: llc -mtriple riscv64 -mattr=+v -start-after riscv-expand-pseudo-pre-emit -o - %s | FileCheck %s
--- |
define void @vnot_mask_1() {
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index 326a66f536f91..8dbfc4268513a 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -748,7 +748,7 @@ class ExegesisRISCVTarget : public ExegesisTarget {
PM.add(exegesis::createRISCVPostprocessingPass());
// PseudoRET will be expanded by RISCVAsmPrinter; we have to expand
// PseudoMovImm with RISCVPostRAExpandPseudoPass though.
- PM.add(createRISCVPostRAExpandPseudoLegacyPass());
+ PM.add(createRISCVExpandPseudoPostRALegacyPass());
}
};
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