[llvm] [RISCV] Align Expand Pseudo Pass Names (PR #218277)

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git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/Target/RISCV/RISCV.h llvm/lib/Target/RISCV/RISCVCodeGenPassBuilder.cpp llvm/lib/Target/RISCV/RISCVTargetMachine.cpp llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp llvm/lib/Target/RISCV/RISCVExpandPseudoPreRA.cpp --diff_from_common_commit
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diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp
index bb62f607c..856be7d03 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoAtomics.cpp
@@ -23,7 +23,8 @@
 
 using namespace llvm;
 
-#define RISCV_EXPAND_PSEUDO_ATOMICS_NAME "RISC-V Pseudo Instruction Expansion - Atomics"
+#define RISCV_EXPAND_PSEUDO_ATOMICS_NAME                                       \
+  "RISC-V Pseudo Instruction Expansion - Atomics"
 
 namespace {
 
@@ -292,7 +293,7 @@ RISCVExpandPseudoAtomicsImpl::getSCForRMW64(AtomicOrdering Ordering) const {
 }
 
 unsigned RISCVExpandPseudoAtomicsImpl::getLRForRMW(AtomicOrdering Ordering,
-                                                  int Width) const {
+                                                   int Width) const {
   if (Width == 32)
     return getLRForRMW32(Ordering);
   if (Width == 64)
@@ -301,7 +302,7 @@ unsigned RISCVExpandPseudoAtomicsImpl::getLRForRMW(AtomicOrdering Ordering,
 }
 
 unsigned RISCVExpandPseudoAtomicsImpl::getSCForRMW(AtomicOrdering Ordering,
-                                                  int Width) const {
+                                                   int Width) const {
   if (Width == 32)
     return getSCForRMW32(Ordering);
   if (Width == 64)
@@ -518,9 +519,9 @@ bool RISCVExpandPseudoAtomicsImpl::expandAtomicBinOp(
 }
 
 void RISCVExpandPseudoAtomicsImpl::insertSext(DebugLoc DL,
-                                             MachineBasicBlock *MBB,
-                                             Register ValReg,
-                                             Register ShamtReg) const {
+                                              MachineBasicBlock *MBB,
+                                              Register ValReg,
+                                              Register ShamtReg) const {
   BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg)
       .addReg(ValReg)
       .addReg(ShamtReg);
@@ -911,7 +912,7 @@ FunctionPass *llvm::createRISCVExpandPseudoAtomicsLegacyPass() {
 
 PreservedAnalyses
 RISCVExpandPseudoAtomicsPass::run(MachineFunction &MF,
-                                 MachineFunctionAnalysisManager &MFAM) {
+                                  MachineFunctionAnalysisManager &MFAM) {
   bool Changed = RISCVExpandPseudoAtomicsImpl().run(MF);
   if (!Changed)
     return PreservedAnalyses::all();
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoPreRA.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoPreRA.cpp
index 46eb63dff..4eb3d26be 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoPreRA.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoPreRA.cpp
@@ -21,7 +21,8 @@
 
 using namespace llvm;
 
-#define RISCV_EXPAND_PSEUDO_PRE_RA_NAME "RISC-V Pseudo Instruction Expansion - Pre-RA"
+#define RISCV_EXPAND_PSEUDO_PRE_RA_NAME                                        \
+  "RISC-V Pseudo Instruction Expansion - Pre-RA"
 
 namespace {
 

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https://github.com/llvm/llvm-project/pull/218277