[llvm] [X86] Avoid shl->mul lowbit-isolate fold on znver5/znver6 when unprofitable (PR #217776)

[PJ Dailey via llvm-commits]

PjDailey11 wrote:

The #214517 fold happens in InstCombine, which is target-independent, so it
applies the same way to every architecture. My fix is in X86's SelectionDAG
combiner, which is separate backend-specific code from AArch64's combiner.
AArch64 would need the same fix written in its own backend files, I just
haven't done that yet, which is what I meant when I said a later "follow-up."
Not really a RISC/microcode thing, more that the x86 and AArch64 fixes are
separate code that has to be written separately.

Does that make sense? 

https://github.com/llvm/llvm-project/pull/217776