[llvm] [X86] Avoid shl->mul lowbit-isolate fold on znver5/znver6 when unprofitable (PR #217776)

[PJ Dailey via llvm-commits]

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@@ -50792,6 +50792,44 @@ static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
   if (SDValue V = combineMulToPMADD52(N, DL, DAG, Subtarget))
     return V;
 
+  // #214517 folds shl X, cttz(Y) into mul(and(neg(Y), Y), X), which is
+  // usually profitable but is worse on some subtargets: on znver5 the mul
+  // form lowers to blsi+imul while the shl form lowers to tzcnt+shlx,
+  // which has better latency/throughput despite matching instruction count
+  // (https://github.com/llvm/llvm-project/issues/216550). Reverse the fold
+  // when the target prefers it. Only valid when Y is provably nonzero:
+  // cttz(Y) returns the bit width when Y == 0, and shl by an out-of-range
+  // amount is poison, while the mul form is well-defined (0) at Y == 0 -
+  // so the rewrite would be a miscompile for Y == 0 without that guard.
+  if (Subtarget.preferShlOverBlsiMul()) {
+    auto MatchLowBitIsolate = [](SDValue And) -> SDValue {
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PjDailey11 wrote:

Yes, that's actually probably more efficient 

https://github.com/llvm/llvm-project/pull/217776