[llvm] [X86] Avoid shl->mul lowbit-isolate fold on znver5/znver6 when unprofitable (PR #217776)

[via llvm-commits]

AZero13 wrote:

> 214517 folds shl X, cttz(Y) into mul(and(neg(Y), Y), X), which is usually profitable but regresses latency/throughput on znver5 (inherited by znver6): same instruction count, worse timing. Add a tuning flag and reverse the fold in DAG combine when the target prefers it and Y is provably nonzero.
> 
> Fixes #216550
> 
> x86 half only; AArch64 left for a follow-up
> 
> **AI Tool Use:** Claude Code was used to help draft DAG combine logic, test cases, and PR description under my direction and review

aarch64? isn't that a RISC that doesn't have microcode, so most instructions should be the same

https://github.com/llvm/llvm-project/pull/217776