[llvm] [GlobalISel][AArch64] Optimize shl, lshr, ashr (PR #213576)

[Yeongu Choe via llvm-commits]

YeonguChoe wrote:

> It's worth noting that there are multiple targets that would benefit from the same optimization: AMDGPU has #212097 open, and both X86 and MIPS also produce redundant ANDs. RISC-V implements the optimization in instruction selector in `RISCVInstructionSelector::selectShiftMask()`.

This one is about Target-dependent combiner code. It is not about Target-independent infrastructure.
Legalizer, Combiner, RegBank, Instruction Selection all are target dependent.

https://github.com/llvm/llvm-project/pull/213576