[llvm] [GlobalISel][AArch64] Optimize shl, lshr, ashr (PR #213576)

[Yeongu Choe via llvm-commits]

YeonguChoe wrote:

Okay.

I will explain how legalizer works. And if this doesn't convince you, I will do it in instruction selection as you say.
I think most people don't have time to analyze until it becomes fundamental element, so I hope this explanation gives overview.

The idea behind legalizer is that it is a [finite state machine](https://en.wikipedia.org/wiki/Finite-state_machine). It runs each step (e.g, `clampScalar`, `clampNumElements`, `minScalarSameAs`) one by one until it reaches conditions in `legalFor`. So if written in pseudocode, it will be as follows.

```python
while(!legalFor(<passing condition>)):
    clampScalar()
    clampNumElements()
    minScalarSameAs()
```

If I draw in a diagram:

<img width="350" alt="Screenshot From 2026-08-04 04-53-20" src="https://github.com/user-attachments/assets/67c33b8b-52f1-4dcb-8698-9fb3039f4a43" />

In theory, every register related work can be done in legalizer without help of combiners.

The internal structures of GlobalISel and SelectionDag are different. Not only this, there are many features that are different. So it is not correct to always follow as SelectionDAG.


https://github.com/llvm/llvm-project/pull/213576