[llvm] [GlobalISel][AArch64] Optimize shl, lshr, ashr (PR #213576)

[David Green via llvm-commits]

davemgreen wrote:

> The internal structures of GlobalISel and SelectionDAG are different. Not only this, there are many features that are different. So it is not correct to always follow as what SelectionDAG does.

Yeah - the question is what should be treated as a legal type in the legalization stage. The intent is for by the time we reach selection, the operations and types are usually close to what can be selected straight to the target instructions, which means i32 or i64 for GPR scalar instructions. There are instructions where we don't know the regbank (whether they will be treated as gpr instructions or executed on the fpr vector registers, like constants), and so allow smaller types but these are usually extended to i32 in RBS once we know they will be placed on GPR registers.

If i8 and i16 shifts are expected to be legal into selection then we need to be very careful about how we treat them to make sure the end result is correct. Another way to look at it is what should happen for an i7? We would add a mask to legalize and not end up removing it. It is expected at the moment for anything scalar and smaller than i32 to be legalized to an i32.

https://github.com/llvm/llvm-project/pull/213576