[llvm] [RISCV] Declare TLSDESC clobbers for vector registers and CSRs per psABI (PR #205027)

[Jessica Clarke via llvm-commits]

jrtc27 wrote:

It's still phrased quite confusingly (especially since where "only" is placed in a sentence, and with what emphasis, can completely change the meaning).

Currently it says:

> Per the RISC-V psABI, the TLSDESC resolver only clobbers a0 and t0 if V-extension is not presented. While when the V is enabled, it would additionally clobbers all the vector registers and vector CSRs, by the new ABI updates (https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/496).

I would suggest something like the following to fix that (fixing some other grammar whilst I'm at it):

> Per the RISC-V psABI, TLSDESC resolvers clobber only a0 and t0 if V is not present, while when V is present, it would additionally clobbers all the vector registers and vector CSRs, by the new ABI updates (https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/496).

Though I think the situation is more clearly explained as something more like:

> RISC-V's ABI states that, aside from V extension state, only a0 and t0
are clobbered by TLSDESC resolvers. The original specification was to
also not clobber any V extension state, but due to implementation
concerns an ABI-breaking change has been made[1] to clobber all V
extension state.
>
> [1] https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/496 

I don't think I would read your commit message and clearly realise that this is a specification change rather than an implementation bug.

Also, "per psABI" is unnecessary in the title; that would be the obvious assumption, with it being noteworthy only if *not* something required by the psABI.

https://github.com/llvm/llvm-project/pull/205027