[llvm] [RISCV] Declare TLSDESC clobbers for vector registers and CSRs per psABI (PR #205027)

via llvm-commits llvm-commits at lists.llvm.org
Sun Jul 19 10:20:57 PDT 2026

Previous message: [llvm] [LoopInterchange] Prevent the transformation stage from stopping partway (PR #205564)
Next message: [llvm] [RISCV] Declare TLSDESC clobbers for vector registers and CSRs per psABI (PR #205027)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

LukeZhuang wrote:

Gentle ping :) @jrtc27 
And just FYI, the corresponding GCC part is already checked-in: https://gcc.gnu.org/cgit/gcc/commit/?id=0748d2c83fc0440f101fe01cc3dfc97c8e11c3b2

https://github.com/llvm/llvm-project/pull/205027

Previous message: [llvm] [LoopInterchange] Prevent the transformation stage from stopping partway (PR #205564)
Next message: [llvm] [RISCV] Declare TLSDESC clobbers for vector registers and CSRs per psABI (PR #205027)
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list