[llvm] [RISCV][SMT] add x100 vector sched info (PR #210597)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 19 07:11:13 PDT 2026
https://github.com/LiqinWeng created https://github.com/llvm/llvm-project/pull/210597
None
>From 644f45911b4e0ffe627b40278595a8b62f59960a Mon Sep 17 00:00:00 2001
From: wengliqin <liqin.weng at spacemit.com>
Date: Mon, 13 Jul 2026 16:53:05 +0800
Subject: [PATCH] [RISCV][SMT] add x100 vector sched info
---
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 23 +-
.../Target/RISCV/RISCVInstrInfoVPseudos.td | 21 +-
llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td | 4 +-
llvm/lib/Target/RISCV/RISCVProcessors.td | 2 +-
llvm/lib/Target/RISCV/RISCVSchedAndes45.td | 9 +-
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 9 +-
llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td | 9 +-
llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td | 12 +-
llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td | 9 +-
.../Target/RISCV/RISCVSchedSpacemitX100.td | 1086 +++-
.../lib/Target/RISCV/RISCVSchedSpacemitX60.td | 9 +-
llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td | 9 +-
llvm/lib/Target/RISCV/RISCVScheduleV.td | 18 +-
.../RISCV/SpacemitX100/rvv/arithmetic.test | 4539 +++++++++++++++++
.../RISCV/SpacemitX100/rvv/bitwise.test | 2891 +++++++++++
.../RISCV/SpacemitX100/rvv/comparison.test | 1802 +++++++
.../RISCV/SpacemitX100/rvv/conversion.test | 1166 +++++
.../llvm-mca/RISCV/SpacemitX100/rvv/fma.test | 1454 ++++++
.../llvm-mca/RISCV/SpacemitX100/rvv/fp.test | 3719 ++++++++++++++
.../llvm-mca/RISCV/SpacemitX100/rvv/mask.test | 1246 +++++
.../RISCV/SpacemitX100/rvv/minmax.test | 746 +++
.../RISCV/SpacemitX100/rvv/mul-div.test | 1986 ++++++++
.../RISCV/SpacemitX100/rvv/permutation.test | 2330 +++++++++
.../RISCV/SpacemitX100/rvv/reduction.test | 1218 +++++
.../RISCV/SpacemitX100/rvv/vle-vse-vlm.test | 362 ++
.../RISCV/SpacemitX100/rvv/vlse-vsse.test | 218 +
.../RISCV/SpacemitX100/rvv/vlseg-vsseg.test | 3122 ++++++++++++
.../RISCV/SpacemitX100/rvv/vlxe-vsxe.test | 394 ++
28 files changed, 28357 insertions(+), 56 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/arithmetic.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/bitwise.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/comparison.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/conversion.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/fma.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/fp.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/mask.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/minmax.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/mul-div.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/permutation.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/reduction.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vle-vse-vlm.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlse-vsse.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlseg-vsseg.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlxe-vsxe.test
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index a60d11c8172b8..63bc4eecfbe37 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1052,23 +1052,24 @@ multiclass VNCLP_IV_V_X_I<string opcodestr, bits<6> funct6> {
}
multiclass VSLD_IV_X_I<string opcodestr, bits<6> funct6, bit slidesUp> {
- // Note: In the future, if VISlideI is also split into VSlideUpI and
- // VSlideDownI, it'll probably better to use two separate multiclasses.
defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");
+ defvar WriteSlideI = !if(slidesUp, "WriteVSlideUpI", "WriteVSlideDownI");
def X : VALUVX<funct6, OPIVX, opcodestr # ".vx">,
SchedBinaryMC<WriteSlideX, "ReadVISlideV", "ReadVISlideX">;
def I : VALUVI<funct6, opcodestr # ".vi", uimm5>,
- SchedUnaryMC<"WriteVSlideI", "ReadVISlideV">;
+ SchedUnaryMC<WriteSlideI, "ReadVISlideV">;
}
-multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6> {
+multiclass VSLD1_MV_X<string opcodestr, bits<6> funct6, bit slidesUp> {
+ defvar WriteSlide1X = !if(slidesUp, "WriteVISlide1Up", "WriteVISlide1Down");
def X : VALUVX<funct6, OPMVX, opcodestr # ".vx">,
- SchedBinaryMC<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX">;
+ SchedBinaryMC<WriteSlide1X, "ReadVISlideV", "ReadVISlideX">;
}
-multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6> {
+multiclass VSLD1_FV_F<string opcodestr, bits<6> funct6, bit slidesUp> {
+ defvar WriteSlide1F = !if(slidesUp, "WriteVFSlide1Up", "WriteVFSlide1Down");
def F : VALUVF<funct6, OPFVF, opcodestr # ".vf">,
- SchedBinaryMC<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF">;
+ SchedBinaryMC<WriteSlide1F, "ReadVFSlideV", "ReadVFSlideF">;
}
multiclass VGTR_IV_V_X_I<string opcodestr, bits<6> funct6> {
@@ -1765,21 +1766,21 @@ let Predicates = [HasVInstructions] in {
let Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp,
ElementsDependOn = EltDepsNone in {
defm VSLIDEUP_V : VSLD_IV_X_I<"vslideup", 0b001110, /*slidesUp=*/true>;
-defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110>;
+defm VSLIDE1UP_V : VSLD1_MV_X<"vslide1up", 0b001110, /*slidesUp=*/true>;
} // Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp, ElementsDependOn = EltDepsNone
let ElementsDependOn = EltDepsNone, ReadsPastVL = 1 in
defm VSLIDEDOWN_V : VSLD_IV_X_I<"vslidedown", 0b001111, /*slidesUp=*/false>;
let ElementsDependOn = EltDepsVL, ReadsPastVL = 1 in
-defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111>;
+defm VSLIDE1DOWN_V : VSLD1_MV_X<"vslide1down", 0b001111, /*slidesUp=*/false>;
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF] in {
let Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp,
ElementsDependOn = EltDepsNone in {
-defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110>;
+defm VFSLIDE1UP_V : VSLD1_FV_F<"vfslide1up", 0b001110, /*slidesUp=*/true>;
} // Constraints = "@earlyclobber $vd", VS1VS2Constraint = SlideUp
let ElementsDependOn = EltDepsVL, ReadsPastVL = 1 in
-defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111>;
+defm VFSLIDE1DOWN_V : VSLD1_FV_F<"vfslide1down", 0b001111, /*slidesUp=*/false>;
} // Predicates = [HasVInstructionsAnyF]
let Predicates = [HasVInstructions] in {
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 077b8f8058932..31fe0ef3bf5dc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -2222,10 +2222,11 @@ multiclass VPseudoBinaryV_VX_RM<LMULInfo m, string Constraint = ""> {
defm "_VX" : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, GPR, m, Constraint>;
}
-multiclass VPseudoVSLD1_VX<string Constraint = ""> {
+multiclass VPseudoVSLD1_VX<bit slidesUp = false, string Constraint = ""> {
+ defvar WriteSlide1X = !if(slidesUp, "WriteVISlide1Up", "WriteVISlide1Down");
foreach m = MxList in {
defm "_VX" : VPseudoBinary<m.vrclass, m.vrclass, GPR, m, Constraint>,
- SchedBinary<"WriteVISlide1X", "ReadVISlideV", "ReadVISlideX",
+ SchedBinary<WriteSlide1X, "ReadVISlideV", "ReadVISlideX",
m.MX, forcePassthruRead=true>;
}
}
@@ -2241,12 +2242,13 @@ multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, int sew> {
UsesVXRM=0>;
}
-multiclass VPseudoVSLD1_VF<string Constraint = ""> {
+multiclass VPseudoVSLD1_VF<bit slidesUp = false, string Constraint = ""> {
+ defvar WriteSlide1F = !if(slidesUp, "WriteVFSlide1Up", "WriteVFSlide1Down");
foreach f = FPList in {
foreach m = f.MxList in {
defm "_V" #f.FX
: VPseudoBinary<m.vrclass, m.vrclass, f.fprclass, m, Constraint>,
- SchedBinary<"WriteVFSlide1F", "ReadVFSlideV", "ReadVFSlideF", m.MX,
+ SchedBinary<WriteSlide1F, "ReadVFSlideV", "ReadVFSlideF", m.MX,
forcePassthruRead=true>;
}
}
@@ -3317,13 +3319,14 @@ multiclass VPseudoVMAC_VV_VF_AAXA_RM {
multiclass VPseudoVSLD_VX_VI<bit slidesUp = false, string Constraint = ""> {
defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");
+ defvar WriteSlideI = !if(slidesUp, "WriteVSlideUpI", "WriteVSlideDownI");
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoVSLDV_VX<m, Constraint>,
SchedTernary<WriteSlideX, "ReadVISlideV", "ReadVISlideV",
"ReadVISlideX", mx>;
defm "" : VPseudoVSLDV_VI<m, Constraint>,
- SchedBinary<"WriteVSlideI", "ReadVISlideV", "ReadVISlideV", mx>;
+ SchedBinary<WriteSlideI, "ReadVISlideV", "ReadVISlideV", mx>;
}
}
@@ -6746,13 +6749,13 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
let Predicates = [HasVInstructions] in {
defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI</*slidesUp=*/true, "@earlyclobber $rd">;
defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI</*slidesUp=*/false>;
- defm PseudoVSLIDE1UP : VPseudoVSLD1_VX<"@earlyclobber $rd">;
- defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX;
+ defm PseudoVSLIDE1UP : VPseudoVSLD1_VX</*slidesUp=*/true, "@earlyclobber $rd">;
+ defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX</*slidesUp=*/false>;
} // Predicates = [HasVInstructions]
let Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT in {
- defm PseudoVFSLIDE1UP : VPseudoVSLD1_VF<"@earlyclobber $rd">;
- defm PseudoVFSLIDE1DOWN : VPseudoVSLD1_VF;
+ defm PseudoVFSLIDE1UP : VPseudoVSLD1_VF</*slidesUp=*/true, "@earlyclobber $rd">;
+ defm PseudoVFSLIDE1DOWN : VPseudoVSLD1_VF</*slidesUp=*/false>;
} // Predicates = [HasVInstructionsAnyF], AltFmtType = IS_NOT_ALTFMT
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
index f6489c8a273fb..ccf4a85c80824 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
@@ -373,8 +373,8 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>;
}
-defm PseudoVFSLIDE1UP_ALT : VPseudoVSLD1_VF<"@earlyclobber $rd">;
-defm PseudoVFSLIDE1DOWN_ALT : VPseudoVSLD1_VF;
+defm PseudoVFSLIDE1UP_ALT : VPseudoVSLD1_VF</*slidesUp=*/true, "@earlyclobber $rd">;
+defm PseudoVFSLIDE1DOWN_ALT : VPseudoVSLD1_VF</*slidesUp=*/false>;
} // Predicates = [HasVInstructionsBF16], AltFmtType = IS_ALTFMT
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 6adbbe0af3782..e9704782f04da 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -853,7 +853,7 @@ def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
TuneShiftedZExtWFusion]>;
def SPACEMIT_A100 : RISCVProcessorModel<"spacemit-a100",
- SpacemitX60Model,
+ SpacemitX100Model,
!listconcat(
!listremove(RVA23S64Features,
[FeatureStdExtSha]),
diff --git a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
index 21663207cf792..867c1f2d24ad1 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedAndes45.td
@@ -1133,10 +1133,13 @@ foreach mx = SchedMxList in {
defvar IsWorstCase = Andes45IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [Andes45VPERMUT], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlide1X", [Andes45VPERMUT], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [Andes45VPERMUT], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [Andes45VPERMUT], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSlideUpX", [Andes45VPERMUT], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSlideDownX", [Andes45VPERMUT], mx, IsWorstCase>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index c2dcdaa5cd828..d163a9e73fe26 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -1141,9 +1141,12 @@ multiclass SiFive7WriteResBase<int VLEN,
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm : LMULWriteResMX<"WriteVSlideUpX", [VCQ, VA1], mx, IsWorstCase>;
defm : LMULWriteResMX<"WriteVSlideDownX", [VCQ, VA1], mx, IsWorstCase>;
- defm : LMULWriteResMX<"WriteVSlideI", [VCQ, VA1], mx, IsWorstCase>;
- defm : LMULWriteResMX<"WriteVISlide1X", [VCQ, VA1], mx, IsWorstCase>;
- defm : LMULWriteResMX<"WriteVFSlide1F", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVSlideUpI", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVSlideDownI", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVISlide1Up", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVISlide1Down", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVFSlide1Up", [VCQ, VA1], mx, IsWorstCase>;
+ defm : LMULWriteResMX<"WriteVFSlide1Down", [VCQ, VA1], mx, IsWorstCase>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
index 5b999c98fbc7c..1323e694dbe36 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
@@ -370,11 +370,14 @@ foreach mx = SchedMxList in {
defvar LMulLat = SiFive8VecGetLMulCycles<mx>.c;
defvar IsWorstCase = SiFive8VecIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SiFiveP400VEXQ0], mx, IsWorstCase>;
}
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP400VEXQ0], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SiFiveP400VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SiFiveP400VEXQ0], mx, IsWorstCase>;
}
}
foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
index db9b17f193a56..eef45b4a74fc8 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
@@ -981,12 +981,16 @@ foreach mx = SchedMxList in {
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
let ReleaseAtCycles = [LMulLat] in {
- let Latency = SiFiveP600VSlideI<mx>.c in
- defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ let Latency = SiFiveP600VSlideI<mx>.c in {
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ }
let Latency = SiFiveP600VSlide1<mx>.c in {
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP600VEXQ0], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SiFiveP600VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SiFiveP600VEXQ0], mx, IsWorstCase>;
}
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
index b0e1c7056c34d..bda3bc8f1c3c9 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFiveP800.td
@@ -698,11 +698,14 @@ foreach mx = SchedMxList in {
defvar LMulLat = SiFiveP800GetLMulCycles<mx>.c;
defvar IsWorstCase = SiFiveP800IsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SiFiveP800VEXQ0], mx, IsWorstCase>;
}
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SiFiveP800VEXQ0], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SiFiveP800VEXQ0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SiFiveP800VEXQ0], mx, IsWorstCase>;
}
}
foreach mx = ["MF8", "MF4", "MF2", "M1"] in {
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td
index 141fcb617ae7a..235c80a3c190e 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX100.td
@@ -11,6 +11,80 @@
// Scheduler model for the SpacemiT-X100 processor.
//
//===----------------------------------------------------------------------===//
+// Latency helper classes
+
+// Used for: arithmetic (min/max/vmerge/vmv),
+// saturating/averaging, FP add/sub/min/max
+class Get2348Latency<string mx> {
+ int c = GetLMULValue<[/*MF8=*/2, /*MF4=*/2, /*MF2=*/2, /*M1=*/2, /*M2=*/3, /*M4=*/4, /*M8=*/8], mx>.c;
+}
+
+//===----------------------------------------------------------------------===//
+
+class SMTX100IsWorstCaseMX<string mx, list<string> MxList> {
+ string LLMUL = LargestLMUL<MxList>.r;
+ bit c = !eq(mx, LLMUL);
+}
+
+class SMTX100IsWorstCaseMXSEW<string mx, int sew, list<string> MxList, bit isF = 0> {
+ string LLMUL = LargestLMUL<MxList>.r;
+ int SSEW = SmallestSEW<mx, isF>.r;
+ bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+defvar SMTX100VLEN = 256;
+defvar SMTX100DLEN = !div(SMTX100VLEN, 2);
+
+class SMTX100GetLMulCycles<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 1,
+ !eq(mx, "M2") : 2,
+ !eq(mx, "M4") : 4,
+ !eq(mx, "M8") : 8,
+ !eq(mx, "MF2") : 1,
+ !eq(mx, "MF4") : 1,
+ !eq(mx, "MF8") : 1
+ );
+}
+
+class SMTX100GetVLMAX<string mx, int sew> {
+ defvar LMUL = SMTX100GetLMulCycles<mx>.c;
+ int val = !cond(
+ !eq(mx, "MF2") : !div(!div(SMTX100VLEN, 2), sew),
+ !eq(mx, "MF4") : !div(!div(SMTX100VLEN, 4), sew),
+ !eq(mx, "MF8") : !div(!div(SMTX100VLEN, 8), sew),
+ true: !div(!mul(SMTX100VLEN, LMUL), sew)
+ );
+}
+
+// Latency for segmented loads and stores are calculated as vl * nf.
+class SMTX100SegmentedLdStCycles<string mx, int sew, int nf> {
+ int c = !mul(SMTX100GetVLMAX<mx, sew>.val, nf);
+}
+
+// Measured vlse latency: a single base curve indexed by LMUL, shifted right
+// by one slot per SEW doubling (since doubling SEW is equivalent to
+// dropping one LMUL step). Combinations below MF8 for a given SEW don't
+// exist and return a dummy 0.
+class SMTX100GetVLDSLat<string mx, int sew> {
+ defvar Base = [4, 5, 9, 22, 50, 114, 242];
+ defvar Index = !cond(
+ !eq(mx, "MF8"): 0,
+ !eq(mx, "MF4"): 1,
+ !eq(mx, "MF2"): 2,
+ !eq(mx, "M1"): 3,
+ !eq(mx, "M2"): 4,
+ !eq(mx, "M4"): 5,
+ !eq(mx, "M8"): 6,
+ );
+ defvar Shift = !cond(
+ !eq(sew, 8): 0,
+ !eq(sew, 16): 1,
+ !eq(sew, 32): 2,
+ !eq(sew, 64): 3,
+ );
+ int val = !if(!lt(Index, Shift), 0, Base[!sub(Index, Shift)]);
+}
def SpacemitX100Model : SchedMachineModel {
let IssueWidth = 4; // 4 micro-ops are dispatched per cycle.
@@ -22,8 +96,7 @@ def SpacemitX100Model : SchedMachineModel {
let CompleteModel = 0;
let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
- HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
- HasVInstructions];
+ HasStdExtZksed, HasStdExtZksh, HasStdExtZkr];
}
let SchedModel = SpacemitX100Model in {
@@ -51,6 +124,17 @@ let BufferSize = 4 in {
def SMTX100_IQ : ProcResGroup<[SMTX100_IQ0, SMTX100_IQ1]>;
def SMTX100_FQ : ProcResGroup<[SMTX100_FQ0, SMTX100_FQ1]>;
+// all vector computre inst in VEU0/VEU1
+def SMTX100_VEU0 : ProcResource<1>;
+def SMTX100_VEU1 : ProcResource<1>;
+// all vector memory inst in VEU2/VEU3
+def SMTX100_VEU2 : ProcResource<1>;
+def SMTX100_VEU3 : ProcResource<1>;
+
+def SMTX100_VIEU : ProcResGroup<[SMTX100_VEU0, SMTX100_VEU1]>;
+def SMTX100_VFPU : ProcResGroup<[SMTX100_VEU0, SMTX100_VEU1]>;
+def SMTX100_VLSU : ProcResGroup<[SMTX100_VEU2, SMTX100_VEU3]>;
+
//===----------------------------------------------------------------------===//
// Branching
@@ -245,6 +329,790 @@ let Latency = 3 in {
// Others
def : WriteRes<WriteCSR, [SMTX100_IQ0]>;
def : WriteRes<WriteNop, [SMTX100_IQ]>;
+def : WriteRes<WriteRdVLENB, [SMTX100_IQ0]>;
+
+// 6. Configuration-Setting Instructions
+def : WriteRes<WriteVSETVLI, [SMTX100_IQ0]>;
+def : WriteRes<WriteVSETIVLI, [SMTX100_IQ0]>;
+def : WriteRes<WriteVSETVL, [SMTX100_IQ0]>;
+
+// 7. Vector Loads and Stores
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxList>.c;
+
+ // Unit-stride loads and stores
+ defvar VLDELat = ConstValueUntilLMULThenDoubleBase<"M4", 4, 6, mx>.c;
+ defvar VLDEOcc = ConstValueUntilLMULThenDoubleBase<"M2", 2, 3, mx>.c;
+ let Latency = VLDELat, ReleaseAtCycles = [VLDEOcc] in
+ defm "" : LMULWriteResMX<"WriteVLDE", [SMTX100_VLSU], mx, IsWorstCase>;
+
+ defvar VSTELatAndOcc = GetLMULValue<[2, 2, 2, 3, 5, 10, 18], mx>.c;
+ let Latency = VSTELatAndOcc, ReleaseAtCycles = [VSTELatAndOcc] in
+ defm "" : LMULWriteResMX<"WriteVSTE", [SMTX100_VLSU], mx, IsWorstCase>;
+
+ defvar VLDFFLat = ConstValueUntilLMULThenDoubleBase<"M4", 4, 6, mx>.c;
+ defvar VLDFFOcc = ConstValueUntilLMULThenDoubleBase<"M2", 2, 3, mx>.c;
+ let Latency = VLDFFLat, ReleaseAtCycles = [VLDFFOcc] in
+ defm "" : LMULWriteResMX<"WriteVLDFF", [SMTX100_VLSU], mx, IsWorstCase>;
+
+ // Mask loads and stores
+ let Latency = 4, ReleaseAtCycles = [2] in
+ defm "" : LMULWriteResMX<"WriteVLDM", [SMTX100_VLSU], mx, IsWorstCase>;
+
+ let Latency = 2, ReleaseAtCycles = [2] in
+ defm "" : LMULWriteResMX<"WriteVSTM", [SMTX100_VEU2], mx, IsWorstCase>;
+
+ // Strided and indexed loads and stores
+ // vlse
+ // e8 = [4, 5, 9, 22, 50, 114, 242]
+ // e16 = [ 4, 5, 9, 22, 50, 114]
+ // e32 = [ 4, 5, 9, 22, 50]
+ // e64 = [ 4, 5, 9, 22]
+
+ // Latency only decides by element
+ // vsse
+ // e8 = [4, 8, 16, 32, 64, 128, 256]
+ // e16 = [ 4, 8, 16, 32, 64, 128]
+ // e32 = [ 4, 8, 16, 32, 64]
+ // e64 = [ 4, 8, 16, 32]
+ foreach eew = [8, 16, 32, 64] in {
+ defvar VLDSLatAndOcc = SMTX100GetVLDSLat<mx, eew>.val;
+ let Latency = VLDSLatAndOcc, ReleaseAtCycles = [VLDSLatAndOcc] in
+ defm "" : LMULWriteResMX<"WriteVLDS" # eew, [SMTX100_VLSU], mx, IsWorstCase>;
+
+ defvar VSTSLatAndOcc = SMTX100GetVLMAX<mx, eew>.val;
+ let Latency = VSTSLatAndOcc, ReleaseAtCycles = [VSTSLatAndOcc] in
+ defm "" : LMULWriteResMX<"WriteVSTS" # eew, [SMTX100_VEU2], mx, IsWorstCase>;
+ }
+
+ foreach eew = [8, 16, 32, 64] in {
+ defvar IdxLdStLatAndOcc = !div(SMTX100GetVLMAX<mx, eew>.val, 2);
+ let Latency = IdxLdStLatAndOcc, ReleaseAtCycles = [IdxLdStLatAndOcc] in {
+ defm "" : LMULWriteResMX<"WriteVLDUX" # eew, [SMTX100_VEU2], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX" # eew, [SMTX100_VEU2], mx, IsWorstCase>;
+
+ defm "" : LMULWriteResMX<"WriteVSTUX" # eew, [SMTX100_VEU2], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX" # eew, [SMTX100_VEU2], mx, IsWorstCase>;
+ }
+ }
+}
+
+// Segmented loads and stores
+foreach mx = SchedMxList in {
+ foreach nf=2-8 in {
+ foreach eew = [8, 16, 32, 64] in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defvar EffectiveNF= !if(!le(nf, 4), 1, nf);
+ defvar SegLdStLatAndOcc = SMTX100SegmentedLdStCycles<mx, eew, EffectiveNF>.c;
+ let Latency = SegLdStLatAndOcc, ReleaseAtCycles = [SegLdStLatAndOcc] in {
+ // Unit-stride segmented
+ defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" #eew, [SMTX100_VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" #eew, [SMTX100_VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" #eew, [SMTX100_VLSU], mx, IsWorstCase>;
+
+ // Strided/indexed segmented
+ defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" #eew, [SMTX100_VLSU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" #eew, [SMTX100_VLSU], mx, IsWorstCase>;
+ }
+
+ defvar IdxSegLdStLatAndOcc = SMTX100SegmentedLdStCycles<mx, eew, nf>.c;
+ let Latency = IdxSegLdStLatAndOcc, ReleaseAtCycles = [IdxSegLdStLatAndOcc] in {
+ // Indexed segmented
+ defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" #eew, [SMTX100_VEU2], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" #eew, [SMTX100_VEU2], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" #eew, [SMTX100_VEU2], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" #eew, [SMTX100_VEU2], mx, IsWorstCase>;
+ }
+ }
+ }
+}
+
+// Whole register move/load/store
+foreach LMul = [1, 2, 4, 8] in {
+ defvar WholeLdLatandOcc = !cond(
+ !eq(LMul, 1) : 2,
+ !eq(LMul, 2) : 3,
+ !eq(LMul, 4) : 6,
+ !eq(LMul, 8) : 18);
+ let Latency = WholeLdLatandOcc, ReleaseAtCycles = [WholeLdLatandOcc] in
+ def : WriteRes<!cast<SchedWrite>("WriteVLD" # LMul # "R"), [SMTX100_VLSU]>;
+
+ defvar WholeStLatandOcc = !cond(
+ !eq(LMul, 1) : 3,
+ !eq(LMul, 2) : 5,
+ !eq(LMul, 4) : 10,
+ !eq(LMul, 8) : 18);
+ let Latency = WholeStLatandOcc, ReleaseAtCycles = [WholeStLatandOcc] in
+ def : WriteRes<!cast<SchedWrite>("WriteVST" # LMul # "R"), [SMTX100_VEU2]>;
+
+ // Whole Vector Register Move
+ defvar VMovLat = !cond(
+ !eq(LMul, 1) : 2,
+ !eq(LMul, 2) : 3,
+ !eq(LMul, 4) : 4,
+ !eq(LMul, 8) : 8);
+ let Latency = VMovLat, ReleaseAtCycles = [LMul] in
+ def : WriteRes<!cast<SchedWrite>("WriteVMov" # LMul # "V"), [SMTX100_VEU0]>;
+}
+
+// 11. Vector Integer Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defvar VIALUOcc = ConstOneUntilM1ThenDouble<mx>.c;
+ // Vector Integer Min/Max Instructions
+ let Latency = Get2348Latency<mx>.c, ReleaseAtCycles = [VIALUOcc] in {
+ defm "" : LMULWriteResMX<"WriteVIMinMaxV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxX", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+
+ // Latency of vadd, vsub, vrsub: 3/3/4/8
+ // Latency of vand, vor, vxor: 2/3/4/8
+ // ReleaseAtCycles : 1/2/4/8
+ // They are grouped together, so we used the worst case 3/3/4/8
+ // TODO: use InstRW to override individual instructions' scheduling data
+ defvar VIALULat = ConstValueUntilLMULThenDoubleBase<"M4", 3, 4, mx>.c;
+ let Latency = VIALULat, ReleaseAtCycles = [VIALUOcc] in {
+ defm "" : LMULWriteResMX<"WriteVIALUV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUX", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUI", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+
+ // let Latency = VIALULat in
+ // def SMX100WriteVCOPY_ # mx : SchedWriteRes<[]>;
+
+ let Latency = Get2348Latency<mx>.c, ReleaseAtCycles = [VIALUOcc] in {
+ // Vector Integer Merge Instructions
+ defm "" : LMULWriteResMX<"WriteVIMergeV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeX", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeI", [SMTX100_VIEU], mx, IsWorstCase>;
+ // Vector Integer Move Instructions
+ defm "" : LMULWriteResMX<"WriteVIMovV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovX", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovI", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+
+ defvar VIShiftLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ defvar VIShiftOcc = ConstOneUntilMF2ThenDouble<mx>.c;
+ let Latency = VIShiftLat, ReleaseAtCycles = [VIShiftOcc] in {
+ // Vector Integer Extension Instructions
+ defm "" : LMULWriteResMX<"WriteVExtV", [SMTX100_VEU0], mx, IsWorstCase>;
+ // Vector Single-Width Bit Shift Instructions
+ defm "" : LMULWriteResMX<"WriteVShiftV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftI", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+
+ defvar VICALULat = ConstValueUntilLMULThenDoubleBase<"M4", 3, 4, mx>.c;
+ let Latency = VICALULat, ReleaseAtCycles = [VIALUOcc] in {
+ // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+ defm "" : LMULWriteResMX<"WriteVICALUV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUI", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+
+ defvar VICmpCarryLat = GetLMULValue<[3, 3, 3, 4, 6, 10, 18], mx>.c;
+ // ReleaseAtCycles: e8 = 1/2/3/5/11, e16/e32/e64 = 1/2/3/5/18
+ // but we use the worse case
+ defvar VICmpCarryOcc = GetLMULValue<[1, 1, 1, 2, 3, 5, 18], mx>.c;
+ let Latency = VICmpCarryLat, ReleaseAtCycles = [VICmpCarryOcc] in {
+ defm "" : LMULWriteResMX<"WriteVICALUMV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMI", [SMTX100_VEU0], mx, IsWorstCase>;
+ // Vector Integer Comparison Instructions
+ defm "" : LMULWriteResMX<"WriteVICmpV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpX", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpI", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+
+ // Latency of vmacc, vmadd, vmul, vmulh, etc.: e8/e16 = 3/3/4/8, e32 = 4/4/5/8,
+ // e64 = 7/8/16/32. We use the worst-case until we can split the SEW.
+ // ReleaseAtCycles: e8/e16/e32 = 1,2,4,8, e64 = 4/8/16/32
+ // TODO: change WriteVIMulV, etc to be defined with LMULSEWSchedWrites
+ defvar VIMulLat = ConstValueUntilLMULThenDoubleBase<"M4", 7, 8, mx>.c;
+ defvar VIMulOcc = ConstValueUntilLMULThenDouble<"M1", 4, mx>.c;
+ let Latency = VIMulLat, ReleaseAtCycles = [VIMulOcc] in {
+ // Vector Single-Width Integer Multiply Instructions
+ defm "" : LMULWriteResMX<"WriteVIMulV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulX", [SMTX100_VIEU], mx, IsWorstCase>;
+ // Vector Single-Width Integer Multiply-Add Instructions
+ defm "" : LMULWriteResMX<"WriteVIMulAddV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddX", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+}
+
+// Widening
+foreach mx = SchedMxListW in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxListW>.c;
+
+ // Vector Widening Integer Add/Subtract
+ defvar VIWIntLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ defvar VIWideningOcc = GetLMULValue<[1, 1, 2, 2, 4, 8], mx>.c;
+ let Latency = VIWIntLat, ReleaseAtCycles = [VIWideningOcc] in {
+ defm "" : LMULWriteResMX<"WriteVIWALUV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUX", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUI", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+
+ // Pattern of vwmul/vwmacc, etc: e8/e16 = 3/3/4/8, e32 = 4/4/5/8
+ defvar VIWMulLat = ConstValueUntilLMULThenDoubleBase<"M2", 4, 5, mx>.c;
+ let Latency = VIWMulLat, ReleaseAtCycles = [VIWideningOcc] in {
+ // Vector Widening Integer Multiply Instructions
+ defm "" : LMULWriteResMX<"WriteVIWMulV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulX", [SMTX100_VIEU], mx, IsWorstCase>;
+ // Vector Widening Integer Multiply-Add Instructions
+ defm "" : LMULWriteResMX<"WriteVIWMulAddV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddX", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+}
+
+// Division and remainder operations
+// Pattern of vdivu: 17/17/17/25/52/102/205
+// Pattern of vdiv: 17/17/17/22/44/88/176
+// Pattern of vremu: 15/15/15/20/40/80/160
+// Pattern of vrem: 15/15/15/22/45/89/176
+// We use for all: 17/17/17/25/52/104/208
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+
+ // Not pipelined
+ defvar VIDivLatAndOcc = ConstValueUntilLMULThenDoubleBase<"M1", 17, 25, mx>.c;
+ let Latency = VIDivLatAndOcc, ReleaseAtCycles = [VIDivLatAndOcc] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Narrowing Shift and Clips
+foreach mx = SchedMxListW in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxListW>.c;
+
+ defvar VNarrowingLat = ConstValueUntilLMULThenDoubleBase<"M1", 3, 4, mx>.c;
+ defvar VNarrowingOcc = ConstOneUntilMF4ThenDouble<mx>.c;
+ let Latency = VNarrowingLat, ReleaseAtCycles = [VNarrowingOcc] in {
+ defm "" : LMULWriteResMX<"WriteVNShiftV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftI", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipI", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+}
+
+// 12. Vector Fixed-Point Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defvar VFALULat = ConstValueUntilLMULThenDoubleBase<"M4", 3, 4, mx>.c;
+ let Latency = VFALULat, ReleaseAtCycles = [ConstOneUntilM1ThenDouble<mx>.c] in {
+ defm "" : LMULWriteResMX<"WriteVSALUV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUX", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUI", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUX", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+
+ // Latency of vsmul: e8/e16 = 3/3/4/8, e32 = 4/4/5/8, e64 = 7/8/16/32
+ // We use the worst-case until we can split the SEW.
+ defvar VSMulLat = ConstValueUntilLMULThenDoubleBase<"M2", 7, 8, mx>.c;
+ // ReleaseAtCycles of vsmul: e8/e16/e32 = 1/2/4/8, e64 = 4/8/16/32
+ // We use the worst-case until we can split the SEW.
+ defvar VSMulOcc = ConstValueUntilLMULThenDoubleBase<"M1", 1, 4, mx>.c;
+ // TODO: change WriteVSMulV/X to be defined with LMULSEWSchedWrites
+ let Latency = VSMulLat, ReleaseAtCycles = [VSMulOcc] in {
+ defm "" : LMULWriteResMX<"WriteVSMulV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulX", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+
+ defvar VSShiftLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ defvar VSShiftOcc = ConstOneUntilMF2ThenDouble<mx>.c;
+ let Latency = VSShiftLat, ReleaseAtCycles = [VSShiftOcc] in {
+ defm "" : LMULWriteResMX<"WriteVSShiftV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftI", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+}
+
+// 13. Vector Floating-Point Instructions
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+
+ defvar VFALUOcc = ConstOneUntilM1ThenDouble<mx>.c;
+ let Latency = Get4458Latency<mx>.c, ReleaseAtCycles = [VFALUOcc] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ }
+
+ defvar VFMaxMinLat = ConstValueUntilLMULThenDoubleBase<"M4", 3, 4, mx>.c;
+ let Latency = VFMaxMinLat, ReleaseAtCycles = [VFALUOcc] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ }
+
+ // Latency: e32 = 4/4/5/8, e64 = 5/5/5/8
+ // Slightly increased latency for sew == 64
+ defvar VFMulLat = !if(!eq(sew, 64), ConstValueUntilLMULThenDoubleBase<"M8", 5, 8, mx>.c,
+ Get4458Latency<mx>.c);
+ let Latency = VFMulLat, ReleaseAtCycles = [ConstOneUntilM1ThenDouble<mx>.c] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ }
+
+ defvar VFSgnjLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ defvar VFSgnjOcc = ConstOneUntilMF2ThenDouble<mx>.c;
+ let Latency = VFSgnjLat, ReleaseAtCycles = [VFSgnjOcc] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ }
+
+ // The following covers vfmacc, vfmsac, vfmadd and their vfn* variants in the same group, but the
+ // ReleaseAtCycles takes one extra cycle for the vfn* variants on lmul == 4
+ // vfmacc/vfmacc/vfmadd/vfmsub: 1/2/4/8 and vfn* variants: 1/2/5/8
+ // Latency: e32 = 4/4/5/8, e64 = 5/5/5/8
+ defvar VFFulAddLat = !if(!eq(sew, 64), ConstValueUntilLMULThenDoubleBase<"M8", 5, 8, mx>.c,
+ Get4458Latency<mx>.c);
+ let Latency = VFFulAddLat, ReleaseAtCycles = [ConstOneUntilM1ThenDouble<mx>.c] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defvar VFCmpLat = GetLMULValue<[3, 3, 3, 4, 6, 10, 18], mx>.c;
+ defvar VFCmpOcc = GetLMULValue<[1, 1, 1, 2, 3, 5, 18], mx>.c;
+ let Latency = VFCmpLat, ReleaseAtCycles = [VFCmpOcc] in {
+ defm "" : LMULWriteResMX<"WriteVFCmpV", [SMTX100_VFPU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFCmpF", [SMTX100_VFPU], mx, IsWorstCase>;
+ }
+
+ defvar VFClassLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ defvar VFClassOcc = ConstOneUntilMF2ThenDouble<mx>.c;
+ let Latency = VFClassLat, ReleaseAtCycles = [VFClassOcc] in {
+ defm "" : LMULWriteResMX<"WriteVFClassV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMergeV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMovV", [SMTX100_VEU0], mx, IsWorstCase>;
+ // TODO TEST LMUL = MF8
+ defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+}
+
+// Widening
+foreach mx = SchedMxListW in {
+ foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
+ defvar VFWCvtILat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ defvar VFWCvtIOcc = ConstOneUntilMF4ThenDouble<mx>.c;
+ let Latency = VFWCvtILat, ReleaseAtCycles = [VFWCvtIOcc] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListFW in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxListFW>.c;
+
+ defvar VFWCvtFToIVLat = ConstValueUntilLMULThenDoubleBase<"M1", 3, 4, mx>.c;
+ defvar VFWCvtFToIVOcc = ConstOneUntilMF4ThenDouble<mx>.c;
+ let Latency = VFWCvtFToIVLat, ReleaseAtCycles = [VFWCvtFToIVOcc] in
+ defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [SMTX100_VEU0], mx, IsWorstCase>;
+}
+
+foreach mx = SchedMxListFW in {
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+
+ defvar VFWCvtFToFVLat = ConstValueUntilLMULThenDoubleBase<"M1", 3, 4, mx>.c;
+ defvar VFWCvtFToFVOcc = ConstOneUntilMF4ThenDouble<mx>.c;
+ let Latency = VFWCvtFToFVLat, ReleaseAtCycles = [VFWCvtFToFVOcc] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+
+ // Latency for vfwsub/vfwadd.vv, vfwsub/vfwadd.vf:
+ // e16 = 3/3/3/4/8, e32 = 4/4/5/8
+ // ReleaseAtCycles for vfwsub/vfwadd.vv, vfwsub/vfwadd.vf: 1/2/2/4/8
+ // Latency for vfwsub/vfwadd.wv, vfwsub/vfwadd.wf:
+ // e16 = 4/4/6/8/16, e32 = 5/6/8/16
+ // ReleaseAtCycles for vfwsub/vfwadd.wv, vfwsub/vfwadd.wf: 2/2/4/8/16
+ // We use the worst-case
+ // TODO: Split .vv/.wv variants into separate scheduling classes
+ defvar VFWALULat = !if(!eq(sew, 16),
+ GetLMULValue<[4, 4, 4, 6, 8, 16], mx>.c,
+ GetLMULValue<[5, 5, 5, 6, 8, 16], mx>.c
+ );
+ defvar VFWALUOcc = GetLMULValue<[2, 2, 2, 4, 8, 16], mx>.c;
+ let Latency = VFWALULat, ReleaseAtCycles = [VFWALUOcc] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ }
+
+ // Latency for vfwmul, vfwmacc, vfwnmacc, etc: e16 = 4/4/4/5/8; e32 = 5/5/5/8
+ defvar VFWMulLat = !if(!eq(sew, 16),
+ GetLMULValue<[4, 4, 4, 4, 5, 8], mx>.c,
+ GetLMULValue<[5, 5, 5, 5, 5, 8], mx>.c
+ );
+ defvar VFWMulOcc = GetLMULValue<[1, 1, 2, 2, 4, 8], mx>.c;
+ let Latency = VFWMulLat, ReleaseAtCycles = [VFWMulOcc] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxListW>.c;
+
+ defvar VFNCvtFToIVLat = GetLMULValue<[3, 3, 4, 4, 8, 16], mx>.c;
+ defvar VFNCvtFToIVOcc = ConstOneUntilMF4ThenDouble<mx>.c;
+ let Latency = VFNCvtFToIVLat, ReleaseAtCycles = [VFNCvtFToIVOcc] in
+ defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [SMTX100_VEU0], mx, IsWorstCase>;
+}
+
+foreach mx = SchedMxListFW in {
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+
+ defvar VFNCvtToFVLat = GetLMULValue<[3, 3, 4, 4, 8, 16], mx>.c;
+ defvar VFNCvtToFVOcc = ConstOneUntilMF4ThenDouble<mx>.c;
+ let Latency = VFNCvtToFVLat, ReleaseAtCycles = [VFNCvtToFVOcc] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Vector Floating-Point Division and Square Root
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+
+ // Compute ReleaseAtCycles based on SEW
+ // vfdiv.vf and vfrdiv.vf a slight latency difference
+ // e16 = 14/28/57/116 , e32 = 24/48/82/193, e64 = 12/24/48/96
+ defvar VFDivFLatAndOcc = !cond(
+ !eq(sew, 16): 14,
+ !eq(sew, 32): 24,
+ !eq(sew, 64): 12,
+ );
+ let Latency = VFDivFLatAndOcc, ReleaseAtCycles = [VFDivFLatAndOcc] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+
+ // e16 = 28/56/112/224, e32 = 36/72/145/290, e64 = 66/132/263/527
+ defvar VFDivVFactor = !cond(
+ !eq(sew, 16): 28,
+ !eq(sew, 32): 36,
+ !eq(sew, 64): 66,
+ );
+ defvar VFDivVLatAndOcc = !mul(ConstOneUntilM1ThenDouble<mx>.c, VFDivVFactor);
+ let Latency = VFDivVLatAndOcc, ReleaseAtCycles = [VFDivVLatAndOcc] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ }
+}
+
+// Pattern for vfsqrt.v: e16 = 26/52/104/208; e32 = 35/72/140/276; e64 = 52/99/216/412
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+
+ defvar VFSqrtVFactor = !cond(
+ !eq(sew, 16): 26,
+ !eq(sew, 32): 35,
+ !eq(sew, 64): 52,
+ );
+ defvar VFSqrtVLatAndOcc = !mul(ConstOneUntilM1ThenDouble<mx>.c, VFSqrtVFactor);
+ let Latency = VFSqrtVLatAndOcc, ReleaseAtCycles = [VFSqrtVLatAndOcc] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [SMTX100_VEU0], mx, sew, IsWorstCase>;
+ }
+}
+
+// 14. Vector Reduction Operations
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+
+ defvar VIRedLat = GetLMULValue<[4, 4, 4, 5, 7, 11, 19], mx>.c;
+ defvar VIRedOcc = GetLMULValue<[1, 1, 1, 1, 2, 6, 19], mx>.c;
+ let Latency = VIRedLat, ReleaseAtCycles = [VIRedOcc] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SMTX100_VIEU], mx, sew, IsWorstCase>;
+
+ // Latency:
+ // Pattern for vredsum: 4/4/4/5/7/11/19
+ // Pattern for vredand, vredor, vredxor: 3/3/3/4/6/10/18
+ // ReleaseAtCycles:
+ // Pattern for vredsum: 1/1/1/1/2/6/19
+ // Pattern for vredand, vredor, vredxor: 1/1/1/1/2/5/18
+ // They are grouped together, so we use the worst-case vredsum latency.
+ // TODO: split vredand, vredor, vredxor into separate scheduling classe.
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SMTX100_VIEU], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxListWRed in {
+ foreach sew = SchedSEWSet<mx, 0, 1>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
+
+ defvar VIRedLat = GetLMULValue<[4, 4, 4, 5, 7, 11, 19], mx>.c;
+ defvar VIRedOcc = GetLMULValue<[1, 1, 1, 1, 2, 6, 19], mx>.c;
+ let Latency = VIRedLat, ReleaseAtCycles = [VIRedOcc] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [SMTX100_VIEU], mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+
+ // Latency is slightly lower for e16/e32, We use the worst-case
+ defvar VFRedLat = GetLMULValue<[12, 12, 12, 15, 21, 33, 57], mx>.c;
+ defvar VFRedOcc = GetLMULValue<[8, 8, 8, 8, 14, 20, 57], mx>.c;
+ let Latency = VFRedLat, ReleaseAtCycles = [VFRedOcc] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+
+ // Compute latency based on SEW
+ defvar VFRedOV_FromLat = !cond(
+ !eq(sew, 16) : ConstValueUntilLMULThenDouble<"MF4", 12, mx>.c,
+ !eq(sew, 32) : ConstValueUntilLMULThenDouble<"MF2", 12, mx>.c,
+ !eq(sew, 64) : ConstValueUntilLMULThenDouble<"M1", 12, mx>.c
+ );
+ defvar VFRedOV_FromOcc = !cond(
+ !eq(sew, 16) : GetLMULValue<[8, 8, 20, 23, 47, 96, 384], mx>.c,
+ !eq(sew, 32) : GetLMULValue<[8, 8, 8, 11, 23, 48, 192], mx>.c,
+ !eq(sew, 64) : GetLMULValue<[6, 6, 6, 6, 12, 25, 97], mx>.c
+ );
+ let Latency = VFRedOV_FromLat, ReleaseAtCycles = [VFRedOV_FromOcc] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListFWRed in {
+ foreach sew = SchedSEWSet<mx, 1, 1>.val in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
+
+ defvar VFRedOVLat = !cond(
+ !eq(sew, 16) : ConstValueUntilLMULThenDouble<"MF4", 16, mx>.c,
+ !eq(sew, 32) : ConstValueUntilLMULThenDouble<"MF2", 16, mx>.c,
+ );
+ defvar VFRedOVOcc = !cond(
+ !eq(sew, 16) : GetLMULValue<[10, 10, 26, 31, 64, 128, 512], mx>.c,
+ !eq(sew, 32) : GetLMULValue<[10, 10, 10, 15, 31, 66, 256], mx>.c,
+ );
+ let Latency = VFRedOVLat, ReleaseAtCycles = [VFRedOVOcc] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [SMTX100_VFPU], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// 15. Vector Mask Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxList>.c;
+
+ let Latency = 2, ReleaseAtCycles = [1] in
+ defm "" : LMULWriteResMX<"WriteVMALUV", [SMTX100_VEU0], mx, IsWorstCase>;
+
+ let Latency = 3, ReleaseAtCycles = [GetLMULValue<[1, 1, 1, 1, 1, 2, 3], mx>.c] in
+ defm "" : LMULWriteResMX<"WriteVMSFSV", [SMTX100_VEU0], mx, IsWorstCase>;
+
+ let Latency = 6, ReleaseAtCycles = [6] in {
+ defm "" : LMULWriteResMX<"WriteVMPopV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMFFSV", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+
+ defvar VIotaLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ defvar VIotaOcc = ConstOneUntilMF2ThenDouble<mx>.c;
+ let Latency = VIotaLat, ReleaseAtCycles = [VIotaOcc] in {
+ defm "" : LMULWriteResMX<"WriteVIotaV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIdxV", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+}
+
+// 16. Vector Permutation Instructions
+// Slide
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defvar VSlideUpLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ defvar VSlideUpOcc = ConstOneUntilMF2ThenDouble<mx>.c;
+ let Latency = VSlideUpLat, ReleaseAtCycles =[VSlideUpOcc] in {
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+
+ defvar VSlideDownLat = GetLMULValue<[3, 3, 3, 4, 5, 9, 17], mx>.c;
+ defvar VSlideDownOcc = GetLMULValue<[1, 1, 1, 3, 5, 9, 17], mx>.c;
+ let Latency = VSlideDownLat, ReleaseAtCycles =[VSlideDownOcc] in {
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+}
+
+// ReleaseAtCycles is 2/2/2/2/2/3/6, but we can't set based on MX for now
+// TODO: Split this into separate WriteRes for each MX
+let Latency = 6, ReleaseAtCycles = [6] in {
+ def : WriteRes<WriteVMovXS, [SMTX100_VEU0]>;
+ def : WriteRes<WriteVMovFS, [SMTX100_VEU0]>;
+}
+
+// ReleaseAtCycles is 1/1/1/1/1/2/3, but we can't set based on MX for now
+// TODO: Split this into separate WriteRes for each MX
+let Latency = 3, ReleaseAtCycles = [3] in {
+ def : WriteRes<WriteVMovSX, [SMTX100_VEU0]>;
+ def : WriteRes<WriteVMovSF, [SMTX100_VEU0]>;
+}
+
+// Integer LMUL Gather and Compress
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxList>.c;
+
+ defvar VRGatherLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ let Latency = VRGatherLat, ReleaseAtCycles = [ConstOneUntilMF2ThenDouble<mx>.c] in {
+ defm "" : LMULWriteResMX<"WriteVRGatherVX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRGatherVI", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar IsWorstCaseSEW = SMTX100IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+
+ defvar VRGatherVVLat = GetLMULValue<[3, 3, 3, 3, 8, 32, 128], mx>.c;
+ defvar VRGatherVVOcc = GetLMULValue<[1, 1, 1, 2, 8, 32, 128], mx>.c;
+ let Latency = VRGatherVVLat, ReleaseAtCycles = [VRGatherVVOcc] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [SMTX100_VEU0], mx, sew, IsWorstCaseSEW>;
+
+ defvar VRGatherEI16Lat = !if(!eq(sew, 8),
+ GetLMULValue<[3, 3, 4, 4, 16, 64, 128], mx>.c,
+ GetLMULValue<[3, 3, 3, 3, 8, 32, 128], mx>.c);
+ defvar VRGatherEI16Occ = !if(!eq(sew, 8),
+ GetLMULValue<[1, 1, 2, 4, 16, 64, 128], mx>.c,
+ GetLMULValue<[1, 1, 1, 2, 8, 32, 128], mx>.c);
+ let Latency = VRGatherEI16Lat, ReleaseAtCycles = [VRGatherEI16Occ] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [SMTX100_VEU0], mx, sew, IsWorstCaseSEW>;
+
+ defvar VCompressVLat = GetLMULValue<[3, 3, 3, 4, 10, 36, 136], mx>.c;
+ defvar VCompressVOcc = GetLMULValue<[1, 1, 1, 3, 10, 36, 136], mx>.c;
+ let Latency = VCompressVLat, ReleaseAtCycles = [VCompressVOcc] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [SMTX100_VEU0], mx, sew, IsWorstCaseSEW>;
+ }
+}
+
+// Vector Crypto
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxList>.c;
+ defvar LMulOcc = !mul(SMTX100GetLMulCycles<mx>.c, 2);
+
+ defvar Lat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ defvar Occ = ConstValueUntilLMULThenDouble<"MF2", 1, mx>.c;
+ let Latency = Lat, ReleaseAtCycles = [Occ] in {
+ // Zvbb
+ defm "" : LMULWriteResMX<"WriteVBREVV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCLZV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCTZV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCPOPV", [SMTX100_VEU0], mx, IsWorstCase>;
+ // Zvkb
+ // VANDN uses WriteVIALU[V|X|I]
+ defm "" : LMULWriteResMX<"WriteVBREV8V", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVREV8V", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRotV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRotX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRotI", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+
+ defvar VCLAndVGLat = ConstValueUntilLMULThenDoubleBase<"M2", 3, 4, mx>.c;
+ let Latency = VCLAndVGLat, ReleaseAtCycles = [LMulOcc] in {
+ // Zvbc
+ defm "" : LMULWriteResMX<"WriteVCLMULV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVCLMULX", [SMTX100_VEU0], mx, IsWorstCase>;
+
+ // Zvkg
+ defm "" : LMULWriteResMX<"WriteVGHSHV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVGMULV", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+
+ // ZvknhaOrZvknhb
+ // vsha2ch.vv / vsha2cl.vv are modeled LMUL-only using the SEW=32 curve:
+ // M2=4, M4=8, M8=16
+ // e32: M2=4, M4=8, M8=16
+ // e64: M4=4, M8=8
+ // TODO: Shold set vsha2ch.vv / vsha2cl.vv SEW-aware?
+ defvar VSHALatandOcc = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;
+ let Latency = VSHALatandOcc, ReleaseAtCycles = [VSHALatandOcc] in {
+ defm "" : LMULWriteResMX<"WriteVSHA2CHV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSHA2CLV", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+
+ // vsha2ms.vv latency depends on SEW: doubling SEW shifts the doubling
+ // threshold right by one LMUL step.
+ // e32: M2=4, M4=8, M8=16
+ // e64: M4=4, M8=8
+ defvar ZvknhSEWs = !listremove(SchedSEWSet<mx>.val, [8, 16]);
+ // Smallest SEW (=32) carries the highest latency, so the WorstCase fallback
+ // is designated to the smallest SEW at the largest LMUL.
+ defvar SmallestZvknhSEW = !head(ZvknhSEWs);
+ foreach sew = ZvknhSEWs in {
+ defvar IsWorstCaseVSHA2MSV = !and(IsWorstCase, !eq(sew, SmallestZvknhSEW));
+ defvar VSHA2MSLatandOcc =
+ ConstValueUntilLMULThenDouble<!if(!eq(sew, 64), "M4", "M2"), 4, mx>.c;
+ let Latency = VSHA2MSLatandOcc, ReleaseAtCycles = [VSHA2MSLatandOcc] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVSHA2MSV", [SMTX100_VIEU], mx, sew,
+ IsWorstCaseVSHA2MSV>;
+ }
+
+ // Zvkned
+ defvar VASELatandOcc = ConstValueUntilLMULThenDouble<"M1", 2, mx>.c;
+ let Latency = VASELatandOcc, ReleaseAtCycles = [VASELatandOcc] in {
+ defm "" : LMULWriteResMX<"WriteVAESMVV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAESKF1V", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAESKF2V", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAESZV", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+
+ defvar VSM3CLat = ConstValueUntilLMULThenDouble<"M4", 4, mx>.c;
+ let Latency = VSM3CLat, ReleaseAtCycles = [SMTX100GetLMulCycles<mx>.c] in
+ defm "" : LMULWriteResMX<"WriteVSM3CV", [SMTX100_VIEU], mx, IsWorstCase>;
+
+ defvar VSM3MLat = ConstValueUntilLMULThenDoubleBase<"M4", 3, 4, mx>.c;
+ let Latency = VSM3MLat, ReleaseAtCycles = [SMTX100GetLMulCycles<mx>.c] in
+ defm "" : LMULWriteResMX<"WriteVSM3MEV", [SMTX100_VIEU], mx, IsWorstCase>;
+
+ defvar VSM4Lat = ConstValueUntilLMULThenDouble<"M2", 4, mx>.c;
+ let Latency = 3, ReleaseAtCycles = [LMulOcc] in {
+ defm "" : LMULWriteResMX<"WriteVSM4KV", [SMTX100_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSM4RV", [SMTX100_VIEU], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListW in {
+ defvar IsWorstCase = SMTX100IsWorstCaseMX<mx, SchedMxListW>.c;
+
+ defvar VWSLat = ConstValueUntilLMULThenDoubleBase<"M1", 3, 4, mx>.c;
+ defvar VWSOcc = ConstValueUntilLMULThenDouble<"MF4", 1, mx>.c;
+ let Latency = VWSLat, ReleaseAtCycles = [VWSOcc] in {
+ defm "" : LMULWriteResMX<"WriteVWSLLV", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVWSLLX", [SMTX100_VEU0], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVWSLLI", [SMTX100_VEU0], mx, IsWorstCase>;
+ }
+}
//===----------------------------------------------------------------------===//
// Bypass and advance
@@ -355,16 +1223,224 @@ def : ReadAdvance<ReadFRoundF32, 0>;
def : ReadAdvance<ReadFRoundF64, 0>;
def : ReadAdvance<ReadFRoundF16, 0>;
+// 6. Configuration-Setting Instructions
+def : ReadAdvance<ReadVSETVLI, 0>;
+def : ReadAdvance<ReadVSETVL, 0>;
+
+// 7. Vector Loads and Stores
+def : ReadAdvance<ReadVLDX, 0>;
+def : ReadAdvance<ReadVSTX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTM", 0>;
+def : ReadAdvance<ReadVLDSX, 0>;
+def : ReadAdvance<ReadVSTSX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
+defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVST1R, 0>;
+def : ReadAdvance<ReadVST2R, 0>;
+def : ReadAdvance<ReadVST4R, 0>;
+def : ReadAdvance<ReadVST8R, 0>;
+
+// 11. Vector Integer Arithmetic Instructions
+defm : LMULReadAdvance<"ReadVIALUV", 0>;
+defm : LMULReadAdvance<"ReadVIALUX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;
+defm : LMULReadAdvance<"ReadVExtV", 0>;
+defm : LMULReadAdvance<"ReadVICALUV", 0>;
+defm : LMULReadAdvance<"ReadVICALUX", 0>;
+defm : LMULReadAdvance<"ReadVShiftV", 0>;
+defm : LMULReadAdvance<"ReadVShiftX", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;
+defm : LMULReadAdvance<"ReadVICmpV", 0>;
+defm : LMULReadAdvance<"ReadVICmpX", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;
+defm : LMULReadAdvance<"ReadVIMulV", 0>;
+defm : LMULReadAdvance<"ReadVIMulX", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddV", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
+defm : LMULReadAdvance<"ReadVIMergeV", 0>;
+defm : LMULReadAdvance<"ReadVIMergeX", 0>;
+defm : LMULReadAdvance<"ReadVIMovV", 0>;
+defm : LMULReadAdvance<"ReadVIMovX", 0>;
+
+// 12. Vector Fixed-Point Arithmetic Instructions
+defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
+
+// 13. Vector Floating-Point Instructions
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;
+defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
+defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
+defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
+
+// 14. Vector Reduction Operations
+def : ReadAdvance<ReadVIRedV, 0>;
+def : ReadAdvance<ReadVIRedV0, 0>;
+def : ReadAdvance<ReadVIWRedV, 0>;
+def : ReadAdvance<ReadVIWRedV0, 0>;
+def : ReadAdvance<ReadVFRedV, 0>;
+def : ReadAdvance<ReadVFRedV0, 0>;
+def : ReadAdvance<ReadVFRedOV, 0>;
+def : ReadAdvance<ReadVFRedOV0, 0>;
+def : ReadAdvance<ReadVFWRedV, 0>;
+def : ReadAdvance<ReadVFWRedV0, 0>;
+def : ReadAdvance<ReadVFWRedOV, 0>;
+def : ReadAdvance<ReadVFWRedOV0, 0>;
+
+// 15. Vector Mask Instructions
+defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
+defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
+
+// 16. Vector Permutation Instructions
+def : ReadAdvance<ReadVMovXS, 0>;
+def : ReadAdvance<ReadVMovSX_V, 0>;
+def : ReadAdvance<ReadVMovSX_X, 0>;
+def : ReadAdvance<ReadVMovFS, 0>;
+def : ReadAdvance<ReadVMovSF_V, 0>;
+def : ReadAdvance<ReadVMovSF_F, 0>;
+defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVMov1V, 0>;
+def : ReadAdvance<ReadVMov2V, 0>;
+def : ReadAdvance<ReadVMov4V, 0>;
+def : ReadAdvance<ReadVMov8V, 0>;
+
+// Vector Crypto Extensions
+// Zvbb
+defm "" : LMULReadAdvance<"ReadVBREVV", 0>;
+defm "" : LMULReadAdvance<"ReadVCLZV", 0>;
+defm "" : LMULReadAdvance<"ReadVCPOPV", 0>;
+defm "" : LMULReadAdvance<"ReadVCTZV", 0>;
+defm "" : LMULReadAdvance<"ReadVWSLLV", 0>;
+defm "" : LMULReadAdvance<"ReadVWSLLX", 0>;
+// Zvbc
+defm "" : LMULReadAdvance<"ReadVCLMULV", 0>;
+defm "" : LMULReadAdvance<"ReadVCLMULX", 0>;
+// Zvkb
+// VANDN uses ReadVIALU[V|X|I]
+defm "" : LMULReadAdvance<"ReadVBREV8V", 0>;
+defm "" : LMULReadAdvance<"ReadVREV8V", 0>;
+defm "" : LMULReadAdvance<"ReadVRotV", 0>;
+defm "" : LMULReadAdvance<"ReadVRotX", 0>;
+// Zvkg
+defm "" : LMULReadAdvance<"ReadVGHSHV", 0>;
+defm "" : LMULReadAdvance<"ReadVGMULV", 0>;
+// Zvknha or Zvknhb
+defm "" : LMULReadAdvance<"ReadVSHA2CHV", 0>;
+defm "" : LMULReadAdvance<"ReadVSHA2CLV", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVSHA2MSV", 0>;
+// Zvkned
+defm "" : LMULReadAdvance<"ReadVAESMVV", 0>;
+defm "" : LMULReadAdvance<"ReadVAESKF1V", 0>;
+defm "" : LMULReadAdvance<"ReadVAESKF2V", 0>;
+defm "" : LMULReadAdvance<"ReadVAESZV", 0>;
+// Zvksed
+defm "" : LMULReadAdvance<"ReadVSM4KV", 0>;
+defm "" : LMULReadAdvance<"ReadVSM4RV", 0>;
+// Zbksh
+defm "" : LMULReadAdvance<"ReadVSM3CV", 0>;
+defm "" : LMULReadAdvance<"ReadVSM3MEV", 0>;
+
+// Others
+def : ReadAdvance<ReadVMask, 0>;
+def : ReadAdvance<ReadVPassthru_WorstCase, 0>;
+foreach mx = SchedMxList in {
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;
+ foreach sew = SchedSEWSet<mx>.val in
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;
+}
+
//===----------------------------------------------------------------------===//
// Unsupported extensions
defm : UnsupportedSchedQ;
-defm : UnsupportedSchedV;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbkb;
defm : UnsupportedSchedZbkx;
defm : UnsupportedSchedZfaWithQ;
-defm : UnsupportedSchedZvk;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedXsf;
}
-
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
index 3d97bb0569291..95f8c1c487832 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSpacemitX60.td
@@ -973,10 +973,13 @@ foreach mx = SchedMxList in {
// The following group slide up and down together, so we use the worst-case
// (slide down) for all.
let Latency = VSlideDownLat, ReleaseAtCycles =[VSlideDownOcc] in {
- defm "" : LMULWriteResMX<"WriteVSlideI", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlide1X", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [SMX60_VIEU], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [SMX60_VIEU], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [SMX60_VFP], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [SMX60_VFP], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [SMX60_VFP], mx, IsWorstCase>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td
index eecae36a2d83d..d6a1f341e3e33 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonX.td
@@ -875,9 +875,12 @@ foreach mx = SchedMxList in {
let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
defm "" : LMULWriteResMX<"WriteVSlideUpX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSlideDownX", [AscalonFX, AscalonV], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSlideI", [AscalonFX, AscalonV], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVISlide1X", [AscalonFX, AscalonV], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVFSlide1F", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideUpI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Up", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1Down", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Up", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1Down", [AscalonFX, AscalonV], mx, IsWorstCase>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index 601308b377c6f..77eec16987b87 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -558,9 +558,12 @@ def WriteVMovFS : SchedWrite;
// 16.3. Vector Slide Instructions
defm "" : LMULSchedWrites<"WriteVSlideUpX">;
defm "" : LMULSchedWrites<"WriteVSlideDownX">;
-defm "" : LMULSchedWrites<"WriteVSlideI">;
-defm "" : LMULSchedWrites<"WriteVISlide1X">;
-defm "" : LMULSchedWrites<"WriteVFSlide1F">;
+defm "" : LMULSchedWrites<"WriteVSlideUpI">;
+defm "" : LMULSchedWrites<"WriteVSlideDownI">;
+defm "" : LMULSchedWrites<"WriteVISlide1Up">;
+defm "" : LMULSchedWrites<"WriteVISlide1Down">;
+defm "" : LMULSchedWrites<"WriteVFSlide1Up">;
+defm "" : LMULSchedWrites<"WriteVFSlide1Down">;
// 16.4. Vector Register Gather Instructions
defm "" : LMULSEWSchedWrites<"WriteVRGatherVV">;
defm "" : LMULSEWSchedWrites<"WriteVRGatherEI16VV">;
@@ -1000,9 +1003,12 @@ def : WriteRes<WriteVMovSF, []>;
def : WriteRes<WriteVMovFS, []>;
defm "" : LMULWriteRes<"WriteVSlideUpX", []>;
defm "" : LMULWriteRes<"WriteVSlideDownX", []>;
-defm "" : LMULWriteRes<"WriteVSlideI", []>;
-defm "" : LMULWriteRes<"WriteVISlide1X", []>;
-defm "" : LMULWriteRes<"WriteVFSlide1F", []>;
+defm "" : LMULWriteRes<"WriteVSlideUpI", []>;
+defm "" : LMULWriteRes<"WriteVSlideDownI", []>;
+defm "" : LMULWriteRes<"WriteVISlide1Up", []>;
+defm "" : LMULWriteRes<"WriteVISlide1Down", []>;
+defm "" : LMULWriteRes<"WriteVFSlide1Up", []>;
+defm "" : LMULWriteRes<"WriteVFSlide1Down", []>;
defm "" : LMULSEWWriteRes<"WriteVRGatherVV", []>;
defm "" : LMULSEWWriteRes<"WriteVRGatherEI16VV", []>;
defm "" : LMULWriteRes<"WriteVRGatherVX", []>;
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/arithmetic.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/arithmetic.test
new file mode 100644
index 0000000000000..ca13a241d77cf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/arithmetic.test
@@ -0,0 +1,4539 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/arithmetic.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMTX100_BQ:2
+# CHECK-NEXT: [1] - SMTX100_FQ:4 SMTX100_FQ0, SMTX100_FQ0, SMTX100_FQ1, SMTX100_FQ1
+# CHECK-NEXT: [2] - SMTX100_FQ0:2
+# CHECK-NEXT: [3] - SMTX100_FQ1:2
+# CHECK-NEXT: [4] - SMTX100_IQ:4 SMTX100_IQ0, SMTX100_IQ0, SMTX100_IQ1, SMTX100_IQ1
+# CHECK-NEXT: [5] - SMTX100_IQ0:2
+# CHECK-NEXT: [6] - SMTX100_IQ1:2
+# CHECK-NEXT: [7] - SMTX100_LSQ:4
+# CHECK-NEXT: [8] - SMTX100_VEU0:1
+# CHECK-NEXT: [9] - SMTX100_VEU1:1
+# CHECK-NEXT: [10] - SMTX100_VEU2:1
+# CHECK-NEXT: [11] - SMTX100_VEU3:1
+# CHECK-NEXT: [12] - SMTX100_VFPU:2 SMTX100_VEU0, SMTX100_VEU1
+# CHECK-NEXT: [13] - SMTX100_VIEU:2 SMTX100_VEU0, SMTX100_VEU1
+# CHECK-NEXT: [14] - SMTX100_VLSU:2 SMTX100_VEU2, SMTX100_VEU3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VI vadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VV vadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VADD_VX vadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSUB_VV vsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSUB_VX vsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VVM vadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VXM vadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VADC_VIM vadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSBC_VVM vsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSBC_VXM vsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_VV vwaddu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_VX vwaddu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_VV vwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_VX vwadd.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_VV vwsubu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_VX vwsubu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_VV vwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_VX vwsub.vx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADDU_VV vaaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADDU_VX vaaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADD_VV vaadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAADD_VX vaadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUBU_VV vasubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUBU_VX vasubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUB_VV vasub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VASUB_VX vasub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VI vmadc.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VIM vmadc.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VV vmadc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VVM vmadc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VX vmadc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMADC_VXM vmadc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VV vmsbc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VVM vmsbc.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VX vmsbc.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 SMTX100_VEU0[5],SMTX100_VFPU[5],SMTX100_VIEU[5] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMTX100_VEU0[18],SMTX100_VFPU[18],SMTX100_VIEU[18] VMSBC_VXM vmsbc.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VRSUB_VI vrsub.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VRSUB_VX vrsub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VI vsaddu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VV vsaddu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADDU_VX vsaddu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VI vsadd.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VV vsadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSADD_VX vsadd.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUBU_VV vssubu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUBU_VX vssubu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUB_VV vssub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VSSUB_VX vssub.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_WV vwaddu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADDU_WX vwaddu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_WV vwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWADD_WX vwadd.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_WV vwsubu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUBU_WX vwsubu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_WV vwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VWSUB_WX vwsub.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VWSUB_WX vwsub.wx v8, v16, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - SMTX100_BQ
+# CHECK-NEXT: [0.1] - SMTX100_BQ
+# CHECK-NEXT: [1.0] - SMTX100_FQ0
+# CHECK-NEXT: [1.1] - SMTX100_FQ0
+# CHECK-NEXT: [2.0] - SMTX100_FQ1
+# CHECK-NEXT: [2.1] - SMTX100_FQ1
+# CHECK-NEXT: [3.0] - SMTX100_IQ0
+# CHECK-NEXT: [3.1] - SMTX100_IQ0
+# CHECK-NEXT: [4.0] - SMTX100_IQ1
+# CHECK-NEXT: [4.1] - SMTX100_IQ1
+# CHECK-NEXT: [5.0] - SMTX100_LSQ
+# CHECK-NEXT: [5.1] - SMTX100_LSQ
+# CHECK-NEXT: [5.2] - SMTX100_LSQ
+# CHECK-NEXT: [5.3] - SMTX100_LSQ
+# CHECK-NEXT: [6] - SMTX100_VEU0
+# CHECK-NEXT: [7] - SMTX100_VEU1
+# CHECK-NEXT: [8] - SMTX100_VEU2
+# CHECK-NEXT: [9] - SMTX100_VEU3
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9]
+# CHECK-NEXT: - - - - - - 560.00 560.00 - - - - - - 2743.00 1233.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vadd.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vsub.vv v8, v8, v8
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+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwadd.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwadd.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsubu.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsubu.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vwsub.wx v8, v16, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vwsub.wx v8, v16, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/bitwise.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/bitwise.test
new file mode 100644
index 0000000000000..c92da333eb207
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/bitwise.test
@@ -0,0 +1,2891 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/bitwise.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMTX100_BQ:2
+# CHECK-NEXT: [1] - SMTX100_FQ:4 SMTX100_FQ0, SMTX100_FQ0, SMTX100_FQ1, SMTX100_FQ1
+# CHECK-NEXT: [2] - SMTX100_FQ0:2
+# CHECK-NEXT: [3] - SMTX100_FQ1:2
+# CHECK-NEXT: [4] - SMTX100_IQ:4 SMTX100_IQ0, SMTX100_IQ0, SMTX100_IQ1, SMTX100_IQ1
+# CHECK-NEXT: [5] - SMTX100_IQ0:2
+# CHECK-NEXT: [6] - SMTX100_IQ1:2
+# CHECK-NEXT: [7] - SMTX100_LSQ:4
+# CHECK-NEXT: [8] - SMTX100_VEU0:1
+# CHECK-NEXT: [9] - SMTX100_VEU1:1
+# CHECK-NEXT: [10] - SMTX100_VEU2:1
+# CHECK-NEXT: [11] - SMTX100_VEU3:1
+# CHECK-NEXT: [12] - SMTX100_VFPU:2 SMTX100_VEU0, SMTX100_VEU1
+# CHECK-NEXT: [13] - SMTX100_VIEU:2 SMTX100_VEU0, SMTX100_VEU1
+# CHECK-NEXT: [14] - SMTX100_VLSU:2 SMTX100_VEU2, SMTX100_VEU3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VV vand.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VX vand.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VAND_VI vand.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VV vor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VX vor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VOR_VI vor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VV vxor.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VX vxor.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VXOR_VI vxor.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRA_WV vnsra.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRA_WX vnsra.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRA_WI vnsra.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRL_WV vnsrl.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRL_WX vnsrl.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNSRL_WI vnsrl.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIPU_WI vnclipu.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIPU_WV vnclipu.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIPU_WX vnclipu.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIP_WI vnclip.wi v8, v16, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIP_WV vnclip.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VNCLIP_WX vnclip.wx v8, v16, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VI vsll.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VV vsll.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSLL_VX vsll.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VI vsra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VV vsra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRA_VX vsra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VI vsrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VV vsrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSRL_VX vsrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VI vssra.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VV vssra.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRA_VX vssra.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VI vssrl.vi v8, v8, 12
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VV vssrl.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VSSRL_VX vssrl.vx v8, v8, t5
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VSSRL_VX vssrl.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - SMTX100_BQ
+# CHECK-NEXT: [0.1] - SMTX100_BQ
+# CHECK-NEXT: [1.0] - SMTX100_FQ0
+# CHECK-NEXT: [1.1] - SMTX100_FQ0
+# CHECK-NEXT: [2.0] - SMTX100_FQ1
+# CHECK-NEXT: [2.1] - SMTX100_FQ1
+# CHECK-NEXT: [3.0] - SMTX100_IQ0
+# CHECK-NEXT: [3.1] - SMTX100_IQ0
+# CHECK-NEXT: [4.0] - SMTX100_IQ1
+# CHECK-NEXT: [4.1] - SMTX100_IQ1
+# CHECK-NEXT: [5.0] - SMTX100_LSQ
+# CHECK-NEXT: [5.1] - SMTX100_LSQ
+# CHECK-NEXT: [5.2] - SMTX100_LSQ
+# CHECK-NEXT: [5.3] - SMTX100_LSQ
+# CHECK-NEXT: [6] - SMTX100_VEU0
+# CHECK-NEXT: [7] - SMTX100_VEU1
+# CHECK-NEXT: [8] - SMTX100_VEU2
+# CHECK-NEXT: [9] - SMTX100_VEU3
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9]
+# CHECK-NEXT: - - - - - - 354.00 354.00 - - - - - - 3303.00 297.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vand.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 2.00 - - vand.vv v8, v8, v8
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+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vi v8, v8, 12
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 - - - vssrl.vx v8, v8, t5
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 16.00 - - - vssrl.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/comparison.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/comparison.test
new file mode 100644
index 0000000000000..2c8c2469e3571
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/comparison.test
@@ -0,0 +1,1802 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/comparison.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VV vmseq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VX vmseq.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSEQ_VI vmseq.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VV vmsle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VX vmsle.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLE_VI vmsle.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VV vmsleu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VX vmsleu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLEU_VI vmsleu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VV vmsne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VX vmsne.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSNE_VI vmsne.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGTU_VI vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGTU_VX vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGT_VI vmsgt.vi v8, v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSGT_VX vmsgt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLTU_VV vmsltu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLTU_VX vmsltu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLT_VV vmslt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VIEU[4] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 8.00 10 SMX60_VIEU[8] VMSLT_VX vmslt.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 18.00 18 SMX60_VIEU[18] VMSLT_VX vmslt.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 440.00 - - - - 2680.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmseq.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsle.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsleu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsne.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgtu.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgtu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgt.vi v8, v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsgt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsltu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmsltu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmslt.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmslt.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 18.00 - vmslt.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/conversion.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/conversion.test
new file mode 100644
index 0000000000000..33adbb90048db
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/conversion.test
@@ -0,0 +1,1166 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/conversion.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSEXT_VF2 vsext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VZEXT_VF2 vzext.vf2 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSEXT_VF4 vsext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VZEXT_VF4 vzext.vf4 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSEXT_VF8 vsext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VZEXT_VF8 vzext.vf8 v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_F_XU_V vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_F_X_V vfcvt.f.x.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_X_F_V vfcvt.x.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFCVT_XU_F_V vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_F_F_W vfncvt.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_F_XU_W vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_F_X_W vfncvt.f.x.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_X_F_W vfncvt.x.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFNCVT_XU_F_W vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_F_F_V vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_F_X_V vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_F_XU_V vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_X_F_V vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFWCVT_XU_F_V vfwcvt.xu.f.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 281.00 - - - 1473.00 368.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vzext.vf2 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vsext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vsext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vzext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vzext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vzext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vzext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vzext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vzext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vzext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vzext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vzext.vf4 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vsext.vf8 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsext.vf8 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsext.vf8 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsext.vf8 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vzext.vf8 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vzext.vf8 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vzext.vf8 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vzext.vf8 v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.f.xu.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.f.x.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.rtz.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.rtz.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.x.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfcvt.xu.f.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfncvt.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.f.xu.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.f.x.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfncvt.f.x.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.f.x.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.f.x.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.f.x.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.f.x.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.f.x.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.f.x.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.f.x.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.rod.f.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.rtz.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.rtz.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfncvt.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.x.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfncvt.xu.f.w v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.f.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.f.x.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.f.xu.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.rtz.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.rtz.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.x.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwcvt.xu.f.v v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwcvt.xu.f.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/fma.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/fma.test
new file mode 100644
index 0000000000000..af7fa7aa3fcfc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/fma.test
@@ -0,0 +1,1454 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fma.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMACC_VV vmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMACC_VX vmacc.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMADD_VV vmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMADD_VX vmadd.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSAC_VV vnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSAC_VX vnmsac.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSUB_VV vnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VNMSUB_VX vnmsub.vx v8, s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCU_VV vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCU_VX vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACC_VV vwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACC_VX vwmacc.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCSU_VV vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCSU_VX vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMACCUS_VX vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWMACC_VF vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWMACC_VV vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWMSAC_VF vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWMSAC_VV vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWNMACC_VF vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWNMACC_VV vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWNMSAC_VF vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VFP VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VFP[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VFP[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 1.00 6 SMX60_VFP VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VFP[2] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 4.00 6 SMX60_VFP[4] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 7 8.00 7 SMX60_VFP[8] VFWNMSAC_VV vfwnmsac.vv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 353.00 - - - 248.00 864.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmacc.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmacc.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmadd.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmadd.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsac.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsac.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsub.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vnmsub.vx v8, s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmacc.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccsu.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmaccus.vx v8, a6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwnmacc.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwnmacc.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwnmsac.vf v8, fa6, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfwnmsac.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfwnmsac.vv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/fp.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/fp.test
new file mode 100644
index 0000000000000..cc58a9bec9581
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/fp.test
@@ -0,0 +1,3719 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fp.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMTX100_BQ:2
+# CHECK-NEXT: [1] - SMTX100_FQ:4 SMTX100_FQ0, SMTX100_FQ0, SMTX100_FQ1, SMTX100_FQ1
+# CHECK-NEXT: [2] - SMTX100_FQ0:2
+# CHECK-NEXT: [3] - SMTX100_FQ1:2
+# CHECK-NEXT: [4] - SMTX100_IQ:4 SMTX100_IQ0, SMTX100_IQ0, SMTX100_IQ1, SMTX100_IQ1
+# CHECK-NEXT: [5] - SMTX100_IQ0:2
+# CHECK-NEXT: [6] - SMTX100_IQ1:2
+# CHECK-NEXT: [7] - SMTX100_LSQ:4
+# CHECK-NEXT: [8] - SMTX100_VEU0:1
+# CHECK-NEXT: [9] - SMTX100_VEU1:1
+# CHECK-NEXT: [10] - SMTX100_VEU2:1
+# CHECK-NEXT: [11] - SMTX100_VEU3:1
+# CHECK-NEXT: [12] - SMTX100_VFPU:2 SMTX100_VEU0, SMTX100_VEU1
+# CHECK-NEXT: [13] - SMTX100_VIEU:2 SMTX100_VEU0, SMTX100_VEU1
+# CHECK-NEXT: [14] - SMTX100_VLSU:2 SMTX100_VEU2, SMTX100_VEU3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFEQ_VF vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFEQ_VV vmfeq.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFGE_VF vmfge.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFGT_VF vmfgt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLE_VF vmfle.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLE_VV vmfle.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLT_VF vmflt.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFLT_VV vmflt.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFNE_VF vmfne.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 1.50 6 SMTX100_VFPU[3],SMTX100_VIEU[3] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 10 2.50 10 SMTX100_VFPU[5],SMTX100_VIEU[5] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 18 9.00 18 SMTX100_VFPU[18],SMTX100_VIEU[18] VMFNE_VV vmfne.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFADD_VV vfadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFADD_VF vfadd.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFSUB_VV vfsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFSUB_VF vfsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFCLASS_V vfclass.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 28 SMTX100_VEU0[28],SMTX100_VFPU[28],SMTX100_VIEU[28] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 28 SMTX100_VEU0[28],SMTX100_VFPU[28],SMTX100_VIEU[28] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 28 SMTX100_VEU0[28],SMTX100_VFPU[28],SMTX100_VIEU[28] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 56 56.00 56 SMTX100_VEU0[56],SMTX100_VFPU[56],SMTX100_VIEU[56] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 112 112.00 112 SMTX100_VEU0[112],SMTX100_VFPU[112],SMTX100_VIEU[112] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 224 224.00 224 SMTX100_VEU0[224],SMTX100_VFPU[224],SMTX100_VIEU[224] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 36 36.00 36 SMTX100_VEU0[36],SMTX100_VFPU[36],SMTX100_VIEU[36] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 36 36.00 36 SMTX100_VEU0[36],SMTX100_VFPU[36],SMTX100_VIEU[36] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 72 72.00 72 SMTX100_VEU0[72],SMTX100_VFPU[72],SMTX100_VIEU[72] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 144 144.00 144 SMTX100_VEU0[144],SMTX100_VFPU[144],SMTX100_VIEU[144] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 288 288.00 288 SMTX100_VEU0[288],SMTX100_VFPU[288],SMTX100_VIEU[288] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 66 66.00 66 SMTX100_VEU0[66],SMTX100_VFPU[66],SMTX100_VIEU[66] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 132 132.00 132 SMTX100_VEU0[132],SMTX100_VFPU[132],SMTX100_VIEU[132] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 264 264.00 264 SMTX100_VEU0[264],SMTX100_VFPU[264],SMTX100_VIEU[264] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 528 528.00 528 SMTX100_VEU0[528],SMTX100_VFPU[528],SMTX100_VIEU[528] VFDIV_VV vfdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMTX100_VEU0[24],SMTX100_VFPU[24],SMTX100_VIEU[24] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMTX100_VEU0[24],SMTX100_VFPU[24],SMTX100_VIEU[24] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMTX100_VEU0[24],SMTX100_VFPU[24],SMTX100_VIEU[24] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMTX100_VEU0[24],SMTX100_VFPU[24],SMTX100_VIEU[24] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMTX100_VEU0[24],SMTX100_VFPU[24],SMTX100_VIEU[24] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMTX100_VEU0[12],SMTX100_VFPU[12],SMTX100_VIEU[12] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMTX100_VEU0[12],SMTX100_VFPU[12],SMTX100_VIEU[12] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMTX100_VEU0[12],SMTX100_VFPU[12],SMTX100_VIEU[12] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMTX100_VEU0[12],SMTX100_VFPU[12],SMTX100_VIEU[12] VFDIV_VF vfdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMAX_VV vfmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMAX_VF vfmax.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMIN_VV vfmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 0.50 3 SMTX100_VFPU,SMTX100_VIEU VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMIN_VF vfmin.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSAC_VV vfmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSAC_VF vfmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSUB_VV vfmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMSUB_VF vfmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMUL_VV vfmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMUL_VF vfmul.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMACC_VF vfmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMACC_VV vfmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMADD_VF vfmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFMADD_VV vfmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMTX100_VEU0[6],SMTX100_VFPU[6],SMTX100_VIEU[6] VFMV_F_S vfmv.f.s fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 3 3.00 3 SMTX100_VEU0[3],SMTX100_VFPU[3],SMTX100_VIEU[3] VFMV_S_F vfmv.s.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFMV_V_F vfmv.v.f v8, fs0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMACC_VF vfnmacc.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMACC_VV vfnmacc.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMADD_VF vfnmadd.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMADD_VV vfnmadd.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSAC_VF vfnmsac.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSAC_VV vfnmsac.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSUB_VF vfnmsub.vf v8, fs0, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 5 0.50 5 SMTX100_VFPU,SMTX100_VIEU VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFNMSUB_VV vfnmsub.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 14 14.00 14 SMTX100_VEU0[14],SMTX100_VFPU[14],SMTX100_VIEU[14] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMTX100_VEU0[24],SMTX100_VFPU[24],SMTX100_VIEU[24] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMTX100_VEU0[24],SMTX100_VFPU[24],SMTX100_VIEU[24] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMTX100_VEU0[24],SMTX100_VFPU[24],SMTX100_VIEU[24] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMTX100_VEU0[24],SMTX100_VFPU[24],SMTX100_VIEU[24] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMTX100_VEU0[24],SMTX100_VFPU[24],SMTX100_VIEU[24] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMTX100_VEU0[12],SMTX100_VFPU[12],SMTX100_VIEU[12] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMTX100_VEU0[12],SMTX100_VFPU[12],SMTX100_VIEU[12] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMTX100_VEU0[12],SMTX100_VFPU[12],SMTX100_VIEU[12] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMTX100_VEU0[12],SMTX100_VFPU[12],SMTX100_VIEU[12] VFRDIV_VF vfrdiv.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFREC7_V vfrec7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFRSQRT7_V vfrsqrt7.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFRSUB_VF vfrsub.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 26 26.00 26 SMTX100_VEU0[26],SMTX100_VFPU[26],SMTX100_VIEU[26] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 26 26.00 26 SMTX100_VEU0[26],SMTX100_VFPU[26],SMTX100_VIEU[26] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 26 26.00 26 SMTX100_VEU0[26],SMTX100_VFPU[26],SMTX100_VIEU[26] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 52 52.00 52 SMTX100_VEU0[52],SMTX100_VFPU[52],SMTX100_VIEU[52] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 104 104.00 104 SMTX100_VEU0[104],SMTX100_VFPU[104],SMTX100_VIEU[104] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 208 208.00 208 SMTX100_VEU0[208],SMTX100_VFPU[208],SMTX100_VIEU[208] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMTX100_VEU0[35],SMTX100_VFPU[35],SMTX100_VIEU[35] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMTX100_VEU0[35],SMTX100_VFPU[35],SMTX100_VIEU[35] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 70 70.00 70 SMTX100_VEU0[70],SMTX100_VFPU[70],SMTX100_VIEU[70] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 140 140.00 140 SMTX100_VEU0[140],SMTX100_VFPU[140],SMTX100_VIEU[140] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 280 280.00 280 SMTX100_VEU0[280],SMTX100_VFPU[280],SMTX100_VIEU[280] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 52 52.00 52 SMTX100_VEU0[52],SMTX100_VFPU[52],SMTX100_VIEU[52] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 104 104.00 104 SMTX100_VEU0[104],SMTX100_VFPU[104],SMTX100_VIEU[104] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 208 208.00 208 SMTX100_VEU0[208],SMTX100_VFPU[208],SMTX100_VIEU[208] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 416 416.00 416 SMTX100_VEU0[416],SMTX100_VFPU[416],SMTX100_VIEU[416] VFSQRT_V vfsqrt.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJN_VF vfsgnjn.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJN_VV vfneg.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJ_VF vfsgnj.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJ_VV vfsgnj.vv v8, v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJX_VF vfsgnjx.vf v8, v8, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 3 1.00 3 SMTX100_VEU0,SMTX100_VFPU,SMTX100_VIEU VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 3 2.00 3 SMTX100_VEU0[2],SMTX100_VFPU[2],SMTX100_VIEU[2] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMTX100_VEU0[4],SMTX100_VFPU[4],SMTX100_VIEU[4] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMTX100_VEU0[8],SMTX100_VFPU[8],SMTX100_VIEU[8] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMTX100_VEU0[16],SMTX100_VFPU[16],SMTX100_VIEU[16] VFSGNJX_VV vfabs.v v8, v8
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWADD_VF vfwadd.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWADD_VV vfwadd.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWADD_WF vfwadd.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWADD_WV vfwadd.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWMUL_VF vfwmul.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.50 4 SMTX100_VFPU,SMTX100_VIEU VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWMUL_VV vfwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWSUB_VF vfwsub.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWSUB_VV vfwsub.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWSUB_WF vfwsub.wf v8, v16, ft0
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMTX100_VFPU[2],SMTX100_VIEU[2] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMTX100_VFPU[4],SMTX100_VIEU[4] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 SMTX100_VFPU[8],SMTX100_VIEU[8] VFWSUB_WV vfwsub.wv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 1 SMTX100_IQ,SMTX100_IQ0 VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 SMTX100_VFPU[16],SMTX100_VIEU[16] VFWSUB_WV vfwsub.wv v8, v16, v24
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - SMTX100_BQ
+# CHECK-NEXT: [0.1] - SMTX100_BQ
+# CHECK-NEXT: [1.0] - SMTX100_FQ0
+# CHECK-NEXT: [1.1] - SMTX100_FQ0
+# CHECK-NEXT: [2.0] - SMTX100_FQ1
+# CHECK-NEXT: [2.1] - SMTX100_FQ1
+# CHECK-NEXT: [3.0] - SMTX100_IQ0
+# CHECK-NEXT: [3.1] - SMTX100_IQ0
+# CHECK-NEXT: [4.0] - SMTX100_IQ1
+# CHECK-NEXT: [4.1] - SMTX100_IQ1
+# CHECK-NEXT: [5.0] - SMTX100_LSQ
+# CHECK-NEXT: [5.1] - SMTX100_LSQ
+# CHECK-NEXT: [5.2] - SMTX100_LSQ
+# CHECK-NEXT: [5.3] - SMTX100_LSQ
+# CHECK-NEXT: [6] - SMTX100_VEU0
+# CHECK-NEXT: [7] - SMTX100_VEU1
+# CHECK-NEXT: [8] - SMTX100_VEU2
+# CHECK-NEXT: [9] - SMTX100_VEU3
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9]
+# CHECK-NEXT: - - - - - - 457.50 457.50 - - - - - - 6844.00 1451.00 - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1.0] [1.1] [2.0] [2.1] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] [5.3] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.50 1.50 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.50 2.50 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 9.00 9.00 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.50 1.50 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.50 2.50 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 9.00 9.00 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.50 1.50 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.50 2.50 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 9.00 9.00 - - vmfeq.vf v8, v8, ft0
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 1.00 - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.50 1.50 - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 2.50 2.50 - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 9.00 9.00 - - vmfeq.vv v8, v8, v8
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 0.50 0.50 - - vmfeq.vv v8, v8, v8
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+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 4.00 4.00 - - vfwsub.wv v8, v16, v24
+# CHECK-NEXT: - - - - - - 0.50 0.50 - - - - - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - - - 8.00 8.00 - - vfwsub.wv v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/mask.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/mask.test
new file mode 100644
index 0000000000000..0ddc8a7d3d946
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/mask.test
@@ -0,0 +1,1246 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mask.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAND_MM vmand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNAND_MM vmnand.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMANDN_MM vmandn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXOR_MM vmxor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMOR_MM vmor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMNOR_MM vmnor.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMORN_MM vmorn.mm v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMXNOR_MM vmxnor.mm v7, v8, v9
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSBF_M vmsbf.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSIF_M vmsif.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMSOF_M vmsof.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VID_V vid.v v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VCPOP_M vcpop.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 2.00 6 SMX60_VIEU[2] VFIRST_M vfirst.m s0, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 301.00 - - - - 490.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnand.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmandn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmnor.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmorn.mm v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmxnor.mm v7, v8, v9
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsbf.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsif.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmsof.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vid.v v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vcpop.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vfirst.m s0, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/minmax.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/minmax.test
new file mode 100644
index 0000000000000..69ba85bd56719
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/minmax.test
@@ -0,0 +1,746 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/minmax.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAX_VV vmax.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAX_VX vmax.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAXU_VV vmaxu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMAXU_VX vmaxu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMIN_VV vmin.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMIN_VX vmin.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMINU_VV vminu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VMINU_VX vminu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMINU_VX vminu.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 176.00 - - - - 528.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmax.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmax.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmaxu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmaxu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmin.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmin.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vminu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vminu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vminu.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/mul-div.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/mul-div.test
new file mode 100644
index 0000000000000..328238da8c1e3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/mul-div.test
@@ -0,0 +1,1986 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mul-div.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMUL_VV vmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMUL_VX vmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIV_VV vdiv.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIV_VX vdiv.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIVU_VV vdivu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VDIVU_VX vdivu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREM_VV vrem.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREM_VX vrem.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREMU_VV vremu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 12 SMX60_VIEU[12] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 24 SMX60_VIEU[24] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 48 SMX60_VIEU[48] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VIEU[96] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VIEU[192] VREMU_VX vremu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULH_VV vmulh.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULH_VX vmulh.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHU_VV vmulhu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHU_VX vmulhu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHSU_VV vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 2.00 8 SMX60_VIEU[2] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 4.00 16 SMX60_VIEU[4] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 8.00 32 SMX60_VIEU[8] VMULHSU_VX vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMUL_VV vwmul.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMUL_VX vwmul.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULU_VV vwmulu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULU_VX vwmulu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULSU_VV vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 4.00 5 SMX60_VIEU[4] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VWMULSU_VX vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VV vsmul.vv v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 7 1.00 7 SMX60_VIEU VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 4.00 7 SMX60_VIEU[4] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSMUL_VX vsmul.vx v8, v8, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VSMUL_VX vsmul.vx v8, v8, t5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 486.00 - - - - 13404.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdiv.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdiv.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdivu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vdivu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vrem.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vrem.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vremu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 12.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 24.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 48.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 96.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 192.00 - vremu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulh.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulh.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhsu.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmulhsu.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmul.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmul.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulsu.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vwmulsu.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 32.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 32.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 32.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 32.00 - vsmul.vv v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 32.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 32.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 32.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vsmul.vx v8, v8, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 32.00 - vsmul.vx v8, v8, t5
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/permutation.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/permutation.test
new file mode 100644
index 0000000000000..243045e25e85b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/permutation.test
@@ -0,0 +1,2330 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/permutation.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_V vmv.v.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_X vmv.v.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV_V_I vmv.v.i v8, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 6 6.00 6 SMX60_VIEU[6] VMV_X_S vmv.x.s s0, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV_S_X vmv.s.x v8, s0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV1R_V vmv1r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMV2R_V vmv2r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMV4R_V vmv4r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMV8R_V vmv8r.v v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VIOTA_M viota.m v8, v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SMX60_VIEU[10] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 36 36.00 36 SMX60_VIEU[36] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 136 136.00 136 SMX60_VIEU[136] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SMX60_VIEU[10] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 36 36.00 36 SMX60_VIEU[36] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 136 136.00 136 SMX60_VIEU[136] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SMX60_VIEU[10] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 36 36.00 36 SMX60_VIEU[36] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 136 136.00 136 SMX60_VIEU[136] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 10 10.00 10 SMX60_VIEU[10] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 36 36.00 36 SMX60_VIEU[36] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 136 136.00 136 SMX60_VIEU[136] VCOMPRESS_VM vcompress.vm v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDE1UP_VX vslide1up.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDE1DOWN_VX vslide1down.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VSLIDEUP_VX vslideup.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEUP_VI vslideup.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEDOWN_VX vslidedown.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VIEU[3] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VIEU[5] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VIEU[9] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VIEU[17] VSLIDEDOWN_VI vslidedown.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 64 SMX60_VIEU[64] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 256 256.00 256 SMX60_VIEU[256] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 64 SMX60_VIEU[64] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 256 256.00 256 SMX60_VIEU[256] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 64 SMX60_VIEU[64] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 256 256.00 256 SMX60_VIEU[256] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 64 SMX60_VIEU[64] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 256 256.00 256 SMX60_VIEU[256] VRGATHER_VV vrgather.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VX vrgather.vx v8, v16, t5
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHER_VI vrgather.vi v8, v16, 12
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 32 SMX60_VIEU[32] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 128.00 128 SMX60_VIEU[128] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 64 SMX60_VIEU[64] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 256 256.00 256 SMX60_VIEU[256] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 64 SMX60_VIEU[64] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 256 256.00 256 SMX60_VIEU[256] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 64 SMX60_VIEU[64] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 256 256.00 256 SMX60_VIEU[256] VRGATHEREI16_VV vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VIM vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VVM vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VIEU VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VIEU[2] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VIEU[4] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VIEU[8] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VIEU[16] VMERGE_VXM vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 SMX60_VFP[2] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 SMX60_VFP[4] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 8.00 8 SMX60_VFP[8] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 16 16.00 16 SMX60_VFP[16] VFMERGE_VFM vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VFP[3] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VFP[5] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VFP[9] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VFP[17] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VFP[3] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VFP[5] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VFP[9] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VFP[17] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VFP[3] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VFP[5] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VFP[9] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VFP[17] VFSLIDE1DOWN_VF vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VFP[3] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VFP[5] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VFP[9] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VFP[17] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 SMX60_VFP VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VFP[3] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VFP[5] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VFP[9] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VFP[17] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 3.00 4 SMX60_VFP[3] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 5 5.00 5 SMX60_VFP[5] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 9 9.00 9 SMX60_VFP[9] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 17 17.00 17 SMX60_VFP[17] VFSLIDE1UP_VF vfslide1up.vf v8, v16, ft0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 572.00 - - - 303.00 6201.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv.v.i v8, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 6.00 - vmv.x.s s0, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv.s.x v8, s0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv1r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmv2r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmv4r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmv8r.v v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - viota.m v8, v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 36.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 136.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 36.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 136.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 36.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 136.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 36.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 136.00 - vcompress.vm v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslide1up.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslide1down.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vslideup.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslideup.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslidedown.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 3.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 5.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 9.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 17.00 - vslidedown.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 64.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 256.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 64.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 256.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 64.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 256.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 64.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 256.00 - vrgather.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vx v8, v16, t5
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgather.vi v8, v16, 12
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 32.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 128.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 64.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 256.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 64.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 256.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 64.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 256.00 - vrgatherei16.vv v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vim v8, v8, 12, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vvm v8, v8, v8, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 8.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 16.00 - vmerge.vxm v8, v8, t5, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 2.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 4.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfmerge.vfm v8, v8, ft0, v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 3.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 5.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 9.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 17.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 3.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 5.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 9.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 17.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 3.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 5.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 9.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 17.00 - - vfslide1down.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 3.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 5.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 9.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 17.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 3.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 5.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 9.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 17.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 3.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 5.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 9.00 - - vfslide1up.vf v8, v16, ft0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 17.00 - - vfslide1up.vf v8, v16, ft0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/reduction.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/reduction.test
new file mode 100644
index 0000000000000..c6bd0c911ce59
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/reduction.test
@@ -0,0 +1,1218 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/reduction.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDAND_VS vredand.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAXU_VS vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMAX_VS vredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMINU_VS vredminu.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDMIN_VS vredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDOR_VS vredor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDSUM_VS vredsum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VREDXOR_VS vredxor.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUMU_VS vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 5 1.00 5 SMX60_VIEU VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.00 5 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 7 2.00 7 SMX60_VIEU[2] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 11 4.00 11 SMX60_VIEU[4] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 19 10.00 19 SMX60_VIEU[10] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 35 35.00 35 SMX60_VIEU[35] VWREDSUM_VS vwredsum.vs v8, v16, v24
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMAX_VS vfredmax.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDMIN_VS vfredmin.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 20.00 24 SMX60_VFP[20] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 SMX60_VFP[24] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 96 48.00 96 SMX60_VFP[48] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 192 96.00 192 SMX60_VFP[96] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 384 384.00 384 SMX60_VFP[384] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 12.00 24 SMX60_VFP[12] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 SMX60_VFP[24] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 96 48.00 96 SMX60_VFP[48] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 192 192.00 192 SMX60_VFP[192] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 SMX60_VFP[6] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 12.00 24 SMX60_VFP[12] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 SMX60_VFP[24] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 96 96.00 96 SMX60_VFP[96] VFREDOSUM_VS vfredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 8.00 12 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 15 8.00 15 SMX60_VFP[8] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 21 14.00 21 SMX60_VFP[14] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 33 20.00 33 SMX60_VFP[20] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 57 57.00 57 SMX60_VFP[57] VFREDUSUM_VS vfredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 27.00 32 SMX60_VFP[27] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 11.00 16 SMX60_VFP[11] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 32.00 64 SMX60_VFP[32] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 64.00 128 SMX60_VFP[64] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 256 128.00 256 SMX60_VFP[128] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 512 512.00 512 SMX60_VFP[512] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 11.00 16 SMX60_VFP[11] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 16.00 32 SMX60_VFP[16] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 32.00 64 SMX60_VFP[32] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 128 64.00 128 SMX60_VFP[64] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 256 256.00 256 SMX60_VFP[256] VFWREDOSUM_VS vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 27.00 32 SMX60_VFP[27] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 11.00 16 SMX60_VFP[11] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 32.00 64 SMX60_VFP[32] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 64.00 128 SMX60_VFP[64] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 256 128.00 256 SMX60_VFP[128] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 512 512.00 512 SMX60_VFP[512] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 11.00 16 SMX60_VFP[11] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 16.00 32 SMX60_VFP[16] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 32.00 64 SMX60_VFP[32] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 128 64.00 128 SMX60_VFP[64] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 256 256.00 256 SMX60_VFP[256] VFWREDUSUM_VS vfwredusum.vs v8, v8, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 294.00 - - - 4271.00 2028.00 -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredand.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmaxu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredminu.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredsum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vredxor.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vwredsumu.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 2.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 4.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 10.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 35.00 - vwredsum.vs v8, v16, v24
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 14.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 20.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 57.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 14.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 20.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 57.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 14.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 20.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 57.00 - - vfredmax.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 14.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 20.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 57.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 14.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 20.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 57.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 14.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 20.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 57.00 - - vfredmin.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 20.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 24.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 48.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 96.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 384.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 12.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 24.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 48.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 192.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 6.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 12.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 24.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 96.00 - - vfredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 14.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 20.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 57.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 14.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 20.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 57.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 8.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 14.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 20.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 57.00 - - vfredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 27.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 11.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 32.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 64.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 128.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 512.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 11.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 32.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 64.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 256.00 - - vfwredosum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - 27.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - 11.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 32.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 64.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 128.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 512.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - 11.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 16.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 32.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 64.00 - - vfwredusum.vs v8, v8, v8
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli t3, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 256.00 - - vfwredusum.vs v8, v8, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vle-vse-vlm.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vle-vse-vlm.test
new file mode 100644
index 0000000000000..a0752b10aa587
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vle-vse-vlm.test
@@ -0,0 +1,362 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vle-vse-vlm.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 19 19.00 * 19 SMX60_VLS[19] VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 19 19.00 * 19 SMX60_VLS[19] VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 19 19.00 * 19 SMX60_VLS[19] VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 3 3.00 * 3 SMX60_VLS[3] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 19 19.00 * 19 SMX60_VLS[19] VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 SMX60_VLS[2] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 SMX60_VLS[2] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 SMX60_VLS[2] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 SMX60_VLS[2] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 SMX60_VLS[2] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 SMX60_VLS[2] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 2.00 * 1 SMX60_VLS[2] VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 5 5.00 * 5 SMX60_VLS[5] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 7 7.00 * 7 SMX60_VLS[7] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 11 11.00 * 11 SMX60_VLS[11] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 19 19.00 * 19 SMX60_VLS[19] VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 5 5.00 * 5 SMX60_VLS[5] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 7 7.00 * 7 SMX60_VLS[7] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 11 11.00 * 11 SMX60_VLS[11] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 19 19.00 * 19 SMX60_VLS[19] VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 5 5.00 * 5 SMX60_VLS[5] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 7 7.00 * 7 SMX60_VLS[7] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 11 11.00 * 11 SMX60_VLS[11] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 19 19.00 * 19 SMX60_VLS[19] VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 5 5.00 * 5 SMX60_VLS[5] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 7 7.00 * 7 SMX60_VLS[7] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 11 11.00 * 11 SMX60_VLS[11] VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 19 19.00 * 19 SMX60_VLS[19] VLE64FF_V vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 80.00 - - - - - 510.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vle8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vle8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vle8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vle8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vle8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vle8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vle8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vle16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vle16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vle16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vle16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vle16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vle16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vle32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vle32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vle32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vle32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vle32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vle64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vle64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vle64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vle64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vse8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vse8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vse8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vse8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vse8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vse8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 19.00 vse8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vse16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vse16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vse16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vse16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vse16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 19.00 vse16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vse32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vse32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vse32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vse32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 19.00 vse32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 3.00 vse64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vse64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vse64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 19.00 vse64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vlm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vlm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vlm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vlm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vlm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vlm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vlm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsm.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vle8ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vle8ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vle8ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 5.00 vle8ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 7.00 vle8ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 11.00 vle8ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 19.00 vle8ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vle16ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vle16ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 5.00 vle16ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 7.00 vle16ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 11.00 vle16ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 19.00 vle16ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vle32ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 5.00 vle32ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 7.00 vle32ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 11.00 vle32ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 19.00 vle32ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 5.00 vle64ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 7.00 vle64ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 11.00 vle64ff.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 19.00 vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlse-vsse.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlse-vsse.test
new file mode 100644
index 0000000000000..37ed3dd247608
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlse-vsse.test
@@ -0,0 +1,218 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlse-vsse.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSE64_V vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 44.00 - - - - - 1888.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vlse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vlse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vlse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vlse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vlse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 128.00 vlse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 256.00 vlse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vlse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vlse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vlse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vlse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vlse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 128.00 vlse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vlse32.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vlse32.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vlse32.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vlse32.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vlse32.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vlse64.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vlse64.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vlse64.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vlse64.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 128.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 256.00 vsse8.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 128.00 vsse16.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vsse32.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsse64.v v8, (a0), t0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlseg-vsseg.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlseg-vsseg.test
new file mode 100644
index 0000000000000..b8e92a7a7c2a7
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlseg-vsseg.test
@@ -0,0 +1,3122 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlseg-vsseg.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 160 160.00 * 160 SMX60_VLS[160] VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSEG5E64_V vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG6E64_V vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 224 224.00 * 224 SMX60_VLS[224] VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSEG7E64_V vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG8E64_V vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 160 160.00 * 160 SMX60_VLS[160] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSSEG5E64_V vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSEG6E64_V vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 224 224.00 * 224 SMX60_VLS[224] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSSEG7E64_V vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSEG8E64_V vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 160 160.00 * 160 SMX60_VLS[160] VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSSEG5E64_V vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSSEG6E64_V vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 224 224.00 * 224 SMX60_VLS[224] VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSSEG7E64_V vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSSEG8E64_V vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 160 160.00 * 160 SMX60_VLS[160] VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSSSEG5E64_V vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSSSEG6E64_V vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 224 224.00 * 224 SMX60_VLS[224] VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSSSEG7E64_V vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSSSEG8E64_V vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 160 160.00 * 160 SMX60_VLS[160] VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLSEG5E64FF_V vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLSEG6E64FF_V vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 224 224.00 * 224 SMX60_VLS[224] VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLSEG7E64FF_V vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLSEG8E64FF_V vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 160 160.00 * 160 SMX60_VLS[160] VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLUXSEG5EI64_V vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLUXSEG6EI64_V vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 224 224.00 * 224 SMX60_VLS[224] VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLUXSEG7EI64_V vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXSEG8EI64_V vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 160 160.00 * 160 SMX60_VLS[160] VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VLOXSEG5EI64_V vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VLOXSEG6EI64_V vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 224 224.00 * 224 SMX60_VLS[224] VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VLOXSEG7EI64_V vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXSEG8EI64_V vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 160 160.00 * 160 SMX60_VLS[160] VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSUXSEG5EI64_V vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSUXSEG6EI64_V vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 224 224.00 * 224 SMX60_VLS[224] VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSUXSEG7EI64_V vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXSEG8EI64_V vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 12 12.00 * 12 SMX60_VLS[12] VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 160 160.00 * 160 SMX60_VLS[160] VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 80 80.00 * 80 SMX60_VLS[80] VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 40 40.00 * 40 SMX60_VLS[40] VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 20 20.00 * 20 SMX60_VLS[20] VSOXSEG5EI64_V vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 192 192.00 * 192 SMX60_VLS[192] VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 96 96.00 * 96 SMX60_VLS[96] VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 48 48.00 * 48 SMX60_VLS[48] VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 24 24.00 * 24 SMX60_VLS[24] VSOXSEG6EI64_V vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 224 224.00 * 224 SMX60_VLS[224] VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 112 112.00 * 112 SMX60_VLS[112] VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 56 56.00 * 56 SMX60_VLS[56] VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 28 28.00 * 28 SMX60_VLS[28] VSOXSEG7EI64_V vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 256 256.00 * 256 SMX60_VLS[256] VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXSEG8EI64_V vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 770.00 - - - - - 46320.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 8.00 vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 16.00 vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 64.00 vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 128.00 vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 256.00 vlseg2e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 8.00 vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 16.00 vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 64.00 vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 128.00 vlseg2e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 8.00 vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 16.00 vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 64.00 vlseg2e32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 8.00 vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 16.00 vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vlseg2e64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 12.00 vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 24.00 vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 48.00 vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 96.00 vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 192.00 vlseg3e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 12.00 vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 24.00 vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 48.00 vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 96.00 vlseg3e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 12.00 vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 24.00 vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 48.00 vlseg3e32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 12.00 vlseg3e64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 24.00 vlseg3e64.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 16.00 vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 64.00 vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 128.00 vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 256.00 vlseg4e8.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 16.00 vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 64.00 vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 128.00 vlseg4e16.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 16.00 vlseg4e32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vlseg4e32.v v8, (a0)
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 64.00 vlseg4e32.v v8, (a0)
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+# CHECK-NEXT: - - - - - - - 80.00 vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 20.00 vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 40.00 vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 20.00 vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 24.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 48.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 96.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 192.00 vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 24.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 48.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 96.00 vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 24.00 vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 48.00 vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 24.00 vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 28.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 56.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 112.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 224.00 vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 28.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 56.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 112.00 vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 28.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 56.00 vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 28.00 vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 64.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 128.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 256.00 vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 64.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 128.00 vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 64.00 vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 32.00 vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlxe-vsxe.test b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlxe-vsxe.test
new file mode 100644
index 0000000000000..35ff68ab9bf29
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SpacemitX100/rvv/vlxe-vsxe.test
@@ -0,0 +1,394 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=spacemit-x100 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlxe-vsxe.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP:1
+# CHECK-NEXT: [1] - SMX60_IEU:2 SMX60_IEUA, SMX60_IEUB
+# CHECK-NEXT: [2] - SMX60_IEUA:1
+# CHECK-NEXT: [3] - SMX60_IEUB:1
+# CHECK-NEXT: [4] - SMX60_LS:2
+# CHECK-NEXT: [5] - SMX60_VFP:1
+# CHECK-NEXT: [6] - SMX60_VIEU:1
+# CHECK-NEXT: [7] - SMX60_VLS:1
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 128 128.00 * 128 SMX60_VLS[128] VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 64 64.00 * 64 SMX60_VLS[64] VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 32 32.00 * 32 SMX60_VLS[32] VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 2.00 * 2 SMX60_VLS[2] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 4.00 * 4 SMX60_VLS[4] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 8.00 * 8 SMX60_VLS[8] VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 1.00 U 1 SMX60_IEU,SMX60_IEUA VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 16.00 * 16 SMX60_VLS[16] VSOXEI64_V vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - SMX60_FP
+# CHECK-NEXT: [1] - SMX60_IEUA
+# CHECK-NEXT: [2] - SMX60_IEUB
+# CHECK-NEXT: [3.0] - SMX60_LS
+# CHECK-NEXT: [3.1] - SMX60_LS
+# CHECK-NEXT: [4] - SMX60_VFP
+# CHECK-NEXT: [5] - SMX60_VIEU
+# CHECK-NEXT: [6] - SMX60_VLS
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6]
+# CHECK-NEXT: - 88.00 - - - - - 1888.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3.0] [3.1] [4] [5] [6] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 128.00 vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 128.00 vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 128.00 vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 128.00 vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 64.00 vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 32.00 vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 2.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - 4.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - 8.00 vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - 1.00 - - - - - - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - 16.00 vsoxei64.v v8, (a0), v0
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