[llvm] [RISCV] computeKnownBits - add support for RISCVISD::VECREDUCE_ADD_VL (PR #210493)

[Sabona Abdi via llvm-commits]

https://github.com/sabonaoabdi updated https://github.com/llvm/llvm-project/pull/210493

>From c03f88d62f28e1cdcb700a021917f08f79022ac9 Mon Sep 17 00:00:00 2001
From: sabonaoabdi <sabonaoabdi at gmail.com>
Date: Sat, 18 Jul 2026 01:45:43 -0500
Subject: [PATCH] [RISCV] Add computeKnownBits support for
 RISCVISD::VECREDUCE_ADD_VL

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 22 +++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 96b6f391863c4..806dc7f1d12b0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -24108,6 +24108,28 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
     Known.Zero.setBitsFrom(Known2.countMaxActiveBits());
     break;
   }
+  case RISCVISD::VECREDUCE_ADD_VL: {
+    SDValue Src = Op.getOperand(1);
+    SDValue InitVal = Op.getOperand(2);
+    SDValue VL = Op.getOperand(4);
+    unsigned NumElts;
+
+    if (isa<ConstantSDNode>(VL)) {
+      NumElts = VL->getAsZExtVal();
+    } else {
+      const RISCVSubtarget &SubTarget = DAG.getSubtarget<RISCVSubtarget>();
+      auto [Min, Max] = computeVLMAXBounds(Src.getSimpleValueType(), SubTarget);
+      NumElts = Max;
+    }
+
+    KnownBits KnownAcrossElts =
+        DAG.computeKnownBits(Src, APInt::getAllOnes(1), Depth + 1);
+    KnownBits VecSum = KnownAcrossElts.reduceAdd(NumElts);
+    KnownBits Start = DAG.computeKnownBits(InitVal, Depth + 1);
+
+    Known = KnownBits::add(Start, VecSum);
+    break;
+  }
   case RISCVISD::CZERO_EQZ:
   case RISCVISD::CZERO_NEZ:
     Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);