[llvm] [AMDGPU] Fix type of SIlds / AMDGPUISD::LDS node (PR #210340)

[Jay Foad via llvm-commits]

https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/210340

iPTR means i64 here, but this node operates on 32-bit LDS addresses.


>From 5d6e5451c0d2c0e7168cf9fffcc53fd58244b9e7 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Fri, 17 Jul 2026 14:48:55 +0100
Subject: [PATCH] [AMDGPU] Fix type of SIlds / AMDGPUISD::LDS node

iPTR means i64 here, but this node operates on 32-bit LDS addresses.
---
 llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp | 2 --
 llvm/lib/Target/AMDGPU/SIInstrInfo.td             | 2 +-
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
index 5b8ee5fbcf9dc..814cc811331b1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUSelectionDAGInfo.cpp
@@ -51,8 +51,6 @@ void AMDGPUSelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
   case AMDGPUISD::ELSE:
   case AMDGPUISD::LOOP:
     // operand #1 must have type i1, but has type i32/i64
-  case AMDGPUISD::LDS:
-    // result #0 must have type i64 (iPTR), but has type i32
     return;
   }
   SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 7be067c085b5f..714627bee2a2c 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -275,7 +275,7 @@ def SIpc_add_rel_offset64 : SDNode<"AMDGPUISD::PC_ADD_REL_OFFSET64",
 >;
 
 def SIlds : SDNode<"AMDGPUISD::LDS",
-  SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>]>
+  SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0,1>]>
 >;
 
 def SIload_d16_lo : SDNode<"AMDGPUISD::LOAD_D16_LO",