[llvm] [RISCV] Add scheduler definitions for XiangShan-KunMingHu (PR #148581)
Lin Wang via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 17 02:47:55 PDT 2026
https://github.com/MrLinWang updated https://github.com/llvm/llvm-project/pull/148581
>From 25a96f7568e8771bae335f96e73f5d21571d05dd Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Mon, 14 Jul 2025 15:01:35 +0700
Subject: [PATCH 01/10] [RISC-V] Add scheduler definitions for
XiangShan-KunMingHu
---
llvm/lib/Target/RISCV/RISCV.td | 1 +
llvm/lib/Target/RISCV/RISCVProcessors.td | 2 +-
.../RISCV/RISCVSchedXiangShanKunMingHu.td | 356 ++++++++++++++++++
3 files changed, 358 insertions(+), 1 deletion(-)
create mode 100644 llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index b24d8637cb27f..2ce3662c88020 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -66,6 +66,7 @@ include "RISCVSchedSyntacoreSCR345.td"
include "RISCVSchedSyntacoreSCR7.td"
include "RISCVSchedTTAscalonD8.td"
include "RISCVSchedXiangShanNanHu.td"
+include "RISCVSchedXiangShanKunMingHu.td"
//===----------------------------------------------------------------------===//
// RISC-V processors supported.
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index 838edf6c57250..fa86fa66101f2 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -628,7 +628,7 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
TuneShiftedZExtWFusion]>;
def XIANGSHAN_KUNMINGHU : RISCVProcessorModel<"xiangshan-kunminghu",
- NoSchedModel,
+ XiangShanKunMingHuModel,
!listconcat(RVA23S64Features,
[FeatureStdExtZacas,
FeatureStdExtZbc,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
new file mode 100644
index 0000000000000..06c2b8a0e4aa2
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -0,0 +1,356 @@
+//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// The XiangShan is a high-performance open-source RISC-V processor project
+// initiated by the Institute of Computing Technology(ICT), Chinese Academy of Sciences(CAS).
+// The KunMingHu architecture is its third-generation derivative,
+// developed by the Institute of Computing Technology, Chinese Academy of Sciences
+// and the Beijing Institute of Open Source Chip (BOSC),
+// with a focus on achieving higher performance.
+// Source: https://github.com/OpenXiangShan/XiangShan
+// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
+
+//===----------------------------------------------------------------------===//
+// KunMingHu core supports "RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh
+// _zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei"
+// then floating-point SEW can only be 64 and 32, not 16 and 8.
+//===----------------------------------------------------------------------===//
+
+def XiangShanKunMingHuModel : SchedMachineModel {
+ let IssueWidth = 6; // 6-way decode and dispatch
+ let MicroOpBufferSize = 256;
+ let LoopMicroOpBufferSize = 48; // Instruction queue size
+ let LoadLatency = 6;
+ let MispredictPenalty = 13; // Based on estimate of pipeline depth.
+ let CompleteModel = 0;
+ let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZkr, HasVInstructions,
+ HasVInstructionsI64];
+}
+
+let SchedModel = XiangShanKunMingHuModel in {
+// Define each kind of processor resource and number available.
+/// Pipline
+let BufferSize = 12 in {
+ // Integer
+ def XSPipeALU0 : ProcResource<1>; // ALU, MUL, BKU
+ def XSPipeALU1 : ProcResource<1>; // ALU, MUL, BKU
+ def XSPipeALU2 : ProcResource<1>; // ALU
+ def XSPipeALU3 : ProcResource<1>; // ALU
+
+ def XSPipeBJU0 : ProcResource<1>; // BRU, JMP
+ def XSPipeBJU1 : ProcResource<1>; // BRU, JMP
+ def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, I2V, CSR
+ def XSPipeDIV : ProcResource<1>; // DIV
+
+ // Floating-point
+ def XSPipeFEX0 : ProcResource<1>; // FALU, FMA
+ def XSPipeFEX1 : ProcResource<1>; // FCVT
+ def XSPipeFEX2 : ProcResource<1>; // FALU, FMA
+ def XSPipeFEX3 : ProcResource<1>; // FDIV
+}
+
+let BufferSize = 24 in {
+ // Load and store
+ def XSPipeLDU : ProcResource<3>; // LDU
+
+ def XSPipeSTA : ProcResource<2>; // STA
+ def XSPipeSTD : ProcResource<2>; // STD
+}
+
+def XSPipeGroupALU : ProcResGroup<[XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3]>;
+def XSPipeGroupMUL : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
+def XSPipeGroupBKU : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
+def XSPipeGroupBRU : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
+def XSPipeGroupJMP : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
+
+def XSPipeGroupFALU : ProcResGroup<[XSPipeFEX0, XSPipeFEX2]>;
+def XSPipeGroupFMA : ProcResGroup<[XSPipeFEX0, XSPipeFEX2]>;
+
+def XSPipeGroupSTU : ProcResGroup<[XSPipeSTA, XSPipeSTD]>;
+
+//===----------------------------------------------------------------------===//
+
+
+// Jump
+def : WriteRes<WriteJmp, [XSPipeGroupBRU]>;
+def : WriteRes<WriteJal, [XSPipeGroupJMP]>;
+def : WriteRes<WriteJalr, [XSPipeGroupJMP]>;
+
+// Integer arithmetic and logic
+def : WriteRes<WriteIALU32, [XSPipeGroupALU]>;
+def : WriteRes<WriteIALU, [XSPipeGroupALU]>;
+def : WriteRes<WriteShiftImm32, [XSPipeGroupALU]>;
+def : WriteRes<WriteShiftImm, [XSPipeGroupALU]>;
+def : WriteRes<WriteShiftReg32, [XSPipeGroupALU]>;
+def : WriteRes<WriteShiftReg, [XSPipeGroupALU]>;
+
+// Integer multiplication
+let Latency = 2 in {
+ def : WriteRes<WriteIMul, [XSPipeGroupMUL]>;
+ def : WriteRes<WriteIMul32, [XSPipeGroupMUL]>;
+}
+
+// Integer division
+// Worst case latency is used.
+// The latency of integer division ranges from 4 to 20.
+let Latency = 20, ReleaseAtCycles = [20] in {
+ def : WriteRes<WriteIDiv32, [XSPipeDIV]>;
+ def : WriteRes<WriteIDiv, [XSPipeDIV]>;
+ def : WriteRes<WriteIRem32, [XSPipeDIV]>;
+ def : WriteRes<WriteIRem, [XSPipeDIV]>;
+}
+
+// Memory
+let Latency = 4 in {
+ def : WriteRes<WriteSTB, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteSTH, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteSTW, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteSTD, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteFST32, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteFST64, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteAtomicSTW, [XSPipeGroupSTU]>;
+ def : WriteRes<WriteAtomicSTD, [XSPipeGroupSTU]>;
+}
+
+let Latency = 6 in {
+ def : WriteRes<WriteLDB, [XSPipeLDU]>;
+ def : WriteRes<WriteLDH, [XSPipeLDU]>;
+ def : WriteRes<WriteLDW, [XSPipeLDU]>;
+ def : WriteRes<WriteLDD, [XSPipeLDU]>;
+
+ def : WriteRes<WriteFLD32, [XSPipeLDU]>;
+ def : WriteRes<WriteFLD64, [XSPipeLDU]>;
+
+ def : WriteRes<WriteAtomicW, [XSPipeLDU]>;
+ def : WriteRes<WriteAtomicD, [XSPipeLDU]>;
+ def : WriteRes<WriteAtomicLDW, [XSPipeLDU]>;
+ def : WriteRes<WriteAtomicLDD, [XSPipeLDU]>;
+}
+
+let Latency = 2 in {
+ def : WriteRes<WriteFAdd32, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFAdd64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFCmp32, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFCmp64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFMinMax32, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFMinMax64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFClass32, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFClass64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFSGNJ32, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFSGNJ64, [XSPipeGroupFALU]>;
+}
+
+let Latency = 2 in {
+ def : WriteRes<WriteFMul32, [XSPipeGroupFMA]>;
+ def : WriteRes<WriteFMul64, [XSPipeGroupFMA]>;
+ def : WriteRes<WriteFMA32, [XSPipeGroupFMA]>;
+ def : WriteRes<WriteFMA64, [XSPipeGroupFMA]>;
+}
+
+// FDIV
+let Latency = 10 in {
+ def : WriteRes<WriteFDiv32, [XSPipeFEX3]>;
+ def : WriteRes<WriteFSqrt32, [XSPipeFEX3]>;
+}
+let Latency = 15 in {
+ def : WriteRes<WriteFDiv64, [XSPipeFEX3]>;
+ def : WriteRes<WriteFSqrt64, [XSPipeFEX3]>;
+}
+
+// FCVT
+let Latency = 3 in {
+ def : WriteRes<WriteFCvtF32ToI32, [XSPipeFEX1]>;
+ def : WriteRes<WriteFCvtF32ToI64, [XSPipeFEX1]>;
+ def : WriteRes<WriteFCvtF64ToI32, [XSPipeFEX1]>;
+ def : WriteRes<WriteFCvtF64ToI64, [XSPipeFEX1]>;
+ def : WriteRes<WriteFCvtF64ToF32, [XSPipeFEX1]>;
+ def : WriteRes<WriteFCvtF32ToF64, [XSPipeFEX1]>;
+ def : WriteRes<WriteFMovF64ToI64, [XSPipeFEX1]>;
+ def : WriteRes<WriteFMovF32ToI32, [XSPipeFEX1]>;
+}
+
+// I2V
+let Latency = 1 in {
+ def : WriteRes<WriteFMovI64ToF64, [XSPipeBJU2]>;
+ def : WriteRes<WriteFMovI32ToF32, [XSPipeBJU2]>;
+}
+
+// I2F
+let Latency = 3 in {
+ def : WriteRes<WriteFCvtI32ToF32, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI64ToF32, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI32ToF64, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI64ToF64, [XSPipeBJU2]>;
+}
+
+/// Zb*
+let Latency = 1 in {
+ // Zba
+ def : WriteRes<WriteSHXADD, [XSPipeGroupALU]>;
+ def : WriteRes<WriteSHXADD32, [XSPipeGroupALU]>;
+
+ // Zbb
+ def : WriteRes<WriteRotateImm, [XSPipeGroupALU]>;
+ def : WriteRes<WriteRotateImm32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteRotateReg, [XSPipeGroupALU]>;
+ def : WriteRes<WriteRotateReg32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteREV8, [XSPipeGroupALU]>;
+ def : WriteRes<WriteORCB, [XSPipeGroupALU]>;
+ def : WriteRes<WriteIMinMax, [XSPipeGroupALU]>;
+
+ // Zbs
+ def : WriteRes<WriteSingleBit, [XSPipeGroupALU]>;
+ def : WriteRes<WriteSingleBitImm, [XSPipeGroupALU]>;
+ def : WriteRes<WriteBEXT, [XSPipeGroupALU]>;
+ def : WriteRes<WriteBEXTI, [XSPipeGroupALU]>;
+
+ // Zbkb
+ def : WriteRes<WriteBREV8, [XSPipeGroupALU]>;
+ def : WriteRes<WritePACK, [XSPipeGroupALU]>;
+ def : WriteRes<WritePACK32, [XSPipeGroupALU]>;
+ def : WriteRes<WriteZIP, [XSPipeGroupALU]>;
+}
+
+let Latency = 3 in {
+ // Zbb
+ def : WriteRes<WriteCLZ, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCLZ32, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCTZ, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCTZ32, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCPOP, [XSPipeGroupBKU]>;
+ def : WriteRes<WriteCPOP32, [XSPipeGroupBKU]>;
+
+ // Zbc
+ def : WriteRes<WriteCLMUL, [XSPipeGroupBKU]>;
+
+ // Zbkx
+ def : WriteRes<WriteXPERM, [XSPipeGroupBKU]>;
+}
+
+// Others
+def : WriteRes<WriteCSR, [XSPipeBJU2]>;
+def : WriteRes<WriteNop, []>;
+
+def : InstRW<[WriteIALU], (instrs COPY)>;
+
+//===----------------------------------------------------------------------===//
+
+// Bypass and advance
+
+class XSLDUtoAnyBypass<SchedRead read, int cycles = 2>
+ : ReadAdvance<read, cycles, [WriteLDB, WriteLDH,
+ WriteLDW, WriteLDD,
+ WriteFLD32, WriteFLD64,
+ WriteAtomicW, WriteAtomicD,
+ WriteAtomicLDW, WriteAtomicLDD]>;
+
+def : ReadAdvance<ReadJmp, 0>;
+def : ReadAdvance<ReadJalr, 0>;
+def : ReadAdvance<ReadCSR, 0>;
+def : ReadAdvance<ReadStoreData, 0>;
+def : ReadAdvance<ReadMemBase, 0>;
+def : XSLDUtoAnyBypass<ReadIALU>;
+def : XSLDUtoAnyBypass<ReadIALU32>;
+def : XSLDUtoAnyBypass<ReadShiftImm>;
+def : XSLDUtoAnyBypass<ReadShiftImm32>;
+def : XSLDUtoAnyBypass<ReadShiftReg>;
+def : XSLDUtoAnyBypass<ReadShiftReg32>;
+def : ReadAdvance<ReadIDiv, 0>;
+def : ReadAdvance<ReadIDiv32, 0>;
+def : ReadAdvance<ReadIRem, 0>;
+def : ReadAdvance<ReadIRem32, 0>;
+def : ReadAdvance<ReadIMul, 0>;
+def : ReadAdvance<ReadIMul32, 0>;
+def : XSLDUtoAnyBypass<ReadAtomicWA>;
+def : XSLDUtoAnyBypass<ReadAtomicWD>;
+def : XSLDUtoAnyBypass<ReadAtomicDA>;
+def : XSLDUtoAnyBypass<ReadAtomicDD>;
+def : XSLDUtoAnyBypass<ReadAtomicLDW>;
+def : XSLDUtoAnyBypass<ReadAtomicLDD>;
+def : ReadAdvance<ReadAtomicSTW, 0>;
+def : ReadAdvance<ReadAtomicSTD, 0>;
+def : ReadAdvance<ReadFStoreData, 0>;
+def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFAdd32, 0>;
+def : ReadAdvance<ReadFAdd64, 0>;
+def : ReadAdvance<ReadFMul32, 0>;
+def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
+def : ReadAdvance<ReadFMA32Addend, 0>;
+def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFMA64Addend, 0>;
+def : ReadAdvance<ReadFDiv32, 0>;
+def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt32, 0>;
+def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp32, 0>;
+def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ32, 0>;
+def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax32, 0>;
+def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFCvtF32ToI32, 0>;
+def : ReadAdvance<ReadFCvtF32ToI64, 0>;
+def : ReadAdvance<ReadFCvtF64ToI32, 0>;
+def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF32, 0>;
+def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF32, 0>;
+def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFMovF32ToI32, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
+def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI64ToF64, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+
+/// B extension
+// Zba
+def : ReadAdvance<ReadSHXADD, 0>;
+def : ReadAdvance<ReadSHXADD32, 0>;
+// Zbb
+def : ReadAdvance<ReadRotateImm, 0>;
+def : ReadAdvance<ReadRotateImm32, 0>;
+def : ReadAdvance<ReadRotateReg, 0>;
+def : ReadAdvance<ReadRotateReg32, 0>;
+def : ReadAdvance<ReadCLZ, 0>;
+def : ReadAdvance<ReadCLZ32, 0>;
+def : ReadAdvance<ReadCTZ, 0>;
+def : ReadAdvance<ReadCTZ32, 0>;
+def : ReadAdvance<ReadCPOP, 0>;
+def : ReadAdvance<ReadCPOP32, 0>;
+def : ReadAdvance<ReadREV8, 0>;
+def : ReadAdvance<ReadORCB, 0>;
+def : ReadAdvance<ReadIMinMax, 0>;
+// Zbc
+def : ReadAdvance<ReadCLMUL, 0>;
+// Zbs
+def : ReadAdvance<ReadSingleBit, 0>;
+def : ReadAdvance<ReadSingleBitImm, 0>;
+// Zbkb
+def : ReadAdvance<ReadBREV8, 0>;
+def : ReadAdvance<ReadPACK, 0>;
+def : ReadAdvance<ReadPACK32, 0>;
+def : ReadAdvance<ReadZIP, 0>;
+// Zbkx
+def : ReadAdvance<ReadXPERM, 0>;
+
+//===----------------------------------------------------------------------===//
+// Unsupported extensions
+defm : UnsupportedSchedQ;
+defm : UnsupportedSchedV;
+defm : UnsupportedSchedZfa;
+defm : UnsupportedSchedZfhmin;
+defm : UnsupportedSchedSFB;
+defm : UnsupportedSchedZabha;
+defm : UnsupportedSchedXsf;
+defm : UnsupportedSchedZvk;
+
+} // SchedModel
>From a75f2e1561e05f60765e51fedafc6849dbe68180 Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Thu, 2 Apr 2026 15:35:46 +0800
Subject: [PATCH 02/10] [RISCV] Add XiangShan Kunminghu scheduling model and
test cases
Add llvm-mca test cases for the XiangShan Kunminghu microarchitecture, including:
- Basic integer and floating-point operation tests
- Branch and memory access instruction tests
- Bit-manipulation extension tests
- Floating-point division and conversion tests
Also update the XiangShan Kunminghu scheduling model:
- Adjust pipeline resource groupings
- Optimize instruction latency and throughput
- Add support for bit-manipulation extensions
- Improve floating-point operation scheduling
---
.../RISCV/RISCVSchedXiangShanKunMingHu.td | 74 ++--
.../RISCV/XiangShan-Kunminghu/bitmanip.s | 179 +++++++++
.../RISCV/XiangShan-Kunminghu/branch.s | 84 +++++
.../RISCV/XiangShan-Kunminghu/cascade-fma.s | 55 +++
.../RISCV/XiangShan-Kunminghu/div-fdiv.s | 119 ++++++
.../RISCV/XiangShan-Kunminghu/fpr-bypass.s | 250 +++++++++++++
.../RISCV/XiangShan-Kunminghu/gpr-bypass.s | 353 ++++++++++++++++++
.../RISCV/XiangShan-Kunminghu/load-store.s | 100 +++++
.../RISCV/XiangShan-Kunminghu/load-to-alu.s | 75 ++++
.../RISCV/XiangShan-Kunminghu/load-to-fpu.s | 75 ++++
.../RISCV/XiangShan-Kunminghu/mul-fmul.s | 74 ++++
.../cascade-fma.s | 0
.../gpr-bypass.s | 0
.../load-to-alu.s | 0
14 files changed, 1404 insertions(+), 34 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/branch.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s
rename llvm/test/tools/llvm-mca/RISCV/{XiangShan => XiangShan-Nanhu}/cascade-fma.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/{XiangShan => XiangShan-Nanhu}/gpr-bypass.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/{XiangShan => XiangShan-Nanhu}/load-to-alu.s (100%)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
index 06c2b8a0e4aa2..52a52c99c2245 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -35,7 +35,7 @@ def XiangShanKunMingHuModel : SchedMachineModel {
let SchedModel = XiangShanKunMingHuModel in {
// Define each kind of processor resource and number available.
/// Pipline
-let BufferSize = 12 in {
+let BufferSize = 24 in {
// Integer
def XSPipeALU0 : ProcResource<1>; // ALU, MUL, BKU
def XSPipeALU1 : ProcResource<1>; // ALU, MUL, BKU
@@ -44,17 +44,20 @@ let BufferSize = 12 in {
def XSPipeBJU0 : ProcResource<1>; // BRU, JMP
def XSPipeBJU1 : ProcResource<1>; // BRU, JMP
- def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, I2V, CSR
- def XSPipeDIV : ProcResource<1>; // DIV
+ def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, I2V, VSet
+ def XSPipeBJU3 : ProcResource<1>; // CSR, Fence, DIV
+}
+let BufferSize = 18 in {
// Floating-point
- def XSPipeFEX0 : ProcResource<1>; // FALU, FMA
- def XSPipeFEX1 : ProcResource<1>; // FCVT
+ def XSPipeFEX0 : ProcResource<1>; // FALU, FMA, FCVT, F2V
+ def XSPipeFEX1 : ProcResource<1>; // FDIV
def XSPipeFEX2 : ProcResource<1>; // FALU, FMA
def XSPipeFEX3 : ProcResource<1>; // FDIV
+ def XSPipeFEX4 : ProcResource<1>; // FALU, FMA
}
-let BufferSize = 24 in {
+let BufferSize = 16 in {
// Load and store
def XSPipeLDU : ProcResource<3>; // LDU
@@ -66,10 +69,10 @@ def XSPipeGroupALU : ProcResGroup<[XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU
def XSPipeGroupMUL : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
def XSPipeGroupBKU : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
def XSPipeGroupBRU : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
-def XSPipeGroupJMP : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
-def XSPipeGroupFALU : ProcResGroup<[XSPipeFEX0, XSPipeFEX2]>;
-def XSPipeGroupFMA : ProcResGroup<[XSPipeFEX0, XSPipeFEX2]>;
+def XSPipeGroupFALU : ProcResGroup<[XSPipeFEX0, XSPipeFEX2, XSPipeFEX4]>;
+def XSPipeGroupFMA : ProcResGroup<[XSPipeFEX0, XSPipeFEX2, XSPipeFEX4]>;
+def XSPipeGroupFDIV : ProcResGroup<[XSPipeFEX1, XSPipeFEX3]>;
def XSPipeGroupSTU : ProcResGroup<[XSPipeSTA, XSPipeSTD]>;
@@ -78,8 +81,8 @@ def XSPipeGroupSTU : ProcResGroup<[XSPipeSTA, XSPipeSTD]>;
// Jump
def : WriteRes<WriteJmp, [XSPipeGroupBRU]>;
-def : WriteRes<WriteJal, [XSPipeGroupJMP]>;
-def : WriteRes<WriteJalr, [XSPipeGroupJMP]>;
+def : WriteRes<WriteJal, [XSPipeGroupBRU]>;
+def : WriteRes<WriteJalr, [XSPipeGroupBRU]>;
// Integer arithmetic and logic
def : WriteRes<WriteIALU32, [XSPipeGroupALU]>;
@@ -99,10 +102,10 @@ let Latency = 2 in {
// Worst case latency is used.
// The latency of integer division ranges from 4 to 20.
let Latency = 20, ReleaseAtCycles = [20] in {
- def : WriteRes<WriteIDiv32, [XSPipeDIV]>;
- def : WriteRes<WriteIDiv, [XSPipeDIV]>;
- def : WriteRes<WriteIRem32, [XSPipeDIV]>;
- def : WriteRes<WriteIRem, [XSPipeDIV]>;
+ def : WriteRes<WriteIDiv32, [XSPipeBJU3]>;
+ def : WriteRes<WriteIDiv, [XSPipeBJU3]>;
+ def : WriteRes<WriteIRem32, [XSPipeBJU3]>;
+ def : WriteRes<WriteIRem, [XSPipeBJU3]>;
}
// Memory
@@ -132,9 +135,12 @@ let Latency = 6 in {
def : WriteRes<WriteAtomicLDD, [XSPipeLDU]>;
}
-let Latency = 2 in {
+let Latency = 1 in {
def : WriteRes<WriteFAdd32, [XSPipeGroupFALU]>;
def : WriteRes<WriteFAdd64, [XSPipeGroupFALU]>;
+}
+
+let Latency = 2 in {
def : WriteRes<WriteFCmp32, [XSPipeGroupFALU]>;
def : WriteRes<WriteFCmp64, [XSPipeGroupFALU]>;
def : WriteRes<WriteFMinMax32, [XSPipeGroupFALU]>;
@@ -145,7 +151,7 @@ let Latency = 2 in {
def : WriteRes<WriteFSGNJ64, [XSPipeGroupFALU]>;
}
-let Latency = 2 in {
+let Latency = 3 in {
def : WriteRes<WriteFMul32, [XSPipeGroupFMA]>;
def : WriteRes<WriteFMul64, [XSPipeGroupFMA]>;
def : WriteRes<WriteFMA32, [XSPipeGroupFMA]>;
@@ -154,34 +160,34 @@ let Latency = 2 in {
// FDIV
let Latency = 10 in {
- def : WriteRes<WriteFDiv32, [XSPipeFEX3]>;
- def : WriteRes<WriteFSqrt32, [XSPipeFEX3]>;
+ def : WriteRes<WriteFDiv32, [XSPipeGroupFDIV]>;
+ def : WriteRes<WriteFSqrt32, [XSPipeGroupFDIV]>;
}
let Latency = 15 in {
- def : WriteRes<WriteFDiv64, [XSPipeFEX3]>;
- def : WriteRes<WriteFSqrt64, [XSPipeFEX3]>;
+ def : WriteRes<WriteFDiv64, [XSPipeGroupFDIV]>;
+ def : WriteRes<WriteFSqrt64, [XSPipeGroupFDIV]>;
}
// FCVT
-let Latency = 3 in {
- def : WriteRes<WriteFCvtF32ToI32, [XSPipeFEX1]>;
- def : WriteRes<WriteFCvtF32ToI64, [XSPipeFEX1]>;
- def : WriteRes<WriteFCvtF64ToI32, [XSPipeFEX1]>;
- def : WriteRes<WriteFCvtF64ToI64, [XSPipeFEX1]>;
- def : WriteRes<WriteFCvtF64ToF32, [XSPipeFEX1]>;
- def : WriteRes<WriteFCvtF32ToF64, [XSPipeFEX1]>;
- def : WriteRes<WriteFMovF64ToI64, [XSPipeFEX1]>;
- def : WriteRes<WriteFMovF32ToI32, [XSPipeFEX1]>;
+let Latency = 2 in {
+ def : WriteRes<WriteFCvtF32ToI32, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF32ToI64, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF64ToI32, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF64ToI64, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF64ToF32, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF32ToF64, [XSPipeFEX0]>;
+ def : WriteRes<WriteFMovF64ToI64, [XSPipeFEX0]>;
+ def : WriteRes<WriteFMovF32ToI32, [XSPipeFEX0]>;
}
// I2V
-let Latency = 1 in {
+let Latency = 0 in {
def : WriteRes<WriteFMovI64ToF64, [XSPipeBJU2]>;
def : WriteRes<WriteFMovI32ToF32, [XSPipeBJU2]>;
}
// I2F
-let Latency = 3 in {
+let Latency = 2 in {
def : WriteRes<WriteFCvtI32ToF32, [XSPipeBJU2]>;
def : WriteRes<WriteFCvtI64ToF32, [XSPipeBJU2]>;
def : WriteRes<WriteFCvtI32ToF64, [XSPipeBJU2]>;
@@ -216,7 +222,7 @@ let Latency = 1 in {
def : WriteRes<WriteZIP, [XSPipeGroupALU]>;
}
-let Latency = 3 in {
+let Latency = 2 in {
// Zbb
def : WriteRes<WriteCLZ, [XSPipeGroupBKU]>;
def : WriteRes<WriteCLZ32, [XSPipeGroupBKU]>;
@@ -233,7 +239,7 @@ let Latency = 3 in {
}
// Others
-def : WriteRes<WriteCSR, [XSPipeBJU2]>;
+def : WriteRes<WriteCSR, [XSPipeBJU3]>;
def : WriteRes<WriteNop, []>;
def : InstRW<[WriteIALU], (instrs COPY)>;
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s
new file mode 100644
index 0000000000000..924fc43a59df1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s
@@ -0,0 +1,179 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -mattr=+zba,+zbb,+zbs -iterations=1 < %s | FileCheck %s
+
+sh1add a0, a1, a2
+sh2add a0, a1, a2
+sh3add a0, a1, a2
+sh1add.uw a0, a1, a2
+sh2add.uw a0, a1, a2
+sh3add.uw a0, a1, a2
+add.uw a0, a1, a2
+slli.uw a0, a1, 1
+
+clz a0, a1
+clzw a0, a1
+ctz a0, a1
+ctzw a0, a1
+cpop a0, a1
+cpopw a0, a1
+
+andn a0, a1, a2
+orn a0, a1, a2
+xnor a0, a1, a2
+
+rol a0, a1, a2
+rolw a0, a1, a2
+ror a0, a1, a2
+rorw a0, a1, a2
+rori a0, a1, 1
+roriw a0, a1, 1
+
+min a0, a1, a2
+minu a0, a1, a2
+max a0, a1, a2
+maxu a0, a1, a2
+
+sext.b a0, a1
+sext.h a0, a1
+zext.h a0, a1
+
+rev8 a0, a1
+orc.b a0, a1
+
+bclr a0, a1, a2
+bclri a0, a1, 1
+bext a0, a1, a2
+bexti a0, a1, 1
+binv a0, a1, a2
+binvi a0, a1, 1
+bset a0, a1, a2
+bseti a0, a1, 1
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 40
+# CHECK-NEXT: Total Cycles: 13
+# CHECK-NEXT: Total uOps: 40
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 3.08
+# CHECK-NEXT: IPC: 3.08
+# CHECK-NEXT: Block RThroughput: 8.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 sh1add a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sh2add a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sh3add a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sh1add.uw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sh2add.uw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sh3add.uw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 add.uw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 slli.uw a0, a1, 1
+# CHECK-NEXT: 1 2 0.50 clz a0, a1
+# CHECK-NEXT: 1 2 0.50 clzw a0, a1
+# CHECK-NEXT: 1 2 0.50 ctz a0, a1
+# CHECK-NEXT: 1 2 0.50 ctzw a0, a1
+# CHECK-NEXT: 1 2 0.50 cpop a0, a1
+# CHECK-NEXT: 1 2 0.50 cpopw a0, a1
+# CHECK-NEXT: 1 1 0.25 andn a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 orn a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 xnor a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 rol a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 rolw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 ror a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 rorw a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 rori a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 roriw a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 min a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 minu a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 max a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 maxu a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 sext.b a0, a1
+# CHECK-NEXT: 1 1 0.25 sext.h a0, a1
+# CHECK-NEXT: 1 1 0.25 zext.h a0, a1
+# CHECK-NEXT: 1 1 0.25 rev8 a0, a1
+# CHECK-NEXT: 1 1 0.25 orc.b a0, a1
+# CHECK-NEXT: 1 1 0.25 bclr a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 bclri a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 bext a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 bexti a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 binv a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 binvi a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 bset a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 bseti a0, a1, 1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 10.00 10.00 10.00 10.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sh1add a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - sh2add a0, a1, a2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sh3add a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - sh1add.uw a0, a1, a2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sh2add.uw a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - sh3add.uw a0, a1, a2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - add.uw a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - slli.uw a0, a1, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - clz a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - clzw a0, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - ctz a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - ctzw a0, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - cpop a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - cpopw a0, a1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - andn a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - orn a0, a1, a2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - xnor a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - rol a0, a1, a2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - rolw a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - ror a0, a1, a2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - rorw a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - rori a0, a1, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - roriw a0, a1, 1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - min a0, a1, a2
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - minu a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - max a0, a1, a2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - maxu a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - sext.b a0, a1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sext.h a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - zext.h a0, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - rev8 a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - orc.b a0, a1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - bclr a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - bclri a0, a1, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - bext a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - bexti a0, a1, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - binv a0, a1, a2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - binvi a0, a1, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - bset a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - bseti a0, a1, 1
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/branch.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/branch.s
new file mode 100644
index 0000000000000..d153cecf582b4
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/branch.s
@@ -0,0 +1,84 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
+
+j 1f
+1:
+jr ra
+
+beq a0, a1, 1f
+1:
+bne a0, a1, 1f
+1:
+blt a0, a1, 1f
+1:
+bge a0, a1, 1f
+1:
+bltu a0, a1, 1f
+1:
+bgeu a0, a1, 1f
+1:
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 8
+# CHECK-NEXT: Total Cycles: 6
+# CHECK-NEXT: Total uOps: 8
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.33
+# CHECK-NEXT: IPC: 1.33
+# CHECK-NEXT: Block RThroughput: 2.7
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 j .Ltmp0
+# CHECK-NEXT: 1 1 0.33 ret
+# CHECK-NEXT: 1 1 0.33 beq a0, a1, .Ltmp1
+# CHECK-NEXT: 1 1 0.33 bne a0, a1, .Ltmp2
+# CHECK-NEXT: 1 1 0.33 blt a0, a1, .Ltmp3
+# CHECK-NEXT: 1 1 0.33 bge a0, a1, .Ltmp4
+# CHECK-NEXT: 1 1 0.33 bltu a0, a1, .Ltmp5
+# CHECK-NEXT: 1 1 0.33 bgeu a0, a1, .Ltmp6
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - 2.00 3.00 3.00 - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - j .Ltmp0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - ret
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - beq a0, a1, .Ltmp1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - bne a0, a1, .Ltmp2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - blt a0, a1, .Ltmp3
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - bge a0, a1, .Ltmp4
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - bltu a0, a1, .Ltmp5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - bgeu a0, a1, .Ltmp6
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
new file mode 100644
index 0000000000000..c7cf24ab0016f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
@@ -0,0 +1,55 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu < %s | FileCheck %s
+
+fmadd.s fa0, fa1, fa2, fa0
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 100
+# CHECK-NEXT: Total Cycles: 303
+# CHECK-NEXT: Total uOps: 100
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.33
+# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: Block RThroughput: 0.3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 0.33 fmadd.s fa0, fa1, fa2, fa0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.34 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.34 - - - - - - - fmadd.s fa0, fa1, fa2, fa0
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
new file mode 100644
index 0000000000000..ad6a54bd28e26
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
@@ -0,0 +1,119 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -timeline -iterations=1 < %s | FileCheck %s
+
+div a0, a1, a2
+divu a0, a1, a2
+divw a0, a1, a2
+divuw a0, a1, a2
+rem a0, a1, a2
+remu a0, a1, a2
+remw a0, a1, a2
+remuw a0, a1, a2
+
+fdiv.s fa0, fa1, fa2
+fdiv.d fa0, fa1, fa2
+fsqrt.s fa0, fa1
+fsqrt.d fa0, fa1
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 12
+# CHECK-NEXT: Total Cycles: 163
+# CHECK-NEXT: Total uOps: 12
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.07
+# CHECK-NEXT: IPC: 0.07
+# CHECK-NEXT: Block RThroughput: 160.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 20 20.00 div a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 divu a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 divw a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 divuw a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 rem a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 remu a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 remw a0, a1, a2
+# CHECK-NEXT: 1 20 20.00 remuw a0, a1, a2
+# CHECK-NEXT: 1 10 0.50 fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: 1 15 0.50 fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: 1 10 0.50 fsqrt.s fa0, fa1
+# CHECK-NEXT: 1 15 0.50 fsqrt.d fa0, fa1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - 160.00 - 2.00 - 2.00 - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - div a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - divu a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - divw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - divuw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - rem a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - remu a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - remw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - remuw a0, a1, a2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fsqrt.s fa0, fa1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fsqrt.d fa0, fa1
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 0123456789 012
+
+# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . div a0, a1, a2
+# CHECK-NEXT: [0,1] D====================eeeeeeeeeeeeeeeeeeeeER . . . . . divu a0, a1, a2
+# CHECK-NEXT: [0,2] D========================================eeeeeeeeeeeeeeeeeeeeER divw a0, a1, a2
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 div a0, a1, a2
+# CHECK-NEXT: 1. 1 21.0 21.0 0.0 divu a0, a1, a2
+# CHECK-NEXT: 2. 1 41.0 41.0 0.0 divw a0, a1, a2
+# CHECK-NEXT: 3. 1 61.0 61.0 0.0 divuw a0, a1, a2
+# CHECK-NEXT: 4. 1 81.0 81.0 0.0 rem a0, a1, a2
+# CHECK-NEXT: 5. 1 101.0 101.0 0.0 remu a0, a1, a2
+# CHECK-NEXT: 6. 1 120.0 120.0 0.0 remw a0, a1, a2
+# CHECK-NEXT: 7. 1 140.0 140.0 0.0 remuw a0, a1, a2
+# CHECK-NEXT: 8. 1 1.0 1.0 149.0 fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: 9. 1 1.0 1.0 144.0 fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: 10. 1 2.0 2.0 148.0 fsqrt.s fa0, fa1
+# CHECK-NEXT: 11. 1 2.0 2.0 143.0 fsqrt.d fa0, fa1
+# CHECK-NEXT: 1 47.7 47.7 48.7 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
new file mode 100644
index 0000000000000..b850d3526e870
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
@@ -0,0 +1,250 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
+
+fadd.s fa0, fa1, fa2
+fadd.d fa0, fa1, fa2
+fsub.s fa0, fa1, fa2
+fsub.d fa0, fa1, fa2
+
+fmul.s fa0, fa1, fa2
+fmul.d fa0, fa1, fa2
+
+fdiv.s fa0, fa1, fa2
+fdiv.d fa0, fa1, fa2
+fsqrt.s fa0, fa1
+fsqrt.d fa0, fa1
+
+fmadd.s fa0, fa1, fa2, fa3
+fmadd.d fa0, fa1, fa2, fa3
+fmsub.s fa0, fa1, fa2, fa3
+fmsub.d fa0, fa1, fa2, fa3
+fnmadd.s fa0, fa1, fa2, fa3
+fnmadd.d fa0, fa1, fa2, fa3
+fnmsub.s fa0, fa1, fa2, fa3
+fnmsub.d fa0, fa1, fa2, fa3
+
+feq.s a0, fa1, fa2
+feq.d a0, fa1, fa2
+flt.s a0, fa1, fa2
+flt.d a0, fa1, fa2
+fle.s a0, fa1, fa2
+fle.d a0, fa1, fa2
+
+fmin.s fa0, fa1, fa2
+fmin.d fa0, fa1, fa2
+fmax.s fa0, fa1, fa2
+fmax.d fa0, fa1, fa2
+
+fsgnj.s fa0, fa1, fa2
+fsgnj.d fa0, fa1, fa2
+fsgnjn.s fa0, fa1, fa2
+fsgnjn.d fa0, fa1, fa2
+fsgnjx.s fa0, fa1, fa2
+fsgnjx.d fa0, fa1, fa2
+
+fmv.x.w a0, fa0
+fmv.x.d a0, fa0
+fmv.w.x fa0, a0
+fmv.d.x fa0, a0
+
+fcvt.s.w fa0, a0
+fcvt.s.wu fa0, a0
+fcvt.s.l fa0, a0
+fcvt.s.lu fa0, a0
+fcvt.d.w fa0, a0
+fcvt.d.wu fa0, a0
+fcvt.d.l fa0, a0
+fcvt.d.lu fa0, a0
+
+fcvt.w.s a0, fa0
+fcvt.wu.s a0, fa0
+fcvt.l.s a0, fa0
+fcvt.lu.s a0, fa0
+fcvt.w.d a0, fa0
+fcvt.wu.d a0, fa0
+fcvt.l.d a0, fa0
+fcvt.lu.d a0, fa0
+
+fcvt.s.d fa0, fa1
+fcvt.d.s fa0, fa1
+
+fclass.s a0, fa0
+fclass.d a0, fa0
+
+flw fa0, 0(a0)
+fld fa0, 0(a0)
+fsw fa0, 0(a0)
+fsd fa0, 0(a0)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 62
+# CHECK-NEXT: Total Cycles: 29
+# CHECK-NEXT: Total uOps: 62
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 2.14
+# CHECK-NEXT: IPC: 2.14
+# CHECK-NEXT: Block RThroughput: 12.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.33 fadd.s fa0, fa1, fa2
+# CHECK-NEXT: 1 1 0.33 fadd.d fa0, fa1, fa2
+# CHECK-NEXT: 1 1 0.33 fsub.s fa0, fa1, fa2
+# CHECK-NEXT: 1 1 0.33 fsub.d fa0, fa1, fa2
+# CHECK-NEXT: 1 3 0.33 fmul.s fa0, fa1, fa2
+# CHECK-NEXT: 1 3 0.33 fmul.d fa0, fa1, fa2
+# CHECK-NEXT: 1 10 0.50 fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: 1 15 0.50 fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: 1 10 0.50 fsqrt.s fa0, fa1
+# CHECK-NEXT: 1 15 0.50 fsqrt.d fa0, fa1
+# CHECK-NEXT: 1 3 0.33 fmadd.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fmadd.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fmsub.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fmsub.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fnmadd.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fnmadd.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fnmsub.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 3 0.33 fnmsub.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: 1 2 0.33 feq.s a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 feq.d a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 flt.s a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 flt.d a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fle.s a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fle.d a0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fmin.s fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fmin.d fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fmax.s fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fmax.d fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnj.s fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnj.d fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnjn.s fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnjn.d fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnjx.s fa0, fa1, fa2
+# CHECK-NEXT: 1 2 0.33 fsgnjx.d fa0, fa1, fa2
+# CHECK-NEXT: 1 2 1.00 fmv.x.w a0, fa0
+# CHECK-NEXT: 1 2 1.00 fmv.x.d a0, fa0
+# CHECK-NEXT: 1 0 1.00 fmv.w.x fa0, a0
+# CHECK-NEXT: 1 0 1.00 fmv.d.x fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.s.w fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.s.wu fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.s.l fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.s.lu fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.d.w fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.d.wu fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.d.l fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.d.lu fa0, a0
+# CHECK-NEXT: 1 2 1.00 fcvt.w.s a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.wu.s a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.l.s a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.lu.s a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.w.d a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.wu.d a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.l.d a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.lu.d a0, fa0
+# CHECK-NEXT: 1 2 1.00 fcvt.s.d fa0, fa1
+# CHECK-NEXT: 1 2 1.00 fcvt.d.s fa0, fa1
+# CHECK-NEXT: 1 2 0.33 fclass.s a0, fa0
+# CHECK-NEXT: 1 2 0.33 fclass.d a0, fa0
+# CHECK-NEXT: 1 6 0.33 * flw fa0, 0(a0)
+# CHECK-NEXT: 1 6 0.33 * fld fa0, 0(a0)
+# CHECK-NEXT: 1 4 0.25 * fsw fa0, 0(a0)
+# CHECK-NEXT: 1 4 0.25 * fsd fa0, 0(a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - 10.00 - 22.00 2.00 11.00 2.00 11.00 - 1.00 1.00 - - 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fadd.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fadd.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fsub.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fsub.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmul.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmul.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fsqrt.s fa0, fa1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fsqrt.d fa0, fa1
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmadd.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmadd.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmsub.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmsub.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fnmadd.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fnmadd.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fnmsub.s fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fnmsub.d fa0, fa1, fa2, fa3
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - feq.s a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - feq.d a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - flt.s a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - flt.d a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fle.s a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fle.d a0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmin.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmin.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmax.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmax.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fsgnj.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fsgnj.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fsgnjn.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fsgnjn.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fsgnjx.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fsgnjx.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmv.x.w a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmv.x.d a0, fa0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fmv.w.x fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fmv.d.x fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.w fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.wu fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.l fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.lu fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.w fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.wu fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.l fa0, a0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.lu fa0, a0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.w.s a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.wu.s a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.l.s a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.lu.s a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.w.d a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.wu.d a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.l.d a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.lu.d a0, fa0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.s.d fa0, fa1
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.d.s fa0, fa1
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fclass.s a0, fa0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fclass.d a0, fa0
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - flw fa0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - fld fa0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 fsw fa0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - fsd fa0, 0(a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
new file mode 100644
index 0000000000000..ce6b171f54c78
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
@@ -0,0 +1,353 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -timeline \
+# RUN: -timeline-max-cycles=1000 -iterations=1 < %s | FileCheck %s
+
+lui a0, 1
+auipc a1, 1
+
+add a0, a0, a1
+addi a0, a0, 1
+addw a0, a0, a0
+addiw a0, a0, 1
+
+sub a0, a0, a0
+subw a0, a0, a0
+
+and a0, a0, a1
+andi a0, a0, 1
+or a0, a0, a1
+ori a0, a0, 1
+xor a0, a0, a1
+xori a0, a0, 1
+
+sll a0, a0, a1
+slli a0, a0, 1
+sllw a0, a0, a1
+slliw a0, a0, 1
+srl a0, a0, a1
+srli a0, a0, 1
+srlw a0, a0, a1
+srliw a0, a0, 1
+sra a0, a0, a1
+srai a0, a0, 1
+sraw a0, a0, a1
+sraiw a0, a0, 1
+
+slt a0, a0, a1
+slti a0, a0, 1
+sltu a0, a0, a1
+sltiu a0, a0, 1
+
+mul a0, a0, a1
+mulh a0, a0, a1
+mulhsu a0, a0, a1
+mulhu a0, a0, a1
+mulw a0, a0, a1
+
+j 1f
+1:
+jr ra
+beq a0, a1, 1f
+1:
+bne a0, a1, 1f
+1:
+blt a0, a1, 1f
+1:
+bge a0, a1, 1f
+1:
+bltu a0, a1, 1f
+1:
+bgeu a0, a1, 1f
+1:
+
+lb a0, 0(a1)
+lh a0, 0(a1)
+lw a0, 0(a1)
+ld a0, 0(a1)
+lbu a0, 0(a1)
+lhu a0, 0(a1)
+lwu a0, 0(a1)
+
+sb a0, 0(a1)
+sh a0, 0(a1)
+sw a0, 0(a1)
+sd a0, 0(a1)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 54
+# CHECK-NEXT: Total Cycles: 44
+# CHECK-NEXT: Total uOps: 54
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.23
+# CHECK-NEXT: IPC: 1.23
+# CHECK-NEXT: Block RThroughput: 9.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.25 lui a0, 1
+# CHECK-NEXT: 1 1 0.25 auipc a1, 1
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 addi a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 addw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 addiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sub a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 subw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 and a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 andi a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 or a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 ori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 xor a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 xori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sll a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 slli a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sllw a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 slliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 srl a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 srli a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 srlw a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 srliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sra a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 srai a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sraw a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 sraiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 slt a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 slti a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 sltu a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 seqz a0, a0
+# CHECK-NEXT: 1 2 0.50 mul a0, a0, a1
+# CHECK-NEXT: 1 2 0.50 mulh a0, a0, a1
+# CHECK-NEXT: 1 2 0.50 mulhsu a0, a0, a1
+# CHECK-NEXT: 1 2 0.50 mulhu a0, a0, a1
+# CHECK-NEXT: 1 2 0.50 mulw a0, a0, a1
+# CHECK-NEXT: 1 1 0.33 j .Ltmp0
+# CHECK-NEXT: 1 1 0.33 ret
+# CHECK-NEXT: 1 1 0.33 beq a0, a1, .Ltmp1
+# CHECK-NEXT: 1 1 0.33 bne a0, a1, .Ltmp2
+# CHECK-NEXT: 1 1 0.33 blt a0, a1, .Ltmp3
+# CHECK-NEXT: 1 1 0.33 bge a0, a1, .Ltmp4
+# CHECK-NEXT: 1 1 0.33 bltu a0, a1, .Ltmp5
+# CHECK-NEXT: 1 1 0.33 bgeu a0, a1, .Ltmp6
+# CHECK-NEXT: 1 6 0.33 * lb a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lh a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lw a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * ld a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lbu a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lhu a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lwu a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sb a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sh a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sw a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sd a0, 0(a1)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 9.00 10.00 8.00 8.00 2.00 3.00 3.00 - - - - - - 2.00 2.00 3.00 1.00 1.00 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - lui a0, 1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - auipc a1, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - add a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - addi a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - addw a0, a0, a0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - addiw a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sub a0, a0, a0
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - subw a0, a0, a0
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - and a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - andi a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - or a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - ori a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - xor a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - xori a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sll a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - slli a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sllw a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - slliw a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - srl a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - srli a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - srlw a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - srliw a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sra a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - srai a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sraw a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - sraiw a0, a0, 1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - slt a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - slti a0, a0, 1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sltu a0, a0, a1
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - seqz a0, a0
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mul a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulh a0, a0, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulhsu a0, a0, a1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulhu a0, a0, a1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulw a0, a0, a1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - j .Ltmp0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - ret
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - beq a0, a1, .Ltmp1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - bne a0, a1, .Ltmp2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - blt a0, a1, .Ltmp3
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - bge a0, a1, .Ltmp4
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - bltu a0, a1, .Ltmp5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - bgeu a0, a1, .Ltmp6
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lb a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - lh a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lw a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - ld a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lbu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lhu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lwu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 sb a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - sh a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - sw a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - sd a0, 0(a1)
+
+# CHECK: Timeline view:
+# CHECK-NEXT: 0123456789 0123456789
+# CHECK-NEXT: Index 0123456789 0123456789 0123
+
+# CHECK: [0,0] DeER . . . . . . . . . lui a0, 1
+# CHECK-NEXT: [0,1] DeER . . . . . . . . . auipc a1, 1
+# CHECK-NEXT: [0,2] D=eER. . . . . . . . . add a0, a0, a1
+# CHECK-NEXT: [0,3] D==eER . . . . . . . . addi a0, a0, 1
+# CHECK-NEXT: [0,4] D===eER . . . . . . . . addw a0, a0, a0
+# CHECK-NEXT: [0,5] D====eER . . . . . . . . addiw a0, a0, 1
+# CHECK-NEXT: [0,6] .D====eER . . . . . . . . sub a0, a0, a0
+# CHECK-NEXT: [0,7] .D=====eER. . . . . . . . subw a0, a0, a0
+# CHECK-NEXT: [0,8] .D======eER . . . . . . . and a0, a0, a1
+# CHECK-NEXT: [0,9] .D=======eER . . . . . . . andi a0, a0, 1
+# CHECK-NEXT: [0,10] .D========eER . . . . . . . or a0, a0, a1
+# CHECK-NEXT: [0,11] .D=========eER . . . . . . . ori a0, a0, 1
+# CHECK-NEXT: [0,12] . D=========eER. . . . . . . xor a0, a0, a1
+# CHECK-NEXT: [0,13] . D==========eER . . . . . . xori a0, a0, 1
+# CHECK-NEXT: [0,14] . D===========eER . . . . . . sll a0, a0, a1
+# CHECK-NEXT: [0,15] . D============eER . . . . . . slli a0, a0, 1
+# CHECK-NEXT: [0,16] . D=============eER . . . . . . sllw a0, a0, a1
+# CHECK-NEXT: [0,17] . D==============eER. . . . . . slliw a0, a0, 1
+# CHECK-NEXT: [0,18] . D==============eER . . . . . srl a0, a0, a1
+# CHECK-NEXT: [0,19] . D===============eER . . . . . srli a0, a0, 1
+# CHECK-NEXT: [0,20] . D================eER . . . . . srlw a0, a0, a1
+# CHECK-NEXT: [0,21] . D=================eER . . . . . srliw a0, a0, 1
+# CHECK-NEXT: [0,22] . D==================eER. . . . . sra a0, a0, a1
+# CHECK-NEXT: [0,23] . D===================eER . . . . srai a0, a0, 1
+# CHECK-NEXT: [0,24] . D===================eER . . . . sraw a0, a0, a1
+# CHECK-NEXT: [0,25] . D====================eER . . . . sraiw a0, a0, 1
+# CHECK-NEXT: [0,26] . D=====================eER . . . . slt a0, a0, a1
+# CHECK-NEXT: [0,27] . D======================eER. . . . slti a0, a0, 1
+# CHECK-NEXT: [0,28] . D=======================eER . . . sltu a0, a0, a1
+# CHECK-NEXT: [0,29] . D========================eER . . . seqz a0, a0
+# CHECK-NEXT: [0,30] . D========================eeER . . . mul a0, a0, a1
+# CHECK-NEXT: [0,31] . D==========================eeER . . mulh a0, a0, a1
+# CHECK-NEXT: [0,32] . D============================eeER . . mulhsu a0, a0, a1
+# CHECK-NEXT: [0,33] . D==============================eeER. . mulhu a0, a0, a1
+# CHECK-NEXT: [0,34] . D================================eeER . mulw a0, a0, a1
+# CHECK-NEXT: [0,35] . DeE---------------------------------R . j .Ltmp0
+# CHECK-NEXT: [0,36] . .DeE--------------------------------R . ret
+# CHECK-NEXT: [0,37] . .D=================================eER. beq a0, a1, .Ltmp1
+# CHECK-NEXT: [0,38] . .D=================================eER. bne a0, a1, .Ltmp2
+# CHECK-NEXT: [0,39] . .D=================================eER. blt a0, a1, .Ltmp3
+# CHECK-NEXT: [0,40] . .D==================================eER bge a0, a1, .Ltmp4
+# CHECK-NEXT: [0,41] . .D==================================eER bltu a0, a1, .Ltmp5
+# CHECK-NEXT: [0,42] . . D=================================eER bgeu a0, a1, .Ltmp6
+# CHECK-NEXT: [0,43] . . DeeeeeeE----------------------------R lb a0, 0(a1)
+# CHECK-NEXT: [0,44] . . DeeeeeeE----------------------------R lh a0, 0(a1)
+# CHECK-NEXT: [0,45] . . DeeeeeeE----------------------------R lw a0, 0(a1)
+# CHECK-NEXT: [0,46] . . D=eeeeeeE---------------------------R ld a0, 0(a1)
+# CHECK-NEXT: [0,47] . . D=eeeeeeE---------------------------R lbu a0, 0(a1)
+# CHECK-NEXT: [0,48] . . D=eeeeeeE--------------------------R lhu a0, 0(a1)
+# CHECK-NEXT: [0,49] . . DeeeeeeE---------------------------R lwu a0, 0(a1)
+# CHECK-NEXT: [0,50] . . D======eeeeE-----------------------R sb a0, 0(a1)
+# CHECK-NEXT: [0,51] . . D======eeeeE-----------------------R sh a0, 0(a1)
+# CHECK-NEXT: [0,52] . . D======eeeeE-----------------------R sw a0, 0(a1)
+# CHECK-NEXT: [0,53] . . D======eeeeE-----------------------R sd a0, 0(a1)
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 lui a0, 1
+# CHECK-NEXT: 1. 1 1.0 1.0 0.0 auipc a1, 1
+# CHECK-NEXT: 2. 1 2.0 0.0 0.0 add a0, a0, a1
+# CHECK-NEXT: 3. 1 3.0 0.0 0.0 addi a0, a0, 1
+# CHECK-NEXT: 4. 1 4.0 0.0 0.0 addw a0, a0, a0
+# CHECK-NEXT: 5. 1 5.0 0.0 0.0 addiw a0, a0, 1
+# CHECK-NEXT: 6. 1 5.0 0.0 0.0 sub a0, a0, a0
+# CHECK-NEXT: 7. 1 6.0 0.0 0.0 subw a0, a0, a0
+# CHECK-NEXT: 8. 1 7.0 0.0 0.0 and a0, a0, a1
+# CHECK-NEXT: 9. 1 8.0 0.0 0.0 andi a0, a0, 1
+# CHECK-NEXT: 10. 1 9.0 0.0 0.0 or a0, a0, a1
+# CHECK-NEXT: 11. 1 10.0 0.0 0.0 ori a0, a0, 1
+# CHECK-NEXT: 12. 1 10.0 0.0 0.0 xor a0, a0, a1
+# CHECK-NEXT: 13. 1 11.0 0.0 0.0 xori a0, a0, 1
+# CHECK-NEXT: 14. 1 12.0 0.0 0.0 sll a0, a0, a1
+# CHECK-NEXT: 15. 1 13.0 0.0 0.0 slli a0, a0, 1
+# CHECK-NEXT: 16. 1 14.0 0.0 0.0 sllw a0, a0, a1
+# CHECK-NEXT: 17. 1 15.0 0.0 0.0 slliw a0, a0, 1
+# CHECK-NEXT: 18. 1 15.0 0.0 0.0 srl a0, a0, a1
+# CHECK-NEXT: 19. 1 16.0 0.0 0.0 srli a0, a0, 1
+# CHECK-NEXT: 20. 1 17.0 0.0 0.0 srlw a0, a0, a1
+# CHECK-NEXT: 21. 1 18.0 0.0 0.0 srliw a0, a0, 1
+# CHECK-NEXT: 22. 1 19.0 0.0 0.0 sra a0, a0, a1
+# CHECK-NEXT: 23. 1 20.0 0.0 0.0 srai a0, a0, 1
+# CHECK-NEXT: 24. 1 20.0 0.0 0.0 sraw a0, a0, a1
+# CHECK-NEXT: 25. 1 21.0 0.0 0.0 sraiw a0, a0, 1
+# CHECK-NEXT: 26. 1 22.0 0.0 0.0 slt a0, a0, a1
+# CHECK-NEXT: 27. 1 23.0 0.0 0.0 slti a0, a0, 1
+# CHECK-NEXT: 28. 1 24.0 0.0 0.0 sltu a0, a0, a1
+# CHECK-NEXT: 29. 1 25.0 0.0 0.0 seqz a0, a0
+# CHECK-NEXT: 30. 1 25.0 0.0 0.0 mul a0, a0, a1
+# CHECK-NEXT: 31. 1 27.0 0.0 0.0 mulh a0, a0, a1
+# CHECK-NEXT: 32. 1 29.0 0.0 0.0 mulhsu a0, a0, a1
+# CHECK-NEXT: 33. 1 31.0 0.0 0.0 mulhu a0, a0, a1
+# CHECK-NEXT: 34. 1 33.0 0.0 0.0 mulw a0, a0, a1
+# CHECK-NEXT: 35. 1 1.0 1.0 33.0 j .Ltmp0
+# CHECK-NEXT: 36. 1 1.0 1.0 32.0 ret
+# CHECK-NEXT: 37. 1 34.0 0.0 0.0 beq a0, a1, .Ltmp1
+# CHECK-NEXT: 38. 1 34.0 0.0 0.0 bne a0, a1, .Ltmp2
+# CHECK-NEXT: 39. 1 34.0 0.0 0.0 blt a0, a1, .Ltmp3
+# CHECK-NEXT: 40. 1 35.0 1.0 0.0 bge a0, a1, .Ltmp4
+# CHECK-NEXT: 41. 1 35.0 1.0 0.0 bltu a0, a1, .Ltmp5
+# CHECK-NEXT: 42. 1 34.0 1.0 0.0 bgeu a0, a1, .Ltmp6
+# CHECK-NEXT: 43. 1 1.0 1.0 28.0 lb a0, 0(a1)
+# CHECK-NEXT: 44. 1 1.0 1.0 28.0 lh a0, 0(a1)
+# CHECK-NEXT: 45. 1 1.0 1.0 28.0 lw a0, 0(a1)
+# CHECK-NEXT: 46. 1 2.0 2.0 27.0 ld a0, 0(a1)
+# CHECK-NEXT: 47. 1 2.0 2.0 27.0 lbu a0, 0(a1)
+# CHECK-NEXT: 48. 1 2.0 2.0 26.0 lhu a0, 0(a1)
+# CHECK-NEXT: 49. 1 1.0 1.0 27.0 lwu a0, 0(a1)
+# CHECK-NEXT: 50. 1 7.0 0.0 23.0 sb a0, 0(a1)
+# CHECK-NEXT: 51. 1 7.0 0.0 23.0 sh a0, 0(a1)
+# CHECK-NEXT: 52. 1 7.0 0.0 23.0 sw a0, 0(a1)
+# CHECK-NEXT: 53. 1 7.0 0.0 23.0 sd a0, 0(a1)
+# CHECK-NEXT: 1 14.2 0.3 6.4 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s
new file mode 100644
index 0000000000000..ac95fce7e614a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s
@@ -0,0 +1,100 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
+
+lb a0, 0(a1)
+lh a0, 0(a1)
+lw a0, 0(a1)
+ld a0, 0(a1)
+lbu a0, 0(a1)
+lhu a0, 0(a1)
+lwu a0, 0(a1)
+
+flw fa0, 0(a1)
+fld fa0, 0(a1)
+
+sb a0, 0(a1)
+sh a0, 0(a1)
+sw a0, 0(a1)
+sd a0, 0(a1)
+
+fsw fa0, 0(a1)
+fsd fa0, 0(a1)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 15
+# CHECK-NEXT: Total Cycles: 15
+# CHECK-NEXT: Total uOps: 15
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 1.00
+# CHECK-NEXT: Block RThroughput: 3.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 6 0.33 * lb a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lh a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lw a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * ld a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lbu a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lhu a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * lwu a0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * flw fa0, 0(a1)
+# CHECK-NEXT: 1 6 0.33 * fld fa0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sb a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sh a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sw a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * sd a0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * fsw fa0, 0(a1)
+# CHECK-NEXT: 1 4 0.25 * fsd fa0, 0(a1)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - - - - - - - 3.00 3.00 3.00 1.00 1.00 2.00 2.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lb a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - lh a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lw a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - ld a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lbu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lhu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - lwu a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - flw fa0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - fld fa0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 sb a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - sh a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - sw a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - sd a0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 fsw fa0, 0(a1)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - fsd fa0, 0(a1)
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
new file mode 100644
index 0000000000000..7665598ab198e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
@@ -0,0 +1,75 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -timeline -iterations=1 < %s | FileCheck %s
+
+ld a1, 0(a0)
+addi a2, a1, 1
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 2
+# CHECK-NEXT: Total Cycles: 9
+# CHECK-NEXT: Total uOps: 2
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.22
+# CHECK-NEXT: IPC: 0.22
+# CHECK-NEXT: Block RThroughput: 0.3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 6 0.33 * ld a1, 0(a0)
+# CHECK-NEXT: 1 1 0.25 addi a2, a1, 1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - ld a1, 0(a0)
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - addi a2, a1, 1
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 012345678
+
+# CHECK: [0,0] DeeeeeeER ld a1, 0(a0)
+# CHECK-NEXT: [0,1] D====eE-R addi a2, a1, 1
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld a1, 0(a0)
+# CHECK-NEXT: 1. 1 5.0 0.0 1.0 addi a2, a1, 1
+# CHECK-NEXT: 1 3.0 0.5 0.5 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
new file mode 100644
index 0000000000000..6c3ffe9f2ff8e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
@@ -0,0 +1,75 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -timeline -iterations=1 < %s | FileCheck %s
+
+fld fa1, 0(a0)
+fadd.s fa2, fa1, fa3
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 2
+# CHECK-NEXT: Total Cycles: 10
+# CHECK-NEXT: Total uOps: 2
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 0.20
+# CHECK-NEXT: IPC: 0.20
+# CHECK-NEXT: Block RThroughput: 0.3
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 6 0.33 * fld fa1, 0(a0)
+# CHECK-NEXT: 1 1 0.33 fadd.s fa2, fa1, fa3
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - 1.00 - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - fld fa1, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fadd.s fa2, fa1, fa3
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 0123456789
+
+# CHECK: [0,0] DeeeeeeER. fld fa1, 0(a0)
+# CHECK-NEXT: [0,1] D======eER fadd.s fa2, fa1, fa3
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 fld fa1, 0(a0)
+# CHECK-NEXT: 1. 1 7.0 0.0 0.0 fadd.s fa2, fa1, fa3
+# CHECK-NEXT: 1 4.0 0.5 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s
new file mode 100644
index 0000000000000..1b36ac96d1fa8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s
@@ -0,0 +1,74 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
+
+mul a0, a1, a2
+mulh a0, a1, a2
+mulhsu a0, a1, a2
+mulhu a0, a1, a2
+mulw a0, a1, a2
+
+fmul.s fa0, fa1, fa2
+fmul.d fa0, fa1, fa2
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 7
+# CHECK-NEXT: Total Cycles: 7
+# CHECK-NEXT: Total uOps: 7
+
+# CHECK: Dispatch Width: 6
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 1.00
+# CHECK-NEXT: Block RThroughput: 2.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 2 0.50 mul a0, a1, a2
+# CHECK-NEXT: 1 2 0.50 mulh a0, a1, a2
+# CHECK-NEXT: 1 2 0.50 mulhsu a0, a1, a2
+# CHECK-NEXT: 1 2 0.50 mulhu a0, a1, a2
+# CHECK-NEXT: 1 2 0.50 mulw a0, a1, a2
+# CHECK-NEXT: 1 3 0.33 fmul.s fa0, fa1, fa2
+# CHECK-NEXT: 1 3 0.33 fmul.d fa0, fa1, fa2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 2.00 3.00 - - - - - - - - 1.00 - 1.00 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mul a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulh a0, a1, a2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulhsu a0, a1, a2
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulhu a0, a1, a2
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulw a0, a1, a2
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmul.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmul.d fa0, fa1, fa2
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/cascade-fma.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s
rename to llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/cascade-fma.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/gpr-bypass.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s
rename to llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/gpr-bypass.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/load-to-alu.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s
rename to llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/load-to-alu.s
>From bbab42d7261df124f0f12f867d55c255993be9a2 Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Thu, 2 Apr 2026 17:42:41 +0800
Subject: [PATCH 03/10] [RISCV] Update XiangShan Kunminghu core documentation
links
Update the XiangShan Kunminghu core documentation links to point to the latest official documentation and user guide.
Co-Authored-By: Chyaka <lilium23187 at gmail.com>
Co-Authored-By: Bhe6669 <hebo at bosc.ac.cn>
Co-Authored-By: Tang Haojin <tanghaojin at outlook.com>
Co-authored-by: buggfg <wangyingying at bosc.ac.cn>
---
llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
index 52a52c99c2245..7602451aedd4a 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -13,13 +13,8 @@
// and the Beijing Institute of Open Source Chip (BOSC),
// with a focus on achieving higher performance.
// Source: https://github.com/OpenXiangShan/XiangShan
-// Documentation: https://github.com/OpenXiangShan/XiangShan-doc
-
-//===----------------------------------------------------------------------===//
-// KunMingHu core supports "RV64IMAFDCV_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh
-// _zksed_zksh_svinval_zicbom_zicboz_zicsr_zifencei"
-// then floating-point SEW can only be 64 and 32, not 16 and 8.
-//===----------------------------------------------------------------------===//
+// Documentation: https://docs.xiangshan.cc/projects/design/en/latest/
+// User Guide: https://docs.xiangshan.cc/projects/user-guide/en/latest/
def XiangShanKunMingHuModel : SchedMachineModel {
let IssueWidth = 6; // 6-way decode and dispatch
>From ae76514009f126cec37c4f204eb295d7f9efee1d Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Thu, 28 May 2026 13:13:47 +0700
Subject: [PATCH 04/10] [RISCV] Overhaul Kunminghu scheduling model and update
MCA tests.
Co-Authored-By: Chyaka <lilium23187 at gmail.com>
Co-Authored-By: Bhe6669 <hebo at bosc.ac.cn>
Co-Authored-By: Tang Haojin <tanghaojin at outlook.com>
Co-authored-by: buggfg <wangyingying at bosc.ac.cn>
---
llvm/lib/Target/RISCV/RISCV.td | 2 +-
.../RISCV/RISCVSchedXiangShanKunMingHu.td | 290 ++++++++++------
.../RISCV/XiangShan-Kunminghu/atomic.test | 255 ++++++++++++++
.../RISCV/XiangShan-Kunminghu/bitmanip.s | 179 ----------
.../RISCV/XiangShan-Kunminghu/cascade-fma.s | 8 +-
.../RISCV/XiangShan-Kunminghu/div-fdiv.s | 89 ++---
.../XiangShan-Kunminghu/floating-point.test | 199 +++++++++++
.../RISCV/XiangShan-Kunminghu/fpr-bypass.s | 218 +-----------
.../RISCV/XiangShan-Kunminghu/gpr-bypass.s | 325 +-----------------
.../RISCV/XiangShan-Kunminghu/integer.test | 191 ++++++++++
.../RISCV/XiangShan-Kunminghu/load-store.s | 100 ------
.../RISCV/XiangShan-Kunminghu/load-to-alu.s | 18 +-
.../RISCV/XiangShan-Kunminghu/load-to-fpu.s | 18 +-
.../XiangShan-Kunminghu/mul-div-rv32.test | 95 +++++
.../RISCV/XiangShan-Kunminghu/mul-div.test | 105 ++++++
.../RISCV/XiangShan-Kunminghu/mul-fmul.s | 74 ----
.../RISCV/XiangShan-Kunminghu/zba.test | 95 +++++
.../RISCV/XiangShan-Kunminghu/zbb.test | 127 +++++++
.../RISCV/XiangShan-Kunminghu/zbc.test | 85 +++++
.../RISCV/XiangShan-Kunminghu/zbs.test | 95 +++++
.../RISCV/XiangShan-Kunminghu/zfh.test | 109 ++++++
.../RISCV/XiangShan-Kunminghu/zfhmin.test | 99 ++++++
.../RISCV/XiangShan-Kunminghu/zicond.test | 87 +++++
.../cascade-fma.s | 0
.../gpr-bypass.s | 0
.../load-to-alu.s | 0
26 files changed, 1822 insertions(+), 1041 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/atomic.test
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/floating-point.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/integer.test
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div-rv32.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div.test
delete mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zba.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbb.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbc.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbs.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfh.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfhmin.test
create mode 100644 llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zicond.test
rename llvm/test/tools/llvm-mca/RISCV/{XiangShan-Nanhu => XiangShan}/cascade-fma.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/{XiangShan-Nanhu => XiangShan}/gpr-bypass.s (100%)
rename llvm/test/tools/llvm-mca/RISCV/{XiangShan-Nanhu => XiangShan}/load-to-alu.s (100%)
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index d21d3dae20afe..4a757869300ca 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -66,8 +66,8 @@ include "RISCVSchedSyntacoreSCR1.td"
include "RISCVSchedSyntacoreSCR345.td"
include "RISCVSchedSyntacoreSCR7.td"
include "RISCVSchedTTAscalonX.td"
-include "RISCVSchedXiangShanNanHu.td"
include "RISCVSchedXiangShanKunMingHu.td"
+include "RISCVSchedXiangShanNanHu.td"
//===----------------------------------------------------------------------===//
// RISC-V processors supported.
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
index 7602451aedd4a..1b6f38a64bada 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -1,4 +1,4 @@
-//==- RISCVSchedXiangShanKunMingHu.td - XiangShanKunMingHu Scheduling Defs -*- tablegen -*-=//
+//==- RISCVSchedXiangShanKunMingHu.td - KMH Scheduling Defs -*- tablegen -*-=//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -7,60 +7,89 @@
//===----------------------------------------------------------------------===//
// The XiangShan is a high-performance open-source RISC-V processor project
-// initiated by the Institute of Computing Technology(ICT), Chinese Academy of Sciences(CAS).
+// initiated by the Institute of Computing Technology(ICT),
+// Chinese Academy of Sciences(CAS).
// The KunMingHu architecture is its third-generation derivative,
-// developed by the Institute of Computing Technology, Chinese Academy of Sciences
+// developed by the Institute of Computing Technology(ICT),
+// Chinese Academy of Sciences(CAS)
// and the Beijing Institute of Open Source Chip (BOSC),
// with a focus on achieving higher performance.
// Source: https://github.com/OpenXiangShan/XiangShan
// Documentation: https://docs.xiangshan.cc/projects/design/en/latest/
// User Guide: https://docs.xiangshan.cc/projects/user-guide/en/latest/
+// Typical Configurations & Instruction Latency:
+// https://docs.xiangshan.cc/projects/user-guide/en/latest/
+// kunminghu-v3/typical-configuration/
def XiangShanKunMingHuModel : SchedMachineModel {
let IssueWidth = 6; // 6-way decode and dispatch
- let MicroOpBufferSize = 256;
+ let MicroOpBufferSize = 160; // ROB size
let LoopMicroOpBufferSize = 48; // Instruction queue size
- let LoadLatency = 6;
+ let LoadLatency = 4;
let MispredictPenalty = 13; // Based on estimate of pipeline depth.
let CompleteModel = 0;
- let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZkr, HasVInstructions,
+ let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZkr,
+ HasVInstructions,
HasVInstructionsI64];
}
let SchedModel = XiangShanKunMingHuModel in {
// Define each kind of processor resource and number available.
-/// Pipline
+// Individual pipeline resources (no BufferSize - they share Issue Queues)
+// Integer execution units
+def XSPipeALU0 : ProcResource<1>; // ALU, MUL, BKU
+def XSPipeALU1 : ProcResource<1>; // ALU, MUL, BKU
+def XSPipeALU2 : ProcResource<1>; // ALU
+def XSPipeALU3 : ProcResource<1>; // ALU
+
+def XSPipeBJU0 : ProcResource<1>; // BRU, JMP
+def XSPipeBJU1 : ProcResource<1>; // BRU, JMP
+def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, I2V, VSet
+def XSPipeBJU3 : ProcResource<1>; // CSR, Fence, DIV
+
+// Floating-point execution units
+def XSPipeFEX0 : ProcResource<1>; // FALU, FMA, FCVT, F2V
+def XSPipeFEX1 : ProcResource<1>; // FDIV
+def XSPipeFEX2 : ProcResource<1>; // FALU, FMA
+def XSPipeFEX3 : ProcResource<1>; // FDIV
+def XSPipeFEX4 : ProcResource<1>; // FALU, FMA
+
+// Parent groups containing all resources to satisfy TableGen overlap rules
+def XSPipeGroupInt : ProcResGroup<[XSPipeALU0, XSPipeALU1,
+ XSPipeALU2, XSPipeALU3,
+ XSPipeBJU0, XSPipeBJU1,
+ XSPipeBJU2, XSPipeBJU3]>;
+def XSPipeGroupFP : ProcResGroup<[XSPipeFEX0, XSPipeFEX1,
+ XSPipeFEX2, XSPipeFEX3, XSPipeFEX4]>;
+
+// Issue Queue groups with BufferSize for llvm-mca buffer tracking
+// Integer Issue Queues: ALU + BJU share the same IQ
let BufferSize = 24 in {
- // Integer
- def XSPipeALU0 : ProcResource<1>; // ALU, MUL, BKU
- def XSPipeALU1 : ProcResource<1>; // ALU, MUL, BKU
- def XSPipeALU2 : ProcResource<1>; // ALU
- def XSPipeALU3 : ProcResource<1>; // ALU
-
- def XSPipeBJU0 : ProcResource<1>; // BRU, JMP
- def XSPipeBJU1 : ProcResource<1>; // BRU, JMP
- def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, I2V, VSet
- def XSPipeBJU3 : ProcResource<1>; // CSR, Fence, DIV
+ def XSPipeIntIQ0 : ProcResGroup<[XSPipeALU0, XSPipeBJU0]>;
+ def XSPipeIntIQ1 : ProcResGroup<[XSPipeALU1, XSPipeBJU1]>;
+ def XSPipeIntIQ2 : ProcResGroup<[XSPipeALU2, XSPipeBJU2]>;
+ def XSPipeIntIQ3 : ProcResGroup<[XSPipeALU3, XSPipeBJU3]>;
}
+// Floating-point Issue Queues:
let BufferSize = 18 in {
- // Floating-point
- def XSPipeFEX0 : ProcResource<1>; // FALU, FMA, FCVT, F2V
- def XSPipeFEX1 : ProcResource<1>; // FDIV
- def XSPipeFEX2 : ProcResource<1>; // FALU, FMA
- def XSPipeFEX3 : ProcResource<1>; // FDIV
- def XSPipeFEX4 : ProcResource<1>; // FALU, FMA
+ def XSPipeFpIQ0 : ProcResGroup<[XSPipeFEX0, XSPipeFEX1]>;
+ def XSPipeFpIQ1 : ProcResGroup<[XSPipeFEX2, XSPipeFEX3]>;
+ def XSPipeFpIQ2 : ProcResGroup<[XSPipeFEX4]>;
}
-let BufferSize = 16 in {
- // Load and store
- def XSPipeLDU : ProcResource<3>; // LDU
+// Memory execution resources.
+def XSPipeLDU : ProcResource<3>; // LDU
+def XSPipeSTA : ProcResource<2>; // STA
+def XSPipeSTD : ProcResource<2>; // STD
- def XSPipeSTA : ProcResource<2>; // STA
- def XSPipeSTD : ProcResource<2>; // STD
-}
+// One shared memory issue queue for LDU/STA/STD.
+let BufferSize = 16 in
+def XSPipeMemIQ : ProcResGroup<[XSPipeLDU, XSPipeSTA, XSPipeSTD]>;
-def XSPipeGroupALU : ProcResGroup<[XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3]>;
+// Instruction dispatch groups for scheduling
+def XSPipeGroupALU : ProcResGroup<[XSPipeALU0, XSPipeALU1, XSPipeALU2,
+ XSPipeALU3]>;
def XSPipeGroupMUL : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
def XSPipeGroupBKU : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
def XSPipeGroupBRU : ProcResGroup<[XSPipeBJU0, XSPipeBJU1, XSPipeBJU2]>;
@@ -69,8 +98,6 @@ def XSPipeGroupFALU : ProcResGroup<[XSPipeFEX0, XSPipeFEX2, XSPipeFEX4]>;
def XSPipeGroupFMA : ProcResGroup<[XSPipeFEX0, XSPipeFEX2, XSPipeFEX4]>;
def XSPipeGroupFDIV : ProcResGroup<[XSPipeFEX1, XSPipeFEX3]>;
-def XSPipeGroupSTU : ProcResGroup<[XSPipeSTA, XSPipeSTD]>;
-
//===----------------------------------------------------------------------===//
@@ -87,40 +114,30 @@ def : WriteRes<WriteShiftImm, [XSPipeGroupALU]>;
def : WriteRes<WriteShiftReg32, [XSPipeGroupALU]>;
def : WriteRes<WriteShiftReg, [XSPipeGroupALU]>;
-// Integer multiplication
-let Latency = 2 in {
+// IMUL
+let Latency = 3 in {
def : WriteRes<WriteIMul, [XSPipeGroupMUL]>;
def : WriteRes<WriteIMul32, [XSPipeGroupMUL]>;
}
-// Integer division
-// Worst case latency is used.
-// The latency of integer division ranges from 4 to 20.
-let Latency = 20, ReleaseAtCycles = [20] in {
+// IDIV
+let Latency = 11, ReleaseAtCycles = [11] in {
def : WriteRes<WriteIDiv32, [XSPipeBJU3]>;
- def : WriteRes<WriteIDiv, [XSPipeBJU3]>;
def : WriteRes<WriteIRem32, [XSPipeBJU3]>;
+}
+let Latency = 19, ReleaseAtCycles = [19] in {
+ def : WriteRes<WriteIDiv, [XSPipeBJU3]>;
def : WriteRes<WriteIRem, [XSPipeBJU3]>;
}
-// Memory
+// LOAD
let Latency = 4 in {
- def : WriteRes<WriteSTB, [XSPipeGroupSTU]>;
- def : WriteRes<WriteSTH, [XSPipeGroupSTU]>;
- def : WriteRes<WriteSTW, [XSPipeGroupSTU]>;
- def : WriteRes<WriteSTD, [XSPipeGroupSTU]>;
- def : WriteRes<WriteFST32, [XSPipeGroupSTU]>;
- def : WriteRes<WriteFST64, [XSPipeGroupSTU]>;
- def : WriteRes<WriteAtomicSTW, [XSPipeGroupSTU]>;
- def : WriteRes<WriteAtomicSTD, [XSPipeGroupSTU]>;
-}
-
-let Latency = 6 in {
def : WriteRes<WriteLDB, [XSPipeLDU]>;
def : WriteRes<WriteLDH, [XSPipeLDU]>;
def : WriteRes<WriteLDW, [XSPipeLDU]>;
def : WriteRes<WriteLDD, [XSPipeLDU]>;
+ def : WriteRes<WriteFLD16, [XSPipeLDU]>;
def : WriteRes<WriteFLD32, [XSPipeLDU]>;
def : WriteRes<WriteFLD64, [XSPipeLDU]>;
@@ -130,94 +147,135 @@ let Latency = 6 in {
def : WriteRes<WriteAtomicLDD, [XSPipeLDU]>;
}
-let Latency = 1 in {
- def : WriteRes<WriteFAdd32, [XSPipeGroupFALU]>;
- def : WriteRes<WriteFAdd64, [XSPipeGroupFALU]>;
+// STORE
+class XSWriteStore<SchedWrite write>
+ : WriteRes<write, [XSPipeSTA, XSPipeSTD]> {
+ let Latency = 4;
+ let ReleaseAtCycles = [1, 1];
}
+def : XSWriteStore<WriteSTB>;
+def : XSWriteStore<WriteSTH>;
+def : XSWriteStore<WriteSTW>;
+def : XSWriteStore<WriteSTD>;
+def : XSWriteStore<WriteFST16>;
+def : XSWriteStore<WriteFST32>;
+def : XSWriteStore<WriteFST64>;
+def : XSWriteStore<WriteAtomicSTW>;
+def : XSWriteStore<WriteAtomicSTD>;
+
+// FADD
+def : WriteRes<WriteFAdd16, [XSPipeGroupFALU]>;
+def : WriteRes<WriteFAdd32, [XSPipeGroupFALU]>;
+def : WriteRes<WriteFAdd64, [XSPipeGroupFALU]>;
+
let Latency = 2 in {
+ def : WriteRes<WriteFCmp16, [XSPipeGroupFALU]>;
def : WriteRes<WriteFCmp32, [XSPipeGroupFALU]>;
def : WriteRes<WriteFCmp64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFMinMax16, [XSPipeGroupFALU]>;
def : WriteRes<WriteFMinMax32, [XSPipeGroupFALU]>;
def : WriteRes<WriteFMinMax64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFClass16, [XSPipeGroupFALU]>;
def : WriteRes<WriteFClass32, [XSPipeGroupFALU]>;
def : WriteRes<WriteFClass64, [XSPipeGroupFALU]>;
+ def : WriteRes<WriteFSGNJ16, [XSPipeGroupFALU]>;
def : WriteRes<WriteFSGNJ32, [XSPipeGroupFALU]>;
def : WriteRes<WriteFSGNJ64, [XSPipeGroupFALU]>;
}
-let Latency = 3 in {
+// FMUL
+let Latency = 4 in {
+ def : WriteRes<WriteFMul16, [XSPipeGroupFMA]>;
def : WriteRes<WriteFMul32, [XSPipeGroupFMA]>;
def : WriteRes<WriteFMul64, [XSPipeGroupFMA]>;
+ def : WriteRes<WriteFMA16, [XSPipeGroupFMA]>;
def : WriteRes<WriteFMA32, [XSPipeGroupFMA]>;
def : WriteRes<WriteFMA64, [XSPipeGroupFMA]>;
}
// FDIV
-let Latency = 10 in {
+let Latency = 9, ReleaseAtCycles = [9] in {
+ def : WriteRes<WriteFDiv16, [XSPipeGroupFDIV]>;
def : WriteRes<WriteFDiv32, [XSPipeGroupFDIV]>;
- def : WriteRes<WriteFSqrt32, [XSPipeGroupFDIV]>;
}
-let Latency = 15 in {
+let Latency = 14, ReleaseAtCycles = [14] in {
def : WriteRes<WriteFDiv64, [XSPipeGroupFDIV]>;
+}
+
+// FSQRT
+let Latency = 10, ReleaseAtCycles = [10] in {
+ def : WriteRes<WriteFSqrt16, [XSPipeGroupFDIV]>;
+ def : WriteRes<WriteFSqrt32, [XSPipeGroupFDIV]>;
+}
+let Latency = 16, ReleaseAtCycles = [16] in {
def : WriteRes<WriteFSqrt64, [XSPipeGroupFDIV]>;
}
-// FCVT
-let Latency = 2 in {
+let Latency = 3 in {
+ // FCVT (F2I)
+ def : WriteRes<WriteFCvtF16ToI32, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF16ToI64, [XSPipeFEX0]>;
def : WriteRes<WriteFCvtF32ToI32, [XSPipeFEX0]>;
def : WriteRes<WriteFCvtF32ToI64, [XSPipeFEX0]>;
def : WriteRes<WriteFCvtF64ToI32, [XSPipeFEX0]>;
def : WriteRes<WriteFCvtF64ToI64, [XSPipeFEX0]>;
- def : WriteRes<WriteFCvtF64ToF32, [XSPipeFEX0]>;
- def : WriteRes<WriteFCvtF32ToF64, [XSPipeFEX0]>;
- def : WriteRes<WriteFMovF64ToI64, [XSPipeFEX0]>;
- def : WriteRes<WriteFMovF32ToI32, [XSPipeFEX0]>;
-}
-
-// I2V
-let Latency = 0 in {
- def : WriteRes<WriteFMovI64ToF64, [XSPipeBJU2]>;
- def : WriteRes<WriteFMovI32ToF32, [XSPipeBJU2]>;
-}
-// I2F
-let Latency = 2 in {
+ // FCVT (F2F)
+ def : WriteRes<WriteFCvtF16ToF32, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF16ToF64, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF32ToF16, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF32ToF64, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF64ToF16, [XSPipeFEX0]>;
+ def : WriteRes<WriteFCvtF64ToF32, [XSPipeFEX0]>;
+
+ // FCVT (I2F)
+ def : WriteRes<WriteFCvtI32ToF16, [XSPipeBJU2]>;
def : WriteRes<WriteFCvtI32ToF32, [XSPipeBJU2]>;
- def : WriteRes<WriteFCvtI64ToF32, [XSPipeBJU2]>;
def : WriteRes<WriteFCvtI32ToF64, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI64ToF16, [XSPipeBJU2]>;
+ def : WriteRes<WriteFCvtI64ToF32, [XSPipeBJU2]>;
def : WriteRes<WriteFCvtI64ToF64, [XSPipeBJU2]>;
}
-/// Zb*
-let Latency = 1 in {
- // Zba
- def : WriteRes<WriteSHXADD, [XSPipeGroupALU]>;
- def : WriteRes<WriteSHXADD32, [XSPipeGroupALU]>;
-
- // Zbb
- def : WriteRes<WriteRotateImm, [XSPipeGroupALU]>;
- def : WriteRes<WriteRotateImm32, [XSPipeGroupALU]>;
- def : WriteRes<WriteRotateReg, [XSPipeGroupALU]>;
- def : WriteRes<WriteRotateReg32, [XSPipeGroupALU]>;
- def : WriteRes<WriteREV8, [XSPipeGroupALU]>;
- def : WriteRes<WriteORCB, [XSPipeGroupALU]>;
- def : WriteRes<WriteIMinMax, [XSPipeGroupALU]>;
-
- // Zbs
- def : WriteRes<WriteSingleBit, [XSPipeGroupALU]>;
- def : WriteRes<WriteSingleBitImm, [XSPipeGroupALU]>;
- def : WriteRes<WriteBEXT, [XSPipeGroupALU]>;
- def : WriteRes<WriteBEXTI, [XSPipeGroupALU]>;
-
- // Zbkb
- def : WriteRes<WriteBREV8, [XSPipeGroupALU]>;
- def : WriteRes<WritePACK, [XSPipeGroupALU]>;
- def : WriteRes<WritePACK32, [XSPipeGroupALU]>;
- def : WriteRes<WriteZIP, [XSPipeGroupALU]>;
+// FMV (F2I)
+let Latency = 3 in {
+ def : WriteRes<WriteFMovF16ToI16, [XSPipeFEX0]>;
+ def : WriteRes<WriteFMovF32ToI32, [XSPipeFEX0]>;
+ def : WriteRes<WriteFMovF64ToI64, [XSPipeFEX0]>;
}
+// FMV (I2F)
+def : WriteRes<WriteFMovI16ToF16, [XSPipeBJU2]>;
+def : WriteRes<WriteFMovI64ToF64, [XSPipeBJU2]>;
+def : WriteRes<WriteFMovI32ToF32, [XSPipeBJU2]>;
-let Latency = 2 in {
+/// Zb*
+// Zba
+def : WriteRes<WriteSHXADD, [XSPipeGroupALU]>;
+def : WriteRes<WriteSHXADD32, [XSPipeGroupALU]>;
+
+// Zbb
+def : WriteRes<WriteRotateImm, [XSPipeGroupALU]>;
+def : WriteRes<WriteRotateImm32, [XSPipeGroupALU]>;
+def : WriteRes<WriteRotateReg, [XSPipeGroupALU]>;
+def : WriteRes<WriteRotateReg32, [XSPipeGroupALU]>;
+def : WriteRes<WriteREV8, [XSPipeGroupALU]>;
+def : WriteRes<WriteORCB, [XSPipeGroupALU]>;
+def : WriteRes<WriteIMinMax, [XSPipeGroupALU]>;
+
+// Zbs
+def : WriteRes<WriteSingleBit, [XSPipeGroupALU]>;
+def : WriteRes<WriteSingleBitImm, [XSPipeGroupALU]>;
+def : WriteRes<WriteBEXT, [XSPipeGroupALU]>;
+def : WriteRes<WriteBEXTI, [XSPipeGroupALU]>;
+
+// Zbkb
+def : WriteRes<WriteBREV8, [XSPipeGroupALU]>;
+def : WriteRes<WritePACK, [XSPipeGroupALU]>;
+def : WriteRes<WritePACK32, [XSPipeGroupALU]>;
+def : WriteRes<WriteZIP, [XSPipeGroupALU]>;
+
+let Latency = 3 in {
// Zbb
def : WriteRes<WriteCLZ, [XSPipeGroupBKU]>;
def : WriteRes<WriteCLZ32, [XSPipeGroupBKU]>;
@@ -277,40 +335,61 @@ def : ReadAdvance<ReadAtomicSTW, 0>;
def : ReadAdvance<ReadAtomicSTD, 0>;
def : ReadAdvance<ReadFStoreData, 0>;
def : ReadAdvance<ReadFMemBase, 0>;
+def : ReadAdvance<ReadFAdd16, 0>;
def : ReadAdvance<ReadFAdd32, 0>;
def : ReadAdvance<ReadFAdd64, 0>;
+def : ReadAdvance<ReadFMul16, 0>;
def : ReadAdvance<ReadFMul32, 0>;
def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA16, 0>;
def : ReadAdvance<ReadFMA32, 0>;
-def : ReadAdvance<ReadFMA32Addend, 0>;
def : ReadAdvance<ReadFMA64, 0>;
+def : ReadAdvance<ReadFMA16Addend, 0>;
+def : ReadAdvance<ReadFMA32Addend, 0>;
def : ReadAdvance<ReadFMA64Addend, 0>;
+def : ReadAdvance<ReadFDiv16, 0>;
def : ReadAdvance<ReadFDiv32, 0>;
def : ReadAdvance<ReadFDiv64, 0>;
+def : ReadAdvance<ReadFSqrt16, 0>;
def : ReadAdvance<ReadFSqrt32, 0>;
def : ReadAdvance<ReadFSqrt64, 0>;
+def : ReadAdvance<ReadFCmp16, 0>;
def : ReadAdvance<ReadFCmp32, 0>;
def : ReadAdvance<ReadFCmp64, 0>;
+def : ReadAdvance<ReadFSGNJ16, 0>;
def : ReadAdvance<ReadFSGNJ32, 0>;
def : ReadAdvance<ReadFSGNJ64, 0>;
+def : ReadAdvance<ReadFMinMax16, 0>;
def : ReadAdvance<ReadFMinMax32, 0>;
def : ReadAdvance<ReadFMinMax64, 0>;
+def : ReadAdvance<ReadFClass16, 0>;
+def : ReadAdvance<ReadFClass32, 0>;
+def : ReadAdvance<ReadFClass64, 0>;
+def : ReadAdvance<ReadFCvtF16ToI32, 0>;
+def : ReadAdvance<ReadFCvtF16ToI64, 0>;
def : ReadAdvance<ReadFCvtF32ToI32, 0>;
def : ReadAdvance<ReadFCvtF32ToI64, 0>;
def : ReadAdvance<ReadFCvtF64ToI32, 0>;
def : ReadAdvance<ReadFCvtF64ToI64, 0>;
+def : ReadAdvance<ReadFCvtI32ToF16, 0>;
def : ReadAdvance<ReadFCvtI32ToF32, 0>;
def : ReadAdvance<ReadFCvtI32ToF64, 0>;
+def : ReadAdvance<ReadFCvtI64ToF16, 0>;
def : ReadAdvance<ReadFCvtI64ToF32, 0>;
def : ReadAdvance<ReadFCvtI64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF16ToF32, 0>;
+def : ReadAdvance<ReadFCvtF16ToF64, 0>;
+def : ReadAdvance<ReadFCvtF32ToF16, 0>;
def : ReadAdvance<ReadFCvtF32ToF64, 0>;
+def : ReadAdvance<ReadFCvtF64ToF16, 0>;
def : ReadAdvance<ReadFCvtF64ToF32, 0>;
+def : ReadAdvance<ReadFMovF16ToI16, 0>;
def : ReadAdvance<ReadFMovF32ToI32, 0>;
-def : ReadAdvance<ReadFMovI32ToF32, 0>;
def : ReadAdvance<ReadFMovF64ToI64, 0>;
+def : ReadAdvance<ReadFMovI16ToF16, 0>;
+def : ReadAdvance<ReadFMovI32ToF32, 0>;
def : ReadAdvance<ReadFMovI64ToF64, 0>;
-def : ReadAdvance<ReadFClass32, 0>;
-def : ReadAdvance<ReadFClass64, 0>;
+
/// B extension
// Zba
@@ -348,7 +427,6 @@ def : ReadAdvance<ReadXPERM, 0>;
defm : UnsupportedSchedQ;
defm : UnsupportedSchedV;
defm : UnsupportedSchedZfa;
-defm : UnsupportedSchedZfhmin;
defm : UnsupportedSchedSFB;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedXsf;
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/atomic.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/atomic.test
new file mode 100644
index 0000000000000..7867e8315be35
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/atomic.test
@@ -0,0 +1,255 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/atomic.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 4 0.33 * 2 XSPipeLDU,XSPipeMemIQ LR_W lr.w t0, (t1)
+# CHECK-NEXT: 1 4 0.33 * 2 XSPipeLDU,XSPipeMemIQ LR_W_AQ lr.w.aq t1, (t2)
+# CHECK-NEXT: 1 4 0.33 * 2 XSPipeLDU,XSPipeMemIQ LR_W_RL lr.w.rl t2, (t3)
+# CHECK-NEXT: 1 4 0.33 * 2 XSPipeLDU,XSPipeMemIQ LR_W_AQRL lr.w.aqrl t3, (t4)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SC_W sc.w t6, t5, (t4)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SC_W_AQ sc.w.aq t5, t4, (t3)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SC_W_RL sc.w.rl t4, t3, (t2)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SC_W_AQRL sc.w.aqrl t3, t2, (t1)
+# CHECK-NEXT: 1 4 0.33 * 2 XSPipeLDU,XSPipeMemIQ LR_D lr.d t0, (t1)
+# CHECK-NEXT: 1 4 0.33 * 2 XSPipeLDU,XSPipeMemIQ LR_D_AQ lr.d.aq t1, (t2)
+# CHECK-NEXT: 1 4 0.33 * 2 XSPipeLDU,XSPipeMemIQ LR_D_RL lr.d.rl t2, (t3)
+# CHECK-NEXT: 1 4 0.33 * 2 XSPipeLDU,XSPipeMemIQ LR_D_AQRL lr.d.aqrl t3, (t4)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SC_D sc.d t6, t5, (t4)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SC_D_AQ sc.d.aq t5, t4, (t3)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SC_D_RL sc.d.rl t4, t3, (t2)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SC_D_AQRL sc.d.aqrl t3, t2, (t1)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOSWAP_W amoswap.w a4, ra, (s0)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOADD_W amoadd.w a1, a2, (a3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOXOR_W amoxor.w a2, a3, (a4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOAND_W amoand.w a3, a4, (a5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOOR_W amoor.w a4, a5, (a6)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMIN_W amomin.w a5, a6, (a7)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAX_W amomax.w s7, s6, (s5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMINU_W amominu.w s6, s5, (s4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAXU_W amomaxu.w s5, s4, (s3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOSWAP_W_AQ amoswap.w.aq a4, ra, (s0)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOADD_W_AQ amoadd.w.aq a1, a2, (a3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOXOR_W_AQ amoxor.w.aq a2, a3, (a4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOAND_W_AQ amoand.w.aq a3, a4, (a5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOOR_W_AQ amoor.w.aq a4, a5, (a6)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMIN_W_AQ amomin.w.aq a5, a6, (a7)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAX_W_AQ amomax.w.aq s7, s6, (s5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMINU_W_AQ amominu.w.aq s6, s5, (s4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAXU_W_AQ amomaxu.w.aq s5, s4, (s3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOSWAP_W_RL amoswap.w.rl a4, ra, (s0)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOADD_W_RL amoadd.w.rl a1, a2, (a3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOXOR_W_RL amoxor.w.rl a2, a3, (a4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOAND_W_RL amoand.w.rl a3, a4, (a5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOOR_W_RL amoor.w.rl a4, a5, (a6)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMIN_W_RL amomin.w.rl a5, a6, (a7)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAX_W_RL amomax.w.rl s7, s6, (s5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMINU_W_RL amominu.w.rl s6, s5, (s4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAXU_W_RL amomaxu.w.rl s5, s4, (s3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOSWAP_W_AQRL amoswap.w.aqrl a4, ra, (s0)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOADD_W_AQRL amoadd.w.aqrl a1, a2, (a3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOXOR_W_AQRL amoxor.w.aqrl a2, a3, (a4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOAND_W_AQRL amoand.w.aqrl a3, a4, (a5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOOR_W_AQRL amoor.w.aqrl a4, a5, (a6)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMIN_W_AQRL amomin.w.aqrl a5, a6, (a7)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAX_W_AQRL amomax.w.aqrl s7, s6, (s5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMINU_W_AQRL amominu.w.aqrl s6, s5, (s4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAXU_W_AQRL amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOSWAP_D amoswap.d a4, ra, (s0)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOADD_D amoadd.d a1, a2, (a3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOXOR_D amoxor.d a2, a3, (a4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOAND_D amoand.d a3, a4, (a5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOOR_D amoor.d a4, a5, (a6)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMIN_D amomin.d a5, a6, (a7)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAX_D amomax.d s7, s6, (s5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMINU_D amominu.d s6, s5, (s4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAXU_D amomaxu.d s5, s4, (s3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOSWAP_D_AQ amoswap.d.aq a4, ra, (s0)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOADD_D_AQ amoadd.d.aq a1, a2, (a3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOXOR_D_AQ amoxor.d.aq a2, a3, (a4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOAND_D_AQ amoand.d.aq a3, a4, (a5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOOR_D_AQ amoor.d.aq a4, a5, (a6)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMIN_D_AQ amomin.d.aq a5, a6, (a7)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAX_D_AQ amomax.d.aq s7, s6, (s5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMINU_D_AQ amominu.d.aq s6, s5, (s4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAXU_D_AQ amomaxu.d.aq s5, s4, (s3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOSWAP_D_RL amoswap.d.rl a4, ra, (s0)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOADD_D_RL amoadd.d.rl a1, a2, (a3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOXOR_D_RL amoxor.d.rl a2, a3, (a4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOAND_D_RL amoand.d.rl a3, a4, (a5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOOR_D_RL amoor.d.rl a4, a5, (a6)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMIN_D_RL amomin.d.rl a5, a6, (a7)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAX_D_RL amomax.d.rl s7, s6, (s5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMINU_D_RL amominu.d.rl s6, s5, (s4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAXU_D_RL amomaxu.d.rl s5, s4, (s3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOSWAP_D_AQRL amoswap.d.aqrl a4, ra, (s0)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOADD_D_AQRL amoadd.d.aqrl a1, a2, (a3)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOXOR_D_AQRL amoxor.d.aqrl a2, a3, (a4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOAND_D_AQRL amoand.d.aqrl a3, a4, (a5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOOR_D_AQRL amoor.d.aqrl a4, a5, (a6)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMIN_D_AQRL amomin.d.aqrl a5, a6, (a7)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAX_D_AQRL amomax.d.aqrl s7, s6, (s5)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMINU_D_AQRL amominu.d.aqrl s6, s5, (s4)
+# CHECK-NEXT: 1 4 0.33 * * 2 XSPipeLDU,XSPipeMemIQ AMOMAXU_D_AQRL amomaxu.d.aqrl s5, s4, (s3)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - - - - - - - 26.67 26.67 26.67 4.00 4.00 4.00 4.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lr.w t0, (t1)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lr.w.aq t1, (t2)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lr.w.rl t2, (t3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lr.w.aqrl t3, (t4)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sc.w t6, t5, (t4)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sc.w.aq t5, t4, (t3)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sc.w.rl t4, t3, (t2)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sc.w.aqrl t3, t2, (t1)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lr.d t0, (t1)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lr.d.aq t1, (t2)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lr.d.rl t2, (t3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lr.d.aqrl t3, (t4)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sc.d t6, t5, (t4)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sc.d.aq t5, t4, (t3)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sc.d.rl t4, t3, (t2)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sc.d.aqrl t3, t2, (t1)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoswap.w a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoadd.w a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoxor.w a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoand.w a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoor.w a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomin.w a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomax.w s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amominu.w s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomaxu.w s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoswap.w.aq a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoadd.w.aq a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoxor.w.aq a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoand.w.aq a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoor.w.aq a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomin.w.aq a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomax.w.aq s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amominu.w.aq s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomaxu.w.aq s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoswap.w.rl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoadd.w.rl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoxor.w.rl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoand.w.rl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoor.w.rl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomin.w.rl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomax.w.rl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amominu.w.rl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomaxu.w.rl s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoswap.w.aqrl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoadd.w.aqrl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoxor.w.aqrl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoand.w.aqrl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoor.w.aqrl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomin.w.aqrl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomax.w.aqrl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amominu.w.aqrl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoswap.d a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoadd.d a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoxor.d a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoand.d a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoor.d a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomin.d a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomax.d s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amominu.d s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomaxu.d s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoswap.d.aq a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoadd.d.aq a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoxor.d.aq a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoand.d.aq a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoor.d.aq a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomin.d.aq a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomax.d.aq s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amominu.d.aq s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomaxu.d.aq s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoswap.d.rl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoadd.d.rl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoxor.d.rl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoand.d.rl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoor.d.rl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomin.d.rl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomax.d.rl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amominu.d.rl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomaxu.d.rl s5, s4, (s3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoswap.d.aqrl a4, ra, (s0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoadd.d.aqrl a1, a2, (a3)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoxor.d.aqrl a2, a3, (a4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoand.d.aqrl a3, a4, (a5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amoor.d.aqrl a4, a5, (a6)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomin.d.aqrl a5, a6, (a7)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomax.d.aqrl s7, s6, (s5)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amominu.d.aqrl s6, s5, (s4)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - amomaxu.d.aqrl s5, s4, (s3)
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s
deleted file mode 100644
index 924fc43a59df1..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/bitmanip.s
+++ /dev/null
@@ -1,179 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -mattr=+zba,+zbb,+zbs -iterations=1 < %s | FileCheck %s
-
-sh1add a0, a1, a2
-sh2add a0, a1, a2
-sh3add a0, a1, a2
-sh1add.uw a0, a1, a2
-sh2add.uw a0, a1, a2
-sh3add.uw a0, a1, a2
-add.uw a0, a1, a2
-slli.uw a0, a1, 1
-
-clz a0, a1
-clzw a0, a1
-ctz a0, a1
-ctzw a0, a1
-cpop a0, a1
-cpopw a0, a1
-
-andn a0, a1, a2
-orn a0, a1, a2
-xnor a0, a1, a2
-
-rol a0, a1, a2
-rolw a0, a1, a2
-ror a0, a1, a2
-rorw a0, a1, a2
-rori a0, a1, 1
-roriw a0, a1, 1
-
-min a0, a1, a2
-minu a0, a1, a2
-max a0, a1, a2
-maxu a0, a1, a2
-
-sext.b a0, a1
-sext.h a0, a1
-zext.h a0, a1
-
-rev8 a0, a1
-orc.b a0, a1
-
-bclr a0, a1, a2
-bclri a0, a1, 1
-bext a0, a1, a2
-bexti a0, a1, 1
-binv a0, a1, a2
-binvi a0, a1, 1
-bset a0, a1, a2
-bseti a0, a1, 1
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 40
-# CHECK-NEXT: Total Cycles: 13
-# CHECK-NEXT: Total uOps: 40
-
-# CHECK: Dispatch Width: 6
-# CHECK-NEXT: uOps Per Cycle: 3.08
-# CHECK-NEXT: IPC: 3.08
-# CHECK-NEXT: Block RThroughput: 8.5
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.25 sh1add a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 sh2add a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 sh3add a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 sh1add.uw a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 sh2add.uw a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 sh3add.uw a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 add.uw a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 slli.uw a0, a1, 1
-# CHECK-NEXT: 1 2 0.50 clz a0, a1
-# CHECK-NEXT: 1 2 0.50 clzw a0, a1
-# CHECK-NEXT: 1 2 0.50 ctz a0, a1
-# CHECK-NEXT: 1 2 0.50 ctzw a0, a1
-# CHECK-NEXT: 1 2 0.50 cpop a0, a1
-# CHECK-NEXT: 1 2 0.50 cpopw a0, a1
-# CHECK-NEXT: 1 1 0.25 andn a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 orn a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 xnor a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 rol a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 rolw a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 ror a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 rorw a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 rori a0, a1, 1
-# CHECK-NEXT: 1 1 0.25 roriw a0, a1, 1
-# CHECK-NEXT: 1 1 0.25 min a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 minu a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 max a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 maxu a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 sext.b a0, a1
-# CHECK-NEXT: 1 1 0.25 sext.h a0, a1
-# CHECK-NEXT: 1 1 0.25 zext.h a0, a1
-# CHECK-NEXT: 1 1 0.25 rev8 a0, a1
-# CHECK-NEXT: 1 1 0.25 orc.b a0, a1
-# CHECK-NEXT: 1 1 0.25 bclr a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 bclri a0, a1, 1
-# CHECK-NEXT: 1 1 0.25 bext a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 bexti a0, a1, 1
-# CHECK-NEXT: 1 1 0.25 binv a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 binvi a0, a1, 1
-# CHECK-NEXT: 1 1 0.25 bset a0, a1, a2
-# CHECK-NEXT: 1 1 0.25 bseti a0, a1, 1
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - XSPipeALU0
-# CHECK-NEXT: [1] - XSPipeALU1
-# CHECK-NEXT: [2] - XSPipeALU2
-# CHECK-NEXT: [3] - XSPipeALU3
-# CHECK-NEXT: [4] - XSPipeBJU0
-# CHECK-NEXT: [5] - XSPipeBJU1
-# CHECK-NEXT: [6] - XSPipeBJU2
-# CHECK-NEXT: [7] - XSPipeBJU3
-# CHECK-NEXT: [8] - XSPipeFEX0
-# CHECK-NEXT: [9] - XSPipeFEX1
-# CHECK-NEXT: [10] - XSPipeFEX2
-# CHECK-NEXT: [11] - XSPipeFEX3
-# CHECK-NEXT: [12] - XSPipeFEX4
-# CHECK-NEXT: [13.0] - XSPipeLDU
-# CHECK-NEXT: [13.1] - XSPipeLDU
-# CHECK-NEXT: [13.2] - XSPipeLDU
-# CHECK-NEXT: [14.0] - XSPipeSTA
-# CHECK-NEXT: [14.1] - XSPipeSTA
-# CHECK-NEXT: [15.0] - XSPipeSTD
-# CHECK-NEXT: [15.1] - XSPipeSTD
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
-# CHECK-NEXT: 10.00 10.00 10.00 10.00 - - - - - - - - - - - - - - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sh1add a0, a1, a2
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - sh2add a0, a1, a2
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sh3add a0, a1, a2
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - sh1add.uw a0, a1, a2
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sh2add.uw a0, a1, a2
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - sh3add.uw a0, a1, a2
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - add.uw a0, a1, a2
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - slli.uw a0, a1, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - clz a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - clzw a0, a1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - ctz a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - ctzw a0, a1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - cpop a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - cpopw a0, a1
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - andn a0, a1, a2
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - orn a0, a1, a2
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - xnor a0, a1, a2
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - rol a0, a1, a2
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - rolw a0, a1, a2
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - ror a0, a1, a2
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - rorw a0, a1, a2
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - rori a0, a1, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - roriw a0, a1, 1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - min a0, a1, a2
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - minu a0, a1, a2
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - max a0, a1, a2
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - maxu a0, a1, a2
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - sext.b a0, a1
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sext.h a0, a1
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - zext.h a0, a1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - rev8 a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - orc.b a0, a1
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - bclr a0, a1, a2
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - bclri a0, a1, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - bext a0, a1, a2
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - bexti a0, a1, 1
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - binv a0, a1, a2
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - binvi a0, a1, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - bset a0, a1, a2
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - bseti a0, a1, 1
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
index c7cf24ab0016f..f37012f1cf13e 100644
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/cascade-fma.s
@@ -5,12 +5,12 @@ fmadd.s fa0, fa1, fa2, fa0
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 100
-# CHECK-NEXT: Total Cycles: 303
+# CHECK-NEXT: Total Cycles: 403
# CHECK-NEXT: Total uOps: 100
# CHECK: Dispatch Width: 6
-# CHECK-NEXT: uOps Per Cycle: 0.33
-# CHECK-NEXT: IPC: 0.33
+# CHECK-NEXT: uOps Per Cycle: 0.25
+# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -22,7 +22,7 @@ fmadd.s fa0, fa1, fa2, fa0
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 3 0.33 fmadd.s fa0, fa1, fa2, fa0
+# CHECK-NEXT: 1 4 0.33 fmadd.s fa0, fa1, fa2, fa0
# CHECK: Resources:
# CHECK-NEXT: [0] - XSPipeALU0
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
index ad6a54bd28e26..12514a4812394 100644
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
@@ -17,13 +17,13 @@ fsqrt.d fa0, fa1
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 12
-# CHECK-NEXT: Total Cycles: 163
+# CHECK-NEXT: Total Cycles: 123
# CHECK-NEXT: Total uOps: 12
# CHECK: Dispatch Width: 6
-# CHECK-NEXT: uOps Per Cycle: 0.07
-# CHECK-NEXT: IPC: 0.07
-# CHECK-NEXT: Block RThroughput: 160.0
+# CHECK-NEXT: uOps Per Cycle: 0.10
+# CHECK-NEXT: IPC: 0.10
+# CHECK-NEXT: Block RThroughput: 120.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -34,18 +34,18 @@ fsqrt.d fa0, fa1
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 20 20.00 div a0, a1, a2
-# CHECK-NEXT: 1 20 20.00 divu a0, a1, a2
-# CHECK-NEXT: 1 20 20.00 divw a0, a1, a2
-# CHECK-NEXT: 1 20 20.00 divuw a0, a1, a2
-# CHECK-NEXT: 1 20 20.00 rem a0, a1, a2
-# CHECK-NEXT: 1 20 20.00 remu a0, a1, a2
-# CHECK-NEXT: 1 20 20.00 remw a0, a1, a2
-# CHECK-NEXT: 1 20 20.00 remuw a0, a1, a2
-# CHECK-NEXT: 1 10 0.50 fdiv.s fa0, fa1, fa2
-# CHECK-NEXT: 1 15 0.50 fdiv.d fa0, fa1, fa2
-# CHECK-NEXT: 1 10 0.50 fsqrt.s fa0, fa1
-# CHECK-NEXT: 1 15 0.50 fsqrt.d fa0, fa1
+# CHECK-NEXT: 1 19 19.00 div a0, a1, a2
+# CHECK-NEXT: 1 19 19.00 divu a0, a1, a2
+# CHECK-NEXT: 1 11 11.00 divw a0, a1, a2
+# CHECK-NEXT: 1 11 11.00 divuw a0, a1, a2
+# CHECK-NEXT: 1 19 19.00 rem a0, a1, a2
+# CHECK-NEXT: 1 19 19.00 remu a0, a1, a2
+# CHECK-NEXT: 1 11 11.00 remw a0, a1, a2
+# CHECK-NEXT: 1 11 11.00 remuw a0, a1, a2
+# CHECK-NEXT: 1 9 4.50 fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: 1 14 7.00 fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: 1 10 5.00 fsqrt.s fa0, fa1
+# CHECK-NEXT: 1 16 8.00 fsqrt.d fa0, fa1
# CHECK: Resources:
# CHECK-NEXT: [0] - XSPipeALU0
@@ -71,30 +71,31 @@ fsqrt.d fa0, fa1
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
-# CHECK-NEXT: - - - - - - - 160.00 - 2.00 - 2.00 - - - - - - - -
+# CHECK-NEXT: - - - - - - - 120.00 - 30.00 - 19.00 - - - - - - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
-# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - div a0, a1, a2
-# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - divu a0, a1, a2
-# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - divw a0, a1, a2
-# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - divuw a0, a1, a2
-# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - rem a0, a1, a2
-# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - remu a0, a1, a2
-# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - remw a0, a1, a2
-# CHECK-NEXT: - - - - - - - 20.00 - - - - - - - - - - - - remuw a0, a1, a2
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fdiv.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fdiv.d fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fsqrt.s fa0, fa1
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fsqrt.d fa0, fa1
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - div a0, a1, a2
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - divu a0, a1, a2
+# CHECK-NEXT: - - - - - - - 11.00 - - - - - - - - - - - - divw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 11.00 - - - - - - - - - - - - divuw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - rem a0, a1, a2
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - remu a0, a1, a2
+# CHECK-NEXT: - - - - - - - 11.00 - - - - - - - - - - - - remw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 11.00 - - - - - - - - - - - - remuw a0, a1, a2
+# CHECK-NEXT: - - - - - - - - - - - 9.00 - - - - - - - - fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - 14.00 - - - - - - - - - - fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - - - - 10.00 - - - - - - - - fsqrt.s fa0, fa1
+# CHECK-NEXT: - - - - - - - - - 16.00 - - - - - - - - - - fsqrt.d fa0, fa1
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789 0123456789
# CHECK-NEXT: Index 0123456789 0123456789 0123456789 012
-# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeeER . . . . . . . . . div a0, a1, a2
-# CHECK-NEXT: [0,1] D====================eeeeeeeeeeeeeeeeeeeeER . . . . . divu a0, a1, a2
-# CHECK-NEXT: [0,2] D========================================eeeeeeeeeeeeeeeeeeeeER divw a0, a1, a2
+# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeER . . . . . . . . . div a0, a1, a2
+# CHECK-NEXT: [0,1] D===================eeeeeeeeeeeeeeeeeeeER . . . . . divu a0, a1, a2
+# CHECK-NEXT: [0,2] D======================================eeeeeeeeeeeER . . . divw a0, a1, a2
+# CHECK-NEXT: [0,3] D=================================================eeeeeeeeeeeER divuw a0, a1, a2
# CHECK-NEXT: Truncated display due to cycle limit
# CHECK: Average Wait times (based on the timeline view):
@@ -105,15 +106,15 @@ fsqrt.d fa0, fa1
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 div a0, a1, a2
-# CHECK-NEXT: 1. 1 21.0 21.0 0.0 divu a0, a1, a2
-# CHECK-NEXT: 2. 1 41.0 41.0 0.0 divw a0, a1, a2
-# CHECK-NEXT: 3. 1 61.0 61.0 0.0 divuw a0, a1, a2
-# CHECK-NEXT: 4. 1 81.0 81.0 0.0 rem a0, a1, a2
-# CHECK-NEXT: 5. 1 101.0 101.0 0.0 remu a0, a1, a2
-# CHECK-NEXT: 6. 1 120.0 120.0 0.0 remw a0, a1, a2
-# CHECK-NEXT: 7. 1 140.0 140.0 0.0 remuw a0, a1, a2
-# CHECK-NEXT: 8. 1 1.0 1.0 149.0 fdiv.s fa0, fa1, fa2
-# CHECK-NEXT: 9. 1 1.0 1.0 144.0 fdiv.d fa0, fa1, fa2
-# CHECK-NEXT: 10. 1 2.0 2.0 148.0 fsqrt.s fa0, fa1
-# CHECK-NEXT: 11. 1 2.0 2.0 143.0 fsqrt.d fa0, fa1
-# CHECK-NEXT: 1 47.7 47.7 48.7 <total>
+# CHECK-NEXT: 1. 1 20.0 20.0 0.0 divu a0, a1, a2
+# CHECK-NEXT: 2. 1 39.0 39.0 0.0 divw a0, a1, a2
+# CHECK-NEXT: 3. 1 50.0 50.0 0.0 divuw a0, a1, a2
+# CHECK-NEXT: 4. 1 61.0 61.0 0.0 rem a0, a1, a2
+# CHECK-NEXT: 5. 1 80.0 80.0 0.0 remu a0, a1, a2
+# CHECK-NEXT: 6. 1 98.0 98.0 0.0 remw a0, a1, a2
+# CHECK-NEXT: 7. 1 109.0 109.0 0.0 remuw a0, a1, a2
+# CHECK-NEXT: 8. 1 1.0 1.0 110.0 fdiv.s fa0, fa1, fa2
+# CHECK-NEXT: 9. 1 1.0 1.0 105.0 fdiv.d fa0, fa1, fa2
+# CHECK-NEXT: 10. 1 10.0 10.0 100.0 fsqrt.s fa0, fa1
+# CHECK-NEXT: 11. 1 15.0 15.0 89.0 fsqrt.d fa0, fa1
+# CHECK-NEXT: 1 40.4 40.4 33.7 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/floating-point.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/floating-point.test
new file mode 100644
index 0000000000000..aa06881688a68
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/floating-point.test
@@ -0,0 +1,199 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/floating-point.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 4 0.33 * 4 XSPipeLDU,XSPipeMemIQ FLW flw ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD FSW fsw ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.33 * 4 XSPipeLDU,XSPipeMemIQ FLD fld ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD FSD fsd ft0, 0(a0)
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FADD_S fadd.s fs10, fs11, ft8
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FSUB_S fsub.s ft9, ft10, ft11
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMUL_S fmul.s ft0, ft1, ft2
+# CHECK-NEXT: 1 9 4.50 9 XSPipeGroupFDIV[9],XSPipeGroupFP[9] FDIV_S fdiv.s ft3, ft4, ft5
+# CHECK-NEXT: 1 10 5.00 10 XSPipeGroupFDIV[10],XSPipeGroupFP[10] FSQRT_S fsqrt.s ft6, ft7
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMIN_S fmin.s fa5, fa6, fa7
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMAX_S fmax.s fs2, fs3, fs4
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMADD_S fmadd.s fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMSUB_S fmsub.s fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FNMSUB_S fnmsub.s fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FNMADD_S fnmadd.s fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FADD_D fadd.d fs10, fs11, ft8
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FSUB_D fsub.d ft9, ft10, ft11
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMUL_D fmul.d ft0, ft1, ft2
+# CHECK-NEXT: 1 14 7.00 14 XSPipeGroupFDIV[14],XSPipeGroupFP[14] FDIV_D fdiv.d ft3, ft4, ft5
+# CHECK-NEXT: 1 16 8.00 16 XSPipeGroupFDIV[16],XSPipeGroupFP[16] FSQRT_D fsqrt.d ft6, ft7
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMIN_D fmin.d fa5, fa6, fa7
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMAX_D fmax.d fs2, fs3, fs4
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMADD_D fmadd.d fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMSUB_D fmsub.d fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FNMSUB_D fnmsub.d fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FNMADD_D fnmadd.d fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_W_S fcvt.w.s a0, fs5
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_WU_S fcvt.wu.s a1, fs6
+# CHECK-NEXT: 1 3 1.00 3 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FCVT_S_W fcvt.s.w ft11, a4
+# CHECK-NEXT: 1 3 1.00 3 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FCVT_S_WU fcvt.s.wu ft0, a5
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_L_S fcvt.l.s a0, ft0
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_LU_S fcvt.lu.s a1, ft1
+# CHECK-NEXT: 1 3 1.00 3 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FCVT_S_L fcvt.s.l ft2, a2
+# CHECK-NEXT: 1 3 1.00 3 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FCVT_S_LU fcvt.s.lu ft3, a3
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMV_X_W fmv.x.w a2, fs7
+# CHECK-NEXT: 1 1 1.00 1 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FMV_W_X fmv.w.x ft1, a6
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FSGNJ_S fsgnj.s fs1, fa0, fa1
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FSGNJN_S fsgnjn.s fa1, fa3, fa4
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_WU_D fcvt.wu.d a4, ft11
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_W_D fcvt.w.d a4, ft11
+# CHECK-NEXT: 1 3 1.00 3 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FCVT_D_W fcvt.d.w ft0, a5
+# CHECK-NEXT: 1 3 1.00 3 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FCVT_D_WU fcvt.d.wu ft1, a6
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_S_D fcvt.s.d fs5, fs6
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_D_S fcvt.d.s fs7, fs8
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_L_D fcvt.l.d a0, ft0
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_LU_D fcvt.lu.d a1, ft1
+# CHECK-NEXT: 1 3 1.00 3 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FCVT_D_L fcvt.d.l ft3, a3
+# CHECK-NEXT: 1 3 1.00 3 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FCVT_D_LU fcvt.d.lu ft4, a4
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMV_X_D fmv.x.d a2, ft2
+# CHECK-NEXT: 1 1 1.00 1 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FMV_D_X fmv.d.x ft5, a5
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FSGNJ_D fsgnj.d fs1, fa0, fa1
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FSGNJN_D fsgnjn.d fa1, fa3, fa4
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FEQ_S feq.s a1, fs8, fs9
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FLT_S flt.s a2, fs10, fs11
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FLE_S fle.s a3, ft8, ft9
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FEQ_D feq.d a1, fs8, fs9
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FLT_D flt.d a2, fs10, fs11
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FLE_D fle.d a3, ft8, ft9
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCLASS_S fclass.s a3, ft10
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCLASS_D fclass.d a3, ft10
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - 10.00 - 22.00 24.50 10.00 24.50 10.00 0.67 0.67 0.67 1.00 1.00 1.00 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - flw ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 fsw ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - fld ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 fsd ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fadd.s fs10, fs11, ft8
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fsub.s ft9, ft10, ft11
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmul.s ft0, ft1, ft2
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - fdiv.s ft3, ft4, ft5
+# CHECK-NEXT: - - - - - - - - - 5.00 - 5.00 - - - - - - - - fsqrt.s ft6, ft7
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmin.s fa5, fa6, fa7
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmax.s fs2, fs3, fs4
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmadd.s fa0, fa1, fa2, ft11
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmsub.s fa4, fa5, fa6, fa7
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fnmsub.s fs2, fs3, fs4, fs5
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fnmadd.s fs6, fs7, fs8, fs9
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fadd.d fs10, fs11, ft8
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fsub.d ft9, ft10, ft11
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmul.d ft0, ft1, ft2
+# CHECK-NEXT: - - - - - - - - - 7.00 - 7.00 - - - - - - - - fdiv.d ft3, ft4, ft5
+# CHECK-NEXT: - - - - - - - - - 8.00 - 8.00 - - - - - - - - fsqrt.d ft6, ft7
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmin.d fa5, fa6, fa7
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmax.d fs2, fs3, fs4
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmadd.d fa0, fa1, fa2, ft11
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmsub.d fa4, fa5, fa6, fa7
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fnmsub.d fs2, fs3, fs4, fs5
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fnmadd.d fs6, fs7, fs8, fs9
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.w.s a0, fs5
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.wu.s a1, fs6
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.w ft11, a4
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.wu ft0, a5
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.l.s a0, ft0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.lu.s a1, ft1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.l ft2, a2
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.lu ft3, a3
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmv.x.w a2, fs7
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fmv.w.x ft1, a6
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fsgnj.s fs1, fa0, fa1
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fsgnjn.s fa1, fa3, fa4
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.wu.d a4, ft11
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.w.d a4, ft11
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.w ft0, a5
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.wu ft1, a6
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.s.d fs5, fs6
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.d.s fs7, fs8
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.l.d a0, ft0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.lu.d a1, ft1
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.l ft3, a3
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.lu ft4, a4
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmv.x.d a2, ft2
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fmv.d.x ft5, a5
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fsgnj.d fs1, fa0, fa1
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fsgnjn.d fa1, fa3, fa4
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - feq.s a1, fs8, fs9
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - flt.s a2, fs10, fs11
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fle.s a3, ft8, ft9
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - feq.d a1, fs8, fs9
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - flt.d a2, fs10, fs11
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fle.d a3, ft8, ft9
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fclass.s a3, ft10
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fclass.d a3, ft10
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
index b850d3526e870..63e1a73608602 100644
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/fpr-bypass.s
@@ -1,90 +1,18 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu < %s | FileCheck %s
fadd.s fa0, fa1, fa2
-fadd.d fa0, fa1, fa2
-fsub.s fa0, fa1, fa2
-fsub.d fa0, fa1, fa2
+fadd.s fa0, fa0, fa2
-fmul.s fa0, fa1, fa2
-fmul.d fa0, fa1, fa2
-
-fdiv.s fa0, fa1, fa2
-fdiv.d fa0, fa1, fa2
-fsqrt.s fa0, fa1
-fsqrt.d fa0, fa1
-
-fmadd.s fa0, fa1, fa2, fa3
-fmadd.d fa0, fa1, fa2, fa3
-fmsub.s fa0, fa1, fa2, fa3
-fmsub.d fa0, fa1, fa2, fa3
-fnmadd.s fa0, fa1, fa2, fa3
-fnmadd.d fa0, fa1, fa2, fa3
-fnmsub.s fa0, fa1, fa2, fa3
-fnmsub.d fa0, fa1, fa2, fa3
-
-feq.s a0, fa1, fa2
-feq.d a0, fa1, fa2
-flt.s a0, fa1, fa2
-flt.d a0, fa1, fa2
-fle.s a0, fa1, fa2
-fle.d a0, fa1, fa2
-
-fmin.s fa0, fa1, fa2
-fmin.d fa0, fa1, fa2
-fmax.s fa0, fa1, fa2
-fmax.d fa0, fa1, fa2
-
-fsgnj.s fa0, fa1, fa2
-fsgnj.d fa0, fa1, fa2
-fsgnjn.s fa0, fa1, fa2
-fsgnjn.d fa0, fa1, fa2
-fsgnjx.s fa0, fa1, fa2
-fsgnjx.d fa0, fa1, fa2
-
-fmv.x.w a0, fa0
-fmv.x.d a0, fa0
-fmv.w.x fa0, a0
-fmv.d.x fa0, a0
-
-fcvt.s.w fa0, a0
-fcvt.s.wu fa0, a0
-fcvt.s.l fa0, a0
-fcvt.s.lu fa0, a0
-fcvt.d.w fa0, a0
-fcvt.d.wu fa0, a0
-fcvt.d.l fa0, a0
-fcvt.d.lu fa0, a0
-
-fcvt.w.s a0, fa0
-fcvt.wu.s a0, fa0
-fcvt.l.s a0, fa0
-fcvt.lu.s a0, fa0
-fcvt.w.d a0, fa0
-fcvt.wu.d a0, fa0
-fcvt.l.d a0, fa0
-fcvt.lu.d a0, fa0
-
-fcvt.s.d fa0, fa1
-fcvt.d.s fa0, fa1
-
-fclass.s a0, fa0
-fclass.d a0, fa0
-
-flw fa0, 0(a0)
-fld fa0, 0(a0)
-fsw fa0, 0(a0)
-fsd fa0, 0(a0)
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 62
-# CHECK-NEXT: Total Cycles: 29
-# CHECK-NEXT: Total uOps: 62
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 200
+# CHECK-NEXT: Total Cycles: 71
+# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 6
-# CHECK-NEXT: uOps Per Cycle: 2.14
-# CHECK-NEXT: IPC: 2.14
-# CHECK-NEXT: Block RThroughput: 12.0
+# CHECK-NEXT: uOps Per Cycle: 2.82
+# CHECK-NEXT: IPC: 2.82
+# CHECK-NEXT: Block RThroughput: 0.7
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -96,67 +24,7 @@ fsd fa0, 0(a0)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 0.33 fadd.s fa0, fa1, fa2
-# CHECK-NEXT: 1 1 0.33 fadd.d fa0, fa1, fa2
-# CHECK-NEXT: 1 1 0.33 fsub.s fa0, fa1, fa2
-# CHECK-NEXT: 1 1 0.33 fsub.d fa0, fa1, fa2
-# CHECK-NEXT: 1 3 0.33 fmul.s fa0, fa1, fa2
-# CHECK-NEXT: 1 3 0.33 fmul.d fa0, fa1, fa2
-# CHECK-NEXT: 1 10 0.50 fdiv.s fa0, fa1, fa2
-# CHECK-NEXT: 1 15 0.50 fdiv.d fa0, fa1, fa2
-# CHECK-NEXT: 1 10 0.50 fsqrt.s fa0, fa1
-# CHECK-NEXT: 1 15 0.50 fsqrt.d fa0, fa1
-# CHECK-NEXT: 1 3 0.33 fmadd.s fa0, fa1, fa2, fa3
-# CHECK-NEXT: 1 3 0.33 fmadd.d fa0, fa1, fa2, fa3
-# CHECK-NEXT: 1 3 0.33 fmsub.s fa0, fa1, fa2, fa3
-# CHECK-NEXT: 1 3 0.33 fmsub.d fa0, fa1, fa2, fa3
-# CHECK-NEXT: 1 3 0.33 fnmadd.s fa0, fa1, fa2, fa3
-# CHECK-NEXT: 1 3 0.33 fnmadd.d fa0, fa1, fa2, fa3
-# CHECK-NEXT: 1 3 0.33 fnmsub.s fa0, fa1, fa2, fa3
-# CHECK-NEXT: 1 3 0.33 fnmsub.d fa0, fa1, fa2, fa3
-# CHECK-NEXT: 1 2 0.33 feq.s a0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 feq.d a0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 flt.s a0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 flt.d a0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fle.s a0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fle.d a0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fmin.s fa0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fmin.d fa0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fmax.s fa0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fmax.d fa0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fsgnj.s fa0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fsgnj.d fa0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fsgnjn.s fa0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fsgnjn.d fa0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fsgnjx.s fa0, fa1, fa2
-# CHECK-NEXT: 1 2 0.33 fsgnjx.d fa0, fa1, fa2
-# CHECK-NEXT: 1 2 1.00 fmv.x.w a0, fa0
-# CHECK-NEXT: 1 2 1.00 fmv.x.d a0, fa0
-# CHECK-NEXT: 1 0 1.00 fmv.w.x fa0, a0
-# CHECK-NEXT: 1 0 1.00 fmv.d.x fa0, a0
-# CHECK-NEXT: 1 2 1.00 fcvt.s.w fa0, a0
-# CHECK-NEXT: 1 2 1.00 fcvt.s.wu fa0, a0
-# CHECK-NEXT: 1 2 1.00 fcvt.s.l fa0, a0
-# CHECK-NEXT: 1 2 1.00 fcvt.s.lu fa0, a0
-# CHECK-NEXT: 1 2 1.00 fcvt.d.w fa0, a0
-# CHECK-NEXT: 1 2 1.00 fcvt.d.wu fa0, a0
-# CHECK-NEXT: 1 2 1.00 fcvt.d.l fa0, a0
-# CHECK-NEXT: 1 2 1.00 fcvt.d.lu fa0, a0
-# CHECK-NEXT: 1 2 1.00 fcvt.w.s a0, fa0
-# CHECK-NEXT: 1 2 1.00 fcvt.wu.s a0, fa0
-# CHECK-NEXT: 1 2 1.00 fcvt.l.s a0, fa0
-# CHECK-NEXT: 1 2 1.00 fcvt.lu.s a0, fa0
-# CHECK-NEXT: 1 2 1.00 fcvt.w.d a0, fa0
-# CHECK-NEXT: 1 2 1.00 fcvt.wu.d a0, fa0
-# CHECK-NEXT: 1 2 1.00 fcvt.l.d a0, fa0
-# CHECK-NEXT: 1 2 1.00 fcvt.lu.d a0, fa0
-# CHECK-NEXT: 1 2 1.00 fcvt.s.d fa0, fa1
-# CHECK-NEXT: 1 2 1.00 fcvt.d.s fa0, fa1
-# CHECK-NEXT: 1 2 0.33 fclass.s a0, fa0
-# CHECK-NEXT: 1 2 0.33 fclass.d a0, fa0
-# CHECK-NEXT: 1 6 0.33 * flw fa0, 0(a0)
-# CHECK-NEXT: 1 6 0.33 * fld fa0, 0(a0)
-# CHECK-NEXT: 1 4 0.25 * fsw fa0, 0(a0)
-# CHECK-NEXT: 1 4 0.25 * fsd fa0, 0(a0)
+# CHECK-NEXT: 1 1 0.33 fadd.s fa0, fa0, fa2
# CHECK: Resources:
# CHECK-NEXT: [0] - XSPipeALU0
@@ -182,69 +50,9 @@ fsd fa0, 0(a0)
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
-# CHECK-NEXT: - - - - - - 10.00 - 22.00 2.00 11.00 2.00 11.00 - 1.00 1.00 - - 1.00 1.00
+# CHECK-NEXT: - - - - - - - - 0.66 - 0.67 - 0.67 - - - - - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fadd.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fadd.d fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fsub.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fsub.d fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmul.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmul.d fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fdiv.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fdiv.d fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - - - - - - - - fsqrt.s fa0, fa1
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - - - - - - - - fsqrt.d fa0, fa1
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmadd.s fa0, fa1, fa2, fa3
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmadd.d fa0, fa1, fa2, fa3
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmsub.s fa0, fa1, fa2, fa3
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmsub.d fa0, fa1, fa2, fa3
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fnmadd.s fa0, fa1, fa2, fa3
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fnmadd.d fa0, fa1, fa2, fa3
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fnmsub.s fa0, fa1, fa2, fa3
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fnmsub.d fa0, fa1, fa2, fa3
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - feq.s a0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - feq.d a0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - flt.s a0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - flt.d a0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fle.s a0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fle.d a0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmin.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmin.d fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmax.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmax.d fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fsgnj.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fsgnj.d fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fsgnjn.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fsgnjn.d fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fsgnjx.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fsgnjx.d fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmv.x.w a0, fa0
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmv.x.d a0, fa0
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fmv.w.x fa0, a0
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fmv.d.x fa0, a0
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.w fa0, a0
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.wu fa0, a0
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.l fa0, a0
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.s.lu fa0, a0
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.w fa0, a0
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.wu fa0, a0
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.l fa0, a0
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fcvt.d.lu fa0, a0
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.w.s a0, fa0
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.wu.s a0, fa0
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.l.s a0, fa0
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.lu.s a0, fa0
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.w.d a0, fa0
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.wu.d a0, fa0
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.l.d a0, fa0
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.lu.d a0, fa0
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.s.d fa0, fa1
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.d.s fa0, fa1
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fclass.s a0, fa0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fclass.d a0, fa0
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - flw fa0, 0(a0)
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - fld fa0, 0(a0)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 fsw fa0, 0(a0)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - fsd fa0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.34 - - - - - - - fadd.s fa0, fa1, fa2
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.34 - 0.33 - - - - - - - fadd.s fa0, fa0, fa2
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
index ce6b171f54c78..8bdcddeca560a 100644
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/gpr-bypass.s
@@ -1,87 +1,18 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -timeline \
-# RUN: -timeline-max-cycles=1000 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu < %s | FileCheck %s
-lui a0, 1
-auipc a1, 1
+add a0, a1, a2
+add a0, a0, a2
-add a0, a0, a1
-addi a0, a0, 1
-addw a0, a0, a0
-addiw a0, a0, 1
-
-sub a0, a0, a0
-subw a0, a0, a0
-
-and a0, a0, a1
-andi a0, a0, 1
-or a0, a0, a1
-ori a0, a0, 1
-xor a0, a0, a1
-xori a0, a0, 1
-
-sll a0, a0, a1
-slli a0, a0, 1
-sllw a0, a0, a1
-slliw a0, a0, 1
-srl a0, a0, a1
-srli a0, a0, 1
-srlw a0, a0, a1
-srliw a0, a0, 1
-sra a0, a0, a1
-srai a0, a0, 1
-sraw a0, a0, a1
-sraiw a0, a0, 1
-
-slt a0, a0, a1
-slti a0, a0, 1
-sltu a0, a0, a1
-sltiu a0, a0, 1
-
-mul a0, a0, a1
-mulh a0, a0, a1
-mulhsu a0, a0, a1
-mulhu a0, a0, a1
-mulw a0, a0, a1
-
-j 1f
-1:
-jr ra
-beq a0, a1, 1f
-1:
-bne a0, a1, 1f
-1:
-blt a0, a1, 1f
-1:
-bge a0, a1, 1f
-1:
-bltu a0, a1, 1f
-1:
-bgeu a0, a1, 1f
-1:
-
-lb a0, 0(a1)
-lh a0, 0(a1)
-lw a0, 0(a1)
-ld a0, 0(a1)
-lbu a0, 0(a1)
-lhu a0, 0(a1)
-lwu a0, 0(a1)
-
-sb a0, 0(a1)
-sh a0, 0(a1)
-sw a0, 0(a1)
-sd a0, 0(a1)
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 54
-# CHECK-NEXT: Total Cycles: 44
-# CHECK-NEXT: Total uOps: 54
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 200
+# CHECK-NEXT: Total Cycles: 54
+# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 6
-# CHECK-NEXT: uOps Per Cycle: 1.23
-# CHECK-NEXT: IPC: 1.23
-# CHECK-NEXT: Block RThroughput: 9.0
+# CHECK-NEXT: uOps Per Cycle: 3.70
+# CHECK-NEXT: IPC: 3.70
+# CHECK-NEXT: Block RThroughput: 0.5
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -92,60 +23,8 @@ sd a0, 0(a1)
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.25 lui a0, 1
-# CHECK-NEXT: 1 1 0.25 auipc a1, 1
-# CHECK-NEXT: 1 1 0.25 add a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 addi a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 addw a0, a0, a0
-# CHECK-NEXT: 1 1 0.25 addiw a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 sub a0, a0, a0
-# CHECK-NEXT: 1 1 0.25 subw a0, a0, a0
-# CHECK-NEXT: 1 1 0.25 and a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 andi a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 or a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 ori a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 xor a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 xori a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 sll a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 slli a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 sllw a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 slliw a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 srl a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 srli a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 srlw a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 srliw a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 sra a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 srai a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 sraw a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 sraiw a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 slt a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 slti a0, a0, 1
-# CHECK-NEXT: 1 1 0.25 sltu a0, a0, a1
-# CHECK-NEXT: 1 1 0.25 seqz a0, a0
-# CHECK-NEXT: 1 2 0.50 mul a0, a0, a1
-# CHECK-NEXT: 1 2 0.50 mulh a0, a0, a1
-# CHECK-NEXT: 1 2 0.50 mulhsu a0, a0, a1
-# CHECK-NEXT: 1 2 0.50 mulhu a0, a0, a1
-# CHECK-NEXT: 1 2 0.50 mulw a0, a0, a1
-# CHECK-NEXT: 1 1 0.33 j .Ltmp0
-# CHECK-NEXT: 1 1 0.33 ret
-# CHECK-NEXT: 1 1 0.33 beq a0, a1, .Ltmp1
-# CHECK-NEXT: 1 1 0.33 bne a0, a1, .Ltmp2
-# CHECK-NEXT: 1 1 0.33 blt a0, a1, .Ltmp3
-# CHECK-NEXT: 1 1 0.33 bge a0, a1, .Ltmp4
-# CHECK-NEXT: 1 1 0.33 bltu a0, a1, .Ltmp5
-# CHECK-NEXT: 1 1 0.33 bgeu a0, a1, .Ltmp6
-# CHECK-NEXT: 1 6 0.33 * lb a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * lh a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * lw a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * ld a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * lbu a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * lhu a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * lwu a0, 0(a1)
-# CHECK-NEXT: 1 4 0.25 * sb a0, 0(a1)
-# CHECK-NEXT: 1 4 0.25 * sh a0, 0(a1)
-# CHECK-NEXT: 1 4 0.25 * sw a0, 0(a1)
-# CHECK-NEXT: 1 4 0.25 * sd a0, 0(a1)
+# CHECK-NEXT: 1 1 0.25 add a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 add a0, a0, a2
# CHECK: Resources:
# CHECK-NEXT: [0] - XSPipeALU0
@@ -171,183 +50,9 @@ sd a0, 0(a1)
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
-# CHECK-NEXT: 9.00 10.00 8.00 8.00 2.00 3.00 3.00 - - - - - - 2.00 2.00 3.00 1.00 1.00 1.00 1.00
+# CHECK-NEXT: 0.50 0.50 0.50 0.50 - - - - - - - - - - - - - - - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - lui a0, 1
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - auipc a1, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - add a0, a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - addi a0, a0, 1
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - addw a0, a0, a0
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - addiw a0, a0, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sub a0, a0, a0
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - subw a0, a0, a0
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - and a0, a0, a1
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - andi a0, a0, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - or a0, a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - ori a0, a0, 1
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - xor a0, a0, a1
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - xori a0, a0, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sll a0, a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - slli a0, a0, 1
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sllw a0, a0, a1
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - slliw a0, a0, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - srl a0, a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - srli a0, a0, 1
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - srlw a0, a0, a1
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - srliw a0, a0, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - sra a0, a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - srai a0, a0, 1
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sraw a0, a0, a1
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - sraiw a0, a0, 1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - slt a0, a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - slti a0, a0, 1
-# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - sltu a0, a0, a1
-# CHECK-NEXT: - - 1.00 - - - - - - - - - - - - - - - - - seqz a0, a0
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mul a0, a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulh a0, a0, a1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulhsu a0, a0, a1
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulhu a0, a0, a1
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulw a0, a0, a1
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - j .Ltmp0
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - ret
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - beq a0, a1, .Ltmp1
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - bne a0, a1, .Ltmp2
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - blt a0, a1, .Ltmp3
-# CHECK-NEXT: - - - - 1.00 - - - - - - - - - - - - - - - bge a0, a1, .Ltmp4
-# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - bltu a0, a1, .Ltmp5
-# CHECK-NEXT: - - - - - 1.00 - - - - - - - - - - - - - - bgeu a0, a1, .Ltmp6
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lb a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - lh a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lw a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - ld a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lbu a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lhu a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lwu a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 sb a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - sh a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - sw a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - sd a0, 0(a1)
-
-# CHECK: Timeline view:
-# CHECK-NEXT: 0123456789 0123456789
-# CHECK-NEXT: Index 0123456789 0123456789 0123
-
-# CHECK: [0,0] DeER . . . . . . . . . lui a0, 1
-# CHECK-NEXT: [0,1] DeER . . . . . . . . . auipc a1, 1
-# CHECK-NEXT: [0,2] D=eER. . . . . . . . . add a0, a0, a1
-# CHECK-NEXT: [0,3] D==eER . . . . . . . . addi a0, a0, 1
-# CHECK-NEXT: [0,4] D===eER . . . . . . . . addw a0, a0, a0
-# CHECK-NEXT: [0,5] D====eER . . . . . . . . addiw a0, a0, 1
-# CHECK-NEXT: [0,6] .D====eER . . . . . . . . sub a0, a0, a0
-# CHECK-NEXT: [0,7] .D=====eER. . . . . . . . subw a0, a0, a0
-# CHECK-NEXT: [0,8] .D======eER . . . . . . . and a0, a0, a1
-# CHECK-NEXT: [0,9] .D=======eER . . . . . . . andi a0, a0, 1
-# CHECK-NEXT: [0,10] .D========eER . . . . . . . or a0, a0, a1
-# CHECK-NEXT: [0,11] .D=========eER . . . . . . . ori a0, a0, 1
-# CHECK-NEXT: [0,12] . D=========eER. . . . . . . xor a0, a0, a1
-# CHECK-NEXT: [0,13] . D==========eER . . . . . . xori a0, a0, 1
-# CHECK-NEXT: [0,14] . D===========eER . . . . . . sll a0, a0, a1
-# CHECK-NEXT: [0,15] . D============eER . . . . . . slli a0, a0, 1
-# CHECK-NEXT: [0,16] . D=============eER . . . . . . sllw a0, a0, a1
-# CHECK-NEXT: [0,17] . D==============eER. . . . . . slliw a0, a0, 1
-# CHECK-NEXT: [0,18] . D==============eER . . . . . srl a0, a0, a1
-# CHECK-NEXT: [0,19] . D===============eER . . . . . srli a0, a0, 1
-# CHECK-NEXT: [0,20] . D================eER . . . . . srlw a0, a0, a1
-# CHECK-NEXT: [0,21] . D=================eER . . . . . srliw a0, a0, 1
-# CHECK-NEXT: [0,22] . D==================eER. . . . . sra a0, a0, a1
-# CHECK-NEXT: [0,23] . D===================eER . . . . srai a0, a0, 1
-# CHECK-NEXT: [0,24] . D===================eER . . . . sraw a0, a0, a1
-# CHECK-NEXT: [0,25] . D====================eER . . . . sraiw a0, a0, 1
-# CHECK-NEXT: [0,26] . D=====================eER . . . . slt a0, a0, a1
-# CHECK-NEXT: [0,27] . D======================eER. . . . slti a0, a0, 1
-# CHECK-NEXT: [0,28] . D=======================eER . . . sltu a0, a0, a1
-# CHECK-NEXT: [0,29] . D========================eER . . . seqz a0, a0
-# CHECK-NEXT: [0,30] . D========================eeER . . . mul a0, a0, a1
-# CHECK-NEXT: [0,31] . D==========================eeER . . mulh a0, a0, a1
-# CHECK-NEXT: [0,32] . D============================eeER . . mulhsu a0, a0, a1
-# CHECK-NEXT: [0,33] . D==============================eeER. . mulhu a0, a0, a1
-# CHECK-NEXT: [0,34] . D================================eeER . mulw a0, a0, a1
-# CHECK-NEXT: [0,35] . DeE---------------------------------R . j .Ltmp0
-# CHECK-NEXT: [0,36] . .DeE--------------------------------R . ret
-# CHECK-NEXT: [0,37] . .D=================================eER. beq a0, a1, .Ltmp1
-# CHECK-NEXT: [0,38] . .D=================================eER. bne a0, a1, .Ltmp2
-# CHECK-NEXT: [0,39] . .D=================================eER. blt a0, a1, .Ltmp3
-# CHECK-NEXT: [0,40] . .D==================================eER bge a0, a1, .Ltmp4
-# CHECK-NEXT: [0,41] . .D==================================eER bltu a0, a1, .Ltmp5
-# CHECK-NEXT: [0,42] . . D=================================eER bgeu a0, a1, .Ltmp6
-# CHECK-NEXT: [0,43] . . DeeeeeeE----------------------------R lb a0, 0(a1)
-# CHECK-NEXT: [0,44] . . DeeeeeeE----------------------------R lh a0, 0(a1)
-# CHECK-NEXT: [0,45] . . DeeeeeeE----------------------------R lw a0, 0(a1)
-# CHECK-NEXT: [0,46] . . D=eeeeeeE---------------------------R ld a0, 0(a1)
-# CHECK-NEXT: [0,47] . . D=eeeeeeE---------------------------R lbu a0, 0(a1)
-# CHECK-NEXT: [0,48] . . D=eeeeeeE--------------------------R lhu a0, 0(a1)
-# CHECK-NEXT: [0,49] . . DeeeeeeE---------------------------R lwu a0, 0(a1)
-# CHECK-NEXT: [0,50] . . D======eeeeE-----------------------R sb a0, 0(a1)
-# CHECK-NEXT: [0,51] . . D======eeeeE-----------------------R sh a0, 0(a1)
-# CHECK-NEXT: [0,52] . . D======eeeeE-----------------------R sw a0, 0(a1)
-# CHECK-NEXT: [0,53] . . D======eeeeE-----------------------R sd a0, 0(a1)
-
-# CHECK: Average Wait times (based on the timeline view):
-# CHECK-NEXT: [0]: Executions
-# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
-# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
-# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
-
-# CHECK: [0] [1] [2] [3]
-# CHECK-NEXT: 0. 1 1.0 1.0 0.0 lui a0, 1
-# CHECK-NEXT: 1. 1 1.0 1.0 0.0 auipc a1, 1
-# CHECK-NEXT: 2. 1 2.0 0.0 0.0 add a0, a0, a1
-# CHECK-NEXT: 3. 1 3.0 0.0 0.0 addi a0, a0, 1
-# CHECK-NEXT: 4. 1 4.0 0.0 0.0 addw a0, a0, a0
-# CHECK-NEXT: 5. 1 5.0 0.0 0.0 addiw a0, a0, 1
-# CHECK-NEXT: 6. 1 5.0 0.0 0.0 sub a0, a0, a0
-# CHECK-NEXT: 7. 1 6.0 0.0 0.0 subw a0, a0, a0
-# CHECK-NEXT: 8. 1 7.0 0.0 0.0 and a0, a0, a1
-# CHECK-NEXT: 9. 1 8.0 0.0 0.0 andi a0, a0, 1
-# CHECK-NEXT: 10. 1 9.0 0.0 0.0 or a0, a0, a1
-# CHECK-NEXT: 11. 1 10.0 0.0 0.0 ori a0, a0, 1
-# CHECK-NEXT: 12. 1 10.0 0.0 0.0 xor a0, a0, a1
-# CHECK-NEXT: 13. 1 11.0 0.0 0.0 xori a0, a0, 1
-# CHECK-NEXT: 14. 1 12.0 0.0 0.0 sll a0, a0, a1
-# CHECK-NEXT: 15. 1 13.0 0.0 0.0 slli a0, a0, 1
-# CHECK-NEXT: 16. 1 14.0 0.0 0.0 sllw a0, a0, a1
-# CHECK-NEXT: 17. 1 15.0 0.0 0.0 slliw a0, a0, 1
-# CHECK-NEXT: 18. 1 15.0 0.0 0.0 srl a0, a0, a1
-# CHECK-NEXT: 19. 1 16.0 0.0 0.0 srli a0, a0, 1
-# CHECK-NEXT: 20. 1 17.0 0.0 0.0 srlw a0, a0, a1
-# CHECK-NEXT: 21. 1 18.0 0.0 0.0 srliw a0, a0, 1
-# CHECK-NEXT: 22. 1 19.0 0.0 0.0 sra a0, a0, a1
-# CHECK-NEXT: 23. 1 20.0 0.0 0.0 srai a0, a0, 1
-# CHECK-NEXT: 24. 1 20.0 0.0 0.0 sraw a0, a0, a1
-# CHECK-NEXT: 25. 1 21.0 0.0 0.0 sraiw a0, a0, 1
-# CHECK-NEXT: 26. 1 22.0 0.0 0.0 slt a0, a0, a1
-# CHECK-NEXT: 27. 1 23.0 0.0 0.0 slti a0, a0, 1
-# CHECK-NEXT: 28. 1 24.0 0.0 0.0 sltu a0, a0, a1
-# CHECK-NEXT: 29. 1 25.0 0.0 0.0 seqz a0, a0
-# CHECK-NEXT: 30. 1 25.0 0.0 0.0 mul a0, a0, a1
-# CHECK-NEXT: 31. 1 27.0 0.0 0.0 mulh a0, a0, a1
-# CHECK-NEXT: 32. 1 29.0 0.0 0.0 mulhsu a0, a0, a1
-# CHECK-NEXT: 33. 1 31.0 0.0 0.0 mulhu a0, a0, a1
-# CHECK-NEXT: 34. 1 33.0 0.0 0.0 mulw a0, a0, a1
-# CHECK-NEXT: 35. 1 1.0 1.0 33.0 j .Ltmp0
-# CHECK-NEXT: 36. 1 1.0 1.0 32.0 ret
-# CHECK-NEXT: 37. 1 34.0 0.0 0.0 beq a0, a1, .Ltmp1
-# CHECK-NEXT: 38. 1 34.0 0.0 0.0 bne a0, a1, .Ltmp2
-# CHECK-NEXT: 39. 1 34.0 0.0 0.0 blt a0, a1, .Ltmp3
-# CHECK-NEXT: 40. 1 35.0 1.0 0.0 bge a0, a1, .Ltmp4
-# CHECK-NEXT: 41. 1 35.0 1.0 0.0 bltu a0, a1, .Ltmp5
-# CHECK-NEXT: 42. 1 34.0 1.0 0.0 bgeu a0, a1, .Ltmp6
-# CHECK-NEXT: 43. 1 1.0 1.0 28.0 lb a0, 0(a1)
-# CHECK-NEXT: 44. 1 1.0 1.0 28.0 lh a0, 0(a1)
-# CHECK-NEXT: 45. 1 1.0 1.0 28.0 lw a0, 0(a1)
-# CHECK-NEXT: 46. 1 2.0 2.0 27.0 ld a0, 0(a1)
-# CHECK-NEXT: 47. 1 2.0 2.0 27.0 lbu a0, 0(a1)
-# CHECK-NEXT: 48. 1 2.0 2.0 26.0 lhu a0, 0(a1)
-# CHECK-NEXT: 49. 1 1.0 1.0 27.0 lwu a0, 0(a1)
-# CHECK-NEXT: 50. 1 7.0 0.0 23.0 sb a0, 0(a1)
-# CHECK-NEXT: 51. 1 7.0 0.0 23.0 sh a0, 0(a1)
-# CHECK-NEXT: 52. 1 7.0 0.0 23.0 sw a0, 0(a1)
-# CHECK-NEXT: 53. 1 7.0 0.0 23.0 sd a0, 0(a1)
-# CHECK-NEXT: 1 14.2 0.3 6.4 <total>
+# CHECK-NEXT: - 0.50 0.25 0.25 - - - - - - - - - - - - - - - - add a0, a1, a2
+# CHECK-NEXT: 0.50 - 0.25 0.25 - - - - - - - - - - - - - - - - add a0, a0, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/integer.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/integer.test
new file mode 100644
index 0000000000000..7907ae226c7bf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/integer.test
@@ -0,0 +1,191 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_ADDI addi a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_ADDIW addiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SLTI slti a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SLTIU seqz a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_ANDI andi a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt ORI ori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt XORI xori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_SLLI slli a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_SRLI srli a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_SRAI srai a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SLLIW slliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SRLIW srliw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SRAIW sraiw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_LUI lui a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt AUIPC auipc a1, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_ADD add a0, a0, a1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_ADDW addw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SLT slt a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SLTU sltu a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_AND and a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_OR or a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_XOR xor a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SLL sll a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SRL srl a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SRA sra a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SLLW sllw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SRLW srlw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SRAW sraw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_SUB sub a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_SUBW subw a0, a0, a0
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupBRU,XSPipeGroupInt JAL jal a0, .Ltmp0
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupBRU,XSPipeGroupInt C_JALR jalr a0
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupBRU,XSPipeGroupInt BEQ beq a0, a0, .Ltmp1
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupBRU,XSPipeGroupInt BNE bne a0, a0, .Ltmp2
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupBRU,XSPipeGroupInt BLT blt a0, a0, .Ltmp3
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupBRU,XSPipeGroupInt BLTU bltu a0, a0, .Ltmp4
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupBRU,XSPipeGroupInt BGE bge a0, a0, .Ltmp5
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupBRU,XSPipeGroupInt BGEU bgeu a0, a0, .Ltmp6
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_ADD add a0, a0, a0
+# CHECK-NEXT: 1 4 0.33 * 4 XSPipeLDU,XSPipeMemIQ LB lb t0, 0(a0)
+# CHECK-NEXT: 1 4 0.33 * 4 XSPipeLDU,XSPipeMemIQ LBU lbu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.33 * 4 XSPipeLDU,XSPipeMemIQ LH lh t0, 0(a0)
+# CHECK-NEXT: 1 4 0.33 * 4 XSPipeLDU,XSPipeMemIQ LHU lhu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.33 * 4 XSPipeLDU,XSPipeMemIQ LW lw t0, 0(a0)
+# CHECK-NEXT: 1 4 0.33 * 4 XSPipeLDU,XSPipeMemIQ LWU lwu t0, 0(a0)
+# CHECK-NEXT: 1 4 0.33 * 4 XSPipeLDU,XSPipeMemIQ LD ld t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SB sb t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SH sh t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SW sw t0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD SD sd t0, 0(a0)
+# CHECK-NEXT: 1 1 1.00 U 1 XSPipeBJU3,XSPipeGroupInt,XSPipeIntIQ3 CSRRW csrrw t0, 4095, t1
+# CHECK-NEXT: 1 1 1.00 U 1 XSPipeBJU3,XSPipeGroupInt,XSPipeIntIQ3 CSRRS csrrs s3, fflags, s5
+# CHECK-NEXT: 1 1 1.00 U 1 XSPipeBJU3,XSPipeGroupInt,XSPipeIntIQ3 CSRRC csrrc sp, 0, ra
+# CHECK-NEXT: 1 1 1.00 U 1 XSPipeBJU3,XSPipeGroupInt,XSPipeIntIQ3 CSRRWI csrrwi a5, 0, 0
+# CHECK-NEXT: 1 1 1.00 U 1 XSPipeBJU3,XSPipeGroupInt,XSPipeIntIQ3 CSRRSI csrrsi t2, 4095, 31
+# CHECK-NEXT: 1 1 1.00 U 1 XSPipeBJU3,XSPipeGroupInt,XSPipeIntIQ3 CSRRCI csrrci t1, sscratch, 5
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 7.75 7.75 7.75 7.75 2.67 2.67 2.67 6.00 - - - - - 2.33 2.33 2.33 2.00 2.00 2.00 2.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addi a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addiw a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - slti a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - seqz a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andi a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - ori a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xori a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - slli a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - srli a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - srai a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - slliw a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - srliw a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sraiw a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - lui a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - auipc a1, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - add a0, a0, a1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - addw a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - slt a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sltu a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - and a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - or a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xor a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sll a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - srl a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sra a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sllw a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - srlw a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sraw a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sub a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - subw a0, a0, a0
+# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - - - - jal a0, .Ltmp0
+# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - - - - jalr a0
+# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - - - - beq a0, a0, .Ltmp1
+# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - - - - bne a0, a0, .Ltmp2
+# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - - - - blt a0, a0, .Ltmp3
+# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - - - - bltu a0, a0, .Ltmp4
+# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - - - - bge a0, a0, .Ltmp5
+# CHECK-NEXT: - - - - 0.33 0.33 0.33 - - - - - - - - - - - - - bgeu a0, a0, .Ltmp6
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - add a0, a0, a0
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lb t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lbu t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lh t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lhu t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lw t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - lwu t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - ld t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sb t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sh t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sw t0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 sd t0, 0(a0)
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - - csrrw t0, 4095, t1
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - - csrrs s3, fflags, s5
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - - csrrc sp, 0, ra
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - - csrrwi a5, 0, 0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - - csrrsi t2, 4095, 31
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - - - - csrrci t1, sscratch, 5
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s
deleted file mode 100644
index ac95fce7e614a..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-store.s
+++ /dev/null
@@ -1,100 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
-
-lb a0, 0(a1)
-lh a0, 0(a1)
-lw a0, 0(a1)
-ld a0, 0(a1)
-lbu a0, 0(a1)
-lhu a0, 0(a1)
-lwu a0, 0(a1)
-
-flw fa0, 0(a1)
-fld fa0, 0(a1)
-
-sb a0, 0(a1)
-sh a0, 0(a1)
-sw a0, 0(a1)
-sd a0, 0(a1)
-
-fsw fa0, 0(a1)
-fsd fa0, 0(a1)
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 15
-# CHECK-NEXT: Total Cycles: 15
-# CHECK-NEXT: Total uOps: 15
-
-# CHECK: Dispatch Width: 6
-# CHECK-NEXT: uOps Per Cycle: 1.00
-# CHECK-NEXT: IPC: 1.00
-# CHECK-NEXT: Block RThroughput: 3.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 6 0.33 * lb a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * lh a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * lw a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * ld a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * lbu a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * lhu a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * lwu a0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * flw fa0, 0(a1)
-# CHECK-NEXT: 1 6 0.33 * fld fa0, 0(a1)
-# CHECK-NEXT: 1 4 0.25 * sb a0, 0(a1)
-# CHECK-NEXT: 1 4 0.25 * sh a0, 0(a1)
-# CHECK-NEXT: 1 4 0.25 * sw a0, 0(a1)
-# CHECK-NEXT: 1 4 0.25 * sd a0, 0(a1)
-# CHECK-NEXT: 1 4 0.25 * fsw fa0, 0(a1)
-# CHECK-NEXT: 1 4 0.25 * fsd fa0, 0(a1)
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - XSPipeALU0
-# CHECK-NEXT: [1] - XSPipeALU1
-# CHECK-NEXT: [2] - XSPipeALU2
-# CHECK-NEXT: [3] - XSPipeALU3
-# CHECK-NEXT: [4] - XSPipeBJU0
-# CHECK-NEXT: [5] - XSPipeBJU1
-# CHECK-NEXT: [6] - XSPipeBJU2
-# CHECK-NEXT: [7] - XSPipeBJU3
-# CHECK-NEXT: [8] - XSPipeFEX0
-# CHECK-NEXT: [9] - XSPipeFEX1
-# CHECK-NEXT: [10] - XSPipeFEX2
-# CHECK-NEXT: [11] - XSPipeFEX3
-# CHECK-NEXT: [12] - XSPipeFEX4
-# CHECK-NEXT: [13.0] - XSPipeLDU
-# CHECK-NEXT: [13.1] - XSPipeLDU
-# CHECK-NEXT: [13.2] - XSPipeLDU
-# CHECK-NEXT: [14.0] - XSPipeSTA
-# CHECK-NEXT: [14.1] - XSPipeSTA
-# CHECK-NEXT: [15.0] - XSPipeSTD
-# CHECK-NEXT: [15.1] - XSPipeSTD
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
-# CHECK-NEXT: - - - - - - - - - - - - - 3.00 3.00 3.00 1.00 1.00 2.00 2.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lb a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - lh a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lw a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - ld a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - lbu a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - 1.00 - - - - lhu a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - lwu a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - 1.00 - - - - - - flw fa0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - 1.00 - - - - - fld fa0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 sb a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - sh a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - - 1.00 - - sw a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - 1.00 - - - sd a0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - - - - 1.00 fsw fa0, 0(a1)
-# CHECK-NEXT: - - - - - - - - - - - - - - - - - - 1.00 - fsd fa0, 0(a1)
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
index 7665598ab198e..d0dbb11882e93 100644
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
@@ -6,12 +6,12 @@ addi a2, a1, 1
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2
-# CHECK-NEXT: Total Cycles: 9
+# CHECK-NEXT: Total Cycles: 7
# CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 6
-# CHECK-NEXT: uOps Per Cycle: 0.22
-# CHECK-NEXT: IPC: 0.22
+# CHECK-NEXT: uOps Per Cycle: 0.29
+# CHECK-NEXT: IPC: 0.29
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -23,7 +23,7 @@ addi a2, a1, 1
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 6 0.33 * ld a1, 0(a0)
+# CHECK-NEXT: 1 4 0.33 * ld a1, 0(a0)
# CHECK-NEXT: 1 1 0.25 addi a2, a1, 1
# CHECK: Resources:
@@ -58,10 +58,10 @@ addi a2, a1, 1
# CHECK-NEXT: - - - 1.00 - - - - - - - - - - - - - - - - addi a2, a1, 1
# CHECK: Timeline view:
-# CHECK-NEXT: Index 012345678
+# CHECK-NEXT: Index 0123456
-# CHECK: [0,0] DeeeeeeER ld a1, 0(a0)
-# CHECK-NEXT: [0,1] D====eE-R addi a2, a1, 1
+# CHECK: [0,0] DeeeeER ld a1, 0(a0)
+# CHECK-NEXT: [0,1] D==eE-R addi a2, a1, 1
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -71,5 +71,5 @@ addi a2, a1, 1
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld a1, 0(a0)
-# CHECK-NEXT: 1. 1 5.0 0.0 1.0 addi a2, a1, 1
-# CHECK-NEXT: 1 3.0 0.5 0.5 <total>
+# CHECK-NEXT: 1. 1 3.0 0.0 1.0 addi a2, a1, 1
+# CHECK-NEXT: 1 2.0 0.5 0.5 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
index 6c3ffe9f2ff8e..11c9a2c9a77e3 100644
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
@@ -6,12 +6,12 @@ fadd.s fa2, fa1, fa3
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2
-# CHECK-NEXT: Total Cycles: 10
+# CHECK-NEXT: Total Cycles: 8
# CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 6
-# CHECK-NEXT: uOps Per Cycle: 0.20
-# CHECK-NEXT: IPC: 0.20
+# CHECK-NEXT: uOps Per Cycle: 0.25
+# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 0.3
# CHECK: Instruction Info:
@@ -23,7 +23,7 @@ fadd.s fa2, fa1, fa3
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 6 0.33 * fld fa1, 0(a0)
+# CHECK-NEXT: 1 4 0.33 * fld fa1, 0(a0)
# CHECK-NEXT: 1 1 0.33 fadd.s fa2, fa1, fa3
# CHECK: Resources:
@@ -58,10 +58,10 @@ fadd.s fa2, fa1, fa3
# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fadd.s fa2, fa1, fa3
# CHECK: Timeline view:
-# CHECK-NEXT: Index 0123456789
+# CHECK-NEXT: Index 01234567
-# CHECK: [0,0] DeeeeeeER. fld fa1, 0(a0)
-# CHECK-NEXT: [0,1] D======eER fadd.s fa2, fa1, fa3
+# CHECK: [0,0] DeeeeER. fld fa1, 0(a0)
+# CHECK-NEXT: [0,1] D====eER fadd.s fa2, fa1, fa3
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
@@ -71,5 +71,5 @@ fadd.s fa2, fa1, fa3
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 fld fa1, 0(a0)
-# CHECK-NEXT: 1. 1 7.0 0.0 0.0 fadd.s fa2, fa1, fa3
-# CHECK-NEXT: 1 4.0 0.5 0.0 <total>
+# CHECK-NEXT: 1. 1 5.0 0.0 0.0 fadd.s fa2, fa1, fa3
+# CHECK-NEXT: 1 3.0 0.5 0.0 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div-rv32.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div-rv32.test
new file mode 100644
index 0000000000000..82779e1b94a6d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div-rv32.test
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/mul-div-rv32.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL C_MUL mul a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL MULH mulh a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL MULHU mulhu a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL MULHSU mulhsu a0, a0, a0
+# CHECK-NEXT: 1 19 19.00 19 XSPipeBJU3[19],XSPipeGroupInt[19],XSPipeIntIQ3[19] DIV div a0, a1, a2
+# CHECK-NEXT: 1 19 19.00 19 XSPipeBJU3[19],XSPipeGroupInt[19],XSPipeIntIQ3[19] DIVU divu a0, a1, a2
+# CHECK-NEXT: 1 19 19.00 19 XSPipeBJU3[19],XSPipeGroupInt[19],XSPipeIntIQ3[19] REM rem a0, a1, a2
+# CHECK-NEXT: 1 19 19.00 19 XSPipeBJU3[19],XSPipeGroupInt[19],XSPipeIntIQ3[19] REMU remu a0, a1, a2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 2.00 2.00 - - - - - 76.00 - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - mul a0, a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - mulh a0, a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - mulhu a0, a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - mulhsu a0, a0, a0
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - div a0, a1, a2
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - divu a0, a1, a2
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - rem a0, a1, a2
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - remu a0, a1, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div.test
new file mode 100644
index 0000000000000..613379b7fab39
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-div.test
@@ -0,0 +1,105 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/mul-div.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL C_MUL mul a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL MULH mulh a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL MULHU mulhu a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL MULHSU mulhsu a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL MULW mulw a0, a0, a0
+# CHECK-NEXT: 1 19 19.00 19 XSPipeBJU3[19],XSPipeGroupInt[19],XSPipeIntIQ3[19] DIV div a0, a1, a2
+# CHECK-NEXT: 1 19 19.00 19 XSPipeBJU3[19],XSPipeGroupInt[19],XSPipeIntIQ3[19] DIVU divu a0, a1, a2
+# CHECK-NEXT: 1 19 19.00 19 XSPipeBJU3[19],XSPipeGroupInt[19],XSPipeIntIQ3[19] REM rem a0, a1, a2
+# CHECK-NEXT: 1 19 19.00 19 XSPipeBJU3[19],XSPipeGroupInt[19],XSPipeIntIQ3[19] REMU remu a0, a1, a2
+# CHECK-NEXT: 1 11 11.00 11 XSPipeBJU3[11],XSPipeGroupInt[11],XSPipeIntIQ3[11] DIVW divw a0, a1, a2
+# CHECK-NEXT: 1 11 11.00 11 XSPipeBJU3[11],XSPipeGroupInt[11],XSPipeIntIQ3[11] DIVUW divuw a0, a1, a2
+# CHECK-NEXT: 1 11 11.00 11 XSPipeBJU3[11],XSPipeGroupInt[11],XSPipeIntIQ3[11] REMW remw a0, a1, a2
+# CHECK-NEXT: 1 11 11.00 11 XSPipeBJU3[11],XSPipeGroupInt[11],XSPipeIntIQ3[11] REMUW remuw a0, a1, a2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 2.50 2.50 - - - - - 120.00 - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - mul a0, a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - mulh a0, a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - mulhu a0, a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - mulhsu a0, a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - mulw a0, a0, a0
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - div a0, a1, a2
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - divu a0, a1, a2
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - rem a0, a1, a2
+# CHECK-NEXT: - - - - - - - 19.00 - - - - - - - - - - - - remu a0, a1, a2
+# CHECK-NEXT: - - - - - - - 11.00 - - - - - - - - - - - - divw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 11.00 - - - - - - - - - - - - divuw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 11.00 - - - - - - - - - - - - remw a0, a1, a2
+# CHECK-NEXT: - - - - - - - 11.00 - - - - - - - - - - - - remuw a0, a1, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s
deleted file mode 100644
index 1b36ac96d1fa8..0000000000000
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/mul-fmul.s
+++ /dev/null
@@ -1,74 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 < %s | FileCheck %s
-
-mul a0, a1, a2
-mulh a0, a1, a2
-mulhsu a0, a1, a2
-mulhu a0, a1, a2
-mulw a0, a1, a2
-
-fmul.s fa0, fa1, fa2
-fmul.d fa0, fa1, fa2
-
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 7
-# CHECK-NEXT: Total Cycles: 7
-# CHECK-NEXT: Total uOps: 7
-
-# CHECK: Dispatch Width: 6
-# CHECK-NEXT: uOps Per Cycle: 1.00
-# CHECK-NEXT: IPC: 1.00
-# CHECK-NEXT: Block RThroughput: 2.5
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 2 0.50 mul a0, a1, a2
-# CHECK-NEXT: 1 2 0.50 mulh a0, a1, a2
-# CHECK-NEXT: 1 2 0.50 mulhsu a0, a1, a2
-# CHECK-NEXT: 1 2 0.50 mulhu a0, a1, a2
-# CHECK-NEXT: 1 2 0.50 mulw a0, a1, a2
-# CHECK-NEXT: 1 3 0.33 fmul.s fa0, fa1, fa2
-# CHECK-NEXT: 1 3 0.33 fmul.d fa0, fa1, fa2
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - XSPipeALU0
-# CHECK-NEXT: [1] - XSPipeALU1
-# CHECK-NEXT: [2] - XSPipeALU2
-# CHECK-NEXT: [3] - XSPipeALU3
-# CHECK-NEXT: [4] - XSPipeBJU0
-# CHECK-NEXT: [5] - XSPipeBJU1
-# CHECK-NEXT: [6] - XSPipeBJU2
-# CHECK-NEXT: [7] - XSPipeBJU3
-# CHECK-NEXT: [8] - XSPipeFEX0
-# CHECK-NEXT: [9] - XSPipeFEX1
-# CHECK-NEXT: [10] - XSPipeFEX2
-# CHECK-NEXT: [11] - XSPipeFEX3
-# CHECK-NEXT: [12] - XSPipeFEX4
-# CHECK-NEXT: [13.0] - XSPipeLDU
-# CHECK-NEXT: [13.1] - XSPipeLDU
-# CHECK-NEXT: [13.2] - XSPipeLDU
-# CHECK-NEXT: [14.0] - XSPipeSTA
-# CHECK-NEXT: [14.1] - XSPipeSTA
-# CHECK-NEXT: [15.0] - XSPipeSTD
-# CHECK-NEXT: [15.1] - XSPipeSTD
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
-# CHECK-NEXT: 2.00 3.00 - - - - - - - - 1.00 - 1.00 - - - - - - -
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mul a0, a1, a2
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulh a0, a1, a2
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulhsu a0, a1, a2
-# CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - - - - mulhu a0, a1, a2
-# CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - - - - mulw a0, a1, a2
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 - - - - - - - fmul.s fa0, fa1, fa2
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - - - - - - - - fmul.d fa0, fa1, fa2
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zba.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zba.test
new file mode 100644
index 0000000000000..ac0cdfc37c9ab
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zba.test
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/zba.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt ADD_UW add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SLLI_UW slli.uw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SH1ADD_UW sh1add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SH2ADD_UW sh2add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SH3ADD_UW sh3add.uw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SH1ADD sh1add a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SH2ADD sh2add a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt SH3ADD sh3add a0, a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 2.00 2.00 2.00 2.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - add.uw a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - slli.uw a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sh1add.uw a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sh2add.uw a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sh3add.uw a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sh1add a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sh2add a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sh3add a0, a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbb.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbb.test
new file mode 100644
index 0000000000000..4f81b14d31cc1
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbb.test
@@ -0,0 +1,127 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/zbb.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt ANDN andn a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt ORN orn a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt XNOR xnor a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL CLZ clz a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL CLZW clzw a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL CTZ ctz a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL CTZW ctzw a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL CPOP cpop a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL CPOPW cpopw a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt MIN min a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt MINU minu a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt MAX max a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt MAXU maxu a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_SEXT_B sext.b a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_SEXT_H sext.h a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt C_ZEXT_H zext.h a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt ROL rol a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt ROLW rolw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt ROR ror a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt RORW rorw a0, a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt RORI rori a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt RORIW roriw a0, a0, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt ORC_B orc.b a0, a0
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt REV8_RV64 rev8 a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 7.50 7.50 4.50 4.50 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - andn a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orn a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - xnor a0, a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - clz a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - clzw a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - ctz a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - ctzw a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - cpop a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - cpopw a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - min a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - minu a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - max a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - maxu a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sext.b a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - sext.h a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - zext.h a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rol a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rolw a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - ror a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rorw a0, a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rori a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - roriw a0, a0, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - orc.b a0, a0
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - rev8 a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbc.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbc.test
new file mode 100644
index 0000000000000..cf2aa78e15956
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbc.test
@@ -0,0 +1,85 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/zbc.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL CLMUL clmul a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL CLMULR clmulr a0, a0, a0
+# CHECK-NEXT: 1 3 0.50 3 XSPipeGroupALU,XSPipeGroupBKU,XSPipeGroupInt,XSPipeGroupMUL CLMULH clmulh a0, a0, a0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 1.50 1.50 - - - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - clmul a0, a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - clmulr a0, a0, a0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - - - - - - - - clmulh a0, a0, a0
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbs.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbs.test
new file mode 100644
index 0000000000000..342c2bb12e398
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zbs.test
@@ -0,0 +1,95 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/zbs.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt BCLR bclr a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt BCLRI bclri a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt BEXT bext a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt BEXTI bexti a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt BINV binv a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt BINVI binvi a0, a1, 1
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt BSET bset a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt BSETI bseti a0, a1, 1
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 2.00 2.00 2.00 2.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bclr a0, a1, a2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bclri a0, a1, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bext a0, a1, a2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bexti a0, a1, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - binv a0, a1, a2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - binvi a0, a1, 1
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bset a0, a1, a2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - bseti a0, a1, 1
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfh.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfh.test
new file mode 100644
index 0000000000000..d71a6ed69f72f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfh.test
@@ -0,0 +1,109 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/zfh.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FADD_H fadd.h fs10, fs11, ft8
+# CHECK-NEXT: 1 1 0.33 1 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FSUB_H fsub.h ft9, ft10, ft11
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMUL_H fmul.h ft0, ft1, ft2
+# CHECK-NEXT: 1 9 4.50 9 XSPipeGroupFDIV[9],XSPipeGroupFP[9] FDIV_H fdiv.h ft3, ft4, ft5
+# CHECK-NEXT: 1 10 5.00 10 XSPipeGroupFDIV[10],XSPipeGroupFP[10] FSQRT_H fsqrt.h ft6, ft7
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMIN_H fmin.h fa5, fa6, fa7
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMAX_H fmax.h fs2, fs3, fs4
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMADD_H fmadd.h fa0, fa1, fa2, ft11
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMSUB_H fmsub.h fa4, fa5, fa6, fa7
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FNMSUB_H fnmsub.h fs2, fs3, fs4, fs5
+# CHECK-NEXT: 1 4 0.33 4 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FNMADD_H fnmadd.h fs6, fs7, fs8, fs9
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FEQ_H feq.h a1, fs8, fs9
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FLT_H flt.h a2, fs10, fs11
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FLE_H fle.h a3, ft8, ft9
+# CHECK-NEXT: 1 2 0.33 2 XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCLASS_H fclass.h a3, ft10
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - - - 4.33 9.50 4.33 9.50 4.33 - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fadd.h fs10, fs11, ft8
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fsub.h ft9, ft10, ft11
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmul.h ft0, ft1, ft2
+# CHECK-NEXT: - - - - - - - - - 4.50 - 4.50 - - - - - - - - fdiv.h ft3, ft4, ft5
+# CHECK-NEXT: - - - - - - - - - 5.00 - 5.00 - - - - - - - - fsqrt.h ft6, ft7
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmin.h fa5, fa6, fa7
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmax.h fs2, fs3, fs4
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmadd.h fa0, fa1, fa2, ft11
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fmsub.h fa4, fa5, fa6, fa7
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fnmsub.h fs2, fs3, fs4, fs5
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fnmadd.h fs6, fs7, fs8, fs9
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - feq.h a1, fs8, fs9
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - flt.h a2, fs10, fs11
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fle.h a3, ft8, ft9
+# CHECK-NEXT: - - - - - - - - 0.33 - 0.33 - 0.33 - - - - - - - fclass.h a3, ft10
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfhmin.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfhmin.test
new file mode 100644
index 0000000000000..d8bff02a00281
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zfhmin.test
@@ -0,0 +1,99 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/zfhmin.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 4 0.33 * 4 XSPipeLDU,XSPipeMemIQ FLH flh ft0, 0(a0)
+# CHECK-NEXT: 1 4 0.50 * 4 XSPipeMemIQ[2],XSPipeSTA,XSPipeSTD FSH fsh ft0, 0(a0)
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FMV_X_H fmv.x.h a2, fs7
+# CHECK-NEXT: 1 1 1.00 1 XSPipeBJU2,XSPipeGroupBRU,XSPipeGroupInt,XSPipeIntIQ2 FMV_H_X fmv.h.x ft1, a6
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_S_H fcvt.s.h fa0, ft0
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_S_H fcvt.s.h fa0, ft0, rup
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_H_S fcvt.h.s ft2, fa2
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_D_H fcvt.d.h fa0, ft0
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_D_H fcvt.d.h fa0, ft0, rup
+# CHECK-NEXT: 1 3 1.00 3 XSPipeFEX0,XSPipeFpIQ0,XSPipeGroupFALU,XSPipeGroupFMA,XSPipeGroupFP FCVT_H_D fcvt.h.d ft2, fa2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: - - - - - - 1.00 - 7.00 - - - - 0.33 0.33 0.33 0.50 0.50 0.50 0.50
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - - 0.33 0.33 0.33 - - - - flh ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - - - - - - - - - 0.50 0.50 0.50 0.50 fsh ft0, 0(a0)
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fmv.x.h a2, fs7
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - - - - - - - - fmv.h.x ft1, a6
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.s.h fa0, ft0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.s.h fa0, ft0, rup
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.h.s ft2, fa2
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.d.h fa0, ft0
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.d.h fa0, ft0, rup
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - - - - - - - - fcvt.h.d ft2, fa2
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zicond.test b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zicond.test
new file mode 100644
index 0000000000000..adf0920d5e5ea
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/zicond.test
@@ -0,0 +1,87 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=xiangshan-kunminghu -iterations=1 -instruction-tables=full %p/../Inputs/zicond.s | FileCheck %s
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0:1
+# CHECK-NEXT: [1] - XSPipeALU1:1
+# CHECK-NEXT: [2] - XSPipeALU2:1
+# CHECK-NEXT: [3] - XSPipeALU3:1
+# CHECK-NEXT: [4] - XSPipeBJU0:1
+# CHECK-NEXT: [5] - XSPipeBJU1:1
+# CHECK-NEXT: [6] - XSPipeBJU2:1
+# CHECK-NEXT: [7] - XSPipeBJU3:1
+# CHECK-NEXT: [8] - XSPipeFEX0:1
+# CHECK-NEXT: [9] - XSPipeFEX1:1
+# CHECK-NEXT: [10] - XSPipeFEX2:1
+# CHECK-NEXT: [11] - XSPipeFEX3:1
+# CHECK-NEXT: [12] - XSPipeFEX4:1
+# CHECK-NEXT: [13] - XSPipeFpIQ0:2 XSPipeFEX0, XSPipeFEX1
+# CHECK-NEXT: [14] - XSPipeFpIQ1:2 XSPipeFEX2, XSPipeFEX3
+# CHECK-NEXT: [15] - XSPipeFpIQ2:1 XSPipeFEX4
+# CHECK-NEXT: [16] - XSPipeGroupALU:4 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3
+# CHECK-NEXT: [17] - XSPipeGroupBKU:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [18] - XSPipeGroupBRU:3 XSPipeBJU0, XSPipeBJU1, XSPipeBJU2
+# CHECK-NEXT: [19] - XSPipeGroupFALU:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [20] - XSPipeGroupFDIV:2 XSPipeFEX1, XSPipeFEX3
+# CHECK-NEXT: [21] - XSPipeGroupFMA:3 XSPipeFEX0, XSPipeFEX2, XSPipeFEX4
+# CHECK-NEXT: [22] - XSPipeGroupFP:5 XSPipeFEX0, XSPipeFEX1, XSPipeFEX2, XSPipeFEX3, XSPipeFEX4
+# CHECK-NEXT: [23] - XSPipeGroupInt:8 XSPipeALU0, XSPipeALU1, XSPipeALU2, XSPipeALU3, XSPipeBJU0, XSPipeBJU1, XSPipeBJU2, XSPipeBJU3
+# CHECK-NEXT: [24] - XSPipeGroupMUL:2 XSPipeALU0, XSPipeALU1
+# CHECK-NEXT: [25] - XSPipeIntIQ0:2 XSPipeALU0, XSPipeBJU0
+# CHECK-NEXT: [26] - XSPipeIntIQ1:2 XSPipeALU1, XSPipeBJU1
+# CHECK-NEXT: [27] - XSPipeIntIQ2:2 XSPipeALU2, XSPipeBJU2
+# CHECK-NEXT: [28] - XSPipeIntIQ3:2 XSPipeALU3, XSPipeBJU3
+# CHECK-NEXT: [29] - XSPipeLDU:3
+# CHECK-NEXT: [30] - XSPipeMemIQ:7 XSPipeLDU, XSPipeLDU, XSPipeLDU, XSPipeSTA, XSPipeSTA, XSPipeSTD, XSPipeSTD
+# CHECK-NEXT: [31] - XSPipeSTA:2
+# CHECK-NEXT: [32] - XSPipeSTD:2
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt CZERO_EQZ czero.eqz a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt CZERO_NEZ czero.nez a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt CZERO_EQZ czero.eqz a0, a1, a2
+# CHECK-NEXT: 1 1 0.25 1 XSPipeGroupALU,XSPipeGroupInt CZERO_NEZ czero.nez a0, a1, a2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - XSPipeALU0
+# CHECK-NEXT: [1] - XSPipeALU1
+# CHECK-NEXT: [2] - XSPipeALU2
+# CHECK-NEXT: [3] - XSPipeALU3
+# CHECK-NEXT: [4] - XSPipeBJU0
+# CHECK-NEXT: [5] - XSPipeBJU1
+# CHECK-NEXT: [6] - XSPipeBJU2
+# CHECK-NEXT: [7] - XSPipeBJU3
+# CHECK-NEXT: [8] - XSPipeFEX0
+# CHECK-NEXT: [9] - XSPipeFEX1
+# CHECK-NEXT: [10] - XSPipeFEX2
+# CHECK-NEXT: [11] - XSPipeFEX3
+# CHECK-NEXT: [12] - XSPipeFEX4
+# CHECK-NEXT: [13.0] - XSPipeLDU
+# CHECK-NEXT: [13.1] - XSPipeLDU
+# CHECK-NEXT: [13.2] - XSPipeLDU
+# CHECK-NEXT: [14.0] - XSPipeSTA
+# CHECK-NEXT: [14.1] - XSPipeSTA
+# CHECK-NEXT: [15.0] - XSPipeSTD
+# CHECK-NEXT: [15.1] - XSPipeSTD
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1]
+# CHECK-NEXT: 1.00 1.00 1.00 1.00 - - - - - - - - - - - - - - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13.0] [13.1] [13.2] [14.0] [14.1] [15.0] [15.1] Instructions:
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - czero.eqz a0, a1, a2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - czero.nez a0, a1, a2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - czero.eqz a0, a1, a2
+# CHECK-NEXT: 0.25 0.25 0.25 0.25 - - - - - - - - - - - - - - - - czero.nez a0, a1, a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/cascade-fma.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/cascade-fma.s
rename to llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/gpr-bypass.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/gpr-bypass.s
rename to llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/load-to-alu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s
similarity index 100%
rename from llvm/test/tools/llvm-mca/RISCV/XiangShan-Nanhu/load-to-alu.s
rename to llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s
>From 3d9953512012e2e9126e498b919c59358b3b302b Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Thu, 28 May 2026 16:00:24 +0700
Subject: [PATCH 05/10] [RISCV][llvm-mca] Fix total iteration count in
XiangShan Kunminghu test checks
---
llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s | 2 +-
.../test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s | 2 +-
.../test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
index 12514a4812394..fffc44b1e3386 100644
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/div-fdiv.s
@@ -117,4 +117,4 @@ fsqrt.d fa0, fa1
# CHECK-NEXT: 9. 1 1.0 1.0 105.0 fdiv.d fa0, fa1, fa2
# CHECK-NEXT: 10. 1 10.0 10.0 100.0 fsqrt.s fa0, fa1
# CHECK-NEXT: 11. 1 15.0 15.0 89.0 fsqrt.d fa0, fa1
-# CHECK-NEXT: 1 40.4 40.4 33.7 <total>
+# CHECK-NEXT: 12 40.4 40.4 33.7 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
index d0dbb11882e93..71c8bc1bb1f7d 100644
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-alu.s
@@ -72,4 +72,4 @@ addi a2, a1, 1
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 ld a1, 0(a0)
# CHECK-NEXT: 1. 1 3.0 0.0 1.0 addi a2, a1, 1
-# CHECK-NEXT: 1 2.0 0.5 0.5 <total>
+# CHECK-NEXT: 2 2.0 0.5 0.5 <total>
diff --git a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
index 11c9a2c9a77e3..7df24eba73256 100644
--- a/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
+++ b/llvm/test/tools/llvm-mca/RISCV/XiangShan-Kunminghu/load-to-fpu.s
@@ -72,4 +72,4 @@ fadd.s fa2, fa1, fa3
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 fld fa1, 0(a0)
# CHECK-NEXT: 1. 1 5.0 0.0 0.0 fadd.s fa2, fa1, fa3
-# CHECK-NEXT: 1 3.0 0.5 0.0 <total>
+# CHECK-NEXT: 2 3.0 0.5 0.0 <total>
>From 5cc562a89fe2273bba7dd4829a58bca1d85700ed Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Fri, 29 May 2026 10:30:03 +0700
Subject: [PATCH 06/10] [RISCV] Remove unused LoopMicroOpBufferSize setting
---
llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
index 1b6f38a64bada..535bee80077b6 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -24,7 +24,6 @@
def XiangShanKunMingHuModel : SchedMachineModel {
let IssueWidth = 6; // 6-way decode and dispatch
let MicroOpBufferSize = 160; // ROB size
- let LoopMicroOpBufferSize = 48; // Instruction queue size
let LoadLatency = 4;
let MispredictPenalty = 13; // Based on estimate of pipeline depth.
let CompleteModel = 0;
>From ddc98e53d1ee42cfecc8783747cfc345534742c9 Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Fri, 29 May 2026 11:45:50 +0700
Subject: [PATCH 07/10] [RISCV] NFC: Clean up KunMingHu scheduler comments
Remove trailing whitespace and stale I2V/F2V mentions from the KunMingHu scheduling model comments.
---
.../RISCV/RISCVSchedXiangShanKunMingHu.td | 30 +++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
index 535bee80077b6..d432e7ec8cf19 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -6,13 +6,13 @@
//
//===----------------------------------------------------------------------===//
-// The XiangShan is a high-performance open-source RISC-V processor project
-// initiated by the Institute of Computing Technology(ICT),
-// Chinese Academy of Sciences(CAS).
-// The KunMingHu architecture is its third-generation derivative,
-// developed by the Institute of Computing Technology(ICT),
-// Chinese Academy of Sciences(CAS)
-// and the Beijing Institute of Open Source Chip (BOSC),
+// The XiangShan is a high-performance open-source RISC-V processor project
+// initiated by the Institute of Computing Technology(ICT),
+// Chinese Academy of Sciences(CAS).
+// The KunMingHu architecture is its third-generation derivative,
+// developed by the Institute of Computing Technology(ICT),
+// Chinese Academy of Sciences(CAS)
+// and the Beijing Institute of Open Source Chip (BOSC),
// with a focus on achieving higher performance.
// Source: https://github.com/OpenXiangShan/XiangShan
// Documentation: https://docs.xiangshan.cc/projects/design/en/latest/
@@ -27,7 +27,7 @@ def XiangShanKunMingHuModel : SchedMachineModel {
let LoadLatency = 4;
let MispredictPenalty = 13; // Based on estimate of pipeline depth.
let CompleteModel = 0;
- let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZkr,
+ let UnsupportedFeatures = [HasStdExtZcmt, HasStdExtZkr,
HasVInstructions,
HasVInstructionsI64];
}
@@ -43,22 +43,22 @@ def XSPipeALU3 : ProcResource<1>; // ALU
def XSPipeBJU0 : ProcResource<1>; // BRU, JMP
def XSPipeBJU1 : ProcResource<1>; // BRU, JMP
-def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, I2V, VSet
+def XSPipeBJU2 : ProcResource<1>; // BRU, JMP, I2F, VSet
def XSPipeBJU3 : ProcResource<1>; // CSR, Fence, DIV
// Floating-point execution units
-def XSPipeFEX0 : ProcResource<1>; // FALU, FMA, FCVT, F2V
+def XSPipeFEX0 : ProcResource<1>; // FALU, FMA, FCVT
def XSPipeFEX1 : ProcResource<1>; // FDIV
def XSPipeFEX2 : ProcResource<1>; // FALU, FMA
def XSPipeFEX3 : ProcResource<1>; // FDIV
def XSPipeFEX4 : ProcResource<1>; // FALU, FMA
// Parent groups containing all resources to satisfy TableGen overlap rules
-def XSPipeGroupInt : ProcResGroup<[XSPipeALU0, XSPipeALU1,
+def XSPipeGroupInt : ProcResGroup<[XSPipeALU0, XSPipeALU1,
XSPipeALU2, XSPipeALU3,
- XSPipeBJU0, XSPipeBJU1,
+ XSPipeBJU0, XSPipeBJU1,
XSPipeBJU2, XSPipeBJU3]>;
-def XSPipeGroupFP : ProcResGroup<[XSPipeFEX0, XSPipeFEX1,
+def XSPipeGroupFP : ProcResGroup<[XSPipeFEX0, XSPipeFEX1,
XSPipeFEX2, XSPipeFEX3, XSPipeFEX4]>;
// Issue Queue groups with BufferSize for llvm-mca buffer tracking
@@ -87,7 +87,7 @@ let BufferSize = 16 in
def XSPipeMemIQ : ProcResGroup<[XSPipeLDU, XSPipeSTA, XSPipeSTD]>;
// Instruction dispatch groups for scheduling
-def XSPipeGroupALU : ProcResGroup<[XSPipeALU0, XSPipeALU1, XSPipeALU2,
+def XSPipeGroupALU : ProcResGroup<[XSPipeALU0, XSPipeALU1, XSPipeALU2,
XSPipeALU3]>;
def XSPipeGroupMUL : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
def XSPipeGroupBKU : ProcResGroup<[XSPipeALU0, XSPipeALU1]>;
@@ -227,7 +227,7 @@ let Latency = 3 in {
def : WriteRes<WriteFCvtF32ToF64, [XSPipeFEX0]>;
def : WriteRes<WriteFCvtF64ToF16, [XSPipeFEX0]>;
def : WriteRes<WriteFCvtF64ToF32, [XSPipeFEX0]>;
-
+
// FCVT (I2F)
def : WriteRes<WriteFCvtI32ToF16, [XSPipeBJU2]>;
def : WriteRes<WriteFCvtI32ToF32, [XSPipeBJU2]>;
>From 2f58374390a70a7818ec6252c2ccf007174a91b5 Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Fri, 29 May 2026 13:12:24 +0700
Subject: [PATCH 08/10] [RISCV] Fix doc URL path in XiangShan KunMingHu
scheduling model
---
llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
index d432e7ec8cf19..60da8f9237517 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -19,7 +19,7 @@
// User Guide: https://docs.xiangshan.cc/projects/user-guide/en/latest/
// Typical Configurations & Instruction Latency:
// https://docs.xiangshan.cc/projects/user-guide/en/latest/
-// kunminghu-v3/typical-configuration/
+// kunminghu-v2/typical-configuration/
def XiangShanKunMingHuModel : SchedMachineModel {
let IssueWidth = 6; // 6-way decode and dispatch
>From 3cdc81b2332df605e5ecd135298e8e3e5ec57740 Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Fri, 29 May 2026 13:18:01 +0700
Subject: [PATCH 09/10] [RISCV] Update doc URL path in XiangShan KunMingHu
scheduling model
---
llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
index 60da8f9237517..650cfb55680fa 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -18,7 +18,7 @@
// Documentation: https://docs.xiangshan.cc/projects/design/en/latest/
// User Guide: https://docs.xiangshan.cc/projects/user-guide/en/latest/
// Typical Configurations & Instruction Latency:
-// https://docs.xiangshan.cc/projects/user-guide/en/latest/
+// https://docs.xiangshan.cc/projects/user-guide/en/
// kunminghu-v2/typical-configuration/
def XiangShanKunMingHuModel : SchedMachineModel {
>From 4d60b00585ee109f9ad1b142b6fb992d044d2c1a Mon Sep 17 00:00:00 2001
From: LinWang <linwang2048 at 163.com>
Date: Fri, 17 Jul 2026 16:47:26 +0700
Subject: [PATCH 10/10] =?UTF-8?q?=E6=96=87=E6=A1=A3(riscv):=20=E6=9B=B4?=
=?UTF-8?q?=E6=96=B0=E5=85=B8=E5=9E=8B=E9=85=8D=E7=BD=AEURL=E4=B8=BA?=
=?UTF-8?q?=E7=9B=B4=E6=8E=A5=E9=93=BE=E6=8E=A5?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
---
llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
index 650cfb55680fa..1f065e254ec78 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedXiangShanKunMingHu.td
@@ -18,8 +18,7 @@
// Documentation: https://docs.xiangshan.cc/projects/design/en/latest/
// User Guide: https://docs.xiangshan.cc/projects/user-guide/en/latest/
// Typical Configurations & Instruction Latency:
-// https://docs.xiangshan.cc/projects/user-guide/en/
-// kunminghu-v2/typical-configuration/
+// https://docs.xiangshan.cc/projects/user-guide/en/kunminghu-v2/typical-configuration/
def XiangShanKunMingHuModel : SchedMachineModel {
let IssueWidth = 6; // 6-way decode and dispatch
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