[llvm] [RISCV] Add scheduler definitions for XiangShan-KunMingHu (PR #148581)

[Craig Topper via llvm-commits]

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@@ -0,0 +1,434 @@
+//==- RISCVSchedXiangShanKunMingHu.td - KMH Scheduling Defs -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+// The XiangShan is a high-performance open-source RISC-V processor project
+// initiated by the Institute of Computing Technology(ICT),
+// Chinese Academy of Sciences(CAS).
+// The KunMingHu architecture is its third-generation derivative,
+// developed by the Institute of Computing Technology(ICT),
+// Chinese Academy of Sciences(CAS)
+// and the Beijing Institute of Open Source Chip (BOSC),
+// with a focus on achieving higher performance.
+// Source: https://github.com/OpenXiangShan/XiangShan
+// Documentation: https://docs.xiangshan.cc/projects/design/en/latest/
+// User Guide: https://docs.xiangshan.cc/projects/user-guide/en/latest/
+// Typical Configurations & Instruction Latency:
+// https://docs.xiangshan.cc/projects/user-guide/en/
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topperc wrote:

I agree, we shouldn't break URLs.

https://github.com/llvm/llvm-project/pull/148581