[llvm] [X86] combineShiftRightLogical - fold srl(vecreduce_umax(x),bw-1) as MOVMSK signbit reduction (PR #210281)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 17 02:07:43 PDT 2026
https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/210281
VectorCombine may have folded: icmp_eq(vecreduce_or(splatsign(x)),0) --> icmp_sgt(vecreduce_umax(x),-1) which DAG folds to: srl(vecreduce_umax(x),bw-1).
This match attempts to lower:
srl(vecreduce_umax(x),bw-1) -> icmp_ne(movmsk(x),0) "any_of negative"
srl(not(vecreduce_umax(x)),bw-1) -> icmp_eq(movmsk(x),0) "none_of negative"
The correct fix would be to improve vecreduce_or costs to prevent VectorCombine doing this, but that change is far too big to be merged into 23.x - so I've created the narrow vXi32 backend fix.
Fixes #209714
>From 3150c9afb1ba0c6712751ed47ed5b9a3d0706019 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 17 Jul 2026 09:21:31 +0100
Subject: [PATCH 1/2] [X86] Add test coverage for #209714
---
llvm/test/CodeGen/X86/vector-reduce-umax.ll | 346 ++++++++++++++++++++
1 file changed, 346 insertions(+)
diff --git a/llvm/test/CodeGen/X86/vector-reduce-umax.ll b/llvm/test/CodeGen/X86/vector-reduce-umax.ll
index b45c2914bdccd..a8a0769a16c34 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-umax.ll
@@ -3504,6 +3504,352 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
ret i8 %1
}
+; PR209714
+define i32 @reduce_umax_v4i32_signbit(ptr %pa, ptr %pb) {
+; X86-SSE2-LABEL: reduce_umax_v4i32_signbit:
+; X86-SSE2: # %bb.0:
+; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE2-NEXT: movdqa (%ecx), %xmm0
+; X86-SSE2-NEXT: pand (%eax), %xmm0
+; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
+; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
+; X86-SSE2-NEXT: pxor %xmm1, %xmm2
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; X86-SSE2-NEXT: pxor %xmm3, %xmm1
+; X86-SSE2-NEXT: pcmpgtd %xmm1, %xmm2
+; X86-SSE2-NEXT: pand %xmm2, %xmm0
+; X86-SSE2-NEXT: pandn %xmm3, %xmm2
+; X86-SSE2-NEXT: por %xmm0, %xmm2
+; X86-SSE2-NEXT: movd %xmm2, %ecx
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1]
+; X86-SSE2-NEXT: movd %xmm0, %eax
+; X86-SSE2-NEXT: orl %ecx, %eax
+; X86-SSE2-NEXT: notl %eax
+; X86-SSE2-NEXT: shrl $31, %eax
+; X86-SSE2-NEXT: retl
+;
+; X64-SSE2-LABEL: reduce_umax_v4i32_signbit:
+; X64-SSE2: # %bb.0:
+; X64-SSE2-NEXT: movdqa (%rsi), %xmm0
+; X64-SSE2-NEXT: pand (%rdi), %xmm0
+; X64-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
+; X64-SSE2-NEXT: movdqa %xmm0, %xmm2
+; X64-SSE2-NEXT: pxor %xmm1, %xmm2
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; X64-SSE2-NEXT: pxor %xmm3, %xmm1
+; X64-SSE2-NEXT: pcmpgtd %xmm1, %xmm2
+; X64-SSE2-NEXT: pand %xmm2, %xmm0
+; X64-SSE2-NEXT: pandn %xmm3, %xmm2
+; X64-SSE2-NEXT: por %xmm0, %xmm2
+; X64-SSE2-NEXT: movd %xmm2, %ecx
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1]
+; X64-SSE2-NEXT: movd %xmm0, %eax
+; X64-SSE2-NEXT: orl %ecx, %eax
+; X64-SSE2-NEXT: notl %eax
+; X64-SSE2-NEXT: shrl $31, %eax
+; X64-SSE2-NEXT: retq
+;
+; X86-SSE4-LABEL: reduce_umax_v4i32_signbit:
+; X86-SSE4: # %bb.0:
+; X86-SSE4-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE4-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE4-NEXT: movdqa (%ecx), %xmm0
+; X86-SSE4-NEXT: pand (%eax), %xmm0
+; X86-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-SSE4-NEXT: pmaxud %xmm0, %xmm1
+; X86-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; X86-SSE4-NEXT: por %xmm1, %xmm0
+; X86-SSE4-NEXT: movd %xmm0, %eax
+; X86-SSE4-NEXT: notl %eax
+; X86-SSE4-NEXT: shrl $31, %eax
+; X86-SSE4-NEXT: retl
+;
+; X64-SSE4-LABEL: reduce_umax_v4i32_signbit:
+; X64-SSE4: # %bb.0:
+; X64-SSE4-NEXT: movdqa (%rsi), %xmm0
+; X64-SSE4-NEXT: pand (%rdi), %xmm0
+; X64-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X64-SSE4-NEXT: pmaxud %xmm0, %xmm1
+; X64-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; X64-SSE4-NEXT: por %xmm1, %xmm0
+; X64-SSE4-NEXT: movd %xmm0, %eax
+; X64-SSE4-NEXT: notl %eax
+; X64-SSE4-NEXT: shrl $31, %eax
+; X64-SSE4-NEXT: retq
+;
+; X86-AVX1-LABEL: reduce_umax_v4i32_signbit:
+; X86-AVX1: # %bb.0:
+; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX1-NEXT: vmovdqa (%ecx), %xmm0
+; X86-AVX1-NEXT: vpand (%eax), %xmm0, %xmm0
+; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
+; X86-AVX1-NEXT: vmovd %xmm0, %eax
+; X86-AVX1-NEXT: notl %eax
+; X86-AVX1-NEXT: shrl $31, %eax
+; X86-AVX1-NEXT: retl
+;
+; X64-AVX1-LABEL: reduce_umax_v4i32_signbit:
+; X64-AVX1: # %bb.0:
+; X64-AVX1-NEXT: vmovdqa (%rsi), %xmm0
+; X64-AVX1-NEXT: vpand (%rdi), %xmm0, %xmm0
+; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
+; X64-AVX1-NEXT: vmovd %xmm0, %eax
+; X64-AVX1-NEXT: notl %eax
+; X64-AVX1-NEXT: shrl $31, %eax
+; X64-AVX1-NEXT: retq
+;
+; X86-AVX2-LABEL: reduce_umax_v4i32_signbit:
+; X86-AVX2: # %bb.0:
+; X86-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX2-NEXT: vmovdqa (%ecx), %xmm0
+; X86-AVX2-NEXT: vpand (%eax), %xmm0, %xmm0
+; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
+; X86-AVX2-NEXT: vmovd %xmm0, %eax
+; X86-AVX2-NEXT: notl %eax
+; X86-AVX2-NEXT: shrl $31, %eax
+; X86-AVX2-NEXT: retl
+;
+; X64-AVX2-LABEL: reduce_umax_v4i32_signbit:
+; X64-AVX2: # %bb.0:
+; X64-AVX2-NEXT: vmovdqa (%rsi), %xmm0
+; X64-AVX2-NEXT: vpand (%rdi), %xmm0, %xmm0
+; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
+; X64-AVX2-NEXT: vmovd %xmm0, %eax
+; X64-AVX2-NEXT: notl %eax
+; X64-AVX2-NEXT: shrl $31, %eax
+; X64-AVX2-NEXT: retq
+;
+; AVX512-LABEL: reduce_umax_v4i32_signbit:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmovdqa (%rsi), %xmm0
+; AVX512-NEXT: vpand (%rdi), %xmm0, %xmm0
+; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vmovd %xmm0, %eax
+; AVX512-NEXT: notl %eax
+; AVX512-NEXT: shrl $31, %eax
+; AVX512-NEXT: retq
+ %a = load <4 x i32>, ptr %pa
+ %b = load <4 x i32>, ptr %pb
+ %a.not = xor <4 x i32> %a, splat (i32 -1)
+ %and = and <4 x i32> %b, %a
+ %rdx = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %and)
+ %cmp = icmp sgt i32 %rdx, -1
+ %res = zext i1 %cmp to i32
+ ret i32 %res
+}
+
+
+; PR209714
+define i32 @reduce_umax_v8i32_signbit_not(ptr %pa, ptr %pb) {
+; X86-SSE2-LABEL: reduce_umax_v8i32_signbit_not:
+; X86-SSE2: # %bb.0:
+; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE2-NEXT: movdqa (%ecx), %xmm2
+; X86-SSE2-NEXT: movdqa 16(%ecx), %xmm3
+; X86-SSE2-NEXT: pandn (%eax), %xmm2
+; X86-SSE2-NEXT: pandn 16(%eax), %xmm3
+; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
+; X86-SSE2-NEXT: movdqa %xmm3, %xmm4
+; X86-SSE2-NEXT: pxor %xmm1, %xmm4
+; X86-SSE2-NEXT: movdqa %xmm2, %xmm0
+; X86-SSE2-NEXT: pxor %xmm1, %xmm0
+; X86-SSE2-NEXT: pcmpgtd %xmm4, %xmm0
+; X86-SSE2-NEXT: pand %xmm0, %xmm2
+; X86-SSE2-NEXT: pandn %xmm3, %xmm0
+; X86-SSE2-NEXT: por %xmm2, %xmm0
+; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
+; X86-SSE2-NEXT: pxor %xmm1, %xmm2
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
+; X86-SSE2-NEXT: pxor %xmm3, %xmm1
+; X86-SSE2-NEXT: pcmpgtd %xmm1, %xmm2
+; X86-SSE2-NEXT: pand %xmm2, %xmm0
+; X86-SSE2-NEXT: pandn %xmm3, %xmm2
+; X86-SSE2-NEXT: por %xmm0, %xmm2
+; X86-SSE2-NEXT: movd %xmm2, %ecx
+; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1]
+; X86-SSE2-NEXT: movd %xmm0, %eax
+; X86-SSE2-NEXT: orl %ecx, %eax
+; X86-SSE2-NEXT: notl %eax
+; X86-SSE2-NEXT: shrl $31, %eax
+; X86-SSE2-NEXT: retl
+;
+; X64-SSE2-LABEL: reduce_umax_v8i32_signbit_not:
+; X64-SSE2: # %bb.0:
+; X64-SSE2-NEXT: movdqa (%rdi), %xmm0
+; X64-SSE2-NEXT: movdqa 16(%rdi), %xmm1
+; X64-SSE2-NEXT: pandn (%rsi), %xmm0
+; X64-SSE2-NEXT: pandn 16(%rsi), %xmm1
+; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
+; X64-SSE2-NEXT: movdqa %xmm1, %xmm3
+; X64-SSE2-NEXT: pxor %xmm2, %xmm3
+; X64-SSE2-NEXT: movdqa %xmm0, %xmm4
+; X64-SSE2-NEXT: pxor %xmm2, %xmm4
+; X64-SSE2-NEXT: pcmpgtd %xmm3, %xmm4
+; X64-SSE2-NEXT: pand %xmm4, %xmm0
+; X64-SSE2-NEXT: pandn %xmm1, %xmm4
+; X64-SSE2-NEXT: por %xmm0, %xmm4
+; X64-SSE2-NEXT: movdqa %xmm4, %xmm0
+; X64-SSE2-NEXT: pxor %xmm2, %xmm0
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[2,3,2,3]
+; X64-SSE2-NEXT: pxor %xmm1, %xmm2
+; X64-SSE2-NEXT: pcmpgtd %xmm2, %xmm0
+; X64-SSE2-NEXT: pand %xmm0, %xmm4
+; X64-SSE2-NEXT: pandn %xmm1, %xmm0
+; X64-SSE2-NEXT: por %xmm4, %xmm0
+; X64-SSE2-NEXT: movd %xmm0, %ecx
+; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; X64-SSE2-NEXT: movd %xmm0, %eax
+; X64-SSE2-NEXT: orl %ecx, %eax
+; X64-SSE2-NEXT: notl %eax
+; X64-SSE2-NEXT: shrl $31, %eax
+; X64-SSE2-NEXT: retq
+;
+; X86-SSE4-LABEL: reduce_umax_v8i32_signbit_not:
+; X86-SSE4: # %bb.0:
+; X86-SSE4-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE4-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE4-NEXT: movdqa (%ecx), %xmm0
+; X86-SSE4-NEXT: movdqa 16(%ecx), %xmm1
+; X86-SSE4-NEXT: pandn 16(%eax), %xmm1
+; X86-SSE4-NEXT: pandn (%eax), %xmm0
+; X86-SSE4-NEXT: pmaxud %xmm1, %xmm0
+; X86-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-SSE4-NEXT: pmaxud %xmm0, %xmm1
+; X86-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; X86-SSE4-NEXT: por %xmm1, %xmm0
+; X86-SSE4-NEXT: movd %xmm0, %eax
+; X86-SSE4-NEXT: notl %eax
+; X86-SSE4-NEXT: shrl $31, %eax
+; X86-SSE4-NEXT: retl
+;
+; X64-SSE4-LABEL: reduce_umax_v8i32_signbit_not:
+; X64-SSE4: # %bb.0:
+; X64-SSE4-NEXT: movdqa (%rdi), %xmm0
+; X64-SSE4-NEXT: movdqa 16(%rdi), %xmm1
+; X64-SSE4-NEXT: pandn 16(%rsi), %xmm1
+; X64-SSE4-NEXT: pandn (%rsi), %xmm0
+; X64-SSE4-NEXT: pmaxud %xmm1, %xmm0
+; X64-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X64-SSE4-NEXT: pmaxud %xmm0, %xmm1
+; X64-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
+; X64-SSE4-NEXT: por %xmm1, %xmm0
+; X64-SSE4-NEXT: movd %xmm0, %eax
+; X64-SSE4-NEXT: notl %eax
+; X64-SSE4-NEXT: shrl $31, %eax
+; X64-SSE4-NEXT: retq
+;
+; X86-AVX1-LABEL: reduce_umax_v8i32_signbit_not:
+; X86-AVX1: # %bb.0:
+; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX1-NEXT: vmovaps (%ecx), %ymm0
+; X86-AVX1-NEXT: vandnps (%eax), %ymm0, %ymm0
+; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; X86-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
+; X86-AVX1-NEXT: vmovd %xmm0, %eax
+; X86-AVX1-NEXT: notl %eax
+; X86-AVX1-NEXT: shrl $31, %eax
+; X86-AVX1-NEXT: vzeroupper
+; X86-AVX1-NEXT: retl
+;
+; X64-AVX1-LABEL: reduce_umax_v8i32_signbit_not:
+; X64-AVX1: # %bb.0:
+; X64-AVX1-NEXT: vmovaps (%rdi), %ymm0
+; X64-AVX1-NEXT: vandnps (%rsi), %ymm0, %ymm0
+; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
+; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
+; X64-AVX1-NEXT: vmovd %xmm0, %eax
+; X64-AVX1-NEXT: notl %eax
+; X64-AVX1-NEXT: shrl $31, %eax
+; X64-AVX1-NEXT: vzeroupper
+; X64-AVX1-NEXT: retq
+;
+; X86-AVX2-LABEL: reduce_umax_v8i32_signbit_not:
+; X86-AVX2: # %bb.0:
+; X86-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX2-NEXT: vmovdqa (%ecx), %ymm0
+; X86-AVX2-NEXT: vpandn (%eax), %ymm0, %ymm0
+; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
+; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X86-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
+; X86-AVX2-NEXT: vmovd %xmm0, %eax
+; X86-AVX2-NEXT: notl %eax
+; X86-AVX2-NEXT: shrl $31, %eax
+; X86-AVX2-NEXT: vzeroupper
+; X86-AVX2-NEXT: retl
+;
+; X64-AVX2-LABEL: reduce_umax_v8i32_signbit_not:
+; X64-AVX2: # %bb.0:
+; X64-AVX2-NEXT: vmovdqa (%rdi), %ymm0
+; X64-AVX2-NEXT: vpandn (%rsi), %ymm0, %ymm0
+; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
+; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; X64-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
+; X64-AVX2-NEXT: vmovd %xmm0, %eax
+; X64-AVX2-NEXT: notl %eax
+; X64-AVX2-NEXT: shrl $31, %eax
+; X64-AVX2-NEXT: vzeroupper
+; X64-AVX2-NEXT: retq
+;
+; AVX512-LABEL: reduce_umax_v8i32_signbit_not:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmovdqa (%rdi), %ymm0
+; AVX512-NEXT: vpandn (%rsi), %ymm0, %ymm0
+; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
+; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
+; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
+; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
+; AVX512-NEXT: vmovd %xmm0, %eax
+; AVX512-NEXT: notl %eax
+; AVX512-NEXT: shrl $31, %eax
+; AVX512-NEXT: vzeroupper
+; AVX512-NEXT: retq
+ %a = load <8 x i32>, ptr %pa
+ %b = load <8 x i32>, ptr %pb
+ %a.not = xor <8 x i32> %a, splat (i32 -1)
+ %and = and <8 x i32> %b, %a.not
+ %rdx = call i32 @llvm.vector.reduce.umax.v8i32(<8 x i32> %and)
+ %cmp = icmp sgt i32 %rdx, -1
+ %res = zext i1 %cmp to i32
+ ret i32 %res
+}
+
declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)
declare i64 @llvm.vector.reduce.umax.v4i64(<4 x i64>)
declare i64 @llvm.vector.reduce.umax.v8i64(<8 x i64>)
>From 040d937786246acdbb4959e0d65fd868b3637c47 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Fri, 17 Jul 2026 09:59:03 +0100
Subject: [PATCH 2/2] [X86] combineShiftRightLogical - fold
srl(vecreduce_umax(x),bw-1) as MOVMSK signbit reduction
VectorCombine may have folded: icmp_eq(vecreduce_or(splatsign(x)),0) --> icmp_sgt(vecreduce_umax(x),-1) which DAG folds to: srl(vecreduce_umax(x),bw-1).
This match attempts to lower:
srl(vecreduce_umax(x),bw-1) -> icmp_ne(movmsk(x),z) "any_of negative"
srl(not(vecreduce_umax(x)),bw-1) -> icmp_eq(movmsk(x),z) "none_of negative"
The correct fix would be to improve vecreduce_or costs to prevent VectorCombine doing this, but that change is far too big to be merged into 23.x - so I've created the narrow vXi32 backend fix.
Fixes #209714
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 20 +
llvm/test/CodeGen/X86/vector-reduce-umax.ll | 426 +++++---------------
2 files changed, 124 insertions(+), 322 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 97e783c09f0f2..c2278183fa133 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -50910,6 +50910,26 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG,
}
}
+ // VectorCombine may have folded:
+ // icmp_eq(vecreduce_or(splatsign(x)),0) --> icmp_sgt(vecreduce_umax(x),-1)
+ // which DAG folds to: srl(vecreduce_umax(x),bw-1).
+ // This attempts to reconstruct the signbit reduction.
+ if (sd_match(N1, m_SpecificInt(EltSizeInBits - 1))) {
+ SDValue X = N0;
+ ISD::CondCode CC = ISD::SETNE;
+ if (sd_match(N0, m_Not(m_Value(X))))
+ CC = ISD::SETEQ;
+ if (X.getOpcode() == ISD::VECREDUCE_UMAX) {
+ SDValue V = X.getOperand(0);
+ if (DAG.getTargetLoweringInfo().isTypeLegal(V.getValueType()) &&
+ (V.getValueType() == MVT::v4i32 || V.getValueType() == MVT::v8i32)) {
+ V = DAG.getNode(X86ISD::MOVMSK, DL, MVT::i32, V);
+ V = DAG.getSetCC(DL, MVT::i8, V, DAG.getConstant(0, DL, MVT::i32), CC);
+ return DAG.getZExtOrTrunc(V, DL, VT);
+ }
+ }
+ }
+
// Only do this on the last DAG combine as it can interfere with other
// combines.
if (!DCI.isAfterLegalizeDAG())
diff --git a/llvm/test/CodeGen/X86/vector-reduce-umax.ll b/llvm/test/CodeGen/X86/vector-reduce-umax.ll
index a8a0769a16c34..ca252968b4898 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-umax.ll
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2,X86-SSE2
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2,X64-SSE2
-; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE4,X86-SSE4,X86-SSE41
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE4,X64-SSE4,X64-SSE41
-; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE4,X86-SSE4,X86-SSE42
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE4,X64-SSE4,X64-SSE42
-; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1,X86-AVX1
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1,X64-AVX1
-; RUN: llc < %s -mtriple=i686-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2,X86-AVX2
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2,X64-AVX2
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2,X86-SSE,X86-SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2,X64-SSE,X64-SSE2
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE4,X86-SSE,X86-SSE4,X86-SSE41
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE4,X64-SSE,X64-SSE4,X64-SSE41
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE4,X86-SSE,X86-SSE4,X86-SSE42
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE4,X64-SSE,X64-SSE4,X64-SSE42
+; RUN: llc < %s -mtriple=i686-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1,X86-AVX,X86-AVX1
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1,X64-AVX,X64-AVX1
+; RUN: llc < %s -mtriple=i686-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2,X86-AVX,X86-AVX2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2,X64-AVX,X64-AVX2
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512,AVX512BW
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=AVX,AVX512,AVX512VL
@@ -3506,145 +3506,52 @@ define i8 @test_v128i8(<128 x i8> %a0) nounwind {
; PR209714
define i32 @reduce_umax_v4i32_signbit(ptr %pa, ptr %pb) {
-; X86-SSE2-LABEL: reduce_umax_v4i32_signbit:
-; X86-SSE2: # %bb.0:
-; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-SSE2-NEXT: movdqa (%ecx), %xmm0
-; X86-SSE2-NEXT: pand (%eax), %xmm0
-; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
-; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
-; X86-SSE2-NEXT: pxor %xmm1, %xmm2
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
-; X86-SSE2-NEXT: pxor %xmm3, %xmm1
-; X86-SSE2-NEXT: pcmpgtd %xmm1, %xmm2
-; X86-SSE2-NEXT: pand %xmm2, %xmm0
-; X86-SSE2-NEXT: pandn %xmm3, %xmm2
-; X86-SSE2-NEXT: por %xmm0, %xmm2
-; X86-SSE2-NEXT: movd %xmm2, %ecx
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1]
-; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: orl %ecx, %eax
-; X86-SSE2-NEXT: notl %eax
-; X86-SSE2-NEXT: shrl $31, %eax
-; X86-SSE2-NEXT: retl
-;
-; X64-SSE2-LABEL: reduce_umax_v4i32_signbit:
-; X64-SSE2: # %bb.0:
-; X64-SSE2-NEXT: movdqa (%rsi), %xmm0
-; X64-SSE2-NEXT: pand (%rdi), %xmm0
-; X64-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
-; X64-SSE2-NEXT: movdqa %xmm0, %xmm2
-; X64-SSE2-NEXT: pxor %xmm1, %xmm2
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
-; X64-SSE2-NEXT: pxor %xmm3, %xmm1
-; X64-SSE2-NEXT: pcmpgtd %xmm1, %xmm2
-; X64-SSE2-NEXT: pand %xmm2, %xmm0
-; X64-SSE2-NEXT: pandn %xmm3, %xmm2
-; X64-SSE2-NEXT: por %xmm0, %xmm2
-; X64-SSE2-NEXT: movd %xmm2, %ecx
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1]
-; X64-SSE2-NEXT: movd %xmm0, %eax
-; X64-SSE2-NEXT: orl %ecx, %eax
-; X64-SSE2-NEXT: notl %eax
-; X64-SSE2-NEXT: shrl $31, %eax
-; X64-SSE2-NEXT: retq
-;
-; X86-SSE4-LABEL: reduce_umax_v4i32_signbit:
-; X86-SSE4: # %bb.0:
-; X86-SSE4-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-SSE4-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-SSE4-NEXT: movdqa (%ecx), %xmm0
-; X86-SSE4-NEXT: pand (%eax), %xmm0
-; X86-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-SSE4-NEXT: pmaxud %xmm0, %xmm1
-; X86-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; X86-SSE4-NEXT: por %xmm1, %xmm0
-; X86-SSE4-NEXT: movd %xmm0, %eax
-; X86-SSE4-NEXT: notl %eax
-; X86-SSE4-NEXT: shrl $31, %eax
-; X86-SSE4-NEXT: retl
-;
-; X64-SSE4-LABEL: reduce_umax_v4i32_signbit:
-; X64-SSE4: # %bb.0:
-; X64-SSE4-NEXT: movdqa (%rsi), %xmm0
-; X64-SSE4-NEXT: pand (%rdi), %xmm0
-; X64-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-SSE4-NEXT: pmaxud %xmm0, %xmm1
-; X64-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; X64-SSE4-NEXT: por %xmm1, %xmm0
-; X64-SSE4-NEXT: movd %xmm0, %eax
-; X64-SSE4-NEXT: notl %eax
-; X64-SSE4-NEXT: shrl $31, %eax
-; X64-SSE4-NEXT: retq
-;
-; X86-AVX1-LABEL: reduce_umax_v4i32_signbit:
-; X86-AVX1: # %bb.0:
-; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-AVX1-NEXT: vmovdqa (%ecx), %xmm0
-; X86-AVX1-NEXT: vpand (%eax), %xmm0, %xmm0
-; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X86-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: notl %eax
-; X86-AVX1-NEXT: shrl $31, %eax
-; X86-AVX1-NEXT: retl
-;
-; X64-AVX1-LABEL: reduce_umax_v4i32_signbit:
-; X64-AVX1: # %bb.0:
-; X64-AVX1-NEXT: vmovdqa (%rsi), %xmm0
-; X64-AVX1-NEXT: vpand (%rdi), %xmm0, %xmm0
-; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X64-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: notl %eax
-; X64-AVX1-NEXT: shrl $31, %eax
-; X64-AVX1-NEXT: retq
-;
-; X86-AVX2-LABEL: reduce_umax_v4i32_signbit:
-; X86-AVX2: # %bb.0:
-; X86-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-AVX2-NEXT: vmovdqa (%ecx), %xmm0
-; X86-AVX2-NEXT: vpand (%eax), %xmm0, %xmm0
-; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X86-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vmovd %xmm0, %eax
-; X86-AVX2-NEXT: notl %eax
-; X86-AVX2-NEXT: shrl $31, %eax
-; X86-AVX2-NEXT: retl
-;
-; X64-AVX2-LABEL: reduce_umax_v4i32_signbit:
-; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vmovdqa (%rsi), %xmm0
-; X64-AVX2-NEXT: vpand (%rdi), %xmm0, %xmm0
-; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X64-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vmovd %xmm0, %eax
-; X64-AVX2-NEXT: notl %eax
-; X64-AVX2-NEXT: shrl $31, %eax
-; X64-AVX2-NEXT: retq
+; X86-SSE-LABEL: reduce_umax_v4i32_signbit:
+; X86-SSE: # %bb.0:
+; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE-NEXT: movaps (%ecx), %xmm0
+; X86-SSE-NEXT: andps (%eax), %xmm0
+; X86-SSE-NEXT: movmskps %xmm0, %ecx
+; X86-SSE-NEXT: xorl %eax, %eax
+; X86-SSE-NEXT: testl %ecx, %ecx
+; X86-SSE-NEXT: sete %al
+; X86-SSE-NEXT: retl
+;
+; X64-SSE-LABEL: reduce_umax_v4i32_signbit:
+; X64-SSE: # %bb.0:
+; X64-SSE-NEXT: movaps (%rsi), %xmm0
+; X64-SSE-NEXT: andps (%rdi), %xmm0
+; X64-SSE-NEXT: movmskps %xmm0, %ecx
+; X64-SSE-NEXT: xorl %eax, %eax
+; X64-SSE-NEXT: testl %ecx, %ecx
+; X64-SSE-NEXT: sete %al
+; X64-SSE-NEXT: retq
+;
+; X86-AVX-LABEL: reduce_umax_v4i32_signbit:
+; X86-AVX: # %bb.0:
+; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-AVX-NEXT: vmovaps (%eax), %xmm0
+; X86-AVX-NEXT: xorl %eax, %eax
+; X86-AVX-NEXT: vtestps (%ecx), %xmm0
+; X86-AVX-NEXT: sete %al
+; X86-AVX-NEXT: retl
+;
+; X64-AVX-LABEL: reduce_umax_v4i32_signbit:
+; X64-AVX: # %bb.0:
+; X64-AVX-NEXT: vmovaps (%rdi), %xmm0
+; X64-AVX-NEXT: xorl %eax, %eax
+; X64-AVX-NEXT: vtestps (%rsi), %xmm0
+; X64-AVX-NEXT: sete %al
+; X64-AVX-NEXT: retq
;
; AVX512-LABEL: reduce_umax_v4i32_signbit:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmovdqa (%rsi), %xmm0
-; AVX512-NEXT: vpand (%rdi), %xmm0, %xmm0
-; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vmovd %xmm0, %eax
-; AVX512-NEXT: notl %eax
-; AVX512-NEXT: shrl $31, %eax
+; AVX512-NEXT: vmovaps (%rdi), %xmm0
+; AVX512-NEXT: xorl %eax, %eax
+; AVX512-NEXT: vtestps (%rsi), %xmm0
+; AVX512-NEXT: sete %al
; AVX512-NEXT: retq
%a = load <4 x i32>, ptr %pa
%b = load <4 x i32>, ptr %pb
@@ -3659,185 +3566,60 @@ define i32 @reduce_umax_v4i32_signbit(ptr %pa, ptr %pb) {
; PR209714
define i32 @reduce_umax_v8i32_signbit_not(ptr %pa, ptr %pb) {
-; X86-SSE2-LABEL: reduce_umax_v8i32_signbit_not:
-; X86-SSE2: # %bb.0:
-; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-SSE2-NEXT: movdqa (%ecx), %xmm2
-; X86-SSE2-NEXT: movdqa 16(%ecx), %xmm3
-; X86-SSE2-NEXT: pandn (%eax), %xmm2
-; X86-SSE2-NEXT: pandn 16(%eax), %xmm3
-; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648,2147483648,2147483648]
-; X86-SSE2-NEXT: movdqa %xmm3, %xmm4
-; X86-SSE2-NEXT: pxor %xmm1, %xmm4
-; X86-SSE2-NEXT: movdqa %xmm2, %xmm0
-; X86-SSE2-NEXT: pxor %xmm1, %xmm0
-; X86-SSE2-NEXT: pcmpgtd %xmm4, %xmm0
-; X86-SSE2-NEXT: pand %xmm0, %xmm2
-; X86-SSE2-NEXT: pandn %xmm3, %xmm0
-; X86-SSE2-NEXT: por %xmm2, %xmm0
-; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
-; X86-SSE2-NEXT: pxor %xmm1, %xmm2
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,2,3]
-; X86-SSE2-NEXT: pxor %xmm3, %xmm1
-; X86-SSE2-NEXT: pcmpgtd %xmm1, %xmm2
-; X86-SSE2-NEXT: pand %xmm2, %xmm0
-; X86-SSE2-NEXT: pandn %xmm3, %xmm2
-; X86-SSE2-NEXT: por %xmm0, %xmm2
-; X86-SSE2-NEXT: movd %xmm2, %ecx
-; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,1,1]
-; X86-SSE2-NEXT: movd %xmm0, %eax
-; X86-SSE2-NEXT: orl %ecx, %eax
-; X86-SSE2-NEXT: notl %eax
-; X86-SSE2-NEXT: shrl $31, %eax
-; X86-SSE2-NEXT: retl
-;
-; X64-SSE2-LABEL: reduce_umax_v8i32_signbit_not:
-; X64-SSE2: # %bb.0:
-; X64-SSE2-NEXT: movdqa (%rdi), %xmm0
-; X64-SSE2-NEXT: movdqa 16(%rdi), %xmm1
-; X64-SSE2-NEXT: pandn (%rsi), %xmm0
-; X64-SSE2-NEXT: pandn 16(%rsi), %xmm1
-; X64-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
-; X64-SSE2-NEXT: movdqa %xmm1, %xmm3
-; X64-SSE2-NEXT: pxor %xmm2, %xmm3
-; X64-SSE2-NEXT: movdqa %xmm0, %xmm4
-; X64-SSE2-NEXT: pxor %xmm2, %xmm4
-; X64-SSE2-NEXT: pcmpgtd %xmm3, %xmm4
-; X64-SSE2-NEXT: pand %xmm4, %xmm0
-; X64-SSE2-NEXT: pandn %xmm1, %xmm4
-; X64-SSE2-NEXT: por %xmm0, %xmm4
-; X64-SSE2-NEXT: movdqa %xmm4, %xmm0
-; X64-SSE2-NEXT: pxor %xmm2, %xmm0
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[2,3,2,3]
-; X64-SSE2-NEXT: pxor %xmm1, %xmm2
-; X64-SSE2-NEXT: pcmpgtd %xmm2, %xmm0
-; X64-SSE2-NEXT: pand %xmm0, %xmm4
-; X64-SSE2-NEXT: pandn %xmm1, %xmm0
-; X64-SSE2-NEXT: por %xmm4, %xmm0
-; X64-SSE2-NEXT: movd %xmm0, %ecx
-; X64-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; X64-SSE2-NEXT: movd %xmm0, %eax
-; X64-SSE2-NEXT: orl %ecx, %eax
-; X64-SSE2-NEXT: notl %eax
-; X64-SSE2-NEXT: shrl $31, %eax
-; X64-SSE2-NEXT: retq
-;
-; X86-SSE4-LABEL: reduce_umax_v8i32_signbit_not:
-; X86-SSE4: # %bb.0:
-; X86-SSE4-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-SSE4-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-SSE4-NEXT: movdqa (%ecx), %xmm0
-; X86-SSE4-NEXT: movdqa 16(%ecx), %xmm1
-; X86-SSE4-NEXT: pandn 16(%eax), %xmm1
-; X86-SSE4-NEXT: pandn (%eax), %xmm0
-; X86-SSE4-NEXT: pmaxud %xmm1, %xmm0
-; X86-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-SSE4-NEXT: pmaxud %xmm0, %xmm1
-; X86-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; X86-SSE4-NEXT: por %xmm1, %xmm0
-; X86-SSE4-NEXT: movd %xmm0, %eax
-; X86-SSE4-NEXT: notl %eax
-; X86-SSE4-NEXT: shrl $31, %eax
-; X86-SSE4-NEXT: retl
-;
-; X64-SSE4-LABEL: reduce_umax_v8i32_signbit_not:
-; X64-SSE4: # %bb.0:
-; X64-SSE4-NEXT: movdqa (%rdi), %xmm0
-; X64-SSE4-NEXT: movdqa 16(%rdi), %xmm1
-; X64-SSE4-NEXT: pandn 16(%rsi), %xmm1
-; X64-SSE4-NEXT: pandn (%rsi), %xmm0
-; X64-SSE4-NEXT: pmaxud %xmm1, %xmm0
-; X64-SSE4-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-SSE4-NEXT: pmaxud %xmm0, %xmm1
-; X64-SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,1,1]
-; X64-SSE4-NEXT: por %xmm1, %xmm0
-; X64-SSE4-NEXT: movd %xmm0, %eax
-; X64-SSE4-NEXT: notl %eax
-; X64-SSE4-NEXT: shrl $31, %eax
-; X64-SSE4-NEXT: retq
-;
-; X86-AVX1-LABEL: reduce_umax_v8i32_signbit_not:
-; X86-AVX1: # %bb.0:
-; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-AVX1-NEXT: vmovaps (%ecx), %ymm0
-; X86-AVX1-NEXT: vandnps (%eax), %ymm0, %ymm0
-; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; X86-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X86-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; X86-AVX1-NEXT: vmovd %xmm0, %eax
-; X86-AVX1-NEXT: notl %eax
-; X86-AVX1-NEXT: shrl $31, %eax
-; X86-AVX1-NEXT: vzeroupper
-; X86-AVX1-NEXT: retl
-;
-; X64-AVX1-LABEL: reduce_umax_v8i32_signbit_not:
-; X64-AVX1: # %bb.0:
-; X64-AVX1-NEXT: vmovaps (%rdi), %ymm0
-; X64-AVX1-NEXT: vandnps (%rsi), %ymm0, %ymm0
-; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
-; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X64-AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
-; X64-AVX1-NEXT: vmovd %xmm0, %eax
-; X64-AVX1-NEXT: notl %eax
-; X64-AVX1-NEXT: shrl $31, %eax
-; X64-AVX1-NEXT: vzeroupper
-; X64-AVX1-NEXT: retq
-;
-; X86-AVX2-LABEL: reduce_umax_v8i32_signbit_not:
-; X86-AVX2: # %bb.0:
-; X86-AVX2-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-AVX2-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-AVX2-NEXT: vmovdqa (%ecx), %ymm0
-; X86-AVX2-NEXT: vpandn (%eax), %ymm0, %ymm0
-; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X86-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X86-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; X86-AVX2-NEXT: vmovd %xmm0, %eax
-; X86-AVX2-NEXT: notl %eax
-; X86-AVX2-NEXT: shrl $31, %eax
-; X86-AVX2-NEXT: vzeroupper
-; X86-AVX2-NEXT: retl
-;
-; X64-AVX2-LABEL: reduce_umax_v8i32_signbit_not:
-; X64-AVX2: # %bb.0:
-; X64-AVX2-NEXT: vmovdqa (%rdi), %ymm0
-; X64-AVX2-NEXT: vpandn (%rsi), %ymm0, %ymm0
-; X64-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
-; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; X64-AVX2-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; X64-AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
-; X64-AVX2-NEXT: vmovd %xmm0, %eax
-; X64-AVX2-NEXT: notl %eax
-; X64-AVX2-NEXT: shrl $31, %eax
-; X64-AVX2-NEXT: vzeroupper
-; X64-AVX2-NEXT: retq
+; X86-SSE-LABEL: reduce_umax_v8i32_signbit_not:
+; X86-SSE: # %bb.0:
+; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-SSE-NEXT: movaps (%ecx), %xmm0
+; X86-SSE-NEXT: movaps 16(%ecx), %xmm1
+; X86-SSE-NEXT: andnps 16(%eax), %xmm1
+; X86-SSE-NEXT: andnps (%eax), %xmm0
+; X86-SSE-NEXT: orps %xmm1, %xmm0
+; X86-SSE-NEXT: movmskps %xmm0, %ecx
+; X86-SSE-NEXT: xorl %eax, %eax
+; X86-SSE-NEXT: testl %ecx, %ecx
+; X86-SSE-NEXT: sete %al
+; X86-SSE-NEXT: retl
+;
+; X64-SSE-LABEL: reduce_umax_v8i32_signbit_not:
+; X64-SSE: # %bb.0:
+; X64-SSE-NEXT: movaps (%rdi), %xmm0
+; X64-SSE-NEXT: movaps 16(%rdi), %xmm1
+; X64-SSE-NEXT: andnps 16(%rsi), %xmm1
+; X64-SSE-NEXT: andnps (%rsi), %xmm0
+; X64-SSE-NEXT: orps %xmm1, %xmm0
+; X64-SSE-NEXT: movmskps %xmm0, %ecx
+; X64-SSE-NEXT: xorl %eax, %eax
+; X64-SSE-NEXT: testl %ecx, %ecx
+; X64-SSE-NEXT: sete %al
+; X64-SSE-NEXT: retq
+;
+; X86-AVX-LABEL: reduce_umax_v8i32_signbit_not:
+; X86-AVX: # %bb.0:
+; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-AVX-NEXT: vmovaps (%eax), %ymm0
+; X86-AVX-NEXT: xorl %eax, %eax
+; X86-AVX-NEXT: vtestps (%ecx), %ymm0
+; X86-AVX-NEXT: setb %al
+; X86-AVX-NEXT: vzeroupper
+; X86-AVX-NEXT: retl
+;
+; X64-AVX-LABEL: reduce_umax_v8i32_signbit_not:
+; X64-AVX: # %bb.0:
+; X64-AVX-NEXT: vmovaps (%rdi), %ymm0
+; X64-AVX-NEXT: xorl %eax, %eax
+; X64-AVX-NEXT: vtestps (%rsi), %ymm0
+; X64-AVX-NEXT: setb %al
+; X64-AVX-NEXT: vzeroupper
+; X64-AVX-NEXT: retq
;
; AVX512-LABEL: reduce_umax_v8i32_signbit_not:
; AVX512: # %bb.0:
-; AVX512-NEXT: vmovdqa (%rdi), %ymm0
-; AVX512-NEXT: vpandn (%rsi), %ymm0, %ymm0
-; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
-; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
-; AVX512-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
-; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0
-; AVX512-NEXT: vmovd %xmm0, %eax
-; AVX512-NEXT: notl %eax
-; AVX512-NEXT: shrl $31, %eax
+; AVX512-NEXT: vmovaps (%rdi), %ymm0
+; AVX512-NEXT: xorl %eax, %eax
+; AVX512-NEXT: vtestps (%rsi), %ymm0
+; AVX512-NEXT: setb %al
; AVX512-NEXT: vzeroupper
; AVX512-NEXT: retq
%a = load <8 x i32>, ptr %pa
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