[llvm] [AArch64] SME definitions for C1-Nano scheduling model (PR #207174)

[via llvm-commits]

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@@ -1562,79 +1851,94 @@ def : InstRW<[C1NanoWrite_8c_2VALU_4rc], (instregex "^N?MATCH_PPzZZ_[BH]")>;
 def : InstRW<[C1NanoWrite_4c_1VMAC], (instrs SMMLA_ZZZ, UMMLA_ZZZ, USMMLA_ZZZ)>;
 
 // Move prefix
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEPERM,
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walkerkd wrote:

Fixed

https://github.com/llvm/llvm-project/pull/207174