[llvm] [AArch64] SME definitions for C1-Nano scheduling model (PR #207174)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 16 05:39:52 PDT 2026
================
@@ -1382,176 +1629,218 @@ def : InstRW<[C1NanoWrite_68c_1VMC_66rc],
// Bitwise select
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_3c_1VALU>],
(instregex "^(BSL|BSL1N|BSL2N|NBSL)_ZZZZ")>;
// Count/reverse bits
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_3c_1VALU>],
(instregex "^(CLS|CLZ|RBIT)_ZPmZ_[BHSD]")>;
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_3c_1VALU>],
(instregex "^CNT_ZPmZ_[BH]")>;
-def : InstRW<[C1NanoWrite_6c_2VALU_4rc],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_6c_2VALU_4rc>],
(instregex "^CNT_ZPmZ_S")>;
-def : InstRW<[C1NanoWrite_9c_2VALU_7rc],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_9c_2VALU_7rc>],
(instregex "^CNT_ZPmZ_D")>;
// Broadcast logical bitmask immediate to vector.
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VALU>],
(instrs DUPM_ZI)>;
// Compare and set flags
-def : InstRW<[C1NanoWrite_5c_2VALU_1rc],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVX0ALU,
+ C1NanoWrite_5c_2VALU_1rc>],
(instregex "^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_PPzZ[IZ]_[BHSD]",
"^CMP(EQ|GE|GT|HI|HS|LE|LO|LS|LT|NE)_WIDE_PPzZZ_[BHS]")>;
// Complex add
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_3c_1VALU>],
(instregex "^CADD_ZZI_[BHSD]")>;
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VALU>],
(instregex "^SQCADD_ZZI_[BHSD]")>;
// Complex dot product 8-bit element
-def : InstRW<[C1NanoWrite_4c_1VMAC],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VMAC>],
(instrs CDOT_ZZZ_S, CDOT_ZZZI_S)>;
// Complex dot product 16-bit element
-def : InstRW<[C1NanoWrite_4c_1VMAC],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VMAC>],
(instrs CDOT_ZZZ_D, CDOT_ZZZI_D)>;
// Complex multiply-add B, H, S element size
-def : InstRW<[C1NanoWrite_4c_1VMAC],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VMAC>],
(instregex "^CMLA_ZZZ_[BHS]", "^CMLA_ZZZI_[HS]")>;
// Complex multiply-add D element size
-def : InstRW<[C1NanoWrite_4c_1VMAC],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VMAC>],
(instrs CMLA_ZZZ_D)>;
// Conditional extract operations, scalar form
-def : InstRW<[C1NanoWrite_4c_2VALU_4rc],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_12c_1CMEPERMF_1CMEVX0ALU_2rc,
+ C1NanoWrite_4c_2VALU_4rc>],
(instregex "^CLAST[AB]_RPZ_[BHSD]")>;
// Conditional extract operations, SIMD&FP scalar and vector forms
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEPERMF_1rc,
+ C1NanoWrite_4c_1VALU>],
(instregex "^CLAST[AB]_[VZ]PZ_[BHSD]",
"^COMPACT_ZPZ_[SD]",
"^SPLICE_ZPZZ?_[BHSD]")>;
// Convert to floating point, 64b to float or convert to double
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VALU>],
(instregex "^[SU]CVTF_ZPmZ_Dto[SD]")>;
// Convert to floating point, 64b to half
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VALU>],
(instregex "^[SU]CVTF_ZPmZ_DtoH")>;
// Convert to floating point, 32b to single or half
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VALU>],
(instregex "^[SU]CVTF_ZPmZ_Sto[HS]")>;
// Convert to floating point, 32b to double
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VALU>],
(instregex "^[SU]CVTF_ZPmZ_StoD")>;
// Convert to floating point, 16b to half
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VALU>],
(instregex "^[SU]CVTF_ZPmZ_HtoH")>;
// Copy, scalar
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_8c_1CMEPERMF_1CMEPERMS_1rc,
+ C1NanoWrite_3c_1VALU>],
(instregex "^CPY_ZPmR_[BHSD]")>;
// Copy, scalar SIMD&FP or imm
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_8c_1CMEPERMF_1CMEPERMS_1rc,
+ C1NanoWrite_3c_1VALU>],
(instregex "^CPY_ZPm[IV]_[BHSD]", "^CPY_ZPzI_[BHSD]")>;
// Divides, 32 bit
-def : InstRW<[C1NanoWrite_15c_1VMC_12rc],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_15c_1VMC_12rc>],
(instregex "^[SU]DIVR?_(ZPmZ|ZPZZ)_S")>;
// Divides, 64 bit
-def : InstRW<[C1NanoWrite_26c_1VMC_23rc],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_12c_1CMEMC_12rc,
+ C1NanoWrite_26c_1VMC_23rc>],
(instregex "^[SU]DIVR?_(ZPmZ|ZPZZ)_D")>;
// Dot product, 8 bit
-def : InstRW<[C1NanoWrite_4c_1VMAC, ReadVMACAccum],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXMUL,
+ C1NanoWrite_4c_1VMAC>, ReadVMACAccum],
(instregex "^[SU]DOT_ZZZI?_BtoS")>;
// Dot product, 8 bit, using signed and unsigned integers
-def : InstRW<[C1NanoWrite_4c_1VMAC, ReadVMACAccum],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXMUL,
+ C1NanoWrite_4c_1VMAC>, ReadVMACAccum],
(instrs SUDOT_ZZZI, USDOT_ZZZI, USDOT_ZZZ)>;
// Dot product, 16 bit
-def : InstRW<[C1NanoWrite_4c_1VMAC, ReadVMACAccum],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXMUL,
+ C1NanoWrite_4c_1VMAC>, ReadVMACAccum],
(instregex "^[SU]DOT_ZZZI?_HtoD")>;
// Duplicate, immediate and indexed form
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEPERM,
+ C1NanoWrite_3c_1VALU>],
(instregex "^DUP_ZI_[BHSD]", "^DUP_ZZI_[BHSDQ]")>;
// Duplicate, scalar form
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEPERMF,
+ C1NanoWrite_3c_1VALU>],
(instregex "^DUP_ZR_[BHSD]")>;
// Extend, sign or zero
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_3c_1VALU>],
(instregex "^[SU]XTB_ZPmZ_[HSD]",
"^[SU]XTH_ZPmZ_[SD]",
"^[SU]XTW_ZPmZ_[D]")>;
// Extract
-def : InstRW<[C1NanoWrite_3c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEPERM,
+ C1NanoWrite_3c_1VALU>],
(instrs EXT_ZZI, EXT_ZZI_CONSTRUCTIVE, EXT_ZZI_B)>;
// Extract narrow saturating
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_4c_1VALU>],
(instregex "^[SU]QXTN[BT]_ZZ_[BHS]", "^SQXTUN[BT]_ZZ_[BHS]")>;
// Extract/insert operation, SIMD and FP scalar form
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEPERMF_1rc,
+ C1NanoWrite_4c_1VALU>],
(instregex "^LAST[AB]_VPZ_[BHSD]", "^INSR_ZV_[BHSD]")>;
// Extract operation, scalar
-def : InstRW<[C1NanoWrite_8c_2VALU_4rc],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_4c_1CMEVXALU,
+ C1NanoWrite_8c_2VALU_4rc>],
(instregex "^LAST[AB]_RPZ_[BHSD]")>;
// Insert operation, scalar
-def : InstRW<[C1NanoWrite_4c_1VALU],
+def : InstRW<[C1NanoStreamingSchedWrite<C1NanoWrite_8c_1CMEPERMF_1CMEVXALU_1rc,
----------------
walkerkd wrote:
Fixed
https://github.com/llvm/llvm-project/pull/207174
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