[llvm] [AMDGPU][CodeGen] Place `S_NOP` after `S_SETREG_IMM32_B32` in predecessor MBB (PR #209620)

[Lucas Ramirez via llvm-commits]

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@@ -432,23 +433,58 @@ AMDGPULowerVGPREncoding::handleCoissue(MachineBasicBlock::instr_iterator I) {
   return I;
 }
 
+/// Returns whether \p MI is a S_SETREG_IMM32_B32(MODE).
+static bool isSetregMode(const MachineInstr &MI, const SIInstrInfo &TII) {
+  if (MI.getOpcode() != AMDGPU::S_SETREG_IMM32_B32)
+    return false;
+
+  const MachineOperand *SIMM16Op =
+      TII.getNamedOperand(MI, AMDGPU::OpName::simm16);
+  auto [HwRegId, _Offset, _Size] =
+      AMDGPU::Hwreg::HwregEncoding::decode(SIMM16Op->getImm());
+  return HwRegId == AMDGPU::Hwreg::ID_MODE;
+}
+
 bool AMDGPULowerVGPREncoding::needNopBeforeSetVGPRMSB(
     MachineBasicBlock::instr_iterator I) {
   while (I != MBB->begin()) {
     I = std::prev(I);
-    if (I->getOpcode() == AMDGPU::S_SETREG_IMM32_B32) {
-      MachineOperand *SIMM16Op =
-          TII->getNamedOperand(*I, AMDGPU::OpName::simm16);
-      auto [HwRegId, Offset, Size] =
-          AMDGPU::Hwreg::HwregEncoding::decode(SIMM16Op->getImm());
-      if (HwRegId == AMDGPU::Hwreg::ID_MODE)
-        return true;
-    }
+    if (isSetregMode(*I, *TII))
+      return true;
     if (!I->isMetaInstruction())
       return false;
   }
-  // FIXME: Return true if the previous MBB falls through and ends with
-  // S_SETREG_IMM32_B32.
+
+  // Look for a potential fallthrough predecessor block. When it ends with a
+  // S_SETREG_IMM32_B32(MODE) we need to insert a S_NOP too.
+  MachineBasicBlock *CurrentMBB = MBB;
+  bool HasEmptyFallThroughPred;
+  do {
+    HasEmptyFallThroughPred = false;
+    for (MachineBasicBlock *PredMBB : CurrentMBB->predecessors()) {
----------------
lucas-rami wrote:

It is indeed easier, thanks.

https://github.com/llvm/llvm-project/pull/209620