[llvm] [AMDGPU] Add OMOD folding for TRANS bfloat16 instructions (PR #208595)

[Jay Foad via llvm-commits]

================
@@ -2363,6 +2363,60 @@ SIFoldOperandsImpl::isOMod(const MachineInstr &MI) const {
 
     return std::pair(nullptr, SIOutMods::NONE);
   }
+  case AMDGPU::V_FMA_MIXLO_BF16:
+  case AMDGPU::V_FMA_MIX_BF16_t16: {
+    if (MFI->getMode().FP32Denormals.Output != DenormalMode::PreserveSign ||
+        MI.mayRaiseFPException())
+      return {nullptr, SIOutMods::NONE};
+
+    const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
+    const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
+    const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
+
+    if (!Src2->isImm() || Src2->getImm() != 0)
+      return {nullptr, SIOutMods::NONE};
+
+    // op_sel bits are in src*_modifiers but don't affect folding
----------------
jayfoad wrote:

Why do they not affect the folding? When you look through REG_SEQUENCE you look through to the first (presumably lo16) operand, but what if op_sel here selected the hi16 part?

https://github.com/llvm/llvm-project/pull/208595