[llvm] [AMDGPU] Add OMOD folding for TRANS bfloat16 instructions (PR #208595)

[Jay Foad via llvm-commits]

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@@ -2379,6 +2433,25 @@ bool SIFoldOperandsImpl::tryFoldOMod(MachineInstr &MI) {
     return false;
 
   MachineInstr *Def = MRI->getVRegDef(RegOp->getReg());
+
+  // Look through REG_SEQUENCE to find the actual instruction.
+  // For BF16 operations, the result is often packed via REG_SEQUENCE with
+  // lo16 subreg for the actual value.
+  if (Def->isRegSequence()) {
+    if (Def->getNumOperands() < 2 || !Def->getOperand(1).isReg())
+      return false;
+
+    Register SrcReg = Def->getOperand(1).getReg();
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jayfoad wrote:

Does not seem safe to assume that the first operand is for lo16 without checking. I think the operands for REG_SEQUENCE could go in any order?

https://github.com/llvm/llvm-project/pull/208595