[llvm] [VPlan] Expand SCEV ptrtoint/ptrtoaddr casts in VPSCEVExpander. (PR #209172)
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 14 04:55:49 PDT 2026
https://github.com/fhahn updated https://github.com/llvm/llvm-project/pull/209172
>From a30fc5fa924d5e594d5d391d536d35a957071e1d Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Fri, 3 Jul 2026 10:24:58 +0100
Subject: [PATCH] [VPlan] Expand SCEV ptrtoint/ptrtoaddr casts in
VPSCEVExpander.
Extend the cast handling in VPSCEVExpander::tryToExpand to also expand
scPtrToInt and scPtrToAddr SCEV expressions to PtrToInt/PtrToAddr
VPInstructions.
This allows pointer-distance expressions (e.g. the runtime-check
difference between two pointers, which contains ptrtoint of each
pointer) to be expanded directly to VPInstructions instead of falling
back to a VPExpandSCEVRecipe.
---
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp | 10 ++-
.../AArch64/aggressive-interleaving.ll | 8 +--
.../AArch64/alias-mask-uniforms.ll | 6 +-
.../LoopVectorize/AArch64/alias-mask.ll | 10 +--
.../LoopVectorize/AArch64/induction-costs.ll | 16 ++---
.../AArch64/partial-reduce-constant-ops.ll | 42 +++++------
.../partial-reduce-incomplete-chains.ll | 6 +-
.../LoopVectorize/AArch64/reduction-cost.ll | 10 +--
.../replicating-load-store-costs-apple.ll | 13 ++--
.../AArch64/replicating-load-store-costs.ll | 13 ++--
.../AArch64/sve-live-out-pointer-induction.ll | 12 ++--
...-interleave-to-widen-memory-derived-ivs.ll | 18 ++---
.../LoopVectorize/PowerPC/pr41179.ll | 16 ++---
.../LoopVectorize/RISCV/pointer-induction.ll | 16 ++---
.../AArch64/vplan-printing-alias-mask.ll | 30 ++++----
.../LoopVectorize/VPlan/expand-scev.ll | 9 ++-
.../VPlan/vplan-predicate-switch.ll | 59 ++++++++-------
.../VPlan/vplan-printing-alias-mask.ll | 44 ++++++------
.../WebAssembly/induction-branch-cost.ll | 2 +-
.../LoopVectorize/X86/cost-model.ll | 2 +-
.../X86/fold-tail-low-trip-count.ll | 12 ++--
.../X86/interleave-opaque-pointers.ll | 12 ++--
.../Transforms/LoopVectorize/X86/optsize.ll | 12 ++--
.../Transforms/LoopVectorize/X86/pr48340.ll | 24 +++----
.../Transforms/LoopVectorize/X86/pr72969.ll | 9 +--
.../LoopVectorize/X86/predicate-switch.ll | 72 +++++++++----------
.../alias-mask-data-tail-folding-style.ll | 2 +-
.../LoopVectorize/alias-mask-needs-freeze.ll | 9 ++-
.../LoopVectorize/alias-mask-small-index.ll | 2 +-
.../Transforms/LoopVectorize/alias-mask.ll | 20 +++---
...nd-sink-mem-ops-with-invariant-pointers.ll | 14 ++--
...aved-accesses-different-insert-position.ll | 2 +-
.../interleaved-accesses-metadata.ll | 16 ++---
.../test/Transforms/LoopVectorize/metadata.ll | 16 ++---
.../Transforms/LoopVectorize/opaque-ptr.ll | 36 +++++-----
.../LoopVectorize/pointer-induction.ll | 16 ++---
llvm/test/Transforms/LoopVectorize/pr45259.ll | 9 +--
.../LoopVectorize/predicate-switch.ll | 4 +-
.../preserve-dbg-loc-and-loop-metadata.ll | 22 +++---
.../LoopVectorize/runtime-check-known-true.ll | 5 +-
.../runtime-check-needed-but-empty.ll | 2 +-
.../LoopVectorize/scev-predicate-reasoning.ll | 12 ++--
42 files changed, 340 insertions(+), 330 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index 7b4ffce87434c..03e1ead89c169 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -821,7 +821,9 @@ VPValue *VPSCEVExpander::tryToExpand(const SCEV *S) {
}
case scTruncate:
case scZeroExtend:
- case scSignExtend: {
+ case scSignExtend:
+ case scPtrToInt:
+ case scPtrToAddr: {
auto *Cast = cast<SCEVCastExpr>(S);
VPValue *Op = tryToExpand(Cast->getOperand());
if (!Op)
@@ -837,6 +839,12 @@ VPValue *VPSCEVExpander::tryToExpand(const SCEV *S) {
case scSignExtend:
Opcode = Instruction::SExt;
break;
+ case scPtrToInt:
+ Opcode = Instruction::PtrToInt;
+ break;
+ case scPtrToAddr:
+ Opcode = Instruction::PtrToAddr;
+ break;
default:
llvm_unreachable("Unhandled cast SCEV");
}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll b/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
index 3eaf4c4b1b3f4..a9a91519e7d32 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
@@ -17,16 +17,16 @@ define void @test_interleave_reduction(ptr %arg, ptr %arg1) {
; A320: [[OUTER]]:
; A320-NEXT: [[TPM26:%.*]] = add i64 0, 1
; A320-NEXT: [[TPM10:%.*]] = alloca i32, align 8
-; A320-NEXT: [[TPM102:%.*]] = ptrtoint ptr [[TPM10]] to i64
; A320-NEXT: [[TPM27:%.*]] = getelementptr inbounds i32, ptr [[TPM10]], i64 [[TPM26]]
; A320-NEXT: [[TPM28:%.*]] = getelementptr inbounds ptr, ptr [[TPM15]], i64 0
; A320-NEXT: [[TPM29:%.*]] = load ptr, ptr [[TPM28]], align 8
-; A320-NEXT: [[TPM291:%.*]] = ptrtoint ptr [[TPM29]] to i64
; A320-NEXT: [[TPM17:%.*]] = alloca double, align 8
; A320-NEXT: [[TPM32:%.*]] = getelementptr inbounds double, ptr [[TPM17]], i64 [[TPM26]]
-; A320-NEXT: [[TMP0:%.*]] = add i64 [[TPM291]], -8
+; A320-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[TPM29]] to i64
+; A320-NEXT: [[TPM102:%.*]] = ptrtoint ptr [[TPM10]] to i64
; A320-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[TPM102]]
-; A320-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 2
+; A320-NEXT: [[TMP6:%.*]] = add i64 [[TMP1]], -8
+; A320-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP6]], 2
; A320-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; A320-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
; A320-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll b/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
index a311167615532..d3539eaa9e380 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
@@ -7,8 +7,8 @@ define void @vf_dependent_uniform(ptr noalias %p, ptr %p.out, ptr %p.in, i64 %n)
; CHECK-LABEL: define void @vf_dependent_uniform(
; CHECK-SAME: ptr noalias [[P:%.*]], ptr [[P_OUT:%.*]], ptr [[P_IN:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[P_OUT1:%.*]] = ptrtoaddr ptr [[P_OUT]] to i64
+; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 1)
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
@@ -114,8 +114,8 @@ define void @uniform_load(ptr noalias %p, ptr %p.out, ptr %p.in, i64 %n) {
; CHECK-LABEL: define void @uniform_load(
; CHECK-SAME: ptr noalias [[P:%.*]], ptr [[P_OUT:%.*]], ptr [[P_IN:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[P_OUT1:%.*]] = ptrtoaddr ptr [[P_OUT]] to i64
+; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 1)
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
@@ -181,8 +181,8 @@ define void @uniform_store(ptr noalias %p, ptr %p.out, ptr %p.in, i64 %n) {
; CHECK-LABEL: define void @uniform_store(
; CHECK-SAME: ptr noalias [[P:%.*]], ptr [[P_OUT:%.*]], ptr [[P_IN:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[P_OUT1:%.*]] = ptrtoaddr ptr [[P_OUT]] to i64
+; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 1)
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll b/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
index 15a9e8d5aa4c0..87bdd1f975423 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
@@ -5,8 +5,8 @@ define void @alias_mask(ptr noalias %a, ptr %b, ptr %c, i64 %n) {
; CHECK-TF-LABEL: define void @alias_mask(
; CHECK-TF-SAME: ptr noalias [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-TF-NEXT: [[ENTRY:.*:]]
-; CHECK-TF-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-TF-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
+; CHECK-TF-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-TF-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK-TF: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-TF-NEXT: [[ALIAS_MASK:%.*]] = call <vscale x 16 x i1> @llvm.loop.dependence.war.mask.nxv16i1.i64(i64 [[B2]], i64 [[C1]], i64 1)
@@ -65,9 +65,9 @@ define void @alias_mask_multiple(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-TF-LABEL: define void @alias_mask_multiple(
; CHECK-TF-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
; CHECK-TF-NEXT: [[ENTRY:.*:]]
-; CHECK-TF-NEXT: [[A3:%.*]] = ptrtoaddr ptr [[A]] to i64
-; CHECK-TF-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-TF-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
+; CHECK-TF-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-TF-NEXT: [[A3:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-TF-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK-TF: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-TF-NEXT: [[TMP2:%.*]] = call <vscale x 16 x i1> @llvm.loop.dependence.war.mask.nxv16i1.i64(i64 [[A3]], i64 [[C1]], i64 1)
@@ -130,8 +130,8 @@ define i8 @alias_masking_exit_value(ptr %ptrA, ptr %ptrB) {
; CHECK-TF-LABEL: define i8 @alias_masking_exit_value(
; CHECK-TF-SAME: ptr [[PTRA:%.*]], ptr [[PTRB:%.*]]) #[[ATTR0]] {
; CHECK-TF-NEXT: [[ENTRY:.*:]]
-; CHECK-TF-NEXT: [[PTRA2:%.*]] = ptrtoaddr ptr [[PTRA]] to i64
; CHECK-TF-NEXT: [[PTRB1:%.*]] = ptrtoaddr ptr [[PTRB]] to i64
+; CHECK-TF-NEXT: [[PTRA2:%.*]] = ptrtoaddr ptr [[PTRA]] to i64
; CHECK-TF-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK-TF: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-TF-NEXT: [[ALIAS_MASK:%.*]] = call <vscale x 16 x i1> @llvm.loop.dependence.war.mask.nxv16i1.i64(i64 [[PTRA2]], i64 [[PTRB1]], i64 1)
@@ -197,8 +197,8 @@ define i32 @partial_reduce(ptr %a, ptr %b, i64 %n) {
; CHECK-TF-LABEL: define i32 @partial_reduce(
; CHECK-TF-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
; CHECK-TF-NEXT: [[ENTRY:.*:]]
-; CHECK-TF-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-TF-NEXT: [[B1:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-TF-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-TF-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK-TF: [[VECTOR_PH]]:
; CHECK-TF-NEXT: [[ALIAS_MASK:%.*]] = call <vscale x 16 x i1> @llvm.loop.dependence.war.mask.nxv16i1.i64(i64 [[A2]], i64 [[B1]], i64 1)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
index b49e1aa5b4e46..5e68b6d6c748e 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
@@ -99,8 +99,8 @@ define i64 @pointer_induction_only(ptr %start, ptr %end) {
; CHECK-LABEL: define i64 @pointer_induction_only(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
+; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2
; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
@@ -435,16 +435,16 @@ define i32 @load_from_pointer_induction(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @load_from_pointer_induction(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[END1]], i64 [[START2]])
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], 1
+; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.umax.i64(i64 [[END1]], i64 [[START2]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
+; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP1]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP20]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]]
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP20]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP20]], [[N_MOD_VF]]
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
@@ -479,7 +479,7 @@ define i32 @load_from_pointer_induction(ptr %start, ptr %end) {
; CHECK-NEXT: [[BIN_RDX:%.*]] = or i32 [[TMP9]], [[TMP8]]
; CHECK-NEXT: [[BIN_RDX9:%.*]] = or i32 [[TMP16]], [[BIN_RDX]]
; CHECK-NEXT: [[BIN_RDX10:%.*]] = or i32 [[TMP17]], [[BIN_RDX9]]
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]]
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP20]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
index ba00cb0c543fd..94f98343421bc 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
@@ -7,10 +7,10 @@ define i32 @red_zext_mul_by_63(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_zext_mul_by_63(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP7]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -73,10 +73,10 @@ define i32 @red_zext_mul_by_255(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_zext_mul_by_255(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP5]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -139,10 +139,10 @@ define i32 @red_zext_mul_by_256(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_zext_mul_by_256(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -205,10 +205,10 @@ define i32 @red_sext_mul_by_63(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_sext_mul_by_63(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP7]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -273,10 +273,10 @@ define i32 @red_sext_mul_by_128(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_sext_mul_by_128(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -340,10 +340,10 @@ define i32 @red_sext_mul_by_255(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_sext_mul_by_255(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -406,10 +406,10 @@ define i32 @red_sext_mul_by_256(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_sext_mul_by_256(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
index 9e4b3b5a921e5..00e9fb2f7dc43 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
@@ -7,10 +7,10 @@ define i32 @red_extended_add_incomplete_chain(ptr %start, ptr %end, i32 %offset)
; CHECK-LABEL: define i32 @red_extended_add_incomplete_chain(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
index 0065ecdec0112..230a9d7325bc5 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
@@ -112,22 +112,22 @@ define i32 @or_reduction_with_freeze(ptr %dst, ptr %src) {
; CHECK-NEXT: [[DST6:%.*]] = ptrtoint ptr [[DST]] to i64
; CHECK-NEXT: [[SRC4:%.*]] = ptrtoint ptr [[SRC]] to i64
; CHECK-NEXT: [[DST3:%.*]] = ptrtoint ptr [[DST]] to i64
-; CHECK-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64
; CHECK-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[DST6]], [[SRC7]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[SRC]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[DST1]], [[TMP11]]
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 10
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[DST1]] to i3
-; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[SRC2]] to i3
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[DST3]] to i3
+; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[SRC4]] to i3
; CHECK-NEXT: [[TMP5:%.*]] = sub i3 [[TMP3]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = zext i3 [[TMP5]] to i64
; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[TMP6]], 0
; CHECK-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
-; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[DST3]], [[SRC4]]
+; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[DST6]], [[SRC7]]
; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP7]], 3
; CHECK-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 8
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll b/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
index 5d754fea2b84d..e46509a4e1c6e 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll
@@ -451,16 +451,17 @@ define void @test_prefer_vector_addressing(ptr %start, ptr %ms, ptr noalias %src
; CHECK-LABEL: define void @test_prefer_vector_addressing(
; CHECK-SAME: ptr [[START:%.*]], ptr [[MS:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
-; CHECK-NEXT: [[MS1:%.*]] = ptrtoint ptr [[MS]] to i64
; CHECK-NEXT: [[GEP_START:%.*]] = getelementptr i8, ptr [[START]], i64 3
+; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[MS]] to i64
+; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[START2]], 3
-; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[MS1]], i64 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[UMAX]], -3
+; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP10]], i64 [[TMP0]])
; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[START2]]
-; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 1)
+; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP2]], -3
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP23]], i64 1)
; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP2]], [[UMIN]]
-; CHECK-NEXT: [[TMP4:%.*]] = udiv i64 [[TMP3]], 3
+; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP3]], -3
+; CHECK-NEXT: [[TMP4:%.*]] = udiv i64 [[TMP24]], 3
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[UMIN]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP5]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP6]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
index ed550598cb872..3c4833012a04c 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll
@@ -447,16 +447,17 @@ define void @test_prefer_vector_addressing(ptr %start, ptr %ms, ptr noalias %src
; CHECK-LABEL: define void @test_prefer_vector_addressing(
; CHECK-SAME: ptr [[START:%.*]], ptr [[MS:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
-; CHECK-NEXT: [[MS1:%.*]] = ptrtoint ptr [[MS]] to i64
; CHECK-NEXT: [[GEP_START:%.*]] = getelementptr i8, ptr [[START]], i64 3
+; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[MS]] to i64
+; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[START2]], 3
-; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[MS1]], i64 [[TMP0]])
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[UMAX]], -3
+; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP10]], i64 [[TMP0]])
; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[START2]]
-; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 1)
+; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP2]], -3
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP23]], i64 1)
; CHECK-NEXT: [[TMP3:%.*]] = sub i64 [[TMP2]], [[UMIN]]
-; CHECK-NEXT: [[TMP4:%.*]] = udiv i64 [[TMP3]], 3
+; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[TMP3]], -3
+; CHECK-NEXT: [[TMP4:%.*]] = udiv i64 [[TMP24]], 3
; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[UMIN]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP5]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP6]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
index 0ae1da776eff3..82c07cd0e5861 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll
@@ -6,8 +6,8 @@ define ptr @test(ptr %start.1, ptr %start.2, ptr %end) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[START_22:%.*]] = ptrtoint ptr [[START_2:%.*]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END:%.*]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START_22]]
+; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[START_22]], [[END1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP6]], -8
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
@@ -21,12 +21,12 @@ define ptr @test(ptr %start.1, ptr %start.2, ptr %end) {
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[N_VEC]], 3
; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START_1:%.*]], i64 [[TMP8]]
-; CHECK-NEXT: [[IND_END3:%.*]] = getelementptr i8, ptr [[START_2]], i64 [[TMP8]]
+; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[END]], i64 [[TMP8]]
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 3
-; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[START_2]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[END]], i64 [[OFFSET_IDX]]
; CHECK-NEXT: [[TMP35:%.*]] = getelementptr i64, ptr [[TMP30]], i64 [[TMP10]]
; CHECK-NEXT: store <vscale x 2 x i64> zeroinitializer, ptr [[TMP30]], align 8
; CHECK-NEXT: store <vscale x 2 x i64> zeroinitializer, ptr [[TMP35]], align 8
@@ -39,7 +39,7 @@ define ptr @test(ptr %start.1, ptr %start.2, ptr %end) {
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[START_1]], [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL4:%.*]] = phi ptr [ [[IND_END3]], [[MIDDLE_BLOCK]] ], [ [[START_2]], [[ENTRY]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL4:%.*]] = phi ptr [ [[TMP12]], [[MIDDLE_BLOCK]] ], [ [[END]], [[ENTRY]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV_1:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ]
@@ -47,7 +47,7 @@ define ptr @test(ptr %start.1, ptr %start.2, ptr %end) {
; CHECK-NEXT: store i64 0, ptr [[IV_2]], align 8
; CHECK-NEXT: [[IV_2_NEXT]] = getelementptr inbounds ptr, ptr [[IV_2]], i64 1
; CHECK-NEXT: [[IV_1_NEXT]] = getelementptr inbounds ptr, ptr [[IV_1]], i64 1
-; CHECK-NEXT: [[CMP_I_I_NOT_I:%.*]] = icmp eq ptr [[IV_2_NEXT]], [[END]]
+; CHECK-NEXT: [[CMP_I_I_NOT_I:%.*]] = icmp eq ptr [[IV_2_NEXT]], [[START_2]]
; CHECK-NEXT: br i1 [[CMP_I_I_NOT_I]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: [[RES_LCSSA:%.*]] = phi ptr [ [[IV_1]], [[LOOP]] ], [ [[IND_ESCAPE]], [[MIDDLE_BLOCK]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
index d39a7b0c23ef8..89a5fab120ac3 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll
@@ -131,10 +131,10 @@ define void @derived_pointer_ivs(ptr noalias %a, ptr noalias %b, ptr %end) {
; VF2-LABEL: define void @derived_pointer_ivs(
; VF2-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr [[END:%.*]]) {
; VF2-NEXT: [[ENTRY:.*:]]
-; VF2-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
; VF2-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; VF2-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -16
-; VF2-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[A2]]
+; VF2-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; VF2-NEXT: [[TMP5:%.*]] = sub i64 [[END1]], [[TMP4]]
+; VF2-NEXT: [[TMP1:%.*]] = add i64 [[TMP5]], -16
; VF2-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 4
; VF2-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; VF2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
@@ -164,10 +164,10 @@ define void @derived_pointer_ivs(ptr noalias %a, ptr noalias %b, ptr %end) {
; VF2IC2-LABEL: define void @derived_pointer_ivs(
; VF2IC2-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr [[END:%.*]]) {
; VF2IC2-NEXT: [[ENTRY:.*:]]
-; VF2IC2-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
; VF2IC2-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; VF2IC2-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -16
-; VF2IC2-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[A2]]
+; VF2IC2-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; VF2IC2-NEXT: [[TMP5:%.*]] = sub i64 [[END1]], [[TMP4]]
+; VF2IC2-NEXT: [[TMP1:%.*]] = add i64 [[TMP5]], -16
; VF2IC2-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 4
; VF2IC2-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; VF2IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -202,10 +202,10 @@ define void @derived_pointer_ivs(ptr noalias %a, ptr noalias %b, ptr %end) {
; VF4-LABEL: define void @derived_pointer_ivs(
; VF4-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], ptr [[END:%.*]]) {
; VF4-NEXT: [[ENTRY:.*:]]
-; VF4-NEXT: [[A2:%.*]] = ptrtoint ptr [[A]] to i64
; VF4-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; VF4-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -16
-; VF4-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[A2]]
+; VF4-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64
+; VF4-NEXT: [[TMP5:%.*]] = sub i64 [[END1]], [[TMP4]]
+; VF4-NEXT: [[TMP1:%.*]] = add i64 [[TMP5]], -16
; VF4-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 4
; VF4-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; VF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll b/llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
index 889ce79f45698..fa2b4e95b594f 100644
--- a/llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
+++ b/llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll
@@ -4,12 +4,12 @@
define void @foo(ptr %start, ptr %end) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START:%.*]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END:%.*]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[END1]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[END1]], -1
-; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[START2]], i64 [[TMP1]])
+; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[START:%.*]] to i64
+; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], -1
+; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[END1]], i64 [[TMP10]])
; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[UMIN]] to i32
+; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[TMP9]] to i32
; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP0]], [[TMP2]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP3]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
@@ -24,8 +24,8 @@ define void @foo(ptr %start, ptr %end) {
; CHECK-NEXT: [[INDUCTION3:%.*]] = add i32 [[OFFSET_IDX]], -1
; CHECK-NEXT: [[TMP4:%.*]] = sub i32 -1, [[INDEX]]
; CHECK-NEXT: [[TMP5:%.*]] = add nsw i32 -1, [[INDUCTION3]]
-; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[END]], i32 [[TMP4]]
-; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[END]], i32 [[TMP5]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[START]], i32 [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[START]], i32 [[TMP5]]
; CHECK-NEXT: store i8 0, ptr [[TMP6]], align 1
; CHECK-NEXT: store i8 0, ptr [[TMP7]], align 1
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
@@ -40,9 +40,9 @@ define void @foo(ptr %start, ptr %end) {
; CHECK: while.body:
; CHECK-NEXT: [[COUNT_09:%.*]] = phi i32 [ [[ADD:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
; CHECK-NEXT: [[ADD]] = add nsw i32 -1, [[COUNT_09]]
-; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr [[END]], i32 [[ADD]]
+; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr [[START]], i32 [[ADD]]
; CHECK-NEXT: store i8 0, ptr [[G]], align 1
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult ptr [[START]], [[G]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult ptr [[END]], [[G]]
; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_END_LOOPEXIT]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: while.end.loopexit:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
index 3a3833a1ed2c8..79660f9b19808 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll
@@ -7,10 +7,10 @@ define void @ptr_induction(ptr %p, ptr noalias %q, ptr noalias %p.end) #0 {
; CHECK-LABEL: define void @ptr_induction(
; CHECK-SAME: ptr [[P:%.*]], ptr noalias [[Q:%.*]], ptr noalias [[P_END:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[P2:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[P_END1:%.*]] = ptrtoint ptr [[P_END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[P_END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[P2]]
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[P_END1]], [[TMP1]]
+; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP8]], 1
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[Q]], i64 0
@@ -22,7 +22,7 @@ define void @ptr_induction(ptr %p, ptr noalias %q, ptr noalias %p.end) #0 {
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <vscale x 2 x i64> [ [[TMP2]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[P]], %[[VECTOR_PH]] ], [ [[PTR_IND7:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP1]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT: [[AVL:%.*]] = phi i64 [ [[TMP3]], %[[VECTOR_PH]] ], [ [[AVL_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[VECTOR_GEP:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <vscale x 2 x i64> [[TMP2]]
; CHECK-NEXT: [[TMP4:%.*]] = call i32 @llvm.experimental.get.vector.length.i64(i64 [[AVL]], i32 2, i1 true)
; CHECK-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
@@ -63,13 +63,13 @@ define i1 @scalarize_ptr_induction(ptr %start, ptr %end, ptr noalias %dst, i1 %c
; CHECK-LABEL: define i1 @scalarize_ptr_induction(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]], ptr noalias [[DST:%.*]], i1 [[C:%.*]]) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[START]], i64 4
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -12
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[END1]], [[TMP4]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP5]], -12
; CHECK-NEXT: [[TMP2:%.*]] = udiv i64 [[TMP1]], 12
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
-; CHECK-NEXT: [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[START]], i64 4
; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 2 x ptr> poison, ptr [[DST]], i64 0
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
index 0dd2e3b645f22..c257a5a14cc27 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll
@@ -10,18 +10,18 @@ define void @alias_mask(ptr noalias %a, ptr %b, ptr %c, i64 %n) {
; FINAL-NEXT: Live-in ir<%n> = original trip-count
; FINAL-EMPTY:
; FINAL-NEXT: ir-bb<entry>:
-; FINAL-NEXT: IR %b2 = ptrtoaddr ptr %b to i64
-; FINAL-NEXT: IR %c1 = ptrtoaddr ptr %c to i64
+; FINAL-NEXT: EMIT-SCALAR vp<[[VP2:%[0-9]+]]> = ptrtoaddr ir<%c> to i64
+; FINAL-NEXT: EMIT-SCALAR vp<[[VP3:%[0-9]+]]> = ptrtoaddr ir<%b> to i64
; FINAL-NEXT: Successor(s): vector.clamped.vf.check
; FINAL-EMPTY:
; FINAL-NEXT: vector.clamped.vf.check:
-; FINAL-NEXT: WIDEN-INTRINSIC vp<[[VP2:%[0-9]+]]> = call llvm.loop.dependence.war.mask(ir<%b2>, ir<%c1>, ir<1>)
-; FINAL-NEXT: EMIT vp<%num.active.lanes> = num-active-lanes vp<[[VP2]]>
+; FINAL-NEXT: WIDEN-INTRINSIC vp<[[VP4:%[0-9]+]]> = call llvm.loop.dependence.war.mask(vp<[[VP3]]>, vp<[[VP2]]>, ir<1>)
+; FINAL-NEXT: EMIT vp<%num.active.lanes> = num-active-lanes vp<[[VP4]]>
; FINAL-NEXT: EMIT vp<%vf.is.scalar> = icmp ule vp<%num.active.lanes>, ir<1>
-; FINAL-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = sub ir<-1>, ir<%n>
-; FINAL-NEXT: EMIT vp<%vf.step.overflow> = icmp ult vp<[[VP3]]>, vp<%num.active.lanes>
-; FINAL-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = or vp<%vf.is.scalar>, vp<%vf.step.overflow>
-; FINAL-NEXT: EMIT branch-on-cond vp<[[VP4]]>
+; FINAL-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = sub ir<-1>, ir<%n>
+; FINAL-NEXT: EMIT vp<%vf.step.overflow> = icmp ult vp<[[VP5]]>, vp<%num.active.lanes>
+; FINAL-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = or vp<%vf.is.scalar>, vp<%vf.step.overflow>
+; FINAL-NEXT: EMIT branch-on-cond vp<[[VP6]]>
; FINAL-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
; FINAL-EMPTY:
; FINAL-NEXT: vector.ph:
@@ -30,19 +30,19 @@ define void @alias_mask(ptr noalias %a, ptr %b, ptr %c, i64 %n) {
; FINAL-EMPTY:
; FINAL-NEXT: vector.body:
; FINAL-NEXT: EMIT-SCALAR vp<%index> = phi [ ir<0>, vector.ph ], [ vp<%index.next>, vector.body ]
-; FINAL-NEXT: ACTIVE-LANE-MASK-PHI vp<[[VP6:%[0-9]+]]> = phi vp<%active.lane.mask.entry>, vp<%active.lane.mask.next>
-; FINAL-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = and vp<[[VP6]]>, vp<[[VP2]]>
+; FINAL-NEXT: ACTIVE-LANE-MASK-PHI vp<[[VP8:%[0-9]+]]> = phi vp<%active.lane.mask.entry>, vp<%active.lane.mask.next>
+; FINAL-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = and vp<[[VP8]]>, vp<[[VP4]]>
; FINAL-NEXT: CLONE ir<%ptr.a> = getelementptr inbounds ir<%a>, vp<%index>
-; FINAL-NEXT: WIDEN ir<%ld.a> = load ir<%ptr.a>, vp<[[VP7]]>
+; FINAL-NEXT: WIDEN ir<%ld.a> = load ir<%ptr.a>, vp<[[VP9]]>
; FINAL-NEXT: CLONE ir<%ptr.b> = getelementptr inbounds ir<%b>, vp<%index>
-; FINAL-NEXT: WIDEN ir<%ld.b> = load ir<%ptr.b>, vp<[[VP7]]>
+; FINAL-NEXT: WIDEN ir<%ld.b> = load ir<%ptr.b>, vp<[[VP9]]>
; FINAL-NEXT: WIDEN ir<%add> = add ir<%ld.b>, ir<%ld.a>
; FINAL-NEXT: CLONE ir<%ptr.c> = getelementptr inbounds ir<%c>, vp<%index>
-; FINAL-NEXT: WIDEN store ir<%ptr.c>, ir<%add>, vp<[[VP7]]>
+; FINAL-NEXT: WIDEN store ir<%ptr.c>, ir<%add>, vp<[[VP9]]>
; FINAL-NEXT: EMIT vp<%index.next> = add vp<%index>, vp<%num.active.lanes>
; FINAL-NEXT: EMIT vp<%active.lane.mask.next> = active lane mask vp<%index.next>, ir<%n>, ir<1>
-; FINAL-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = not vp<%active.lane.mask.next>
-; FINAL-NEXT: EMIT branch-on-cond vp<[[VP8]]>
+; FINAL-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = not vp<%active.lane.mask.next>
+; FINAL-NEXT: EMIT branch-on-cond vp<[[VP10]]>
; FINAL-NEXT: Successor(s): middle.block, vector.body
; FINAL-EMPTY:
; FINAL-NEXT: middle.block:
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
index d19c09486a95b..84d56c18ddb30 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
@@ -260,13 +260,12 @@ exit:
define void @scev_ptrtoint_expanded(ptr %start, ptr %end) {
; CHECK-LABEL: VPlan for loop in 'scev_ptrtoint_expanded'
; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
-; CHECK-NEXT: Live-in ir<%0> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<entry>:
-; CHECK-NEXT: IR %start2 = ptrtoint ptr %start to i64
-; CHECK-NEXT: IR %end1 = ptrtoint ptr %end to i64
-; CHECK-NEXT: IR %0 = sub i64 %end1, %start2
-; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%0>, ir<4>
+; CHECK-NEXT: EMIT-SCALAR vp<[[VP2:%[0-9]+]]> = ptrtoint ir<%end> to i64
+; CHECK-NEXT: EMIT-SCALAR vp<[[VP3:%[0-9]+]]> = ptrtoint ir<%start> to i64
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = sub vp<[[VP2]]>, vp<[[VP3]]>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP4]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
;
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
index 2204d3acb7f87..dc0c673267026 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll
@@ -4,34 +4,33 @@
define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; CHECK-LABEL: VPlan for loop in 'switch4_default_common_dest_with_case'
; CHECK: VPlan 'Final VPlan for VF={2},UF={1}' {
-; CHECK-NEXT: Live-in ir<%0> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<entry>:
-; CHECK-NEXT: IR %start2 = ptrtoint ptr %start to i64
-; CHECK-NEXT: IR %end1 = ptrtoint ptr %end to i64
-; CHECK-NEXT: IR %0 = sub i64 %end1, %start2
-; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%0>, ir<2>
+; CHECK-NEXT: EMIT-SCALAR vp<[[VP2:%[0-9]+]]> = ptrtoint ir<%end> to i64
+; CHECK-NEXT: EMIT-SCALAR vp<[[VP3:%[0-9]+]]> = ptrtoint ir<%start> to i64
+; CHECK-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = sub vp<[[VP2]]>, vp<[[VP3]]>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP4]]>, ir<2>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
; CHECK-EMPTY:
; CHECK-NEXT: vector.ph:
-; CHECK-NEXT: EMIT vp<%n.mod.vf> = urem ir<%0>, ir<2>
-; CHECK-NEXT: EMIT vp<%n.vec> = sub ir<%0>, vp<%n.mod.vf>
-; CHECK-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = ptradd ir<%start>, vp<%n.vec>
+; CHECK-NEXT: EMIT vp<%n.mod.vf> = urem vp<[[VP4]]>, ir<2>
+; CHECK-NEXT: EMIT vp<%n.vec> = sub vp<[[VP4]]>, vp<%n.mod.vf>
+; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = ptradd ir<%start>, vp<%n.vec>
; CHECK-NEXT: Successor(s): vector.body
; CHECK-EMPTY:
; CHECK-NEXT: vector.body:
; CHECK-NEXT: EMIT-SCALAR vp<%index> = phi [ ir<0>, vector.ph ], [ vp<%index.next>, pred.store.continue ]
-; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = SCALAR-STEPS vp<%index>, ir<1>, ir<2>, ir<1>
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<%index>, ir<1>, ir<2>, ir<1>
; CHECK-NEXT: EMIT vp<%next.gep> = ptradd ir<%start>, vp<%index>
-; CHECK-NEXT: EMIT vp<%next.gep>.1 = ptradd ir<%start>, vp<[[VP4]]>
+; CHECK-NEXT: EMIT vp<%next.gep>.1 = ptradd ir<%start>, vp<[[VP7]]>
; CHECK-NEXT: WIDEN ir<%l> = load vp<%next.gep>
-; CHECK-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = icmp eq ir<%l>, ir<-12>
-; CHECK-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = icmp eq ir<%l>, ir<13>
-; CHECK-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = or vp<[[VP5]]>, vp<[[VP6]]>
-; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = not vp<[[VP7]]>
-; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = extractelement vp<[[VP6]]>, ir<0>
-; CHECK-NEXT: EMIT branch-on-cond vp<[[VP9]]>
+; CHECK-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = icmp eq ir<%l>, ir<-12>
+; CHECK-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = icmp eq ir<%l>, ir<13>
+; CHECK-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = or vp<[[VP8]]>, vp<[[VP9]]>
+; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = not vp<[[VP10]]>
+; CHECK-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = extractelement vp<[[VP9]]>, ir<0>
+; CHECK-NEXT: EMIT branch-on-cond vp<[[VP12]]>
; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.if:
@@ -39,8 +38,8 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; CHECK-NEXT: Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.continue:
-; CHECK-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = extractelement vp<[[VP6]]>, ir<1>
-; CHECK-NEXT: EMIT branch-on-cond vp<[[VP11]]>
+; CHECK-NEXT: EMIT vp<[[VP14:%[0-9]+]]> = extractelement vp<[[VP9]]>, ir<1>
+; CHECK-NEXT: EMIT branch-on-cond vp<[[VP14]]>
; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.if:
@@ -48,8 +47,8 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; CHECK-NEXT: Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.continue:
-; CHECK-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = extractelement vp<[[VP5]]>, ir<0>
-; CHECK-NEXT: EMIT branch-on-cond vp<[[VP13]]>
+; CHECK-NEXT: EMIT vp<[[VP16:%[0-9]+]]> = extractelement vp<[[VP8]]>, ir<0>
+; CHECK-NEXT: EMIT branch-on-cond vp<[[VP16]]>
; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.if:
@@ -57,8 +56,8 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; CHECK-NEXT: Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.continue:
-; CHECK-NEXT: EMIT vp<[[VP15:%[0-9]+]]> = extractelement vp<[[VP5]]>, ir<1>
-; CHECK-NEXT: EMIT branch-on-cond vp<[[VP15]]>
+; CHECK-NEXT: EMIT vp<[[VP18:%[0-9]+]]> = extractelement vp<[[VP8]]>, ir<1>
+; CHECK-NEXT: EMIT branch-on-cond vp<[[VP18]]>
; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.if:
@@ -66,8 +65,8 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; CHECK-NEXT: Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.continue:
-; CHECK-NEXT: EMIT vp<[[VP17:%[0-9]+]]> = extractelement vp<[[VP8]]>, ir<0>
-; CHECK-NEXT: EMIT branch-on-cond vp<[[VP17]]>
+; CHECK-NEXT: EMIT vp<[[VP20:%[0-9]+]]> = extractelement vp<[[VP11]]>, ir<0>
+; CHECK-NEXT: EMIT branch-on-cond vp<[[VP20]]>
; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.if:
@@ -75,8 +74,8 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; CHECK-NEXT: Successor(s): pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.continue:
-; CHECK-NEXT: EMIT vp<[[VP19:%[0-9]+]]> = extractelement vp<[[VP8]]>, ir<1>
-; CHECK-NEXT: EMIT branch-on-cond vp<[[VP19]]>
+; CHECK-NEXT: EMIT vp<[[VP22:%[0-9]+]]> = extractelement vp<[[VP11]]>, ir<1>
+; CHECK-NEXT: EMIT branch-on-cond vp<[[VP22]]>
; CHECK-NEXT: Successor(s): pred.store.if, pred.store.continue
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.if:
@@ -85,12 +84,12 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; CHECK-EMPTY:
; CHECK-NEXT: pred.store.continue:
; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<%index>, ir<2>
-; CHECK-NEXT: EMIT vp<[[VP21:%[0-9]+]]> = icmp eq vp<%index.next>, vp<%n.vec>
-; CHECK-NEXT: EMIT branch-on-cond vp<[[VP21]]>
+; CHECK-NEXT: EMIT vp<[[VP24:%[0-9]+]]> = icmp eq vp<%index.next>, vp<%n.vec>
+; CHECK-NEXT: EMIT branch-on-cond vp<[[VP24]]>
; CHECK-NEXT: Successor(s): middle.block, vector.body
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
-; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq ir<%0>, vp<%n.vec>
+; CHECK-NEXT: EMIT vp<%cmp.n> = icmp eq vp<[[VP4]]>, vp<%n.vec>
; CHECK-NEXT: EMIT branch-on-cond vp<%cmp.n>
; CHECK-NEXT: Successor(s): ir-bb<exit>, ir-bb<scalar.ph>
; CHECK-EMPTY:
@@ -98,7 +97,7 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; CHECK-NEXT: No successors
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<scalar.ph>:
-; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP3]]>, middle.block ], [ ir<%start>, ir-bb<entry> ]
+; CHECK-NEXT: EMIT-SCALAR vp<%bc.resume.val> = phi [ vp<[[VP6]]>, middle.block ], [ ir<%start>, ir-bb<entry> ]
; CHECK-NEXT: Successor(s): ir-bb<loop.header>
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<loop.header>:
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll
index 18d7cb0760fa0..6466a6e141ae5 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll
@@ -55,47 +55,47 @@ define void @alias_mask(ptr noalias %a, ptr %b, ptr %c, i64 %n) {
; FINAL-NEXT: Live-in ir<%n> = original trip-count
; FINAL-EMPTY:
; FINAL-NEXT: ir-bb<entry>:
-; FINAL-NEXT: IR %b2 = ptrtoaddr ptr %b to i64
-; FINAL-NEXT: IR %c1 = ptrtoaddr ptr %c to i64
+; FINAL-NEXT: EMIT-SCALAR vp<[[VP2:%[0-9]+]]> = ptrtoaddr ir<%c> to i64
+; FINAL-NEXT: EMIT-SCALAR vp<[[VP3:%[0-9]+]]> = ptrtoaddr ir<%b> to i64
; FINAL-NEXT: Successor(s): vector.clamped.vf.check
; FINAL-EMPTY:
; FINAL-NEXT: vector.clamped.vf.check:
-; FINAL-NEXT: WIDEN-INTRINSIC vp<[[VP2:%[0-9]+]]> = call llvm.loop.dependence.war.mask(ir<%b2>, ir<%c1>, ir<1>)
-; FINAL-NEXT: EMIT vp<%num.active.lanes> = num-active-lanes vp<[[VP2]]>
+; FINAL-NEXT: WIDEN-INTRINSIC vp<[[VP4:%[0-9]+]]> = call llvm.loop.dependence.war.mask(vp<[[VP3]]>, vp<[[VP2]]>, ir<1>)
+; FINAL-NEXT: EMIT vp<%num.active.lanes> = num-active-lanes vp<[[VP4]]>
; FINAL-NEXT: EMIT vp<%vf.is.scalar> = icmp ule vp<%num.active.lanes>, ir<1>
-; FINAL-NEXT: EMIT vp<[[VP3:%[0-9]+]]> = sub ir<-1>, ir<%n>
-; FINAL-NEXT: EMIT vp<%vf.step.overflow> = icmp ult vp<[[VP3]]>, vp<%num.active.lanes>
-; FINAL-NEXT: EMIT vp<[[VP4:%[0-9]+]]> = or vp<%vf.is.scalar>, vp<%vf.step.overflow>
-; FINAL-NEXT: EMIT branch-on-cond vp<[[VP4]]>
+; FINAL-NEXT: EMIT vp<[[VP5:%[0-9]+]]> = sub ir<-1>, ir<%n>
+; FINAL-NEXT: EMIT vp<%vf.step.overflow> = icmp ult vp<[[VP5]]>, vp<%num.active.lanes>
+; FINAL-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = or vp<%vf.is.scalar>, vp<%vf.step.overflow>
+; FINAL-NEXT: EMIT branch-on-cond vp<[[VP6]]>
; FINAL-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
; FINAL-EMPTY:
; FINAL-NEXT: vector.ph:
; FINAL-NEXT: EMIT vp<%trip.count.minus.1> = sub ir<%n>, ir<1>
-; FINAL-NEXT: EMIT vp<[[VP6:%[0-9]+]]> = sub vp<%num.active.lanes>, ir<1>
-; FINAL-NEXT: EMIT vp<%n.rnd.up> = add ir<%n>, vp<[[VP6]]>
+; FINAL-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = sub vp<%num.active.lanes>, ir<1>
+; FINAL-NEXT: EMIT vp<%n.rnd.up> = add ir<%n>, vp<[[VP8]]>
; FINAL-NEXT: EMIT vp<%n.mod.vf> = urem vp<%n.rnd.up>, vp<%num.active.lanes>
; FINAL-NEXT: EMIT vp<%n.vec> = sub vp<%n.rnd.up>, vp<%n.mod.vf>
-; FINAL-NEXT: EMIT vp<[[VP7:%[0-9]+]]> = broadcast vp<%trip.count.minus.1>
-; FINAL-NEXT: EMIT vp<[[VP8:%[0-9]+]]> = step-vector i64
-; FINAL-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = broadcast vp<%num.active.lanes>
+; FINAL-NEXT: EMIT vp<[[VP9:%[0-9]+]]> = broadcast vp<%trip.count.minus.1>
+; FINAL-NEXT: EMIT vp<[[VP10:%[0-9]+]]> = step-vector i64
+; FINAL-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = broadcast vp<%num.active.lanes>
; FINAL-NEXT: Successor(s): vector.body
; FINAL-EMPTY:
; FINAL-NEXT: vector.body:
; FINAL-NEXT: EMIT-SCALAR vp<%index> = phi [ ir<0>, vector.ph ], [ vp<%index.next>, vector.body ]
-; FINAL-NEXT: WIDEN-PHI vp<[[VP10:%[0-9]+]]> = phi [ vp<[[VP8]]>, vector.ph ], [ vp<%vec.ind.next>, vector.body ]
-; FINAL-NEXT: EMIT vp<[[VP11:%[0-9]+]]> = icmp ule vp<[[VP10]]>, vp<[[VP7]]>
-; FINAL-NEXT: EMIT vp<[[VP12:%[0-9]+]]> = and vp<[[VP11]]>, vp<[[VP2]]>
+; FINAL-NEXT: WIDEN-PHI vp<[[VP12:%[0-9]+]]> = phi [ vp<[[VP10]]>, vector.ph ], [ vp<%vec.ind.next>, vector.body ]
+; FINAL-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = icmp ule vp<[[VP12]]>, vp<[[VP9]]>
+; FINAL-NEXT: EMIT vp<[[VP14:%[0-9]+]]> = and vp<[[VP13]]>, vp<[[VP4]]>
; FINAL-NEXT: CLONE ir<%ptr.a> = getelementptr inbounds ir<%a>, vp<%index>
-; FINAL-NEXT: WIDEN ir<%ld.a> = load ir<%ptr.a>, vp<[[VP12]]>
+; FINAL-NEXT: WIDEN ir<%ld.a> = load ir<%ptr.a>, vp<[[VP14]]>
; FINAL-NEXT: CLONE ir<%ptr.b> = getelementptr inbounds ir<%b>, vp<%index>
-; FINAL-NEXT: WIDEN ir<%ld.b> = load ir<%ptr.b>, vp<[[VP12]]>
+; FINAL-NEXT: WIDEN ir<%ld.b> = load ir<%ptr.b>, vp<[[VP14]]>
; FINAL-NEXT: WIDEN ir<%add> = add ir<%ld.b>, ir<%ld.a>
; FINAL-NEXT: CLONE ir<%ptr.c> = getelementptr inbounds ir<%c>, vp<%index>
-; FINAL-NEXT: WIDEN store ir<%ptr.c>, ir<%add>, vp<[[VP12]]>
+; FINAL-NEXT: WIDEN store ir<%ptr.c>, ir<%add>, vp<[[VP14]]>
; FINAL-NEXT: EMIT vp<%index.next> = add vp<%index>, vp<%num.active.lanes>
-; FINAL-NEXT: EMIT vp<%vec.ind.next> = add nuw vp<[[VP10]]>, vp<[[VP9]]>
-; FINAL-NEXT: EMIT vp<[[VP13:%[0-9]+]]> = icmp eq vp<%index.next>, vp<%n.vec>
-; FINAL-NEXT: EMIT branch-on-cond vp<[[VP13]]>
+; FINAL-NEXT: EMIT vp<%vec.ind.next> = add nuw vp<[[VP12]]>, vp<[[VP11]]>
+; FINAL-NEXT: EMIT vp<[[VP15:%[0-9]+]]> = icmp eq vp<%index.next>, vp<%n.vec>
+; FINAL-NEXT: EMIT branch-on-cond vp<[[VP15]]>
; FINAL-NEXT: Successor(s): middle.block, vector.body
; FINAL-EMPTY:
; FINAL-NEXT: middle.block:
diff --git a/llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll b/llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
index 5fa5fa93775a7..7e7bd3243ab76 100644
--- a/llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll
@@ -8,8 +8,8 @@ define void @induction_phi_and_branch_cost(ptr %end, ptr %start.1, ptr %start.2)
; CHECK-LABEL: define void @induction_phi_and_branch_cost(
; CHECK-SAME: ptr [[END:%.*]], ptr [[START_1:%.*]], ptr [[START_2:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[END2:%.*]] = ptrtoint ptr [[END]] to i32
; CHECK-NEXT: [[START_11:%.*]] = ptrtoint ptr [[START_1]] to i32
+; CHECK-NEXT: [[END2:%.*]] = ptrtoint ptr [[END]] to i32
; CHECK-NEXT: [[TMP0:%.*]] = sub i32 [[START_11]], [[END2]]
; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[TMP0]], 2
; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/X86/cost-model.ll b/llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
index ea98c4c116952..1853b2648af7e 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/cost-model.ll
@@ -550,8 +550,8 @@ define i1 @any_of_cost(ptr %start, ptr %end) #0 {
; CHECK-LABEL: define i1 @any_of_cost(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR2]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
+; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]
; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], 40
; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll b/llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
index 65729c941696b..d83617bf7b45d 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll
@@ -44,10 +44,10 @@ define ptr @low_trip_count_via_profile_info_with_iv_live_out(ptr align 16 %start
; CHECK-LABEL: define ptr @low_trip_count_via_profile_info_with_iv_live_out(
; CHECK-SAME: ptr align 16 [[START:%.*]], ptr align 16 [[END:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP7]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP1]], 63
@@ -98,10 +98,10 @@ define void @low_trip_count_via_profile_info(ptr align 16 %start, ptr align 16 %
; CHECK-LABEL: define void @low_trip_count_via_profile_info(
; CHECK-SAME: ptr align 16 [[START:%.*]], ptr align 16 [[END:%.*]], ptr noalias [[SRC:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[END1]], [[TMP6]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP7]], 1
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP1]], 63
diff --git a/llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll b/llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
index 1944387ece3e7..4f52fcfb5402f 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll
@@ -11,8 +11,8 @@ define void @test_pr55375_interleave_opaque_ptr(ptr %start, ptr %end) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START:%.*]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END:%.*]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -16
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[START2]], [[END1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP5]], -16
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 4
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
@@ -21,11 +21,11 @@ define void @test_pr55375_interleave_opaque_ptr(ptr %start, ptr %end) {
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 2
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
; CHECK-NEXT: [[TMP4:%.*]] = shl i64 [[N_VEC]], 4
-; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[END]], i64 [[TMP4]]
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[START]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[END]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <2 x i64> <i64 0, i64 16>
; CHECK-NEXT: [[TMP7:%.*]] = extractelement <2 x ptr> [[TMP10]], i64 0
; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <2 x ptr> splat (ptr null), <2 x ptr> [[TMP10]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -39,7 +39,7 @@ define void @test_pr55375_interleave_opaque_ptr(ptr %start, ptr %end) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP8]], [[MIDDLE_BLOCK]] ], [ [[END]], [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
@@ -47,7 +47,7 @@ define void @test_pr55375_interleave_opaque_ptr(ptr %start, ptr %end) {
; CHECK-NEXT: store ptr [[IV]], ptr [[IV_1]], align 8
; CHECK-NEXT: store ptr null, ptr [[IV]], align 8
; CHECK-NEXT: [[IV_NEXT]] = getelementptr inbounds [[PAIR]], ptr [[IV]], i64 1
-; CHECK-NEXT: [[EC:%.*]] = icmp eq ptr [[IV_NEXT]], [[END]]
+; CHECK-NEXT: [[EC:%.*]] = icmp eq ptr [[IV_NEXT]], [[START]]
; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/LoopVectorize/X86/optsize.ll b/llvm/test/Transforms/LoopVectorize/X86/optsize.ll
index 8460af9e6aa25..fa3b93503ecdf 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/optsize.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/optsize.ll
@@ -325,10 +325,10 @@ define void @tail_folded_store_avx512(ptr %start, ptr %end) #3 {
; CHECK-LABEL: define void @tail_folded_store_avx512(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR3:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[END2:%.*]] = ptrtoint ptr [[END]] to i32
; CHECK-NEXT: [[START1:%.*]] = ptrtoint ptr [[START]] to i32
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[START1]], -72
-; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[END2]]
+; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[END]] to i32
+; CHECK-NEXT: [[TMP8:%.*]] = sub i32 [[START1]], [[TMP4]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP8]], -72
; CHECK-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 72
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], 1
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
@@ -360,10 +360,10 @@ define void @tail_folded_store_avx512(ptr %start, ptr %end) #3 {
; AUTOVF-LABEL: define void @tail_folded_store_avx512(
; AUTOVF-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR3:[0-9]+]] {
; AUTOVF-NEXT: [[ENTRY:.*:]]
-; AUTOVF-NEXT: [[END2:%.*]] = ptrtoint ptr [[END]] to i32
; AUTOVF-NEXT: [[START1:%.*]] = ptrtoint ptr [[START]] to i32
-; AUTOVF-NEXT: [[TMP0:%.*]] = add i32 [[START1]], -72
-; AUTOVF-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[END2]]
+; AUTOVF-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[END]] to i32
+; AUTOVF-NEXT: [[TMP8:%.*]] = sub i32 [[START1]], [[TMP4]]
+; AUTOVF-NEXT: [[TMP1:%.*]] = add i32 [[TMP8]], -72
; AUTOVF-NEXT: [[TMP2:%.*]] = udiv i32 [[TMP1]], 72
; AUTOVF-NEXT: [[TMP3:%.*]] = add nuw nsw i32 [[TMP2]], 1
; AUTOVF-NEXT: br label %[[VECTOR_PH:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr48340.ll b/llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
index 5eb12b5e932f2..1c3454da43a22 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr48340.ll
@@ -12,8 +12,8 @@ define ptr @foo(ptr %p, ptr %p.last) #0 {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[P3:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[P_LAST1:%.*]] = ptrtoint ptr [[P_LAST:%.*]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[P_LAST1]], -1024
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[P3]]
+; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[P3]], [[P_LAST1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP6]], -1024
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 10
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 16
@@ -22,11 +22,11 @@ define ptr @foo(ptr %p, ptr %p.last) #0 {
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 16
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
; CHECK-NEXT: [[TMP4:%.*]] = shl i64 [[N_VEC]], 10
-; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[P_LAST]], i64 [[TMP4]]
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[P]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[P_LAST]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <4 x i64> <i64 0, i64 1024, i64 2048, i64 3072>
; CHECK-NEXT: [[STEP_ADD:%.*]] = getelementptr i8, <4 x ptr> [[TMP5]], <4 x i64> splat (i64 4096)
; CHECK-NEXT: [[STEP_ADD_2:%.*]] = getelementptr i8, <4 x ptr> [[STEP_ADD]], <4 x i64> splat (i64 4096)
@@ -41,13 +41,13 @@ define ptr @foo(ptr %p, ptr %p.last) #0 {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[P]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP7]], [[MIDDLE_BLOCK]] ], [ [[P_LAST]], [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[P2:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[P_INC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[P_INC]] = getelementptr inbounds i64, ptr [[P2]], i64 128
; CHECK-NEXT: [[V:%.*]] = load ptr, ptr [[P2]], align 8
-; CHECK-NEXT: [[B:%.*]] = icmp eq ptr [[P_INC]], [[P_LAST]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq ptr [[P_INC]], [[P]]
; CHECK-NEXT: br i1 [[B]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: [[V_LCSSA:%.*]] = phi ptr [ [[V]], [[LOOP]] ], [ [[TMP10]], [[MIDDLE_BLOCK]] ]
@@ -72,8 +72,8 @@ define ptr @bar(ptr %p, ptr %p.last) #0 {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[P3:%.*]] = ptrtoint ptr [[P:%.*]] to i64
; CHECK-NEXT: [[P_LAST1:%.*]] = ptrtoint ptr [[P_LAST:%.*]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[P_LAST1]], -1024
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[P3]]
+; CHECK-NEXT: [[TMP6:%.*]] = sub i64 [[P3]], [[P_LAST1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP6]], -1024
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 10
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 16
@@ -82,11 +82,11 @@ define ptr @bar(ptr %p, ptr %p.last) #0 {
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 16
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
; CHECK-NEXT: [[TMP4:%.*]] = shl i64 [[N_VEC]], 10
-; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[P_LAST]], i64 [[TMP4]]
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[P]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[P_LAST]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <4 x i64> <i64 0, i64 1024, i64 2048, i64 3072>
; CHECK-NEXT: [[STEP_ADD:%.*]] = getelementptr i8, <4 x ptr> [[TMP5]], <4 x i64> splat (i64 4096)
; CHECK-NEXT: [[STEP_ADD_2:%.*]] = getelementptr i8, <4 x ptr> [[STEP_ADD]], <4 x i64> splat (i64 4096)
@@ -101,13 +101,13 @@ define ptr @bar(ptr %p, ptr %p.last) #0 {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[P]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP7]], [[MIDDLE_BLOCK]] ], [ [[P_LAST]], [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[P2:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[P_INC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[P_INC]] = getelementptr inbounds i64, ptr [[P2]], i64 128
; CHECK-NEXT: [[V:%.*]] = load ptr, ptr [[P2]], align 8
-; CHECK-NEXT: [[B:%.*]] = icmp eq ptr [[P_INC]], [[P_LAST]]
+; CHECK-NEXT: [[B:%.*]] = icmp eq ptr [[P_INC]], [[P]]
; CHECK-NEXT: br i1 [[B]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: [[V_LCSSA:%.*]] = phi ptr [ [[V]], [[LOOP]] ], [ [[TMP10]], [[MIDDLE_BLOCK]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll b/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
index e06a063fe4aa7..f96de49bcb5a4 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr72969.ll
@@ -28,10 +28,11 @@ define void @test(ptr %p) {
; VEC-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {
; VEC-NEXT: entry:
; VEC-NEXT: [[P1:%.*]] = ptrtoint ptr [[P]] to i64
-; VEC-NEXT: [[TMP0:%.*]] = add i64 [[P1]], 16
-; VEC-NEXT: [[UMAX2:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 add (i64 ptrtoint (ptr @h to i64), i64 1))
-; VEC-NEXT: [[TMP1:%.*]] = add i64 [[UMAX2]], -9
-; VEC-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[P1]]
+; VEC-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P]] to i64
+; VEC-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 16
+; VEC-NEXT: [[TMP9:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 add (i64 ptrtoint (ptr @h to i64), i64 1))
+; VEC-NEXT: [[TMP15:%.*]] = sub i64 [[TMP9]], [[TMP0]]
+; VEC-NEXT: [[TMP2:%.*]] = add i64 [[TMP15]], -9
; VEC-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; VEC-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; VEC-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 8
diff --git a/llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll b/llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
index 4802df6caee6d..1b20ad367a4e2 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll
@@ -6,10 +6,10 @@ define void @switch_default_to_latch_common_dest(ptr %start, ptr %end) {
; COST-LABEL: define void @switch_default_to_latch_common_dest(
; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0:[0-9]+]] {
; COST-NEXT: [[ENTRY:.*]]:
-; COST-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; COST-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; COST-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; COST-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[START]] to i64
+; COST-NEXT: [[TMP12:%.*]] = sub i64 [[END1]], [[TMP11]]
+; COST-NEXT: [[TMP1:%.*]] = add i64 [[TMP12]], -8
; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -58,10 +58,10 @@ define void @switch_default_to_latch_common_dest(ptr %start, ptr %end) {
; FORCED-LABEL: define void @switch_default_to_latch_common_dest(
; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0:[0-9]+]] {
; FORCED-NEXT: [[ENTRY:.*]]:
-; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; FORCED-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[START]] to i64
+; FORCED-NEXT: [[TMP16:%.*]] = sub i64 [[END1]], [[TMP15]]
+; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP16]], -8
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -141,10 +141,10 @@ define void @switch_default_to_latch_common_dest_using_branches(ptr %start, ptr
; COST-LABEL: define void @switch_default_to_latch_common_dest_using_branches(
; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; COST-NEXT: [[ENTRY:.*]]:
-; COST-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; COST-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; COST-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; COST-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[START]] to i64
+; COST-NEXT: [[TMP14:%.*]] = sub i64 [[END1]], [[TMP13]]
+; COST-NEXT: [[TMP1:%.*]] = add i64 [[TMP14]], -8
; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -196,10 +196,10 @@ define void @switch_default_to_latch_common_dest_using_branches(ptr %start, ptr
; FORCED-LABEL: define void @switch_default_to_latch_common_dest_using_branches(
; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; FORCED-NEXT: [[ENTRY:.*]]:
-; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; FORCED-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[START]] to i64
+; FORCED-NEXT: [[TMP20:%.*]] = sub i64 [[END1]], [[TMP19]]
+; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP20]], -8
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -319,10 +319,10 @@ define void @switch_all_dests_distinct(ptr %start, ptr %end) {
; FORCED-LABEL: define void @switch_all_dests_distinct(
; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; FORCED-NEXT: [[ENTRY:.*]]:
-; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; FORCED-NEXT: [[TMP21:%.*]] = ptrtoint ptr [[START]] to i64
+; FORCED-NEXT: [[TMP22:%.*]] = sub i64 [[END1]], [[TMP21]]
+; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP22]], -8
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -437,10 +437,10 @@ define void @switch_all_dests_distinct_variant_using_branches(ptr %start, ptr %e
; COST-LABEL: define void @switch_all_dests_distinct_variant_using_branches(
; COST-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; COST-NEXT: [[ENTRY:.*]]:
-; COST-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; COST-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; COST-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; COST-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; COST-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[START]] to i64
+; COST-NEXT: [[TMP17:%.*]] = sub i64 [[END1]], [[TMP16]]
+; COST-NEXT: [[TMP1:%.*]] = add i64 [[TMP17]], -8
; COST-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; COST-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; COST-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -509,10 +509,10 @@ define void @switch_all_dests_distinct_variant_using_branches(ptr %start, ptr %e
; FORCED-LABEL: define void @switch_all_dests_distinct_variant_using_branches(
; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; FORCED-NEXT: [[ENTRY:.*]]:
-; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; FORCED-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[START]] to i64
+; FORCED-NEXT: [[TMP26:%.*]] = sub i64 [[END1]], [[TMP25]]
+; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP26]], -8
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -669,10 +669,10 @@ define void @switch_multiple_common_dests(ptr %start, ptr %end) {
; FORCED-LABEL: define void @switch_multiple_common_dests(
; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; FORCED-NEXT: [[ENTRY:.*]]:
-; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; FORCED-NEXT: [[TMP29:%.*]] = ptrtoint ptr [[START]] to i64
+; FORCED-NEXT: [[TMP30:%.*]] = sub i64 [[END1]], [[TMP29]]
+; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP30]], -8
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -818,10 +818,10 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; FORCED-LABEL: define void @switch4_default_common_dest_with_case(
; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; FORCED-NEXT: [[ENTRY:.*]]:
-; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; FORCED-NEXT: [[TMP17:%.*]] = ptrtoint ptr [[START]] to i64
+; FORCED-NEXT: [[TMP18:%.*]] = sub i64 [[END1]], [[TMP17]]
+; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP18]], -8
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -954,10 +954,10 @@ define void @switch_under_br_default_common_dest_with_case(ptr %start, ptr %end,
; FORCED-LABEL: define void @switch_under_br_default_common_dest_with_case(
; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i64 [[X:%.*]]) #[[ATTR0]] {
; FORCED-NEXT: [[ENTRY:.*]]:
-; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; FORCED-NEXT: [[TMP25:%.*]] = ptrtoint ptr [[START]] to i64
+; FORCED-NEXT: [[TMP26:%.*]] = sub i64 [[END1]], [[TMP25]]
+; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP26]], -8
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -1107,10 +1107,10 @@ define void @br_under_switch_default_common_dest_with_case(ptr %start, ptr %end,
; FORCED-LABEL: define void @br_under_switch_default_common_dest_with_case(
; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i64 [[X:%.*]]) #[[ATTR0]] {
; FORCED-NEXT: [[ENTRY:.*]]:
-; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; FORCED-NEXT: [[TMP29:%.*]] = ptrtoint ptr [[START]] to i64
+; FORCED-NEXT: [[TMP30:%.*]] = sub i64 [[END1]], [[TMP29]]
+; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP30]], -8
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
@@ -1261,10 +1261,10 @@ define void @large_number_of_cases(ptr %start, ptr %end) {
; FORCED-LABEL: define void @large_number_of_cases(
; FORCED-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; FORCED-NEXT: [[ENTRY:.*]]:
-; FORCED-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; FORCED-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; FORCED-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; FORCED-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; FORCED-NEXT: [[TMP43:%.*]] = ptrtoint ptr [[START]] to i64
+; FORCED-NEXT: [[TMP44:%.*]] = sub i64 [[END1]], [[TMP43]]
+; FORCED-NEXT: [[TMP1:%.*]] = add i64 [[TMP44]], -8
; FORCED-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; FORCED-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; FORCED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 8
diff --git a/llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll b/llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
index 9ab6484da2b6b..1062bf59e0c58 100644
--- a/llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
+++ b/llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll
@@ -5,8 +5,8 @@ define void @test(ptr %src, ptr %dst, i32 %n) {
; CHECK-LABEL: define void @test(
; CHECK-SAME: ptr [[SRC:%.*]], ptr [[DST:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[SRC2:%.*]] = ptrtoaddr ptr [[SRC]] to i64
; CHECK-NEXT: [[DST1:%.*]] = ptrtoaddr ptr [[DST]] to i64
+; CHECK-NEXT: [[SRC2:%.*]] = ptrtoaddr ptr [[SRC]] to i64
; CHECK-NEXT: [[UMAX3:%.*]] = call i32 @llvm.umax.i32(i32 [[N]], i32 1)
; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/alias-mask-needs-freeze.ll b/llvm/test/Transforms/LoopVectorize/alias-mask-needs-freeze.ll
index 44940aff48699..4f729ef8552fa 100644
--- a/llvm/test/Transforms/LoopVectorize/alias-mask-needs-freeze.ll
+++ b/llvm/test/Transforms/LoopVectorize/alias-mask-needs-freeze.ll
@@ -6,10 +6,10 @@ define void @alias_mask_forked_pointer_needs_freeze(ptr %base1, ptr %base2,
; CHECK-LABEL: define void @alias_mask_forked_pointer_needs_freeze(
; CHECK-SAME: ptr [[BASE1:%.*]], ptr [[BASE2:%.*]], ptr [[DEST:%.*]], ptr [[PREDICATES:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[PREDICATES4:%.*]] = ptrtoaddr ptr [[PREDICATES]] to i64
-; CHECK-NEXT: [[BASE23:%.*]] = ptrtoaddr ptr [[BASE2]] to i64
-; CHECK-NEXT: [[BASE12:%.*]] = ptrtoaddr ptr [[BASE1]] to i64
; CHECK-NEXT: [[DEST1:%.*]] = ptrtoaddr ptr [[DEST]] to i64
+; CHECK-NEXT: [[BASE12:%.*]] = ptrtoaddr ptr [[BASE1]] to i64
+; CHECK-NEXT: [[BASE23:%.*]] = ptrtoaddr ptr [[BASE2]] to i64
+; CHECK-NEXT: [[PREDICATES4:%.*]] = ptrtoaddr ptr [[PREDICATES]] to i64
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[TMP0:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[PREDICATES4]], i64 [[DEST1]], i64 4)
@@ -18,8 +18,7 @@ define void @alias_mask_forked_pointer_needs_freeze(ptr %base1, ptr %base2,
; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[TMP1]], i64 [[TMP2]], i64 4)
; CHECK-NEXT: [[TMP4:%.*]] = and <4 x i1> [[TMP0]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = freeze i64 [[BASE12]]
-; CHECK-NEXT: [[TMP6:%.*]] = freeze i64 [[DEST1]]
-; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[TMP5]], i64 [[TMP6]], i64 4)
+; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[TMP5]], i64 [[TMP2]], i64 4)
; CHECK-NEXT: [[TMP8:%.*]] = and <4 x i1> [[TMP4]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext <4 x i1> [[TMP8]] to <4 x i64>
; CHECK-NEXT: [[NUM_ACTIVE_LANES:%.*]] = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> [[TMP9]])
diff --git a/llvm/test/Transforms/LoopVectorize/alias-mask-small-index.ll b/llvm/test/Transforms/LoopVectorize/alias-mask-small-index.ll
index 3605ab03911bb..b3c3d31daa192 100644
--- a/llvm/test/Transforms/LoopVectorize/alias-mask-small-index.ll
+++ b/llvm/test/Transforms/LoopVectorize/alias-mask-small-index.ll
@@ -9,8 +9,8 @@ define void @alias_mask(ptr noalias %a, ptr %b, ptr %c, i64 %n) {
; CHECK-LABEL: define void @alias_mask(
; CHECK-SAME: ptr noalias [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i16
; CHECK-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i16
+; CHECK-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i16
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[TMP0:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i16(i16 [[B2]], i16 [[C1]], i16 1)
diff --git a/llvm/test/Transforms/LoopVectorize/alias-mask.ll b/llvm/test/Transforms/LoopVectorize/alias-mask.ll
index 841035c96c7a9..7035332a1b763 100644
--- a/llvm/test/Transforms/LoopVectorize/alias-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/alias-mask.ll
@@ -11,8 +11,8 @@ define void @alias_mask(ptr noalias %a, ptr %b, ptr %c, i64 %n) {
; CHECK-LABEL: define void @alias_mask(
; CHECK-SAME: ptr noalias [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
+; CHECK-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[B2]], i64 [[C1]], i64 1)
@@ -79,9 +79,9 @@ define void @alias_mask_multiple(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-LABEL: define void @alias_mask_multiple(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[A3:%.*]] = ptrtoaddr ptr [[A]] to i64
-; CHECK-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
+; CHECK-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-NEXT: [[A3:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[A3]], i64 [[C1]], i64 1)
@@ -149,8 +149,8 @@ define void @alias_mask_non_default_address_space(ptr addrspace(1) noalias %a, p
; CHECK-LABEL: define void @alias_mask_non_default_address_space(
; CHECK-SAME: ptr addrspace(1) noalias [[A:%.*]], ptr addrspace(1) [[B:%.*]], ptr addrspace(1) [[C:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[B2:%.*]] = ptrtoaddr ptr addrspace(1) [[B]] to i64
; CHECK-NEXT: [[C1:%.*]] = ptrtoaddr ptr addrspace(1) [[C]] to i64
+; CHECK-NEXT: [[B2:%.*]] = ptrtoaddr ptr addrspace(1) [[B]] to i64
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[B2]], i64 [[C1]], i64 1)
@@ -217,8 +217,8 @@ define void @alias_mask_known_trip_count(ptr noalias %a, ptr %b, ptr %c) {
; CHECK-LABEL: define void @alias_mask_known_trip_count(
; CHECK-SAME: ptr noalias [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
+; CHECK-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[B2]], i64 [[C1]], i64 1)
@@ -283,8 +283,8 @@ define void @alias_mask_truncated_wide_induction(ptr %a, ptr %b, i64 %n) {
; CHECK-LABEL: define void @alias_mask_truncated_wide_induction(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: [[B1:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[TMP0:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[A2]], i64 [[B1]], i64 2)
@@ -356,8 +356,8 @@ define i8 @add_reduction(ptr %a, ptr %b, i64 %n) {
; CHECK-LABEL: define i8 @add_reduction(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: [[B1:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: br label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
; CHECK-NEXT: [[ALIAS_MASK:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[A2]], i64 [[B1]], i64 1)
@@ -423,8 +423,8 @@ define i32 @find_last_reduction(ptr %a, ptr noalias %b, ptr %c, i64 %n) {
; CHECK-LABEL: define i32 @find_last_reduction(
; CHECK-SAME: ptr [[A:%.*]], ptr noalias [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
+; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[ALIAS_MASK:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[A2]], i64 [[C1]], i64 4)
@@ -502,8 +502,8 @@ define i64 @find_iv_reduction(ptr %a, ptr %b, i64 %n) {
; CHECK-LABEL: define i64 @find_iv_reduction(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: [[B1:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-NEXT: [[ALIAS_MASK:%.*]] = call <4 x i1> @llvm.loop.dependence.war.mask.v4i1.i64(i64 [[A2]], i64 [[B1]], i64 8)
@@ -573,9 +573,9 @@ define i64 @any_of_reduction(i64 %a, ptr %src, ptr %dst, i32 %n) {
; CHECK-LABEL: define i64 @any_of_reduction(
; CHECK-SAME: i64 [[A:%.*]], ptr [[SRC:%.*]], ptr [[DST:%.*]], i32 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[SRC2:%.*]] = ptrtoaddr ptr [[SRC]] to i64
; CHECK-NEXT: [[DST1:%.*]] = ptrtoaddr ptr [[DST]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[DST1]], 4
+; CHECK-NEXT: [[SRC2:%.*]] = ptrtoaddr ptr [[SRC]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[SRC2]], 4
; CHECK-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll b/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
index 9e5cd1a25c6f1..4349e7ea277f7 100644
--- a/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
+++ b/llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll
@@ -212,22 +212,22 @@ define void @load_store_noalias_via_tbaa(ptr %p, ptr %q, ptr %n) {
; CHECK-NEXT: [[P6:%.*]] = ptrtoint ptr [[P]] to i64
; CHECK-NEXT: [[N5:%.*]] = ptrtoint ptr [[N]] to i64
; CHECK-NEXT: [[P2:%.*]] = ptrtoint ptr [[P]] to i64
+; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[P2]], -3074457345618258603
; CHECK-NEXT: [[N1:%.*]] = ptrtoint ptr [[N]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = mul i64 [[N5]], 3074457345618258603
-; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[P6]], 3074457345618258603
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP0]], [[TMP1]]
+; CHECK-NEXT: [[TMP17:%.*]] = mul i64 [[N1]], 3074457345618258603
+; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], [[TMP17]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 2
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[N1]] to i2
-; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[P2]] to i2
+; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[N5]] to i2
+; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[P6]] to i2
; CHECK-NEXT: [[TMP7:%.*]] = sub i2 [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = zext i2 [[TMP7]] to i64
; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[TMP8]], 0
-; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[N1]], 3074457345618258603
-; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[P2]], 3074457345618258603
+; CHECK-NEXT: [[TMP9:%.*]] = mul i64 [[N5]], 3074457345618258603
+; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[P6]], 3074457345618258603
; CHECK-NEXT: [[TMP11:%.*]] = sub i64 [[TMP9]], [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = lshr i64 [[TMP11]], 2
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[P]], i64 4
diff --git a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
index fcfdafa82d75c..2fbe729851799 100644
--- a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
+++ b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll
@@ -138,8 +138,8 @@ define i64 @interleave_group_load_pointer_type(ptr %start, ptr %end) {
; CHECK-LABEL: define i64 @interleave_group_load_pointer_type(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
+; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]
; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], 24
; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
index e9dfebff0d809..eba2fcafbda42 100644
--- a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll
@@ -78,17 +78,17 @@ define void @ir_tbaa_different(ptr %base, ptr %end, ptr %src) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[BASE2:%.*]] = ptrtoint ptr [[BASE]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[BASE3:%.*]] = ptrtoint ptr [[BASE]] to i64
; CHECK-NEXT: [[END2:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[BASE2]]
+; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[BASE]] to i64
+; CHECK-NEXT: [[TMP16:%.*]] = sub i64 [[END2]], [[TMP10]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP16]], -8
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
-; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[END2]], -8
-; CHECK-NEXT: [[TMP12:%.*]] = sub i64 [[TMP10]], [[BASE3]]
+; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[END1]], -8
+; CHECK-NEXT: [[TMP12:%.*]] = sub i64 [[TMP17]], [[BASE2]]
; CHECK-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP12]], 3
; CHECK-NEXT: [[TMP14:%.*]] = shl nuw i64 [[TMP13]], 3
; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP14]], 8
@@ -170,10 +170,10 @@ define void @noalias_metadata_from_versioning(ptr %base, ptr %end, ptr %src) {
; CHECK-LABEL: define void @noalias_metadata_from_versioning(
; CHECK-SAME: ptr [[BASE:%.*]], ptr [[END:%.*]], ptr [[SRC:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[BASE2:%.*]] = ptrtoint ptr [[BASE]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[BASE2]]
+; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[BASE]] to i64
+; CHECK-NEXT: [[TMP11:%.*]] = sub i64 [[END1]], [[TMP10]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP11]], -8
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
diff --git a/llvm/test/Transforms/LoopVectorize/metadata.ll b/llvm/test/Transforms/LoopVectorize/metadata.ll
index 2040dbe247608..66881a385e654 100644
--- a/llvm/test/Transforms/LoopVectorize/metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/metadata.ll
@@ -503,17 +503,17 @@ define void @noalias_metadata(ptr align 8 %dst, ptr align 8 %src) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[SRC4:%.*]] = ptrtoint ptr [[SRC]] to i64
; CHECK-NEXT: [[DST3:%.*]] = ptrtoint ptr [[DST]] to i64
-; CHECK-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64
; CHECK-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64
-; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[DST3]], [[SRC4]]
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[SRC]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[DST1]], [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 8
-; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[DST1]], 8
-; CHECK-NEXT: [[TMP22:%.*]] = sub i64 [[TMP5]], [[SRC2]]
+; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[DST3]], 8
+; CHECK-NEXT: [[TMP22:%.*]] = sub i64 [[TMP5]], [[SRC4]]
; CHECK-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP22]]
; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP5]]
; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]]
@@ -556,17 +556,17 @@ define void @noalias_metadata(ptr align 8 %dst, ptr align 8 %src) {
; INTERLEAVE-NEXT: [[ENTRY:.*]]:
; INTERLEAVE-NEXT: [[SRC4:%.*]] = ptrtoint ptr [[SRC]] to i64
; INTERLEAVE-NEXT: [[DST3:%.*]] = ptrtoint ptr [[DST]] to i64
-; INTERLEAVE-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64
; INTERLEAVE-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64
-; INTERLEAVE-NEXT: [[TMP2:%.*]] = sub i64 [[DST3]], [[SRC4]]
+; INTERLEAVE-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[SRC]] to i64
+; INTERLEAVE-NEXT: [[TMP2:%.*]] = sub i64 [[DST1]], [[TMP1]]
; INTERLEAVE-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; INTERLEAVE-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; INTERLEAVE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 4
; INTERLEAVE-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; INTERLEAVE: [[VECTOR_MEMCHECK]]:
; INTERLEAVE-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 8
-; INTERLEAVE-NEXT: [[TMP5:%.*]] = add i64 [[DST1]], 8
-; INTERLEAVE-NEXT: [[TMP22:%.*]] = sub i64 [[TMP5]], [[SRC2]]
+; INTERLEAVE-NEXT: [[TMP5:%.*]] = add i64 [[DST3]], 8
+; INTERLEAVE-NEXT: [[TMP22:%.*]] = sub i64 [[TMP5]], [[SRC4]]
; INTERLEAVE-NEXT: [[SCEVGEP5:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP22]]
; INTERLEAVE-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP5]]
; INTERLEAVE-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]]
diff --git a/llvm/test/Transforms/LoopVectorize/opaque-ptr.ll b/llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
index c3978d173fd87..cb84af11b2159 100644
--- a/llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
+++ b/llvm/test/Transforms/LoopVectorize/opaque-ptr.ll
@@ -8,24 +8,24 @@ define void @test_ptr_iv_no_inbounds(ptr %p1.start, ptr %p2.start, ptr %p1.end)
; CHECK-NEXT: [[P1_END6:%.*]] = ptrtoint ptr [[P1_END:%.*]] to i64
; CHECK-NEXT: [[P1_START4:%.*]] = ptrtoint ptr [[P1_START]] to i64
; CHECK-NEXT: [[P1_END3:%.*]] = ptrtoint ptr [[P1_END]] to i64
-; CHECK-NEXT: [[P1_START2:%.*]] = ptrtoint ptr [[P1_START]] to i64
; CHECK-NEXT: [[P1_END1:%.*]] = ptrtoint ptr [[P1_END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[P1_END6]], -4
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[P1_START7]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P1_START]] to i64
+; CHECK-NEXT: [[TMP14:%.*]] = sub i64 [[P1_END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP14]], -4
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 2
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
; CHECK: vector.scevcheck:
-; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[P1_END1]] to i2
-; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[P1_START2]] to i2
+; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[P1_END3]] to i2
+; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[P1_START4]] to i2
; CHECK-NEXT: [[TMP6:%.*]] = sub i2 [[TMP4]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = zext i2 [[TMP6]] to i64
; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[TMP7]], 0
; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]]
; CHECK: vector.memcheck:
-; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[P1_END3]], -4
-; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[TMP8]], [[P1_START4]]
+; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[P1_END6]], -4
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[TMP15]], [[P1_START7]]
; CHECK-NEXT: [[TMP10:%.*]] = lshr i64 [[TMP9]], 2
; CHECK-NEXT: [[TMP11:%.*]] = shl nuw i64 [[TMP10]], 2
; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], 4
@@ -99,17 +99,17 @@ define void @test_ptr_iv_with_inbounds(ptr %p1.start, ptr %p2.start, ptr %p1.end
; CHECK-NEXT: entry:
; CHECK-NEXT: [[P1_START5:%.*]] = ptrtoint ptr [[P1_START:%.*]] to i64
; CHECK-NEXT: [[P1_END4:%.*]] = ptrtoint ptr [[P1_END:%.*]] to i64
-; CHECK-NEXT: [[P1_START2:%.*]] = ptrtoint ptr [[P1_START]] to i64
; CHECK-NEXT: [[P1_END1:%.*]] = ptrtoint ptr [[P1_END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[P1_END4]], -4
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[P1_START5]]
+; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P1_START]] to i64
+; CHECK-NEXT: [[TMP10:%.*]] = sub i64 [[P1_END1]], [[TMP4]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP10]], -4
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 2
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]
; CHECK: vector.memcheck:
-; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[P1_END1]], -4
-; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP4]], [[P1_START2]]
+; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[P1_END4]], -4
+; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP11]], [[P1_START5]]
; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 2
; CHECK-NEXT: [[TMP7:%.*]] = shl nuw i64 [[TMP6]], 2
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 4
@@ -183,8 +183,8 @@ define void @store_pointer_induction(ptr %start, ptr %end) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START:%.*]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END:%.*]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[START2]], [[END1]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], -8
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
@@ -193,11 +193,11 @@ define void @store_pointer_induction(ptr %start, ptr %end) {
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 2
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
; CHECK-NEXT: [[TMP4:%.*]] = shl i64 [[N_VEC]], 3
-; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[END]], i64 [[TMP4]]
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[START]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ]
+; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi ptr [ [[END]], [[VECTOR_PH]] ], [ [[PTR_IND:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[POINTER_PHI]], <2 x i64> <i64 0, i64 8>
; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x ptr> [[TMP5]], i64 0
; CHECK-NEXT: store <2 x ptr> [[TMP5]], ptr [[TMP6]], align 4
@@ -209,13 +209,13 @@ define void @store_pointer_induction(ptr %start, ptr %end) {
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP7]], [[MIDDLE_BLOCK]] ], [ [[END]], [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: store ptr [[IV]], ptr [[IV]], align 4
; CHECK-NEXT: [[IV_NEXT]] = getelementptr inbounds ptr, ptr [[IV]], i32 1
-; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq ptr [[IV_NEXT]], [[END]]
+; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq ptr [[IV_NEXT]], [[START]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP17:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: ret void
diff --git a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
index 0bd18f3f90307..e154764f62092 100644
--- a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
@@ -8,10 +8,10 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16
define void @a(ptr readnone %b) {
; CHECK-LABEL: @a(
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[B1:%.*]] = ptrtoint ptr [[B:%.*]] to i64
-; CHECK-NEXT: [[CMP_NOT4:%.*]] = icmp eq ptr [[B]], null
+; CHECK-NEXT: [[CMP_NOT4:%.*]] = icmp eq ptr [[B:%.*]], null
; CHECK-NEXT: br i1 [[CMP_NOT4]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_PREHEADER:%.*]]
; CHECK: for.body.preheader:
+; CHECK-NEXT: [[B1:%.*]] = ptrtoint ptr [[B]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 0, [[B1]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
@@ -44,25 +44,25 @@ define void @a(ptr readnone %b) {
; CHECK: pred.store.continue:
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP7]], i64 1
; CHECK-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]]
-; CHECK: pred.store.if5:
+; CHECK: pred.store.if4:
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[NEXT_GEP2]], i64 -1
; CHECK-NEXT: store i8 95, ptr [[TMP12]], align 1
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE6]]
-; CHECK: pred.store.continue6:
+; CHECK: pred.store.continue5:
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP7]], i64 2
; CHECK-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]]
-; CHECK: pred.store.if7:
+; CHECK: pred.store.if6:
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[NEXT_GEP3]], i64 -1
; CHECK-NEXT: store i8 95, ptr [[TMP15]], align 1
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE8]]
-; CHECK: pred.store.continue8:
+; CHECK: pred.store.continue7:
; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i1> [[TMP7]], i64 3
; CHECK-NEXT: br i1 [[TMP16]], label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10]]
-; CHECK: pred.store.if9:
+; CHECK: pred.store.if8:
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i8, ptr [[NEXT_GEP4]], i64 -1
; CHECK-NEXT: store i8 95, ptr [[TMP18]], align 1
; CHECK-NEXT: br label [[PRED_STORE_CONTINUE10]]
-; CHECK: pred.store.continue10:
+; CHECK: pred.store.continue9:
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
diff --git a/llvm/test/Transforms/LoopVectorize/pr45259.ll b/llvm/test/Transforms/LoopVectorize/pr45259.ll
index ed45353c216b4..64724519a6c6b 100644
--- a/llvm/test/Transforms/LoopVectorize/pr45259.ll
+++ b/llvm/test/Transforms/LoopVectorize/pr45259.ll
@@ -15,10 +15,11 @@ define i8 @widget(ptr %arr, i8 %t9) {
; CHECK-NEXT: br i1 [[C]], label [[FOR_PREHEADER:%.*]], label [[BB6]]
; CHECK: for.preheader:
; CHECK-NEXT: [[T1_0_LCSSA1:%.*]] = phi ptr [ [[T1_0]], [[BB6]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[ARR1]] to i32
-; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[TMP0]]
-; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[T1_0_LCSSA2]] to i32
-; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARR]] to i64
+; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
+; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[T1_0]] to i64
+; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP2]] to i32
+; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP16]], [[TMP1]]
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP3]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
; CHECK: vector.scevcheck:
diff --git a/llvm/test/Transforms/LoopVectorize/predicate-switch.ll b/llvm/test/Transforms/LoopVectorize/predicate-switch.ll
index abb64bd1bf088..264baae35c0fe 100644
--- a/llvm/test/Transforms/LoopVectorize/predicate-switch.ll
+++ b/llvm/test/Transforms/LoopVectorize/predicate-switch.ll
@@ -6,8 +6,8 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; IC1-LABEL: define void @switch4_default_common_dest_with_case(
; IC1-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
; IC1-NEXT: [[ENTRY:.*]]:
-; IC1-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; IC1-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
+; IC1-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; IC1-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]
; IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
; IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
@@ -98,8 +98,8 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
; IC2-LABEL: define void @switch4_default_common_dest_with_case(
; IC2-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
; IC2-NEXT: [[ENTRY:.*]]:
-; IC2-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; IC2-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
+; IC2-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; IC2-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]
; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll b/llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
index 8a136a85bd8d3..2936444f1d0ff 100644
--- a/llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
+++ b/llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll
@@ -71,10 +71,10 @@ define void @widen_ptr_induction_dbg(ptr %start, ptr %end) {
; CHECK-LABEL: define void @widen_ptr_induction_dbg(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], -8
; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3
; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4
@@ -113,12 +113,12 @@ define void @widen_ptr_induction_dbg(ptr %start, ptr %end) {
; DEBUGLOC-LABEL: define void @widen_ptr_induction_dbg(
; DEBUGLOC-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) !dbg [[DBG29:![0-9]+]] {
; DEBUGLOC-NEXT: [[ENTRY:.*]]:
-; DEBUGLOC-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64, !dbg [[DBG34:![0-9]+]]
-; DEBUGLOC-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64, !dbg [[DBG34]]
-; DEBUGLOC-NEXT: [[TMP0:%.*]] = add i64 [[END1]], -8, !dbg [[DBG34]]
-; DEBUGLOC-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]], !dbg [[DBG34]]
-; DEBUGLOC-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3, !dbg [[DBG34]]
-; DEBUGLOC-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1, !dbg [[DBG34]]
+; DEBUGLOC-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[END]] to i64, !dbg [[DBG34:![0-9]+]]
+; DEBUGLOC-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[START]] to i64, !dbg [[DBG34]]
+; DEBUGLOC-NEXT: [[TMP2:%.*]] = sub i64 [[TMP0]], [[TMP1]], !dbg [[DBG34]]
+; DEBUGLOC-NEXT: [[TMP7:%.*]] = add i64 [[TMP2]], -8, !dbg [[DBG34]]
+; DEBUGLOC-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP7]], 3, !dbg [[DBG34]]
+; DEBUGLOC-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP8]], 1, !dbg [[DBG34]]
; DEBUGLOC-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 4, !dbg [[DBG34]]
; DEBUGLOC-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]], !dbg [[DBG34]]
; DEBUGLOC: [[VECTOR_PH]]:
@@ -135,8 +135,8 @@ define void @widen_ptr_induction_dbg(ptr %start, ptr %end) {
; DEBUGLOC-NEXT: store <4 x ptr> [[VECTOR_GEP]], ptr [[TMP6]], align 1, !dbg [[DBG36:![0-9]+]]
; DEBUGLOC-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; DEBUGLOC-NEXT: [[PTR_IND]] = getelementptr i8, ptr [[POINTER_PHI]], i64 32, !dbg [[DBG35]]
-; DEBUGLOC-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]], !dbg [[DBG37:![0-9]+]]
-; DEBUGLOC-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !dbg [[DBG37]], !llvm.loop [[LOOP38:![0-9]+]]
+; DEBUGLOC-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]], !dbg [[DBG37:![0-9]+]]
+; DEBUGLOC-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !dbg [[DBG37]], !llvm.loop [[LOOP38:![0-9]+]]
; DEBUGLOC: [[MIDDLE_BLOCK]]:
; DEBUGLOC-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]], !dbg [[DBG37]]
; DEBUGLOC-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]], !dbg [[DBG37]]
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll b/llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
index 98c80065c792b..b5be50e8c7b45 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll
@@ -11,9 +11,10 @@ define void @test_runtime_check_known_false_after_construction(ptr %start.1, ptr
; CHECK-NEXT: [[START_2_INT:%.*]] = ptrtoint ptr [[GEP_START_2]] to i64
; CHECK-NEXT: [[DIFF:%.*]] = sub i64 [[START_1_INT]], [[START_2_INT]]
; CHECK-NEXT: [[START_2_DIFF:%.*]] = getelementptr i8, ptr [[START_2]], i64 [[DIFF]]
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 8
+; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[END]] to i64
; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START_1_INT]]
-; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 2305843009213693951
+; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP1]], 8
+; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP12]], 2305843009213693951
; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 4
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll b/llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
index cd7af0e94ab15..852a5b10d6067 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll
@@ -77,11 +77,11 @@ define void @diff_memcheck_known_false_for_vf_4(ptr %B, ptr %A, ptr %end) {
; CHECK-LABEL: define void @diff_memcheck_known_false_for_vf_4(
; CHECK-SAME: ptr [[B:%.*]], ptr [[A:%.*]], ptr [[END:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
; CHECK-NEXT: [[A_INT:%.*]] = ptrtoint ptr [[A]] to i64
; CHECK-NEXT: [[B_CAST:%.*]] = ptrtoint ptr [[B]] to i64
; CHECK-NEXT: [[PTR_SUB:%.*]] = sub i64 [[A_INT]], [[B_CAST]]
; CHECK-NEXT: [[ADD_PTR11:%.*]] = getelementptr i8, ptr [[B]], i64 [[PTR_SUB]]
+; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[A_INT]], [[END1]]
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll b/llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
index 5cf72a642147c..6d2b0a42298b9 100644
--- a/llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
+++ b/llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll
@@ -122,14 +122,14 @@ define void @implied_wrap_predicate(ptr %A, ptr %B, ptr %C) {
; CHECK-LABEL: define void @implied_wrap_predicate(
; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[A3:%.*]] = ptrtoint ptr [[A]] to i64
; CHECK-NEXT: [[C2:%.*]] = ptrtoaddr ptr [[C]] to i64
; CHECK-NEXT: [[A1:%.*]] = ptrtoint ptr [[A]] to i64
+; CHECK-NEXT: [[A3:%.*]] = ptrtoint ptr [[A]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[A3]], 16
-; CHECK-NEXT: [[UMAX4:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 add (i64 ptrtoint (ptr @h to i64), i64 1))
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[UMAX4]], -9
+; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP0]], i64 add (i64 ptrtoint (ptr @h to i64), i64 1))
; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[A3]]
-; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3
+; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP2]], -9
+; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP20]], 3
; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
@@ -147,8 +147,8 @@ define void @implied_wrap_predicate(ptr %A, ptr %B, ptr %C) {
; CHECK-NEXT: br i1 [[TMP13]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
; CHECK-NEXT: [[TMP14:%.*]] = sub i64 [[C2]], [[A1]]
-; CHECK-NEXT: [[TMP20:%.*]] = sub i64 [[TMP14]], 1
-; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP20]], 31
+; CHECK-NEXT: [[TMP21:%.*]] = sub i64 [[TMP14]], 1
+; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP21]], 31
; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP4]], 4
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