[llvm] [VPlan] Expand SCEV ptrtoint/ptrtoaddr casts in VPSCEVExpander. (PR #209172)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 13 06:11:36 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-vectorizers
Author: Florian Hahn (fhahn)
<details>
<summary>Changes</summary>
Extend the cast handling in VPSCEVExpander::tryToExpand to also expand scPtrToInt and scPtrToAddr SCEV expressions to PtrToInt/PtrToAddr VPInstructions.
This allows pointer-distance expressions (e.g. the runtime-check difference between two pointers, which contains ptrtoint of each pointer) to be expanded directly to VPInstructions instead of falling back to a VPExpandSCEVRecipe.
---
Patch is 118.85 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/209172.diff
42 Files Affected:
- (modified) llvm/lib/Transforms/Vectorize/VPlanUtils.cpp (+9-1)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll (+4-4)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll (+3-3)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll (+8-8)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll (+21-21)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll (+3-3)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll (+5-5)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs-apple.ll (+7-6)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/replicating-load-store-costs.ll (+7-6)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/sve-live-out-pointer-induction.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/AArch64/transform-narrow-interleave-to-widen-memory-derived-ivs.ll (+9-9)
- (modified) llvm/test/Transforms/LoopVectorize/PowerPC/pr41179.ll (+8-8)
- (modified) llvm/test/Transforms/LoopVectorize/RISCV/pointer-induction.ll (+8-8)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/AArch64/vplan-printing-alias-mask.ll (+15-15)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll (+4-5)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/vplan-predicate-switch.ll (+29-30)
- (modified) llvm/test/Transforms/LoopVectorize/VPlan/vplan-printing-alias-mask.ll (+22-22)
- (modified) llvm/test/Transforms/LoopVectorize/WebAssembly/induction-branch-cost.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/cost-model.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/X86/fold-tail-low-trip-count.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/interleave-opaque-pointers.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/optsize.ll (+6-6)
- (modified) llvm/test/Transforms/LoopVectorize/X86/pr48340.ll (+12-12)
- (modified) llvm/test/Transforms/LoopVectorize/X86/pr72969.ll (+5-4)
- (modified) llvm/test/Transforms/LoopVectorize/X86/predicate-switch.ll (+36-36)
- (modified) llvm/test/Transforms/LoopVectorize/alias-mask-data-tail-folding-style.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/alias-mask-needs-freeze.ll (+4-5)
- (modified) llvm/test/Transforms/LoopVectorize/alias-mask-small-index.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/alias-mask.ll (+10-10)
- (modified) llvm/test/Transforms/LoopVectorize/hoist-and-sink-mem-ops-with-invariant-pointers.ll (+7-7)
- (modified) llvm/test/Transforms/LoopVectorize/interleaved-accesses-different-insert-position.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/interleaved-accesses-metadata.ll (+8-8)
- (modified) llvm/test/Transforms/LoopVectorize/metadata.ll (+8-8)
- (modified) llvm/test/Transforms/LoopVectorize/opaque-ptr.ll (+18-18)
- (modified) llvm/test/Transforms/LoopVectorize/pointer-induction.ll (+8-8)
- (modified) llvm/test/Transforms/LoopVectorize/pr45259.ll (+5-4)
- (modified) llvm/test/Transforms/LoopVectorize/predicate-switch.ll (+2-2)
- (modified) llvm/test/Transforms/LoopVectorize/preserve-dbg-loc-and-loop-metadata.ll (+11-11)
- (modified) llvm/test/Transforms/LoopVectorize/runtime-check-known-true.ll (+3-2)
- (modified) llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll (+1-1)
- (modified) llvm/test/Transforms/LoopVectorize/scev-predicate-reasoning.ll (+6-6)
``````````diff
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index 7b4ffce87434c..03e1ead89c169 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -821,7 +821,9 @@ VPValue *VPSCEVExpander::tryToExpand(const SCEV *S) {
}
case scTruncate:
case scZeroExtend:
- case scSignExtend: {
+ case scSignExtend:
+ case scPtrToInt:
+ case scPtrToAddr: {
auto *Cast = cast<SCEVCastExpr>(S);
VPValue *Op = tryToExpand(Cast->getOperand());
if (!Op)
@@ -837,6 +839,12 @@ VPValue *VPSCEVExpander::tryToExpand(const SCEV *S) {
case scSignExtend:
Opcode = Instruction::SExt;
break;
+ case scPtrToInt:
+ Opcode = Instruction::PtrToInt;
+ break;
+ case scPtrToAddr:
+ Opcode = Instruction::PtrToAddr;
+ break;
default:
llvm_unreachable("Unhandled cast SCEV");
}
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll b/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
index 3eaf4c4b1b3f4..a9a91519e7d32 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/aggressive-interleaving.ll
@@ -17,16 +17,16 @@ define void @test_interleave_reduction(ptr %arg, ptr %arg1) {
; A320: [[OUTER]]:
; A320-NEXT: [[TPM26:%.*]] = add i64 0, 1
; A320-NEXT: [[TPM10:%.*]] = alloca i32, align 8
-; A320-NEXT: [[TPM102:%.*]] = ptrtoint ptr [[TPM10]] to i64
; A320-NEXT: [[TPM27:%.*]] = getelementptr inbounds i32, ptr [[TPM10]], i64 [[TPM26]]
; A320-NEXT: [[TPM28:%.*]] = getelementptr inbounds ptr, ptr [[TPM15]], i64 0
; A320-NEXT: [[TPM29:%.*]] = load ptr, ptr [[TPM28]], align 8
-; A320-NEXT: [[TPM291:%.*]] = ptrtoint ptr [[TPM29]] to i64
; A320-NEXT: [[TPM17:%.*]] = alloca double, align 8
; A320-NEXT: [[TPM32:%.*]] = getelementptr inbounds double, ptr [[TPM17]], i64 [[TPM26]]
-; A320-NEXT: [[TMP0:%.*]] = add i64 [[TPM291]], -8
+; A320-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[TPM29]] to i64
+; A320-NEXT: [[TPM102:%.*]] = ptrtoint ptr [[TPM10]] to i64
; A320-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[TPM102]]
-; A320-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 2
+; A320-NEXT: [[TMP6:%.*]] = add i64 [[TMP1]], -8
+; A320-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP6]], 2
; A320-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
; A320-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
; A320-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll b/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
index a311167615532..d3539eaa9e380 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask-uniforms.ll
@@ -7,8 +7,8 @@ define void @vf_dependent_uniform(ptr noalias %p, ptr %p.out, ptr %p.in, i64 %n)
; CHECK-LABEL: define void @vf_dependent_uniform(
; CHECK-SAME: ptr noalias [[P:%.*]], ptr [[P_OUT:%.*]], ptr [[P_IN:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[P_OUT1:%.*]] = ptrtoaddr ptr [[P_OUT]] to i64
+; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 1)
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
@@ -114,8 +114,8 @@ define void @uniform_load(ptr noalias %p, ptr %p.out, ptr %p.in, i64 %n) {
; CHECK-LABEL: define void @uniform_load(
; CHECK-SAME: ptr noalias [[P:%.*]], ptr [[P_OUT:%.*]], ptr [[P_IN:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[P_OUT1:%.*]] = ptrtoaddr ptr [[P_OUT]] to i64
+; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 1)
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
@@ -181,8 +181,8 @@ define void @uniform_store(ptr noalias %p, ptr %p.out, ptr %p.in, i64 %n) {
; CHECK-LABEL: define void @uniform_store(
; CHECK-SAME: ptr noalias [[P:%.*]], ptr [[P_OUT:%.*]], ptr [[P_IN:%.*]], i64 [[N:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[P_OUT1:%.*]] = ptrtoaddr ptr [[P_OUT]] to i64
+; CHECK-NEXT: [[P_IN2:%.*]] = ptrtoaddr ptr [[P_IN]] to i64
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 1)
; CHECK-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK: [[VECTOR_CLAMPED_VF_CHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll b/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
index 15a9e8d5aa4c0..87bdd1f975423 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/alias-mask.ll
@@ -5,8 +5,8 @@ define void @alias_mask(ptr noalias %a, ptr %b, ptr %c, i64 %n) {
; CHECK-TF-LABEL: define void @alias_mask(
; CHECK-TF-SAME: ptr noalias [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-TF-NEXT: [[ENTRY:.*:]]
-; CHECK-TF-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-TF-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
+; CHECK-TF-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-TF-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK-TF: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-TF-NEXT: [[ALIAS_MASK:%.*]] = call <vscale x 16 x i1> @llvm.loop.dependence.war.mask.nxv16i1.i64(i64 [[B2]], i64 [[C1]], i64 1)
@@ -65,9 +65,9 @@ define void @alias_mask_multiple(ptr %a, ptr %b, ptr %c, i64 %n) {
; CHECK-TF-LABEL: define void @alias_mask_multiple(
; CHECK-TF-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
; CHECK-TF-NEXT: [[ENTRY:.*:]]
-; CHECK-TF-NEXT: [[A3:%.*]] = ptrtoaddr ptr [[A]] to i64
-; CHECK-TF-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
; CHECK-TF-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
+; CHECK-TF-NEXT: [[B2:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-TF-NEXT: [[A3:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-TF-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK-TF: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-TF-NEXT: [[TMP2:%.*]] = call <vscale x 16 x i1> @llvm.loop.dependence.war.mask.nxv16i1.i64(i64 [[A3]], i64 [[C1]], i64 1)
@@ -130,8 +130,8 @@ define i8 @alias_masking_exit_value(ptr %ptrA, ptr %ptrB) {
; CHECK-TF-LABEL: define i8 @alias_masking_exit_value(
; CHECK-TF-SAME: ptr [[PTRA:%.*]], ptr [[PTRB:%.*]]) #[[ATTR0]] {
; CHECK-TF-NEXT: [[ENTRY:.*:]]
-; CHECK-TF-NEXT: [[PTRA2:%.*]] = ptrtoaddr ptr [[PTRA]] to i64
; CHECK-TF-NEXT: [[PTRB1:%.*]] = ptrtoaddr ptr [[PTRB]] to i64
+; CHECK-TF-NEXT: [[PTRA2:%.*]] = ptrtoaddr ptr [[PTRA]] to i64
; CHECK-TF-NEXT: br label %[[VECTOR_CLAMPED_VF_CHECK:.*]]
; CHECK-TF: [[VECTOR_CLAMPED_VF_CHECK]]:
; CHECK-TF-NEXT: [[ALIAS_MASK:%.*]] = call <vscale x 16 x i1> @llvm.loop.dependence.war.mask.nxv16i1.i64(i64 [[PTRA2]], i64 [[PTRB1]], i64 1)
@@ -197,8 +197,8 @@ define i32 @partial_reduce(ptr %a, ptr %b, i64 %n) {
; CHECK-TF-LABEL: define i32 @partial_reduce(
; CHECK-TF-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[N:%.*]]) #[[ATTR0]] {
; CHECK-TF-NEXT: [[ENTRY:.*:]]
-; CHECK-TF-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-TF-NEXT: [[B1:%.*]] = ptrtoaddr ptr [[B]] to i64
+; CHECK-TF-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; CHECK-TF-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK-TF: [[VECTOR_PH]]:
; CHECK-TF-NEXT: [[ALIAS_MASK:%.*]] = call <vscale x 16 x i1> @llvm.loop.dependence.war.mask.nxv16i1.i64(i64 [[A2]], i64 [[B1]], i64 1)
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
index b49e1aa5b4e46..5e68b6d6c748e 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
@@ -99,8 +99,8 @@ define i64 @pointer_induction_only(ptr %start, ptr %end) {
; CHECK-LABEL: define i64 @pointer_induction_only(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
+; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]]
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2
; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
@@ -435,16 +435,16 @@ define i32 @load_from_pointer_induction(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @load_from_pointer_induction(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[END1]], i64 [[START2]])
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], 1
+; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.umax.i64(i64 [[END1]], i64 [[START2]])
; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
+; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[TMP1]], 1
+; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP20]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]]
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP20]], 4
+; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP20]], [[N_MOD_VF]]
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]]
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
@@ -479,7 +479,7 @@ define i32 @load_from_pointer_induction(ptr %start, ptr %end) {
; CHECK-NEXT: [[BIN_RDX:%.*]] = or i32 [[TMP9]], [[TMP8]]
; CHECK-NEXT: [[BIN_RDX9:%.*]] = or i32 [[TMP16]], [[BIN_RDX]]
; CHECK-NEXT: [[BIN_RDX10:%.*]] = or i32 [[TMP17]], [[BIN_RDX9]]
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]]
+; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP20]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
index ba00cb0c543fd..94f98343421bc 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-constant-ops.ll
@@ -7,10 +7,10 @@ define i32 @red_zext_mul_by_63(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_zext_mul_by_63(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP7]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -73,10 +73,10 @@ define i32 @red_zext_mul_by_255(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_zext_mul_by_255(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP5]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -139,10 +139,10 @@ define i32 @red_zext_mul_by_256(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_zext_mul_by_256(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -205,10 +205,10 @@ define i32 @red_sext_mul_by_63(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_sext_mul_by_63(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP8:%.*]] = sub i64 [[END1]], [[TMP7]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP8]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -273,10 +273,10 @@ define i32 @red_sext_mul_by_128(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_sext_mul_by_128(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -340,10 +340,10 @@ define i32 @red_sext_mul_by_255(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_sext_mul_by_255(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
@@ -406,10 +406,10 @@ define i32 @red_sext_mul_by_256(ptr %start, ptr %end) {
; CHECK-LABEL: define i32 @red_sext_mul_by_256(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
index 9e4b3b5a921e5..00e9fb2f7dc43 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/partial-reduce-incomplete-chains.ll
@@ -7,10 +7,10 @@ define i32 @red_extended_add_incomplete_chain(ptr %start, ptr %end, i32 %offset)
; CHECK-LABEL: define i32 @red_extended_add_incomplete_chain(
; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]], i32 [[OFFSET:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64
; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END1]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]]
+; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[START]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = sub i64 [[END1]], [[TMP8]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP9]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
index 0065ecdec0112..230a9d7325bc5 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-cost.ll
@@ -112,22 +112,22 @@ define i32 @or_reduction_with_freeze(ptr %dst, ptr %src) {
; CHECK-NEXT: [[DST6:%.*]] = ptrtoint ptr [[DST]] to i64
; CHECK-NEXT: [[SRC4:%.*]] = ptrtoint ptr [[SRC]] to i64
; CHECK-NEXT: [[DST3:%.*]] = ptrtoint ptr [[DST]] to i64
-; CHECK-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64
; CHECK-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[DST6]], [[SRC7]]
+; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[SRC]] to i64
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[DST1]], [[TMP11]]
; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 3
; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 10
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
-; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[DST1]] to i3
-; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[SRC2]] to i3
+; CHECK-NEXT: [[TMP3:%.*]] = trunc i64 [[DST3]] to i3
+; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[SRC4]] to i3
; CHECK-NEXT: [[TMP5:%.*]] = sub i3 [[TMP3]], [[TMP4]]
; CHECK-NEXT: [[TMP6:%.*]] = zext i3 [[TMP5]] to i64
; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i64 [[TMP6]], 0
; CHECK-NEXT: br i1 [[IDENT_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
-; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[DST3]], [[SRC4]]
+; CHECK-NEXT: [[TMP7:%.*]] = sub i64 [[DST6]], [[SRC7]]
; CHECK-NEXT: [[TMP8:%.*]] = lshr i64 [[TMP7]], 3
; CHECK-NEXT: [[TMP9:%.*]] = shl nuw i64 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 8
diff --gi...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/209172
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