[llvm] [SPARC] Don't combine misaligned memory ops with BSWAP (PR #206345)

[Sergei Barannikov via llvm-commits]

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@@ -3300,10 +3304,15 @@ SDValue SparcTargetLowering::PerformSTORECombine(SDNode *N,
   SDValue Op = N->getOperand(1);
   EVT VT = Op.getValueType();
   unsigned Opcode = Op.getOpcode();
+  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
+  StoreSDNode *SN = dyn_cast<StoreSDNode>(N);
+
   bool IsLittleEndian = DAG.getDataLayout().isLittleEndian();
+  bool IsAlignedStore = SN && SN->getAlign() >= VT.getScalarStoreSize();
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s-barannikov wrote:

It looks like truncating stores are supported? Should this compare to MemVT size?

https://github.com/llvm/llvm-project/pull/206345