[llvm] [AMDGPU] Add post-RA peephole to fuse v_lshlrev_b32 + v_or_b32 into v_lshl_or_b32 (PR #202585)
Barbara Mitic via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 11 08:14:19 PDT 2026
https://github.com/barbara-amd updated https://github.com/llvm/llvm-project/pull/202585
>From 29148f8273e3447b2d73ab7475c3cc0119ad89a7 Mon Sep 17 00:00:00 2001
From: Barbara Mitic <Barbara.Mitic at amd.com>
Date: Tue, 2 Jun 2026 11:42:39 +0200
Subject: [PATCH 1/3] [AMDGPU] Add post-RA peephole to fuse v_lshlrev_b32 +
v_or_b32 into v_lshl_or_b32
Add a post-RA peephole in SIShrinkInstructions that fuses v_lshlrev_b32 +
v_or_b32 into v_lshl_or_b32 when the shift result has a single use.
Existing TableGen patterns for this fusion rarely fire because they rely on
conservative SelectionDAG-level analysis. The HasOneUseBinOp predicate rejects
cases where the shift has multiple DAG-level uses but only one after register
allocation. Constant-bus and divergence checks are similarly conservative
without final register classes.
This post-RA implementation solves these issues by operating on complete
allocation information. It verifies single-use through kill flags
(with a computeRegisterLiveness scan fallback), validates operands using
isOperandLegal() for proper constant-bus checking with SGPR deduplication,
and handles VOP3 literal constraints correctly.
The peephole follows the matchSwap pattern: search forward (max 16 instructions),
check hazards and liveness, build the fused instruction, validate all operands,
and erase originals on success. Running in addPreSched2() lets the scheduler
see the fused instruction while preserving other SIShrinkInstructions optimizations.
---
.../Target/AMDGPU/SIShrinkInstructions.cpp | 154 +
.../CodeGen/AMDGPU/GlobalISel/add.v2i16.ll | 6 +-
.../AMDGPU/GlobalISel/atomic_load_flat.ll | 3 +-
.../AMDGPU/GlobalISel/atomic_load_global.ll | 3 +-
.../AMDGPU/GlobalISel/atomic_load_local_2.ll | 3 +-
.../AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 10 +-
.../CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll | 122 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll | 25 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 39 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 35 +-
.../test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 14 +-
.../CodeGen/AMDGPU/GlobalISel/sext_inreg.ll | 3 +-
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 14 +-
.../AMDGPU/GlobalISel/strict_fma.f16.ll | 16 +-
.../test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll | 5 +-
.../test/CodeGen/AMDGPU/GlobalISel/usubsat.ll | 5 +-
.../abi-attribute-hints-undefined-behavior.ll | 9 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 9914 +++++++----------
.../CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll | 528 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 1338 +--
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 2394 ++--
.../CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll | 167 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 4733 ++++----
.../CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll | 444 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 497 +-
.../AMDGPU/amdgpu-codegenprepare-idiv.ll | 26 +-
.../atomic_optimizations_global_pointer.ll | 5 +-
...tor-flatscratchinit-undefined-behavior2.ll | 12 +-
.../buffer-fat-pointer-atomicrmw-fadd.ll | 13 +-
.../buffer-fat-pointer-atomicrmw-fmax.ll | 13 +-
.../buffer-fat-pointer-atomicrmw-fmin.ll | 13 +-
.../CodeGen/AMDGPU/calling-conventions.ll | 25 +-
llvm/test/CodeGen/AMDGPU/cc-update.ll | 12 +-
llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll | 22 +-
.../AMDGPU/copysign-to-disjoint-or-combine.ll | 3 +-
llvm/test/CodeGen/AMDGPU/ctlz.ll | 4 +-
llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll | 12 +-
llvm/test/CodeGen/AMDGPU/ctpop16.ll | 162 +-
llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll | 32 +-
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 3 +-
llvm/test/CodeGen/AMDGPU/ds_read2.ll | 6 +-
.../test/CodeGen/AMDGPU/extract-i8-codegen.ll | 8 +-
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll | 14 +-
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 53 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fadd.ll | 40 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmax.ll | 40 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmin.ll | 40 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fsub.ll | 40 +-
llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll | 31 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 84 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 171 +-
llvm/test/CodeGen/AMDGPU/function-args.ll | 234 +-
.../CodeGen/AMDGPU/global-atomicrmw-fadd.ll | 40 +-
.../CodeGen/AMDGPU/global-atomicrmw-fmax.ll | 40 +-
.../CodeGen/AMDGPU/global-atomicrmw-fmin.ll | 40 +-
.../CodeGen/AMDGPU/global-atomicrmw-fsub.ll | 40 +-
llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll | 8 +-
llvm/test/CodeGen/AMDGPU/idot4u.ll | 7 +-
.../CodeGen/AMDGPU/integer-mad-patterns.ll | 124 +-
llvm/test/CodeGen/AMDGPU/itofp.i128.ll | 8 +-
llvm/test/CodeGen/AMDGPU/kernel-args.ll | 3 +-
.../CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll | 3 +-
llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll | 18 +-
llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll | 6 +-
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll | 31 +-
llvm/test/CodeGen/AMDGPU/load-global-i16.ll | 7 +-
llvm/test/CodeGen/AMDGPU/load-hi16.ll | 28 +-
llvm/test/CodeGen/AMDGPU/load-lo16.ll | 18 +-
.../CodeGen/AMDGPU/local-atomicrmw-fadd.ll | 20 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmax.ll | 20 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmin.ll | 20 +-
.../CodeGen/AMDGPU/local-atomicrmw-fsub.ll | 20 +-
...ne-sink-temporal-divergence-swdev407790.ll | 17 +-
.../CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll | 86 +-
llvm/test/CodeGen/AMDGPU/pack.v2i16.ll | 3 +-
llvm/test/CodeGen/AMDGPU/permute_i8.ll | 40 +-
.../promote-constOffset-to-imm-gfx12.mir | 12 +-
.../AMDGPU/reassoc-mul-add-1-to-mad.ll | 24 +-
llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 8 +-
llvm/test/CodeGen/AMDGPU/sdiv.ll | 28 +-
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll | 103 +-
.../AMDGPU/select-fabs-fneg-extract.v2f16.ll | 6 +-
llvm/test/CodeGen/AMDGPU/shl.ll | 3 +-
llvm/test/CodeGen/AMDGPU/shl_or.ll | 18 +-
.../CodeGen/AMDGPU/shrink-add-sub-constant.ll | 15 +-
llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll | 10 +-
.../splitkit-getsubrangeformask-phi-extend.ll | 262 +-
llvm/test/CodeGen/AMDGPU/stack-realign.ll | 9 +-
llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll | 3 +-
llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll | 17 +-
llvm/test/CodeGen/AMDGPU/trunc-store.ll | 56 +-
llvm/test/CodeGen/AMDGPU/udiv.ll | 46 +-
llvm/test/CodeGen/AMDGPU/v_lshl_or_b32.mir | 131 +
.../AMDGPU/v_mac_f16-fpdp-rounding-mode.ll | 3 +-
llvm/test/CodeGen/AMDGPU/v_mac_f16.ll | 3 +-
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 3 +-
.../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 24 +-
.../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 24 +-
.../test/CodeGen/AMDGPU/vector-reduce-umax.ll | 24 +-
.../test/CodeGen/AMDGPU/vni8-across-blocks.ll | 11 +-
100 files changed, 9520 insertions(+), 13569 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/v_lshl_or_b32.mir
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index d1ed1831cfbec..85765df01d4b2 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -58,6 +58,7 @@ class SIShrinkInstructions {
unsigned I) const;
void dropInstructionKeepingImpDefs(MachineInstr &MI) const;
MachineInstr *matchSwap(MachineInstr &MovT) const;
+ MachineInstr *matchLshlOr(MachineInstr &Shift) const;
public:
SIShrinkInstructions() = default;
@@ -850,6 +851,147 @@ MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
return nullptr;
}
+// Fuse v_lshlrev_b32 vDst, vAmt, vSrc + v_or_b32 vRes, vDst, vOther
+// into v_lshl_or_b32 vRes, vSrc, vAmt, vOther (GFX9+).
+// Requires the shift result to be dead after the or and the combined operand
+// list to satisfy the V_LSHL_OR_B32 constant-bus / literal-encoding rules.
+// Complements the SDAG ThreeOpFrag cshl_32+or pattern, which is blocked by
+// HasOneUseBinOp when the shift's DAG node has other consumers.
+MachineInstr *SIShrinkInstructions::matchLshlOr(MachineInstr &Shift) const {
+ if (TII->pseudoToMCOpcode(AMDGPU::V_LSHL_OR_B32_e64) == -1)
+ return nullptr;
+
+ assert(Shift.getOpcode() == AMDGPU::V_LSHLREV_B32_e32 ||
+ Shift.getOpcode() == AMDGPU::V_LSHLREV_B32_e64);
+
+ // V_LSHLREV / V_OR layout: 0 = vdst, 1 = src0, 2 = src1.
+ MachineOperand *ShDst = &Shift.getOperand(0);
+ MachineOperand *ShAmt = &Shift.getOperand(1);
+ MachineOperand *ShVal = &Shift.getOperand(2);
+ if (!ShDst->isReg())
+ return nullptr;
+
+ Register ShDstReg = ShDst->getReg();
+ unsigned ShDstSub = ShDst->getSubReg();
+
+ if (!TRI->isVGPR(*MRI, ShDstReg))
+ return nullptr;
+
+ // Search up to 16 instructions forward for the OR. Limit prevents
+ // unbounded scans while covering the vast majority of fusion opportunities.
+ // Matches the search window used in matchSwap.
+ const unsigned SearchLimit = 16;
+ unsigned Count = 0;
+
+ for (auto Iter = std::next(Shift.getIterator()),
+ E = Shift.getParent()->instr_end();
+ Iter != E && Count < SearchLimit; ++Iter) {
+ if (Iter->isDebugInstr())
+ continue;
+ ++Count;
+
+ bool IsOr = (Iter->getOpcode() == AMDGPU::V_OR_B32_e32 ||
+ Iter->getOpcode() == AMDGPU::V_OR_B32_e64);
+
+ if (!IsOr) {
+ // Reject intervening hazards.
+ if (instReadsReg(&*Iter, ShDstReg, ShDstSub) ||
+ instModifiesReg(&*Iter, ShDstReg, ShDstSub))
+ return nullptr;
+ if (ShVal->isReg() && Iter->modifiesRegister(ShVal->getReg(), TRI))
+ return nullptr;
+ if (ShAmt->isReg() && Iter->modifiesRegister(ShAmt->getReg(), TRI))
+ return nullptr;
+ continue;
+ }
+ if (Iter->getNumExplicitOperands() < 3)
+ return nullptr;
+ MachineOperand *OrDst = &Iter->getOperand(0);
+ MachineOperand *OrSrc0 = &Iter->getOperand(1);
+ MachineOperand *OrSrc1 = &Iter->getOperand(2);
+ if (!OrDst->isReg())
+ return nullptr;
+
+ if (!TRI->isVGPR(*MRI, OrDst->getReg()))
+ return nullptr;
+
+ // Find which OR source uses the shift result (commutative).
+ MachineOperand *KillUse;
+ MachineOperand *Other;
+ if (OrSrc0->isReg() && OrSrc0->getReg() == ShDstReg &&
+ OrSrc0->getSubReg() == ShDstSub) {
+ KillUse = OrSrc0;
+ Other = OrSrc1;
+ } else if (OrSrc1->isReg() && OrSrc1->getReg() == ShDstReg &&
+ OrSrc1->getSubReg() == ShDstSub) {
+ KillUse = OrSrc1;
+ Other = OrSrc0;
+ } else {
+ return nullptr;
+ }
+
+ // The other operand can't be the shift result itself (e.g. "or x, x"):
+ // fusion deletes the shift, leaving it undefined.
+ if (Other->isReg() && TRI->regsOverlap(Other->getReg(), ShDstReg))
+ return nullptr;
+
+ // Fusion deletes the shift, so its result must be dead after the OR. Trust
+ // a kill flag; otherwise query liveness just past the OR (catches later
+ // reads, read-modify uses, and live-out).
+ if (!KillUse->isKill()) {
+ if (ShDstSub != 0)
+ return nullptr;
+ MachineBasicBlock::iterator AfterOr =
+ std::next(MachineBasicBlock::iterator(*Iter));
+ MachineBasicBlock::LivenessQueryResult LQR =
+ Iter->getParent()->computeRegisterLiveness(TRI, ShDstReg, AfterOr,
+ /*Neighborhood=*/16);
+ if (LQR != MachineBasicBlock::LQR_Dead)
+ return nullptr;
+ }
+
+ LLVM_DEBUG(dbgs() << "Matched v_lshl_or:\n" << Shift << *Iter);
+
+ // Build the fused instruction and validate all operands are legal
+ // (constant-bus limits, VOP3 literal constraints, register classes). Bail
+ // if illegal.
+ MachineBasicBlock &MBB = *Iter->getParent();
+ MachineInstrBuilder MIB =
+ BuildMI(MBB, Iter->getIterator(), Iter->getDebugLoc(),
+ TII->get(AMDGPU::V_LSHL_OR_B32_e64))
+ .addReg(OrDst->getReg(), RegState::Define, OrDst->getSubReg());
+ MIB.add(*ShVal);
+ MIB.add(*ShAmt);
+ MIB.add(*Other);
+ MachineInstr *NewMI = MIB.getInstr();
+
+ const int SrcIdx[] = {AMDGPU::getNamedOperandIdx(AMDGPU::V_LSHL_OR_B32_e64,
+ AMDGPU::OpName::src0),
+ AMDGPU::getNamedOperandIdx(AMDGPU::V_LSHL_OR_B32_e64,
+ AMDGPU::OpName::src1),
+ AMDGPU::getNamedOperandIdx(AMDGPU::V_LSHL_OR_B32_e64,
+ AMDGPU::OpName::src2)};
+ for (int Idx : SrcIdx) {
+ if (Idx < 0 || !TII->isOperandLegal(*NewMI, Idx)) {
+ NewMI->eraseFromParent();
+ return nullptr;
+ }
+ }
+
+ auto ResumeIt = std::next(Shift.getIterator());
+ // Resume from the newly created instruction if Shift and OR were adjacent;
+ // otherwise continue from the instruction after the Shift.
+ MachineInstr *Next =
+ (ResumeIt != MBB.end() && &*ResumeIt == &*Iter) ? NewMI : &*ResumeIt;
+
+ Iter->eraseFromParent();
+ Shift.eraseFromParent();
+ return Next;
+ }
+
+ return nullptr;
+}
+
// If an instruction has dead sdst replace it with NULL register on gfx1030+
bool SIShrinkInstructions::tryReplaceDeadSDST(MachineInstr &MI) const {
if (!ST->hasGFX10_3Insts())
@@ -916,6 +1058,18 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
}
}
+ // Fuse v_lshlrev_b32 + v_or_b32 into v_lshl_or_b32. Post-RA only:
+ // earlier passes / SDAG patterns get first crack pre-RA, and post-RA
+ // we have accurate kill flags and final register classes.
+ if (IsPostRA && (MI.getOpcode() == AMDGPU::V_LSHLREV_B32_e32 ||
+ MI.getOpcode() == AMDGPU::V_LSHLREV_B32_e64)) {
+ if (auto *NextMI = matchLshlOr(MI)) {
+ Next = NextMI->getIterator();
+ Changed = true;
+ continue;
+ }
+ }
+
// Shrink scalar logic operations.
if (MI.getOpcode() == AMDGPU::S_AND_B32 ||
MI.getOpcode() == AMDGPU::S_OR_B32 ||
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
index b65f71ab20b1a..d9f3be3966832 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
@@ -673,8 +673,7 @@ define <2 x i16> @add_inline_imm_neg1_0(<2 x i16> %x) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-NEXT: v_add_u16_e32 v0, -1, v0
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: add_inline_imm_neg1_0:
@@ -708,8 +707,7 @@ define <2 x i16> @add_inline_imm_1_0(<2 x i16> %x) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-NEXT: v_add_u16_e32 v0, 1, v0
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: add_inline_imm_1_0:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
index a28b217607eec..34ab5a3a1502f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
@@ -209,9 +209,8 @@ define i32 @atomic_load_flat_monotonic_i16_d16_lo_or(ptr %ptr, i16 %high) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_flat_monotonic_i16_d16_lo_or:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
index 2be9e29530ace..c2d857a2c8656 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
@@ -551,9 +551,8 @@ define i32 @atomic_load_global_monotonic_i16_d16_lo_or(ptr addrspace(1) %ptr, i1
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_global_monotonic_i16_d16_lo_or:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
index 08be9df3e5c5c..0b4284c8d4896 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
@@ -424,9 +424,8 @@ define i32 @atomic_load_local_monotonic_i16_d16_lo_or(ptr addrspace(3) %ptr, i16
; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: ds_read_u16 v0, v0
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_local_monotonic_i16_d16_lo_or:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
index de586a5921724..9433e3fda3c4d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
@@ -795,15 +795,13 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
; VI-NEXT: v_add_u16_e32 v8, 9, v8
-; VI-NEXT: v_and_b32_e32 v10, 0xff, v10
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
-; VI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; VI-NEXT: v_and_b32_e32 v10, 0xff, v10
; VI-NEXT: v_lshlrev_b32_sdwa v0, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v10
; VI-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v2, 24, v6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v2, v0, v2
+; VI-NEXT: v_and_b32_e32 v6, 0xff, v6
+; VI-NEXT: v_lshl_or_b32 v0, v10, 16, v0
+; VI-NEXT: v_lshl_or_b32 v2, v6, 24, v0
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
index 805053c7d19fc..509641b0b15e3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
@@ -855,8 +855,7 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v4, v6, v3
-; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_fdiv_v2f16:
@@ -888,8 +887,7 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v6, v3
-; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_fdiv_v2f16:
@@ -1240,8 +1238,7 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v4, v6, v3
-; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_fdiv_v2f16_ulp25:
@@ -1273,8 +1270,7 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v6, v3
-; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_fdiv_v2f16_ulp25:
@@ -1548,8 +1544,7 @@ define <2 x half> @v_rcp_v2f16(<2 x half> %x) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_rcp_v2f16:
@@ -1576,8 +1571,7 @@ define <2 x half> @v_rcp_v2f16(<2 x half> %x) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_rcp_v2f16:
@@ -1835,8 +1829,7 @@ define <2 x half> @v_neg_rcp_v2f16(<2 x half> %x) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, -1.0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, -1.0
-; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_neg_rcp_v2f16:
@@ -1863,8 +1856,7 @@ define <2 x half> @v_neg_rcp_v2f16(<2 x half> %x) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, -1.0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, -1.0
-; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_neg_rcp_v2f16:
@@ -2125,8 +2117,7 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_rcp_v2f16_fabs:
@@ -2154,8 +2145,7 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_rcp_v2f16_fabs:
@@ -2425,8 +2415,7 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, -1.0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, -1.0
-; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_neg_rcp_v2f16_fabs:
@@ -2454,8 +2443,7 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, -1.0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, -1.0
-; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_neg_rcp_v2f16_fabs:
@@ -2885,8 +2873,7 @@ define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_rcp_v2f16_ulp25:
@@ -2913,8 +2900,7 @@ define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_rcp_v2f16_ulp25:
@@ -5423,28 +5409,27 @@ define <2 x half> @v_rsq_v2f16(<2 x half> %a) {
; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v3
; GFX8-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v4
; GFX8-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v5
-; GFX8-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX8-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v6
-; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5
+; GFX8-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v7
; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4
-; GFX8-IEEE-NEXT: v_add_f32_e32 v7, v7, v5
+; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5
; GFX8-IEEE-NEXT: v_add_f32_e32 v6, v6, v4
-; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7
+; GFX8-IEEE-NEXT: v_add_f32_e32 v7, v7, v5
; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6
-; GFX8-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v3
+; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7
; GFX8-IEEE-NEXT: v_add_f32_e32 v2, 1.0, v2
-; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5
+; GFX8-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v3
; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4
-; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5
; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3
; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v6
-; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v7
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0
+; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0
-; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0
+; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_rsq_v2f16:
@@ -5458,22 +5443,21 @@ define <2 x half> @v_rsq_v2f16(<2 x half> %a) {
; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v3
; GFX8-FLUSH-NEXT: v_mad_f32 v6, -v2, v4, 1.0
; GFX8-FLUSH-NEXT: v_mad_f32 v7, -v3, v5, 1.0
-; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v5
; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v4
-; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.0
+; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v5
; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, 1.0
-; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5
+; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.0
; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
-; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5
; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v3
; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v6
-; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v7
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0
+; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0
-; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0
+; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_rsq_v2f16:
@@ -5722,28 +5706,27 @@ define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {
; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v3
; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4
; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v3, v5
-; GFX8-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v7
; GFX8-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v6
-; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5
+; GFX8-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v7
; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4
-; GFX8-IEEE-NEXT: v_sub_f32_e32 v7, v7, v5
+; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5
; GFX8-IEEE-NEXT: v_sub_f32_e32 v6, v6, v4
-; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7
+; GFX8-IEEE-NEXT: v_sub_f32_e32 v7, v7, v5
; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6
-; GFX8-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v3
+; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7
; GFX8-IEEE-NEXT: v_add_f32_e32 v2, -1.0, v2
-; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5
+; GFX8-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v3
; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4
-; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5
; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3
; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v6
-; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v7
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, -1.0
+; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, -1.0
-; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, -1.0
+; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_neg_rsq_v2f16:
@@ -5757,22 +5740,21 @@ define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {
; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v3
; GFX8-FLUSH-NEXT: v_mad_f32 v6, v2, v4, -1.0
; GFX8-FLUSH-NEXT: v_mad_f32 v7, v3, v5, -1.0
-; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v5
; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v4
-; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.0
+; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v5
; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, -1.0
-; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5
+; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.0
; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
-; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v3
+; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5
; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2
-; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v7
+; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v3
; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v6
-; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
+; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v7
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2
-; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, -1.0
+; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, -1.0
-; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, -1.0
+; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_neg_rsq_v2f16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
index 24f3e0c85c519..a417f5f6c44c0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
@@ -388,8 +388,7 @@ define <2 x half> @v_fma_v2f16(<2 x half> %x, <2 x half> %y, <2 x half> %z) {
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v3, v4, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v2f16:
@@ -460,8 +459,7 @@ define <2 x half> @v_fma_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y, <2 x half>
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v3, v4, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v2f16_fneg_lhs:
@@ -533,8 +531,7 @@ define <2 x half> @v_fma_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y, <2 x half>
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v3, v4, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v2f16_fneg_rhs:
@@ -604,8 +601,7 @@ define <2 x half> @v_fma_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y, <2 x h
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v3, v4, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v2f16_fneg_lhs_rhs:
@@ -681,9 +677,8 @@ define <3 x half> @v_fma_v3f16(<3 x half> %x, <3 x half> %y, <3 x half> %z) {
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v4
; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
; GFX8-NEXT: v_fma_f16 v2, v6, v7, v8
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v3f16:
@@ -768,19 +763,17 @@ define <4 x half> @v_fma_v4f16(<4 x half> %x, <4 x half> %y, <4 x half> %z) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v5
; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
; GFX8-NEXT: v_fma_f16 v2, v6, v8, v10
; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
; GFX8-NEXT: v_fma_f16 v3, v7, v9, v11
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX8-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v4f16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 6b1b797e3cfec..6f43ae7438a39 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -1410,34 +1410,32 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX8-NEXT: v_and_b32_e32 v5, 7, v5
; GFX8-NEXT: v_lshlrev_b16_e32 v3, v9, v3
; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v4
-; GFX8-NEXT: v_mov_b32_e32 v7, 0xff
; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
; GFX8-NEXT: v_mov_b32_e32 v4, 7
; GFX8-NEXT: v_mov_b32_e32 v8, -1
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xff
; GFX8-NEXT: v_and_b32_sdwa v5, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_sdwa v7, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_xor_b32_sdwa v9, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX8-NEXT: v_xor_b32_sdwa v2, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v7
-; GFX8-NEXT: v_and_b32_e32 v9, 7, v9
+; GFX8-NEXT: v_and_b32_sdwa v7, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 25, v1
; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
; GFX8-NEXT: v_lshlrev_b16_sdwa v5, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, v9, v7
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v7
+; GFX8-NEXT: v_and_b32_e32 v9, 7, v9
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, v9, v7
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 8
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX8-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX8-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_lshl_or_b32 v0, v0, 24, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshl_v4i8:
@@ -5819,8 +5817,7 @@ define i64 @v_fshl_i64_48(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v0
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 16, v[2:3]
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_lshl_or_b32 v1, v4, 16, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshl_i64_48:
@@ -6533,15 +6530,14 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
+; GFX8-NEXT: v_mov_b32_e32 v15, 0x7f
; GFX8-NEXT: v_cndmask_b32_e32 v10, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[4:5]
-; GFX8-NEXT: v_mov_b32_e32 v15, 0x7f
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 31, v6
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[6:7]
; GFX8-NEXT: v_bfi_b32 v14, v8, 0, v15
; GFX8-NEXT: v_not_b32_e32 v17, 63
+; GFX8-NEXT: v_lshl_or_b32 v1, v6, 31, v1
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 64, v14
; GFX8-NEXT: v_add_u32_e32 v15, vcc, v14, v17
; GFX8-NEXT: v_lshrrev_b64 v[4:5], v14, v[0:1]
@@ -7051,14 +7047,13 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX8-NEXT: s_cmp_lg_u32 s5, 0
-; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
+; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
; GFX8-NEXT: s_andn2_b32 s2, 0x7f, s4
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 31, v2
+; GFX8-NEXT: v_lshl_or_b32 v1, v2, 31, v1
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX8-NEXT: s_sub_i32 s3, s2, 64
; GFX8-NEXT: s_sub_i32 s4, 64, s2
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
; GFX8-NEXT: s_cmp_lt_u32 s2, 64
; GFX8-NEXT: s_cselect_b32 s5, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s2, 0
@@ -8246,8 +8241,7 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX8-NEXT: v_cndmask_b32_e64 v23, v1, v3, s[4:5]
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[8:9]
; GFX8-NEXT: v_mov_b32_e32 v17, 0x7f
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 31, v10
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_lshl_or_b32 v1, v10, 31, v1
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[10:11]
; GFX8-NEXT: v_bfi_b32 v10, v16, 0, v17
; GFX8-NEXT: v_cndmask_b32_e32 v24, 0, v21, vcc
@@ -8287,9 +8281,8 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
-; GFX8-NEXT: v_lshlrev_b32_e32 v10, 31, v14
-; GFX8-NEXT: v_or_b32_e32 v9, v9, v10
; GFX8-NEXT: v_lshrrev_b64 v[10:11], 1, v[14:15]
+; GFX8-NEXT: v_lshl_or_b32 v9, v14, 31, v9
; GFX8-NEXT: v_bfi_b32 v14, v20, 0, v17
; GFX8-NEXT: v_add_u32_e32 v18, vcc, v14, v18
; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v14
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index cf58ba6658321..28ea57c30a777 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -1422,29 +1422,27 @@ define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX8-NEXT: v_xor_b32_sdwa v9, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_sdwa v5, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_and_b32_e32 v9, 7, v9
-; GFX8-NEXT: v_mov_b32_e32 v8, 0xff
; GFX8-NEXT: v_lshlrev_b16_e32 v5, v9, v5
; GFX8-NEXT: v_mov_b32_e32 v9, 7
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX8-NEXT: v_xor_b32_sdwa v4, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v8, 0xff
; GFX8-NEXT: v_and_b32_sdwa v10, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_sdwa v8, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v4, 7, v4
; GFX8-NEXT: v_and_b32_sdwa v2, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX8-NEXT: v_lshrrev_b16_e32 v8, v10, v8
+; GFX8-NEXT: v_and_b32_sdwa v8, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v4, v0
; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v8
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, v10, v8
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 8
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v8
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v5
; GFX8-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v5
+; GFX8-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 24, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_lshl_or_b32 v0, v0, 24, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_v4i8:
@@ -1888,10 +1886,10 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_not_b32_e32 v4, 23
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_readfirstlane_b32 s4, v3
; GFX8-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX8-NEXT: v_mul_hi_u32 v3, v3, s5
@@ -1909,9 +1907,8 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v2
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v0, v3, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_i24:
@@ -2827,11 +2824,11 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX8-NEXT: v_readfirstlane_b32 s4, v6
; GFX8-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX8-NEXT: v_mul_hi_u32 v6, v6, s5
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX8-NEXT: v_readfirstlane_b32 s5, v6
; GFX8-NEXT: s_add_i32 s4, s4, s5
; GFX8-NEXT: v_mul_hi_u32 v6, v4, s4
@@ -2859,11 +2856,10 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, v4, v1
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v2, v3
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_lshl_or_b32 v1, v1, v4, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_v2i24:
@@ -5467,8 +5463,7 @@ define i64 @v_fshr_i64_5(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v0
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3]
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 27, v4
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_lshl_or_b32 v1, v4, 27, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_i64_5:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index 4d0662098c261..fc7b6777bce8c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -688,22 +688,20 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX8-NEXT: v_lshlrev_b16_e32 v5, 8, v8
; GFX8-NEXT: v_max_i16_e32 v6, 0, v4
; GFX8-NEXT: v_sub_u16_e32 v7, 0x8000, v7
-; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
; GFX8-NEXT: v_sub_u16_e32 v6, 0x7fff, v6
; GFX8-NEXT: v_max_i16_e32 v5, v7, v5
+; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
+; GFX8-NEXT: v_min_i16_e32 v5, v5, v6
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX8-NEXT: v_ashrrev_i16_e32 v3, 8, v3
-; GFX8-NEXT: v_min_i16_e32 v5, v5, v6
-; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: v_add_u16_e32 v4, v4, v5
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_ashrrev_i16_e32 v4, 8, v4
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-NEXT: v_ashrrev_i16_e32 v4, 8, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_saddsat_v4i8:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
index ab7e11a78ed57..03107a08fe5ba 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
@@ -1345,9 +1345,8 @@ define i65 @v_sext_inreg_i65_22(i65 %value) {
; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_bfe_u32 v1, v1, 0, 10
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, 10, v2
+; GFX8-NEXT: v_lshl_or_b32 v1, v2, 10, v1
; GFX8-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3]
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_sext_inreg_i65_22:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index 5409743ce85ee..10376d2599d95 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -688,22 +688,20 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX8-NEXT: v_lshlrev_b16_e32 v5, 8, v8
; GFX8-NEXT: v_add_u16_e32 v6, 0x8001, v6
; GFX8-NEXT: v_min_i16_e32 v7, -1, v4
-; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
; GFX8-NEXT: v_add_u16_e32 v7, 0x8000, v7
; GFX8-NEXT: v_max_i16_e32 v5, v6, v5
+; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
+; GFX8-NEXT: v_min_i16_e32 v5, v5, v7
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX8-NEXT: v_ashrrev_i16_e32 v3, 8, v3
-; GFX8-NEXT: v_min_i16_e32 v5, v5, v7
-; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-NEXT: v_sub_u16_e32 v4, v4, v5
+; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NEXT: v_ashrrev_i16_e32 v4, 8, v4
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-NEXT: v_ashrrev_i16_e32 v4, 8, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v4i8:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
index 92d87a0d74efb..64bfb9b6db44e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
@@ -199,8 +199,7 @@ define void @v_constained_fma_v2f16_fpexcept_strict_div(<2 x half> %x, <2 x half
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v5, v6, v7
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: flat_store_dword v[3:4], v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -425,19 +424,17 @@ define void @v_constained_fma_v4f16_fpexcept_strict_div(<4 x half> %x, <4 x half
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3
+; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v4
; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v5
; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
; GFX8-NEXT: v_fma_f16 v2, v8, v10, v12
; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
; GFX8-NEXT: v_fma_f16 v3, v9, v11, v13
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX8-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -916,8 +913,7 @@ define void @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_div(<2 x half> %x,
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v5, v6, v7
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: flat_store_dword v[3:4], v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
index 567656635b726..336efe6ee2de5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
@@ -591,10 +591,9 @@ define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7
; GFX8-NEXT: v_add_u16_e64 v3, v3, v4 clamp
; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
-; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 8, v0
; GFX8-NEXT: v_and_b32_sdwa v1, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
index e17706ba6dd67..8c8370927d294 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
@@ -579,10 +579,9 @@ define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7
; GFX8-NEXT: v_sub_u16_e64 v3, v3, v4 clamp
; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
-; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 8, v0
; GFX8-NEXT: v_and_b32_sdwa v1, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
diff --git a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
index ca96693fc44e9..9c5907d9ec72a 100644
--- a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
+++ b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
@@ -50,10 +50,9 @@ define amdgpu_kernel void @parent_kernel_missing_inputs() #0 {
; FIXEDABI-SDAG-NEXT: s_add_i32 s4, s4, s9
; FIXEDABI-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
; FIXEDABI-SDAG-NEXT: s_add_u32 s0, s0, s9
-; FIXEDABI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; FIXEDABI-SDAG-NEXT: s_addc_u32 s1, s1, 0
; FIXEDABI-SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; FIXEDABI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; FIXEDABI-SDAG-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; FIXEDABI-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s5
; FIXEDABI-SDAG-NEXT: s_mov_b32 s14, s8
; FIXEDABI-SDAG-NEXT: s_getpc_b64 s[4:5]
@@ -72,13 +71,11 @@ define amdgpu_kernel void @parent_kernel_missing_inputs() #0 {
; FIXEDABI-GISEL-NEXT: s_add_i32 s4, s4, s9
; FIXEDABI-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
; FIXEDABI-GISEL-NEXT: s_add_u32 s0, s0, s9
-; FIXEDABI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; FIXEDABI-GISEL-NEXT: s_addc_u32 s1, s1, 0
-; FIXEDABI-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
-; FIXEDABI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
+; FIXEDABI-GISEL-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; FIXEDABI-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s5
; FIXEDABI-GISEL-NEXT: s_mov_b32 s14, s8
-; FIXEDABI-GISEL-NEXT: v_or_b32_e32 v31, v0, v1
+; FIXEDABI-GISEL-NEXT: v_lshl_or_b32 v31, v2, 20, v0
; FIXEDABI-GISEL-NEXT: s_getpc_b64 s[4:5]
; FIXEDABI-GISEL-NEXT: s_add_u32 s4, s4, requires_all_inputs at rel32@lo+4
; FIXEDABI-GISEL-NEXT: s_addc_u32 s5, s5, requires_all_inputs at rel32@hi+12
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 8fb907a94fb4a..dd574a62201f1 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -5742,49 +5742,41 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v55, v57, v41, s4
; VI-NEXT: v_perm_b32 v1, v1, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v55
-; VI-NEXT: v_or_b32_e32 v1, v1, v48
+; VI-NEXT: v_lshl_or_b32 v1, v55, 16, v1
+; VI-NEXT: v_perm_b32 v2, v2, v53, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v34, v56, s4
-; VI-NEXT: v_perm_b32 v2, v2, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v47, v40, s4
; VI-NEXT: v_perm_b32 v2, v3, v38, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v46, v45, s4
; VI-NEXT: v_perm_b32 v1, v4, v52, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v46, v45, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v33, v39, s4
; VI-NEXT: v_perm_b32 v2, v5, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v44, v43, s4
; VI-NEXT: v_perm_b32 v1, v6, v51, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v44, v43, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v50, v54, s4
; VI-NEXT: v_perm_b32 v2, v7, v63, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v62, v61, s4
; VI-NEXT: v_perm_b32 v1, v8, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v62, v61, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -5792,14 +5784,12 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v49, s4
; VI-NEXT: v_perm_b32 v1, v60, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v59, v58, s4
; VI-NEXT: v_perm_b32 v1, v10, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v59, v58, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
@@ -5808,21 +5798,19 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v11, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v12, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -5831,21 +5819,19 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
@@ -5854,21 +5840,19 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -5877,21 +5861,19 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -5900,21 +5882,19 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
@@ -5924,19 +5904,17 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -5946,19 +5924,17 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v23, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v24, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
@@ -5968,74 +5944,70 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v26, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v27, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v27, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v28, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v29, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v29, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v30, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v31, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
@@ -6045,8 +6017,7 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v32, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -9469,136 +9440,121 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24
; VI-NEXT: .LBB13_3: ; %end
; VI-NEXT: v_mov_b32_e32 v9, s48
-; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s82
-; VI-NEXT: v_perm_b32 v9, s53, v9, v1
+; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
+; VI-NEXT: v_mov_b32_e32 v4, s67
; VI-NEXT: v_perm_b32 v3, s16, v2, v1
+; VI-NEXT: v_perm_b32 v9, s53, v9, v1
; VI-NEXT: v_mov_b32_e32 v24, s83
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v4, s67
-; VI-NEXT: v_perm_b32 v24, s85, v24, v1
-; VI-NEXT: v_or_b32_e32 v3, v3, v9
; VI-NEXT: v_perm_b32 v2, s17, v4, v1
; VI-NEXT: v_mov_b32_e32 v13, s38
-; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v24
; VI-NEXT: v_mov_b32_e32 v4, s47
-; VI-NEXT: v_perm_b32 v13, s81, v13, v1
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
-; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
+; VI-NEXT: v_perm_b32 v24, s85, v24, v1
+; VI-NEXT: v_lshl_or_b32 v3, v9, 16, v3
+; VI-NEXT: v_mov_b32_e32 v6, s46
; VI-NEXT: v_perm_b32 v5, s18, v4, v1
+; VI-NEXT: v_perm_b32 v13, s81, v13, v1
; VI-NEXT: v_mov_b32_e32 v25, s80
-; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
-; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_perm_b32 v25, s87, v25, v1
-; VI-NEXT: v_or_b32_e32 v2, v5, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
+; VI-NEXT: v_mov_b32_e32 v26, s68
+; VI-NEXT: v_readlane_b32 s16, v33, 57
+; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v24, 16, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: v_perm_b32 v4, s19, v6, v1
; VI-NEXT: v_mov_b32_e32 v17, s36
-; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v25
; VI-NEXT: v_mov_b32_e32 v6, s69
-; VI-NEXT: v_perm_b32 v17, s84, v17, v1
-; VI-NEXT: v_or_b32_e32 v2, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
-; VI-NEXT: v_perm_b32 v7, s20, v6, v1
-; VI-NEXT: v_mov_b32_e32 v26, s68
-; VI-NEXT: v_readlane_b32 s16, v33, 57
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; VI-NEXT: v_mov_b32_e32 v8, s65
-; VI-NEXT: v_perm_b32 v26, s16, v26, v1
-; VI-NEXT: v_or_b32_e32 v2, v7, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
-; VI-NEXT: v_perm_b32 v6, s21, v8, v1
; VI-NEXT: v_mov_b32_e32 v19, s34
+; VI-NEXT: v_perm_b32 v25, s87, v25, v1
+; VI-NEXT: v_perm_b32 v26, s16, v26, v1
; VI-NEXT: v_readlane_b32 s16, v33, 56
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
-; VI-NEXT: v_mov_b32_e32 v8, s55
-; VI-NEXT: v_perm_b32 v19, s16, v19, v1
-; VI-NEXT: v_or_b32_e32 v2, v6, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
-; VI-NEXT: v_perm_b32 v10, s22, v8, v1
-; VI-NEXT: v_mov_b32_e32 v27, s71
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
-; VI-NEXT: v_mov_b32_e32 v11, s52
-; VI-NEXT: v_perm_b32 v27, s70, v27, v1
-; VI-NEXT: v_or_b32_e32 v2, v10, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
-; VI-NEXT: v_perm_b32 v8, s23, v11, v1
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v13, 16, v5
+; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
+; VI-NEXT: v_mov_b32_e32 v8, s65
+; VI-NEXT: v_perm_b32 v7, s20, v6, v1
; VI-NEXT: v_mov_b32_e32 v20, s30
+; VI-NEXT: v_perm_b32 v17, s84, v17, v1
+; VI-NEXT: v_perm_b32 v19, s16, v19, v1
; VI-NEXT: v_readlane_b32 s16, v33, 55
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
-; VI-NEXT: v_mov_b32_e32 v11, s54
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v25, 16, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
+; VI-NEXT: v_perm_b32 v6, s21, v8, v1
+; VI-NEXT: v_mov_b32_e32 v8, s55
; VI-NEXT: v_perm_b32 v20, s16, v20, v1
; VI-NEXT: v_readlane_b32 s16, v33, 53
-; VI-NEXT: v_or_b32_e32 v2, v8, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
-; VI-NEXT: v_perm_b32 v12, s24, v11, v1
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v17, 16, v7
+; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
+; VI-NEXT: v_mov_b32_e32 v11, s52
+; VI-NEXT: v_perm_b32 v10, s22, v8, v1
+; VI-NEXT: v_mov_b32_e32 v27, s71
; VI-NEXT: v_mov_b32_e32 v28, s16
; VI-NEXT: v_readlane_b32 s16, v33, 54
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
-; VI-NEXT: v_mov_b32_e32 v14, s66
-; VI-NEXT: v_perm_b32 v28, s16, v28, v1
-; VI-NEXT: v_or_b32_e32 v2, v12, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
-; VI-NEXT: v_perm_b32 v11, s25, v14, v1
+; VI-NEXT: v_lshl_or_b32 v2, v26, 16, v6
+; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
+; VI-NEXT: v_perm_b32 v8, s23, v11, v1
+; VI-NEXT: v_mov_b32_e32 v11, s54
; VI-NEXT: v_mov_b32_e32 v21, s90
+; VI-NEXT: v_perm_b32 v27, s70, v27, v1
+; VI-NEXT: v_perm_b32 v28, s16, v28, v1
; VI-NEXT: v_readlane_b32 s16, v33, 52
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v28
-; VI-NEXT: v_mov_b32_e32 v14, s51
+; VI-NEXT: v_lshl_or_b32 v2, v19, 16, v10
+; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
+; VI-NEXT: v_mov_b32_e32 v14, s66
+; VI-NEXT: v_perm_b32 v12, s24, v11, v1
; VI-NEXT: v_perm_b32 v21, s16, v21, v1
; VI-NEXT: v_readlane_b32 s16, v33, 50
-; VI-NEXT: v_or_b32_e32 v2, v11, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
-; VI-NEXT: v_perm_b32 v15, s26, v14, v1
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v27, 16, v8
+; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
+; VI-NEXT: v_perm_b32 v11, s25, v14, v1
+; VI-NEXT: v_mov_b32_e32 v14, s51
; VI-NEXT: v_mov_b32_e32 v29, s16
; VI-NEXT: v_readlane_b32 s16, v33, 51
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
+; VI-NEXT: v_lshl_or_b32 v2, v20, 16, v12
+; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
; VI-NEXT: v_mov_b32_e32 v16, s86
-; VI-NEXT: v_perm_b32 v29, s16, v29, v1
-; VI-NEXT: v_or_b32_e32 v2, v15, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
-; VI-NEXT: v_perm_b32 v14, s27, v16, v1
+; VI-NEXT: v_perm_b32 v15, s26, v14, v1
; VI-NEXT: v_mov_b32_e32 v22, s88
+; VI-NEXT: v_perm_b32 v29, s16, v29, v1
; VI-NEXT: v_readlane_b32 s16, v33, 49
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
+; VI-NEXT: v_lshl_or_b32 v2, v28, 16, v11
+; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
+; VI-NEXT: v_perm_b32 v14, s27, v16, v1
; VI-NEXT: v_mov_b32_e32 v16, s50
; VI-NEXT: v_perm_b32 v22, s16, v22, v1
; VI-NEXT: v_readlane_b32 s16, v33, 47
-; VI-NEXT: v_or_b32_e32 v2, v14, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v21, 16, v15
+; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
+; VI-NEXT: v_mov_b32_e32 v23, s64
; VI-NEXT: v_perm_b32 v18, s28, v16, v1
; VI-NEXT: v_mov_b32_e32 v30, s16
; VI-NEXT: v_readlane_b32 s16, v33, 48
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
-; VI-NEXT: v_mov_b32_e32 v23, s64
+; VI-NEXT: v_lshl_or_b32 v2, v29, 16, v14
+; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
+; VI-NEXT: v_perm_b32 v16, s29, v23, v1
; VI-NEXT: v_perm_b32 v30, s16, v30, v1
; VI-NEXT: v_readlane_b32 s16, v33, 46
-; VI-NEXT: v_or_b32_e32 v2, v18, v2
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v22, 16, v18
; VI-NEXT: v_add_u32_e32 v4, vcc, 48, v0
-; VI-NEXT: v_perm_b32 v16, s29, v23, v1
; VI-NEXT: v_mov_b32_e32 v23, s78
; VI-NEXT: v_mov_b32_e32 v31, s16
; VI-NEXT: v_readlane_b32 s16, v33, 45
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
-; VI-NEXT: v_perm_b32 v3, s16, v23, v1
-; VI-NEXT: v_or_b32_e32 v2, v16, v2
+; VI-NEXT: v_lshl_or_b32 v2, v30, 16, v16
; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
+; VI-NEXT: v_perm_b32 v3, s16, v23, v1
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, s44, v31, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: v_readlane_b32 s16, v33, 44
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9606,20 +9562,18 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 42
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 43
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s45, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 60, v0
; VI-NEXT: v_readlane_b32 s16, v33, 41
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s76
; VI-NEXT: v_readlane_b32 s16, v33, 40
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s42, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 64, v0
; VI-NEXT: v_readlane_b32 s16, v33, 39
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9627,20 +9581,18 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 37
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 38
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s43, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x44, v0
; VI-NEXT: v_readlane_b32 s16, v33, 36
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_readlane_b32 s16, v33, 35
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s40, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x48, v0
; VI-NEXT: v_readlane_b32 s16, v33, 34
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9648,10 +9600,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 32
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 33
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s41, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x4c, v0
; VI-NEXT: v_readlane_b32 s16, v33, 31
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9660,8 +9611,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: v_readlane_b32 s14, v33, 30
; VI-NEXT: v_perm_b32 v3, s14, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x50, v0
; VI-NEXT: v_readlane_b32 s14, v33, 29
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9669,10 +9619,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s14, v33, 27
; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_readlane_b32 s14, v33, 28
-; VI-NEXT: v_perm_b32 v3, s14, v3, v1
; VI-NEXT: v_perm_b32 v2, s15, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s14, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x54, v0
; VI-NEXT: v_readlane_b32 s14, v33, 26
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9681,8 +9630,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s62
; VI-NEXT: v_readlane_b32 s12, v33, 25
; VI-NEXT: v_perm_b32 v3, s12, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x58, v0
; VI-NEXT: v_readlane_b32 s12, v33, 24
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9690,10 +9638,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s12, v33, 22
; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_readlane_b32 s12, v33, 23
-; VI-NEXT: v_perm_b32 v3, s12, v3, v1
; VI-NEXT: v_perm_b32 v2, s13, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s12, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x5c, v0
; VI-NEXT: v_readlane_b32 s12, v33, 21
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9702,8 +9649,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s60
; VI-NEXT: v_readlane_b32 s10, v33, 20
; VI-NEXT: v_perm_b32 v3, s10, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x60, v0
; VI-NEXT: v_readlane_b32 s10, v33, 19
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9711,10 +9657,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s10, v33, 17
; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_readlane_b32 s10, v33, 18
-; VI-NEXT: v_perm_b32 v3, s10, v3, v1
; VI-NEXT: v_perm_b32 v2, s11, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s10, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x64, v0
; VI-NEXT: v_readlane_b32 s10, v33, 16
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9723,8 +9668,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s58
; VI-NEXT: v_readlane_b32 s8, v33, 15
; VI-NEXT: v_perm_b32 v3, s8, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x68, v0
; VI-NEXT: v_readlane_b32 s8, v33, 14
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9732,10 +9676,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s8, v33, 12
; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_readlane_b32 s8, v33, 13
-; VI-NEXT: v_perm_b32 v3, s8, v3, v1
; VI-NEXT: v_perm_b32 v2, s9, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s8, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x6c, v0
; VI-NEXT: v_readlane_b32 s8, v33, 11
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9744,8 +9687,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_readlane_b32 s6, v33, 10
; VI-NEXT: v_perm_b32 v3, s6, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x70, v0
; VI-NEXT: v_readlane_b32 s6, v33, 9
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9753,10 +9695,9 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s6, v33, 7
; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_readlane_b32 s6, v33, 8
-; VI-NEXT: v_perm_b32 v3, s6, v3, v1
; VI-NEXT: v_perm_b32 v2, s7, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s6, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x74, v0
; VI-NEXT: v_readlane_b32 s6, v33, 6
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9766,8 +9707,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_readlane_b32 s4, v33, 5
; VI-NEXT: v_perm_b32 v3, s4, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x78, v0
; VI-NEXT: v_readlane_b32 s4, v33, 4
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9777,8 +9717,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s4, v33, 3
; VI-NEXT: v_perm_b32 v2, s5, v2, v1
; VI-NEXT: v_perm_b32 v1, s4, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_readlane_b32 s30, v32, 30
; VI-NEXT: v_readlane_b32 s7, v33, 1
@@ -10370,166 +10309,146 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24
; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24
; GFX9-NEXT: .LBB13_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v8, s36
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s85
-; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
-; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
-; GFX9-NEXT: v_mov_b32_e32 v21, s52
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v4, s71
-; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
+; GFX9-NEXT: v_mov_b32_e32 v21, s52
+; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
; GFX9-NEXT: v_perm_b32 v2, s17, v4, v1
; GFX9-NEXT: v_mov_b32_e32 v11, s34
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v21
; GFX9-NEXT: v_mov_b32_e32 v4, s69
-; GFX9-NEXT: v_perm_b32 v11, s54, v11, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
+; GFX9-NEXT: v_mov_b32_e32 v6, s68
; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
+; GFX9-NEXT: v_perm_b32 v11, s54, v11, v1
; GFX9-NEXT: v_mov_b32_e32 v22, s48
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v11
-; GFX9-NEXT: v_mov_b32_e32 v6, s68
-; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v21, 16, v2
; GFX9-NEXT: v_perm_b32 v4, s19, v6, v1
; GFX9-NEXT: v_mov_b32_e32 v14, s30
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; GFX9-NEXT: v_mov_b32_e32 v6, s70
-; GFX9-NEXT: v_perm_b32 v14, s39, v14, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshl_or_b32 v2, v11, 16, v5
+; GFX9-NEXT: v_mov_b32_e32 v9, s80
; GFX9-NEXT: v_perm_b32 v7, s20, v6, v1
+; GFX9-NEXT: v_perm_b32 v14, s39, v14, v1
; GFX9-NEXT: v_mov_b32_e32 v23, s49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v14
-; GFX9-NEXT: v_mov_b32_e32 v9, s80
-; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: v_lshl_or_b32 v2, v22, 16, v4
; GFX9-NEXT: v_perm_b32 v6, s21, v9, v1
; GFX9-NEXT: v_mov_b32_e32 v15, s94
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v9, s64
-; GFX9-NEXT: v_perm_b32 v15, s97, v15, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v6, v2
+; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: v_lshl_or_b32 v2, v14, 16, v7
+; GFX9-NEXT: v_mov_b32_e32 v12, s66
; GFX9-NEXT: v_perm_b32 v10, s22, v9, v1
+; GFX9-NEXT: v_perm_b32 v15, s97, v15, v1
; GFX9-NEXT: v_mov_b32_e32 v24, s98
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v15
-; GFX9-NEXT: v_mov_b32_e32 v12, s66
-; GFX9-NEXT: v_perm_b32 v24, s87, v24, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v10, v2
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: v_lshl_or_b32 v2, v23, 16, v6
; GFX9-NEXT: v_perm_b32 v9, s23, v12, v1
; GFX9-NEXT: v_mov_b32_e32 v16, s92
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v24
; GFX9-NEXT: v_mov_b32_e32 v12, s55
-; GFX9-NEXT: v_perm_b32 v16, s86, v16, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v9, v2
+; GFX9-NEXT: v_perm_b32 v24, s87, v24, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: v_lshl_or_b32 v2, v15, 16, v10
+; GFX9-NEXT: v_mov_b32_e32 v17, s65
; GFX9-NEXT: v_perm_b32 v13, s24, v12, v1
+; GFX9-NEXT: v_perm_b32 v16, s86, v16, v1
; GFX9-NEXT: v_mov_b32_e32 v25, s84
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v16
-; GFX9-NEXT: v_mov_b32_e32 v17, s65
-; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v13, v2
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: v_lshl_or_b32 v2, v24, 16, v9
; GFX9-NEXT: v_perm_b32 v12, s25, v17, v1
; GFX9-NEXT: v_mov_b32_e32 v17, s90
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v25
; GFX9-NEXT: v_mov_b32_e32 v18, s67
-; GFX9-NEXT: v_perm_b32 v17, s82, v17, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v12, v2
+; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: v_lshl_or_b32 v2, v16, 16, v13
+; GFX9-NEXT: v_mov_b32_e32 v8, s36
+; GFX9-NEXT: v_mov_b32_e32 v19, s53
; GFX9-NEXT: v_perm_b32 v18, s26, v18, v1
+; GFX9-NEXT: v_perm_b32 v17, s82, v17, v1
; GFX9-NEXT: v_mov_b32_e32 v26, s81
; GFX9-NEXT: v_readlane_b32 s16, v30, 49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; GFX9-NEXT: v_mov_b32_e32 v19, s53
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: v_lshl_or_b32 v2, v25, 16, v12
+; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
+; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
; GFX9-NEXT: v_perm_b32 v26, s16, v26, v1
; GFX9-NEXT: v_readlane_b32 s16, v30, 47
-; GFX9-NEXT: v_or_b32_e32 v2, v18, v2
-; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: v_lshl_or_b32 v2, v17, 16, v18
; GFX9-NEXT: v_mov_b32_e32 v20, s88
+; GFX9-NEXT: v_mov_b32_e32 v27, s83
; GFX9-NEXT: v_mov_b32_e32 v28, s16
+; GFX9-NEXT: v_lshl_or_b32 v3, v8, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 48
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v26
-; GFX9-NEXT: v_mov_b32_e32 v27, s83
+; GFX9-NEXT: v_lshl_or_b32 v2, v26, 16, v19
+; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v3, s16, v20, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v19, v2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_perm_b32 v2, s28, v27, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 45
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 46
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v2, s29, v28, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 44
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s78
; GFX9-NEXT: v_readlane_b32 s16, v30, 43
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s44, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 42
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 40
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 41
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s45, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 39
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s76
; GFX9-NEXT: v_readlane_b32 s16, v30, 38
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s42, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 37
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 35
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 36
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s43, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 34
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: v_readlane_b32 s16, v30, 33
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s40, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 32
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 30
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 31
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s41, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 29
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: v_mov_b32_e32 v2, s16
@@ -10537,18 +10456,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: v_readlane_b32 s14, v30, 28
; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s14, v30, 27
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: v_mov_b32_e32 v2, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 25
; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 26
-; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s15, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s14, v30, 24
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: v_mov_b32_e32 v2, s14
@@ -10556,18 +10473,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s62
; GFX9-NEXT: v_readlane_b32 s12, v30, 23
; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s12, v30, 22
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: v_mov_b32_e32 v2, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 20
; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 21
-; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s13, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s12, v30, 19
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: v_mov_b32_e32 v2, s12
@@ -10575,18 +10490,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s60
; GFX9-NEXT: v_readlane_b32 s10, v30, 18
; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s10, v30, 17
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: v_mov_b32_e32 v2, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 15
; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 16
-; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s11, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s10, v30, 14
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: v_mov_b32_e32 v2, s10
@@ -10594,18 +10507,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s58
; GFX9-NEXT: v_readlane_b32 s8, v30, 13
; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s8, v30, 12
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: v_mov_b32_e32 v2, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 10
; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 11
-; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s9, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s8, v30, 9
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: v_mov_b32_e32 v2, s8
@@ -10613,18 +10524,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_readlane_b32 s6, v30, 8
; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s6, v30, 7
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 5
; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 6
-; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s7, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s6, v30, 4
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: v_mov_b32_e32 v2, s6
@@ -10632,8 +10541,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: v_readlane_b32 s4, v30, 3
; GFX9-NEXT: v_perm_b32 v3, s4, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s4, v30, 2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_mov_b32_e32 v2, s4
@@ -10642,8 +10550,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_readlane_b32 s4, v30, 1
; GFX9-NEXT: v_perm_b32 v2, s5, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s4, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: v_readlane_b32 s30, v29, 34
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: v_readlane_b32 s31, v29, 35
@@ -11234,70 +11141,65 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: s_lshr_b64 s[42:43], s[4:5], 24
; GFX11-NEXT: .LBB13_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v2, s103, s30, v1
-; GFX11-NEXT: v_readlane_b32 s30, v24, 7
-; GFX11-NEXT: v_readlane_b32 s31, v24, 8
-; GFX11-NEXT: v_readlane_b32 s103, v24, 5
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_perm_b32 v18, s84, s83, v1
; GFX11-NEXT: v_perm_b32 v3, s0, s104, v1
; GFX11-NEXT: v_perm_b32 v4, s1, s102, v1
; GFX11-NEXT: v_perm_b32 v5, s100, s94, v1
-; GFX11-NEXT: v_perm_b32 v19, s81, s80, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-NEXT: v_perm_b32 v6, s2, s101, v1
; GFX11-NEXT: v_perm_b32 v7, s3, s99, v1
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-NEXT: v_perm_b32 v18, s84, s83, v1
+; GFX11-NEXT: v_perm_b32 v19, s81, s80, v1
; GFX11-NEXT: v_perm_b32 v8, s97, s92, v1
-; GFX11-NEXT: v_or_b32_e32 v3, v4, v18
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v19
-; GFX11-NEXT: v_perm_b32 v11, s86, s90, v1
-; GFX11-NEXT: v_perm_b32 v20, s71, s70, v1
-; GFX11-NEXT: v_perm_b32 v21, s67, s66, v1
-; GFX11-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX11-NEXT: v_or_b32_e32 v5, v7, v5
; GFX11-NEXT: v_perm_b32 v9, s16, s98, v1
; GFX11-NEXT: v_perm_b32 v10, s17, s96, v1
+; GFX11-NEXT: v_perm_b32 v11, s86, s90, v1
; GFX11-NEXT: v_perm_b32 v12, s18, s87, v1
; GFX11-NEXT: v_perm_b32 v13, s19, s85, v1
-; GFX11-NEXT: v_perm_b32 v22, s64, s55, v1
+; GFX11-NEXT: v_perm_b32 v20, s71, s70, v1
+; GFX11-NEXT: v_perm_b32 v21, s67, s66, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v18, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v4, v5, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v5, v19, 16, v7
+; GFX11-NEXT: v_readlane_b32 s0, v25, 6
+; GFX11-NEXT: v_readlane_b32 s1, v25, 4
+; GFX11-NEXT: v_readlane_b32 s30, v24, 7
+; GFX11-NEXT: v_readlane_b32 s31, v24, 8
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v20
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v21
+; GFX11-NEXT: v_lshl_or_b32 v2, v8, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v3, v20, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v4, v11, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v5, v21, 16, v13
+; GFX11-NEXT: v_readlane_b32 s104, v24, 6
+; GFX11-NEXT: v_readlane_b32 s103, v24, 5
+; GFX11-NEXT: v_readlane_b32 s102, v24, 4
+; GFX11-NEXT: v_readlane_b32 s101, v24, 3
+; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:16
+; GFX11-NEXT: v_perm_b32 v5, s50, s72, v1
+; GFX11-NEXT: v_readlane_b32 s100, v24, 2
+; GFX11-NEXT: v_readlane_b32 s99, v24, 1
+; GFX11-NEXT: v_readlane_b32 s98, v24, 0
+; GFX11-NEXT: v_readlane_b32 s97, v23, 31
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-NEXT: v_perm_b32 v8, s48, s39, v1
; GFX11-NEXT: v_perm_b32 v14, s82, s88, v1
-; GFX11-NEXT: v_perm_b32 v17, s21, s65, v1
-; GFX11-NEXT: v_or_b32_e32 v2, v9, v2
-; GFX11-NEXT: v_or_b32_e32 v3, v10, v3
-; GFX11-NEXT: v_or_b32_e32 v4, v12, v4
-; GFX11-NEXT: v_or_b32_e32 v5, v13, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v22
; GFX11-NEXT: v_perm_b32 v15, s69, s78, v1
; GFX11-NEXT: v_perm_b32 v16, s20, s68, v1
+; GFX11-NEXT: v_perm_b32 v17, s21, s65, v1
+; GFX11-NEXT: v_perm_b32 v22, s64, s55, v1
; GFX11-NEXT: v_perm_b32 v6, s53, s52, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v14
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:16
-; GFX11-NEXT: v_or_b32_e32 v3, v17, v8
-; GFX11-NEXT: v_perm_b32 v8, s48, s39, v1
; GFX11-NEXT: v_perm_b32 v9, s22, s54, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v15
-; GFX11-NEXT: v_or_b32_e32 v2, v16, v7
-; GFX11-NEXT: v_perm_b32 v5, s50, s72, v1
; GFX11-NEXT: v_perm_b32 v7, s23, s51, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v11, s25, s38, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_readlane_b32 s0, v25, 6
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-NEXT: v_or_b32_e32 v5, v7, v6
+; GFX11-NEXT: v_lshl_or_b32 v2, v14, 16, v16
+; GFX11-NEXT: v_lshl_or_b32 v3, v22, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v4, v15, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v7
; GFX11-NEXT: v_or_b32_e32 v7, v11, v8
; GFX11-NEXT: v_perm_b32 v11, s0, s74, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 3
-; GFX11-NEXT: v_readlane_b32 s1, v25, 4
; GFX11-NEXT: v_perm_b32 v9, s24, s49, v1
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:32
; GFX11-NEXT: v_perm_b32 v12, s37, s76, v1
@@ -11306,109 +11208,102 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: v_readlane_b32 s0, v25, 7
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_perm_b32 v10, s34, vcc_hi, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v8
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; GFX11-NEXT: v_perm_b32 v4, s28, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 5
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-NEXT: v_perm_b32 v9, s27, s35, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s29, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 1
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_readlane_b32 s1, v26, 31
; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
+; GFX11-NEXT: v_readlane_b32 s96, v23, 30
; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s62, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 2
-; GFX11-NEXT: v_readlane_b32 s104, v24, 6
; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:48
-; GFX11-NEXT: v_readlane_b32 s102, v24, 4
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
+; GFX11-NEXT: v_readlane_b32 s87, v23, 29
+; GFX11-NEXT: v_readlane_b32 s86, v23, 28
+; GFX11-NEXT: v_readlane_b32 s85, v23, 27
; GFX11-NEXT: v_perm_b32 v4, s40, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 30
-; GFX11-NEXT: v_readlane_b32 s101, v24, 3
-; GFX11-NEXT: v_readlane_b32 s100, v24, 2
-; GFX11-NEXT: v_readlane_b32 s99, v24, 1
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-NEXT: v_readlane_b32 s84, v23, 26
+; GFX11-NEXT: v_readlane_b32 s83, v23, 25
+; GFX11-NEXT: v_readlane_b32 s82, v23, 24
+; GFX11-NEXT: v_lshl_or_b32 v4, v12, 16, v4
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 0
; GFX11-NEXT: v_readlane_b32 s1, v26, 26
-; GFX11-NEXT: v_readlane_b32 s98, v24, 0
-; GFX11-NEXT: v_readlane_b32 s97, v23, 31
+; GFX11-NEXT: v_readlane_b32 s81, v23, 23
+; GFX11-NEXT: v_readlane_b32 s80, v23, 22
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v10
; GFX11-NEXT: v_perm_b32 v5, s41, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 28
-; GFX11-NEXT: v_readlane_b32 s96, v23, 30
-; GFX11-NEXT: v_readlane_b32 s87, v23, 29
-; GFX11-NEXT: v_readlane_b32 s86, v23, 28
+; GFX11-NEXT: v_readlane_b32 s71, v23, 21
+; GFX11-NEXT: v_readlane_b32 s70, v23, 20
+; GFX11-NEXT: v_readlane_b32 s69, v23, 19
; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-NEXT: v_perm_b32 v11, s0, s60, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 25
-; GFX11-NEXT: v_readlane_b32 s85, v23, 27
-; GFX11-NEXT: v_readlane_b32 s84, v23, 26
+; GFX11-NEXT: v_readlane_b32 s68, v23, 18
+; GFX11-NEXT: v_readlane_b32 s67, v23, 17
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:64
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v11
; GFX11-NEXT: v_perm_b32 v6, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 29
; GFX11-NEXT: v_readlane_b32 s1, v26, 21
-; GFX11-NEXT: v_readlane_b32 s83, v23, 25
-; GFX11-NEXT: v_readlane_b32 s82, v23, 24
+; GFX11-NEXT: v_readlane_b32 s66, v23, 16
+; GFX11-NEXT: v_readlane_b32 s65, v23, 15
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v6
; GFX11-NEXT: v_perm_b32 v8, s14, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 27
-; GFX11-NEXT: v_readlane_b32 s81, v23, 23
-; GFX11-NEXT: v_readlane_b32 s80, v23, 22
-; GFX11-NEXT: v_readlane_b32 s71, v23, 21
+; GFX11-NEXT: v_readlane_b32 s64, v23, 14
+; GFX11-NEXT: v_readlane_b32 s55, v23, 13
+; GFX11-NEXT: v_readlane_b32 s54, v23, 12
; GFX11-NEXT: v_or_b32_e32 v6, v8, v9
; GFX11-NEXT: v_perm_b32 v10, s15, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 23
-; GFX11-NEXT: v_readlane_b32 s70, v23, 20
-; GFX11-NEXT: v_readlane_b32 s69, v23, 19
-; GFX11-NEXT: v_readlane_b32 s68, v23, 18
+; GFX11-NEXT: v_readlane_b32 s53, v23, 11
+; GFX11-NEXT: v_readlane_b32 s52, v23, 10
+; GFX11-NEXT: v_readlane_b32 s51, v23, 9
; GFX11-NEXT: v_or_b32_e32 v7, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s58, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 24
-; GFX11-NEXT: v_readlane_b32 s67, v23, 17
-; GFX11-NEXT: v_readlane_b32 s66, v23, 16
-; GFX11-NEXT: v_readlane_b32 s65, v23, 15
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
+; GFX11-NEXT: v_readlane_b32 s50, v23, 8
+; GFX11-NEXT: v_readlane_b32 s49, v23, 7
+; GFX11-NEXT: v_readlane_b32 s48, v23, 6
+; GFX11-NEXT: v_readlane_b32 s39, v23, 5
; GFX11-NEXT: v_perm_b32 v8, s12, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 20
-; GFX11-NEXT: v_readlane_b32 s64, v23, 14
-; GFX11-NEXT: v_readlane_b32 s55, v23, 13
-; GFX11-NEXT: v_readlane_b32 s54, v23, 12
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-NEXT: v_readlane_b32 s38, v23, 4
+; GFX11-NEXT: v_readlane_b32 s37, v23, 3
+; GFX11-NEXT: v_readlane_b32 s36, v23, 2
+; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v8
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 22
; GFX11-NEXT: v_readlane_b32 s1, v26, 16
-; GFX11-NEXT: v_readlane_b32 s53, v23, 11
-; GFX11-NEXT: v_readlane_b32 s52, v23, 10
+; GFX11-NEXT: v_readlane_b32 s35, v23, 1
+; GFX11-NEXT: v_readlane_b32 s34, v23, 0
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; GFX11-NEXT: v_perm_b32 v9, s13, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 18
-; GFX11-NEXT: v_readlane_b32 s51, v23, 9
-; GFX11-NEXT: v_readlane_b32 s50, v23, 8
-; GFX11-NEXT: v_readlane_b32 s49, v23, 7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
; GFX11-NEXT: v_perm_b32 v11, s0, s56, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 15
-; GFX11-NEXT: v_readlane_b32 s48, v23, 6
-; GFX11-NEXT: v_readlane_b32 s39, v23, 5
-; GFX11-NEXT: v_readlane_b32 s38, v23, 4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; GFX11-NEXT: v_perm_b32 v2, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 19
; GFX11-NEXT: v_readlane_b32 s1, v26, 11
-; GFX11-NEXT: v_readlane_b32 s37, v23, 3
-; GFX11-NEXT: v_readlane_b32 s36, v23, 2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX11-NEXT: v_perm_b32 v4, s10, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 17
-; GFX11-NEXT: v_readlane_b32 s35, v23, 1
-; GFX11-NEXT: v_readlane_b32 s34, v23, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s11, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 13
@@ -11416,53 +11311,45 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s46, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v4, s8, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-NEXT: v_lshl_or_b32 v4, v12, 16, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 12
; GFX11-NEXT: v_readlane_b32 s1, v26, 6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v5, s9, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v10
+; GFX11-NEXT: v_lshl_or_b32 v5, v10, 16, v5
; GFX11-NEXT: v_perm_b32 v11, s0, s44, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 9
; GFX11-NEXT: v_readlane_b32 s1, v26, 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v12, s6, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v10, v12, v11
+; GFX11-NEXT: v_lshl_or_b32 v10, v11, 16, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v14, s7, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v11, v14, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v12, s0, s42, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_perm_b32 v13, s4, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v12, v13, v12
+; GFX11-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX11-NEXT: v_perm_b32 v13, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s5, s0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v13, v1, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v1
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:80
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:96
@@ -13465,19 +13352,12 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v33, v62, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v63, v60, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v53, v58, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v51, v56, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v45, v44, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v49, v48, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr62
; VI-NEXT: ; implicit-def: $vgpr63
@@ -13498,21 +13378,18 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v16, v17, v16, s6
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13521,8 +13398,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13531,8 +13407,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13541,8 +13416,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13551,8 +13425,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13561,8 +13434,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13570,24 +13442,23 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v41, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v55, v34, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v61, v32, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v59, v54, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v57, v52, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v47, v38, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v35, v46, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_perm_b32 v14, v43, v50, s6
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: v_perm_b32 v15, v39, v42, s6
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr41
@@ -13612,8 +13483,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_or_b32_e32 v16, v16, v17
+; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13622,8 +13492,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; VI-NEXT: v_or_b32_e32 v17, v17, v18
+; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13632,8 +13501,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v18, v18, v19
+; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13642,8 +13510,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13652,8 +13519,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v20, v20, v21
+; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13662,8 +13528,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13672,8 +13537,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s6
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_or_b32_e32 v22, v22, v23
+; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13682,8 +13546,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13692,8 +13555,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_or_b32_e32 v24, v24, v25
+; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13702,8 +13564,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13712,8 +13573,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_or_b32_e32 v26, v26, v27
+; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13722,8 +13582,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13732,8 +13591,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v28, v28, v29
+; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13742,8 +13600,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13752,8 +13609,7 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v30, v30, v31
+; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13826,10 +13682,9 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_or_b32_e32 v31, v31, v32
+; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
@@ -17031,18 +16886,18 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
@@ -17065,28 +16920,28 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -17101,18 +16956,16 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
@@ -17131,28 +16984,27 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
@@ -17167,13 +17019,12 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
@@ -17196,28 +17047,27 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
@@ -17232,13 +17082,12 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v18, 16, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
@@ -17261,28 +17110,27 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
@@ -17297,13 +17145,12 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v21
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
@@ -17326,28 +17173,27 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
@@ -17362,12 +17208,11 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
@@ -18889,127 +18734,103 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB15_2
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s75
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s73
-; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s63
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s61
-; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s59
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s57
-; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s47
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s45
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s13
-; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s11
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s9
-; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s7
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s8, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v14, v13, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s6, v15, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v14, v13, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v52, v51, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v54, v53, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v48, v39, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v50, v49, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v36, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v38, v37, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v32, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v34, v33, s4
-; VI-NEXT: v_or_b32_e32 v15, v16, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; VI-NEXT: v_perm_b32 v16, v60, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: v_perm_b32 v17, v62, v61, s4
-; VI-NEXT: v_or_b32_e32 v16, v17, v16
+; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; VI-NEXT: v_perm_b32 v17, v59, v18, s4
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: v_perm_b32 v18, v41, v40, s4
-; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v18
; VI-NEXT: v_perm_b32 v18, v57, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v19, v42, v58, s4
-; VI-NEXT: v_or_b32_e32 v18, v19, v18
+; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; VI-NEXT: v_perm_b32 v19, v45, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: v_perm_b32 v20, v56, v47, s4
-; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; VI-NEXT: v_perm_b32 v20, v44, v21, s4
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: v_perm_b32 v21, v46, v26, s4
-; VI-NEXT: v_or_b32_e32 v20, v21, v20
+; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; VI-NEXT: v_perm_b32 v21, v31, v22, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: v_perm_b32 v22, v24, v43, s4
-; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; VI-NEXT: v_perm_b32 v22, v28, v23, s4
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; VI-NEXT: v_perm_b32 v23, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v22, v23, v22
-; VI-NEXT: v_perm_b32 v23, v25, v63, s4
; VI-NEXT: v_mov_b32_e32 v44, v24
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_perm_b32 v23, v25, v63, s4
; VI-NEXT: v_perm_b32 v24, v27, v55, s4
-; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v45, v26
@@ -19019,80 +18840,72 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v24, v25, v24, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
-; VI-NEXT: v_or_b32_e32 v24, v25, v24
+; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
-; VI-NEXT: v_or_b32_e32 v26, v27, v26
+; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
-; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v28, v29, v28
+; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
-; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
-; VI-NEXT: v_or_b32_e32 v30, v31, v30
+; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v43, v46, v43, s4
-; VI-NEXT: v_or_b32_e32 v31, v43, v31
+; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB15_3
; VI-NEXT: .LBB15_2:
@@ -19813,127 +19626,103 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB15_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
+; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
+; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v18
; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
+; GFX9-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
+; GFX9-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
+; GFX9-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX9-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
+; GFX9-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v45, v26
@@ -19943,80 +19732,72 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
+; GFX9-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
+; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
+; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
+; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
+; GFX9-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
+; GFX9-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
+; GFX9-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
+; GFX9-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB15_3
; GFX9-NEXT: .LBB15_2:
@@ -20556,56 +20337,49 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -20697,143 +20471,132 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB15_3
; GFX11-TRUE16-NEXT: .LBB15_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v8, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
-; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -21130,56 +20893,49 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -21271,143 +21027,132 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB15_3
; GFX11-FAKE16-NEXT: .LBB15_2: ; %cmp.true
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -40734,49 +40479,41 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v55, v57, v41, s4
; VI-NEXT: v_perm_b32 v1, v1, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v55
-; VI-NEXT: v_or_b32_e32 v1, v1, v48
+; VI-NEXT: v_lshl_or_b32 v1, v55, 16, v1
+; VI-NEXT: v_perm_b32 v2, v2, v53, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v34, v56, s4
-; VI-NEXT: v_perm_b32 v2, v2, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v47, v40, s4
; VI-NEXT: v_perm_b32 v2, v3, v38, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v46, v45, s4
; VI-NEXT: v_perm_b32 v1, v4, v52, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v46, v45, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v33, v39, s4
; VI-NEXT: v_perm_b32 v2, v5, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v44, v43, s4
; VI-NEXT: v_perm_b32 v1, v6, v51, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v44, v43, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v50, v54, s4
; VI-NEXT: v_perm_b32 v2, v7, v63, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v62, v61, s4
; VI-NEXT: v_perm_b32 v1, v8, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v62, v61, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -40784,14 +40521,12 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v49, s4
; VI-NEXT: v_perm_b32 v1, v60, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v59, v58, s4
; VI-NEXT: v_perm_b32 v1, v10, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v59, v58, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
@@ -40800,21 +40535,19 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v11, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v12, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -40823,21 +40556,19 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
@@ -40846,21 +40577,19 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -40869,21 +40598,19 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -40892,21 +40619,19 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
@@ -40916,19 +40641,17 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -40938,19 +40661,17 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v23, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v24, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
@@ -40960,74 +40681,70 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v26, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v27, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v27, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v28, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v29, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v29, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v30, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v31, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
@@ -41037,8 +40754,7 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v32, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -45053,55 +44769,46 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v33, v33, v41, s4
; VI-NEXT: v_perm_b32 v31, v31, v61, s4
-; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
-; VI-NEXT: v_or_b32_e32 v31, v31, v33
+; VI-NEXT: v_lshl_or_b32 v31, v33, 16, v31
+; VI-NEXT: v_perm_b32 v32, v32, v60, s4
; VI-NEXT: buffer_store_dword v31, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v31, v50, v59, s4
-; VI-NEXT: v_perm_b32 v32, v32, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v31, v32, v31
+; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v32
; VI-NEXT: v_add_u32_e32 v32, vcc, 4, v0
; VI-NEXT: buffer_store_dword v31, v32, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v31, v48, v40, s4
; VI-NEXT: v_perm_b32 v29, v29, v58, s4
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v29, v29, v31
+; VI-NEXT: v_lshl_or_b32 v29, v31, 16, v29
; VI-NEXT: v_add_u32_e32 v31, vcc, 8, v0
; VI-NEXT: buffer_store_dword v29, v31, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v29, v30, v52, s4
; VI-NEXT: v_perm_b32 v30, v56, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; VI-NEXT: v_add_u32_e32 v30, vcc, 12, v0
; VI-NEXT: buffer_store_dword v29, v30, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v29, v47, v39, s4
; VI-NEXT: v_perm_b32 v27, v27, v46, s4
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v27, v27, v29
+; VI-NEXT: v_lshl_or_b32 v27, v29, 16, v27
; VI-NEXT: v_add_u32_e32 v29, vcc, 16, v0
; VI-NEXT: buffer_store_dword v27, v29, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v27, v28, v45, s4
; VI-NEXT: v_perm_b32 v28, v43, v44, s4
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; VI-NEXT: v_add_u32_e32 v28, vcc, 20, v0
; VI-NEXT: buffer_store_dword v27, v28, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v27, v42, v54, s4
; VI-NEXT: v_perm_b32 v25, v25, v49, s4
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_or_b32_e32 v25, v25, v27
+; VI-NEXT: v_lshl_or_b32 v25, v27, 16, v25
; VI-NEXT: v_add_u32_e32 v27, vcc, 24, v0
; VI-NEXT: buffer_store_dword v25, v27, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v25, v26, v51, s4
; VI-NEXT: v_perm_b32 v26, v38, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; VI-NEXT: v_add_u32_e32 v26, vcc, 28, v0
; VI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v25, v37, v53, s4
; VI-NEXT: v_perm_b32 v23, v23, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_or_b32_e32 v23, v23, v25
+; VI-NEXT: v_lshl_or_b32 v23, v25, 16, v23
; VI-NEXT: v_add_u32_e32 v25, vcc, 32, v0
; VI-NEXT: buffer_store_dword v23, v25, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
@@ -45140,8 +44847,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s4
; VI-NEXT: v_perm_b32 v24, v34, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; VI-NEXT: v_add_u32_e32 v24, vcc, 36, v0
; VI-NEXT: buffer_store_dword v23, v24, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
@@ -45150,10 +44856,9 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s4
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v21, v24, s4
-; VI-NEXT: v_or_b32_e32 v21, v21, v23
+; VI-NEXT: v_lshl_or_b32 v21, v23, 16, v21
; VI-NEXT: v_add_u32_e32 v23, vcc, 40, v0
; VI-NEXT: buffer_store_dword v21, v23, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
@@ -45163,8 +44868,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v22, v23, s4
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; VI-NEXT: v_add_u32_e32 v22, vcc, 44, v0
; VI-NEXT: buffer_store_dword v21, v22, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
@@ -45173,10 +44877,9 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s4
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v19, v22, s4
-; VI-NEXT: v_or_b32_e32 v19, v19, v21
+; VI-NEXT: v_lshl_or_b32 v19, v21, 16, v19
; VI-NEXT: v_add_u32_e32 v21, vcc, 48, v0
; VI-NEXT: buffer_store_dword v19, v21, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
@@ -45186,8 +44889,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v20, v21, s4
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; VI-NEXT: v_add_u32_e32 v20, vcc, 52, v0
; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
@@ -45196,10 +44898,9 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s4
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v17, v20, s4
-; VI-NEXT: v_or_b32_e32 v17, v17, v19
+; VI-NEXT: v_lshl_or_b32 v17, v19, 16, v17
; VI-NEXT: v_add_u32_e32 v19, vcc, 56, v0
; VI-NEXT: buffer_store_dword v17, v19, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -45209,8 +44910,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v18, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; VI-NEXT: v_or_b32_e32 v17, v17, v18
+; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; VI-NEXT: v_add_u32_e32 v18, vcc, 60, v0
; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
@@ -45219,10 +44919,9 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s4
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v15, v18, s4
-; VI-NEXT: v_or_b32_e32 v15, v15, v17
+; VI-NEXT: v_lshl_or_b32 v15, v17, 16, v15
; VI-NEXT: v_add_u32_e32 v17, vcc, 64, v0
; VI-NEXT: buffer_store_dword v15, v17, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
@@ -45232,8 +44931,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v16, v16, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
@@ -45242,10 +44940,9 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s4
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v13, v16, s4
-; VI-NEXT: v_or_b32_e32 v13, v13, v15
+; VI-NEXT: v_lshl_or_b32 v13, v15, 16, v13
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v13, v15, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
@@ -45255,8 +44952,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v14, v14, v15, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
@@ -45267,8 +44963,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v14, v13, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_or_b32_e32 v11, v11, v13
+; VI-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
@@ -45278,8 +44973,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v12, v12, v13, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
@@ -45290,8 +44984,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v11, v12, v11, s4
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; VI-NEXT: v_or_b32_e32 v9, v9, v11
+; VI-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v9, v11, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
@@ -45301,8 +44994,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v10, v10, v11, s4
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -45313,8 +45005,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v9, v10, v9, s4
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v7, v7, v9
+; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
@@ -45324,8 +45015,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v9, s4
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -45336,8 +45026,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v5, v5, v7
+; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
@@ -45347,8 +45036,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v6, v7, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
@@ -45359,8 +45047,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v3, v3, v5
+; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
@@ -45370,8 +45057,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v4, v5, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -45382,8 +45068,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
@@ -45394,8 +45079,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -46292,7 +45976,9 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_perm_b32 v35, v51, v40, s4
; GFX9-NEXT: v_perm_b32 v55, v55, v42, s4
; GFX9-NEXT: v_perm_b32 v20, v48, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v20, v55, 16, v20
; GFX9-NEXT: v_perm_b32 v48, v52, v41, s4
+; GFX9-NEXT: v_lshl_or_b32 v18, v48, 16, v18
; GFX9-NEXT: v_perm_b32 v17, v36, v17, s4
; GFX9-NEXT: v_perm_b32 v33, v33, v61, s4
; GFX9-NEXT: v_perm_b32 v31, v31, v60, s4
@@ -46361,110 +46047,89 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v15, v15, v50, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v50, 16, v55
-; GFX9-NEXT: v_or_b32_e32 v20, v20, v50
; GFX9-NEXT: buffer_store_dword v20, v0, s[0:3], 0 offen
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v20, v20, v50, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX9-NEXT: v_or_b32_e32 v19, v19, v20
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; GFX9-NEXT: buffer_store_dword v19, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v48
-; GFX9-NEXT: v_or_b32_e32 v18, v18, v19
; GFX9-NEXT: buffer_store_dword v18, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v18, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v17, v17, v18
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v35
-; GFX9-NEXT: v_or_b32_e32 v17, v33, v17
+; GFX9-NEXT: v_lshl_or_b32 v17, v35, 16, v33
; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v17
+; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v34
-; GFX9-NEXT: v_or_b32_e32 v16, v31, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v34, 16, v31
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v32, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v32
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v36
-; GFX9-NEXT: v_or_b32_e32 v16, v29, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v36, 16, v29
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v30, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v30
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v37
-; GFX9-NEXT: v_or_b32_e32 v16, v27, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v37, 16, v27
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v28, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v28
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v38
-; GFX9-NEXT: v_or_b32_e32 v16, v25, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v38, 16, v25
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v26, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v26
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v39
-; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v39, 16, v23
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v24, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v24
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v49
-; GFX9-NEXT: v_or_b32_e32 v16, v21, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v49, 16, v21
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v22
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v15, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46473,8 +46138,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v14, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46484,8 +46148,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46494,8 +46157,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46505,8 +46167,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46515,8 +46176,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v10, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46526,8 +46186,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46536,8 +46195,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46547,8 +46205,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46557,8 +46214,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v6, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46568,8 +46224,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46578,8 +46233,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46589,8 +46243,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46599,8 +46252,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -47294,138 +46946,106 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: v_readlane_b32 s0, v77, 7
; GFX11-NEXT: v_mov_b32_e32 v70, s0
; GFX11-NEXT: .LBB37_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v67, v73, v67, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v66, v60, v66, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v33, v33, v72, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v34, v34, v63, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v68, v61, v62, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v66, v60, v66, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v57, v31, v57, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v67
-; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v66
; GFX11-NEXT: v_perm_b32 v58, v58, v59, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v34, v34, v63, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
-; GFX11-NEXT: v_or_b32_e32 v31, v33, v67
+; GFX11-NEXT: v_perm_b32 v56, v32, v56, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v31, v67, 16, v33
+; GFX11-NEXT: v_lshl_or_b32 v32, v68, 16, v34
; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v33, v57, v66
+; GFX11-NEXT: v_lshl_or_b32 v33, v66, 16, v57
+; GFX11-NEXT: v_perm_b32 v27, v27, v46, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v66, v44, v45, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v67, v40, v41, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v56, v32, v56, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v58, 16, v58
-; GFX11-NEXT: v_perm_b32 v53, v177, v53, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v32, v34, v68
-; GFX11-NEXT: v_perm_b32 v27, v27, v46, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v65
; GFX11-NEXT: v_perm_b32 v28, v28, v42, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v66
+; GFX11-NEXT: v_perm_b32 v67, v40, v41, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v68, v25, v183, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
; GFX11-NEXT: v_perm_b32 v182, v26, v182, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v67
-; GFX11-NEXT: v_or_b32_e32 v34, v56, v58
+; GFX11-NEXT: v_lshl_or_b32 v34, v58, 16, v56
+; GFX11-NEXT: v_perm_b32 v53, v177, v53, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v21, v21, v167, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-NEXT: v_or_b32_e32 v25, v27, v65
-; GFX11-NEXT: v_or_b32_e32 v26, v28, v66
-; GFX11-NEXT: v_or_b32_e32 v27, v68, v64
-; GFX11-NEXT: v_or_b32_e32 v28, v182, v67
+; GFX11-NEXT: v_lshl_or_b32 v25, v65, 16, v27
+; GFX11-NEXT: v_lshl_or_b32 v26, v66, 16, v28
+; GFX11-NEXT: v_lshl_or_b32 v27, v64, 16, v68
+; GFX11-NEXT: v_lshl_or_b32 v28, v67, 16, v182
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_store_b128 v0, v[31:34], off
; GFX11-NEXT: scratch_store_b128 v0, v[25:28], off offset:16
; GFX11-NEXT: v_perm_b32 v26, v165, v166, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v25, v21, v53
+; GFX11-NEXT: v_lshl_or_b32 v25, v53, 16, v21
; GFX11-NEXT: v_perm_b32 v21, v22, v164, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v163, v52, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v28, v151, v51, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v27, v161, v162, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX11-NEXT: v_perm_b32 v19, v19, v160, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-NEXT: v_perm_b32 v28, v151, v51, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v17, v17, v149, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-NEXT: v_perm_b32 v27, v161, v162, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v20, v20, v150, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_or_b32_e32 v26, v21, v26
-; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
+; GFX11-NEXT: v_lshl_or_b32 v26, v26, 16, v21
+; GFX11-NEXT: v_lshl_or_b32 v19, v22, 16, v19
; GFX11-NEXT: v_perm_b32 v22, v147, v148, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v21, v17, v28
+; GFX11-NEXT: v_lshl_or_b32 v21, v28, 16, v17
; GFX11-NEXT: v_perm_b32 v17, v18, v146, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v145, v50, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v28, v134, v49, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v20, v20, v27
-; GFX11-NEXT: v_perm_b32 v27, v135, v144, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v15, v15, v133, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v28, v134, v49, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v13, v13, v132, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-NEXT: v_lshl_or_b32 v20, v27, 16, v20
+; GFX11-NEXT: v_perm_b32 v27, v135, v144, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v16, v16, v131, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
-; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
+; GFX11-NEXT: v_lshl_or_b32 v22, v22, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v15
; GFX11-NEXT: v_perm_b32 v18, v129, v130, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v17, v13, v28
-; GFX11-NEXT: v_perm_b32 v28, v116, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v27
+; GFX11-NEXT: v_lshl_or_b32 v17, v28, 16, v13
; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v116, v38, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v9, v114, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v16, v27, 16, v16
; GFX11-NEXT: v_perm_b32 v14, v119, v48, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v27, v117, v118, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v9, v9, v114, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-NEXT: v_perm_b32 v11, v11, v115, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v113, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v28
+; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v28, 16, v9
; GFX11-NEXT: v_perm_b32 v9, v10, v102, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v101, v37, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
-; GFX11-NEXT: v_perm_b32 v14, v103, v112, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v27
-; GFX11-NEXT: v_perm_b32 v27, v99, v100, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v28, v98, v36, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v7, v7, v97, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v54, v181, v54, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v64, v179, v180, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-NEXT: v_perm_b32 v23, v23, v178, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v24, v176, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
+; GFX11-NEXT: v_perm_b32 v14, v103, v112, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v12, v27, 16, v12
+; GFX11-NEXT: v_perm_b32 v27, v99, v100, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v98, v36, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v8, v8, v87, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX11-NEXT: v_perm_b32 v5, v5, v96, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
; GFX11-NEXT: v_perm_b32 v10, v85, v86, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v23, v178, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT: v_perm_b32 v24, v24, v176, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v27
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v28
+; GFX11-NEXT: v_perm_b32 v6, v6, v80, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v23, v54, 16, v23
+; GFX11-NEXT: v_lshl_or_b32 v24, v64, 16, v24
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v27, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v9, v28, 16, v5
; GFX11-NEXT: v_perm_b32 v5, v84, v35, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v27, v81, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v28, v71, v29, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v29, v69, v70, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v80, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_or_b32_e32 v23, v23, v54
-; GFX11-NEXT: v_or_b32_e32 v24, v24, v64
-; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-NEXT: v_perm_b32 v29, v69, v70, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v30, v1, v30, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-NEXT: v_perm_b32 v31, v2, v39, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v27
-; GFX11-NEXT: v_or_b32_e32 v3, v30, v28
-; GFX11-NEXT: v_or_b32_e32 v4, v31, v29
+; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v27, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v28, 16, v30
+; GFX11-NEXT: v_lshl_or_b32 v4, v29, 16, v31
; GFX11-NEXT: s_clause 0x5
; GFX11-NEXT: scratch_store_b128 v0, v[23:26], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
@@ -49353,19 +48973,12 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v33, v62, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v63, v60, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v53, v58, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v51, v56, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v45, v44, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v49, v48, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr62
; VI-NEXT: ; implicit-def: $vgpr63
@@ -49386,21 +48999,18 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v16, v17, v16, s6
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49409,8 +49019,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49419,8 +49028,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49429,8 +49037,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49439,8 +49046,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49449,8 +49055,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49458,24 +49063,23 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v41, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v55, v34, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v61, v32, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v59, v54, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v57, v52, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v47, v38, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v35, v46, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_perm_b32 v14, v43, v50, s6
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: v_perm_b32 v15, v39, v42, s6
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr41
@@ -49500,8 +49104,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_or_b32_e32 v16, v16, v17
+; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49510,8 +49113,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; VI-NEXT: v_or_b32_e32 v17, v17, v18
+; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49520,8 +49122,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v18, v18, v19
+; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49530,8 +49131,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49540,8 +49140,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v20, v20, v21
+; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49550,8 +49149,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49560,8 +49158,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s6
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_or_b32_e32 v22, v22, v23
+; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49570,8 +49167,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49580,8 +49176,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_or_b32_e32 v24, v24, v25
+; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49590,8 +49185,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49600,8 +49194,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_or_b32_e32 v26, v26, v27
+; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49610,8 +49203,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49620,8 +49212,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v28, v28, v29
+; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49630,8 +49221,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49640,8 +49230,7 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v30, v30, v31
+; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49714,10 +49303,9 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_or_b32_e32 v31, v31, v32
+; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
@@ -52919,18 +52507,18 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
@@ -52953,28 +52541,28 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -52989,18 +52577,16 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
@@ -53019,28 +52605,27 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
@@ -53055,13 +52640,12 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
@@ -53084,28 +52668,27 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
@@ -53120,13 +52703,12 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v18, 16, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
@@ -53149,28 +52731,27 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
@@ -53185,13 +52766,12 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v21
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
@@ -53214,28 +52794,27 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
@@ -53250,12 +52829,11 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
@@ -54777,127 +54355,103 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB39_2
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s75
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s73
-; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s63
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s61
-; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s59
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s57
-; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s47
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s45
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s13
-; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s11
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s9
-; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s7
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s8, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v14, v13, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s6, v15, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v14, v13, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v52, v51, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v54, v53, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v48, v39, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v50, v49, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v36, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v38, v37, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v32, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v34, v33, s4
-; VI-NEXT: v_or_b32_e32 v15, v16, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; VI-NEXT: v_perm_b32 v16, v60, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: v_perm_b32 v17, v62, v61, s4
-; VI-NEXT: v_or_b32_e32 v16, v17, v16
+; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; VI-NEXT: v_perm_b32 v17, v59, v18, s4
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: v_perm_b32 v18, v41, v40, s4
-; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v18
; VI-NEXT: v_perm_b32 v18, v57, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v19, v42, v58, s4
-; VI-NEXT: v_or_b32_e32 v18, v19, v18
+; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; VI-NEXT: v_perm_b32 v19, v45, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: v_perm_b32 v20, v56, v47, s4
-; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; VI-NEXT: v_perm_b32 v20, v44, v21, s4
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: v_perm_b32 v21, v46, v26, s4
-; VI-NEXT: v_or_b32_e32 v20, v21, v20
+; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; VI-NEXT: v_perm_b32 v21, v31, v22, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: v_perm_b32 v22, v24, v43, s4
-; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; VI-NEXT: v_perm_b32 v22, v28, v23, s4
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; VI-NEXT: v_perm_b32 v23, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v22, v23, v22
-; VI-NEXT: v_perm_b32 v23, v25, v63, s4
; VI-NEXT: v_mov_b32_e32 v44, v24
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_perm_b32 v23, v25, v63, s4
; VI-NEXT: v_perm_b32 v24, v27, v55, s4
-; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v45, v26
@@ -54907,80 +54461,72 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; VI-NEXT: v_perm_b32 v24, v25, v24, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
-; VI-NEXT: v_or_b32_e32 v24, v25, v24
+; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
-; VI-NEXT: v_or_b32_e32 v26, v27, v26
+; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
-; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v28, v29, v28
+; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
-; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
-; VI-NEXT: v_or_b32_e32 v30, v31, v30
+; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v43, v46, v43, s4
-; VI-NEXT: v_or_b32_e32 v31, v43, v31
+; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB39_3
; VI-NEXT: .LBB39_2:
@@ -55701,127 +55247,103 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB39_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
+; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
+; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v18
; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
+; GFX9-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
+; GFX9-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
+; GFX9-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX9-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
+; GFX9-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v45, v26
@@ -55831,80 +55353,72 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
+; GFX9-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
+; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
+; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
+; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
+; GFX9-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
+; GFX9-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
+; GFX9-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
+; GFX9-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB39_3
; GFX9-NEXT: .LBB39_2:
@@ -56444,56 +55958,49 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -56585,143 +56092,132 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB39_3
; GFX11-TRUE16-NEXT: .LBB39_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v8, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
-; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -57018,56 +56514,49 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -57159,143 +56648,132 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB39_3
; GFX11-FAKE16-NEXT: .LBB39_2: ; %cmp.true
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -75484,49 +74962,41 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v55, v57, v41, s4
; VI-NEXT: v_perm_b32 v1, v1, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v55
-; VI-NEXT: v_or_b32_e32 v1, v1, v48
+; VI-NEXT: v_lshl_or_b32 v1, v55, 16, v1
+; VI-NEXT: v_perm_b32 v2, v2, v53, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v34, v56, s4
-; VI-NEXT: v_perm_b32 v2, v2, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v47, v40, s4
; VI-NEXT: v_perm_b32 v2, v3, v38, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v46, v45, s4
; VI-NEXT: v_perm_b32 v1, v4, v52, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v46, v45, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v33, v39, s4
; VI-NEXT: v_perm_b32 v2, v5, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v44, v43, s4
; VI-NEXT: v_perm_b32 v1, v6, v51, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v44, v43, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v50, v54, s4
; VI-NEXT: v_perm_b32 v2, v7, v63, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v62, v61, s4
; VI-NEXT: v_perm_b32 v1, v8, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v62, v61, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -75534,14 +75004,12 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v49, s4
; VI-NEXT: v_perm_b32 v1, v60, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v59, v58, s4
; VI-NEXT: v_perm_b32 v1, v10, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v59, v58, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
@@ -75550,21 +75018,19 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v11, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v12, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -75573,21 +75039,19 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
@@ -75596,21 +75060,19 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -75619,21 +75081,19 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -75642,21 +75102,19 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
@@ -75666,19 +75124,17 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -75688,19 +75144,17 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v23, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v24, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
@@ -75710,74 +75164,70 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v26, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v27, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v27, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v28, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v29, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v29, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v30, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v31, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
@@ -75787,8 +75237,7 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v32, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -79227,136 +78676,121 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24
; VI-NEXT: .LBB57_3: ; %end
; VI-NEXT: v_mov_b32_e32 v9, s48
-; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s82
-; VI-NEXT: v_perm_b32 v9, s53, v9, v1
+; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
+; VI-NEXT: v_mov_b32_e32 v4, s67
; VI-NEXT: v_perm_b32 v3, s16, v2, v1
+; VI-NEXT: v_perm_b32 v9, s53, v9, v1
; VI-NEXT: v_mov_b32_e32 v24, s83
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v4, s67
-; VI-NEXT: v_perm_b32 v24, s85, v24, v1
-; VI-NEXT: v_or_b32_e32 v3, v3, v9
; VI-NEXT: v_perm_b32 v2, s17, v4, v1
; VI-NEXT: v_mov_b32_e32 v13, s38
-; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v24
; VI-NEXT: v_mov_b32_e32 v4, s47
-; VI-NEXT: v_perm_b32 v13, s81, v13, v1
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
-; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
+; VI-NEXT: v_perm_b32 v24, s85, v24, v1
+; VI-NEXT: v_lshl_or_b32 v3, v9, 16, v3
+; VI-NEXT: v_mov_b32_e32 v6, s46
; VI-NEXT: v_perm_b32 v5, s18, v4, v1
+; VI-NEXT: v_perm_b32 v13, s81, v13, v1
; VI-NEXT: v_mov_b32_e32 v25, s80
-; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
-; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_perm_b32 v25, s87, v25, v1
-; VI-NEXT: v_or_b32_e32 v2, v5, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
+; VI-NEXT: v_mov_b32_e32 v26, s68
+; VI-NEXT: v_readlane_b32 s16, v33, 57
+; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v24, 16, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: v_perm_b32 v4, s19, v6, v1
; VI-NEXT: v_mov_b32_e32 v17, s36
-; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v25
; VI-NEXT: v_mov_b32_e32 v6, s69
-; VI-NEXT: v_perm_b32 v17, s84, v17, v1
-; VI-NEXT: v_or_b32_e32 v2, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
-; VI-NEXT: v_perm_b32 v7, s20, v6, v1
-; VI-NEXT: v_mov_b32_e32 v26, s68
-; VI-NEXT: v_readlane_b32 s16, v33, 57
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; VI-NEXT: v_mov_b32_e32 v8, s65
-; VI-NEXT: v_perm_b32 v26, s16, v26, v1
-; VI-NEXT: v_or_b32_e32 v2, v7, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
-; VI-NEXT: v_perm_b32 v6, s21, v8, v1
; VI-NEXT: v_mov_b32_e32 v19, s34
+; VI-NEXT: v_perm_b32 v25, s87, v25, v1
+; VI-NEXT: v_perm_b32 v26, s16, v26, v1
; VI-NEXT: v_readlane_b32 s16, v33, 56
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
-; VI-NEXT: v_mov_b32_e32 v8, s55
-; VI-NEXT: v_perm_b32 v19, s16, v19, v1
-; VI-NEXT: v_or_b32_e32 v2, v6, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
-; VI-NEXT: v_perm_b32 v10, s22, v8, v1
-; VI-NEXT: v_mov_b32_e32 v27, s71
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
-; VI-NEXT: v_mov_b32_e32 v11, s52
-; VI-NEXT: v_perm_b32 v27, s70, v27, v1
-; VI-NEXT: v_or_b32_e32 v2, v10, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
-; VI-NEXT: v_perm_b32 v8, s23, v11, v1
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v13, 16, v5
+; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
+; VI-NEXT: v_mov_b32_e32 v8, s65
+; VI-NEXT: v_perm_b32 v7, s20, v6, v1
; VI-NEXT: v_mov_b32_e32 v20, s30
+; VI-NEXT: v_perm_b32 v17, s84, v17, v1
+; VI-NEXT: v_perm_b32 v19, s16, v19, v1
; VI-NEXT: v_readlane_b32 s16, v33, 55
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
-; VI-NEXT: v_mov_b32_e32 v11, s54
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v25, 16, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
+; VI-NEXT: v_perm_b32 v6, s21, v8, v1
+; VI-NEXT: v_mov_b32_e32 v8, s55
; VI-NEXT: v_perm_b32 v20, s16, v20, v1
; VI-NEXT: v_readlane_b32 s16, v33, 53
-; VI-NEXT: v_or_b32_e32 v2, v8, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
-; VI-NEXT: v_perm_b32 v12, s24, v11, v1
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v17, 16, v7
+; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
+; VI-NEXT: v_mov_b32_e32 v11, s52
+; VI-NEXT: v_perm_b32 v10, s22, v8, v1
+; VI-NEXT: v_mov_b32_e32 v27, s71
; VI-NEXT: v_mov_b32_e32 v28, s16
; VI-NEXT: v_readlane_b32 s16, v33, 54
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
-; VI-NEXT: v_mov_b32_e32 v14, s66
-; VI-NEXT: v_perm_b32 v28, s16, v28, v1
-; VI-NEXT: v_or_b32_e32 v2, v12, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
-; VI-NEXT: v_perm_b32 v11, s25, v14, v1
+; VI-NEXT: v_lshl_or_b32 v2, v26, 16, v6
+; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
+; VI-NEXT: v_perm_b32 v8, s23, v11, v1
+; VI-NEXT: v_mov_b32_e32 v11, s54
; VI-NEXT: v_mov_b32_e32 v21, s90
+; VI-NEXT: v_perm_b32 v27, s70, v27, v1
+; VI-NEXT: v_perm_b32 v28, s16, v28, v1
; VI-NEXT: v_readlane_b32 s16, v33, 52
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v28
-; VI-NEXT: v_mov_b32_e32 v14, s51
+; VI-NEXT: v_lshl_or_b32 v2, v19, 16, v10
+; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
+; VI-NEXT: v_mov_b32_e32 v14, s66
+; VI-NEXT: v_perm_b32 v12, s24, v11, v1
; VI-NEXT: v_perm_b32 v21, s16, v21, v1
; VI-NEXT: v_readlane_b32 s16, v33, 50
-; VI-NEXT: v_or_b32_e32 v2, v11, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
-; VI-NEXT: v_perm_b32 v15, s26, v14, v1
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v27, 16, v8
+; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
+; VI-NEXT: v_perm_b32 v11, s25, v14, v1
+; VI-NEXT: v_mov_b32_e32 v14, s51
; VI-NEXT: v_mov_b32_e32 v29, s16
; VI-NEXT: v_readlane_b32 s16, v33, 51
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
+; VI-NEXT: v_lshl_or_b32 v2, v20, 16, v12
+; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
; VI-NEXT: v_mov_b32_e32 v16, s86
-; VI-NEXT: v_perm_b32 v29, s16, v29, v1
-; VI-NEXT: v_or_b32_e32 v2, v15, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
-; VI-NEXT: v_perm_b32 v14, s27, v16, v1
+; VI-NEXT: v_perm_b32 v15, s26, v14, v1
; VI-NEXT: v_mov_b32_e32 v22, s88
+; VI-NEXT: v_perm_b32 v29, s16, v29, v1
; VI-NEXT: v_readlane_b32 s16, v33, 49
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
+; VI-NEXT: v_lshl_or_b32 v2, v28, 16, v11
+; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
+; VI-NEXT: v_perm_b32 v14, s27, v16, v1
; VI-NEXT: v_mov_b32_e32 v16, s50
; VI-NEXT: v_perm_b32 v22, s16, v22, v1
; VI-NEXT: v_readlane_b32 s16, v33, 47
-; VI-NEXT: v_or_b32_e32 v2, v14, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v21, 16, v15
+; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
+; VI-NEXT: v_mov_b32_e32 v23, s64
; VI-NEXT: v_perm_b32 v18, s28, v16, v1
; VI-NEXT: v_mov_b32_e32 v30, s16
; VI-NEXT: v_readlane_b32 s16, v33, 48
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
-; VI-NEXT: v_mov_b32_e32 v23, s64
+; VI-NEXT: v_lshl_or_b32 v2, v29, 16, v14
+; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
+; VI-NEXT: v_perm_b32 v16, s29, v23, v1
; VI-NEXT: v_perm_b32 v30, s16, v30, v1
; VI-NEXT: v_readlane_b32 s16, v33, 46
-; VI-NEXT: v_or_b32_e32 v2, v18, v2
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v22, 16, v18
; VI-NEXT: v_add_u32_e32 v4, vcc, 48, v0
-; VI-NEXT: v_perm_b32 v16, s29, v23, v1
; VI-NEXT: v_mov_b32_e32 v23, s78
; VI-NEXT: v_mov_b32_e32 v31, s16
; VI-NEXT: v_readlane_b32 s16, v33, 45
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
-; VI-NEXT: v_perm_b32 v3, s16, v23, v1
-; VI-NEXT: v_or_b32_e32 v2, v16, v2
+; VI-NEXT: v_lshl_or_b32 v2, v30, 16, v16
; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
+; VI-NEXT: v_perm_b32 v3, s16, v23, v1
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, s44, v31, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: v_readlane_b32 s16, v33, 44
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79364,20 +78798,18 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 42
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 43
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s45, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 60, v0
; VI-NEXT: v_readlane_b32 s16, v33, 41
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s76
; VI-NEXT: v_readlane_b32 s16, v33, 40
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s42, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 64, v0
; VI-NEXT: v_readlane_b32 s16, v33, 39
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79385,20 +78817,18 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 37
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 38
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s43, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x44, v0
; VI-NEXT: v_readlane_b32 s16, v33, 36
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_readlane_b32 s16, v33, 35
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s40, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x48, v0
; VI-NEXT: v_readlane_b32 s16, v33, 34
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79406,10 +78836,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 32
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 33
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s41, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x4c, v0
; VI-NEXT: v_readlane_b32 s16, v33, 31
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79418,8 +78847,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: v_readlane_b32 s14, v33, 30
; VI-NEXT: v_perm_b32 v3, s14, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x50, v0
; VI-NEXT: v_readlane_b32 s14, v33, 29
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79427,10 +78855,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s14, v33, 27
; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_readlane_b32 s14, v33, 28
-; VI-NEXT: v_perm_b32 v3, s14, v3, v1
; VI-NEXT: v_perm_b32 v2, s15, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s14, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x54, v0
; VI-NEXT: v_readlane_b32 s14, v33, 26
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79439,8 +78866,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s62
; VI-NEXT: v_readlane_b32 s12, v33, 25
; VI-NEXT: v_perm_b32 v3, s12, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x58, v0
; VI-NEXT: v_readlane_b32 s12, v33, 24
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79448,10 +78874,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s12, v33, 22
; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_readlane_b32 s12, v33, 23
-; VI-NEXT: v_perm_b32 v3, s12, v3, v1
; VI-NEXT: v_perm_b32 v2, s13, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s12, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x5c, v0
; VI-NEXT: v_readlane_b32 s12, v33, 21
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79460,8 +78885,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s60
; VI-NEXT: v_readlane_b32 s10, v33, 20
; VI-NEXT: v_perm_b32 v3, s10, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x60, v0
; VI-NEXT: v_readlane_b32 s10, v33, 19
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79469,10 +78893,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s10, v33, 17
; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_readlane_b32 s10, v33, 18
-; VI-NEXT: v_perm_b32 v3, s10, v3, v1
; VI-NEXT: v_perm_b32 v2, s11, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s10, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x64, v0
; VI-NEXT: v_readlane_b32 s10, v33, 16
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79481,8 +78904,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s58
; VI-NEXT: v_readlane_b32 s8, v33, 15
; VI-NEXT: v_perm_b32 v3, s8, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x68, v0
; VI-NEXT: v_readlane_b32 s8, v33, 14
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79490,10 +78912,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s8, v33, 12
; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_readlane_b32 s8, v33, 13
-; VI-NEXT: v_perm_b32 v3, s8, v3, v1
; VI-NEXT: v_perm_b32 v2, s9, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s8, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x6c, v0
; VI-NEXT: v_readlane_b32 s8, v33, 11
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79502,8 +78923,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_readlane_b32 s6, v33, 10
; VI-NEXT: v_perm_b32 v3, s6, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x70, v0
; VI-NEXT: v_readlane_b32 s6, v33, 9
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79511,10 +78931,9 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s6, v33, 7
; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_readlane_b32 s6, v33, 8
-; VI-NEXT: v_perm_b32 v3, s6, v3, v1
; VI-NEXT: v_perm_b32 v2, s7, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s6, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x74, v0
; VI-NEXT: v_readlane_b32 s6, v33, 6
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79524,8 +78943,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_readlane_b32 s4, v33, 5
; VI-NEXT: v_perm_b32 v3, s4, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x78, v0
; VI-NEXT: v_readlane_b32 s4, v33, 4
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -79535,8 +78953,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s4, v33, 3
; VI-NEXT: v_perm_b32 v2, s5, v2, v1
; VI-NEXT: v_perm_b32 v1, s4, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_readlane_b32 s30, v32, 30
; VI-NEXT: v_readlane_b32 s7, v33, 1
@@ -80128,166 +79545,146 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24
; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24
; GFX9-NEXT: .LBB57_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v8, s36
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s85
-; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
-; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
-; GFX9-NEXT: v_mov_b32_e32 v21, s52
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v4, s71
-; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
+; GFX9-NEXT: v_mov_b32_e32 v21, s52
+; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
; GFX9-NEXT: v_perm_b32 v2, s17, v4, v1
; GFX9-NEXT: v_mov_b32_e32 v11, s34
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v21
; GFX9-NEXT: v_mov_b32_e32 v4, s69
-; GFX9-NEXT: v_perm_b32 v11, s54, v11, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
+; GFX9-NEXT: v_mov_b32_e32 v6, s68
; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
+; GFX9-NEXT: v_perm_b32 v11, s54, v11, v1
; GFX9-NEXT: v_mov_b32_e32 v22, s48
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v11
-; GFX9-NEXT: v_mov_b32_e32 v6, s68
-; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v21, 16, v2
; GFX9-NEXT: v_perm_b32 v4, s19, v6, v1
; GFX9-NEXT: v_mov_b32_e32 v14, s30
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; GFX9-NEXT: v_mov_b32_e32 v6, s70
-; GFX9-NEXT: v_perm_b32 v14, s39, v14, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshl_or_b32 v2, v11, 16, v5
+; GFX9-NEXT: v_mov_b32_e32 v9, s80
; GFX9-NEXT: v_perm_b32 v7, s20, v6, v1
+; GFX9-NEXT: v_perm_b32 v14, s39, v14, v1
; GFX9-NEXT: v_mov_b32_e32 v23, s49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v14
-; GFX9-NEXT: v_mov_b32_e32 v9, s80
-; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: v_lshl_or_b32 v2, v22, 16, v4
; GFX9-NEXT: v_perm_b32 v6, s21, v9, v1
; GFX9-NEXT: v_mov_b32_e32 v15, s94
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v9, s64
-; GFX9-NEXT: v_perm_b32 v15, s97, v15, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v6, v2
+; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: v_lshl_or_b32 v2, v14, 16, v7
+; GFX9-NEXT: v_mov_b32_e32 v12, s66
; GFX9-NEXT: v_perm_b32 v10, s22, v9, v1
+; GFX9-NEXT: v_perm_b32 v15, s97, v15, v1
; GFX9-NEXT: v_mov_b32_e32 v24, s98
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v15
-; GFX9-NEXT: v_mov_b32_e32 v12, s66
-; GFX9-NEXT: v_perm_b32 v24, s87, v24, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v10, v2
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: v_lshl_or_b32 v2, v23, 16, v6
; GFX9-NEXT: v_perm_b32 v9, s23, v12, v1
; GFX9-NEXT: v_mov_b32_e32 v16, s92
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v24
; GFX9-NEXT: v_mov_b32_e32 v12, s55
-; GFX9-NEXT: v_perm_b32 v16, s86, v16, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v9, v2
+; GFX9-NEXT: v_perm_b32 v24, s87, v24, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: v_lshl_or_b32 v2, v15, 16, v10
+; GFX9-NEXT: v_mov_b32_e32 v17, s65
; GFX9-NEXT: v_perm_b32 v13, s24, v12, v1
+; GFX9-NEXT: v_perm_b32 v16, s86, v16, v1
; GFX9-NEXT: v_mov_b32_e32 v25, s84
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v16
-; GFX9-NEXT: v_mov_b32_e32 v17, s65
-; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v13, v2
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: v_lshl_or_b32 v2, v24, 16, v9
; GFX9-NEXT: v_perm_b32 v12, s25, v17, v1
; GFX9-NEXT: v_mov_b32_e32 v17, s90
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v25
; GFX9-NEXT: v_mov_b32_e32 v18, s67
-; GFX9-NEXT: v_perm_b32 v17, s82, v17, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v12, v2
+; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: v_lshl_or_b32 v2, v16, 16, v13
+; GFX9-NEXT: v_mov_b32_e32 v8, s36
+; GFX9-NEXT: v_mov_b32_e32 v19, s53
; GFX9-NEXT: v_perm_b32 v18, s26, v18, v1
+; GFX9-NEXT: v_perm_b32 v17, s82, v17, v1
; GFX9-NEXT: v_mov_b32_e32 v26, s81
; GFX9-NEXT: v_readlane_b32 s16, v30, 49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; GFX9-NEXT: v_mov_b32_e32 v19, s53
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: v_lshl_or_b32 v2, v25, 16, v12
+; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
+; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
; GFX9-NEXT: v_perm_b32 v26, s16, v26, v1
; GFX9-NEXT: v_readlane_b32 s16, v30, 47
-; GFX9-NEXT: v_or_b32_e32 v2, v18, v2
-; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: v_lshl_or_b32 v2, v17, 16, v18
; GFX9-NEXT: v_mov_b32_e32 v20, s88
+; GFX9-NEXT: v_mov_b32_e32 v27, s83
; GFX9-NEXT: v_mov_b32_e32 v28, s16
+; GFX9-NEXT: v_lshl_or_b32 v3, v8, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 48
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v26
-; GFX9-NEXT: v_mov_b32_e32 v27, s83
+; GFX9-NEXT: v_lshl_or_b32 v2, v26, 16, v19
+; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v3, s16, v20, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v19, v2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_perm_b32 v2, s28, v27, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 45
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 46
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v2, s29, v28, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 44
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s78
; GFX9-NEXT: v_readlane_b32 s16, v30, 43
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s44, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 42
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 40
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 41
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s45, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 39
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s76
; GFX9-NEXT: v_readlane_b32 s16, v30, 38
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s42, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 37
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 35
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 36
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s43, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 34
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: v_readlane_b32 s16, v30, 33
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s40, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 32
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 30
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 31
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s41, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 29
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: v_mov_b32_e32 v2, s16
@@ -80295,18 +79692,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: v_readlane_b32 s14, v30, 28
; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s14, v30, 27
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: v_mov_b32_e32 v2, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 25
; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 26
-; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s15, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s14, v30, 24
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: v_mov_b32_e32 v2, s14
@@ -80314,18 +79709,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s62
; GFX9-NEXT: v_readlane_b32 s12, v30, 23
; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s12, v30, 22
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: v_mov_b32_e32 v2, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 20
; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 21
-; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s13, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s12, v30, 19
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: v_mov_b32_e32 v2, s12
@@ -80333,18 +79726,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s60
; GFX9-NEXT: v_readlane_b32 s10, v30, 18
; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s10, v30, 17
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: v_mov_b32_e32 v2, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 15
; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 16
-; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s11, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s10, v30, 14
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: v_mov_b32_e32 v2, s10
@@ -80352,18 +79743,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s58
; GFX9-NEXT: v_readlane_b32 s8, v30, 13
; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s8, v30, 12
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: v_mov_b32_e32 v2, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 10
; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 11
-; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s9, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s8, v30, 9
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: v_mov_b32_e32 v2, s8
@@ -80371,18 +79760,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_readlane_b32 s6, v30, 8
; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s6, v30, 7
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 5
; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 6
-; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s7, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s6, v30, 4
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: v_mov_b32_e32 v2, s6
@@ -80390,8 +79777,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: v_readlane_b32 s4, v30, 3
; GFX9-NEXT: v_perm_b32 v3, s4, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s4, v30, 2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_mov_b32_e32 v2, s4
@@ -80400,8 +79786,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_readlane_b32 s4, v30, 1
; GFX9-NEXT: v_perm_b32 v2, s5, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s4, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: v_readlane_b32 s30, v29, 34
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: v_readlane_b32 s31, v29, 35
@@ -80997,70 +80382,65 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: s_lshr_b64 s[42:43], s[4:5], 24
; GFX11-NEXT: .LBB57_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v2, s103, s30, v1
-; GFX11-NEXT: v_readlane_b32 s30, v24, 7
-; GFX11-NEXT: v_readlane_b32 s31, v24, 8
-; GFX11-NEXT: v_readlane_b32 s103, v24, 5
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_perm_b32 v18, s84, s83, v1
; GFX11-NEXT: v_perm_b32 v3, s0, s104, v1
; GFX11-NEXT: v_perm_b32 v4, s1, s102, v1
; GFX11-NEXT: v_perm_b32 v5, s100, s94, v1
-; GFX11-NEXT: v_perm_b32 v19, s81, s80, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-NEXT: v_perm_b32 v6, s2, s101, v1
; GFX11-NEXT: v_perm_b32 v7, s3, s99, v1
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX11-NEXT: v_perm_b32 v18, s84, s83, v1
+; GFX11-NEXT: v_perm_b32 v19, s81, s80, v1
; GFX11-NEXT: v_perm_b32 v8, s97, s92, v1
-; GFX11-NEXT: v_or_b32_e32 v3, v4, v18
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v19
-; GFX11-NEXT: v_perm_b32 v11, s86, s90, v1
-; GFX11-NEXT: v_perm_b32 v20, s71, s70, v1
-; GFX11-NEXT: v_perm_b32 v21, s67, s66, v1
-; GFX11-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX11-NEXT: v_or_b32_e32 v5, v7, v5
; GFX11-NEXT: v_perm_b32 v9, s16, s98, v1
; GFX11-NEXT: v_perm_b32 v10, s17, s96, v1
+; GFX11-NEXT: v_perm_b32 v11, s86, s90, v1
; GFX11-NEXT: v_perm_b32 v12, s18, s87, v1
; GFX11-NEXT: v_perm_b32 v13, s19, s85, v1
-; GFX11-NEXT: v_perm_b32 v22, s64, s55, v1
+; GFX11-NEXT: v_perm_b32 v20, s71, s70, v1
+; GFX11-NEXT: v_perm_b32 v21, s67, s66, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v18, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v4, v5, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v5, v19, 16, v7
+; GFX11-NEXT: v_readlane_b32 s0, v25, 6
+; GFX11-NEXT: v_readlane_b32 s1, v25, 4
+; GFX11-NEXT: v_readlane_b32 s30, v24, 7
+; GFX11-NEXT: v_readlane_b32 s31, v24, 8
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v20
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v21
+; GFX11-NEXT: v_lshl_or_b32 v2, v8, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v3, v20, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v4, v11, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v5, v21, 16, v13
+; GFX11-NEXT: v_readlane_b32 s104, v24, 6
+; GFX11-NEXT: v_readlane_b32 s103, v24, 5
+; GFX11-NEXT: v_readlane_b32 s102, v24, 4
+; GFX11-NEXT: v_readlane_b32 s101, v24, 3
+; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:16
+; GFX11-NEXT: v_perm_b32 v5, s50, s72, v1
+; GFX11-NEXT: v_readlane_b32 s100, v24, 2
+; GFX11-NEXT: v_readlane_b32 s99, v24, 1
+; GFX11-NEXT: v_readlane_b32 s98, v24, 0
+; GFX11-NEXT: v_readlane_b32 s97, v23, 31
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-NEXT: v_perm_b32 v8, s48, s39, v1
; GFX11-NEXT: v_perm_b32 v14, s82, s88, v1
-; GFX11-NEXT: v_perm_b32 v17, s21, s65, v1
-; GFX11-NEXT: v_or_b32_e32 v2, v9, v2
-; GFX11-NEXT: v_or_b32_e32 v3, v10, v3
-; GFX11-NEXT: v_or_b32_e32 v4, v12, v4
-; GFX11-NEXT: v_or_b32_e32 v5, v13, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v22
; GFX11-NEXT: v_perm_b32 v15, s69, s78, v1
; GFX11-NEXT: v_perm_b32 v16, s20, s68, v1
+; GFX11-NEXT: v_perm_b32 v17, s21, s65, v1
+; GFX11-NEXT: v_perm_b32 v22, s64, s55, v1
; GFX11-NEXT: v_perm_b32 v6, s53, s52, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v14
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:16
-; GFX11-NEXT: v_or_b32_e32 v3, v17, v8
-; GFX11-NEXT: v_perm_b32 v8, s48, s39, v1
; GFX11-NEXT: v_perm_b32 v9, s22, s54, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v15
-; GFX11-NEXT: v_or_b32_e32 v2, v16, v7
-; GFX11-NEXT: v_perm_b32 v5, s50, s72, v1
; GFX11-NEXT: v_perm_b32 v7, s23, s51, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v11, s25, s38, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_readlane_b32 s0, v25, 6
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-NEXT: v_or_b32_e32 v5, v7, v6
+; GFX11-NEXT: v_lshl_or_b32 v2, v14, 16, v16
+; GFX11-NEXT: v_lshl_or_b32 v3, v22, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v4, v15, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v7
; GFX11-NEXT: v_or_b32_e32 v7, v11, v8
; GFX11-NEXT: v_perm_b32 v11, s0, s74, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 3
-; GFX11-NEXT: v_readlane_b32 s1, v25, 4
; GFX11-NEXT: v_perm_b32 v9, s24, s49, v1
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:32
; GFX11-NEXT: v_perm_b32 v12, s37, s76, v1
@@ -81069,109 +80449,102 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: v_readlane_b32 s0, v25, 7
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_perm_b32 v10, s34, vcc_hi, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v8
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; GFX11-NEXT: v_perm_b32 v4, s28, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 5
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-NEXT: v_perm_b32 v9, s27, s35, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s29, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 1
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_readlane_b32 s1, v26, 31
; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
+; GFX11-NEXT: v_readlane_b32 s96, v23, 30
; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s62, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 2
-; GFX11-NEXT: v_readlane_b32 s104, v24, 6
; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:48
-; GFX11-NEXT: v_readlane_b32 s102, v24, 4
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
+; GFX11-NEXT: v_readlane_b32 s87, v23, 29
+; GFX11-NEXT: v_readlane_b32 s86, v23, 28
+; GFX11-NEXT: v_readlane_b32 s85, v23, 27
; GFX11-NEXT: v_perm_b32 v4, s40, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 30
-; GFX11-NEXT: v_readlane_b32 s101, v24, 3
-; GFX11-NEXT: v_readlane_b32 s100, v24, 2
-; GFX11-NEXT: v_readlane_b32 s99, v24, 1
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-NEXT: v_readlane_b32 s84, v23, 26
+; GFX11-NEXT: v_readlane_b32 s83, v23, 25
+; GFX11-NEXT: v_readlane_b32 s82, v23, 24
+; GFX11-NEXT: v_lshl_or_b32 v4, v12, 16, v4
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 0
; GFX11-NEXT: v_readlane_b32 s1, v26, 26
-; GFX11-NEXT: v_readlane_b32 s98, v24, 0
-; GFX11-NEXT: v_readlane_b32 s97, v23, 31
+; GFX11-NEXT: v_readlane_b32 s81, v23, 23
+; GFX11-NEXT: v_readlane_b32 s80, v23, 22
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v10
; GFX11-NEXT: v_perm_b32 v5, s41, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 28
-; GFX11-NEXT: v_readlane_b32 s96, v23, 30
-; GFX11-NEXT: v_readlane_b32 s87, v23, 29
-; GFX11-NEXT: v_readlane_b32 s86, v23, 28
+; GFX11-NEXT: v_readlane_b32 s71, v23, 21
+; GFX11-NEXT: v_readlane_b32 s70, v23, 20
+; GFX11-NEXT: v_readlane_b32 s69, v23, 19
; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-NEXT: v_perm_b32 v11, s0, s60, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 25
-; GFX11-NEXT: v_readlane_b32 s85, v23, 27
-; GFX11-NEXT: v_readlane_b32 s84, v23, 26
+; GFX11-NEXT: v_readlane_b32 s68, v23, 18
+; GFX11-NEXT: v_readlane_b32 s67, v23, 17
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:64
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v11
; GFX11-NEXT: v_perm_b32 v6, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 29
; GFX11-NEXT: v_readlane_b32 s1, v26, 21
-; GFX11-NEXT: v_readlane_b32 s83, v23, 25
-; GFX11-NEXT: v_readlane_b32 s82, v23, 24
+; GFX11-NEXT: v_readlane_b32 s66, v23, 16
+; GFX11-NEXT: v_readlane_b32 s65, v23, 15
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v6
; GFX11-NEXT: v_perm_b32 v8, s14, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 27
-; GFX11-NEXT: v_readlane_b32 s81, v23, 23
-; GFX11-NEXT: v_readlane_b32 s80, v23, 22
-; GFX11-NEXT: v_readlane_b32 s71, v23, 21
+; GFX11-NEXT: v_readlane_b32 s64, v23, 14
+; GFX11-NEXT: v_readlane_b32 s55, v23, 13
+; GFX11-NEXT: v_readlane_b32 s54, v23, 12
; GFX11-NEXT: v_or_b32_e32 v6, v8, v9
; GFX11-NEXT: v_perm_b32 v10, s15, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 23
-; GFX11-NEXT: v_readlane_b32 s70, v23, 20
-; GFX11-NEXT: v_readlane_b32 s69, v23, 19
-; GFX11-NEXT: v_readlane_b32 s68, v23, 18
+; GFX11-NEXT: v_readlane_b32 s53, v23, 11
+; GFX11-NEXT: v_readlane_b32 s52, v23, 10
+; GFX11-NEXT: v_readlane_b32 s51, v23, 9
; GFX11-NEXT: v_or_b32_e32 v7, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s58, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 24
-; GFX11-NEXT: v_readlane_b32 s67, v23, 17
-; GFX11-NEXT: v_readlane_b32 s66, v23, 16
-; GFX11-NEXT: v_readlane_b32 s65, v23, 15
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
+; GFX11-NEXT: v_readlane_b32 s50, v23, 8
+; GFX11-NEXT: v_readlane_b32 s49, v23, 7
+; GFX11-NEXT: v_readlane_b32 s48, v23, 6
+; GFX11-NEXT: v_readlane_b32 s39, v23, 5
; GFX11-NEXT: v_perm_b32 v8, s12, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 20
-; GFX11-NEXT: v_readlane_b32 s64, v23, 14
-; GFX11-NEXT: v_readlane_b32 s55, v23, 13
-; GFX11-NEXT: v_readlane_b32 s54, v23, 12
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-NEXT: v_readlane_b32 s38, v23, 4
+; GFX11-NEXT: v_readlane_b32 s37, v23, 3
+; GFX11-NEXT: v_readlane_b32 s36, v23, 2
+; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v8
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 22
; GFX11-NEXT: v_readlane_b32 s1, v26, 16
-; GFX11-NEXT: v_readlane_b32 s53, v23, 11
-; GFX11-NEXT: v_readlane_b32 s52, v23, 10
+; GFX11-NEXT: v_readlane_b32 s35, v23, 1
+; GFX11-NEXT: v_readlane_b32 s34, v23, 0
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; GFX11-NEXT: v_perm_b32 v9, s13, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 18
-; GFX11-NEXT: v_readlane_b32 s51, v23, 9
-; GFX11-NEXT: v_readlane_b32 s50, v23, 8
-; GFX11-NEXT: v_readlane_b32 s49, v23, 7
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
; GFX11-NEXT: v_perm_b32 v11, s0, s56, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 15
-; GFX11-NEXT: v_readlane_b32 s48, v23, 6
-; GFX11-NEXT: v_readlane_b32 s39, v23, 5
-; GFX11-NEXT: v_readlane_b32 s38, v23, 4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; GFX11-NEXT: v_perm_b32 v2, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 19
; GFX11-NEXT: v_readlane_b32 s1, v26, 11
-; GFX11-NEXT: v_readlane_b32 s37, v23, 3
-; GFX11-NEXT: v_readlane_b32 s36, v23, 2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX11-NEXT: v_perm_b32 v4, s10, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 17
-; GFX11-NEXT: v_readlane_b32 s35, v23, 1
-; GFX11-NEXT: v_readlane_b32 s34, v23, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s11, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 13
@@ -81179,53 +80552,45 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s46, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v4, s8, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-NEXT: v_lshl_or_b32 v4, v12, 16, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 12
; GFX11-NEXT: v_readlane_b32 s1, v26, 6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v5, s9, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v10
+; GFX11-NEXT: v_lshl_or_b32 v5, v10, 16, v5
; GFX11-NEXT: v_perm_b32 v11, s0, s44, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 9
; GFX11-NEXT: v_readlane_b32 s1, v26, 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v10
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v12, s6, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v10, v12, v11
+; GFX11-NEXT: v_lshl_or_b32 v10, v11, 16, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v14, s7, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v11, v14, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v12, s0, s42, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_perm_b32 v13, s4, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v12, v13, v12
+; GFX11-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX11-NEXT: v_perm_b32 v13, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s5, s0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v13, v1, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v1
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:80
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:96
@@ -83228,19 +82593,12 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v33, v62, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v63, v60, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v53, v58, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v51, v56, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v45, v44, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v49, v48, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr62
; VI-NEXT: ; implicit-def: $vgpr63
@@ -83261,21 +82619,18 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v16, v17, v16, s6
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83284,8 +82639,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83294,8 +82648,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83304,8 +82657,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83314,8 +82666,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83324,8 +82675,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83333,24 +82683,23 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v41, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v55, v34, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v61, v32, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v59, v54, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v57, v52, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v47, v38, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v35, v46, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_perm_b32 v14, v43, v50, s6
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: v_perm_b32 v15, v39, v42, s6
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr41
@@ -83375,8 +82724,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_or_b32_e32 v16, v16, v17
+; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83385,8 +82733,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; VI-NEXT: v_or_b32_e32 v17, v17, v18
+; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83395,8 +82742,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v18, v18, v19
+; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83405,8 +82751,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83415,8 +82760,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v20, v20, v21
+; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83425,8 +82769,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83435,8 +82778,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s6
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_or_b32_e32 v22, v22, v23
+; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83445,8 +82787,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83455,8 +82796,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_or_b32_e32 v24, v24, v25
+; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83465,8 +82805,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83475,8 +82814,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_or_b32_e32 v26, v26, v27
+; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83485,8 +82823,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83495,8 +82832,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v28, v28, v29
+; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83505,8 +82841,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83515,8 +82850,7 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v30, v30, v31
+; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -83589,10 +82923,9 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_or_b32_e32 v31, v31, v32
+; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
@@ -86794,18 +86127,18 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
@@ -86828,28 +86161,28 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -86864,18 +86197,16 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
@@ -86894,28 +86225,27 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
@@ -86930,13 +86260,12 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
@@ -86959,28 +86288,27 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
@@ -86995,13 +86323,12 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v18, 16, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
@@ -87024,28 +86351,27 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
@@ -87060,13 +86386,12 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v21
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
@@ -87089,28 +86414,27 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
@@ -87125,12 +86449,11 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
@@ -88652,127 +87975,103 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB59_2
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s75
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s73
-; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s63
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s61
-; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s59
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s57
-; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s47
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s45
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s13
-; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s11
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s9
-; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s7
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s8, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v14, v13, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s6, v15, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v14, v13, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v52, v51, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v54, v53, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v48, v39, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v50, v49, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v36, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v38, v37, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v32, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v34, v33, s4
-; VI-NEXT: v_or_b32_e32 v15, v16, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; VI-NEXT: v_perm_b32 v16, v60, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: v_perm_b32 v17, v62, v61, s4
-; VI-NEXT: v_or_b32_e32 v16, v17, v16
+; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; VI-NEXT: v_perm_b32 v17, v59, v18, s4
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: v_perm_b32 v18, v41, v40, s4
-; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v18
; VI-NEXT: v_perm_b32 v18, v57, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v19, v42, v58, s4
-; VI-NEXT: v_or_b32_e32 v18, v19, v18
+; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; VI-NEXT: v_perm_b32 v19, v45, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: v_perm_b32 v20, v56, v47, s4
-; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; VI-NEXT: v_perm_b32 v20, v44, v21, s4
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: v_perm_b32 v21, v46, v26, s4
-; VI-NEXT: v_or_b32_e32 v20, v21, v20
+; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; VI-NEXT: v_perm_b32 v21, v31, v22, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: v_perm_b32 v22, v24, v43, s4
-; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; VI-NEXT: v_perm_b32 v22, v28, v23, s4
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; VI-NEXT: v_perm_b32 v23, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v22, v23, v22
-; VI-NEXT: v_perm_b32 v23, v25, v63, s4
; VI-NEXT: v_mov_b32_e32 v44, v24
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_perm_b32 v23, v25, v63, s4
; VI-NEXT: v_perm_b32 v24, v27, v55, s4
-; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v45, v26
@@ -88782,80 +88081,72 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v24, v25, v24, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
-; VI-NEXT: v_or_b32_e32 v24, v25, v24
+; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
-; VI-NEXT: v_or_b32_e32 v26, v27, v26
+; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
-; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v28, v29, v28
+; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
-; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
-; VI-NEXT: v_or_b32_e32 v30, v31, v30
+; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v43, v46, v43, s4
-; VI-NEXT: v_or_b32_e32 v31, v43, v31
+; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB59_3
; VI-NEXT: .LBB59_2:
@@ -89576,127 +88867,103 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB59_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
+; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
+; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v18
; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
+; GFX9-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
+; GFX9-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
+; GFX9-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX9-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
+; GFX9-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v45, v26
@@ -89706,80 +88973,72 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
+; GFX9-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
+; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
+; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
+; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
+; GFX9-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
+; GFX9-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
+; GFX9-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
+; GFX9-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB59_3
; GFX9-NEXT: .LBB59_2:
@@ -90319,56 +89578,49 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -90460,143 +89712,132 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB59_3
; GFX11-TRUE16-NEXT: .LBB59_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v8, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
-; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -90893,56 +90134,49 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -91034,143 +90268,132 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB59_3
; GFX11-FAKE16-NEXT: .LBB59_2: ; %cmp.true
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -107525,37 +106748,31 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v55, v55, v41, s4
; VI-NEXT: v_perm_b32 v1, v1, v47, s4
+; VI-NEXT: v_lshl_or_b32 v1, v55, 16, v1
; VI-NEXT: v_perm_b32 v2, v2, v54, s4
-; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v55
-; VI-NEXT: v_or_b32_e32 v1, v1, v54
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v48, v46, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v53, v40, s4
; VI-NEXT: v_perm_b32 v2, v3, v45, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v44, v38, s4
; VI-NEXT: v_perm_b32 v1, v4, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v44, v38, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v52, v39, s4
; VI-NEXT: v_perm_b32 v2, v5, v43, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v62, v37, s4
; VI-NEXT: v_perm_b32 v1, v6, v63, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v62, v37, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
@@ -107563,14 +106780,12 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v7, v51, s4
; VI-NEXT: v_perm_b32 v1, v33, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v60, v59, s4
; VI-NEXT: v_perm_b32 v1, v8, v61, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v60, v59, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -107578,14 +106793,12 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v50, s4
; VI-NEXT: v_perm_b32 v1, v36, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v35, v49, s4
; VI-NEXT: v_perm_b32 v1, v10, v58, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v35, v49, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
@@ -107594,19 +106807,17 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: v_perm_b32 v2, v11, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v12, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -107615,21 +106826,19 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
@@ -107638,21 +106847,19 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
@@ -107661,21 +106868,19 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
@@ -107684,21 +106889,19 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -107709,19 +106912,17 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
@@ -107731,19 +106932,17 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v23, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v24, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
@@ -107753,30 +106952,28 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v26, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v27, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v27, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
@@ -107785,41 +106982,39 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v28, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v56, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v29, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v29, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v30, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v31, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -107829,8 +107024,7 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v32, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -111873,13 +111067,11 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v41, v45, v42, s4
; VI-NEXT: v_perm_b32 v31, v31, v46, s4
+; VI-NEXT: v_lshl_or_b32 v31, v41, 16, v31
; VI-NEXT: v_perm_b32 v32, v32, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v41
-; VI-NEXT: v_or_b32_e32 v31, v31, v36
; VI-NEXT: buffer_store_dword v31, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v31, v55, v61, s4
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v31, v32, v31
+; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v32
; VI-NEXT: v_add_u32_e32 v32, vcc, 4, v0
; VI-NEXT: buffer_store_dword v31, v32, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
@@ -111920,28 +111112,24 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v29, v29, v31
+; VI-NEXT: v_lshl_or_b32 v29, v31, 16, v29
; VI-NEXT: v_add_u32_e32 v31, vcc, 8, v0
; VI-NEXT: buffer_store_dword v29, v31, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v29, v30, v60, s4
; VI-NEXT: v_perm_b32 v30, v40, v59, s4
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; VI-NEXT: v_add_u32_e32 v30, vcc, 12, v0
; VI-NEXT: buffer_store_dword v29, v30, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v29, v50, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v27, v27, v29
+; VI-NEXT: v_lshl_or_b32 v27, v29, 16, v27
; VI-NEXT: v_add_u32_e32 v29, vcc, 16, v0
; VI-NEXT: buffer_store_dword v27, v29, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v27, v28, v49, s4
; VI-NEXT: v_perm_b32 v28, v58, v39, s4
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; VI-NEXT: v_add_u32_e32 v28, vcc, 20, v0
; VI-NEXT: buffer_store_dword v27, v28, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
@@ -111950,16 +111138,14 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v25, v28, s4
-; VI-NEXT: v_or_b32_e32 v25, v25, v27
+; VI-NEXT: v_lshl_or_b32 v25, v27, 16, v25
; VI-NEXT: v_add_u32_e32 v27, vcc, 24, v0
; VI-NEXT: buffer_store_dword v25, v27, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v25, v26, v35, s4
; VI-NEXT: v_perm_b32 v26, v57, v54, s4
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; VI-NEXT: v_add_u32_e32 v26, vcc, 28, v0
; VI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -111968,16 +111154,14 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v23, v26, s4
-; VI-NEXT: v_or_b32_e32 v23, v23, v25
+; VI-NEXT: v_lshl_or_b32 v23, v25, 16, v23
; VI-NEXT: v_add_u32_e32 v25, vcc, 32, v0
; VI-NEXT: buffer_store_dword v23, v25, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v23, v24, v48, s4
; VI-NEXT: v_perm_b32 v24, v56, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; VI-NEXT: v_add_u32_e32 v24, vcc, 36, v0
; VI-NEXT: buffer_store_dword v23, v24, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
@@ -111986,16 +111170,14 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s4
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v21, v24, s4
-; VI-NEXT: v_or_b32_e32 v21, v21, v23
+; VI-NEXT: v_lshl_or_b32 v21, v23, 16, v21
; VI-NEXT: v_add_u32_e32 v23, vcc, 40, v0
; VI-NEXT: buffer_store_dword v21, v23, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v21, v22, v47, s4
; VI-NEXT: v_perm_b32 v22, v38, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; VI-NEXT: v_add_u32_e32 v22, vcc, 44, v0
; VI-NEXT: buffer_store_dword v21, v22, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
@@ -112004,16 +111186,14 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s4
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v19, v22, s4
-; VI-NEXT: v_or_b32_e32 v19, v19, v21
+; VI-NEXT: v_lshl_or_b32 v19, v21, 16, v19
; VI-NEXT: v_add_u32_e32 v21, vcc, 48, v0
; VI-NEXT: buffer_store_dword v19, v21, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v19, v20, v52, s4
; VI-NEXT: v_perm_b32 v20, v37, v51, s4
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; VI-NEXT: v_add_u32_e32 v20, vcc, 52, v0
; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
@@ -112022,10 +111202,9 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s4
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v17, v20, s4
-; VI-NEXT: v_or_b32_e32 v17, v17, v19
+; VI-NEXT: v_lshl_or_b32 v17, v19, 16, v17
; VI-NEXT: v_add_u32_e32 v19, vcc, 56, v0
; VI-NEXT: buffer_store_dword v17, v19, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
@@ -112035,8 +111214,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; VI-NEXT: v_or_b32_e32 v17, v17, v18
+; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; VI-NEXT: v_add_u32_e32 v18, vcc, 60, v0
; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
@@ -112045,10 +111223,9 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s4
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v15, v18, s4
-; VI-NEXT: v_or_b32_e32 v15, v15, v17
+; VI-NEXT: v_lshl_or_b32 v15, v17, 16, v15
; VI-NEXT: v_add_u32_e32 v17, vcc, 64, v0
; VI-NEXT: buffer_store_dword v15, v17, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
@@ -112058,8 +111235,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v16, v17, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
@@ -112068,10 +111244,9 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s4
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v11, v11, v16, s4
-; VI-NEXT: v_or_b32_e32 v11, v11, v15
+; VI-NEXT: v_lshl_or_b32 v11, v15, 16, v11
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v11, v15, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -112081,8 +111256,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v12, v15, v12, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -112093,8 +111267,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v11, v11, v15, s4
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; VI-NEXT: v_or_b32_e32 v9, v9, v11
+; VI-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v9, v11, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
@@ -112104,8 +111277,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v10, v11, v10, s4
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -112116,8 +111288,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v9, v9, v10, s4
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v7, v7, v9
+; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
@@ -112127,8 +111298,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v9, v8, s4
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
@@ -112139,8 +111309,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v7, v7, v8, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v5, v5, v7
+; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
@@ -112150,8 +111319,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
@@ -112162,8 +111330,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v5, v5, v6, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v3, v3, v5
+; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
@@ -112173,8 +111340,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -112185,8 +111351,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v3, v3, v4, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
@@ -112196,31 +111361,29 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_perm_b32 v1, v13, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_perm_b32 v1, v13, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -113129,14 +112292,12 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v48, v48, v60, s4
-; GFX9-NEXT: v_perm_b32 v25, v41, v25, s4
; GFX9-NEXT: v_perm_b32 v37, v37, v44, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX9-NEXT: v_or_b32_e32 v25, v37, v25
+; GFX9-NEXT: v_perm_b32 v25, v41, v25, s4
+; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v37
; GFX9-NEXT: v_perm_b32 v26, v26, v42, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: v_perm_b32 v38, v38, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v26, v39, v26
+; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v39
; GFX9-NEXT: v_perm_b32 v24, v24, v58, s4
; GFX9-NEXT: v_perm_b32 v22, v22, v55, s4
; GFX9-NEXT: v_readlane_b32 s30, v63, 34
@@ -113186,6 +112347,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_perm_b32 v45, v59, v52, s4
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v48, v45, 16, v48
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v35, v15, v19, s4
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
@@ -113195,6 +112357,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_perm_b32 v56, v56, v59, s4
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v38, v56, 16, v38
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v19, v51, v19, s4
; GFX9-NEXT: v_perm_b32 v32, v32, v15, s4
@@ -113236,86 +112399,67 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v15, v15, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v45
; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX9-NEXT: v_or_b32_e32 v48, v48, v51
-; GFX9-NEXT: v_or_b32_e32 v25, v34, v25
-; GFX9-NEXT: buffer_store_dword v48, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v48, v43, v61, s4
+; GFX9-NEXT: v_lshl_or_b32 v25, v27, 16, v34
; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v25, v47, v54, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v48
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX9-NEXT: v_or_b32_e32 v48, v49, v48
-; GFX9-NEXT: v_or_b32_e32 v25, v30, v25
-; GFX9-NEXT: buffer_store_dword v48, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v56
+; GFX9-NEXT: buffer_store_dword v48, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v48, v43, v61, s4
+; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v30
+; GFX9-NEXT: v_lshl_or_b32 v48, v48, 16, v49
; GFX9-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v40
+; GFX9-NEXT: v_lshl_or_b32 v26, v40, 16, v36
; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v35
-; GFX9-NEXT: v_or_b32_e32 v38, v38, v48
-; GFX9-NEXT: v_or_b32_e32 v26, v36, v26
-; GFX9-NEXT: v_or_b32_e32 v25, v32, v25
+; GFX9-NEXT: v_lshl_or_b32 v25, v35, 16, v32
+; GFX9-NEXT: buffer_store_dword v48, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v38, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v31, v25, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v25
+; GFX9-NEXT: v_lshl_or_b32 v16, v25, 16, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19
-; GFX9-NEXT: v_or_b32_e32 v16, v20, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v19, 16, v20
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v19, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v28, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v28
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v29, 16, v23
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v19, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v24, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v24
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v33
-; GFX9-NEXT: v_or_b32_e32 v16, v21, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v33, 16, v21
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v19, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v22
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v50
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v50, 16, v17
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v17, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v18, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v18
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v15, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113324,8 +112468,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113335,8 +112478,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v13
+; GFX9-NEXT: v_lshl_or_b32 v9, v13, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113345,8 +112487,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v13, v10, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113356,8 +112497,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113366,8 +112506,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113377,8 +112516,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v7, v7, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113387,8 +112525,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113398,8 +112535,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v5, v6, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113408,8 +112544,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113419,8 +112554,7 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v3, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -113429,28 +112563,27 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_perm_b32 v1, v11, v1, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v57, v2, s4
-; GFX9-NEXT: v_perm_b32 v1, v11, v1, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_perm_b32 v1, v12, v1, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v1, v12, v1, s4
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -114133,135 +113266,108 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v69, v41, v69, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v48, v48, v42, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v49, v49, v73, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v70, v72, v63, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v68, v181, v68, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v181, v62, v60, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
-; GFX11-NEXT: v_perm_b32 v49, v49, v73, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v70
-; GFX11-NEXT: v_perm_b32 v35, v35, v180, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v180, 16, v181
-; GFX11-NEXT: v_or_b32_e32 v60, v48, v69
+; GFX11-NEXT: v_lshl_or_b32 v60, v69, 16, v48
; GFX11-NEXT: v_perm_b32 v48, v178, v67, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v61, v49, v70
+; GFX11-NEXT: v_perm_b32 v35, v35, v180, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v61, v70, 16, v49
+; GFX11-NEXT: v_lshl_or_b32 v63, v181, 16, v36
; GFX11-NEXT: v_perm_b32 v49, v56, v46, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v63, v36, v180
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v48
; GFX11-NEXT: v_perm_b32 v48, v166, v66, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v62, v68, 16, v35
+; GFX11-NEXT: v_perm_b32 v35, v59, v58, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v31, v31, v177, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v27, v27, v165, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; GFX11-NEXT: v_perm_b32 v28, v28, v47, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v49, 16, v49
-; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v48
-; GFX11-NEXT: v_or_b32_e32 v62, v35, v68
-; GFX11-NEXT: v_perm_b32 v35, v59, v58, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v32, v57, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; GFX11-NEXT: v_or_b32_e32 v66, v31, v36
-; GFX11-NEXT: v_or_b32_e32 v69, v28, v49
; GFX11-NEXT: v_or_b32_e32 v68, v27, v48
; GFX11-NEXT: v_perm_b32 v27, v161, v65, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v69, v28, v49
; GFX11-NEXT: v_perm_b32 v28, v45, v44, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v31, v151, v64, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v32, v32, v57, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v35
; GFX11-NEXT: v_perm_b32 v23, v23, v160, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-NEXT: v_perm_b32 v31, v151, v64, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v24, v43, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-NEXT: v_perm_b32 v21, v21, v149, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX11-NEXT: v_or_b32_e32 v67, v32, v35
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_store_b128 v0, v[60:63], off
; GFX11-NEXT: scratch_store_b128 v0, v[66:69], off offset:16
-; GFX11-NEXT: v_or_b32_e32 v64, v23, v27
+; GFX11-NEXT: v_lshl_or_b32 v64, v27, 16, v23
; GFX11-NEXT: v_perm_b32 v23, v40, v182, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v65, v24, v28
-; GFX11-NEXT: v_or_b32_e32 v66, v21, v31
+; GFX11-NEXT: v_lshl_or_b32 v65, v28, 16, v24
+; GFX11-NEXT: v_lshl_or_b32 v66, v31, 16, v21
; GFX11-NEXT: v_perm_b32 v21, v22, v183, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v146, v54, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v179, v176, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v27, v133, v53, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v19, v19, v135, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-NEXT: v_perm_b32 v27, v133, v53, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v20, v20, v167, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v17, v17, v132, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_or_b32_e32 v67, v21, v23
-; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
+; GFX11-NEXT: v_lshl_or_b32 v67, v23, 16, v21
+; GFX11-NEXT: v_lshl_or_b32 v19, v22, 16, v19
; GFX11-NEXT: v_perm_b32 v22, v164, v162, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v20, v20, v24
-; GFX11-NEXT: v_or_b32_e32 v21, v17, v27
+; GFX11-NEXT: v_lshl_or_b32 v20, v24, 16, v20
+; GFX11-NEXT: v_lshl_or_b32 v21, v27, 16, v17
; GFX11-NEXT: v_perm_b32 v17, v18, v163, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v128, v52, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v118, v51, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v150, v148, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v15, v15, v119, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v24, v118, v51, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v13, v13, v117, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-NEXT: v_perm_b32 v23, v150, v148, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v16, v16, v147, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
-; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
+; GFX11-NEXT: v_lshl_or_b32 v22, v22, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v15
; GFX11-NEXT: v_perm_b32 v18, v145, v134, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v17, v13, v24
-; GFX11-NEXT: v_perm_b32 v24, v100, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v23
+; GFX11-NEXT: v_lshl_or_b32 v17, v24, 16, v13
; GFX11-NEXT: v_perm_b32 v13, v14, v144, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v100, v38, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v9, v99, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v16, v23, 16, v16
; GFX11-NEXT: v_perm_b32 v14, v113, v50, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v131, v130, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v9, v9, v99, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v11, v11, v112, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v129, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v24
+; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v24, 16, v9
; GFX11-NEXT: v_perm_b32 v9, v10, v115, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v96, v37, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
+; GFX11-NEXT: v_perm_b32 v7, v7, v87, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
; GFX11-NEXT: v_perm_b32 v14, v116, v114, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v23
+; GFX11-NEXT: v_lshl_or_b32 v12, v23, 16, v12
; GFX11-NEXT: v_perm_b32 v23, v103, v102, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v85, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v87, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v101, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v5, v5, v84, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
; GFX11-NEXT: v_perm_b32 v10, v98, v97, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v23
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v24
+; GFX11-NEXT: v_perm_b32 v6, v6, v86, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v23, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v9, v24, 16, v5
; GFX11-NEXT: v_perm_b32 v5, v80, v29, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v71, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v83, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v30, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v55, v39, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v86, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v71, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v81, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_perm_b32 v25, v55, v39, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v26, v1, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v27, v2, v34, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v23
-; GFX11-NEXT: v_or_b32_e32 v3, v26, v24
-; GFX11-NEXT: v_or_b32_e32 v4, v27, v25
+; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v23, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v24, 16, v26
+; GFX11-NEXT: v_lshl_or_b32 v4, v25, 16, v27
; GFX11-NEXT: s_clause 0x5
; GFX11-NEXT: scratch_store_b128 v0, v[64:67], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
@@ -116189,19 +115295,12 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v33, v62, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v63, v60, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v53, v58, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v51, v56, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v45, v44, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v49, v48, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr62
; VI-NEXT: ; implicit-def: $vgpr63
@@ -116222,21 +115321,18 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v16, v17, v16, s6
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116245,8 +115341,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116255,8 +115350,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116265,8 +115359,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116275,8 +115368,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116285,8 +115377,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116294,24 +115385,23 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v41, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v55, v34, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v61, v32, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v59, v54, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v57, v52, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v47, v38, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v35, v46, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_perm_b32 v14, v43, v50, s6
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: v_perm_b32 v15, v39, v42, s6
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr41
@@ -116336,8 +115426,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_or_b32_e32 v16, v16, v17
+; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116346,8 +115435,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; VI-NEXT: v_or_b32_e32 v17, v17, v18
+; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116356,8 +115444,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v18, v18, v19
+; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116366,8 +115453,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116376,8 +115462,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v20, v20, v21
+; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116386,8 +115471,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116396,8 +115480,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s6
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_or_b32_e32 v22, v22, v23
+; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116406,8 +115489,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116416,8 +115498,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_or_b32_e32 v24, v24, v25
+; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116426,8 +115507,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116436,8 +115516,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_or_b32_e32 v26, v26, v27
+; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116446,8 +115525,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116456,8 +115534,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v28, v28, v29
+; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116466,8 +115543,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116476,8 +115552,7 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v30, v30, v31
+; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -116550,10 +115625,9 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_or_b32_e32 v31, v31, v32
+; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
@@ -119755,18 +118829,18 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
@@ -119789,28 +118863,28 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -119825,18 +118899,16 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
@@ -119855,28 +118927,27 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
@@ -119891,13 +118962,12 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
@@ -119920,28 +118990,27 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
@@ -119956,13 +119025,12 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v18, 16, v16
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
@@ -119985,28 +119053,27 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
@@ -120021,13 +119088,12 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v21
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
@@ -120050,28 +119116,27 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
@@ -120086,12 +119151,11 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
@@ -121613,127 +120677,103 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB75_2
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s75
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s73
-; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s63
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s61
-; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s59
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s57
-; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s47
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s45
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s13
-; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s11
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s9
-; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s7
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s8, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v14, v13, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s6, v15, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v14, v13, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v52, v51, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v54, v53, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v48, v39, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v50, v49, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v36, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v38, v37, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v32, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v34, v33, s4
-; VI-NEXT: v_or_b32_e32 v15, v16, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; VI-NEXT: v_perm_b32 v16, v60, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: v_perm_b32 v17, v62, v61, s4
-; VI-NEXT: v_or_b32_e32 v16, v17, v16
+; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; VI-NEXT: v_perm_b32 v17, v59, v18, s4
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: v_perm_b32 v18, v41, v40, s4
-; VI-NEXT: v_or_b32_e32 v17, v18, v17
+; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v18
; VI-NEXT: v_perm_b32 v18, v57, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v19, v42, v58, s4
-; VI-NEXT: v_or_b32_e32 v18, v19, v18
+; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; VI-NEXT: v_perm_b32 v19, v45, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: v_perm_b32 v20, v56, v47, s4
-; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; VI-NEXT: v_perm_b32 v20, v44, v21, s4
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: v_perm_b32 v21, v46, v26, s4
-; VI-NEXT: v_or_b32_e32 v20, v21, v20
+; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; VI-NEXT: v_perm_b32 v21, v31, v22, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: v_perm_b32 v22, v24, v43, s4
-; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; VI-NEXT: v_perm_b32 v22, v28, v23, s4
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; VI-NEXT: v_perm_b32 v23, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v22, v23, v22
-; VI-NEXT: v_perm_b32 v23, v25, v63, s4
; VI-NEXT: v_mov_b32_e32 v44, v24
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_perm_b32 v23, v25, v63, s4
; VI-NEXT: v_perm_b32 v24, v27, v55, s4
-; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v45, v26
@@ -121743,80 +120783,72 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; VI-NEXT: v_perm_b32 v24, v25, v24, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
-; VI-NEXT: v_or_b32_e32 v24, v25, v24
+; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
-; VI-NEXT: v_or_b32_e32 v26, v27, v26
+; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
-; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v28, v29, v28
+; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
-; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
-; VI-NEXT: v_or_b32_e32 v30, v31, v30
+; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v43, v46, v43, s4
-; VI-NEXT: v_or_b32_e32 v31, v43, v31
+; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB75_3
; VI-NEXT: .LBB75_2:
@@ -122537,127 +121569,103 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB75_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
+; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
+; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v18
; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
+; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
+; GFX9-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
+; GFX9-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
+; GFX9-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX9-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
+; GFX9-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v45, v26
@@ -122667,80 +121675,72 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
+; GFX9-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
+; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
+; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
+; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
+; GFX9-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
+; GFX9-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
+; GFX9-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
+; GFX9-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB75_3
; GFX9-NEXT: .LBB75_2:
@@ -123280,56 +122280,49 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -123421,143 +122414,132 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB75_3
; GFX11-TRUE16-NEXT: .LBB75_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v8, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
-; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -123854,56 +122836,49 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -123995,143 +122970,132 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB75_3
; GFX11-FAKE16-NEXT: .LBB75_2: ; %cmp.true
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -141203,19 +140167,12 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v10, v37, v36, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v59, v34, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v57, v32, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v47, v46, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v43, v42, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v55, v54, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v51, v50, s6
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr59
@@ -141237,16 +140194,14 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141255,8 +140210,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141265,8 +140219,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141275,8 +140228,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141285,8 +140237,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141295,8 +140246,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141305,24 +140255,22 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_perm_b32 v9, v39, v62, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v38, v61, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v39, v62, s6
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v35, v60, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v33, v58, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v63, v56, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v45, v44, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v41, v40, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_perm_b32 v14, v53, v52, s6
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr61
@@ -141341,7 +140289,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v49, v15, s6
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr49
@@ -141353,16 +140301,14 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_or_b32_e32 v16, v16, v17
+; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v17, v18, v19
+; VI-NEXT: v_lshl_or_b32 v17, v19, 16, v18
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141371,8 +140317,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v18, v18, v19
+; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141381,8 +140326,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141391,8 +140335,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v20, v20, v21
+; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141401,8 +140344,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141411,8 +140353,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v23, v24, s6
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_or_b32_e32 v22, v22, v23
+; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141421,8 +140362,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141431,8 +140371,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v25, v26, s6
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_or_b32_e32 v24, v24, v25
+; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141441,8 +140380,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141451,8 +140389,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_or_b32_e32 v26, v26, v27
+; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141461,8 +140398,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141471,8 +140407,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v28, v28, v29
+; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141481,8 +140416,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -141491,8 +140425,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v30, v30, v31
+; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
@@ -141557,14 +140490,13 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v32, v33, v32, s6
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v32, v33, v32, s6
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: v_or_b32_e32 v31, v31, v32
+; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
@@ -146970,82 +145902,70 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB89_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s8, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s10
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s8, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s7
-; VI-NEXT: v_perm_b32 v5, s14, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s10
; VI-NEXT: v_perm_b32 v4, s11, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s41
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s14, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s13
-; VI-NEXT: v_perm_b32 v6, s46, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s41
; VI-NEXT: v_perm_b32 v5, s42, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s57
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s46, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s45
-; VI-NEXT: v_perm_b32 v7, s63, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s57
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s61
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s63, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s62
-; VI-NEXT: v_perm_b32 v8, s73, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s61
; VI-NEXT: v_perm_b32 v7, s74, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s12
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s73, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s9
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s12
; VI-NEXT: v_perm_b32 v8, s76, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_mov_b32_e32 v43, v10
; VI-NEXT: v_mov_b32_e32 v10, s43
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v10, s56, v10, v11
; VI-NEXT: v_perm_b32 v9, s44, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_perm_b32 v10, s56, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_mov_b32_e32 v10, s47
; VI-NEXT: v_mov_b32_e32 v35, v12
; VI-NEXT: v_mov_b32_e32 v12, s59
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
-; VI-NEXT: v_mov_b32_e32 v10, s47
-; VI-NEXT: v_perm_b32 v12, s72, v12, v11
; VI-NEXT: v_perm_b32 v10, s60, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s72, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v15, v14, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s75, v13, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v15, v14, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
@@ -147054,26 +145974,22 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: v_perm_b32 v23, v51, v33, s4
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v12, v56, v12, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_perm_b32 v14, v59, v14, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v13, v47, v13, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v14, v59, v14, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v15, v32, v15, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v61, v13, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v17, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v21, v16, s4
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v17, v28, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v21, v58, v46, s4
; VI-NEXT: v_perm_b32 v24, v36, v49, s4
; VI-NEXT: v_mov_b32_e32 v28, v52
@@ -147081,44 +145997,36 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v16, v19, v16, s4
; VI-NEXT: v_perm_b32 v19, v26, v22, s4
-; VI-NEXT: v_or_b32_e32 v17, v19, v17
+; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v19
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; VI-NEXT: v_or_b32_e32 v15, v16, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; VI-NEXT: v_perm_b32 v16, v25, v20, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_or_b32_e32 v16, v18, v16
+; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v18
; VI-NEXT: v_perm_b32 v18, v45, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v20, v44, v29, s4
; VI-NEXT: v_perm_b32 v22, v53, v42, s4
; VI-NEXT: v_mov_b32_e32 v45, v34
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v19, v30, v19, s4
-; VI-NEXT: v_or_b32_e32 v18, v19, v18
+; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; VI-NEXT: v_perm_b32 v19, v55, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; VI-NEXT: v_perm_b32 v20, v39, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v20, v21, v20
+; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; VI-NEXT: v_perm_b32 v21, v38, v63, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; VI-NEXT: v_perm_b32 v22, v54, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v22, v23, v22
+; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
; VI-NEXT: v_perm_b32 v23, v40, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; VI-NEXT: v_perm_b32 v24, v48, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_mov_b32_e32 v48, v25
; VI-NEXT: v_perm_b32 v25, v25, v41, s4
-; VI-NEXT: v_or_b32_e32 v24, v25, v24
+; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v34, v33
; VI-NEXT: v_mov_b32_e32 v33, v26
@@ -147130,45 +146038,40 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
-; VI-NEXT: v_or_b32_e32 v26, v27, v26
+; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v28, v29, s4
-; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v28, v28, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v62, v29, s4
-; VI-NEXT: v_or_b32_e32 v28, v29, v28
+; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v62, v44
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v43, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
@@ -147176,18 +146079,16 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
-; VI-NEXT: v_or_b32_e32 v30, v31, v30
+; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_mov_b32_e32 v35, v43
; VI-NEXT: v_perm_b32 v43, v44, v43, s4
-; VI-NEXT: v_or_b32_e32 v31, v43, v31
+; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; VI-NEXT: v_mov_b32_e32 v43, v39
; VI-NEXT: v_mov_b32_e32 v39, v34
; VI-NEXT: v_mov_b32_e32 v34, v52
@@ -148687,12 +147588,11 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB89_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
@@ -148706,134 +147606,117 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v15, 0xff, v50
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s88 :: v_dual_and_b32 v29, 0xff, v166
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v37, 8, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v86, 8, s88
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v70, 8, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v33, 8, v15
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v32, 8, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v39, 8, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v119, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v82, 8, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v64, 8, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v128, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v101, 8, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v87, 8, v10
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v150, 8, v8
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v102, 8, v30
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v132, 8, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v183, v129, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v41, v133, 8, v29
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v178, 8, v40
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
@@ -149205,10 +148088,11 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s74, 0xff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v33
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v48
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v32
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
@@ -149224,61 +148108,52 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s11, s8, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s76, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
-; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v35, 8, s76
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v33, 8, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v32, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v9, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v36
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v11, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v37, 8, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v36, 8, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v14, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v34, 8, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v82, v64, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v9, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v96, v85, 0xc0c0004
@@ -149288,18 +148163,18 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v117
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v144
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v10, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v84, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v19, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v87, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v135
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v150
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v11, 16, v9
@@ -149315,82 +148190,72 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v11, 16, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v117, 8, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v134
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v119
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-FAKE16-NEXT: s_and_b32 s77, s62, 0xff
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v114, 8, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v119, 8, v10
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s59, 8
; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s45, 8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v24, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v114
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_and_b32 s78, s56, 0xff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v24, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s79
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
; GFX11-FAKE16-NEXT: s_and_b32 s79, s63, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s61, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v144, 8, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v147, 8, v10
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v147
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v26, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v133
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v26, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v133, 8, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v26
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v177
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v164
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v151
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v28, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v164, 8, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v135, 8, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v176
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v161
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v28, v29
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v161, 8, v28
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v179, v163, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v165
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v178
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v166
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v11, v31
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v165, 8, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v166, 8, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v150, 8, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v40
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB89_3
@@ -152891,12 +151756,10 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v2, v2, v35, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v45, v39, v45, s4
-; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v45
-; VI-NEXT: v_or_b32_e32 v1, v1, v33
+; VI-NEXT: v_lshl_or_b32 v1, v45, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v53, v49, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
@@ -152904,14 +151767,12 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
; VI-NEXT: v_perm_b32 v1, v36, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v43, v37, s4
; VI-NEXT: v_perm_b32 v1, v4, v61, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v43, v37, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
@@ -152919,19 +151780,17 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v5, v55, s4
; VI-NEXT: v_perm_b32 v1, v48, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v6, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
@@ -152939,14 +151798,12 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v7, v54, s4
; VI-NEXT: v_perm_b32 v1, v44, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v51, v47, s4
; VI-NEXT: v_perm_b32 v1, v8, v56, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v51, v47, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -152955,19 +151812,17 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: v_perm_b32 v2, v9, v63, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v10, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -152976,21 +151831,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v11, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v12, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
@@ -152999,21 +151852,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v2, v3, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
@@ -153022,21 +151873,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -153044,19 +151893,17 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v60, s4
; VI-NEXT: v_perm_b32 v1, v41, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -153065,21 +151912,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
@@ -153090,19 +151935,17 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -153113,19 +151956,17 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v23, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v24, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
@@ -153136,19 +151977,17 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v26, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
@@ -153156,14 +151995,12 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v27, v50, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v59, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v34, v57, s4
; VI-NEXT: v_perm_b32 v1, v28, v58, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v34, v57, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -153171,8 +152008,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v29, v38, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v42, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
@@ -153180,8 +152016,7 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v30, v52, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
@@ -153192,20 +152027,18 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v32, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v2, v3, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -160463,27 +159296,23 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_mov_b32_e32 v20, v10
; VI-NEXT: .LBB91_5: ; %end
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v6, v33, v6, s4
; VI-NEXT: v_perm_b32 v26, v26, v58, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v6, v26, v6
+; VI-NEXT: v_perm_b32 v6, v33, v6, s4
+; VI-NEXT: v_lshl_or_b32 v6, v6, 16, v26
+; VI-NEXT: v_perm_b32 v33, v47, v50, s4
; VI-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v6, v25, v30, s4
-; VI-NEXT: v_perm_b32 v33, v47, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v6, v33, v6
+; VI-NEXT: v_lshl_or_b32 v6, v6, 16, v33
; VI-NEXT: v_add_u32_e32 v25, vcc, 4, v0
-; VI-NEXT: v_perm_b32 v5, v24, v5, s4
; VI-NEXT: buffer_store_dword v6, v25, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v6, v29, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v5, v6, v5
+; VI-NEXT: v_perm_b32 v5, v24, v5, s4
+; VI-NEXT: v_lshl_or_b32 v5, v5, 16, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 8, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v6, v11, v28, s4
; VI-NEXT: v_perm_b32 v5, v23, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v11, v28, s4
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 12, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
@@ -160522,8 +159351,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v2, v4, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v4, v5, v4
+; VI-NEXT: v_lshl_or_b32 v4, v4, 16, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 16, v0
; VI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
@@ -160531,8 +159359,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v4, v60, v20, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v5, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_add_u32_e32 v5, vcc, 20, v0
; VI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
@@ -160541,8 +159368,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v3, v4, v3
+; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
@@ -160552,8 +159378,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v4, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
@@ -160564,19 +159389,17 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v4, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v3, v4, v3, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v2, v37, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v3, v4, v3, s4
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
@@ -160585,19 +159408,17 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v2, v49, v2, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v3, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v48, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
@@ -160607,8 +159428,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v52, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
@@ -160617,8 +159437,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v51, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v22, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
@@ -160628,19 +159447,17 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v44, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v19, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -160648,14 +159465,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v59, v53, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v36, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v55, v15, s4
; VI-NEXT: v_perm_b32 v1, v56, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v55, v15, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -160663,14 +159478,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v41, v9, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v21, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v39, v54, s4
; VI-NEXT: v_perm_b32 v1, v14, v40, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v39, v54, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
@@ -160678,8 +159491,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v18, v17, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v7, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
@@ -160687,8 +159499,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v12, v13, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
@@ -160699,19 +159510,17 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v8, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -160722,8 +159531,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v42, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
@@ -160735,8 +159543,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
@@ -160749,8 +159556,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
@@ -160762,8 +159568,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
@@ -160776,8 +159581,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
@@ -160789,8 +159593,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
@@ -160802,18 +159605,16 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v61, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_perm_b32 v1, v1, v43, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -162314,8 +161115,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v26, v34, v26, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v34, 16, v50
-; GFX9-NEXT: v_or_b32_e32 v26, v26, v34
+; GFX9-NEXT: v_lshl_or_b32 v26, v50, 16, v26
; GFX9-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -162325,14 +161125,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v27, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v9, v26, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v26
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v49
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v49, 16, v8
; GFX9-NEXT: buffer_store_dword v8, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -162340,14 +161138,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v60, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v48
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v48, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162356,14 +161152,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v7, v7, v53, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v38
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v54, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v38, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162372,14 +161166,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v7, v7, v55, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v12, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162388,14 +161180,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v7, v7, v41, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v47, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v42, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v36, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162404,36 +161194,30 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v7, v7, v43, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v46, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v14
+; GFX9-NEXT: v_perm_b32 v8, v56, v51, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v44, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v14, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v8, v56, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v45, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_perm_b32 v7, v13, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v30
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: v_perm_b32 v8, v58, v32, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v30, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v7, v61, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, v58, v32, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v7, v1, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v33
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v7
+; GFX9-NEXT: v_lshl_or_b32 v1, v33, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -162441,14 +161225,12 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v1, v3, s4
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v31, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162457,8 +161239,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v24, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162467,8 +161248,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v1, v1, v5, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162477,8 +161257,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v29, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162488,8 +161267,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v10, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162498,8 +161276,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v1, v1, v11, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v28, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162509,8 +161286,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162519,8 +161295,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v1, v1, v17, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v25, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162530,18 +161305,17 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:104
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_perm_b32 v1, v1, v19, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v1, v1, v19, s4
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162553,8 +161327,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162565,8 +161338,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162578,8 +161350,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -162590,8 +161361,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -163860,93 +162630,70 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_perm_b32 v115, v117, v63, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_perm_b32 v117, v114, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v114, v129, v62, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v37, v132, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
+; GFX11-TRUE16-NEXT: v_perm_b32 v114, v129, v62, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v118, v118, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v128, v116, v61, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v32, v148, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v163, v30, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v114
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v114, v38, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v114, v2, 16, v38
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v144, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; GFX11-TRUE16-NEXT: v_perm_b32 v128, v116, v61, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v116, v37, 16, v118
; GFX11-TRUE16-NEXT: v_perm_b32 v33, v130, v59, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v148, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v115, v117, v115
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v116, v118, v37
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v117, v128, v129
; GFX11-TRUE16-NEXT: v_perm_b32 v37, v133, v58, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v38, v119, v57, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v119, v135, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v128, v33, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v118, v145, v56, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v131, v131, v47, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v96, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v115, v115, 16, v117
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v117, v128, v129
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v128, v2, 16, v33
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v129, v37, 16, v38
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v130, v32, 16, v119
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v160, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v149, v43, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v130, v119, v32
; GFX11-TRUE16-NEXT: v_perm_b32 v32, v146, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v163, v30, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v118, v145, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v129, v38, v37
; GFX11-TRUE16-NEXT: v_perm_b32 v33, v134, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v32, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v161, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v131, v131, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118
; GFX11-TRUE16-NEXT: v_perm_b32 v37, v150, v40, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v167, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v33, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v147, v182, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v177, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v131, v131, v118
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, v37, v38
-; GFX11-TRUE16-NEXT: v_perm_b32 v38, v166, v180, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v131, v118, 16, v131
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v69, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v96, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v68, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v82, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v100, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[114:117], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[128:131], off offset:16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v2, 16, v32
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v161, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v31, 16, v33
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, v37, v38
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v147, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v167, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v38, v166, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v177, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v116, v165, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, v33, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v176, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v114, v38, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v51, v45, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v68, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v84, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v82, v9, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v100, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v37, v164, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v116, v116, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v162, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v4, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v83, v7, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v5, v23
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v23, 16, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v80, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v86, v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v9, v18
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v97, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v164, v181, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v115, v151, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v53, v1, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v66, v3, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v117, v25, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v55, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v67, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v33, v2, 16, v33
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v114, v26, 16, v38
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v176, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v116, v25, 16, v116
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v162, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v51, v45, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v4, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v22, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v85, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v17
@@ -163955,15 +162702,17 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v101, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v113, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v112, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v115, v115, v37
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v115, v37, 16, v115
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v53, v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v34, v52, v44, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v66, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v37, v64, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v117, v2, 16, v25
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v55, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v26, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v54, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v67, v35, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v65, v6, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v70, v8, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v10, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
@@ -163976,10 +162725,10 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v99, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v34, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v37, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v25
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v34
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v37
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v25, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v26, 16, v6
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v22
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v23
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v12, v17
@@ -165328,83 +164077,63 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v35, v112, v73, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v112, v114, v63, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v34, v129, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v103, v103, v72, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v34, v129, v34, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v114, v118, v62, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v112
; GFX11-FAKE16-NEXT: v_perm_b32 v115, v115, v60, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v112, v35, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v134, v33, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v112
; GFX11-FAKE16-NEXT: v_perm_b32 v118, v113, v61, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v129, 16, v114
+; GFX11-FAKE16-NEXT: v_perm_b32 v32, v147, v32, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v113, v103, v117
+; GFX11-FAKE16-NEXT: v_perm_b32 v103, v133, v56, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v112, v2, 16, v35
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v134, v33, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v114, v115, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v115, v118, v129
; GFX11-FAKE16-NEXT: v_perm_b32 v33, v128, v59, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v34, v130, v58, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v32, v147, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v103, v133, v56, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v115, v118, v129
; GFX11-FAKE16-NEXT: v_perm_b32 v35, v116, v57, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v116, v132, v46, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v118, v119, v47, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v33, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v150, v28, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v145, v42, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v35, v34
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v66, v21, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v65, v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v85, v19, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v2, 16, v33
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v33, v34, 16, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v116, v117
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v150, v28, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v118, v103
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v145, v42, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v103, v144, v40, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v162, v27, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v116, v131, v183, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v66, v21, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v117, v148, v182, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v81, v20, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v80, v7, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v21, 16, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v69, v31, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v71, v9, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v18, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[112:115], off
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[32:35], off offset:16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v103, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v2, 16, v103
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v149, v181, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v116, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v33, v28, 16, v116
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v34, v27, 16, v117
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v135, v180, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v164, v26, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v163, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v65, v5, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v81, v20, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v85, v19, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v117, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v135, v180, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v103, v161, v178, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v166, v25, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v112, v146, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v80, v7, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v69, v31, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v71, v9, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v18, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v114, 16, v25
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v27, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v103, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v165, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v112, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v151, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v36, v48, v45, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v48, v49, v44, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v20, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v67, v8, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v30, 0xc0c0004
@@ -165412,13 +164141,16 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v19
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v24, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v55, v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v114, 16, v25
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v35, v2, 16, v27
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v26, 16, v103
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v165, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v112
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v151, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v36, v48, v45, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v48, v49, v44, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v39, v4, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v48, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v48, v52, v41, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v37, v64, v37, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v68, v10, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v20
@@ -165429,14 +164161,15 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v13, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v101, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v113, v160, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v55, v3, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v39, v53, v43, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v36
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v2, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v48
+; GFX11-FAKE16-NEXT: v_perm_b32 v48, v52, v41, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v36, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v48
+; GFX11-FAKE16-NEXT: v_perm_b32 v37, v64, v37, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v70, v12, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v21
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v16, 0xc0c0004
@@ -165448,9 +164181,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v15, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v113, v114
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v39, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v39
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v48, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v37, 16, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v16, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v19
@@ -167884,19 +166617,12 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v10, v37, v36, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v59, v34, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v57, v32, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v47, v46, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v43, v42, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v55, v54, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v51, v50, s6
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr59
@@ -167918,16 +166644,14 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -167936,8 +166660,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -167946,8 +166669,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -167956,8 +166678,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -167966,8 +166687,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -167976,8 +166696,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -167986,24 +166705,22 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_perm_b32 v9, v39, v62, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v38, v61, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v39, v62, s6
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v35, v60, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v33, v58, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v63, v56, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v45, v44, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v41, v40, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_perm_b32 v14, v53, v52, s6
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr61
@@ -168022,7 +166739,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v49, v15, s6
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr49
@@ -168034,16 +166751,14 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_or_b32_e32 v16, v16, v17
+; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v17, v18, v19
+; VI-NEXT: v_lshl_or_b32 v17, v19, 16, v18
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168052,8 +166767,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v18, v18, v19
+; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168062,8 +166776,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168072,8 +166785,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v20, v20, v21
+; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168082,8 +166794,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168092,8 +166803,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v23, v24, s6
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_or_b32_e32 v22, v22, v23
+; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168102,8 +166812,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168112,8 +166821,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v25, v26, s6
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_or_b32_e32 v24, v24, v25
+; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168122,8 +166830,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168132,8 +166839,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_or_b32_e32 v26, v26, v27
+; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168142,8 +166848,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168152,8 +166857,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v28, v28, v29
+; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168162,8 +166866,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -168172,8 +166875,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v30, v30, v31
+; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
@@ -168238,14 +166940,13 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v32, v33, v32, s6
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v32, v33, v32, s6
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: v_or_b32_e32 v31, v31, v32
+; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
@@ -173706,82 +172407,70 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB93_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s8, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s10
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s8, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s7
-; VI-NEXT: v_perm_b32 v5, s14, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s10
; VI-NEXT: v_perm_b32 v4, s11, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s41
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s14, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s13
-; VI-NEXT: v_perm_b32 v6, s46, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s41
; VI-NEXT: v_perm_b32 v5, s42, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s57
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s46, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s45
-; VI-NEXT: v_perm_b32 v7, s63, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s57
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s61
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s63, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s62
-; VI-NEXT: v_perm_b32 v8, s73, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s61
; VI-NEXT: v_perm_b32 v7, s74, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s12
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s73, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s9
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s12
; VI-NEXT: v_perm_b32 v8, s76, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_mov_b32_e32 v43, v10
; VI-NEXT: v_mov_b32_e32 v10, s43
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v10, s56, v10, v11
; VI-NEXT: v_perm_b32 v9, s44, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_perm_b32 v10, s56, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_mov_b32_e32 v10, s47
; VI-NEXT: v_mov_b32_e32 v35, v12
; VI-NEXT: v_mov_b32_e32 v12, s59
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
-; VI-NEXT: v_mov_b32_e32 v10, s47
-; VI-NEXT: v_perm_b32 v12, s72, v12, v11
; VI-NEXT: v_perm_b32 v10, s60, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s72, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v15, v14, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s75, v13, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v15, v14, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
@@ -173790,26 +172479,22 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: v_perm_b32 v23, v51, v33, s4
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v12, v56, v12, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_perm_b32 v14, v59, v14, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v13, v47, v13, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v14, v59, v14, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v15, v32, v15, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v61, v13, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v17, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v21, v16, s4
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v17, v28, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v21, v58, v46, s4
; VI-NEXT: v_perm_b32 v24, v36, v49, s4
; VI-NEXT: v_mov_b32_e32 v28, v52
@@ -173817,44 +172502,36 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v16, v19, v16, s4
; VI-NEXT: v_perm_b32 v19, v26, v22, s4
-; VI-NEXT: v_or_b32_e32 v17, v19, v17
+; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v19
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; VI-NEXT: v_or_b32_e32 v15, v16, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; VI-NEXT: v_perm_b32 v16, v25, v20, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_or_b32_e32 v16, v18, v16
+; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v18
; VI-NEXT: v_perm_b32 v18, v45, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v20, v44, v29, s4
; VI-NEXT: v_perm_b32 v22, v53, v42, s4
; VI-NEXT: v_mov_b32_e32 v45, v34
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v19, v30, v19, s4
-; VI-NEXT: v_or_b32_e32 v18, v19, v18
+; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; VI-NEXT: v_perm_b32 v19, v55, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; VI-NEXT: v_perm_b32 v20, v39, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v20, v21, v20
+; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; VI-NEXT: v_perm_b32 v21, v38, v63, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; VI-NEXT: v_perm_b32 v22, v54, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v22, v23, v22
+; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
; VI-NEXT: v_perm_b32 v23, v40, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; VI-NEXT: v_perm_b32 v24, v48, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_mov_b32_e32 v48, v25
; VI-NEXT: v_perm_b32 v25, v25, v41, s4
-; VI-NEXT: v_or_b32_e32 v24, v25, v24
+; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v34, v33
; VI-NEXT: v_mov_b32_e32 v33, v26
@@ -173866,45 +172543,40 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
-; VI-NEXT: v_or_b32_e32 v26, v27, v26
+; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v28, v29, s4
-; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v28, v28, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v62, v29, s4
-; VI-NEXT: v_or_b32_e32 v28, v29, v28
+; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v62, v44
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v43, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
@@ -173912,18 +172584,16 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
-; VI-NEXT: v_or_b32_e32 v30, v31, v30
+; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_mov_b32_e32 v35, v43
; VI-NEXT: v_perm_b32 v43, v44, v43, s4
-; VI-NEXT: v_or_b32_e32 v31, v43, v31
+; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; VI-NEXT: v_mov_b32_e32 v43, v39
; VI-NEXT: v_mov_b32_e32 v39, v34
; VI-NEXT: v_mov_b32_e32 v34, v52
@@ -175423,12 +174093,11 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB93_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
@@ -175442,134 +174111,117 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v15, 0xff, v50
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s88 :: v_dual_and_b32 v29, 0xff, v166
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v37, 8, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v86, 8, s88
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v70, 8, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v33, 8, v15
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v32, 8, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v39, 8, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v119, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v82, 8, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v64, 8, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v128, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v101, 8, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v87, 8, v10
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v150, 8, v8
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v102, 8, v30
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v132, 8, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v183, v129, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v41, v133, 8, v29
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v178, 8, v40
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
@@ -175941,10 +174593,11 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s74, 0xff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v33
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v48
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v32
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
@@ -175960,61 +174613,52 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s11, s8, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s76, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
-; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v35, 8, s76
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v33, 8, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v32, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v9, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v36
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v11, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v37, 8, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v36, 8, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v14, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v34, 8, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v82, v64, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v9, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v96, v85, 0xc0c0004
@@ -176024,18 +174668,18 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v117
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v144
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v10, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v84, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v19, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v87, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v135
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v150
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v11, 16, v9
@@ -176051,82 +174695,72 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v11, 16, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v117, 8, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v134
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v119
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-FAKE16-NEXT: s_and_b32 s77, s62, 0xff
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v114, 8, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v119, 8, v10
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s59, 8
; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s45, 8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v24, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v114
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_and_b32 s78, s56, 0xff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v24, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s79
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
; GFX11-FAKE16-NEXT: s_and_b32 s79, s63, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s61, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v144, 8, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v147, 8, v10
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v147
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v26, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v133
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v26, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v133, 8, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v26
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v177
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v164
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v151
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v28, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v164, 8, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v135, 8, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v176
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v161
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v28, v29
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v161, 8, v28
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v179, v163, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v165
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v178
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v166
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v11, v31
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v165, 8, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v166, 8, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v150, 8, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v40
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB93_3
@@ -178726,172 +177360,138 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v42, 0x200
; VI-NEXT: v_add_f16_sdwa v23, v18, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
; VI-NEXT: v_add_f16_e32 v18, 0x200, v18
+; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v57, v23, 16, v18
; VI-NEXT: v_add_f16_sdwa v23, v17, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v57, v18, v29
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
; VI-NEXT: v_add_f16_e32 v17, 0x200, v17
+; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v56, v23, 16, v17
; VI-NEXT: v_add_f16_sdwa v23, v20, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v56, v17, v29
-; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
; VI-NEXT: v_add_f16_e32 v20, 0x200, v20
+; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v59, v23, 16, v20
; VI-NEXT: v_add_f16_sdwa v23, v19, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, 0x200, v19
-; VI-NEXT: v_or_b32_e32 v59, v20, v29
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
-; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; VI-NEXT: v_add_f16_sdwa v20, v51, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v51, 0x200, v51
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; VI-NEXT: v_add_f16_sdwa v37, v10, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
; VI-NEXT: v_add_f16_sdwa v45, v14, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
-; VI-NEXT: v_or_b32_e32 v58, v19, v29
+; VI-NEXT: v_lshl_or_b32 v32, v45, 16, v14
+; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
+; VI-NEXT: v_lshl_or_b32 v53, v37, 16, v10
+; VI-NEXT: v_lshl_or_b32 v58, v23, 16, v19
; VI-NEXT: v_add_f16_sdwa v19, v22, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
; VI-NEXT: v_add_f16_e32 v22, 0x200, v22
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v55, v19, 16, v22
; VI-NEXT: v_add_f16_sdwa v19, v21, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, 0x200, v21
-; VI-NEXT: v_or_b32_e32 v55, v22, v29
+; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: s_waitcnt vmcnt(5)
-; VI-NEXT: v_add_f16_sdwa v19, v24, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_e32 v24, 0x200, v24
; VI-NEXT: v_add_f16_sdwa v22, v8, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT: v_or_b32_e32 v54, v21, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
+; VI-NEXT: v_lshl_or_b32 v54, v19, 16, v21
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_add_f16_sdwa v19, v24, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v24, 0x200, v24
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v61, v19, 16, v24
; VI-NEXT: v_add_f16_sdwa v19, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, 0x200, v23
-; VI-NEXT: v_or_b32_e32 v61, v24, v29
; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: v_add_f16_sdwa v19, v26, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_e32 v26, 0x200, v26
; VI-NEXT: v_add_f16_sdwa v24, v4, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_add_f16_sdwa v21, v6, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
-; VI-NEXT: v_or_b32_e32 v60, v23, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
+; VI-NEXT: v_lshl_or_b32 v49, v21, 16, v6
+; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
+; VI-NEXT: v_lshl_or_b32 v44, v24, 16, v4
+; VI-NEXT: v_lshl_or_b32 v60, v19, 16, v23
+; VI-NEXT: v_add_f16_sdwa v19, v26, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v26, 0x200, v26
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v63, v19, 16, v26
; VI-NEXT: v_add_f16_sdwa v19, v25, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, 0x200, v25
-; VI-NEXT: v_or_b32_e32 v63, v26, v29
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: v_add_f16_sdwa v19, v28, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_e32 v28, 0x200, v28
; VI-NEXT: v_add_f16_sdwa v26, v31, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v31, 0x200, v31
; VI-NEXT: v_add_f16_sdwa v23, v12, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v34, v26, 16, v31
; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
-; VI-NEXT: v_or_b32_e32 v62, v25, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
+; VI-NEXT: v_lshl_or_b32 v41, v23, 16, v12
+; VI-NEXT: v_lshl_or_b32 v62, v19, 16, v25
+; VI-NEXT: v_add_f16_sdwa v19, v28, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v28, 0x200, v28
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v39, v19, 16, v28
; VI-NEXT: v_add_f16_sdwa v19, v27, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, 0x200, v27
-; VI-NEXT: v_or_b32_e32 v39, v28, v29
; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
+; VI-NEXT: v_add_f16_sdwa v25, v30, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v30, 0x200, v30
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v33, v25, 16, v30
+; VI-NEXT: v_add_f16_sdwa v25, v16, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v38, v19, 16, v27
; VI-NEXT: v_add_f16_sdwa v19, v50, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v50, 0x200, v50
; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_sdwa v25, v30, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v30, 0x200, v30
+; VI-NEXT: v_mov_b32_e32 v27, v30
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v38, v27, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v26
-; VI-NEXT: v_or_b32_e32 v34, v31, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v25
-; VI-NEXT: v_or_b32_e32 v33, v30, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: v_or_b32_e32 v36, v51, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
-; VI-NEXT: v_add_f16_sdwa v19, v2, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v35, v50, v29
-; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
+; VI-NEXT: v_mov_b32_e32 v28, v31
+; VI-NEXT: v_lshl_or_b32 v30, v25, 16, v16
+; VI-NEXT: v_lshl_or_b32 v36, v20, 16, v51
; VI-NEXT: v_add_f16_sdwa v20, v1, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
-; VI-NEXT: v_or_b32_e32 v47, v2, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v46, v1, v29
+; VI-NEXT: v_lshl_or_b32 v46, v20, 16, v1
; VI-NEXT: v_add_f16_sdwa v20, v3, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v24
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
-; VI-NEXT: v_or_b32_e32 v44, v4, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v43, v3, v29
+; VI-NEXT: v_lshl_or_b32 v43, v20, 16, v3
; VI-NEXT: v_add_f16_sdwa v20, v5, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v21
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
-; VI-NEXT: v_or_b32_e32 v49, v6, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v48, v5, v29
+; VI-NEXT: v_lshl_or_b32 v48, v20, 16, v5
; VI-NEXT: v_add_f16_sdwa v20, v7, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v22
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
-; VI-NEXT: v_or_b32_e32 v51, v8, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
+; VI-NEXT: v_lshl_or_b32 v35, v19, 16, v50
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v50, v7, v29
+; VI-NEXT: v_lshl_or_b32 v50, v20, 16, v7
; VI-NEXT: v_add_f16_sdwa v20, v9, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v37
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
-; VI-NEXT: v_or_b32_e32 v53, v10, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v52, v9, v29
+; VI-NEXT: v_lshl_or_b32 v52, v20, 16, v9
; VI-NEXT: v_add_f16_sdwa v20, v11, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
-; VI-NEXT: v_or_b32_e32 v41, v12, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
+; VI-NEXT: v_add_f16_sdwa v19, v2, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v40, v11, v29
+; VI-NEXT: v_lshl_or_b32 v40, v20, 16, v11
; VI-NEXT: v_add_f16_sdwa v20, v13, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v45
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
-; VI-NEXT: v_or_b32_e32 v32, v14, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
-; VI-NEXT: v_mov_b32_e32 v27, v30
-; VI-NEXT: v_add_f16_sdwa v25, v16, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_mov_b32_e32 v28, v31
-; VI-NEXT: v_or_b32_e32 v31, v13, v29
-; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
; VI-NEXT: v_add_f16_sdwa v42, v15, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v25
; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
-; VI-NEXT: v_or_b32_e32 v30, v16, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v42
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v29, v15, v29
+; VI-NEXT: v_lshl_or_b32 v31, v20, 16, v13
+; VI-NEXT: v_lshl_or_b32 v29, v42, 16, v15
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v30
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v29
@@ -178905,6 +177505,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v40
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v53
+; VI-NEXT: v_lshl_or_b32 v51, v22, 16, v8
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v52
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
@@ -178915,8 +177516,10 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v49
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v48
+; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v44
+; VI-NEXT: v_lshl_or_b32 v47, v19, 16, v2
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v43
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
@@ -179027,7 +177630,6 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_bfe_u32 v19, v19, 8, 8
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v58, v21
@@ -179061,10 +177663,9 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v24, v46, s4
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v24, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v29
+; VI-NEXT: v_lshl_or_b32 v1, v29, 16, v1
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
@@ -179072,8 +177673,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v2, v2, v24, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v35, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
@@ -179082,8 +177682,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v43, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
@@ -179092,8 +177691,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v4, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v34, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
@@ -179102,8 +177700,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v48, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v5, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
@@ -179112,8 +177709,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v6, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v58, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -179122,10 +177718,9 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v7, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
@@ -179134,8 +177729,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v8, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v37, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
@@ -179144,10 +177738,9 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
@@ -179156,8 +177749,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v10, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v59, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
@@ -179166,10 +177758,9 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v11, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
@@ -179178,8 +177769,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v12, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v45, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
@@ -179188,10 +177778,9 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
@@ -179200,8 +177789,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v14, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v40, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
@@ -179210,69 +177798,61 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v3, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v63, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v47, v38, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v56, v54, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v49, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v39, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v53, v33, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
@@ -179281,8 +177861,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: v_perm_b32 v2, v36, v62, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -179291,8 +177870,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v3, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v41, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
@@ -179302,8 +177880,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -179312,8 +177889,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v26, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v42, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
@@ -179323,8 +177899,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v27, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
@@ -179333,8 +177908,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v28, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v32, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -179344,8 +177918,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v30, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
@@ -179354,18 +177927,17 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v52, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_perm_b32 v1, v50, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v61, v2, s4
-; VI-NEXT: v_perm_b32 v1, v50, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
@@ -179375,8 +177947,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v51, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v44, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -183130,206 +181701,173 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_lshr_b32 s46, s45, 16
; VI-NEXT: v_mov_b32_e32 v7, 0x200
; VI-NEXT: v_add_f16_e32 v36, s46, v7
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
; VI-NEXT: v_add_f16_e32 v2, s45, v7
; VI-NEXT: s_lshr_b32 s45, s44, 16
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v23, v2, v1
+; VI-NEXT: v_lshl_or_b32 v23, v36, 16, v2
; VI-NEXT: v_add_f16_e32 v1, s45, v7
; VI-NEXT: v_add_f16_e32 v2, s44, v7
; VI-NEXT: s_lshr_b32 s44, s43, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v53, s44, v7
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v22, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v53
+; VI-NEXT: v_lshl_or_b32 v22, v1, 16, v2
+; VI-NEXT: v_add_f16_e32 v53, s44, v7
; VI-NEXT: v_add_f16_e32 v2, s43, v7
; VI-NEXT: s_lshr_b32 s43, s42, 16
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v25, v2, v1
+; VI-NEXT: v_lshl_or_b32 v25, v53, 16, v2
; VI-NEXT: v_add_f16_e32 v1, s43, v7
; VI-NEXT: v_add_f16_e32 v2, s42, v7
; VI-NEXT: s_lshr_b32 s42, s41, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v50, s42, v7
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v24, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v50
+; VI-NEXT: v_lshl_or_b32 v24, v1, 16, v2
+; VI-NEXT: v_add_f16_e32 v50, s42, v7
; VI-NEXT: v_add_f16_e32 v2, s41, v7
; VI-NEXT: s_lshr_b32 s41, s40, 16
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v27, v2, v1
+; VI-NEXT: v_lshl_or_b32 v27, v50, 16, v2
; VI-NEXT: v_add_f16_e32 v1, s41, v7
; VI-NEXT: v_add_f16_e32 v2, s40, v7
; VI-NEXT: s_lshr_b32 s40, s15, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v61, s40, v7
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v26, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
+; VI-NEXT: v_lshl_or_b32 v26, v1, 16, v2
+; VI-NEXT: v_add_f16_e32 v61, s40, v7
; VI-NEXT: v_add_f16_e32 v2, s15, v7
; VI-NEXT: s_lshr_b32 s15, s14, 16
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v29, v2, v1
+; VI-NEXT: v_lshl_or_b32 v29, v61, 16, v2
; VI-NEXT: v_add_f16_e32 v1, s15, v7
; VI-NEXT: v_add_f16_e32 v2, s14, v7
; VI-NEXT: s_lshr_b32 s14, s13, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v51, s14, v7
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v28, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
+; VI-NEXT: v_lshl_or_b32 v28, v1, 16, v2
+; VI-NEXT: v_add_f16_e32 v51, s14, v7
; VI-NEXT: v_add_f16_e32 v2, s13, v7
; VI-NEXT: s_lshr_b32 s13, s12, 16
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v6, v2, v1
+; VI-NEXT: v_lshl_or_b32 v6, v51, 16, v2
; VI-NEXT: v_add_f16_e32 v1, s13, v7
; VI-NEXT: v_add_f16_e32 v2, s12, v7
; VI-NEXT: s_lshr_b32 s12, s11, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v41, s12, v7
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v5, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v41
+; VI-NEXT: v_lshl_or_b32 v5, v1, 16, v2
+; VI-NEXT: v_add_f16_e32 v41, s12, v7
; VI-NEXT: v_add_f16_e32 v2, s11, v7
; VI-NEXT: s_lshr_b32 s11, s10, 16
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v31, v2, v1
+; VI-NEXT: v_lshl_or_b32 v31, v41, 16, v2
; VI-NEXT: v_add_f16_e32 v1, s11, v7
; VI-NEXT: v_add_f16_e32 v2, s10, v7
; VI-NEXT: s_lshr_b32 s10, s9, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v37, s10, v7
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v30, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v37
+; VI-NEXT: v_lshl_or_b32 v30, v1, 16, v2
+; VI-NEXT: v_add_f16_e32 v37, s10, v7
; VI-NEXT: v_add_f16_e32 v2, s9, v7
; VI-NEXT: s_lshr_b32 s9, s8, 16
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v4, v2, v1
+; VI-NEXT: v_lshl_or_b32 v4, v37, 16, v2
; VI-NEXT: v_add_f16_e32 v1, s9, v7
; VI-NEXT: v_add_f16_e32 v2, s8, v7
-; VI-NEXT: s_lshr_b32 s8, s7, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_add_f16_e32 v52, s8, v7
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v3, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v52
+; VI-NEXT: v_lshl_or_b32 v3, v1, 16, v2
+; VI-NEXT: s_lshr_b32 s8, s7, 16
; VI-NEXT: v_add_f16_e32 v2, s7, v7
; VI-NEXT: s_lshr_b32 s7, s6, 16
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v2, v2, v1
-; VI-NEXT: v_add_f16_e32 v1, s7, v7
; VI-NEXT: v_add_f16_e32 v8, s6, v7
; VI-NEXT: s_lshr_b32 s6, s17, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v42, s6, v7
-; VI-NEXT: s_lshr_b32 s6, s16, 16
-; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v1, v8, v1
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v42
; VI-NEXT: v_add_f16_e32 v9, s17, v7
-; VI-NEXT: v_add_f16_e32 v11, s6, v7
-; VI-NEXT: s_lshr_b32 s6, s19, 16
+; VI-NEXT: s_lshr_b32 s6, s16, 16
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v33, v9, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; VI-NEXT: v_lshl_or_b32 v33, v42, 16, v9
+; VI-NEXT: v_add_f16_e32 v11, s6, v7
; VI-NEXT: v_add_f16_e32 v9, s16, v7
-; VI-NEXT: v_add_f16_e32 v60, s6, v7
-; VI-NEXT: s_lshr_b32 s6, s18, 16
+; VI-NEXT: s_lshr_b32 s6, s19, 16
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v32, v9, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v60
+; VI-NEXT: v_lshl_or_b32 v32, v11, 16, v9
+; VI-NEXT: v_add_f16_e32 v60, s6, v7
; VI-NEXT: v_add_f16_e32 v9, s19, v7
-; VI-NEXT: v_add_f16_e32 v55, s6, v7
-; VI-NEXT: s_lshr_b32 s6, s21, 16
+; VI-NEXT: s_lshr_b32 s6, s18, 16
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v21, v9, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v55
+; VI-NEXT: v_lshl_or_b32 v21, v60, 16, v9
+; VI-NEXT: v_add_f16_e32 v55, s6, v7
; VI-NEXT: v_add_f16_e32 v9, s18, v7
+; VI-NEXT: s_lshr_b32 s6, s21, 16
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; VI-NEXT: v_add_f16_e32 v1, s7, v7
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v20, v55, 16, v9
; VI-NEXT: s_lshr_b32 s7, s20, 16
; VI-NEXT: v_add_f16_e32 v39, s6, v7
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v20, v9, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v39
; VI-NEXT: v_add_f16_e32 v9, s21, v7
-; VI-NEXT: v_add_f16_e32 v38, s7, v7
-; VI-NEXT: s_lshr_b32 s6, s23, 16
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v35, v9, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; VI-NEXT: v_lshl_or_b32 v35, v39, 16, v9
+; VI-NEXT: v_add_f16_e32 v38, s7, v7
; VI-NEXT: v_add_f16_e32 v9, s20, v7
+; VI-NEXT: s_lshr_b32 s6, s23, 16
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v34, v38, 16, v9
; VI-NEXT: s_lshr_b32 s7, s22, 16
; VI-NEXT: v_add_f16_e32 v49, s6, v7
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v34, v9, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
; VI-NEXT: v_add_f16_e32 v9, s23, v7
-; VI-NEXT: v_add_f16_e32 v48, s7, v7
-; VI-NEXT: s_lshr_b32 s6, s25, 16
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v19, v9, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v48
+; VI-NEXT: v_lshl_or_b32 v19, v49, 16, v9
+; VI-NEXT: v_add_f16_e32 v48, s7, v7
; VI-NEXT: v_add_f16_e32 v9, s22, v7
-; VI-NEXT: v_add_f16_e32 v45, s6, v7
+; VI-NEXT: s_lshr_b32 s6, s25, 16
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v18, v9, v8
+; VI-NEXT: v_lshl_or_b32 v18, v48, 16, v9
; VI-NEXT: s_lshr_b32 s7, s24, 16
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v45
+; VI-NEXT: v_add_f16_e32 v45, s6, v7
; VI-NEXT: v_add_f16_e32 v9, s25, v7
-; VI-NEXT: v_or_b32_e32 v16, v9, v8
-; VI-NEXT: v_add_f16_e32 v8, s7, v7
-; VI-NEXT: s_lshr_b32 s6, s27, 16
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v8
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_lshl_or_b32 v16, v45, 16, v9
+; VI-NEXT: v_add_f16_e32 v8, s7, v7
; VI-NEXT: v_add_f16_e32 v9, s24, v7
-; VI-NEXT: v_add_f16_e32 v47, s6, v7
+; VI-NEXT: s_lshr_b32 s6, s27, 16
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v15, v9, v8
+; VI-NEXT: v_lshl_or_b32 v15, v8, 16, v9
; VI-NEXT: s_lshr_b32 s7, s26, 16
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v47
+; VI-NEXT: v_add_f16_e32 v47, s6, v7
; VI-NEXT: v_add_f16_e32 v9, s27, v7
-; VI-NEXT: v_or_b32_e32 v13, v9, v8
-; VI-NEXT: v_add_f16_e32 v8, s7, v7
; VI-NEXT: s_lshr_b32 s6, s29, 16
-; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_add_f16_e32 v54, s26, v7
-; VI-NEXT: v_add_f16_e32 v57, s6, v7
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v12, v54, v8
+; VI-NEXT: v_lshl_or_b32 v13, v47, 16, v9
+; VI-NEXT: v_add_f16_e32 v8, s7, v7
+; VI-NEXT: v_add_f16_e32 v54, s26, v7
; VI-NEXT: s_lshr_b32 s7, s28, 16
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v57
+; VI-NEXT: v_add_f16_e32 v57, s6, v7
; VI-NEXT: v_add_f16_e32 v9, s29, v7
-; VI-NEXT: v_or_b32_e32 v10, v9, v8
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v12, v8, 16, v54
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v10, v57, 16, v9
; VI-NEXT: v_add_f16_e32 v8, s7, v7
+; VI-NEXT: v_add_f16_e32 v9, s28, v7
; VI-NEXT: s_lshr_b32 s6, s5, 16
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_add_f16_e32 v9, s28, v7
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v9, v8, 16, v9
; VI-NEXT: s_lshr_b32 s7, s4, 16
; VI-NEXT: v_add_f16_e32 v59, s6, v7
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v9, v9, v8
; VI-NEXT: v_add_f16_e32 v8, s5, v7
; VI-NEXT: v_add_f16_e32 v14, s7, v7
; VI-NEXT: v_add_f16_e32 v17, s4, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v8, v8, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v14
+; VI-NEXT: v_lshl_or_b32 v8, v59, 16, v8
+; VI-NEXT: v_add_f16_e32 v52, s8, v7
; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v7, v17, v7
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v7, v14, 16, v17
; VI-NEXT: v_lshrrev_b32_e32 v14, 8, v8
; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v14, 8, v7
@@ -183348,7 +181886,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v16
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v15
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v2, v52, 16, v2
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[16:17], 24, v[15:16]
; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v19
@@ -183842,19 +182381,12 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v20, v23, v20, s4
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: v_perm_b32 v30, v42, v30, s4
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_perm_b32 v19, v55, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: v_perm_b32 v18, v38, v18, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v15, v39, v15, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v12, v49, v12, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v9, v45, v9, s4
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_readlane_b32 s30, v63, 30
; VI-NEXT: v_readlane_b32 s31, v63, 31
; VI-NEXT: v_readlane_b32 s87, v63, 29
@@ -183889,53 +182421,51 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v58, v23, v58, s4
-; VI-NEXT: v_or_b32_e32 v20, v58, v20
+; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v58
; VI-NEXT: buffer_store_dword v20, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v20, v56, s4
-; VI-NEXT: v_or_b32_e32 v20, v20, v30
+; VI-NEXT: v_lshl_or_b32 v20, v30, 16, v20
; VI-NEXT: v_add_u32_e32 v30, vcc, 4, v0
; VI-NEXT: buffer_store_dword v20, v30, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v20, v46, s4
-; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; VI-NEXT: v_add_u32_e32 v20, vcc, 8, v0
; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v20, v60, v22, s4
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v19, v40, s4
-; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; VI-NEXT: v_add_u32_e32 v20, vcc, 12, v0
; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v19, v44, s4
-; VI-NEXT: v_or_b32_e32 v18, v19, v18
+; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; VI-NEXT: v_add_u32_e32 v19, vcc, 16, v0
; VI-NEXT: buffer_store_dword v18, v19, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v18, v43, s4
-; VI-NEXT: v_or_b32_e32 v15, v18, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v18
; VI-NEXT: v_add_u32_e32 v18, vcc, 20, v0
; VI-NEXT: buffer_store_dword v15, v18, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v15, v48, v17, s4
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v17, v10, s4
-; VI-NEXT: v_or_b32_e32 v15, v17, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v17
; VI-NEXT: v_add_u32_e32 v17, vcc, 24, v0
; VI-NEXT: buffer_store_dword v15, v17, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v15, v10, s4
-; VI-NEXT: v_or_b32_e32 v12, v15, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v15
; VI-NEXT: v_add_u32_e32 v15, vcc, 28, v0
; VI-NEXT: buffer_store_dword v12, v15, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
@@ -183943,17 +182473,16 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v12, v10, v16, s4
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v15, v10, s4
-; VI-NEXT: v_or_b32_e32 v12, v15, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v15
; VI-NEXT: v_add_u32_e32 v15, vcc, 32, v0
; VI-NEXT: buffer_store_dword v12, v15, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v12, v12, v10, s4
-; VI-NEXT: v_or_b32_e32 v9, v12, v9
+; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v12
; VI-NEXT: v_add_u32_e32 v12, vcc, 36, v0
; VI-NEXT: buffer_store_dword v9, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
@@ -183962,17 +182491,15 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v9, v9, v13, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v12, v54, v10, s4
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v9, v12, v9
+; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v12
; VI-NEXT: v_add_u32_e32 v12, vcc, 40, v0
; VI-NEXT: buffer_store_dword v9, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v12, v47, v28, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v9, v9, v10, s4
-; VI-NEXT: v_or_b32_e32 v9, v9, v12
+; VI-NEXT: v_lshl_or_b32 v9, v12, 16, v9
; VI-NEXT: v_add_u32_e32 v12, vcc, 44, v0
; VI-NEXT: buffer_store_dword v9, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
@@ -183980,19 +182507,17 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v9, v9, v7, s4
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v10, v7, v10, s4
-; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; VI-NEXT: v_add_u32_e32 v10, vcc, 48, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v10, v57, v26, s4
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v9, v7, v9, s4
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_add_u32_e32 v10, vcc, 52, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
@@ -184002,10 +182527,9 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v7, v7, v9, s4
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v9, v9, v10, s4
-; VI-NEXT: v_or_b32_e32 v7, v9, v7
+; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v9
; VI-NEXT: v_add_u32_e32 v9, vcc, 56, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
@@ -184013,16 +182537,14 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v7, v9, s4
; VI-NEXT: v_perm_b32 v9, v59, v11, s4
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v7, v7, v9
+; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, 60, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v7, v53, v14, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v9, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v7
+; VI-NEXT: v_lshl_or_b32 v1, v7, 16, v1
; VI-NEXT: v_add_u32_e32 v7, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
@@ -184031,8 +182553,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v21, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v7, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v1, v1, v7
+; VI-NEXT: v_lshl_or_b32 v1, v7, 16, v1
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
@@ -184041,16 +182562,14 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v24, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v7, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v7, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v7, v36, v25, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v34, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v7
+; VI-NEXT: v_lshl_or_b32 v1, v7, 16, v1
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
@@ -184059,8 +182578,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v6, v8, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v1, v1, v6
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
@@ -184069,8 +182587,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v29, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v50, v6, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v1, v1, v6
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
@@ -184079,8 +182596,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v33, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v1, v1, v5
+; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v1
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
@@ -184089,8 +182605,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v61, v5, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v1, v1, v5
+; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v1
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
@@ -184099,8 +182614,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v1, v1, v4
+; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
@@ -184110,8 +182624,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v51, v4, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v1, v1, v4
+; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
@@ -184121,8 +182634,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
@@ -184132,8 +182644,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v41, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
@@ -184143,8 +182654,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -184154,8 +182664,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v37, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -184167,8 +182676,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
@@ -184179,8 +182687,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v52, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -185103,8 +183610,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v39, v39, v44, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; GFX9-NEXT: v_or_b32_e32 v39, v48, v39
+; GFX9-NEXT: v_lshl_or_b32 v39, v39, 16, v48
+; GFX9-NEXT: v_lshl_or_b32 v37, v50, 16, v37
; GFX9-NEXT: v_perm_b32 v23, v34, v23, s4
; GFX9-NEXT: v_perm_b32 v32, v32, v59, s4
; GFX9-NEXT: v_perm_b32 v29, v29, v57, s4
@@ -185158,8 +183665,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: v_perm_b32 v18, v18, v54, s4
; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v18, v21, v18
+; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v21
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v38, v47, v52, s4
; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -185190,22 +183696,17 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v39, v39, v48, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; GFX9-NEXT: v_or_b32_e32 v39, v49, v39
+; GFX9-NEXT: v_lshl_or_b32 v39, v39, 16, v49
; GFX9-NEXT: buffer_store_dword v39, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v50
-; GFX9-NEXT: v_or_b32_e32 v37, v37, v39
; GFX9-NEXT: buffer_store_dword v37, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v37, v37, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; GFX9-NEXT: v_or_b32_e32 v24, v24, v37
+; GFX9-NEXT: v_lshl_or_b32 v24, v37, 16, v24
; GFX9-NEXT: buffer_store_dword v24, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: buffer_store_dword v18, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -185213,79 +183714,66 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v18, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v18
+; GFX9-NEXT: v_lshl_or_b32 v16, v18, 16, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v35
-; GFX9-NEXT: v_or_b32_e32 v16, v33, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v35, 16, v33
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v23
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v34
-; GFX9-NEXT: v_or_b32_e32 v16, v31, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v34, 16, v31
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v32, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v32
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v36
-; GFX9-NEXT: v_or_b32_e32 v16, v29, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v36, 16, v29
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v30, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v30
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v38
-; GFX9-NEXT: v_or_b32_e32 v16, v27, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v38, 16, v27
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v28, 16, v22
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v25, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v25
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX9-NEXT: v_or_b32_e32 v16, v19, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v26, 16, v19
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v20, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v20
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v15, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185294,8 +183782,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v14, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185305,8 +183792,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185315,8 +183801,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185326,8 +183811,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185336,8 +183820,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v10, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185347,8 +183830,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185357,8 +183839,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185368,8 +183849,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185378,8 +183858,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v6, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185389,8 +183868,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -185399,8 +183877,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -185408,13 +183885,11 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_perm_b32 v1, v2, v41, s4
; GFX9-NEXT: v_perm_b32 v2, v40, v42, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -186109,136 +184584,105 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: v_mov_b32_e32 v148, s0
; GFX11-NEXT: .LBB95_5: ; %end
; GFX11-NEXT: v_perm_b32 v68, v73, v70, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v35, v35, v63, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v70, v62, v72, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v69, v60, v69, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v70
-; GFX11-NEXT: v_perm_b32 v35, v35, v63, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
; GFX11-NEXT: v_perm_b32 v56, v33, v56, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
; GFX11-NEXT: v_perm_b32 v58, v58, v59, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v57, v34, v57, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v34, v36, v70
+; GFX11-NEXT: v_lshl_or_b32 v33, v68, 16, v35
+; GFX11-NEXT: v_lshl_or_b32 v34, v70, 16, v36
+; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v35, v69, 16, v56
; GFX11-NEXT: v_perm_b32 v29, v29, v45, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v65
-; GFX11-NEXT: v_perm_b32 v70, v27, v182, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
-; GFX11-NEXT: v_or_b32_e32 v33, v35, v68
-; GFX11-NEXT: v_or_b32_e32 v35, v56, v69
; GFX11-NEXT: v_perm_b32 v68, v44, v46, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v30, v40, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v69, v41, v42, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v58, 16, v58
-; GFX11-NEXT: v_or_b32_e32 v27, v29, v65
-; GFX11-NEXT: v_or_b32_e32 v29, v70, v64
+; GFX11-NEXT: v_perm_b32 v70, v27, v182, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v182, v28, v183, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v36, v58, 16, v57
+; GFX11-NEXT: v_lshl_or_b32 v27, v65, 16, v29
+; GFX11-NEXT: v_lshl_or_b32 v28, v68, 16, v30
+; GFX11-NEXT: v_lshl_or_b32 v29, v64, 16, v70
+; GFX11-NEXT: v_lshl_or_b32 v30, v69, 16, v182
; GFX11-NEXT: v_perm_b32 v54, v181, v54, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v64, v179, v180, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v53, v178, v53, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v30, v30, v40, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
-; GFX11-NEXT: v_perm_b32 v182, v28, v183, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
-; GFX11-NEXT: v_or_b32_e32 v36, v57, v58
; GFX11-NEXT: v_perm_b32 v23, v23, v177, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-NEXT: v_perm_b32 v53, v178, v53, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v24, v167, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
; GFX11-NEXT: v_perm_b32 v21, v21, v176, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-NEXT: v_or_b32_e32 v28, v30, v68
-; GFX11-NEXT: v_or_b32_e32 v30, v182, v69
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_store_b128 v0, v[33:36], off
; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:16
-; GFX11-NEXT: v_or_b32_e32 v27, v23, v54
+; GFX11-NEXT: v_perm_b32 v30, v160, v51, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v27, v54, 16, v23
; GFX11-NEXT: v_perm_b32 v23, v165, v166, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v28, v24, v64
-; GFX11-NEXT: v_or_b32_e32 v29, v21, v53
+; GFX11-NEXT: v_lshl_or_b32 v28, v64, 16, v24
+; GFX11-NEXT: v_lshl_or_b32 v29, v53, 16, v21
; GFX11-NEXT: v_perm_b32 v21, v22, v164, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v163, v52, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v161, v162, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v30, v160, v51, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v17, v17, v150, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v30
-; GFX11-NEXT: v_or_b32_e32 v30, v21, v23
-; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
+; GFX11-NEXT: v_lshl_or_b32 v30, v23, 16, v21
+; GFX11-NEXT: v_lshl_or_b32 v19, v22, 16, v19
; GFX11-NEXT: v_perm_b32 v22, v147, v148, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v20, v20, v24
+; GFX11-NEXT: v_lshl_or_b32 v20, v24, 16, v20
; GFX11-NEXT: v_or_b32_e32 v21, v17, v33
; GFX11-NEXT: v_perm_b32 v17, v18, v146, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v145, v67, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v133, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v135, v144, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v15, v15, v134, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v24, v133, v66, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v13, v13, v131, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-NEXT: v_perm_b32 v23, v135, v144, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v16, v16, v132, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
-; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
+; GFX11-NEXT: v_lshl_or_b32 v22, v22, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v15
; GFX11-NEXT: v_perm_b32 v18, v129, v130, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v17, v13, v24
-; GFX11-NEXT: v_perm_b32 v24, v115, v48, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v23
+; GFX11-NEXT: v_lshl_or_b32 v17, v24, 16, v13
; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v115, v48, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v9, v113, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v16, v23, 16, v16
; GFX11-NEXT: v_perm_b32 v14, v119, v49, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v117, v118, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v9, v9, v113, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v11, v11, v116, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v114, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v24
+; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v24, 16, v9
; GFX11-NEXT: v_perm_b32 v9, v10, v102, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v101, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
+; GFX11-NEXT: v_perm_b32 v7, v7, v98, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
; GFX11-NEXT: v_perm_b32 v14, v103, v112, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v23
+; GFX11-NEXT: v_lshl_or_b32 v12, v23, 16, v12
; GFX11-NEXT: v_perm_b32 v23, v99, v100, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v97, v37, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v98, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v96, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v5, v5, v87, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
; GFX11-NEXT: v_perm_b32 v10, v85, v86, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v23
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v24
+; GFX11-NEXT: v_perm_b32 v6, v6, v83, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v23, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v9, v24, 16, v5
; GFX11-NEXT: v_perm_b32 v5, v84, v31, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v80, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v71, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v39, v50, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v83, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_perm_b32 v25, v39, v50, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v31, v1, v32, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v26, v2, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v23
-; GFX11-NEXT: v_or_b32_e32 v3, v31, v24
-; GFX11-NEXT: v_or_b32_e32 v4, v26, v25
+; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v23, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v24, 16, v31
+; GFX11-NEXT: v_lshl_or_b32 v4, v25, 16, v26
; GFX11-NEXT: s_clause 0x5
; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
@@ -188667,19 +187111,12 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v10, v37, v36, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v59, v34, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v57, v32, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v47, v46, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v43, v42, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v55, v54, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v51, v50, s6
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr59
@@ -188701,16 +187138,14 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188719,8 +187154,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188729,8 +187163,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188739,8 +187172,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188749,8 +187181,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188759,8 +187190,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188769,24 +187199,22 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_perm_b32 v9, v39, v62, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v38, v61, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v39, v62, s6
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v35, v60, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v33, v58, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v63, v56, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v45, v44, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v41, v40, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_perm_b32 v14, v53, v52, s6
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr61
@@ -188805,7 +187233,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v49, v15, s6
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr49
@@ -188817,16 +187245,14 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_or_b32_e32 v16, v16, v17
+; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v17, v18, v19
+; VI-NEXT: v_lshl_or_b32 v17, v19, 16, v18
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188835,8 +187261,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v18, v18, v19
+; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188845,8 +187270,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v19, v19, v20
+; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188855,8 +187279,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v20, v20, v21
+; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188865,8 +187288,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v21, v21, v22
+; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188875,8 +187297,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v23, v24, s6
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_or_b32_e32 v22, v22, v23
+; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188885,8 +187306,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; VI-NEXT: v_or_b32_e32 v23, v23, v24
+; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188895,8 +187315,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v25, v26, s6
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; VI-NEXT: v_or_b32_e32 v24, v24, v25
+; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188905,8 +187324,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; VI-NEXT: v_or_b32_e32 v25, v25, v26
+; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188915,8 +187333,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; VI-NEXT: v_or_b32_e32 v26, v26, v27
+; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188925,8 +187342,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; VI-NEXT: v_or_b32_e32 v27, v27, v28
+; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188935,8 +187351,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v28, v28, v29
+; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188945,8 +187360,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
-; VI-NEXT: v_or_b32_e32 v29, v29, v30
+; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -188955,8 +187369,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; VI-NEXT: v_or_b32_e32 v30, v30, v31
+; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
@@ -189021,14 +187434,13 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_perm_b32 v32, v33, v32, s6
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v32, v33, v32, s6
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: v_or_b32_e32 v31, v31, v32
+; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
@@ -194489,82 +192901,70 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB97_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s8, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s10
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s8, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s7
-; VI-NEXT: v_perm_b32 v5, s14, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s10
; VI-NEXT: v_perm_b32 v4, s11, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s41
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s14, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s13
-; VI-NEXT: v_perm_b32 v6, s46, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s41
; VI-NEXT: v_perm_b32 v5, s42, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s57
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s46, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s45
-; VI-NEXT: v_perm_b32 v7, s63, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s57
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s61
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s63, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s62
-; VI-NEXT: v_perm_b32 v8, s73, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s61
; VI-NEXT: v_perm_b32 v7, s74, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s12
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s73, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s9
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s12
; VI-NEXT: v_perm_b32 v8, s76, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_mov_b32_e32 v43, v10
; VI-NEXT: v_mov_b32_e32 v10, s43
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v10, s56, v10, v11
; VI-NEXT: v_perm_b32 v9, s44, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_perm_b32 v10, s56, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_mov_b32_e32 v10, s47
; VI-NEXT: v_mov_b32_e32 v35, v12
; VI-NEXT: v_mov_b32_e32 v12, s59
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
-; VI-NEXT: v_mov_b32_e32 v10, s47
-; VI-NEXT: v_perm_b32 v12, s72, v12, v11
; VI-NEXT: v_perm_b32 v10, s60, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s72, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v15, v14, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s75, v13, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v15, v14, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
@@ -194573,26 +192973,22 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v23, v51, v33, s4
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v12, v56, v12, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_perm_b32 v14, v59, v14, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v13, v47, v13, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; VI-NEXT: v_perm_b32 v14, v59, v14, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v15, v32, v15, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v61, v13, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v17, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v21, v16, s4
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v17, v28, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v21, v58, v46, s4
; VI-NEXT: v_perm_b32 v24, v36, v49, s4
; VI-NEXT: v_mov_b32_e32 v28, v52
@@ -194600,44 +192996,36 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v16, v19, v16, s4
; VI-NEXT: v_perm_b32 v19, v26, v22, s4
-; VI-NEXT: v_or_b32_e32 v17, v19, v17
+; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v19
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; VI-NEXT: v_or_b32_e32 v15, v16, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; VI-NEXT: v_perm_b32 v16, v25, v20, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_or_b32_e32 v16, v18, v16
+; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v18
; VI-NEXT: v_perm_b32 v18, v45, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v20, v44, v29, s4
; VI-NEXT: v_perm_b32 v22, v53, v42, s4
; VI-NEXT: v_mov_b32_e32 v45, v34
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v19, v30, v19, s4
-; VI-NEXT: v_or_b32_e32 v18, v19, v18
+; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
; VI-NEXT: v_perm_b32 v19, v55, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_or_b32_e32 v19, v20, v19
+; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
; VI-NEXT: v_perm_b32 v20, v39, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; VI-NEXT: v_or_b32_e32 v20, v21, v20
+; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
; VI-NEXT: v_perm_b32 v21, v38, v63, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v21, v22, v21
+; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
; VI-NEXT: v_perm_b32 v22, v54, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v22, v23, v22
+; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
; VI-NEXT: v_perm_b32 v23, v40, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; VI-NEXT: v_or_b32_e32 v23, v24, v23
+; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
; VI-NEXT: v_perm_b32 v24, v48, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_mov_b32_e32 v48, v25
; VI-NEXT: v_perm_b32 v25, v25, v41, s4
-; VI-NEXT: v_or_b32_e32 v24, v25, v24
+; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v34, v33
; VI-NEXT: v_mov_b32_e32 v33, v26
@@ -194649,45 +193037,40 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_or_b32_e32 v25, v26, v25
+; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
-; VI-NEXT: v_or_b32_e32 v26, v27, v26
+; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v28, v29, s4
-; VI-NEXT: v_or_b32_e32 v27, v28, v27
+; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v28, v28, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v62, v29, s4
-; VI-NEXT: v_or_b32_e32 v28, v29, v28
+; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v62, v44
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v43, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; VI-NEXT: v_or_b32_e32 v29, v30, v29
+; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
@@ -194695,18 +193078,16 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
-; VI-NEXT: v_or_b32_e32 v30, v31, v30
+; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_mov_b32_e32 v35, v43
; VI-NEXT: v_perm_b32 v43, v44, v43, s4
-; VI-NEXT: v_or_b32_e32 v31, v43, v31
+; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
; VI-NEXT: v_mov_b32_e32 v43, v39
; VI-NEXT: v_mov_b32_e32 v39, v34
; VI-NEXT: v_mov_b32_e32 v34, v52
@@ -196206,12 +194587,11 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB97_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
@@ -196225,134 +194605,117 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v15, 0xff, v50
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s88 :: v_dual_and_b32 v29, 0xff, v166
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v37, 8, v10
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v86, 8, s88
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v70, 8, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v33, 8, v15
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v32, 8, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v39, 8, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v119, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v82, 8, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v64, 8, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v128, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v101, 8, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v87, 8, v10
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v150, 8, v8
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v102, 8, v30
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v132, 8, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v183, v129, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v41, v133, 8, v29
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v178, 8, v40
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
@@ -196724,10 +195087,11 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s74, 0xff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v33
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v48
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v32
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
@@ -196743,61 +195107,52 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s11, s8, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s76, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
-; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v35, 8, s76
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v33, 8, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v32, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v9, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v36
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v11, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v37, 8, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v36, 8, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v14, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v34, 8, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v82, v64, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v9, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v96, v85, 0xc0c0004
@@ -196807,18 +195162,18 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v117
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v144
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v10, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v84, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v19, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v87, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v135
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v150
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v11, 16, v9
@@ -196834,82 +195189,72 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v11, 16, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v117, 8, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v134
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v119
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-FAKE16-NEXT: s_and_b32 s77, s62, 0xff
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v114, 8, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v119, 8, v10
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s59, 8
; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s45, 8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v24, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v114
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_and_b32 s78, s56, 0xff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v24, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s79
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
; GFX11-FAKE16-NEXT: s_and_b32 s79, s63, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s61, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v144, 8, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v147, 8, v10
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v147
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v26, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v133
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v26, v27
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v133, 8, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v26
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v177
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v164
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v151
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v28, v29
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v164, 8, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v135, 8, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v176
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v161
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v28, v29
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v161, 8, v28
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v179, v163, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v165
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v178
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v166
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v11, v31
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v165, 8, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v166, 8, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v150, 8, v30
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v40
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB97_3
@@ -199615,181 +197960,151 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB98_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v31, 3
-; VI-NEXT: v_add_u16_sdwa v55, v18, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v32, 3, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v55
+; VI-NEXT: v_add_u16_sdwa v55, v18, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v18, v32, v18
+; VI-NEXT: v_lshl_or_b32 v18, v55, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v17
; VI-NEXT: v_add_u16_sdwa v17, v17, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; VI-NEXT: v_add_u16_sdwa v54, v20, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v17, v32, v17
+; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v20
-; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v54
+; VI-NEXT: v_add_u16_sdwa v54, v20, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v20, v32, v20
+; VI-NEXT: v_lshl_or_b32 v20, v54, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v19
; VI-NEXT: v_add_u16_sdwa v19, v19, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; VI-NEXT: v_add_u16_sdwa v57, v22, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v19, v32, v19
+; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v22
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v57
-; VI-NEXT: v_add_u16_sdwa v52, v21, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v57, v22, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v22, v32, v22
+; VI-NEXT: v_lshl_or_b32 v22, v57, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v21
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v52
-; VI-NEXT: v_add_u16_sdwa v56, v24, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v52, v21, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v21, v32, v21
+; VI-NEXT: v_lshl_or_b32 v21, v52, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v24
-; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v56
-; VI-NEXT: v_add_u16_sdwa v50, v23, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v56, v24, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v24, v32, v24
+; VI-NEXT: v_lshl_or_b32 v24, v56, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v23
-; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v50
-; VI-NEXT: v_add_u16_sdwa v49, v26, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v50, v23, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v23, v32, v23
+; VI-NEXT: v_lshl_or_b32 v23, v50, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v26
-; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v49
-; VI-NEXT: v_add_u16_sdwa v59, v25, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v49, v26, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v26, v32, v26
+; VI-NEXT: v_lshl_or_b32 v26, v49, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v25
-; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v59
-; VI-NEXT: v_add_u16_sdwa v38, v28, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v59, v25, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v25, v32, v25
+; VI-NEXT: v_lshl_or_b32 v25, v59, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v28
-; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v38
-; VI-NEXT: v_add_u16_sdwa v35, v27, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v38, v28, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v28, v32, v28
+; VI-NEXT: v_lshl_or_b32 v28, v38, 16, v32
; VI-NEXT: v_add_u16_e32 v32, 3, v27
-; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v35
-; VI-NEXT: v_add_u16_sdwa v48, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v27, v32, v27
-; VI-NEXT: v_add_u16_e32 v32, 3, v30
+; VI-NEXT: v_add_u16_sdwa v35, v27, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v33, 3, v29
; VI-NEXT: v_add_u16_sdwa v34, v29, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
-; VI-NEXT: v_or_b32_e32 v30, v32, v29
-; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v34
-; VI-NEXT: v_add_u16_sdwa v53, v37, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v27, v35, 16, v32
+; VI-NEXT: v_add_u16_e32 v32, 3, v30
+; VI-NEXT: v_add_u16_sdwa v48, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v29, v33, v29
+; VI-NEXT: v_lshl_or_b32 v29, v34, 16, v33
; VI-NEXT: v_add_u16_e32 v34, 3, v37
-; VI-NEXT: v_add_u16_sdwa v33, v36, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v53
+; VI-NEXT: v_add_u16_sdwa v53, v37, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v39, 3, v36
-; VI-NEXT: v_or_b32_e32 v37, v34, v32
-; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v33
-; VI-NEXT: v_add_u16_sdwa v47, v2, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v33, v36, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v30, v48, 16, v32
; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v37, v53, 16, v34
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v36, v39, v32
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v36, v33, 16, v39
; VI-NEXT: v_add_u16_e32 v33, 3, v2
+; VI-NEXT: v_add_u16_sdwa v47, v2, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v34, 3, v1
; VI-NEXT: v_add_u16_sdwa v32, v1, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v47
-; VI-NEXT: v_or_b32_e32 v2, v33, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
-; VI-NEXT: v_add_u16_sdwa v46, v4, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v2, v47, 16, v33
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v1, v34, v1
+; VI-NEXT: v_lshl_or_b32 v1, v32, 16, v34
; VI-NEXT: v_add_u16_e32 v33, 3, v4
+; VI-NEXT: v_add_u16_sdwa v46, v4, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v34, 3, v3
; VI-NEXT: v_add_u16_sdwa v32, v3, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v46
-; VI-NEXT: v_or_b32_e32 v4, v33, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v32
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v3, v34, v3
-; VI-NEXT: v_add_u16_sdwa v34, v6, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v4, v46, 16, v33
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v3, v32, 16, v34
; VI-NEXT: v_add_u16_e32 v33, 3, v6
+; VI-NEXT: v_add_u16_sdwa v34, v6, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v39, 3, v5
; VI-NEXT: v_add_u16_sdwa v32, v5, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v34
-; VI-NEXT: v_or_b32_e32 v6, v33, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v32
-; VI-NEXT: v_add_u16_sdwa v62, v8, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v6, v34, 16, v33
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v5, v39, v5
+; VI-NEXT: v_lshl_or_b32 v5, v32, 16, v39
; VI-NEXT: v_add_u16_e32 v39, 3, v8
+; VI-NEXT: v_add_u16_sdwa v62, v8, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v33, 3, v7
; VI-NEXT: v_add_u16_sdwa v32, v7, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v62
-; VI-NEXT: v_or_b32_e32 v8, v39, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
-; VI-NEXT: v_add_u16_sdwa v61, v10, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v8, v62, 16, v39
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v7, v33, v7
-; VI-NEXT: v_add_u16_e32 v33, 3, v10
+; VI-NEXT: v_lshl_or_b32 v7, v32, 16, v33
; VI-NEXT: v_add_u16_e32 v39, 3, v9
; VI-NEXT: v_add_u16_sdwa v32, v9, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v61
-; VI-NEXT: v_or_b32_e32 v10, v33, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v32
-; VI-NEXT: v_add_u16_sdwa v60, v12, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; VI-NEXT: v_add_u16_e32 v33, 3, v10
+; VI-NEXT: v_add_u16_sdwa v61, v10, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v9, v39, v9
-; VI-NEXT: v_add_u16_e32 v33, 3, v12
+; VI-NEXT: v_lshl_or_b32 v9, v32, 16, v39
; VI-NEXT: v_add_u16_e32 v39, 3, v11
; VI-NEXT: v_add_u16_sdwa v32, v11, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v60
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v12, v33, v11
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
-; VI-NEXT: v_add_u16_sdwa v33, v14, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v10, v61, 16, v33
+; VI-NEXT: v_add_u16_e32 v33, 3, v12
+; VI-NEXT: v_add_u16_sdwa v60, v12, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v11, v39, v11
-; VI-NEXT: v_add_u16_e32 v39, 3, v14
+; VI-NEXT: v_lshl_or_b32 v11, v32, 16, v39
; VI-NEXT: v_add_u16_e32 v40, 3, v13
; VI-NEXT: v_add_u16_sdwa v32, v13, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v33
; VI-NEXT: v_add_u16_sdwa v63, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v14, v39, v13
+; VI-NEXT: v_add_u16_e32 v16, 3, v16
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v12, v60, 16, v33
+; VI-NEXT: v_add_u16_sdwa v33, v14, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v32
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v13, v32, 16, v40
; VI-NEXT: v_add_u16_sdwa v31, v15, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v16, 3, v16
; VI-NEXT: v_add_u16_e32 v32, 3, v15
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v63
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v16, v16, v15
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v31
+; VI-NEXT: v_lshl_or_b32 v16, v63, 16, v16
; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v15, v32, v15
+; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; VI-NEXT: v_lshl_or_b32 v15, v31, 16, v32
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v16
; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v15
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[15:16]
+; VI-NEXT: v_add_u16_e32 v39, 3, v14
+; VI-NEXT: v_lshl_or_b32 v14, v33, 16, v39
; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: v_or_b32_e32 v13, v40, v13
; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v14
; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v13
@@ -199821,7 +198136,6 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v3
@@ -199898,7 +198212,6 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; VI-NEXT: v_bfe_u32 v1, v49, 8, 8
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[39:40], 24, v[23:24]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
@@ -199930,8 +198243,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v41, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
@@ -199940,8 +198252,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v47, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
@@ -199951,8 +198262,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
@@ -199962,8 +198272,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v46, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
@@ -199973,10 +198282,9 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -199986,8 +198294,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v34, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
@@ -199997,10 +198304,9 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
@@ -200010,8 +198316,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v62, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
@@ -200021,10 +198326,9 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
@@ -200034,8 +198338,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v61, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
@@ -200045,10 +198348,9 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -200058,8 +198360,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v60, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -200069,10 +198370,9 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
@@ -200082,8 +198382,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v33, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
@@ -200093,10 +198392,9 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
@@ -200106,8 +198404,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v63, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
@@ -200116,16 +198413,14 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v44, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v58, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v57, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v40, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
@@ -200134,8 +198429,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v43, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v32, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
@@ -200143,8 +198437,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: v_perm_b32 v2, v55, v49, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
@@ -200152,8 +198445,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: v_perm_b32 v2, v52, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -200161,8 +198453,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: v_perm_b32 v2, v51, v38, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
@@ -200170,8 +198461,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: v_perm_b32 v2, v50, v39, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -200181,8 +198471,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v56, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
@@ -200193,8 +198482,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v59, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
@@ -200205,8 +198493,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
@@ -200217,8 +198504,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v35, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
@@ -200228,8 +198514,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v45, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
@@ -200241,8 +198526,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
@@ -200253,8 +198537,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
@@ -200266,8 +198549,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
@@ -200278,8 +198560,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v53, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -204233,114 +202514,99 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 27
; VI-NEXT: v_mov_b32_e32 v24, s16
; VI-NEXT: v_readlane_b32 s16, v33, 28
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_perm_b32 v24, s16, v24, v1
-; VI-NEXT: v_or_b32_e32 v3, v3, v10
; VI-NEXT: v_mov_b32_e32 v13, s38
+; VI-NEXT: v_perm_b32 v24, s16, v24, v1
; VI-NEXT: v_readlane_b32 s16, v33, 26
-; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v24
; VI-NEXT: v_perm_b32 v13, s16, v13, v1
; VI-NEXT: v_readlane_b32 s16, v33, 24
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
-; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: v_mov_b32_e32 v25, s16
; VI-NEXT: v_readlane_b32 s16, v33, 25
-; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
-; VI-NEXT: v_perm_b32 v25, s16, v25, v1
-; VI-NEXT: v_or_b32_e32 v2, v5, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: v_mov_b32_e32 v16, s36
+; VI-NEXT: v_perm_b32 v25, s16, v25, v1
; VI-NEXT: v_readlane_b32 s16, v33, 23
-; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v25
; VI-NEXT: v_perm_b32 v16, s16, v16, v1
; VI-NEXT: v_readlane_b32 s16, v33, 21
-; VI-NEXT: v_or_b32_e32 v2, v4, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
; VI-NEXT: v_mov_b32_e32 v26, s16
; VI-NEXT: v_readlane_b32 s16, v33, 22
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v16
-; VI-NEXT: v_perm_b32 v26, s16, v26, v1
-; VI-NEXT: v_or_b32_e32 v2, v7, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
; VI-NEXT: v_mov_b32_e32 v19, s34
+; VI-NEXT: v_perm_b32 v26, s16, v26, v1
; VI-NEXT: v_readlane_b32 s16, v33, 20
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
+; VI-NEXT: v_lshl_or_b32 v3, v10, 16, v3
; VI-NEXT: v_perm_b32 v19, s16, v19, v1
; VI-NEXT: v_readlane_b32 s16, v33, 18
-; VI-NEXT: v_or_b32_e32 v2, v6, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
+; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v24, 16, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: v_mov_b32_e32 v27, s16
; VI-NEXT: v_readlane_b32 s16, v33, 19
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
-; VI-NEXT: v_perm_b32 v27, s16, v27, v1
-; VI-NEXT: v_or_b32_e32 v2, v9, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v13, 16, v5
+; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: v_mov_b32_e32 v20, s30
+; VI-NEXT: v_perm_b32 v27, s16, v27, v1
; VI-NEXT: v_readlane_b32 s16, v33, 17
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v25, 16, v4
+; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
; VI-NEXT: v_perm_b32 v20, s16, v20, v1
; VI-NEXT: v_readlane_b32 s16, v33, 15
-; VI-NEXT: v_or_b32_e32 v2, v8, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v16, 16, v7
+; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
; VI-NEXT: v_mov_b32_e32 v28, s16
; VI-NEXT: v_readlane_b32 s16, v33, 16
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
-; VI-NEXT: v_perm_b32 v28, s16, v28, v1
-; VI-NEXT: v_or_b32_e32 v2, v12, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
+; VI-NEXT: v_lshl_or_b32 v2, v26, 16, v6
+; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
; VI-NEXT: v_mov_b32_e32 v21, s90
+; VI-NEXT: v_perm_b32 v28, s16, v28, v1
; VI-NEXT: v_readlane_b32 s16, v33, 13
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v28
+; VI-NEXT: v_lshl_or_b32 v2, v19, 16, v9
+; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
; VI-NEXT: v_perm_b32 v21, s16, v21, v1
; VI-NEXT: v_readlane_b32 s16, v33, 10
-; VI-NEXT: v_or_b32_e32 v2, v11, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v27, 16, v8
+; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
; VI-NEXT: v_mov_b32_e32 v29, s16
; VI-NEXT: v_readlane_b32 s16, v33, 11
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
-; VI-NEXT: v_perm_b32 v29, s16, v29, v1
-; VI-NEXT: v_or_b32_e32 v2, v15, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
+; VI-NEXT: v_lshl_or_b32 v2, v20, 16, v12
+; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
; VI-NEXT: v_mov_b32_e32 v22, s88
+; VI-NEXT: v_perm_b32 v29, s16, v29, v1
; VI-NEXT: v_readlane_b32 s16, v33, 8
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
+; VI-NEXT: v_lshl_or_b32 v2, v28, 16, v11
+; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
; VI-NEXT: v_perm_b32 v22, s16, v22, v1
; VI-NEXT: v_readlane_b32 s16, v33, 5
-; VI-NEXT: v_or_b32_e32 v2, v14, v2
-; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v21, 16, v15
+; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
; VI-NEXT: v_perm_b32 v18, s28, v17, v1
; VI-NEXT: v_mov_b32_e32 v30, s16
; VI-NEXT: v_readlane_b32 s16, v33, 6
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
+; VI-NEXT: v_lshl_or_b32 v2, v29, 16, v14
+; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
+; VI-NEXT: v_perm_b32 v17, s29, v23, v1
; VI-NEXT: v_perm_b32 v30, s16, v30, v1
; VI-NEXT: v_readlane_b32 s16, v33, 4
-; VI-NEXT: v_or_b32_e32 v2, v18, v2
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshl_or_b32 v2, v22, 16, v18
; VI-NEXT: v_add_u32_e32 v4, vcc, 48, v0
-; VI-NEXT: v_perm_b32 v17, s29, v23, v1
; VI-NEXT: v_mov_b32_e32 v23, s78
; VI-NEXT: v_mov_b32_e32 v31, s16
; VI-NEXT: v_readlane_b32 s16, v33, 3
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
-; VI-NEXT: v_perm_b32 v3, s16, v23, v1
-; VI-NEXT: v_or_b32_e32 v2, v17, v2
+; VI-NEXT: v_lshl_or_b32 v2, v30, 16, v17
; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
+; VI-NEXT: v_perm_b32 v3, s16, v23, v1
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, s44, v31, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: v_readlane_b32 s16, v33, 2
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204348,42 +202614,37 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 0
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 1
-; VI-NEXT: v_perm_b32 v3, s16, v3, v1
; VI-NEXT: v_perm_b32 v2, s45, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s16, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 60, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s76
; VI-NEXT: v_mov_b32_e32 v2, s70
-; VI-NEXT: v_perm_b32 v3, s53, v3, v1
+; VI-NEXT: v_mov_b32_e32 v3, s76
; VI-NEXT: v_perm_b32 v2, s42, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s53, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 64, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s55
; VI-NEXT: v_mov_b32_e32 v2, s52
-; VI-NEXT: v_perm_b32 v3, s65, v3, v1
+; VI-NEXT: v_mov_b32_e32 v3, s55
; VI-NEXT: v_perm_b32 v2, s43, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s65, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_mov_b32_e32 v2, s85
-; VI-NEXT: v_perm_b32 v3, s50, v3, v1
+; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_perm_b32 v2, s40, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s50, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s84
; VI-NEXT: v_mov_b32_e32 v2, s51
-; VI-NEXT: v_perm_b32 v3, s80, v3, v1
+; VI-NEXT: v_mov_b32_e32 v3, s84
; VI-NEXT: v_perm_b32 v2, s41, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s80, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v2, s83
@@ -204391,18 +202652,16 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: v_readlane_b32 s14, v33, 57
; VI-NEXT: v_perm_b32 v3, s14, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x50, v0
; VI-NEXT: v_readlane_b32 s14, v33, 55
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_mov_b32_e32 v2, s69
; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_readlane_b32 s14, v33, 56
-; VI-NEXT: v_mov_b32_e32 v2, s69
-; VI-NEXT: v_perm_b32 v3, s14, v3, v1
; VI-NEXT: v_perm_b32 v2, s15, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s14, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x54, v0
; VI-NEXT: v_readlane_b32 s14, v33, 54
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204411,8 +202670,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s62
; VI-NEXT: v_readlane_b32 s12, v33, 53
; VI-NEXT: v_perm_b32 v3, s12, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x58, v0
; VI-NEXT: v_readlane_b32 s12, v33, 52
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204420,10 +202678,9 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s12, v33, 50
; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_readlane_b32 s12, v33, 51
-; VI-NEXT: v_perm_b32 v3, s12, v3, v1
; VI-NEXT: v_perm_b32 v2, s13, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s12, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x5c, v0
; VI-NEXT: v_readlane_b32 s12, v33, 49
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204432,8 +202689,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s60
; VI-NEXT: v_readlane_b32 s10, v33, 48
; VI-NEXT: v_perm_b32 v3, s10, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x60, v0
; VI-NEXT: v_readlane_b32 s10, v33, 47
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204441,10 +202697,9 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s10, v33, 45
; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_readlane_b32 s10, v33, 46
-; VI-NEXT: v_perm_b32 v3, s10, v3, v1
; VI-NEXT: v_perm_b32 v2, s11, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s10, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x64, v0
; VI-NEXT: v_readlane_b32 s10, v33, 44
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204453,8 +202708,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s58
; VI-NEXT: v_readlane_b32 s8, v33, 43
; VI-NEXT: v_perm_b32 v3, s8, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x68, v0
; VI-NEXT: v_readlane_b32 s8, v33, 42
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204462,10 +202716,9 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s8, v33, 40
; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_readlane_b32 s8, v33, 41
-; VI-NEXT: v_perm_b32 v3, s8, v3, v1
; VI-NEXT: v_perm_b32 v2, s9, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s8, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x6c, v0
; VI-NEXT: v_readlane_b32 s8, v33, 39
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204474,8 +202727,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_readlane_b32 s6, v33, 38
; VI-NEXT: v_perm_b32 v3, s6, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x70, v0
; VI-NEXT: v_readlane_b32 s6, v33, 37
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204483,10 +202735,9 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s6, v33, 35
; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_readlane_b32 s6, v33, 36
-; VI-NEXT: v_perm_b32 v3, s6, v3, v1
; VI-NEXT: v_perm_b32 v2, s7, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s6, v3, v1
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x74, v0
; VI-NEXT: v_readlane_b32 s6, v33, 34
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204495,8 +202746,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s46
; VI-NEXT: v_readlane_b32 s4, v33, 33
; VI-NEXT: v_perm_b32 v3, s4, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x78, v0
; VI-NEXT: v_readlane_b32 s4, v33, 32
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -204506,8 +202756,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s4, v33, 31
; VI-NEXT: v_perm_b32 v2, s5, v2, v1
; VI-NEXT: v_perm_b32 v1, s4, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_readlane_b32 s30, v32, 30
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -205604,8 +203853,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v39, v39, v44, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; GFX9-NEXT: v_or_b32_e32 v39, v48, v39
+; GFX9-NEXT: v_lshl_or_b32 v39, v39, 16, v48
+; GFX9-NEXT: v_lshl_or_b32 v37, v50, 16, v37
; GFX9-NEXT: v_perm_b32 v23, v34, v23, s4
; GFX9-NEXT: v_perm_b32 v32, v32, v59, s4
; GFX9-NEXT: v_perm_b32 v29, v29, v57, s4
@@ -205659,8 +203908,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: v_perm_b32 v18, v18, v54, s4
; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v18, v21, v18
+; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v21
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v38, v47, v52, s4
; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -205691,22 +203939,17 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v39, v39, v48, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; GFX9-NEXT: v_or_b32_e32 v39, v49, v39
+; GFX9-NEXT: v_lshl_or_b32 v39, v39, 16, v49
; GFX9-NEXT: buffer_store_dword v39, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v50
-; GFX9-NEXT: v_or_b32_e32 v37, v37, v39
; GFX9-NEXT: buffer_store_dword v37, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v37, v37, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; GFX9-NEXT: v_or_b32_e32 v24, v24, v37
+; GFX9-NEXT: v_lshl_or_b32 v24, v37, 16, v24
; GFX9-NEXT: buffer_store_dword v24, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: buffer_store_dword v18, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -205714,79 +203957,66 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v18, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v18
+; GFX9-NEXT: v_lshl_or_b32 v16, v18, 16, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v35
-; GFX9-NEXT: v_or_b32_e32 v16, v33, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v35, 16, v33
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v23
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v34
-; GFX9-NEXT: v_or_b32_e32 v16, v31, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v34, 16, v31
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v32, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v32
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v36
-; GFX9-NEXT: v_or_b32_e32 v16, v29, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v36, 16, v29
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v30, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v30
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v38
-; GFX9-NEXT: v_or_b32_e32 v16, v27, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v38, 16, v27
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v28, 16, v22
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v25, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v25
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX9-NEXT: v_or_b32_e32 v16, v19, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v26, 16, v19
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v20, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v20
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v15, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205795,8 +204025,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v14, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205806,8 +204035,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205816,8 +204044,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205827,8 +204054,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205837,8 +204063,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v10, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205848,8 +204073,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205858,8 +204082,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205869,8 +204092,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205879,8 +204101,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v6, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205890,8 +204111,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -205900,8 +204120,7 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -205909,13 +204128,11 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_perm_b32 v1, v2, v41, s4
; GFX9-NEXT: v_perm_b32 v2, v40, v42, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -206610,136 +204827,105 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX11-NEXT: v_mov_b32_e32 v148, s0
; GFX11-NEXT: .LBB99_5: ; %end
; GFX11-NEXT: v_perm_b32 v68, v73, v70, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v35, v35, v63, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v70, v62, v72, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v69, v60, v69, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v70
-; GFX11-NEXT: v_perm_b32 v35, v35, v63, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
; GFX11-NEXT: v_perm_b32 v56, v33, v56, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
; GFX11-NEXT: v_perm_b32 v58, v58, v59, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v57, v34, v57, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v34, v36, v70
+; GFX11-NEXT: v_lshl_or_b32 v33, v68, 16, v35
+; GFX11-NEXT: v_lshl_or_b32 v34, v70, 16, v36
+; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v35, v69, 16, v56
; GFX11-NEXT: v_perm_b32 v29, v29, v45, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v65
-; GFX11-NEXT: v_perm_b32 v70, v27, v182, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
-; GFX11-NEXT: v_or_b32_e32 v33, v35, v68
-; GFX11-NEXT: v_or_b32_e32 v35, v56, v69
; GFX11-NEXT: v_perm_b32 v68, v44, v46, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v30, v40, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v69, v41, v42, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v58, 16, v58
-; GFX11-NEXT: v_or_b32_e32 v27, v29, v65
-; GFX11-NEXT: v_or_b32_e32 v29, v70, v64
+; GFX11-NEXT: v_perm_b32 v70, v27, v182, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v182, v28, v183, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v36, v58, 16, v57
+; GFX11-NEXT: v_lshl_or_b32 v27, v65, 16, v29
+; GFX11-NEXT: v_lshl_or_b32 v28, v68, 16, v30
+; GFX11-NEXT: v_lshl_or_b32 v29, v64, 16, v70
+; GFX11-NEXT: v_lshl_or_b32 v30, v69, 16, v182
; GFX11-NEXT: v_perm_b32 v54, v181, v54, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v64, v179, v180, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v53, v178, v53, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v30, v30, v40, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
-; GFX11-NEXT: v_perm_b32 v182, v28, v183, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
-; GFX11-NEXT: v_or_b32_e32 v36, v57, v58
; GFX11-NEXT: v_perm_b32 v23, v23, v177, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-NEXT: v_perm_b32 v53, v178, v53, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v24, v167, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
; GFX11-NEXT: v_perm_b32 v21, v21, v176, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-NEXT: v_or_b32_e32 v28, v30, v68
-; GFX11-NEXT: v_or_b32_e32 v30, v182, v69
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_store_b128 v0, v[33:36], off
; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:16
-; GFX11-NEXT: v_or_b32_e32 v27, v23, v54
+; GFX11-NEXT: v_perm_b32 v30, v160, v51, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v27, v54, 16, v23
; GFX11-NEXT: v_perm_b32 v23, v165, v166, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v28, v24, v64
-; GFX11-NEXT: v_or_b32_e32 v29, v21, v53
+; GFX11-NEXT: v_lshl_or_b32 v28, v64, 16, v24
+; GFX11-NEXT: v_lshl_or_b32 v29, v53, 16, v21
; GFX11-NEXT: v_perm_b32 v21, v22, v164, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v163, v52, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v161, v162, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v30, v160, v51, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v17, v17, v150, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v30
-; GFX11-NEXT: v_or_b32_e32 v30, v21, v23
-; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
+; GFX11-NEXT: v_lshl_or_b32 v30, v23, 16, v21
+; GFX11-NEXT: v_lshl_or_b32 v19, v22, 16, v19
; GFX11-NEXT: v_perm_b32 v22, v147, v148, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v20, v20, v24
+; GFX11-NEXT: v_lshl_or_b32 v20, v24, 16, v20
; GFX11-NEXT: v_or_b32_e32 v21, v17, v33
; GFX11-NEXT: v_perm_b32 v17, v18, v146, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v145, v67, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v133, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v135, v144, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v15, v15, v134, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v24, v133, v66, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v13, v13, v131, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-NEXT: v_perm_b32 v23, v135, v144, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v16, v16, v132, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
-; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
+; GFX11-NEXT: v_lshl_or_b32 v22, v22, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v15
; GFX11-NEXT: v_perm_b32 v18, v129, v130, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v17, v13, v24
-; GFX11-NEXT: v_perm_b32 v24, v115, v48, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v23
+; GFX11-NEXT: v_lshl_or_b32 v17, v24, 16, v13
; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v115, v48, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v9, v113, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v16, v23, 16, v16
; GFX11-NEXT: v_perm_b32 v14, v119, v49, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v117, v118, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v9, v9, v113, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v11, v11, v116, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v114, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v24
+; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v24, 16, v9
; GFX11-NEXT: v_perm_b32 v9, v10, v102, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v101, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
+; GFX11-NEXT: v_perm_b32 v7, v7, v98, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
; GFX11-NEXT: v_perm_b32 v14, v103, v112, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v23
+; GFX11-NEXT: v_lshl_or_b32 v12, v23, 16, v12
; GFX11-NEXT: v_perm_b32 v23, v99, v100, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v97, v37, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v98, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v96, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v5, v5, v87, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
; GFX11-NEXT: v_perm_b32 v10, v85, v86, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v23
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v24
+; GFX11-NEXT: v_perm_b32 v6, v6, v83, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v23, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v9, v24, 16, v5
; GFX11-NEXT: v_perm_b32 v5, v84, v31, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v80, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v71, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v39, v50, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v83, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_perm_b32 v25, v39, v50, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v31, v1, v32, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v26, v2, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v23
-; GFX11-NEXT: v_or_b32_e32 v3, v31, v24
-; GFX11-NEXT: v_or_b32_e32 v4, v26, v25
+; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v23, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v24, 16, v31
+; GFX11-NEXT: v_lshl_or_b32 v4, v25, 16, v26
; GFX11-NEXT: s_clause 0x5
; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index 7e231f48de12a..9e9b7ab09c7d7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -4107,22 +4107,18 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB26_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v17, v20, s6
; VI-NEXT: v_perm_b32 v0, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v17, v20, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -4609,31 +4605,27 @@ define inreg <4 x i32> @bitcast_v16i8_to_v4i32_scalar(<16 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB27_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v3
; VI-NEXT: v_perm_b32 v0, s16, v0, v3
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v3
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v3
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v3
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v2, v2, v4
+; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v3, v4, v3
+; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; VI-NEXT: s_cbranch_execnz .LBB27_3
; VI-NEXT: .LBB27_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -4692,31 +4684,27 @@ define inreg <4 x i32> @bitcast_v16i8_to_v4i32_scalar(<16 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -8634,22 +8622,18 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB50_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v17, v20, s6
; VI-NEXT: v_perm_b32 v0, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v17, v20, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -9136,31 +9120,27 @@ define inreg <4 x float> @bitcast_v16i8_to_v4f32_scalar(<16 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v3
; VI-NEXT: v_perm_b32 v0, s16, v0, v3
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v3
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v3
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v3
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v2, v2, v4
+; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v3, v4, v3
+; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -9219,31 +9199,27 @@ define inreg <4 x float> @bitcast_v16i8_to_v4f32_scalar(<16 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -12746,22 +12722,18 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB70_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v17, v20, s6
; VI-NEXT: v_perm_b32 v0, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v17, v20, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -13248,31 +13220,27 @@ define inreg <2 x i64> @bitcast_v16i8_to_v2i64_scalar(<16 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB71_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v3
; VI-NEXT: v_perm_b32 v0, s16, v0, v3
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v3
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v3
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v3
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v2, v2, v4
+; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v3, v4, v3
+; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; VI-NEXT: s_cbranch_execnz .LBB71_3
; VI-NEXT: .LBB71_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -13331,31 +13299,27 @@ define inreg <2 x i64> @bitcast_v16i8_to_v2i64_scalar(<16 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -16496,22 +16460,18 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB86_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v17, v20, s6
; VI-NEXT: v_perm_b32 v0, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v17, v20, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -16998,31 +16958,27 @@ define inreg <2 x double> @bitcast_v16i8_to_v2f64_scalar(<16 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB87_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v3
; VI-NEXT: v_perm_b32 v0, s16, v0, v3
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v3
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v3
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v3
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v2, v2, v4
+; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v3, v4, v3
+; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; VI-NEXT: s_cbranch_execnz .LBB87_3
; VI-NEXT: .LBB87_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -17081,31 +17037,27 @@ define inreg <2 x double> @bitcast_v16i8_to_v2f64_scalar(<16 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -19270,22 +19222,18 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB96_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v3, 3
-; VI-NEXT: v_add_u16_sdwa v6, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v2, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v14, v19, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v10, v18, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v17, 3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; VI-NEXT: v_add_u16_sdwa v6, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v16, 3, v0
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; VI-NEXT: v_add_u16_sdwa v2, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v21, 3, v19
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
+; VI-NEXT: v_add_u16_sdwa v14, v19, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v8, 3, v18
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
-; VI-NEXT: v_or_b32_e32 v1, v17, v1
-; VI-NEXT: v_or_b32_e32 v0, v16, v0
-; VI-NEXT: v_or_b32_e32 v19, v21, v4
-; VI-NEXT: v_or_b32_e32 v18, v8, v3
+; VI-NEXT: v_add_u16_sdwa v10, v18, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v17
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v16
+; VI-NEXT: v_lshl_or_b32 v19, v14, 16, v21
+; VI-NEXT: v_lshl_or_b32 v18, v10, 16, v8
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[18:19]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v19
@@ -20015,22 +19963,18 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB98_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v17, v20, s6
; VI-NEXT: v_perm_b32 v0, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v17, v20, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -20544,31 +20488,27 @@ define inreg <8 x i16> @bitcast_v16i8_to_v8i16_scalar(<16 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB99_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v3
; VI-NEXT: v_perm_b32 v0, s16, v0, v3
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v3
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v3
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v3
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v2, v2, v4
+; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v3, v4, v3
+; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; VI-NEXT: s_cbranch_execnz .LBB99_3
; VI-NEXT: .LBB99_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -20627,31 +20567,27 @@ define inreg <8 x i16> @bitcast_v16i8_to_v8i16_scalar(<16 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB99_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB99_3
; GFX9-NEXT: .LBB99_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -22246,21 +22182,17 @@ define <16 x i8> @bitcast_v8f16_to_v16i8(<8 x half> %a, i32 %b) #0 {
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v3, 0x200
; VI-NEXT: v_add_f16_sdwa v6, v19, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
; VI-NEXT: v_add_f16_e32 v19, 0x200, v19
; VI-NEXT: v_add_f16_sdwa v2, v18, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_sdwa v14, v17, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_sdwa v10, v16, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v1, v19, v0
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; VI-NEXT: v_add_f16_e32 v18, 0x200, v18
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
+; VI-NEXT: v_add_f16_sdwa v14, v17, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v17, 0x200, v17
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; VI-NEXT: v_add_f16_sdwa v10, v16, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
-; VI-NEXT: v_or_b32_e32 v0, v18, v0
-; VI-NEXT: v_or_b32_e32 v8, v17, v4
-; VI-NEXT: v_or_b32_e32 v7, v16, v3
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v19
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v18
+; VI-NEXT: v_lshl_or_b32 v8, v14, 16, v17
+; VI-NEXT: v_lshl_or_b32 v7, v10, 16, v16
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[7:8]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v8
@@ -22621,23 +22553,19 @@ define inreg <16 x i8> @bitcast_v8f16_to_v16i8_scalar(<8 x half> inreg %a, i32 i
; VI-NEXT: v_mov_b32_e32 v1, 0x200
; VI-NEXT: v_add_f16_e32 v6, s4, v1
; VI-NEXT: s_lshr_b32 s4, s16, 16
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; VI-NEXT: v_add_f16_e32 v17, s17, v1
; VI-NEXT: v_add_f16_e32 v2, s4, v1
; VI-NEXT: s_lshr_b32 s4, s19, 16
-; VI-NEXT: v_or_b32_e32 v19, v17, v0
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; VI-NEXT: v_add_f16_e32 v0, s16, v1
; VI-NEXT: v_add_f16_e32 v14, s4, v1
; VI-NEXT: s_lshr_b32 s4, s18, 16
-; VI-NEXT: v_or_b32_e32 v18, v0, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
+; VI-NEXT: v_add_f16_e32 v17, s17, v1
+; VI-NEXT: v_add_f16_e32 v0, s16, v1
; VI-NEXT: v_add_f16_e32 v16, s19, v1
; VI-NEXT: v_add_f16_e32 v10, s4, v1
-; VI-NEXT: v_or_b32_e32 v21, v16, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; VI-NEXT: v_add_f16_e32 v8, s18, v1
-; VI-NEXT: v_or_b32_e32 v20, v8, v3
+; VI-NEXT: v_lshl_or_b32 v19, v6, 16, v17
+; VI-NEXT: v_lshl_or_b32 v18, v2, 16, v0
+; VI-NEXT: v_lshl_or_b32 v21, v14, 16, v16
+; VI-NEXT: v_lshl_or_b32 v20, v10, 16, v8
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[20:21]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[18:19]
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v21
@@ -23011,22 +22939,18 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB106_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v17, v20, s6
; VI-NEXT: v_perm_b32 v0, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v17, v20, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -23540,31 +23464,27 @@ define inreg <8 x half> @bitcast_v16i8_to_v8f16_scalar(<16 x i8> inreg %a, i32 i
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB107_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v3
; VI-NEXT: v_perm_b32 v0, s16, v0, v3
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v3
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v3
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v3
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v2, v2, v4
+; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v3, v4, v3
+; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; VI-NEXT: s_cbranch_execnz .LBB107_3
; VI-NEXT: .LBB107_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -23623,31 +23543,27 @@ define inreg <8 x half> @bitcast_v16i8_to_v8f16_scalar(<16 x i8> inreg %a, i32 i
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB107_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB107_3
; GFX9-NEXT: .LBB107_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -25316,22 +25232,18 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB110_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v17, v20, s6
; VI-NEXT: v_perm_b32 v0, v19, v18, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v17, v20, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -25841,31 +25753,27 @@ define inreg <8 x bfloat> @bitcast_v16i8_to_v8bf16_scalar(<16 x i8> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB111_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v3
; VI-NEXT: v_perm_b32 v0, s16, v0, v3
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v3
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v3
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v3
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v2, v2, v4
+; VI-NEXT: v_perm_b32 v4, s26, v4, v3
+; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v3, v4, v3
+; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; VI-NEXT: s_cbranch_execnz .LBB111_3
; VI-NEXT: .LBB111_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -25924,31 +25832,27 @@ define inreg <8 x bfloat> @bitcast_v16i8_to_v8bf16_scalar(<16 x i8> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB111_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB111_3
; GFX9-NEXT: .LBB111_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index 224b73353c3bc..cfa0d58088341 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -6267,39 +6267,31 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB26_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v36, v35, s6
; VI-NEXT: v_perm_b32 v0, v38, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v32, v31, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v36, v35, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v34, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v32, v31, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
@@ -6850,62 +6842,61 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
@@ -7202,55 +7193,47 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s47, v0
; VI-NEXT: s_cbranch_scc0 .LBB27_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v7
; VI-NEXT: v_perm_b32 v0, s16, v0, v7
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v7
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v7
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v7
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s47, v4, v7
+; VI-NEXT: v_mov_b32_e32 v4, s46
; VI-NEXT: v_perm_b32 v3, s28, v3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s42
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s47, v4, v7
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s44
-; VI-NEXT: v_perm_b32 v5, s43, v5, v7
+; VI-NEXT: v_mov_b32_e32 v5, s42
; VI-NEXT: v_perm_b32 v4, s45, v4, v7
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s14
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s43, v5, v7
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s40
-; VI-NEXT: v_perm_b32 v6, s15, v6, v7
+; VI-NEXT: v_mov_b32_e32 v6, s14
; VI-NEXT: v_perm_b32 v5, s41, v5, v7
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v8, s10
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s15, v6, v7
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s12
-; VI-NEXT: v_perm_b32 v8, s11, v8, v7
+; VI-NEXT: v_mov_b32_e32 v8, s10
; VI-NEXT: v_perm_b32 v6, s13, v6, v7
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v6, v6, v8
+; VI-NEXT: v_perm_b32 v8, s11, v8, v7
+; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s8
; VI-NEXT: v_mov_b32_e32 v9, s6
; VI-NEXT: v_perm_b32 v8, s9, v8, v7
; VI-NEXT: v_perm_b32 v7, s7, v9, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v7, v8, v7
+; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; VI-NEXT: s_cbranch_execnz .LBB27_3
; VI-NEXT: .LBB27_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -7365,55 +7348,47 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_mov_b32_e32 v4, s46
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s44
-; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_mov_b32_e32 v5, s42
; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v6, s14
; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s12
-; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_mov_b32_e32 v8, s10
; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -7519,33 +7494,31 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB27_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
@@ -7556,43 +7529,40 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-NEXT: .LBB27_2: ; %cmp.true
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-NEXT: s_add_i32 s18, s18, 3
+; GFX11-NEXT: s_add_i32 s22, s22, 3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: s_add_i32 s24, s24, 3
+; GFX11-NEXT: s_add_i32 s26, s26, 3
+; GFX11-NEXT: s_add_i32 s28, s28, 3
+; GFX11-NEXT: s_add_i32 s41, s41, 3
+; GFX11-NEXT: s_add_i32 s15, s15, 3
+; GFX11-NEXT: s_add_i32 s13, s13, 3
; GFX11-NEXT: s_add_i32 s11, s11, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
@@ -13535,39 +13505,31 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB50_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v36, v35, s6
; VI-NEXT: v_perm_b32 v0, v38, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v32, v31, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v36, v35, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v34, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v32, v31, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
@@ -14118,62 +14080,61 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
@@ -14470,55 +14431,47 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s47, v0
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v7
; VI-NEXT: v_perm_b32 v0, s16, v0, v7
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v7
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v7
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v7
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s47, v4, v7
+; VI-NEXT: v_mov_b32_e32 v4, s46
; VI-NEXT: v_perm_b32 v3, s28, v3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s42
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s47, v4, v7
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s44
-; VI-NEXT: v_perm_b32 v5, s43, v5, v7
+; VI-NEXT: v_mov_b32_e32 v5, s42
; VI-NEXT: v_perm_b32 v4, s45, v4, v7
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s14
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s43, v5, v7
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s40
-; VI-NEXT: v_perm_b32 v6, s15, v6, v7
+; VI-NEXT: v_mov_b32_e32 v6, s14
; VI-NEXT: v_perm_b32 v5, s41, v5, v7
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v8, s10
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s15, v6, v7
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s12
-; VI-NEXT: v_perm_b32 v8, s11, v8, v7
+; VI-NEXT: v_mov_b32_e32 v8, s10
; VI-NEXT: v_perm_b32 v6, s13, v6, v7
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v6, v6, v8
+; VI-NEXT: v_perm_b32 v8, s11, v8, v7
+; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s8
; VI-NEXT: v_mov_b32_e32 v9, s6
; VI-NEXT: v_perm_b32 v8, s9, v8, v7
; VI-NEXT: v_perm_b32 v7, s7, v9, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v7, v8, v7
+; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -14633,55 +14586,47 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_mov_b32_e32 v4, s46
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s44
-; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_mov_b32_e32 v5, s42
; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v6, s14
; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s12
-; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_mov_b32_e32 v8, s10
; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -14787,33 +14732,31 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB51_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
@@ -14824,43 +14767,40 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-NEXT: .LBB51_2: ; %cmp.true
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-NEXT: s_add_i32 s18, s18, 3
+; GFX11-NEXT: s_add_i32 s22, s22, 3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: s_add_i32 s24, s24, 3
+; GFX11-NEXT: s_add_i32 s26, s26, 3
+; GFX11-NEXT: s_add_i32 s28, s28, 3
+; GFX11-NEXT: s_add_i32 s41, s41, 3
+; GFX11-NEXT: s_add_i32 s15, s15, 3
+; GFX11-NEXT: s_add_i32 s13, s13, 3
; GFX11-NEXT: s_add_i32 s11, s11, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
@@ -20264,39 +20204,31 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB70_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v36, v35, s6
; VI-NEXT: v_perm_b32 v0, v38, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v32, v31, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v36, v35, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v34, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v32, v31, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
@@ -20847,62 +20779,61 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
@@ -21199,55 +21130,47 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s47, v0
; VI-NEXT: s_cbranch_scc0 .LBB71_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v7
; VI-NEXT: v_perm_b32 v0, s16, v0, v7
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v7
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v7
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v7
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s47, v4, v7
+; VI-NEXT: v_mov_b32_e32 v4, s46
; VI-NEXT: v_perm_b32 v3, s28, v3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s42
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s47, v4, v7
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s44
-; VI-NEXT: v_perm_b32 v5, s43, v5, v7
+; VI-NEXT: v_mov_b32_e32 v5, s42
; VI-NEXT: v_perm_b32 v4, s45, v4, v7
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s14
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s43, v5, v7
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s40
-; VI-NEXT: v_perm_b32 v6, s15, v6, v7
+; VI-NEXT: v_mov_b32_e32 v6, s14
; VI-NEXT: v_perm_b32 v5, s41, v5, v7
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v8, s10
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s15, v6, v7
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s12
-; VI-NEXT: v_perm_b32 v8, s11, v8, v7
+; VI-NEXT: v_mov_b32_e32 v8, s10
; VI-NEXT: v_perm_b32 v6, s13, v6, v7
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v6, v6, v8
+; VI-NEXT: v_perm_b32 v8, s11, v8, v7
+; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s8
; VI-NEXT: v_mov_b32_e32 v9, s6
; VI-NEXT: v_perm_b32 v8, s9, v8, v7
; VI-NEXT: v_perm_b32 v7, s7, v9, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v7, v8, v7
+; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; VI-NEXT: s_cbranch_execnz .LBB71_3
; VI-NEXT: .LBB71_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -21362,55 +21285,47 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_mov_b32_e32 v4, s46
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s44
-; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_mov_b32_e32 v5, s42
; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v6, s14
; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s12
-; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_mov_b32_e32 v8, s10
; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -21516,33 +21431,31 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB71_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
@@ -21553,43 +21466,40 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-NEXT: .LBB71_2: ; %cmp.true
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-NEXT: s_add_i32 s18, s18, 3
+; GFX11-NEXT: s_add_i32 s22, s22, 3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: s_add_i32 s24, s24, 3
+; GFX11-NEXT: s_add_i32 s26, s26, 3
+; GFX11-NEXT: s_add_i32 s28, s28, 3
+; GFX11-NEXT: s_add_i32 s41, s41, 3
+; GFX11-NEXT: s_add_i32 s15, s15, 3
+; GFX11-NEXT: s_add_i32 s13, s13, 3
; GFX11-NEXT: s_add_i32 s11, s11, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
@@ -26526,39 +26436,31 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB86_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v36, v35, s6
; VI-NEXT: v_perm_b32 v0, v38, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v32, v31, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v36, v35, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v34, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v32, v31, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
@@ -27109,62 +27011,61 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
@@ -27461,55 +27362,47 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s47, v0
; VI-NEXT: s_cbranch_scc0 .LBB87_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v7
; VI-NEXT: v_perm_b32 v0, s16, v0, v7
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v7
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v7
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v7
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s47, v4, v7
+; VI-NEXT: v_mov_b32_e32 v4, s46
; VI-NEXT: v_perm_b32 v3, s28, v3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s42
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s47, v4, v7
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s44
-; VI-NEXT: v_perm_b32 v5, s43, v5, v7
+; VI-NEXT: v_mov_b32_e32 v5, s42
; VI-NEXT: v_perm_b32 v4, s45, v4, v7
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s14
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s43, v5, v7
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s40
-; VI-NEXT: v_perm_b32 v6, s15, v6, v7
+; VI-NEXT: v_mov_b32_e32 v6, s14
; VI-NEXT: v_perm_b32 v5, s41, v5, v7
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v8, s10
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s15, v6, v7
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s12
-; VI-NEXT: v_perm_b32 v8, s11, v8, v7
+; VI-NEXT: v_mov_b32_e32 v8, s10
; VI-NEXT: v_perm_b32 v6, s13, v6, v7
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v6, v6, v8
+; VI-NEXT: v_perm_b32 v8, s11, v8, v7
+; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s8
; VI-NEXT: v_mov_b32_e32 v9, s6
; VI-NEXT: v_perm_b32 v8, s9, v8, v7
; VI-NEXT: v_perm_b32 v7, s7, v9, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v7, v8, v7
+; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; VI-NEXT: s_cbranch_execnz .LBB87_3
; VI-NEXT: .LBB87_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -27624,55 +27517,47 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_mov_b32_e32 v4, s46
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s44
-; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_mov_b32_e32 v5, s42
; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v6, s14
; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s12
-; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_mov_b32_e32 v8, s10
; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -27778,33 +27663,31 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB87_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
@@ -27815,43 +27698,40 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-NEXT: .LBB87_2: ; %cmp.true
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-NEXT: s_add_i32 s18, s18, 3
+; GFX11-NEXT: s_add_i32 s22, s22, 3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: s_add_i32 s24, s24, 3
+; GFX11-NEXT: s_add_i32 s26, s26, 3
+; GFX11-NEXT: s_add_i32 s28, s28, 3
+; GFX11-NEXT: s_add_i32 s41, s41, 3
+; GFX11-NEXT: s_add_i32 s15, s15, 3
+; GFX11-NEXT: s_add_i32 s13, s13, 3
; GFX11-NEXT: s_add_i32 s11, s11, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
@@ -31309,38 +31189,30 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB96_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v9, 3
-; VI-NEXT: v_add_u16_sdwa v36, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v32, v0, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v14, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v10, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v22, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v18, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v30, v7, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v26, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v48, 3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; VI-NEXT: v_add_u16_sdwa v36, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v50, 3, v0
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v32
+; VI-NEXT: v_add_u16_sdwa v32, v0, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v35, 3, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
+; VI-NEXT: v_add_u16_sdwa v14, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v8, 3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
+; VI-NEXT: v_add_u16_sdwa v10, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v49, 3, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v22
+; VI-NEXT: v_add_u16_sdwa v22, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v16, 3, v4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v18
+; VI-NEXT: v_add_u16_sdwa v18, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v51, 3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
+; VI-NEXT: v_add_u16_sdwa v30, v7, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v24, 3, v6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v26
-; VI-NEXT: v_or_b32_e32 v1, v48, v1
-; VI-NEXT: v_or_b32_e32 v0, v50, v0
-; VI-NEXT: v_or_b32_e32 v3, v35, v3
-; VI-NEXT: v_or_b32_e32 v2, v8, v2
-; VI-NEXT: v_or_b32_e32 v5, v49, v5
-; VI-NEXT: v_or_b32_e32 v4, v16, v4
-; VI-NEXT: v_or_b32_e32 v7, v51, v7
-; VI-NEXT: v_or_b32_e32 v6, v24, v6
+; VI-NEXT: v_add_u16_sdwa v26, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v1, v36, 16, v48
+; VI-NEXT: v_lshl_or_b32 v0, v32, 16, v50
+; VI-NEXT: v_lshl_or_b32 v3, v14, 16, v35
+; VI-NEXT: v_lshl_or_b32 v2, v10, 16, v8
+; VI-NEXT: v_lshl_or_b32 v5, v22, 16, v49
+; VI-NEXT: v_lshl_or_b32 v4, v18, 16, v16
+; VI-NEXT: v_lshl_or_b32 v7, v30, 16, v51
+; VI-NEXT: v_lshl_or_b32 v6, v26, 16, v24
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[4:5]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3]
@@ -32620,39 +32492,31 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB98_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v34, v35, s6
; VI-NEXT: v_perm_b32 v0, v32, v38, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v31, v33, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v34, v35, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v36, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v31, v33, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr34
@@ -33614,55 +33478,47 @@ define inreg <16 x i16> @bitcast_v32i8_to_v16i16_scalar(<32 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s10, v0
; VI-NEXT: s_cbranch_scc0 .LBB99_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v7
; VI-NEXT: v_perm_b32 v0, s16, v0, v7
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v7
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v7
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v7
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s10, v4, v7
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_perm_b32 v3, s28, v3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s8
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s10, v4, v7
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s7
-; VI-NEXT: v_perm_b32 v5, s12, v5, v7
+; VI-NEXT: v_mov_b32_e32 v5, s8
; VI-NEXT: v_perm_b32 v4, s9, v4, v7
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s13
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s12, v5, v7
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s11
-; VI-NEXT: v_perm_b32 v6, s40, v6, v7
+; VI-NEXT: v_mov_b32_e32 v6, s13
; VI-NEXT: v_perm_b32 v5, s14, v5, v7
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s40, v6, v7
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s15
-; VI-NEXT: v_perm_b32 v8, s44, v8, v7
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v6, s42, v6, v7
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v6, v6, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v7
+; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_mov_b32_e32 v9, s46
; VI-NEXT: v_perm_b32 v8, s45, v8, v7
; VI-NEXT: v_perm_b32 v7, s47, v9, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v7, v8, v7
+; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; VI-NEXT: s_cbranch_execnz .LBB99_3
; VI-NEXT: .LBB99_2: ; %cmp.true
; VI-NEXT: s_add_i32 s47, s47, 3
@@ -36734,38 +36590,30 @@ define <32 x i8> @bitcast_v16f16_to_v32i8(<16 x half> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB104_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v5, 0x200
-; VI-NEXT: v_add_f16_sdwa v14, v33, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_sdwa v36, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v14
+; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
+; VI-NEXT: v_add_f16_sdwa v2, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
+; VI-NEXT: v_add_f16_sdwa v14, v33, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v33, 0x200, v33
; VI-NEXT: v_add_f16_sdwa v10, v32, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v36
-; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
-; VI-NEXT: v_or_b32_e32 v12, v33, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; VI-NEXT: v_add_f16_e32 v32, 0x200, v32
; VI-NEXT: v_add_f16_sdwa v22, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v4, v1, v2
-; VI-NEXT: v_add_f16_sdwa v2, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v11, v32, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
; VI-NEXT: v_add_f16_e32 v35, 0x200, v35
; VI-NEXT: v_add_f16_sdwa v18, v34, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_sdwa v30, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_sdwa v26, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
-; VI-NEXT: v_or_b32_e32 v9, v35, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v18
; VI-NEXT: v_add_f16_e32 v34, 0x200, v34
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v30
+; VI-NEXT: v_add_f16_sdwa v30, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
+; VI-NEXT: v_add_f16_sdwa v26, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
-; VI-NEXT: v_or_b32_e32 v3, v0, v3
-; VI-NEXT: v_or_b32_e32 v8, v34, v8
-; VI-NEXT: v_or_b32_e32 v16, v7, v13
-; VI-NEXT: v_or_b32_e32 v15, v6, v5
+; VI-NEXT: v_lshl_or_b32 v4, v36, 16, v1
+; VI-NEXT: v_lshl_or_b32 v3, v2, 16, v0
+; VI-NEXT: v_lshl_or_b32 v12, v14, 16, v33
+; VI-NEXT: v_lshl_or_b32 v11, v10, 16, v32
+; VI-NEXT: v_lshl_or_b32 v9, v22, 16, v35
+; VI-NEXT: v_lshl_or_b32 v8, v18, 16, v34
+; VI-NEXT: v_lshl_or_b32 v16, v30, 16, v7
+; VI-NEXT: v_lshl_or_b32 v15, v26, 16, v6
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[15:16]
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[8:9]
@@ -37387,39 +37235,31 @@ define inreg <32 x i8> @bitcast_v16f16_to_v32i8_scalar(<16 x half> inreg %a, i32
; VI-NEXT: s_lshr_b32 s4, s19, 16
; VI-NEXT: v_add_f16_e32 v14, s4, v1
; VI-NEXT: s_lshr_b32 s4, s18, 16
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v14
-; VI-NEXT: v_add_f16_e32 v34, s19, v1
; VI-NEXT: v_add_f16_e32 v10, s4, v1
; VI-NEXT: s_lshr_b32 s4, s21, 16
-; VI-NEXT: v_or_b32_e32 v12, v34, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v10
-; VI-NEXT: v_add_f16_e32 v8, s18, v1
; VI-NEXT: v_add_f16_e32 v22, s4, v1
; VI-NEXT: s_lshr_b32 s4, s20, 16
-; VI-NEXT: v_or_b32_e32 v11, v8, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v22
-; VI-NEXT: v_add_f16_e32 v33, s21, v1
; VI-NEXT: v_add_f16_e32 v18, s4, v1
; VI-NEXT: s_lshr_b32 s4, s23, 16
-; VI-NEXT: v_or_b32_e32 v20, v33, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v18
-; VI-NEXT: v_add_f16_e32 v16, s20, v1
; VI-NEXT: v_add_f16_e32 v30, s4, v1
; VI-NEXT: s_lshr_b32 s4, s22, 16
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
; VI-NEXT: v_add_f16_e32 v35, s17, v1
-; VI-NEXT: v_or_b32_e32 v19, v16, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v30
+; VI-NEXT: v_add_f16_e32 v0, s16, v1
+; VI-NEXT: v_add_f16_e32 v34, s19, v1
+; VI-NEXT: v_add_f16_e32 v8, s18, v1
+; VI-NEXT: v_add_f16_e32 v33, s21, v1
+; VI-NEXT: v_add_f16_e32 v16, s20, v1
; VI-NEXT: v_add_f16_e32 v32, s23, v1
; VI-NEXT: v_add_f16_e32 v26, s4, v1
-; VI-NEXT: v_or_b32_e32 v4, v35, v0
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
-; VI-NEXT: v_add_f16_e32 v0, s16, v1
-; VI-NEXT: v_or_b32_e32 v37, v32, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
; VI-NEXT: v_add_f16_e32 v24, s22, v1
-; VI-NEXT: v_or_b32_e32 v3, v0, v3
-; VI-NEXT: v_or_b32_e32 v36, v24, v5
+; VI-NEXT: v_lshl_or_b32 v4, v6, 16, v35
+; VI-NEXT: v_lshl_or_b32 v3, v2, 16, v0
+; VI-NEXT: v_lshl_or_b32 v12, v14, 16, v34
+; VI-NEXT: v_lshl_or_b32 v11, v10, 16, v8
+; VI-NEXT: v_lshl_or_b32 v20, v22, 16, v33
+; VI-NEXT: v_lshl_or_b32 v19, v18, 16, v16
+; VI-NEXT: v_lshl_or_b32 v37, v30, 16, v32
+; VI-NEXT: v_lshl_or_b32 v36, v26, 16, v24
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[36:37]
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v19
@@ -38079,39 +37919,31 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB106_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v34, v35, s6
; VI-NEXT: v_perm_b32 v0, v32, v38, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v31, v33, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v34, v35, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v36, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v31, v33, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr34
@@ -39073,55 +38905,47 @@ define inreg <16 x half> @bitcast_v32i8_to_v16f16_scalar(<32 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s10, v0
; VI-NEXT: s_cbranch_scc0 .LBB107_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v7
; VI-NEXT: v_perm_b32 v0, s16, v0, v7
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v7
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v7
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v7
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s10, v4, v7
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_perm_b32 v3, s28, v3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s8
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s10, v4, v7
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s7
-; VI-NEXT: v_perm_b32 v5, s12, v5, v7
+; VI-NEXT: v_mov_b32_e32 v5, s8
; VI-NEXT: v_perm_b32 v4, s9, v4, v7
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s13
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s12, v5, v7
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s11
-; VI-NEXT: v_perm_b32 v6, s40, v6, v7
+; VI-NEXT: v_mov_b32_e32 v6, s13
; VI-NEXT: v_perm_b32 v5, s14, v5, v7
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s40, v6, v7
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s15
-; VI-NEXT: v_perm_b32 v8, s44, v8, v7
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v6, s42, v6, v7
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v6, v6, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v7
+; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_mov_b32_e32 v9, s46
; VI-NEXT: v_perm_b32 v8, s45, v8, v7
; VI-NEXT: v_perm_b32 v7, s47, v9, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v7, v8, v7
+; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; VI-NEXT: s_cbranch_execnz .LBB107_3
; VI-NEXT: .LBB107_2: ; %cmp.true
; VI-NEXT: s_add_i32 s47, s47, 3
@@ -42467,39 +42291,31 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB110_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v34, v35, s6
; VI-NEXT: v_perm_b32 v0, v32, v38, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v31, v33, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v34, v35, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v36, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v31, v33, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr34
@@ -43453,55 +43269,47 @@ define inreg <16 x bfloat> @bitcast_v32i8_to_v16bf16_scalar(<32 x i8> inreg %a,
; VI-NEXT: v_readfirstlane_b32 s10, v0
; VI-NEXT: s_cbranch_scc0 .LBB111_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v7
; VI-NEXT: v_perm_b32 v0, s16, v0, v7
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v7
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v7
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v7
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v7
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v7
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s10, v4, v7
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_perm_b32 v3, s28, v3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s8
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s10, v4, v7
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s7
-; VI-NEXT: v_perm_b32 v5, s12, v5, v7
+; VI-NEXT: v_mov_b32_e32 v5, s8
; VI-NEXT: v_perm_b32 v4, s9, v4, v7
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s13
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s12, v5, v7
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s11
-; VI-NEXT: v_perm_b32 v6, s40, v6, v7
+; VI-NEXT: v_mov_b32_e32 v6, s13
; VI-NEXT: v_perm_b32 v5, s14, v5, v7
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s40, v6, v7
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s15
-; VI-NEXT: v_perm_b32 v8, s44, v8, v7
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v6, s42, v6, v7
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v6, v6, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v7
+; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_mov_b32_e32 v9, s46
; VI-NEXT: v_perm_b32 v8, s45, v8, v7
; VI-NEXT: v_perm_b32 v7, s47, v9, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v7, v8, v7
+; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; VI-NEXT: s_cbranch_execnz .LBB111_3
; VI-NEXT: .LBB111_2: ; %cmp.true
; VI-NEXT: s_add_i32 s47, s47, 3
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index aba9755a4f357..576ce576c73e1 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -2734,61 +2734,51 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v48, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v1, v1, v15
+; VI-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v39, s4
; VI-NEXT: v_perm_b32 v2, v38, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v35, v14, s4
; VI-NEXT: v_perm_b32 v1, v3, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v35, v14, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v33, v32, s4
; VI-NEXT: v_perm_b32 v1, v4, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v33, v32, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v30, v13, s4
; VI-NEXT: v_perm_b32 v1, v5, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v30, v13, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v28, v27, s4
; VI-NEXT: v_perm_b32 v1, v6, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v28, v27, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v25, v12, s4
; VI-NEXT: v_perm_b32 v1, v7, v26, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v25, v12, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v23, v22, s4
; VI-NEXT: v_perm_b32 v1, v8, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v23, v22, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v20, v11, s4
; VI-NEXT: v_perm_b32 v1, v9, v21, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v20, v11, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v18, v17, s4
; VI-NEXT: v_perm_b32 v1, v10, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v18, v17, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -3572,84 +3562,74 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; VI-NEXT: s_lshr_b32 s75, s16, 16
; VI-NEXT: s_lshr_b32 s76, s16, 8
; VI-NEXT: .LBB13_3: ; %end
+; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s12
-; VI-NEXT: v_mov_b32_e32 v1, s76
-; VI-NEXT: v_perm_b32 v3, s75, v3, v2
; VI-NEXT: v_perm_b32 v1, s16, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
-; VI-NEXT: v_mov_b32_e32 v3, s72
+; VI-NEXT: v_perm_b32 v3, s75, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s74
-; VI-NEXT: v_perm_b32 v3, s73, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: v_perm_b32 v1, s17, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s73, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_mov_b32_e32 v1, s63
-; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s59
; VI-NEXT: v_mov_b32_e32 v1, s61
-; VI-NEXT: v_perm_b32 v3, s60, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s59
; VI-NEXT: v_perm_b32 v1, s19, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s60, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_mov_b32_e32 v1, s58
-; VI-NEXT: v_perm_b32 v3, s57, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s57, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s46
; VI-NEXT: v_mov_b32_e32 v1, s56
-; VI-NEXT: v_perm_b32 v3, s47, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s46
; VI-NEXT: v_perm_b32 v1, s21, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s47, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_mov_b32_e32 v1, s45
-; VI-NEXT: v_perm_b32 v3, s44, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_perm_b32 v1, s22, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s44, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s41
; VI-NEXT: v_mov_b32_e32 v1, s43
-; VI-NEXT: v_perm_b32 v3, s42, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s41
; VI-NEXT: v_perm_b32 v1, s23, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s42, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v1, s40
-; VI-NEXT: v_perm_b32 v3, s29, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_perm_b32 v1, s24, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s29, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s28
; VI-NEXT: v_mov_b32_e32 v3, s26
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
; VI-NEXT: v_perm_b32 v2, s27, v3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -3766,76 +3746,66 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; GFX9-NEXT: s_lshr_b32 s75, s16, 16
; GFX9-NEXT: s_lshr_b32 s76, s16, 8
; GFX9-NEXT: .LBB13_3: ; %end
+; GFX9-NEXT: v_mov_b32_e32 v1, s76
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s12
-; GFX9-NEXT: v_mov_b32_e32 v1, s76
-; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s72
+; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s74
-; GFX9-NEXT: v_perm_b32 v3, s73, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
+; GFX9-NEXT: v_perm_b32 v3, s73, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s59
+; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s61
-; GFX9-NEXT: v_perm_b32 v3, s60, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s59
; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_perm_b32 v3, s60, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s58
-; GFX9-NEXT: v_perm_b32 v3, s57, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s46
+; GFX9-NEXT: v_perm_b32 v3, s57, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s56
-; GFX9-NEXT: v_perm_b32 v3, s47, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
+; GFX9-NEXT: v_perm_b32 v3, s47, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s45
-; GFX9-NEXT: v_perm_b32 v3, s44, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s41
+; GFX9-NEXT: v_perm_b32 v3, s44, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s43
-; GFX9-NEXT: v_perm_b32 v3, s42, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s41
; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s4
+; GFX9-NEXT: v_perm_b32 v3, s42, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s40
-; GFX9-NEXT: v_perm_b32 v3, s29, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s29, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s28
; GFX9-NEXT: v_mov_b32_e32 v3, s26
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s27, v3, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -3954,47 +3924,37 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; GFX11-NEXT: s_lshr_b32 s62, s0, 8
; GFX11-NEXT: .LBB13_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v6, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v2, s61, s12, v6
-; GFX11-NEXT: v_perm_b32 v4, s59, s58, v6
-; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
-; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s0, s62, v6
+; GFX11-NEXT: v_perm_b32 v2, s61, s12, v6
; GFX11-NEXT: v_perm_b32 v3, s1, s60, v6
+; GFX11-NEXT: v_perm_b32 v4, s59, s58, v6
; GFX11-NEXT: v_perm_b32 v5, s2, s57, v6
+; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
; GFX11-NEXT: v_perm_b32 v8, s3, s47, v6
+; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
; GFX11-NEXT: v_perm_b32 v10, s16, s44, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v12, s24, s4, v6
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v5, v7
+; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v7, 16, v5
; GFX11-NEXT: v_perm_b32 v7, s42, s41, v6
-; GFX11-NEXT: v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v11
+; GFX11-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v5, v11, 16, v10
; GFX11-NEXT: v_perm_b32 v8, s29, s6, v6
-; GFX11-NEXT: v_perm_b32 v11, s27, s26, v6
-; GFX11-NEXT: v_perm_b32 v14, s22, s14, v6
; GFX11-NEXT: v_perm_b32 v9, s17, s40, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v10, s18, s28, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_perm_b32 v11, s27, s26, v6
; GFX11-NEXT: v_perm_b32 v13, s19, s25, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: v_perm_b32 v12, s24, s4, v6
+; GFX11-NEXT: v_perm_b32 v14, s22, s14, v6
; GFX11-NEXT: v_perm_b32 v15, s20, s23, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_perm_b32 v16, s21, s15, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v10, v8
-; GFX11-NEXT: v_or_b32_e32 v8, v13, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v12
-; GFX11-NEXT: v_or_b32_e32 v10, v16, v14
+; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v9, v12, 16, v15
+; GFX11-NEXT: v_lshl_or_b32 v10, v14, 16, v16
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -4377,48 +4337,37 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB14_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v38, v37, s6
; VI-NEXT: v_perm_b32 v0, v48, v39, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v34, v33, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v38, v37, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v36, v35, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v34, v33, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v32, v31, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v9, v54, v53, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, v30, v55, s6
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_perm_b32 v10, v50, v49, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v54, v53, s6
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v52, v51, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, v50, v49, s6
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
@@ -5161,12 +5110,11 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
@@ -5552,67 +5500,57 @@ define inreg <10 x i32> @bitcast_v40i8_to_v10i32_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s63, v0
; VI-NEXT: s_cbranch_scc0 .LBB15_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v9
; VI-NEXT: v_perm_b32 v0, s16, v0, v9
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v9
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v9
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v9
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s62
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s63, v4, v9
+; VI-NEXT: v_mov_b32_e32 v4, s62
; VI-NEXT: v_perm_b32 v3, s28, v3, v9
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s63, v4, v9
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s60
-; VI-NEXT: v_perm_b32 v5, s59, v5, v9
+; VI-NEXT: v_mov_b32_e32 v5, s58
; VI-NEXT: v_perm_b32 v4, s61, v4, v9
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s59, v5, v9
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s56
-; VI-NEXT: v_perm_b32 v6, s47, v6, v9
+; VI-NEXT: v_mov_b32_e32 v6, s46
; VI-NEXT: v_perm_b32 v5, s57, v5, v9
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s42
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s47, v6, v9
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s44
-; VI-NEXT: v_perm_b32 v7, s43, v7, v9
+; VI-NEXT: v_mov_b32_e32 v7, s42
; VI-NEXT: v_perm_b32 v6, s45, v6, v9
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s14
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s43, v7, v9
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s40
-; VI-NEXT: v_perm_b32 v8, s15, v8, v9
+; VI-NEXT: v_mov_b32_e32 v8, s14
; VI-NEXT: v_perm_b32 v7, s41, v7, v9
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s15, v8, v9
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s12
-; VI-NEXT: v_perm_b32 v10, s11, v10, v9
+; VI-NEXT: v_mov_b32_e32 v10, s10
; VI-NEXT: v_perm_b32 v8, s13, v8, v9
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v8, v8, v10
+; VI-NEXT: v_perm_b32 v10, s11, v10, v9
+; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s8
; VI-NEXT: v_mov_b32_e32 v11, s6
; VI-NEXT: v_perm_b32 v10, s9, v10, v9
; VI-NEXT: v_perm_b32 v9, s7, v11, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; VI-NEXT: s_cbranch_execnz .LBB15_3
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -5755,67 +5693,57 @@ define inreg <10 x i32> @bitcast_v40i8_to_v10i32_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB15_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_mov_b32_e32 v4, s62
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s60
-; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_mov_b32_e32 v5, s58
; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s56
-; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_mov_b32_e32 v6, s46
; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s44
-; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_mov_b32_e32 v7, s42
; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s40
-; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v8, s14
; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s12
-; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_mov_b32_e32 v10, s10
; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; GFX9-NEXT: s_cbranch_execnz .LBB15_3
; GFX9-NEXT: .LBB15_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -5947,47 +5875,37 @@ define inreg <10 x i32> @bitcast_v40i8_to_v10i32_scalar(<40 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB15_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v14
+; GFX11-NEXT: v_lshl_or_b32 v9, v13, 16, v15
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB15_3
; GFX11-NEXT: .LBB15_2: ; %cmp.true
@@ -9369,61 +9287,51 @@ define <40 x i8> @bitcast_v10f32_to_v40i8(<10 x float> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v48, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v1, v1, v15
+; VI-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v39, s4
; VI-NEXT: v_perm_b32 v2, v38, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v35, v14, s4
; VI-NEXT: v_perm_b32 v1, v3, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v35, v14, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v33, v32, s4
; VI-NEXT: v_perm_b32 v1, v4, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v33, v32, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v30, v13, s4
; VI-NEXT: v_perm_b32 v1, v5, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v30, v13, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v28, v27, s4
; VI-NEXT: v_perm_b32 v1, v6, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v28, v27, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v25, v12, s4
; VI-NEXT: v_perm_b32 v1, v7, v26, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v25, v12, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v23, v22, s4
; VI-NEXT: v_perm_b32 v1, v8, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v23, v22, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v20, v11, s4
; VI-NEXT: v_perm_b32 v1, v9, v21, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v20, v11, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v18, v17, s4
; VI-NEXT: v_perm_b32 v1, v10, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v18, v17, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -10304,61 +10212,51 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v48, v15, s4
; VI-NEXT: v_perm_b32 v9, v9, v39, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v9, v9, v15
+; VI-NEXT: v_lshl_or_b32 v9, v15, 16, v9
; VI-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v9, v10, v38, s4
; VI-NEXT: v_perm_b32 v10, v36, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_add_u32_e32 v10, vcc, 4, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v9, v34, v14, s4
; VI-NEXT: v_perm_b32 v7, v7, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v7, v7, v9
+; VI-NEXT: v_perm_b32 v9, v34, v14, s4
+; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, 8, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v7, v8, v33, s4
; VI-NEXT: v_perm_b32 v8, v31, v32, s4
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 12, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v7, v29, v13, s4
; VI-NEXT: v_perm_b32 v5, v5, v30, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v5, v5, v7
+; VI-NEXT: v_perm_b32 v7, v29, v13, s4
+; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, 16, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v6, v28, s4
; VI-NEXT: v_perm_b32 v6, v26, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 20, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v5, v24, v12, s4
; VI-NEXT: v_perm_b32 v3, v3, v25, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v3, v3, v5
+; VI-NEXT: v_perm_b32 v5, v24, v12, s4
+; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; VI-NEXT: v_add_u32_e32 v5, vcc, 24, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v3, v4, v23, s4
; VI-NEXT: v_perm_b32 v4, v21, v22, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v3, v19, v11, s4
; VI-NEXT: v_perm_b32 v1, v1, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, v19, v11, s4
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v18, s4
; VI-NEXT: v_perm_b32 v2, v16, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -10520,53 +10418,43 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
+; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v38, s4
; GFX9-NEXT: v_perm_b32 v10, v36, v37, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v33, s4
; GFX9-NEXT: v_perm_b32 v8, v31, v32, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v28, s4
; GFX9-NEXT: v_perm_b32 v6, v26, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v23, s4
; GFX9-NEXT: v_perm_b32 v4, v21, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v18, s4
; GFX9-NEXT: v_perm_b32 v2, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10714,8 +10602,8 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX11-NEXT: v_perm_b32 v14, v34, v14, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v15
; GFX11-NEXT: v_perm_b32 v15, v32, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v36
; GFX11-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v14
@@ -10724,17 +10612,15 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX11-NEXT: v_perm_b32 v5, v5, v29, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-NEXT: v_or_b32_e32 v8, v10, v31
-; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v10, v14, v15
; GFX11-NEXT: v_perm_b32 v14, v22, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v13, v5, v13
; GFX11-NEXT: v_perm_b32 v5, v26, v12, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v6, v6, v25, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v27
; GFX11-NEXT: v_perm_b32 v3, v3, v24, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v20, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-NEXT: v_perm_b32 v1, v1, v17, 0xc0c0004
@@ -10742,8 +10628,8 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX11-NEXT: v_perm_b32 v2, v2, v16, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v15
; GFX11-NEXT: v_or_b32_e32 v9, v35, v9
-; GFX11-NEXT: v_or_b32_e32 v14, v6, v12
-; GFX11-NEXT: v_or_b32_e32 v15, v3, v5
+; GFX11-NEXT: v_lshl_or_b32 v14, v27, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v15, v5, 16, v3
; GFX11-NEXT: v_or_b32_e32 v16, v4, v18
; GFX11-NEXT: v_or_b32_e32 v1, v1, v11
; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
@@ -11097,48 +10983,37 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB34_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v38, v37, s6
; VI-NEXT: v_perm_b32 v0, v48, v39, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v34, v33, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v38, v37, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v36, v35, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v34, v33, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v32, v31, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v12, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v14, v15, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v9, v54, v53, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, v30, v55, s6
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_perm_b32 v10, v50, v49, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v54, v53, s6
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v52, v51, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, v50, v49, s6
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
@@ -11881,12 +11756,11 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
@@ -12272,67 +12146,57 @@ define inreg <10 x float> @bitcast_v40i8_to_v10f32_scalar(<40 x i8> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s63, v0
; VI-NEXT: s_cbranch_scc0 .LBB35_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v9
; VI-NEXT: v_perm_b32 v0, s16, v0, v9
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v9
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v9
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v9
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s62
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s63, v4, v9
+; VI-NEXT: v_mov_b32_e32 v4, s62
; VI-NEXT: v_perm_b32 v3, s28, v3, v9
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s63, v4, v9
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s60
-; VI-NEXT: v_perm_b32 v5, s59, v5, v9
+; VI-NEXT: v_mov_b32_e32 v5, s58
; VI-NEXT: v_perm_b32 v4, s61, v4, v9
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s59, v5, v9
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s56
-; VI-NEXT: v_perm_b32 v6, s47, v6, v9
+; VI-NEXT: v_mov_b32_e32 v6, s46
; VI-NEXT: v_perm_b32 v5, s57, v5, v9
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s42
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s47, v6, v9
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s44
-; VI-NEXT: v_perm_b32 v7, s43, v7, v9
+; VI-NEXT: v_mov_b32_e32 v7, s42
; VI-NEXT: v_perm_b32 v6, s45, v6, v9
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s14
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s43, v7, v9
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s40
-; VI-NEXT: v_perm_b32 v8, s15, v8, v9
+; VI-NEXT: v_mov_b32_e32 v8, s14
; VI-NEXT: v_perm_b32 v7, s41, v7, v9
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s15, v8, v9
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s12
-; VI-NEXT: v_perm_b32 v10, s11, v10, v9
+; VI-NEXT: v_mov_b32_e32 v10, s10
; VI-NEXT: v_perm_b32 v8, s13, v8, v9
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v8, v8, v10
+; VI-NEXT: v_perm_b32 v10, s11, v10, v9
+; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s8
; VI-NEXT: v_mov_b32_e32 v11, s6
; VI-NEXT: v_perm_b32 v10, s9, v10, v9
; VI-NEXT: v_perm_b32 v9, s7, v11, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; VI-NEXT: s_cbranch_execnz .LBB35_3
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -12475,67 +12339,57 @@ define inreg <10 x float> @bitcast_v40i8_to_v10f32_scalar(<40 x i8> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB35_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_mov_b32_e32 v4, s62
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s60
-; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_mov_b32_e32 v5, s58
; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s56
-; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_mov_b32_e32 v6, s46
; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s44
-; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_mov_b32_e32 v7, s42
; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s40
-; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v8, s14
; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s12
-; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_mov_b32_e32 v10, s10
; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; GFX9-NEXT: s_cbranch_execnz .LBB35_3
; GFX9-NEXT: .LBB35_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -12667,47 +12521,37 @@ define inreg <10 x float> @bitcast_v40i8_to_v10f32_scalar(<40 x i8> inreg %a, i3
; GFX11-NEXT: s_cbranch_scc0 .LBB35_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v14
+; GFX11-NEXT: v_lshl_or_b32 v9, v13, 16, v15
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB35_3
; GFX11-NEXT: .LBB35_2: ; %cmp.true
@@ -15525,49 +15369,39 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB48_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v11, 3
-; VI-NEXT: v_add_u16_sdwa v17, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v20, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v18, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v22, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v42, 3, v10
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
+; VI-NEXT: v_add_u16_sdwa v17, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v43, 3, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v20
-; VI-NEXT: v_add_u16_sdwa v19, v6, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v24, v5, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v20, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v54, 3, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v18
+; VI-NEXT: v_add_u16_sdwa v18, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v40, 3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v22
-; VI-NEXT: v_or_b32_e32 v10, v42, v10
-; VI-NEXT: v_or_b32_e32 v9, v43, v9
+; VI-NEXT: v_add_u16_sdwa v22, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v10, v17, 16, v42
+; VI-NEXT: v_lshl_or_b32 v9, v20, 16, v43
; VI-NEXT: v_add_u16_sdwa v23, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v26, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v21, v4, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v25, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v49, 3, v6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
+; VI-NEXT: v_add_u16_sdwa v19, v6, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v51, 3, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v24
-; VI-NEXT: v_or_b32_e32 v8, v54, v8
-; VI-NEXT: v_or_b32_e32 v7, v40, v7
+; VI-NEXT: v_add_u16_sdwa v24, v5, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v8, v18, 16, v54
+; VI-NEXT: v_lshl_or_b32 v7, v22, 16, v40
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT: v_add_u16_e32 v37, 3, v4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
; VI-NEXT: v_add_u16_e32 v38, 3, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v25
-; VI-NEXT: v_or_b32_e32 v6, v49, v6
-; VI-NEXT: v_or_b32_e32 v5, v51, v5
+; VI-NEXT: v_lshl_or_b32 v6, v19, 16, v49
+; VI-NEXT: v_lshl_or_b32 v5, v24, 16, v51
; VI-NEXT: v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT: v_add_u16_e32 v32, 3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
; VI-NEXT: v_add_u16_e32 v33, 3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26
-; VI-NEXT: v_or_b32_e32 v4, v37, v4
-; VI-NEXT: v_or_b32_e32 v3, v38, v3
+; VI-NEXT: v_lshl_or_b32 v4, v21, 16, v37
+; VI-NEXT: v_lshl_or_b32 v3, v25, 16, v38
; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[5:6]
-; VI-NEXT: v_or_b32_e32 v2, v32, v2
-; VI-NEXT: v_or_b32_e32 v1, v33, v1
+; VI-NEXT: v_lshl_or_b32 v2, v23, 16, v32
+; VI-NEXT: v_lshl_or_b32 v1, v26, 16, v33
; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v10
@@ -15588,63 +15422,53 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; VI-NEXT: .LBB48_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v2, v26, v15, s4
; VI-NEXT: v_perm_b32 v1, v33, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
-; VI-NEXT: v_perm_b32 v2, v23, v41, s4
+; VI-NEXT: v_perm_b32 v2, v26, v15, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v32, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v23, v41, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v25, v14, s4
; VI-NEXT: v_perm_b32 v1, v38, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v25, v14, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v21, v52, s4
; VI-NEXT: v_perm_b32 v1, v37, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v21, v52, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v24, v13, s4
; VI-NEXT: v_perm_b32 v1, v51, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v24, v13, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v19, v39, s4
; VI-NEXT: v_perm_b32 v1, v49, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v19, v39, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v22, v12, s4
; VI-NEXT: v_perm_b32 v1, v40, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v22, v12, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v18, v35, s4
; VI-NEXT: v_perm_b32 v1, v54, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v18, v35, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v20, v11, s4
; VI-NEXT: v_perm_b32 v1, v43, v28, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v20, v11, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v17, v30, s4
; VI-NEXT: v_perm_b32 v1, v42, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v17, v30, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -16562,84 +16386,74 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; VI-NEXT: s_lshr_b32 s75, s16, 16
; VI-NEXT: s_lshr_b32 s76, s16, 8
; VI-NEXT: .LBB49_3: ; %end
+; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s12
-; VI-NEXT: v_mov_b32_e32 v1, s76
-; VI-NEXT: v_perm_b32 v3, s75, v3, v2
; VI-NEXT: v_perm_b32 v1, s16, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
-; VI-NEXT: v_mov_b32_e32 v3, s72
+; VI-NEXT: v_perm_b32 v3, s75, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s74
-; VI-NEXT: v_perm_b32 v3, s73, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: v_perm_b32 v1, s17, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s73, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_mov_b32_e32 v1, s63
-; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s59
; VI-NEXT: v_mov_b32_e32 v1, s61
-; VI-NEXT: v_perm_b32 v3, s60, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s59
; VI-NEXT: v_perm_b32 v1, s19, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s60, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_mov_b32_e32 v1, s58
-; VI-NEXT: v_perm_b32 v3, s57, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s57, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s46
; VI-NEXT: v_mov_b32_e32 v1, s56
-; VI-NEXT: v_perm_b32 v3, s47, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s46
; VI-NEXT: v_perm_b32 v1, s21, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s47, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_mov_b32_e32 v1, s45
-; VI-NEXT: v_perm_b32 v3, s44, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_perm_b32 v1, s22, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s44, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s41
; VI-NEXT: v_mov_b32_e32 v1, s43
-; VI-NEXT: v_perm_b32 v3, s42, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s41
; VI-NEXT: v_perm_b32 v1, s23, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s42, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v1, s40
-; VI-NEXT: v_perm_b32 v3, s29, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_perm_b32 v1, s24, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s29, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s28
; VI-NEXT: v_mov_b32_e32 v3, s26
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
; VI-NEXT: v_perm_b32 v2, s27, v3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -16833,53 +16647,43 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
+; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v38, s4
; GFX9-NEXT: v_perm_b32 v10, v36, v37, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v33, s4
; GFX9-NEXT: v_perm_b32 v8, v31, v32, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v28, s4
; GFX9-NEXT: v_perm_b32 v6, v26, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v23, s4
; GFX9-NEXT: v_perm_b32 v4, v21, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v18, s4
; GFX9-NEXT: v_perm_b32 v2, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -17027,8 +16831,8 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v14, v34, v14, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v15
; GFX11-NEXT: v_perm_b32 v15, v32, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v36
; GFX11-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v14
@@ -17037,17 +16841,15 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v5, v5, v29, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-NEXT: v_or_b32_e32 v8, v10, v31
-; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v10, v14, v15
; GFX11-NEXT: v_perm_b32 v14, v22, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v13, v5, v13
; GFX11-NEXT: v_perm_b32 v5, v26, v12, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v6, v6, v25, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v27
; GFX11-NEXT: v_perm_b32 v3, v3, v24, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v20, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-NEXT: v_perm_b32 v1, v1, v17, 0xc0c0004
@@ -17055,8 +16857,8 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v2, v2, v16, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v15
; GFX11-NEXT: v_or_b32_e32 v9, v35, v9
-; GFX11-NEXT: v_or_b32_e32 v14, v6, v12
-; GFX11-NEXT: v_or_b32_e32 v15, v3, v5
+; GFX11-NEXT: v_lshl_or_b32 v14, v27, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v15, v5, 16, v3
; GFX11-NEXT: v_or_b32_e32 v16, v4, v18
; GFX11-NEXT: v_or_b32_e32 v1, v1, v11
; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
@@ -17501,48 +17303,37 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB50_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v37, v36, s6
; VI-NEXT: v_perm_b32 v0, v31, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v49, v48, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v37, v36, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v35, v34, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v53, v52, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v49, v48, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v39, v38, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v32, v54, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v53, v52, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v51, v50, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v32, v54, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v9, v44, v42, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, v30, v55, s6
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_perm_b32 v10, v47, v46, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v44, v42, s6
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, v47, v46, s6
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr37
@@ -18816,67 +18607,57 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s10, v0
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v9
; VI-NEXT: v_perm_b32 v0, s16, v0, v9
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v9
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v9
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v9
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s10, v4, v9
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_perm_b32 v3, s28, v3, v9
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s8
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s10, v4, v9
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s7
-; VI-NEXT: v_perm_b32 v5, s12, v5, v9
+; VI-NEXT: v_mov_b32_e32 v5, s8
; VI-NEXT: v_perm_b32 v4, s9, v4, v9
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s13
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s12, v5, v9
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s11
-; VI-NEXT: v_perm_b32 v6, s40, v6, v9
+; VI-NEXT: v_mov_b32_e32 v6, s13
; VI-NEXT: v_perm_b32 v5, s14, v5, v9
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s41
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s40, v6, v9
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s15
-; VI-NEXT: v_perm_b32 v7, s44, v7, v9
+; VI-NEXT: v_mov_b32_e32 v7, s41
; VI-NEXT: v_perm_b32 v6, s42, v6, v9
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s45
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s44, v7, v9
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s43
-; VI-NEXT: v_perm_b32 v8, s56, v8, v9
+; VI-NEXT: v_mov_b32_e32 v8, s45
; VI-NEXT: v_perm_b32 v7, s46, v7, v9
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v10, s57
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s56, v8, v9
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s47
-; VI-NEXT: v_perm_b32 v10, s60, v10, v9
+; VI-NEXT: v_mov_b32_e32 v10, s57
; VI-NEXT: v_perm_b32 v8, s58, v8, v9
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v8, v8, v10
+; VI-NEXT: v_perm_b32 v10, s60, v10, v9
+; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s59
; VI-NEXT: v_mov_b32_e32 v11, s62
; VI-NEXT: v_perm_b32 v10, s61, v10, v9
; VI-NEXT: v_perm_b32 v9, s63, v11, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s63, s63, 3
@@ -21808,49 +21589,39 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB60_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v11, 0x200
+; VI-NEXT: v_add_f16_sdwa v17, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
+; VI-NEXT: v_add_f16_sdwa v20, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
+; VI-NEXT: v_add_f16_sdwa v18, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
+; VI-NEXT: v_add_f16_sdwa v22, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
+; VI-NEXT: v_lshl_or_b32 v29, v17, 16, v10
+; VI-NEXT: v_lshl_or_b32 v28, v20, 16, v9
; VI-NEXT: v_add_f16_sdwa v23, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v23
-; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: v_add_f16_sdwa v26, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v39, v2, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v26
-; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v21, v4, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v38, v1, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v21
-; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_add_f16_sdwa v25, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v36, v4, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v25
-; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
; VI-NEXT: v_add_f16_sdwa v19, v6, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v35, v3, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v19
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_add_f16_sdwa v24, v5, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v34, v6, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v24
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
-; VI-NEXT: v_add_f16_sdwa v18, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v33, v5, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v18
-; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT: v_add_f16_sdwa v22, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v31, v8, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
-; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
-; VI-NEXT: v_add_f16_sdwa v17, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_sdwa v20, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v30, v7, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v17
-; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v20
-; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
-; VI-NEXT: v_or_b32_e32 v29, v10, v12
-; VI-NEXT: v_or_b32_e32 v28, v9, v11
+; VI-NEXT: v_lshl_or_b32 v31, v18, 16, v8
+; VI-NEXT: v_lshl_or_b32 v30, v22, 16, v7
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[28:29]
+; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
+; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
+; VI-NEXT: v_lshl_or_b32 v34, v19, 16, v6
+; VI-NEXT: v_lshl_or_b32 v33, v24, 16, v5
; VI-NEXT: v_lshrrev_b64 v[12:13], 24, v[30:31]
+; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
+; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
+; VI-NEXT: v_lshl_or_b32 v36, v21, 16, v4
+; VI-NEXT: v_lshl_or_b32 v35, v25, 16, v3
; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[33:34]
+; VI-NEXT: v_lshl_or_b32 v39, v23, 16, v2
+; VI-NEXT: v_lshl_or_b32 v38, v26, 16, v1
; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[35:36]
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[38:39]
; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v29
@@ -21873,61 +21644,51 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v26, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v1, v1, v15
+; VI-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v39, s4
; VI-NEXT: v_perm_b32 v2, v23, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v25, v14, s4
; VI-NEXT: v_perm_b32 v1, v3, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v25, v14, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v21, v38, s4
; VI-NEXT: v_perm_b32 v1, v4, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v21, v38, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v24, v13, s4
; VI-NEXT: v_perm_b32 v1, v5, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v24, v13, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v19, v35, s4
; VI-NEXT: v_perm_b32 v1, v6, v32, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v19, v35, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v22, v12, s4
; VI-NEXT: v_perm_b32 v1, v7, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v22, v12, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v18, v33, s4
; VI-NEXT: v_perm_b32 v1, v8, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v18, v33, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v20, v11, s4
; VI-NEXT: v_perm_b32 v1, v9, v28, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v20, v11, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v17, v30, s4
; VI-NEXT: v_perm_b32 v1, v10, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v17, v30, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -22813,56 +22574,46 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; VI-NEXT: v_mov_b32_e32 v1, 0x200
; VI-NEXT: v_add_f16_e32 v7, s4, v1
; VI-NEXT: s_lshr_b32 s4, s16, 16
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
-; VI-NEXT: v_add_f16_e32 v14, s17, v1
; VI-NEXT: v_add_f16_e32 v12, s4, v1
; VI-NEXT: s_lshr_b32 s4, s19, 16
-; VI-NEXT: v_or_b32_e32 v39, v14, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v12
-; VI-NEXT: v_add_f16_e32 v21, s16, v1
; VI-NEXT: v_add_f16_e32 v8, s4, v1
; VI-NEXT: s_lshr_b32 s4, s18, 16
-; VI-NEXT: v_or_b32_e32 v38, v21, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v8
-; VI-NEXT: v_add_f16_e32 v16, s19, v1
; VI-NEXT: v_add_f16_e32 v13, s4, v1
; VI-NEXT: s_lshr_b32 s4, s21, 16
-; VI-NEXT: v_or_b32_e32 v36, v16, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
-; VI-NEXT: v_add_f16_e32 v23, s18, v1
; VI-NEXT: v_add_f16_e32 v9, s4, v1
; VI-NEXT: s_lshr_b32 s4, s20, 16
-; VI-NEXT: v_or_b32_e32 v35, v23, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
-; VI-NEXT: v_add_f16_e32 v18, s21, v1
; VI-NEXT: v_add_f16_e32 v15, s4, v1
; VI-NEXT: s_lshr_b32 s4, s23, 16
-; VI-NEXT: v_or_b32_e32 v33, v18, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v15
-; VI-NEXT: v_add_f16_e32 v24, s20, v1
; VI-NEXT: v_add_f16_e32 v10, s4, v1
; VI-NEXT: s_lshr_b32 s4, s22, 16
-; VI-NEXT: v_or_b32_e32 v32, v24, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
-; VI-NEXT: v_add_f16_e32 v20, s23, v1
; VI-NEXT: v_add_f16_e32 v17, s4, v1
; VI-NEXT: s_lshr_b32 s4, s25, 16
-; VI-NEXT: v_or_b32_e32 v31, v20, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; VI-NEXT: v_add_f16_e32 v25, s22, v1
; VI-NEXT: v_add_f16_e32 v11, s4, v1
; VI-NEXT: s_lshr_b32 s4, s24, 16
-; VI-NEXT: v_or_b32_e32 v30, v25, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
; VI-NEXT: v_add_f16_e32 v22, s25, v1
; VI-NEXT: v_add_f16_e32 v19, s4, v1
-; VI-NEXT: v_or_b32_e32 v28, v22, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
; VI-NEXT: v_add_f16_e32 v26, s24, v1
-; VI-NEXT: v_or_b32_e32 v27, v26, v2
+; VI-NEXT: v_add_f16_e32 v20, s23, v1
+; VI-NEXT: v_add_f16_e32 v25, s22, v1
+; VI-NEXT: v_lshl_or_b32 v28, v11, 16, v22
+; VI-NEXT: v_lshl_or_b32 v27, v19, 16, v26
+; VI-NEXT: v_add_f16_e32 v14, s17, v1
+; VI-NEXT: v_add_f16_e32 v21, s16, v1
+; VI-NEXT: v_add_f16_e32 v16, s19, v1
+; VI-NEXT: v_add_f16_e32 v23, s18, v1
+; VI-NEXT: v_add_f16_e32 v18, s21, v1
+; VI-NEXT: v_add_f16_e32 v24, s20, v1
+; VI-NEXT: v_lshl_or_b32 v31, v10, 16, v20
+; VI-NEXT: v_lshl_or_b32 v30, v17, 16, v25
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[27:28]
+; VI-NEXT: v_lshl_or_b32 v33, v9, 16, v18
+; VI-NEXT: v_lshl_or_b32 v32, v15, 16, v24
; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[30:31]
+; VI-NEXT: v_lshl_or_b32 v36, v8, 16, v16
+; VI-NEXT: v_lshl_or_b32 v35, v13, 16, v23
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[32:33]
+; VI-NEXT: v_lshl_or_b32 v39, v7, 16, v14
+; VI-NEXT: v_lshl_or_b32 v38, v12, 16, v21
; VI-NEXT: v_lshrrev_b64 v[4:5], 24, v[35:36]
; VI-NEXT: v_lshrrev_b64 v[5:6], 24, v[38:39]
; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v28
@@ -22958,61 +22709,51 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v5, v12, v5, s4
; VI-NEXT: v_perm_b32 v12, v21, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v5, v12, v5
-; VI-NEXT: v_perm_b32 v7, v7, v38, s4
+; VI-NEXT: v_lshl_or_b32 v5, v5, 16, v12
; VI-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v14, v39, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v5, v5, v7
+; VI-NEXT: v_perm_b32 v7, v7, v38, s4
+; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, 4, v0
-; VI-NEXT: v_perm_b32 v4, v13, v4, s4
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v23, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v4, v5, v4
+; VI-NEXT: v_perm_b32 v4, v13, v4, s4
+; VI-NEXT: v_lshl_or_b32 v4, v4, 16, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 8, v0
; VI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v5, v8, v35, s4
; VI-NEXT: v_perm_b32 v4, v16, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v8, v35, s4
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_add_u32_e32 v5, vcc, 12, v0
-; VI-NEXT: v_perm_b32 v3, v15, v3, s4
; VI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v4, v24, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v3, v4, v3
+; VI-NEXT: v_perm_b32 v3, v15, v3, s4
+; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v4, v9, v32, s4
; VI-NEXT: v_perm_b32 v3, v18, v33, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v9, v32, s4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
-; VI-NEXT: v_perm_b32 v2, v17, v2, s4
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v3, v25, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_perm_b32 v2, v17, v2, s4
+; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v3, v10, v30, s4
; VI-NEXT: v_perm_b32 v2, v20, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v30, s4
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
-; VI-NEXT: v_perm_b32 v1, v19, v1, s4
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, v26, v28, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_perm_b32 v1, v19, v1, s4
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v11, v27, s4
; VI-NEXT: v_perm_b32 v1, v22, v6, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v11, v27, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -23175,53 +22916,43 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
+; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v38, s4
; GFX9-NEXT: v_perm_b32 v10, v36, v37, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v33, s4
; GFX9-NEXT: v_perm_b32 v8, v31, v32, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v28, s4
; GFX9-NEXT: v_perm_b32 v6, v26, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v23, s4
; GFX9-NEXT: v_perm_b32 v4, v21, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v18, s4
; GFX9-NEXT: v_perm_b32 v2, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -23369,8 +23100,8 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v14, v34, v14, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v15
; GFX11-NEXT: v_perm_b32 v15, v32, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v36
; GFX11-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v14
@@ -23379,17 +23110,15 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v5, v5, v29, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-NEXT: v_or_b32_e32 v8, v10, v31
-; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v10, v14, v15
; GFX11-NEXT: v_perm_b32 v14, v22, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v13, v5, v13
; GFX11-NEXT: v_perm_b32 v5, v26, v12, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v6, v6, v25, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v27
; GFX11-NEXT: v_perm_b32 v3, v3, v24, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v20, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-NEXT: v_perm_b32 v1, v1, v17, 0xc0c0004
@@ -23397,8 +23126,8 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v2, v2, v16, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v15
; GFX11-NEXT: v_or_b32_e32 v9, v35, v9
-; GFX11-NEXT: v_or_b32_e32 v14, v6, v12
-; GFX11-NEXT: v_or_b32_e32 v15, v3, v5
+; GFX11-NEXT: v_lshl_or_b32 v14, v27, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v15, v5, 16, v3
; GFX11-NEXT: v_or_b32_e32 v16, v4, v18
; GFX11-NEXT: v_or_b32_e32 v1, v1, v11
; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
@@ -23843,48 +23572,37 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB62_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v37, v36, s6
; VI-NEXT: v_perm_b32 v0, v31, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v49, v48, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v37, v36, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v35, v34, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v53, v52, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v49, v48, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v39, v38, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v32, v54, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v53, v52, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v51, v50, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v32, v54, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v9, v44, v42, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, v30, v55, s6
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_perm_b32 v10, v47, v46, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v44, v42, s6
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, v47, v46, s6
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr37
@@ -25158,67 +24876,57 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s10, v0
; VI-NEXT: s_cbranch_scc0 .LBB63_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v9
; VI-NEXT: v_perm_b32 v0, s16, v0, v9
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v9
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v9
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v9
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s10, v4, v9
+; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_perm_b32 v3, s28, v3, v9
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s8
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s10, v4, v9
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s7
-; VI-NEXT: v_perm_b32 v5, s12, v5, v9
+; VI-NEXT: v_mov_b32_e32 v5, s8
; VI-NEXT: v_perm_b32 v4, s9, v4, v9
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s13
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s12, v5, v9
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s11
-; VI-NEXT: v_perm_b32 v6, s40, v6, v9
+; VI-NEXT: v_mov_b32_e32 v6, s13
; VI-NEXT: v_perm_b32 v5, s14, v5, v9
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s41
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s40, v6, v9
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s15
-; VI-NEXT: v_perm_b32 v7, s44, v7, v9
+; VI-NEXT: v_mov_b32_e32 v7, s41
; VI-NEXT: v_perm_b32 v6, s42, v6, v9
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s45
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s44, v7, v9
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s43
-; VI-NEXT: v_perm_b32 v8, s56, v8, v9
+; VI-NEXT: v_mov_b32_e32 v8, s45
; VI-NEXT: v_perm_b32 v7, s46, v7, v9
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v10, s57
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s56, v8, v9
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s47
-; VI-NEXT: v_perm_b32 v10, s60, v10, v9
+; VI-NEXT: v_mov_b32_e32 v10, s57
; VI-NEXT: v_perm_b32 v8, s58, v8, v9
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v8, v8, v10
+; VI-NEXT: v_perm_b32 v10, s60, v10, v9
+; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s59
; VI-NEXT: v_mov_b32_e32 v11, s62
; VI-NEXT: v_perm_b32 v10, s61, v10, v9
; VI-NEXT: v_perm_b32 v9, s63, v11, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; VI-NEXT: s_cbranch_execnz .LBB63_3
; VI-NEXT: .LBB63_2: ; %cmp.true
; VI-NEXT: s_add_i32 s63, s63, 3
@@ -28239,48 +27947,37 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB72_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v52, v51, s6
; VI-NEXT: v_perm_b32 v0, v54, v53, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v48, v39, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v52, v51, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v50, v49, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v36, v35, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v48, v39, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v38, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v36, v35, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v34, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v32, v31, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_perm_b32 v8, v30, v45, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v9, v44, v43, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, v30, v45, s6
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v47, v46, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_perm_b32 v10, v40, v55, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v44, v43, s6
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v42, v41, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, v40, v55, s6
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -29057,12 +28754,11 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
@@ -29472,67 +29168,57 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s63, v0
; VI-NEXT: s_cbranch_scc0 .LBB73_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v9
; VI-NEXT: v_perm_b32 v0, s16, v0, v9
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v9
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v9
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v9
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s62
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s63, v4, v9
+; VI-NEXT: v_mov_b32_e32 v4, s62
; VI-NEXT: v_perm_b32 v3, s28, v3, v9
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s63, v4, v9
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s60
-; VI-NEXT: v_perm_b32 v5, s59, v5, v9
+; VI-NEXT: v_mov_b32_e32 v5, s58
; VI-NEXT: v_perm_b32 v4, s61, v4, v9
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s59, v5, v9
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s56
-; VI-NEXT: v_perm_b32 v6, s47, v6, v9
+; VI-NEXT: v_mov_b32_e32 v6, s46
; VI-NEXT: v_perm_b32 v5, s57, v5, v9
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s42
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s47, v6, v9
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s44
-; VI-NEXT: v_perm_b32 v7, s43, v7, v9
+; VI-NEXT: v_mov_b32_e32 v7, s42
; VI-NEXT: v_perm_b32 v6, s45, v6, v9
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s14
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s43, v7, v9
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s40
-; VI-NEXT: v_perm_b32 v8, s15, v8, v9
+; VI-NEXT: v_mov_b32_e32 v8, s14
; VI-NEXT: v_perm_b32 v7, s41, v7, v9
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s15, v8, v9
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s12
-; VI-NEXT: v_perm_b32 v10, s11, v10, v9
+; VI-NEXT: v_mov_b32_e32 v10, s10
; VI-NEXT: v_perm_b32 v8, s13, v8, v9
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v8, v8, v10
+; VI-NEXT: v_perm_b32 v10, s11, v10, v9
+; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s8
; VI-NEXT: v_mov_b32_e32 v11, s6
; VI-NEXT: v_perm_b32 v10, s9, v10, v9
; VI-NEXT: v_perm_b32 v9, s7, v11, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; VI-NEXT: s_cbranch_execnz .LBB73_3
; VI-NEXT: .LBB73_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -29675,67 +29361,57 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB73_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_mov_b32_e32 v4, s62
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s60
-; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_mov_b32_e32 v5, s58
; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s56
-; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_mov_b32_e32 v6, s46
; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s44
-; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_mov_b32_e32 v7, s42
; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s40
-; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v8, s14
; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s12
-; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_mov_b32_e32 v10, s10
; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; GFX9-NEXT: s_cbranch_execnz .LBB73_3
; GFX9-NEXT: .LBB73_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -29867,47 +29543,37 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB73_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v14
+; GFX11-NEXT: v_lshl_or_b32 v9, v13, 16, v15
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB73_3
; GFX11-NEXT: .LBB73_2: ; %cmp.true
@@ -30367,61 +30033,51 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v48, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v1, v1, v15
+; VI-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v39, s4
; VI-NEXT: v_perm_b32 v2, v38, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v35, v14, s4
; VI-NEXT: v_perm_b32 v1, v3, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v35, v14, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v33, v32, s4
; VI-NEXT: v_perm_b32 v1, v4, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v33, v32, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v30, v13, s4
; VI-NEXT: v_perm_b32 v1, v5, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v30, v13, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v28, v27, s4
; VI-NEXT: v_perm_b32 v1, v6, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v28, v27, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v25, v12, s4
; VI-NEXT: v_perm_b32 v1, v7, v26, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v25, v12, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v23, v22, s4
; VI-NEXT: v_perm_b32 v1, v8, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v23, v22, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v20, v11, s4
; VI-NEXT: v_perm_b32 v1, v9, v21, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v20, v11, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v18, v17, s4
; VI-NEXT: v_perm_b32 v1, v10, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v18, v17, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -31280,61 +30936,51 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v34, v15, s4
; VI-NEXT: v_perm_b32 v9, v9, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v9, v9, v15
+; VI-NEXT: v_lshl_or_b32 v9, v15, 16, v9
; VI-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v9, v10, v48, s4
; VI-NEXT: v_perm_b32 v10, v39, v38, s4
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_add_u32_e32 v10, vcc, 4, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v9, v31, v14, s4
; VI-NEXT: v_perm_b32 v7, v7, v32, s4
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v7, v7, v9
+; VI-NEXT: v_perm_b32 v9, v31, v14, s4
+; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, 8, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v7, v8, v37, s4
; VI-NEXT: v_perm_b32 v8, v35, v33, s4
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 12, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v7, v26, v13, s4
; VI-NEXT: v_perm_b32 v5, v5, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v5, v5, v7
+; VI-NEXT: v_perm_b32 v7, v26, v13, s4
+; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, 16, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v6, v30, s4
; VI-NEXT: v_perm_b32 v6, v29, v28, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 20, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v5, v21, v12, s4
; VI-NEXT: v_perm_b32 v3, v3, v22, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v3, v3, v5
+; VI-NEXT: v_perm_b32 v5, v21, v12, s4
+; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; VI-NEXT: v_add_u32_e32 v5, vcc, 24, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v3, v4, v25, s4
; VI-NEXT: v_perm_b32 v4, v24, v23, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v3, v18, v11, s4
; VI-NEXT: v_perm_b32 v1, v1, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, v18, v11, s4
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v20, s4
; VI-NEXT: v_perm_b32 v2, v17, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -31491,53 +31137,43 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v33, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
+; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v48, s4
; GFX9-NEXT: v_perm_b32 v10, v39, v38, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v9, v30, v14, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v32, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v30, v14, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v37, s4
; GFX9-NEXT: v_perm_b32 v8, v36, v34, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v7, v26, v13, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v26, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v31, s4
; GFX9-NEXT: v_perm_b32 v6, v29, v28, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v5, v21, v12, s4
; GFX9-NEXT: v_perm_b32 v3, v3, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_perm_b32 v5, v21, v12, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v25, s4
; GFX9-NEXT: v_perm_b32 v4, v24, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v3, v17, v11, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, v17, v11, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v20, s4
; GFX9-NEXT: v_perm_b32 v2, v18, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -31672,47 +31308,37 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v33, s24 :: v_dual_mov_b32 v38, s23
; GFX11-NEXT: v_dual_mov_b32 v39, s22 :: v_dual_mov_b32 v48, s15
; GFX11-NEXT: .LBB75_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v16, v34, v16, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v12, v12, v35, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v32, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v31, v37, v36, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v32, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-NEXT: v_perm_b32 v14, v28, v14, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-NEXT: v_perm_b32 v8, v8, v33, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v34, v16, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v12, v35, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v34, v39, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v16
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
; GFX11-NEXT: v_perm_b32 v5, v5, v26, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v14
-; GFX11-NEXT: v_or_b32_e32 v14, v7, v15
+; GFX11-NEXT: v_lshl_or_b32 v14, v15, 16, v7
; GFX11-NEXT: v_perm_b32 v7, v30, v29, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v15, v8, v16
+; GFX11-NEXT: v_lshl_or_b32 v15, v31, 16, v8
; GFX11-NEXT: v_perm_b32 v8, v23, v10, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v25, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v19, v9, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v16, v20, v18, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v34
; GFX11-NEXT: v_perm_b32 v6, v6, v27, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v3, v3, v22, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_perm_b32 v10, v25, v24, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v12, v16, 16, v12
+; GFX11-NEXT: v_perm_b32 v9, v19, v9, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v20, v18, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v1, v1, v11, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v16
-; GFX11-NEXT: v_or_b32_e32 v13, v13, v28
+; GFX11-NEXT: v_lshl_or_b32 v13, v34, 16, v13
; GFX11-NEXT: v_or_b32_e32 v5, v5, v26
-; GFX11-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v3, v8
-; GFX11-NEXT: v_or_b32_e32 v8, v4, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v9
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v11
+; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v8, v10, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v1, v9, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v16, 16, v2
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[12:15], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -32086,48 +31712,37 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB76_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v52, v51, s6
; VI-NEXT: v_perm_b32 v0, v54, v53, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v48, v39, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v52, v51, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v50, v49, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v36, v35, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v48, v39, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v38, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v36, v35, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v34, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v32, v31, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_perm_b32 v8, v30, v45, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v9, v44, v43, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, v30, v45, s6
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v47, v46, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_perm_b32 v10, v40, v55, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v44, v43, s6
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v42, v41, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, v40, v55, s6
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -32904,12 +32519,11 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
@@ -33319,67 +32933,57 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s63, v0
; VI-NEXT: s_cbranch_scc0 .LBB77_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v9
; VI-NEXT: v_perm_b32 v0, s16, v0, v9
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v9
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v9
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, s22, v2, v9
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v9
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s62
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v9
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s63, v4, v9
+; VI-NEXT: v_mov_b32_e32 v4, s62
; VI-NEXT: v_perm_b32 v3, s28, v3, v9
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s63, v4, v9
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s60
-; VI-NEXT: v_perm_b32 v5, s59, v5, v9
+; VI-NEXT: v_mov_b32_e32 v5, s58
; VI-NEXT: v_perm_b32 v4, s61, v4, v9
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s59, v5, v9
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s56
-; VI-NEXT: v_perm_b32 v6, s47, v6, v9
+; VI-NEXT: v_mov_b32_e32 v6, s46
; VI-NEXT: v_perm_b32 v5, s57, v5, v9
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s42
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s47, v6, v9
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s44
-; VI-NEXT: v_perm_b32 v7, s43, v7, v9
+; VI-NEXT: v_mov_b32_e32 v7, s42
; VI-NEXT: v_perm_b32 v6, s45, v6, v9
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s14
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s43, v7, v9
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s40
-; VI-NEXT: v_perm_b32 v8, s15, v8, v9
+; VI-NEXT: v_mov_b32_e32 v8, s14
; VI-NEXT: v_perm_b32 v7, s41, v7, v9
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s15, v8, v9
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s12
-; VI-NEXT: v_perm_b32 v10, s11, v10, v9
+; VI-NEXT: v_mov_b32_e32 v10, s10
; VI-NEXT: v_perm_b32 v8, s13, v8, v9
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v8, v8, v10
+; VI-NEXT: v_perm_b32 v10, s11, v10, v9
+; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s8
; VI-NEXT: v_mov_b32_e32 v11, s6
; VI-NEXT: v_perm_b32 v10, s9, v10, v9
; VI-NEXT: v_perm_b32 v9, s7, v11, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v9, v10, v9
+; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; VI-NEXT: s_cbranch_execnz .LBB77_3
; VI-NEXT: .LBB77_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -33522,67 +33126,57 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB77_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_mov_b32_e32 v4, s62
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s60
-; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_mov_b32_e32 v5, s58
; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s56
-; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_mov_b32_e32 v6, s46
; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s44
-; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_mov_b32_e32 v7, s42
; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s40
-; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v8, s14
; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s12
-; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_mov_b32_e32 v10, s10
; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; GFX9-NEXT: s_cbranch_execnz .LBB77_3
; GFX9-NEXT: .LBB77_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -33714,47 +33308,37 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB77_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v14
+; GFX11-NEXT: v_lshl_or_b32 v9, v13, 16, v15
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB77_3
; GFX11-NEXT: .LBB77_2: ; %cmp.true
@@ -34224,61 +33808,51 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v48, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v1, v1, v15
+; VI-NEXT: v_lshl_or_b32 v1, v15, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v39, s4
; VI-NEXT: v_perm_b32 v2, v38, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v35, v14, s4
; VI-NEXT: v_perm_b32 v1, v3, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v35, v14, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v33, v32, s4
; VI-NEXT: v_perm_b32 v1, v4, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v33, v32, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v30, v13, s4
; VI-NEXT: v_perm_b32 v1, v5, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v30, v13, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v28, v27, s4
; VI-NEXT: v_perm_b32 v1, v6, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v28, v27, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v25, v12, s4
; VI-NEXT: v_perm_b32 v1, v7, v26, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v25, v12, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v23, v22, s4
; VI-NEXT: v_perm_b32 v1, v8, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v23, v22, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v20, v11, s4
; VI-NEXT: v_perm_b32 v1, v9, v21, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v20, v11, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v18, v17, s4
; VI-NEXT: v_perm_b32 v1, v10, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v18, v17, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -35068,84 +34642,74 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; VI-NEXT: s_lshr_b32 s75, s16, 16
; VI-NEXT: s_lshr_b32 s76, s16, 8
; VI-NEXT: .LBB79_3: ; %end
+; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s12
-; VI-NEXT: v_mov_b32_e32 v1, s76
-; VI-NEXT: v_perm_b32 v3, s75, v3, v2
; VI-NEXT: v_perm_b32 v1, s16, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
-; VI-NEXT: v_mov_b32_e32 v3, s72
+; VI-NEXT: v_perm_b32 v3, s75, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s74
-; VI-NEXT: v_perm_b32 v3, s73, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: v_perm_b32 v1, s17, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s73, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_mov_b32_e32 v1, s63
-; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s59
; VI-NEXT: v_mov_b32_e32 v1, s61
-; VI-NEXT: v_perm_b32 v3, s60, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s59
; VI-NEXT: v_perm_b32 v1, s19, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s60, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_mov_b32_e32 v1, s58
-; VI-NEXT: v_perm_b32 v3, s57, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s57, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s46
; VI-NEXT: v_mov_b32_e32 v1, s56
-; VI-NEXT: v_perm_b32 v3, s47, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s46
; VI-NEXT: v_perm_b32 v1, s21, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s47, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_mov_b32_e32 v1, s45
-; VI-NEXT: v_perm_b32 v3, s44, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_perm_b32 v1, s22, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s44, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s41
; VI-NEXT: v_mov_b32_e32 v1, s43
-; VI-NEXT: v_perm_b32 v3, s42, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s41
; VI-NEXT: v_perm_b32 v1, s23, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s42, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v1, s40
-; VI-NEXT: v_perm_b32 v3, s29, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_perm_b32 v1, s24, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s29, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s28
; VI-NEXT: v_mov_b32_e32 v3, s26
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
; VI-NEXT: v_perm_b32 v2, s27, v3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -35262,76 +34826,66 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; GFX9-NEXT: s_lshr_b32 s75, s16, 16
; GFX9-NEXT: s_lshr_b32 s76, s16, 8
; GFX9-NEXT: .LBB79_3: ; %end
+; GFX9-NEXT: v_mov_b32_e32 v1, s76
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s12
-; GFX9-NEXT: v_mov_b32_e32 v1, s76
-; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s72
+; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s74
-; GFX9-NEXT: v_perm_b32 v3, s73, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
+; GFX9-NEXT: v_perm_b32 v3, s73, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s59
+; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s61
-; GFX9-NEXT: v_perm_b32 v3, s60, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s59
; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_perm_b32 v3, s60, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s58
-; GFX9-NEXT: v_perm_b32 v3, s57, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s46
+; GFX9-NEXT: v_perm_b32 v3, s57, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s56
-; GFX9-NEXT: v_perm_b32 v3, s47, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
+; GFX9-NEXT: v_perm_b32 v3, s47, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s45
-; GFX9-NEXT: v_perm_b32 v3, s44, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s41
+; GFX9-NEXT: v_perm_b32 v3, s44, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s43
-; GFX9-NEXT: v_perm_b32 v3, s42, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s41
; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s4
+; GFX9-NEXT: v_perm_b32 v3, s42, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s40
-; GFX9-NEXT: v_perm_b32 v3, s29, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s29, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s28
; GFX9-NEXT: v_mov_b32_e32 v3, s26
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s27, v3, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -35450,47 +35004,37 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; GFX11-NEXT: s_lshr_b32 s62, s0, 8
; GFX11-NEXT: .LBB79_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v6, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v2, s61, s12, v6
-; GFX11-NEXT: v_perm_b32 v4, s59, s58, v6
-; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
-; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s0, s62, v6
+; GFX11-NEXT: v_perm_b32 v2, s61, s12, v6
; GFX11-NEXT: v_perm_b32 v3, s1, s60, v6
+; GFX11-NEXT: v_perm_b32 v4, s59, s58, v6
; GFX11-NEXT: v_perm_b32 v5, s2, s57, v6
+; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
; GFX11-NEXT: v_perm_b32 v8, s3, s47, v6
+; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
; GFX11-NEXT: v_perm_b32 v10, s16, s44, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v12, s24, s4, v6
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v5, v7
+; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v7, 16, v5
; GFX11-NEXT: v_perm_b32 v7, s42, s41, v6
-; GFX11-NEXT: v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v11
+; GFX11-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v5, v11, 16, v10
; GFX11-NEXT: v_perm_b32 v8, s29, s6, v6
-; GFX11-NEXT: v_perm_b32 v11, s27, s26, v6
-; GFX11-NEXT: v_perm_b32 v14, s22, s14, v6
; GFX11-NEXT: v_perm_b32 v9, s17, s40, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v10, s18, s28, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_perm_b32 v11, s27, s26, v6
; GFX11-NEXT: v_perm_b32 v13, s19, s25, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: v_perm_b32 v12, s24, s4, v6
+; GFX11-NEXT: v_perm_b32 v14, s22, s14, v6
; GFX11-NEXT: v_perm_b32 v15, s20, s23, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_perm_b32 v16, s21, s15, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v10, v8
-; GFX11-NEXT: v_or_b32_e32 v8, v13, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v12
-; GFX11-NEXT: v_or_b32_e32 v10, v16, v14
+; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v9, v12, 16, v15
+; GFX11-NEXT: v_lshl_or_b32 v10, v14, 16, v16
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
index 123d1042e27c9..c25ad3ffd6e38 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
@@ -2232,8 +2232,7 @@ define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -2377,11 +2376,9 @@ define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -2450,8 +2447,7 @@ define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) #0
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_cbranch_execnz .LBB23_3
; VI-NEXT: .LBB23_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -2482,8 +2478,7 @@ define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) #0
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB23_3
; GFX9-NEXT: .LBB23_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -2511,12 +2506,10 @@ define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) #0
; GFX11-NEXT: s_cbranch_scc0 .LBB23_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB23_3
; GFX11-NEXT: .LBB23_2: ; %cmp.true
@@ -2530,9 +2523,8 @@ define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) #0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB23_4:
@@ -4495,8 +4487,7 @@ define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -4640,11 +4631,9 @@ define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4713,8 +4702,7 @@ define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b)
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: .LBB43_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -4745,8 +4733,7 @@ define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b)
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB43_3
; GFX9-NEXT: .LBB43_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -4774,12 +4761,10 @@ define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b)
; GFX11-NEXT: s_cbranch_scc0 .LBB43_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB43_3
; GFX11-NEXT: .LBB43_2: ; %cmp.true
@@ -4793,9 +4778,8 @@ define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: .LBB43_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_4:
@@ -6155,10 +6139,9 @@ define <4 x i8> @bitcast_v2i16_to_v4i8(<2 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB56_2
; VI-NEXT: .LBB56_4: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v1, 3
-; VI-NEXT: v_add_u16_sdwa v2, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v0, 3, v4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v0, v1
+; VI-NEXT: v_add_u16_sdwa v2, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; VI-NEXT: v_bfe_u32 v3, v2, 8, 8
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -6476,8 +6459,7 @@ define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -6621,11 +6603,9 @@ define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6700,8 +6680,7 @@ define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inre
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_cbranch_execnz .LBB59_3
; VI-NEXT: .LBB59_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -6732,8 +6711,7 @@ define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inre
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB59_3
; GFX9-NEXT: .LBB59_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -6761,12 +6739,10 @@ define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_cbranch_scc0 .LBB59_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB59_3
; GFX11-NEXT: .LBB59_2: ; %cmp.true
@@ -6780,9 +6756,8 @@ define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: .LBB59_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB59_4:
@@ -7811,9 +7786,8 @@ define <4 x i8> @bitcast_v2f16_to_v4i8(<2 x half> %a, i32 %b) #0 {
; VI-NEXT: .LBB68_4: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v1, 0x200
; VI-NEXT: v_add_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
-; VI-NEXT: v_or_b32_e32 v1, v0, v1
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; VI-NEXT: v_bfe_u32 v3, v2, 8, 8
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -7977,9 +7951,8 @@ define inreg <4 x i8> @bitcast_v2f16_to_v4i8_scalar(<2 x half> inreg %a, i32 inr
; VI-NEXT: s_lshr_b32 s4, s16, 16
; VI-NEXT: v_mov_b32_e32 v0, 0x200
; VI-NEXT: v_add_f16_e32 v2, s4, v0
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; VI-NEXT: v_add_f16_e32 v0, s16, v0
-; VI-NEXT: v_or_b32_e32 v1, v0, v1
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v0
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; VI-NEXT: v_bfe_u32 v3, v2, 8, 8
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8135,8 +8108,7 @@ define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -8280,11 +8252,9 @@ define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -8359,8 +8329,7 @@ define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inr
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_cbranch_execnz .LBB71_3
; VI-NEXT: .LBB71_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -8391,8 +8360,7 @@ define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inr
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -8420,12 +8388,10 @@ define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inr
; GFX11-NEXT: s_cbranch_scc0 .LBB71_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-NEXT: .LBB71_2: ; %cmp.true
@@ -8439,9 +8405,8 @@ define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inr
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: .LBB71_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB71_4:
@@ -9578,8 +9543,7 @@ define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -9723,11 +9687,9 @@ define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9798,8 +9760,7 @@ define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_cbranch_execnz .LBB79_3
; VI-NEXT: .LBB79_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -9830,8 +9791,7 @@ define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB79_3
; GFX9-NEXT: .LBB79_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9859,12 +9819,10 @@ define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB79_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB79_3
; GFX11-NEXT: .LBB79_2: ; %cmp.true
@@ -9878,9 +9836,8 @@ define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: .LBB79_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB79_4:
@@ -10262,8 +10219,7 @@ define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -10407,11 +10363,9 @@ define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -10480,8 +10434,7 @@ define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inre
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_cbranch_execnz .LBB83_3
; VI-NEXT: .LBB83_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -10512,8 +10465,7 @@ define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inre
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB83_3
; GFX9-NEXT: .LBB83_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -10541,12 +10493,10 @@ define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_cbranch_scc0 .LBB83_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB83_3
; GFX11-NEXT: .LBB83_2: ; %cmp.true
@@ -10560,9 +10510,8 @@ define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: .LBB83_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB83_4:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index d43b0226756d5..f7641f6cb6724 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -9097,102 +9097,86 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v1, v1, v21
+; VI-NEXT: v_lshl_or_b32 v1, v21, 16, v1
+; VI-NEXT: v_perm_b32 v2, v2, v29, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
-; VI-NEXT: v_perm_b32 v2, v2, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v59, v58, s4
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v59, v58, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v56, v26, s4
; VI-NEXT: v_perm_b32 v1, v5, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v56, v26, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v46, v45, s4
; VI-NEXT: v_perm_b32 v1, v6, v47, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v46, v45, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v43, v25, s4
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v43, v25, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v41, v40, s4
; VI-NEXT: v_perm_b32 v1, v8, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v41, v40, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v54, v22, s4
; VI-NEXT: v_perm_b32 v1, v9, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v54, v22, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v52, v51, s4
; VI-NEXT: v_perm_b32 v1, v10, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v52, v51, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v49, v19, s4
; VI-NEXT: v_perm_b32 v1, v11, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v49, v19, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v39, v38, s4
; VI-NEXT: v_perm_b32 v1, v12, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v39, v38, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v36, v18, s4
; VI-NEXT: v_perm_b32 v1, v13, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v36, v18, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v34, v33, s4
; VI-NEXT: v_perm_b32 v1, v14, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v34, v33, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -10540,132 +10524,116 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; VI-NEXT: s_lshr_b32 s66, s16, 16
; VI-NEXT: s_lshr_b32 s67, s16, 8
; VI-NEXT: .LBB25_3: ; %end
+; VI-NEXT: v_mov_b32_e32 v1, s67
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s44
-; VI-NEXT: v_mov_b32_e32 v1, s67
-; VI-NEXT: v_perm_b32 v3, s66, v3, v2
; VI-NEXT: v_perm_b32 v1, s16, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
-; VI-NEXT: v_mov_b32_e32 v3, s55
+; VI-NEXT: v_perm_b32 v3, s66, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s65
-; VI-NEXT: v_perm_b32 v3, s64, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s55
; VI-NEXT: v_perm_b32 v1, s17, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s64, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s42
; VI-NEXT: v_mov_b32_e32 v1, s54
-; VI-NEXT: v_perm_b32 v3, s53, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s42
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s53, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s50
; VI-NEXT: v_mov_b32_e32 v1, s52
-; VI-NEXT: v_perm_b32 v3, s51, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s50
; VI-NEXT: v_perm_b32 v1, s19, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s51, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s40
; VI-NEXT: v_mov_b32_e32 v1, s49
-; VI-NEXT: v_perm_b32 v3, s48, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s40
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s48, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s37
; VI-NEXT: v_mov_b32_e32 v1, s39
-; VI-NEXT: v_perm_b32 v3, s38, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s37
; VI-NEXT: v_perm_b32 v1, s21, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s38, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_mov_b32_e32 v1, s36
-; VI-NEXT: v_perm_b32 v3, s35, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_perm_b32 v1, s22, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s35, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s30
; VI-NEXT: v_mov_b32_e32 v1, s34
-; VI-NEXT: v_perm_b32 v3, s31, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s30
; VI-NEXT: v_perm_b32 v1, s23, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s31, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_mov_b32_e32 v1, s91
-; VI-NEXT: v_perm_b32 v3, s90, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_perm_b32 v1, s24, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s90, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s79
; VI-NEXT: v_mov_b32_e32 v1, s89
-; VI-NEXT: v_perm_b32 v3, s88, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s79
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s88, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_mov_b32_e32 v1, s78
-; VI-NEXT: v_perm_b32 v3, s77, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_perm_b32 v1, s26, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s77, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_mov_b32_e32 v1, s76
-; VI-NEXT: v_perm_b32 v3, s75, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_perm_b32 v1, s27, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s75, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_mov_b32_e32 v1, s73
-; VI-NEXT: v_perm_b32 v3, s72, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_perm_b32 v1, s28, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s72, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s61
; VI-NEXT: v_mov_b32_e32 v1, s63
-; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s61
; VI-NEXT: v_perm_b32 v1, s29, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_mov_b32_e32 v1, s60
-; VI-NEXT: v_perm_b32 v3, s59, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_perm_b32 v1, s4, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s59, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_perm_b32 v1, s5, v1, v2
; VI-NEXT: v_perm_b32 v2, s57, v3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: v_readlane_b32 s30, v4, 18
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -10887,118 +10855,102 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX9-NEXT: s_lshr_b32 s54, s16, 16
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
; GFX9-NEXT: .LBB25_3: ; %end
+; GFX9-NEXT: v_mov_b32_e32 v1, s55
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s44
-; GFX9-NEXT: v_mov_b32_e32 v1, s55
-; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s51
+; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s53
-; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s51
; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s42
+; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s50
-; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s42
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s38
+; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s48
-; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s38
; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s40
+; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s37
-; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s40
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s31
+; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s35
-; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s31
; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s14
+; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s30
-; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s92
+; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s94
-; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s92
; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s12
+; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s91
-; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s79
+; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s89
-; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s79
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
+; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: v_mov_b32_e32 v1, s78
-; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_perm_b32 v1, s26, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s74
+; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_mov_b32_e32 v1, s76
-; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: v_perm_b32 v1, s27, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_mov_b32_e32 v1, s73
-; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_perm_b32 v1, s28, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s61
+; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s61
; GFX9-NEXT: v_perm_b32 v1, s29, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
+; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v1, s60
-; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_perm_b32 v1, s4, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v1, s58
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_perm_b32 v1, s5, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s57, v3, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_readlane_b32 s30, v4, 14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_readlane_b32 s31, v4, 15
@@ -11208,72 +11160,59 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
; GFX11-NEXT: .LBB25_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v12, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
-; GFX11-NEXT: v_readlane_b32 s34, v23, 0
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
-; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_perm_b32 v1, s0, s48, v12
+; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
; GFX11-NEXT: v_perm_b32 v3, s1, s38, v12
+; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
+; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
; GFX11-NEXT: v_perm_b32 v6, s2, s35, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_perm_b32 v8, s30, vcc_hi, v12
-; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
-; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v6, v5
-; GFX11-NEXT: v_perm_b32 v5, s93, s92, v12
+; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
+; GFX11-NEXT: v_lshl_or_b32 v3, v5, 16, v6
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s16, s94, v12
+; GFX11-NEXT: v_perm_b32 v5, s93, s92, v12
; GFX11-NEXT: v_perm_b32 v8, s90, s12, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
+; GFX11-NEXT: v_perm_b32 v6, s16, s94, v12
+; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
; GFX11-NEXT: v_perm_b32 v13, s18, s89, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-NEXT: v_or_b32_e32 v5, v6, v9
; GFX11-NEXT: v_perm_b32 v9, s88, s78, v12
; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT: v_perm_b32 v10, s77, s10, v12
-; GFX11-NEXT: v_perm_b32 v11, s75, s74, v12
-; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
-; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-NEXT: v_or_b32_e32 v7, v13, v8
; GFX11-NEXT: v_perm_b32 v8, s19, s79, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_perm_b32 v10, s77, s10, v12
+; GFX11-NEXT: v_perm_b32 v11, s75, s74, v12
; GFX11-NEXT: v_perm_b32 v13, s20, s76, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v15, s21, s73, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
; GFX11-NEXT: v_perm_b32 v16, s22, s63, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v9, v13, v10
+; GFX11-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v9, v10, 16, v13
; GFX11-NEXT: v_perm_b32 v13, s62, s61, v12
-; GFX11-NEXT: v_or_b32_e32 v10, v15, v11
-; GFX11-NEXT: v_or_b32_e32 v11, v16, v14
+; GFX11-NEXT: v_lshl_or_b32 v10, v11, 16, v15
+; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
+; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v16
; GFX11-NEXT: v_perm_b32 v14, s59, s6, v12
+; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
; GFX11-NEXT: v_perm_b32 v17, s57, s56, v12
; GFX11-NEXT: v_perm_b32 v18, s46, s4, v12
-; GFX11-NEXT: v_perm_b32 v20, s44, s42, v12
-; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v19, s25, s47, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-NEXT: v_perm_b32 v20, s44, s42, v12
; GFX11-NEXT: v_perm_b32 v21, s26, s45, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-NEXT: v_perm_b32 v22, s27, s43, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT: v_or_b32_e32 v12, v15, v13
-; GFX11-NEXT: v_or_b32_e32 v13, v16, v14
-; GFX11-NEXT: v_or_b32_e32 v14, v19, v17
-; GFX11-NEXT: v_or_b32_e32 v15, v21, v18
-; GFX11-NEXT: v_or_b32_e32 v16, v22, v20
+; GFX11-NEXT: v_lshl_or_b32 v12, v13, 16, v15
+; GFX11-NEXT: v_lshl_or_b32 v13, v14, 16, v16
+; GFX11-NEXT: v_lshl_or_b32 v14, v17, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v21
+; GFX11-NEXT: v_lshl_or_b32 v16, v20, 16, v22
; GFX11-NEXT: v_readlane_b32 s30, v23, 7
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
@@ -11287,6 +11226,7 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: v_readlane_b32 s37, v23, 3
; GFX11-NEXT: v_readlane_b32 s36, v23, 2
; GFX11-NEXT: v_readlane_b32 s35, v23, 1
+; GFX11-NEXT: v_readlane_b32 s34, v23, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v23, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -12051,44 +11991,33 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB26_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v52, v51, s6
-; VI-NEXT: v_perm_b32 v3, v48, v39, s6
; VI-NEXT: v_perm_b32 v0, v54, v53, s6
+; VI-NEXT: v_perm_b32 v1, v52, v51, s6
; VI-NEXT: v_perm_b32 v2, v50, v49, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_perm_b32 v3, v36, v35, s6
+; VI-NEXT: v_perm_b32 v3, v48, v39, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_perm_b32 v2, v38, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v36, v35, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v34, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v32, v31, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -12128,11 +12057,9 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -12140,20 +12067,19 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr24
@@ -12189,8 +12115,7 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -12213,10 +12138,9 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
@@ -13470,9 +13394,9 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
@@ -13485,13 +13409,12 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
@@ -13515,28 +13438,27 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
@@ -13551,12 +13473,11 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
@@ -14136,96 +14057,80 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB27_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s75
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s73
-; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s63
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s61
-; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s59
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s57
-; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s47
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s45
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s13
-; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s11
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s9
-; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s7
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s8, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v24, v22, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v24, v22, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
-; VI-NEXT: v_or_b32_e32 v15, v35, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; VI-NEXT: s_cbranch_execnz .LBB27_3
; VI-NEXT: .LBB27_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -14447,98 +14352,81 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
+; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
+; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -14747,74 +14635,63 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-TRUE16-NEXT: .LBB27_2: ; %cmp.true
@@ -14829,18 +14706,17 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -15031,74 +14907,63 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-FAKE16-NEXT: .LBB27_2: ; %cmp.true
@@ -15113,18 +14978,17 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -23865,102 +23729,86 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v1, v1, v21
+; VI-NEXT: v_lshl_or_b32 v1, v21, 16, v1
+; VI-NEXT: v_perm_b32 v2, v2, v29, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
-; VI-NEXT: v_perm_b32 v2, v2, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v59, v58, s4
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v59, v58, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v56, v26, s4
; VI-NEXT: v_perm_b32 v1, v5, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v56, v26, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v46, v45, s4
; VI-NEXT: v_perm_b32 v1, v6, v47, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v46, v45, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v43, v25, s4
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v43, v25, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v41, v40, s4
; VI-NEXT: v_perm_b32 v1, v8, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v41, v40, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v54, v22, s4
; VI-NEXT: v_perm_b32 v1, v9, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v54, v22, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v52, v51, s4
; VI-NEXT: v_perm_b32 v1, v10, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v52, v51, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v49, v19, s4
; VI-NEXT: v_perm_b32 v1, v11, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v49, v19, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v39, v38, s4
; VI-NEXT: v_perm_b32 v1, v12, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v39, v38, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v36, v18, s4
; VI-NEXT: v_perm_b32 v1, v13, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v36, v18, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v34, v33, s4
; VI-NEXT: v_perm_b32 v1, v14, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v34, v33, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -25478,73 +25326,61 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v18, v18, v24, s4
; VI-NEXT: v_perm_b32 v15, v15, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
-; VI-NEXT: v_or_b32_e32 v15, v15, v17
+; VI-NEXT: v_lshl_or_b32 v15, v18, 16, v15
+; VI-NEXT: v_perm_b32 v16, v16, v62, s4
; VI-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v15, v60, v61, s4
-; VI-NEXT: v_perm_b32 v16, v16, v62, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v15, v16, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; VI-NEXT: v_add_u32_e32 v16, vcc, 4, v0
; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v15, v59, v23, s4
; VI-NEXT: v_perm_b32 v13, v13, v58, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v13, v13, v15
+; VI-NEXT: v_lshl_or_b32 v13, v15, 16, v13
; VI-NEXT: v_add_u32_e32 v15, vcc, 8, v0
; VI-NEXT: buffer_store_dword v13, v15, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v13, v14, v57, s4
; VI-NEXT: v_perm_b32 v14, v47, v56, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_add_u32_e32 v14, vcc, 12, v0
; VI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v13, v45, v22, s4
; VI-NEXT: v_perm_b32 v11, v11, v46, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_or_b32_e32 v11, v11, v13
+; VI-NEXT: v_perm_b32 v13, v45, v22, s4
+; VI-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; VI-NEXT: v_add_u32_e32 v13, vcc, 16, v0
; VI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v11, v12, v44, s4
; VI-NEXT: v_perm_b32 v12, v42, v43, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_add_u32_e32 v12, vcc, 20, v0
; VI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v11, v40, v21, s4
; VI-NEXT: v_perm_b32 v9, v9, v41, s4
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; VI-NEXT: v_or_b32_e32 v9, v9, v11
+; VI-NEXT: v_perm_b32 v11, v40, v21, s4
+; VI-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; VI-NEXT: v_add_u32_e32 v11, vcc, 24, v0
; VI-NEXT: buffer_store_dword v9, v11, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v9, v10, v55, s4
; VI-NEXT: v_perm_b32 v10, v53, v54, s4
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_add_u32_e32 v10, vcc, 28, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v9, v51, v20, s4
; VI-NEXT: v_perm_b32 v7, v7, v52, s4
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_or_b32_e32 v7, v7, v9
+; VI-NEXT: v_perm_b32 v9, v51, v20, s4
+; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, 32, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v7, v8, v50, s4
; VI-NEXT: v_perm_b32 v8, v48, v49, s4
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 36, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v7, v38, v19, s4
; VI-NEXT: v_perm_b32 v5, v5, v39, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v5, v5, v7
+; VI-NEXT: v_perm_b32 v7, v38, v19, s4
+; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, 40, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v6, v37, s4
; VI-NEXT: v_perm_b32 v6, v35, v36, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 44, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
@@ -25573,28 +25409,24 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v5, v33, v5, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v3, v3, v5
+; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; VI-NEXT: v_add_u32_e32 v5, vcc, 48, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v3, v4, v32, s4
; VI-NEXT: v_perm_b32 v4, v30, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v3, v28, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v27, s4
; VI-NEXT: v_perm_b32 v2, v25, v26, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -25905,65 +25737,53 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v21, s14
; GFX9-NEXT: .LBB49_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v19, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v18
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -25988,26 +25808,22 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -26250,71 +26066,55 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
; GFX11-NEXT: .LBB49_5: ; %end
-; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
-; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
+; GFX11-NEXT: v_lshl_or_b32 v82, v24, 16, v13
; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v81, v86, 16, v18
; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
-; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
+; GFX11-NEXT: v_lshl_or_b32 v83, v84, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v22, 16, v9
; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
+; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v80, v25, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
+; GFX11-NEXT: v_lshl_or_b32 v12, v18, 16, v12
; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
+; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v17, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v9, v18, 16, v5
; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
-; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
-; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
+; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v17, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v15, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v4, v18, 16, v16
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
@@ -27044,44 +26844,33 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB50_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v52, v51, s6
-; VI-NEXT: v_perm_b32 v3, v48, v39, s6
; VI-NEXT: v_perm_b32 v0, v54, v53, s6
+; VI-NEXT: v_perm_b32 v1, v52, v51, s6
; VI-NEXT: v_perm_b32 v2, v50, v49, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_perm_b32 v3, v36, v35, s6
+; VI-NEXT: v_perm_b32 v3, v48, v39, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_perm_b32 v2, v38, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v36, v35, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v34, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v32, v31, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -27121,11 +26910,9 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -27133,20 +26920,19 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr24
@@ -27182,8 +26968,7 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -27206,10 +26991,9 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
@@ -28463,9 +28247,9 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
@@ -28478,13 +28262,12 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
@@ -28508,28 +28291,27 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
@@ -28544,12 +28326,11 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
@@ -29129,96 +28910,80 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s75
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s73
-; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s63
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s61
-; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s59
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s57
-; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s47
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s45
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s13
-; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s11
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s9
-; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s7
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s8, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v24, v22, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v24, v22, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
-; VI-NEXT: v_or_b32_e32 v15, v35, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -29440,98 +29205,81 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
+; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
+; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -29740,74 +29488,63 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-TRUE16-NEXT: .LBB51_2: ; %cmp.true
@@ -29822,18 +29559,17 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -30024,74 +29760,63 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-FAKE16-NEXT: .LBB51_2: ; %cmp.true
@@ -30106,18 +29831,17 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -37991,102 +37715,86 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v1, v1, v21
+; VI-NEXT: v_lshl_or_b32 v1, v21, 16, v1
+; VI-NEXT: v_perm_b32 v2, v2, v29, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
-; VI-NEXT: v_perm_b32 v2, v2, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v59, v58, s4
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v59, v58, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v56, v26, s4
; VI-NEXT: v_perm_b32 v1, v5, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v56, v26, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v46, v45, s4
; VI-NEXT: v_perm_b32 v1, v6, v47, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v46, v45, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v43, v25, s4
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v43, v25, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v41, v40, s4
; VI-NEXT: v_perm_b32 v1, v8, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v41, v40, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v54, v22, s4
; VI-NEXT: v_perm_b32 v1, v9, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v54, v22, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v52, v51, s4
; VI-NEXT: v_perm_b32 v1, v10, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v52, v51, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v49, v19, s4
; VI-NEXT: v_perm_b32 v1, v11, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v49, v19, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v39, v38, s4
; VI-NEXT: v_perm_b32 v1, v12, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v39, v38, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v36, v18, s4
; VI-NEXT: v_perm_b32 v1, v13, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v36, v18, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v34, v33, s4
; VI-NEXT: v_perm_b32 v1, v14, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v34, v33, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -39444,132 +39152,116 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; VI-NEXT: s_lshr_b32 s66, s16, 16
; VI-NEXT: s_lshr_b32 s67, s16, 8
; VI-NEXT: .LBB69_3: ; %end
+; VI-NEXT: v_mov_b32_e32 v1, s67
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s44
-; VI-NEXT: v_mov_b32_e32 v1, s67
-; VI-NEXT: v_perm_b32 v3, s66, v3, v2
; VI-NEXT: v_perm_b32 v1, s16, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
-; VI-NEXT: v_mov_b32_e32 v3, s55
+; VI-NEXT: v_perm_b32 v3, s66, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s65
-; VI-NEXT: v_perm_b32 v3, s64, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s55
; VI-NEXT: v_perm_b32 v1, s17, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s64, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s42
; VI-NEXT: v_mov_b32_e32 v1, s54
-; VI-NEXT: v_perm_b32 v3, s53, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s42
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s53, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s50
; VI-NEXT: v_mov_b32_e32 v1, s52
-; VI-NEXT: v_perm_b32 v3, s51, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s50
; VI-NEXT: v_perm_b32 v1, s19, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s51, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s40
; VI-NEXT: v_mov_b32_e32 v1, s49
-; VI-NEXT: v_perm_b32 v3, s48, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s40
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s48, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s37
; VI-NEXT: v_mov_b32_e32 v1, s39
-; VI-NEXT: v_perm_b32 v3, s38, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s37
; VI-NEXT: v_perm_b32 v1, s21, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s38, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_mov_b32_e32 v1, s36
-; VI-NEXT: v_perm_b32 v3, s35, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_perm_b32 v1, s22, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s35, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s30
; VI-NEXT: v_mov_b32_e32 v1, s34
-; VI-NEXT: v_perm_b32 v3, s31, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s30
; VI-NEXT: v_perm_b32 v1, s23, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s31, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_mov_b32_e32 v1, s91
-; VI-NEXT: v_perm_b32 v3, s90, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_perm_b32 v1, s24, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s90, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s79
; VI-NEXT: v_mov_b32_e32 v1, s89
-; VI-NEXT: v_perm_b32 v3, s88, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s79
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s88, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_mov_b32_e32 v1, s78
-; VI-NEXT: v_perm_b32 v3, s77, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_perm_b32 v1, s26, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s77, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_mov_b32_e32 v1, s76
-; VI-NEXT: v_perm_b32 v3, s75, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_perm_b32 v1, s27, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s75, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_mov_b32_e32 v1, s73
-; VI-NEXT: v_perm_b32 v3, s72, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_perm_b32 v1, s28, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s72, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s61
; VI-NEXT: v_mov_b32_e32 v1, s63
-; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s61
; VI-NEXT: v_perm_b32 v1, s29, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_mov_b32_e32 v1, s60
-; VI-NEXT: v_perm_b32 v3, s59, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_perm_b32 v1, s4, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s59, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_perm_b32 v1, s5, v1, v2
; VI-NEXT: v_perm_b32 v2, s57, v3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: v_readlane_b32 s30, v4, 18
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -39791,118 +39483,102 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX9-NEXT: s_lshr_b32 s54, s16, 16
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
; GFX9-NEXT: .LBB69_3: ; %end
+; GFX9-NEXT: v_mov_b32_e32 v1, s55
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s44
-; GFX9-NEXT: v_mov_b32_e32 v1, s55
-; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s51
+; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s53
-; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s51
; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s42
+; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s50
-; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s42
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s38
+; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s48
-; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s38
; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s40
+; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s37
-; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s40
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s31
+; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s35
-; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s31
; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s14
+; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s30
-; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s92
+; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s94
-; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s92
; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s12
+; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s91
-; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s79
+; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s89
-; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s79
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
+; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: v_mov_b32_e32 v1, s78
-; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_perm_b32 v1, s26, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s74
+; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_mov_b32_e32 v1, s76
-; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: v_perm_b32 v1, s27, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_mov_b32_e32 v1, s73
-; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_perm_b32 v1, s28, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s61
+; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s61
; GFX9-NEXT: v_perm_b32 v1, s29, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
+; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v1, s60
-; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_perm_b32 v1, s4, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v1, s58
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_perm_b32 v1, s5, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s57, v3, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_readlane_b32 s30, v4, 14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_readlane_b32 s31, v4, 15
@@ -40112,72 +39788,59 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
; GFX11-NEXT: .LBB69_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v12, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
-; GFX11-NEXT: v_readlane_b32 s34, v23, 0
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
-; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_perm_b32 v1, s0, s48, v12
+; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
; GFX11-NEXT: v_perm_b32 v3, s1, s38, v12
+; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
+; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
; GFX11-NEXT: v_perm_b32 v6, s2, s35, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_perm_b32 v8, s30, vcc_hi, v12
-; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
-; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v6, v5
-; GFX11-NEXT: v_perm_b32 v5, s93, s92, v12
+; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
+; GFX11-NEXT: v_lshl_or_b32 v3, v5, 16, v6
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s16, s94, v12
+; GFX11-NEXT: v_perm_b32 v5, s93, s92, v12
; GFX11-NEXT: v_perm_b32 v8, s90, s12, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
+; GFX11-NEXT: v_perm_b32 v6, s16, s94, v12
+; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
; GFX11-NEXT: v_perm_b32 v13, s18, s89, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-NEXT: v_or_b32_e32 v5, v6, v9
; GFX11-NEXT: v_perm_b32 v9, s88, s78, v12
; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT: v_perm_b32 v10, s77, s10, v12
-; GFX11-NEXT: v_perm_b32 v11, s75, s74, v12
-; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
-; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-NEXT: v_or_b32_e32 v7, v13, v8
; GFX11-NEXT: v_perm_b32 v8, s19, s79, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_perm_b32 v10, s77, s10, v12
+; GFX11-NEXT: v_perm_b32 v11, s75, s74, v12
; GFX11-NEXT: v_perm_b32 v13, s20, s76, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v15, s21, s73, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
; GFX11-NEXT: v_perm_b32 v16, s22, s63, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v9, v13, v10
+; GFX11-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v9, v10, 16, v13
; GFX11-NEXT: v_perm_b32 v13, s62, s61, v12
-; GFX11-NEXT: v_or_b32_e32 v10, v15, v11
-; GFX11-NEXT: v_or_b32_e32 v11, v16, v14
+; GFX11-NEXT: v_lshl_or_b32 v10, v11, 16, v15
+; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
+; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v16
; GFX11-NEXT: v_perm_b32 v14, s59, s6, v12
+; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
; GFX11-NEXT: v_perm_b32 v17, s57, s56, v12
; GFX11-NEXT: v_perm_b32 v18, s46, s4, v12
-; GFX11-NEXT: v_perm_b32 v20, s44, s42, v12
-; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v19, s25, s47, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-NEXT: v_perm_b32 v20, s44, s42, v12
; GFX11-NEXT: v_perm_b32 v21, s26, s45, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-NEXT: v_perm_b32 v22, s27, s43, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT: v_or_b32_e32 v12, v15, v13
-; GFX11-NEXT: v_or_b32_e32 v13, v16, v14
-; GFX11-NEXT: v_or_b32_e32 v14, v19, v17
-; GFX11-NEXT: v_or_b32_e32 v15, v21, v18
-; GFX11-NEXT: v_or_b32_e32 v16, v22, v20
+; GFX11-NEXT: v_lshl_or_b32 v12, v13, 16, v15
+; GFX11-NEXT: v_lshl_or_b32 v13, v14, 16, v16
+; GFX11-NEXT: v_lshl_or_b32 v14, v17, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v21
+; GFX11-NEXT: v_lshl_or_b32 v16, v20, 16, v22
; GFX11-NEXT: v_readlane_b32 s30, v23, 7
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
@@ -40191,6 +39854,7 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: v_readlane_b32 s37, v23, 3
; GFX11-NEXT: v_readlane_b32 s36, v23, 2
; GFX11-NEXT: v_readlane_b32 s35, v23, 1
+; GFX11-NEXT: v_readlane_b32 s34, v23, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v23, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -40955,44 +40619,33 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB70_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v52, v51, s6
-; VI-NEXT: v_perm_b32 v3, v48, v39, s6
; VI-NEXT: v_perm_b32 v0, v54, v53, s6
+; VI-NEXT: v_perm_b32 v1, v52, v51, s6
; VI-NEXT: v_perm_b32 v2, v50, v49, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_perm_b32 v3, v36, v35, s6
+; VI-NEXT: v_perm_b32 v3, v48, v39, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_perm_b32 v2, v38, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v36, v35, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v34, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v32, v31, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -41032,11 +40685,9 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -41044,20 +40695,19 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr24
@@ -41093,8 +40743,7 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -41117,10 +40766,9 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
@@ -42374,9 +42022,9 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
@@ -42389,13 +42037,12 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
@@ -42419,28 +42066,27 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
@@ -42455,12 +42101,11 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
@@ -43040,96 +42685,80 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB71_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s75
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s73
-; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s63
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s61
-; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s59
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s57
-; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s47
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s45
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s13
-; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s11
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s9
-; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s7
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s8, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v24, v22, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v24, v22, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
-; VI-NEXT: v_or_b32_e32 v15, v35, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; VI-NEXT: s_cbranch_execnz .LBB71_3
; VI-NEXT: .LBB71_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -43351,98 +42980,81 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
+; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
+; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -43651,74 +43263,63 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-TRUE16-NEXT: .LBB71_2: ; %cmp.true
@@ -43733,18 +43334,17 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -43935,74 +43535,63 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-FAKE16-NEXT: .LBB71_2: ; %cmp.true
@@ -44017,18 +43606,17 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -51181,102 +50769,86 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v1, v1, v21
+; VI-NEXT: v_lshl_or_b32 v1, v21, 16, v1
+; VI-NEXT: v_perm_b32 v2, v2, v29, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
-; VI-NEXT: v_perm_b32 v2, v2, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v59, v58, s4
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v59, v58, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v56, v26, s4
; VI-NEXT: v_perm_b32 v1, v5, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v56, v26, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v46, v45, s4
; VI-NEXT: v_perm_b32 v1, v6, v47, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v46, v45, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v43, v25, s4
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v43, v25, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v41, v40, s4
; VI-NEXT: v_perm_b32 v1, v8, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v41, v40, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v54, v22, s4
; VI-NEXT: v_perm_b32 v1, v9, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v54, v22, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v52, v51, s4
; VI-NEXT: v_perm_b32 v1, v10, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v52, v51, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v49, v19, s4
; VI-NEXT: v_perm_b32 v1, v11, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v49, v19, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v39, v38, s4
; VI-NEXT: v_perm_b32 v1, v12, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v39, v38, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v36, v18, s4
; VI-NEXT: v_perm_b32 v1, v13, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v36, v18, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v34, v33, s4
; VI-NEXT: v_perm_b32 v1, v14, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v34, v33, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -52771,61 +52343,51 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v24, v57, v24, s4
; VI-NEXT: v_perm_b32 v15, v15, v58, s4
+; VI-NEXT: v_lshl_or_b32 v15, v24, 16, v15
; VI-NEXT: v_perm_b32 v16, v16, v18, s4
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24
-; VI-NEXT: v_or_b32_e32 v15, v15, v18
; VI-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v15, v17, v62, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v15, v16, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
; VI-NEXT: v_add_u32_e32 v16, vcc, 4, v0
; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v15, v44, v23, s4
; VI-NEXT: v_perm_b32 v13, v13, v45, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v13, v13, v15
+; VI-NEXT: v_lshl_or_b32 v13, v15, 16, v13
; VI-NEXT: v_add_u32_e32 v15, vcc, 8, v0
; VI-NEXT: buffer_store_dword v13, v15, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v13, v14, v61, s4
; VI-NEXT: v_perm_b32 v14, v60, v59, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_add_u32_e32 v14, vcc, 12, v0
; VI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v13, v55, v22, s4
; VI-NEXT: v_perm_b32 v11, v11, v40, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_or_b32_e32 v11, v11, v13
+; VI-NEXT: v_perm_b32 v13, v55, v22, s4
+; VI-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; VI-NEXT: v_add_u32_e32 v13, vcc, 16, v0
; VI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v11, v12, v56, s4
; VI-NEXT: v_perm_b32 v12, v47, v46, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_add_u32_e32 v12, vcc, 20, v0
; VI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v11, v50, v21, s4
; VI-NEXT: v_perm_b32 v7, v7, v52, s4
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; VI-NEXT: v_or_b32_e32 v7, v7, v11
+; VI-NEXT: v_perm_b32 v11, v50, v21, s4
+; VI-NEXT: v_lshl_or_b32 v7, v11, 16, v7
; VI-NEXT: v_add_u32_e32 v11, vcc, 24, v0
; VI-NEXT: buffer_store_dword v7, v11, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v7, v8, v43, s4
; VI-NEXT: v_perm_b32 v8, v42, v41, s4
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_add_u32_e32 v8, vcc, 28, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v7, v39, v20, s4
; VI-NEXT: v_perm_b32 v5, v5, v49, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v5, v5, v7
+; VI-NEXT: v_perm_b32 v7, v39, v20, s4
+; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; VI-NEXT: v_add_u32_e32 v7, vcc, 32, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v6, v54, s4
; VI-NEXT: v_perm_b32 v6, v53, v51, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 36, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
@@ -52854,28 +52416,24 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v5, v35, v5, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v3, v3, v5
+; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; VI-NEXT: v_add_u32_e32 v5, vcc, 40, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v3, v4, v48, s4
; VI-NEXT: v_perm_b32 v4, v38, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v3, v30, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v34, s4
; VI-NEXT: v_perm_b32 v2, v33, v32, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
@@ -52883,14 +52441,12 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; VI-NEXT: v_perm_b32 v1, v9, v28, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v27, v25, s4
; VI-NEXT: v_perm_b32 v1, v10, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v27, v25, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -53199,55 +52755,45 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: .LBB85_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v24, v57, v24, s4
-; GFX9-NEXT: v_perm_b32 v15, v15, v59, s4
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
; GFX9-NEXT: v_perm_b32 v18, v56, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v24
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v23
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v17, v62, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_perm_b32 v13, v13, v47, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v18, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v61, s4
; GFX9-NEXT: v_perm_b32 v14, v60, v58, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v13, v42, v22, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v43, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v13
+; GFX9-NEXT: v_perm_b32 v13, v42, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v13, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v9, v10, v46, s4
; GFX9-NEXT: v_perm_b32 v10, v45, v44, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v9, v50, v21, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v50, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v7, v8, v41, s4
; GFX9-NEXT: v_perm_b32 v8, v40, v55, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_perm_b32 v24, v57, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v15, v59, s4
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v48, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v24, 16, v15
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v17, v62, s4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v5, v6, v54, s4
; GFX9-NEXT: v_perm_b32 v6, v53, v52, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -53272,39 +52818,33 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v35, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v3, v4, v49, s4
; GFX9-NEXT: v_perm_b32 v4, v39, v37, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v30, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v1, v2, v34, s4
; GFX9-NEXT: v_perm_b32 v2, v33, v32, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v1, v11, v27, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v26, v2, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-NEXT: v_perm_b32 v2, v28, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v12, v29, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, v28, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -53540,70 +53080,56 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v87, s45 :: v_dual_mov_b32 v86, s43
; GFX11-NEXT: .LBB85_5: ; %end
; GFX11-NEXT: v_perm_b32 v26, v69, v26, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v17, v17, v68, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v27, v82, v27, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v82, v96, v87, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v17, v17, v68, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v21, v21, v81, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_perm_b32 v68, v85, v84, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v54, v24, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v22, v86, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v82
-; GFX11-NEXT: v_or_b32_e32 v86, v17, v26
+; GFX11-NEXT: v_perm_b32 v68, v85, v84, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v86, v26, 16, v17
; GFX11-NEXT: v_perm_b32 v17, v18, v83, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v64, v25, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v84, v21, v27
-; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v68
+; GFX11-NEXT: v_perm_b32 v24, v54, v24, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v11, v11, v53, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_or_b32_e32 v85, v22, v69
+; GFX11-NEXT: v_lshl_or_b32 v84, v27, 16, v21
+; GFX11-NEXT: v_lshl_or_b32 v85, v82, 16, v22
+; GFX11-NEXT: v_perm_b32 v18, v64, v25, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v80, v71, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v15, v15, v55, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v87, v17, v21
-; GFX11-NEXT: v_or_b32_e32 v17, v11, v24
-; GFX11-NEXT: v_perm_b32 v11, v12, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v12, v49, v23, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v16, v16, v70, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
-; GFX11-NEXT: v_perm_b32 v18, v67, v65, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v21, v52, v51, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v19, v37, v19, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v87, v68, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v17, v24, 16, v11
+; GFX11-NEXT: v_perm_b32 v11, v12, v66, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v49, v23, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v7, v7, v39, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v22
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v15
+; GFX11-NEXT: v_perm_b32 v18, v67, v65, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v16, v22, 16, v16
; GFX11-NEXT: v_perm_b32 v8, v8, v50, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v21
; GFX11-NEXT: v_perm_b32 v5, v5, v35, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT: v_or_b32_e32 v21, v7, v12
+; GFX11-NEXT: v_lshl_or_b32 v21, v12, 16, v7
; GFX11-NEXT: v_perm_b32 v7, v48, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v18, v11, v18
+; GFX11-NEXT: v_perm_b32 v6, v6, v36, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v11
; GFX11-NEXT: v_or_b32_e32 v22, v8, v22
; GFX11-NEXT: v_or_b32_e32 v23, v5, v19
; GFX11-NEXT: v_perm_b32 v5, v31, v13, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v30, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v8, v34, v33, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v9, v14, v9, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v11, v29, v28, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v36, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v3, v3, v30, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v32, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_perm_b32 v11, v29, v28, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v1, v10, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_perm_b32 v12, v2, v20, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_or_b32_e32 v24, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v8
-; GFX11-NEXT: v_or_b32_e32 v3, v10, v9
-; GFX11-NEXT: v_or_b32_e32 v4, v12, v11
+; GFX11-NEXT: v_lshl_or_b32 v24, v7, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v8, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v9, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v4, v11, 16, v12
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[84:87], off
@@ -54333,44 +53859,33 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB86_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v52, v51, s6
-; VI-NEXT: v_perm_b32 v3, v48, v39, s6
; VI-NEXT: v_perm_b32 v0, v54, v53, s6
+; VI-NEXT: v_perm_b32 v1, v52, v51, s6
; VI-NEXT: v_perm_b32 v2, v50, v49, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_perm_b32 v3, v36, v35, s6
+; VI-NEXT: v_perm_b32 v3, v48, v39, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_perm_b32 v2, v38, v37, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v36, v35, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_perm_b32 v3, v34, v33, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v32, v31, s6
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_perm_b32 v4, v16, v17, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -54410,11 +53925,9 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -54422,20 +53935,19 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr24
@@ -54471,8 +53983,7 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -54495,10 +54006,9 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
@@ -55752,9 +55262,9 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
@@ -55767,13 +55277,12 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
@@ -55797,28 +55306,27 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
@@ -55833,12 +55341,11 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
@@ -56418,96 +55925,80 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB87_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s75
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s76, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s73
-; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s63
; VI-NEXT: v_perm_b32 v4, s74, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s72, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s61
-; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s59
; VI-NEXT: v_perm_b32 v5, s62, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s60, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s57
-; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s47
; VI-NEXT: v_perm_b32 v6, s58, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s56, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s45
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_perm_b32 v7, s46, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v8, s42, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s40, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s13
-; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s11
; VI-NEXT: v_perm_b32 v9, s14, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s12, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s9
-; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s7
; VI-NEXT: v_perm_b32 v10, s10, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s8, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v24, v22, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s6, v26, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v24, v22, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
-; VI-NEXT: v_or_b32_e32 v15, v35, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; VI-NEXT: s_cbranch_execnz .LBB87_3
; VI-NEXT: .LBB87_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -56729,98 +56220,81 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
+; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
+; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
+; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -57029,74 +56503,63 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-TRUE16-NEXT: .LBB87_2: ; %cmp.true
@@ -57111,18 +56574,17 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -57313,74 +56775,63 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-FAKE16-NEXT: .LBB87_2: ; %cmp.true
@@ -57395,18 +56846,17 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -64395,30 +63845,22 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB96_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v17, 3
-; VI-NEXT: v_add_u16_sdwa v28, v12, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v33, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v26, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v29, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v30, v10, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v35, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v45, 3, v12
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
+; VI-NEXT: v_add_u16_sdwa v28, v12, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v47, 3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
+; VI-NEXT: v_add_u16_sdwa v33, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v62, 3, v16
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v26
+; VI-NEXT: v_add_u16_sdwa v26, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v51, 3, v15
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v29
-; VI-NEXT: v_add_u16_sdwa v32, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v37, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v29, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v41, 3, v10
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v30
+; VI-NEXT: v_add_u16_sdwa v30, v10, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v43, 3, v9
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
-; VI-NEXT: v_or_b32_e32 v12, v45, v12
-; VI-NEXT: v_or_b32_e32 v11, v47, v11
-; VI-NEXT: v_or_b32_e32 v16, v62, v16
-; VI-NEXT: v_or_b32_e32 v15, v51, v15
+; VI-NEXT: v_add_u16_sdwa v35, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v12, v28, 16, v45
+; VI-NEXT: v_lshl_or_b32 v11, v33, 16, v47
+; VI-NEXT: v_lshl_or_b32 v16, v26, 16, v62
+; VI-NEXT: v_lshl_or_b32 v15, v29, 16, v51
; VI-NEXT: v_add_u16_sdwa v38, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v49, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v36, v4, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -64426,48 +63868,40 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_sdwa v34, v6, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v39, v5, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v50, 3, v8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v32
+; VI-NEXT: v_add_u16_sdwa v32, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v52, 3, v7
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
-; VI-NEXT: v_or_b32_e32 v10, v41, v10
-; VI-NEXT: v_or_b32_e32 v9, v43, v9
+; VI-NEXT: v_add_u16_sdwa v37, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v10, v30, 16, v41
+; VI-NEXT: v_lshl_or_b32 v9, v35, 16, v43
; VI-NEXT: v_add_u16_sdwa v27, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v31, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
; VI-NEXT: v_add_u16_e32 v59, 3, v6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
; VI-NEXT: v_add_u16_e32 v61, 3, v5
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
-; VI-NEXT: v_or_b32_e32 v8, v50, v8
-; VI-NEXT: v_or_b32_e32 v7, v52, v7
+; VI-NEXT: v_lshl_or_b32 v8, v32, 16, v50
+; VI-NEXT: v_lshl_or_b32 v7, v37, 16, v52
; VI-NEXT: v_add_u16_e32 v58, 3, v14
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v27
; VI-NEXT: v_add_u16_e32 v60, 3, v13
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
; VI-NEXT: v_add_u16_e32 v46, 3, v4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
; VI-NEXT: v_add_u16_e32 v56, 3, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
-; VI-NEXT: v_or_b32_e32 v6, v59, v6
-; VI-NEXT: v_or_b32_e32 v5, v61, v5
-; VI-NEXT: v_or_b32_e32 v14, v58, v14
-; VI-NEXT: v_or_b32_e32 v13, v60, v13
+; VI-NEXT: v_lshl_or_b32 v6, v34, 16, v59
+; VI-NEXT: v_lshl_or_b32 v5, v39, 16, v61
+; VI-NEXT: v_lshl_or_b32 v14, v27, 16, v58
+; VI-NEXT: v_lshl_or_b32 v13, v31, 16, v60
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
; VI-NEXT: v_add_u16_e32 v53, 3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v38
; VI-NEXT: v_add_u16_e32 v55, 3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v49
-; VI-NEXT: v_or_b32_e32 v4, v46, v4
-; VI-NEXT: v_or_b32_e32 v3, v56, v3
+; VI-NEXT: v_lshl_or_b32 v4, v36, 16, v46
+; VI-NEXT: v_lshl_or_b32 v3, v48, 16, v56
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[13:14]
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v13
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
-; VI-NEXT: v_or_b32_e32 v2, v53, v2
-; VI-NEXT: v_or_b32_e32 v1, v55, v1
+; VI-NEXT: v_lshl_or_b32 v2, v38, 16, v53
+; VI-NEXT: v_lshl_or_b32 v1, v49, 16, v55
; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
@@ -64515,67 +63949,58 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v1, v49, v24, s4
; VI-NEXT: v_perm_b32 v2, v55, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
-; VI-NEXT: v_perm_b32 v2, v38, v63, s4
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v53, v44, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v38, v63, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v48, v23, s4
; VI-NEXT: v_perm_b32 v2, v56, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v46, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v39, v22, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v61, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v34, v40, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v59, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v37, v21, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v52, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v50, v17, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v32, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v35, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v43, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
@@ -64584,24 +64009,21 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v41, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v30, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v33, v19, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v47, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v28, v54, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v45, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
@@ -64610,8 +64032,7 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v31, v2, s4
; VI-NEXT: v_perm_b32 v1, v60, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
@@ -64620,8 +64041,7 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v58, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v27, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -64630,17 +64050,15 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v29, v2, s4
; VI-NEXT: v_perm_b32 v1, v51, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v26, v25, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v62, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -66222,132 +65640,116 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; VI-NEXT: s_lshr_b32 s66, s16, 16
; VI-NEXT: s_lshr_b32 s67, s16, 8
; VI-NEXT: .LBB97_3: ; %end
+; VI-NEXT: v_mov_b32_e32 v1, s67
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s44
-; VI-NEXT: v_mov_b32_e32 v1, s67
-; VI-NEXT: v_perm_b32 v3, s66, v3, v2
; VI-NEXT: v_perm_b32 v1, s16, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
-; VI-NEXT: v_mov_b32_e32 v3, s55
+; VI-NEXT: v_perm_b32 v3, s66, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s65
-; VI-NEXT: v_perm_b32 v3, s64, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s55
; VI-NEXT: v_perm_b32 v1, s17, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s64, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s42
; VI-NEXT: v_mov_b32_e32 v1, s54
-; VI-NEXT: v_perm_b32 v3, s53, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s42
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s53, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s50
; VI-NEXT: v_mov_b32_e32 v1, s52
-; VI-NEXT: v_perm_b32 v3, s51, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s50
; VI-NEXT: v_perm_b32 v1, s19, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s51, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s40
; VI-NEXT: v_mov_b32_e32 v1, s49
-; VI-NEXT: v_perm_b32 v3, s48, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s40
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s48, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s37
; VI-NEXT: v_mov_b32_e32 v1, s39
-; VI-NEXT: v_perm_b32 v3, s38, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s37
; VI-NEXT: v_perm_b32 v1, s21, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s38, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_mov_b32_e32 v1, s36
-; VI-NEXT: v_perm_b32 v3, s35, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_perm_b32 v1, s22, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s35, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s30
; VI-NEXT: v_mov_b32_e32 v1, s34
-; VI-NEXT: v_perm_b32 v3, s31, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s30
; VI-NEXT: v_perm_b32 v1, s23, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s31, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_mov_b32_e32 v1, s91
-; VI-NEXT: v_perm_b32 v3, s90, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_perm_b32 v1, s24, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s90, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s79
; VI-NEXT: v_mov_b32_e32 v1, s89
-; VI-NEXT: v_perm_b32 v3, s88, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s79
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s88, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_mov_b32_e32 v1, s78
-; VI-NEXT: v_perm_b32 v3, s77, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_perm_b32 v1, s26, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s77, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_mov_b32_e32 v1, s76
-; VI-NEXT: v_perm_b32 v3, s75, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_perm_b32 v1, s27, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s75, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_mov_b32_e32 v1, s73
-; VI-NEXT: v_perm_b32 v3, s72, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_perm_b32 v1, s28, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s72, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s61
; VI-NEXT: v_mov_b32_e32 v1, s63
-; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s61
; VI-NEXT: v_perm_b32 v1, s29, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s62, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_mov_b32_e32 v1, s60
-; VI-NEXT: v_perm_b32 v3, s59, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_perm_b32 v1, s4, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s59, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_perm_b32 v1, s5, v1, v2
; VI-NEXT: v_perm_b32 v2, s57, v3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: v_readlane_b32 s30, v4, 18
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -66713,65 +66115,53 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v21, s14
; GFX9-NEXT: .LBB97_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v19, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v18
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -66796,26 +66186,22 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -67058,71 +66444,55 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
; GFX11-NEXT: .LBB97_5: ; %end
-; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
-; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
+; GFX11-NEXT: v_lshl_or_b32 v82, v24, 16, v13
; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v81, v86, 16, v18
; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
-; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
+; GFX11-NEXT: v_lshl_or_b32 v83, v84, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v22, 16, v9
; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
+; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v80, v25, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
+; GFX11-NEXT: v_lshl_or_b32 v12, v18, 16, v12
; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
+; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v17, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v9, v18, 16, v5
; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
-; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
-; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
+; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v17, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v15, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v4, v18, 16, v16
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
@@ -68029,28 +67399,17 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_perm_b32 v9, v44, v42, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v57, v46, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v11, v58, v47, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v33, v62, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v35, v34, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v49, v48, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v51, v50, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; kill: killed $vgpr18
; VI-NEXT: ; implicit-def: $vgpr18
@@ -68083,16 +67442,14 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -68101,8 +67458,7 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -68110,37 +67466,35 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v17, v4, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v16, v4, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v61, v60, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v59, v56, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v31, v63, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_perm_b32 v14, v39, v38, s6
-; VI-NEXT: v_perm_b32 v16, v32, v54, s6
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: v_perm_b32 v15, v53, v52, s6
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_perm_b32 v16, v32, v54, s6
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr16
; VI-NEXT: ; implicit-def: $vgpr16
@@ -70470,96 +69824,80 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB99_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s45
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s57, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s45
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s47
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s57, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_perm_b32 v5, s59, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s47
; VI-NEXT: v_perm_b32 v4, s56, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s60
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s59, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_perm_b32 v6, s63, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s60
; VI-NEXT: v_perm_b32 v5, s61, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s72
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s63, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s62
-; VI-NEXT: v_perm_b32 v7, s75, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s72
; VI-NEXT: v_perm_b32 v6, s73, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s42
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s75, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s74
-; VI-NEXT: v_perm_b32 v8, s43, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s42
; VI-NEXT: v_perm_b32 v7, s76, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s7
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s43, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s6
-; VI-NEXT: v_perm_b32 v9, s9, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s7
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s9, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s8
-; VI-NEXT: v_perm_b32 v10, s13, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s10
; VI-NEXT: v_perm_b32 v9, s11, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s14
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s13, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s12
-; VI-NEXT: v_perm_b32 v12, s40, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s14
; VI-NEXT: v_perm_b32 v10, s15, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s40, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v18, v17, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s41, v16, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v18, v17, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v25, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v22, v19, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v30, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v27, v21, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v32, v26, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v29, v23, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v34, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v33, v28, s4
-; VI-NEXT: v_or_b32_e32 v15, v35, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; VI-NEXT: s_cbranch_execnz .LBB99_3
; VI-NEXT: .LBB99_2: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v34
@@ -71113,16 +70451,14 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB99_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
@@ -71143,53 +70479,52 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v34, 8, v10
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v50, 8, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v48, 8, v14
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v31, 8, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v32, 8, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v35, 8, v16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB99_3
; GFX11-TRUE16-NEXT: .LBB99_2: ; %cmp.true
@@ -71400,23 +70735,23 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
+; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
+; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
@@ -71427,35 +70762,29 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v34, 8, s79
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v31, 8, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v35, 8, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v38, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v33, 8, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 8, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
@@ -77058,81 +76387,65 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB104_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v17, 0x200
+; VI-NEXT: v_add_f16_sdwa v29, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
+; VI-NEXT: v_add_f16_sdwa v32, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
+; VI-NEXT: v_add_f16_sdwa v30, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
+; VI-NEXT: v_add_f16_sdwa v34, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
+; VI-NEXT: v_lshl_or_b32 v43, v29, 16, v16
+; VI-NEXT: v_lshl_or_b32 v42, v32, 16, v15
; VI-NEXT: v_add_f16_sdwa v49, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v49
-; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: v_add_f16_sdwa v52, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v28, v2, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v52
-; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v39, v4, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v27, v1, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v39
-; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_add_f16_sdwa v51, v3, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v23, v4, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v51
-; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
; VI-NEXT: v_add_f16_sdwa v37, v6, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v22, v3, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v37
-; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_add_f16_sdwa v50, v5, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v54, v6, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v50
-; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
; VI-NEXT: v_add_f16_sdwa v35, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v53, v5, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v35
-; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
; VI-NEXT: v_add_f16_sdwa v48, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v25, v8, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v48
-; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_add_f16_sdwa v33, v10, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v24, v7, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v33
-; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
; VI-NEXT: v_add_f16_sdwa v38, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v46, v10, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v38
-; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
; VI-NEXT: v_add_f16_sdwa v31, v12, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v45, v9, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31
-; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
; VI-NEXT: v_add_f16_sdwa v36, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v21, v12, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v36
-; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
-; VI-NEXT: v_add_f16_sdwa v30, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v20, v11, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30
-; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
-; VI-NEXT: v_add_f16_sdwa v34, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v41, v14, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v34
-; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
-; VI-NEXT: v_add_f16_sdwa v29, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_sdwa v32, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v40, v13, v18
-; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29
-; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v32
-; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
-; VI-NEXT: v_or_b32_e32 v43, v16, v18
-; VI-NEXT: v_or_b32_e32 v42, v15, v17
+; VI-NEXT: v_lshl_or_b32 v41, v30, 16, v14
+; VI-NEXT: v_lshl_or_b32 v40, v34, 16, v13
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[42:43]
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[40:41]
+; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
+; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v43
+; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
+; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
+; VI-NEXT: v_lshl_or_b32 v21, v31, 16, v12
+; VI-NEXT: v_lshl_or_b32 v20, v36, 16, v11
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v42
+; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
+; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
+; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
+; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
+; VI-NEXT: v_lshl_or_b32 v46, v33, 16, v10
+; VI-NEXT: v_lshl_or_b32 v45, v38, 16, v9
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v20
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[20:21]
+; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
+; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
+; VI-NEXT: v_lshl_or_b32 v23, v39, 16, v4
+; VI-NEXT: v_lshl_or_b32 v22, v51, 16, v3
+; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
+; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
+; VI-NEXT: v_lshl_or_b32 v25, v35, 16, v8
+; VI-NEXT: v_lshl_or_b32 v24, v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v41
; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v21
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[45:46]
+; VI-NEXT: v_lshl_or_b32 v28, v49, 16, v2
+; VI-NEXT: v_lshl_or_b32 v27, v52, 16, v1
+; VI-NEXT: v_lshl_or_b32 v54, v37, 16, v6
+; VI-NEXT: v_lshl_or_b32 v53, v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v46
; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v25
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v24
@@ -77161,102 +76474,86 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v22, v52, v22, s4
; VI-NEXT: v_perm_b32 v1, v1, v26, s4
-; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; VI-NEXT: v_or_b32_e32 v1, v1, v22
+; VI-NEXT: v_lshl_or_b32 v1, v22, 16, v1
+; VI-NEXT: v_perm_b32 v2, v2, v63, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v49, v54, s4
-; VI-NEXT: v_perm_b32 v2, v2, v63, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v51, v21, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v39, v53, s4
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v39, v53, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v50, v25, s4
; VI-NEXT: v_perm_b32 v1, v5, v58, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v50, v25, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v37, v61, s4
; VI-NEXT: v_perm_b32 v1, v6, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v37, v61, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v48, v24, s4
; VI-NEXT: v_perm_b32 v1, v7, v47, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v48, v24, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v35, v59, s4
; VI-NEXT: v_perm_b32 v1, v8, v46, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v35, v59, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v38, v20, s4
; VI-NEXT: v_perm_b32 v1, v9, v44, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v38, v20, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v33, v56, s4
; VI-NEXT: v_perm_b32 v1, v10, v43, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v33, v56, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v36, v19, s4
; VI-NEXT: v_perm_b32 v1, v11, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v36, v19, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v31, v45, s4
; VI-NEXT: v_perm_b32 v1, v12, v41, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v31, v45, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v34, v18, s4
; VI-NEXT: v_perm_b32 v1, v13, v40, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v34, v18, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v30, v28, s4
; VI-NEXT: v_perm_b32 v1, v14, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v30, v28, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v32, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v15, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v29, v27, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -78796,99 +78093,83 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; VI-NEXT: v_mov_b32_e32 v1, 0x200
; VI-NEXT: v_add_f16_e32 v11, s6, v1
; VI-NEXT: s_lshr_b32 s6, s16, 16
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
-; VI-NEXT: v_add_f16_e32 v25, s17, v1
; VI-NEXT: v_add_f16_e32 v18, s6, v1
; VI-NEXT: s_lshr_b32 s6, s19, 16
-; VI-NEXT: v_or_b32_e32 v10, v25, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v18
-; VI-NEXT: v_add_f16_e32 v33, s16, v1
; VI-NEXT: v_add_f16_e32 v12, s6, v1
; VI-NEXT: s_lshr_b32 s6, s18, 16
-; VI-NEXT: v_or_b32_e32 v9, v33, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v12
-; VI-NEXT: v_add_f16_e32 v27, s19, v1
; VI-NEXT: v_add_f16_e32 v20, s6, v1
; VI-NEXT: s_lshr_b32 s6, s21, 16
-; VI-NEXT: v_or_b32_e32 v52, v27, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
-; VI-NEXT: v_add_f16_e32 v35, s18, v1
; VI-NEXT: v_add_f16_e32 v13, s6, v1
; VI-NEXT: s_lshr_b32 s6, s20, 16
-; VI-NEXT: v_or_b32_e32 v51, v35, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
-; VI-NEXT: v_add_f16_e32 v28, s21, v1
; VI-NEXT: v_add_f16_e32 v21, s6, v1
; VI-NEXT: s_lshr_b32 s6, s23, 16
-; VI-NEXT: v_or_b32_e32 v8, v28, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
-; VI-NEXT: v_add_f16_e32 v37, s20, v1
; VI-NEXT: v_add_f16_e32 v14, s6, v1
; VI-NEXT: s_lshr_b32 s6, s22, 16
-; VI-NEXT: v_or_b32_e32 v7, v37, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
-; VI-NEXT: v_add_f16_e32 v30, s23, v1
; VI-NEXT: v_add_f16_e32 v22, s6, v1
; VI-NEXT: s_lshr_b32 s6, s25, 16
-; VI-NEXT: v_or_b32_e32 v57, v30, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
-; VI-NEXT: v_add_f16_e32 v38, s22, v1
; VI-NEXT: v_add_f16_e32 v15, s6, v1
; VI-NEXT: s_lshr_b32 s6, s24, 16
-; VI-NEXT: v_or_b32_e32 v56, v38, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v15
-; VI-NEXT: v_add_f16_e32 v31, s25, v1
; VI-NEXT: v_add_f16_e32 v23, s6, v1
; VI-NEXT: s_lshr_b32 s6, s27, 16
-; VI-NEXT: v_or_b32_e32 v6, v31, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
-; VI-NEXT: v_add_f16_e32 v39, s24, v1
; VI-NEXT: v_add_f16_e32 v16, s6, v1
; VI-NEXT: s_lshr_b32 s6, s26, 16
-; VI-NEXT: v_or_b32_e32 v5, v39, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v16
-; VI-NEXT: v_add_f16_e32 v32, s27, v1
; VI-NEXT: v_add_f16_e32 v24, s6, v1
; VI-NEXT: s_lshr_b32 s6, s29, 16
-; VI-NEXT: v_or_b32_e32 v42, v32, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v24
-; VI-NEXT: v_add_f16_e32 v48, s26, v1
; VI-NEXT: v_add_f16_e32 v17, s6, v1
; VI-NEXT: s_lshr_b32 s6, s28, 16
-; VI-NEXT: v_or_b32_e32 v41, v48, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; VI-NEXT: v_add_f16_e32 v34, s29, v1
; VI-NEXT: v_add_f16_e32 v26, s6, v1
; VI-NEXT: s_lshr_b32 s6, s5, 16
-; VI-NEXT: v_or_b32_e32 v55, v34, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
-; VI-NEXT: v_add_f16_e32 v49, s28, v1
-; VI-NEXT: v_add_f16_e32 v19, s6, v1
; VI-NEXT: v_add_f16_e32 v36, s5, v1
; VI-NEXT: s_lshr_b32 s5, s4, 16
-; VI-NEXT: v_or_b32_e32 v54, v49, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
+; VI-NEXT: v_add_f16_e32 v19, s6, v1
; VI-NEXT: v_add_f16_e32 v29, s5, v1
-; VI-NEXT: v_or_b32_e32 v44, v36, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
; VI-NEXT: v_add_f16_e32 v50, s4, v1
-; VI-NEXT: v_or_b32_e32 v43, v50, v2
+; VI-NEXT: v_lshl_or_b32 v44, v19, 16, v36
+; VI-NEXT: v_lshl_or_b32 v43, v29, 16, v50
+; VI-NEXT: v_add_f16_e32 v25, s17, v1
+; VI-NEXT: v_add_f16_e32 v33, s16, v1
+; VI-NEXT: v_add_f16_e32 v27, s19, v1
+; VI-NEXT: v_add_f16_e32 v35, s18, v1
+; VI-NEXT: v_add_f16_e32 v28, s21, v1
+; VI-NEXT: v_add_f16_e32 v37, s20, v1
+; VI-NEXT: v_add_f16_e32 v30, s23, v1
+; VI-NEXT: v_add_f16_e32 v38, s22, v1
+; VI-NEXT: v_add_f16_e32 v31, s25, v1
+; VI-NEXT: v_add_f16_e32 v39, s24, v1
+; VI-NEXT: v_add_f16_e32 v32, s27, v1
+; VI-NEXT: v_add_f16_e32 v48, s26, v1
+; VI-NEXT: v_add_f16_e32 v34, s29, v1
+; VI-NEXT: v_add_f16_e32 v49, s28, v1
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[43:44]
+; VI-NEXT: v_lshl_or_b32 v55, v17, 16, v34
+; VI-NEXT: v_lshl_or_b32 v54, v26, 16, v49
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[54:55]
+; VI-NEXT: v_lshl_or_b32 v42, v16, 16, v32
+; VI-NEXT: v_lshl_or_b32 v41, v24, 16, v48
; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v43
+; VI-NEXT: v_lshl_or_b32 v6, v15, 16, v31
+; VI-NEXT: v_lshl_or_b32 v5, v23, 16, v39
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[41:42]
+; VI-NEXT: v_lshl_or_b32 v57, v14, 16, v30
+; VI-NEXT: v_lshl_or_b32 v56, v22, 16, v38
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v44
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v5
; VI-NEXT: v_lshrrev_b64 v[4:5], 24, v[5:6]
+; VI-NEXT: v_lshl_or_b32 v8, v13, 16, v28
+; VI-NEXT: v_lshl_or_b32 v7, v21, 16, v37
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v55
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v42
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v6
; VI-NEXT: v_lshrrev_b64 v[5:6], 24, v[56:57]
+; VI-NEXT: v_lshl_or_b32 v52, v12, 16, v27
+; VI-NEXT: v_lshl_or_b32 v51, v20, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v7
; VI-NEXT: v_lshrrev_b64 v[6:7], 24, v[7:8]
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v25
+; VI-NEXT: v_lshl_or_b32 v9, v18, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v57
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v8
; VI-NEXT: v_lshrrev_b64 v[7:8], 24, v[51:52]
@@ -79032,85 +78313,71 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v8, v18, v8, s4
; VI-NEXT: v_perm_b32 v1, v33, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v1, v1, v8
-; VI-NEXT: v_perm_b32 v8, v11, v62, s4
+; VI-NEXT: v_lshl_or_b32 v1, v8, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v25, v51, s4
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v1, v1, v8
+; VI-NEXT: v_perm_b32 v8, v11, v62, s4
+; VI-NEXT: v_lshl_or_b32 v1, v8, 16, v1
; VI-NEXT: v_add_u32_e32 v8, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v8, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v20, v7, s4
; VI-NEXT: v_perm_b32 v7, v35, v61, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v7, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v7, v12, v59, s4
; VI-NEXT: v_perm_b32 v1, v27, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v1, v1, v7
+; VI-NEXT: v_perm_b32 v7, v12, v59, s4
+; VI-NEXT: v_lshl_or_b32 v1, v7, 16, v1
; VI-NEXT: v_add_u32_e32 v7, vcc, 12, v0
-; VI-NEXT: v_perm_b32 v6, v21, v6, s4
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v37, v58, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v1, v1, v6
+; VI-NEXT: v_perm_b32 v6, v21, v6, s4
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; VI-NEXT: v_add_u32_e32 v6, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v6, v13, v56, s4
; VI-NEXT: v_perm_b32 v1, v28, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_or_b32_e32 v1, v1, v6
+; VI-NEXT: v_perm_b32 v6, v13, v56, s4
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; VI-NEXT: v_add_u32_e32 v6, vcc, 20, v0
-; VI-NEXT: v_perm_b32 v5, v22, v5, s4
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v38, v47, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v1, v1, v5
+; VI-NEXT: v_perm_b32 v5, v22, v5, s4
+; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v1
; VI-NEXT: v_add_u32_e32 v5, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v5, v14, v46, s4
; VI-NEXT: v_perm_b32 v1, v30, v45, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_or_b32_e32 v1, v1, v5
+; VI-NEXT: v_perm_b32 v5, v14, v46, s4
+; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v1
; VI-NEXT: v_add_u32_e32 v5, vcc, 28, v0
-; VI-NEXT: v_perm_b32 v4, v23, v4, s4
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v39, v44, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v1, v1, v4
+; VI-NEXT: v_perm_b32 v4, v23, v4, s4
+; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v4, v15, v43, s4
; VI-NEXT: v_perm_b32 v1, v31, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v1, v1, v4
+; VI-NEXT: v_perm_b32 v4, v15, v43, s4
+; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
-; VI-NEXT: v_perm_b32 v3, v24, v3, s4
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v48, v40, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, v24, v3, s4
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v3, v16, v41, s4
; VI-NEXT: v_perm_b32 v1, v32, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, v16, v41, s4
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
-; VI-NEXT: v_perm_b32 v2, v26, v2, s4
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v49, v54, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v26, v2, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v17, v10, s4
; VI-NEXT: v_perm_b32 v1, v34, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v17, v10, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
@@ -79139,14 +78406,12 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v29, v2, s4
; VI-NEXT: v_perm_b32 v1, v50, v1, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v19, v9, s4
; VI-NEXT: v_perm_b32 v1, v36, v52, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v19, v9, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -79458,65 +78723,53 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v21, s14
; GFX9-NEXT: .LBB105_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v19, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v18
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -79541,26 +78794,22 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -79803,71 +79052,55 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
; GFX11-NEXT: .LBB105_5: ; %end
-; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
-; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
+; GFX11-NEXT: v_lshl_or_b32 v82, v24, 16, v13
; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v81, v86, 16, v18
; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
-; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
+; GFX11-NEXT: v_lshl_or_b32 v83, v84, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v22, 16, v9
; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
+; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v80, v25, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
+; GFX11-NEXT: v_lshl_or_b32 v12, v18, 16, v12
; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
+; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v17, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v9, v18, 16, v5
; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
-; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
-; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
+; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v17, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v15, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v4, v18, 16, v16
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
@@ -80774,28 +80007,17 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_perm_b32 v9, v44, v42, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v57, v46, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v11, v58, v47, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v33, v62, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v35, v34, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v49, v48, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v51, v50, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; kill: killed $vgpr18
; VI-NEXT: ; implicit-def: $vgpr18
@@ -80828,16 +80050,14 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -80846,8 +80066,7 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -80855,37 +80074,35 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v17, v4, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v16, v4, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v61, v60, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v59, v56, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v31, v63, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_perm_b32 v14, v39, v38, s6
-; VI-NEXT: v_perm_b32 v16, v32, v54, s6
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: v_perm_b32 v15, v53, v52, s6
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_perm_b32 v16, v32, v54, s6
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr16
; VI-NEXT: ; implicit-def: $vgpr16
@@ -83215,96 +82432,80 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB107_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s45
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s57, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s45
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s47
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s57, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_perm_b32 v5, s59, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s47
; VI-NEXT: v_perm_b32 v4, s56, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s60
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s59, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_perm_b32 v6, s63, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s60
; VI-NEXT: v_perm_b32 v5, s61, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s72
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s63, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s62
-; VI-NEXT: v_perm_b32 v7, s75, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s72
; VI-NEXT: v_perm_b32 v6, s73, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s42
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s75, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s74
-; VI-NEXT: v_perm_b32 v8, s43, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s42
; VI-NEXT: v_perm_b32 v7, s76, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s7
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s43, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s6
-; VI-NEXT: v_perm_b32 v9, s9, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s7
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s9, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s8
-; VI-NEXT: v_perm_b32 v10, s13, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s10
; VI-NEXT: v_perm_b32 v9, s11, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s14
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s13, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s12
-; VI-NEXT: v_perm_b32 v12, s40, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s14
; VI-NEXT: v_perm_b32 v10, s15, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s40, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v18, v17, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s41, v16, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v18, v17, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v25, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v22, v19, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v30, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v27, v21, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v32, v26, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v29, v23, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v34, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v33, v28, s4
-; VI-NEXT: v_or_b32_e32 v15, v35, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; VI-NEXT: s_cbranch_execnz .LBB107_3
; VI-NEXT: .LBB107_2: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v34
@@ -83858,16 +83059,14 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB107_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
@@ -83888,53 +83087,52 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v34, 8, v10
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v50, 8, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v48, 8, v14
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v31, 8, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v32, 8, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v35, 8, v16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB107_3
; GFX11-TRUE16-NEXT: .LBB107_2: ; %cmp.true
@@ -84145,23 +83343,23 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
+; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
+; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
@@ -84172,35 +83370,29 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v34, 8, s79
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v31, 8, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v35, 8, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v38, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v33, 8, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 8, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
@@ -85680,102 +84872,86 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; VI-NEXT: v_or_b32_e32 v1, v1, v21
+; VI-NEXT: v_lshl_or_b32 v1, v21, 16, v1
+; VI-NEXT: v_perm_b32 v2, v2, v29, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
-; VI-NEXT: v_perm_b32 v2, v2, v29, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v59, v58, s4
; VI-NEXT: v_perm_b32 v1, v4, v60, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v59, v58, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v56, v26, s4
; VI-NEXT: v_perm_b32 v1, v5, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v56, v26, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v46, v45, s4
; VI-NEXT: v_perm_b32 v1, v6, v47, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v46, v45, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v43, v25, s4
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v43, v25, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v41, v40, s4
; VI-NEXT: v_perm_b32 v1, v8, v42, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v41, v40, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v54, v22, s4
; VI-NEXT: v_perm_b32 v1, v9, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v54, v22, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v52, v51, s4
; VI-NEXT: v_perm_b32 v1, v10, v53, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v52, v51, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v49, v19, s4
; VI-NEXT: v_perm_b32 v1, v11, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v49, v19, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v39, v38, s4
; VI-NEXT: v_perm_b32 v1, v12, v48, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v39, v38, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v36, v18, s4
; VI-NEXT: v_perm_b32 v1, v13, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v36, v18, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v34, v33, s4
; VI-NEXT: v_perm_b32 v1, v14, v35, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v34, v33, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -88639,93 +87815,78 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: v_mov_b32_e32 v31, s6
; VI-NEXT: .LBB109_5: ; %end
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v3, v3, v31, s4
; VI-NEXT: v_perm_b32 v2, v2, v6, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v3, v31, s4
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v1, v1, v62, s4
; VI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, v61, v60, s4
-; VI-NEXT: v_perm_b32 v1, v1, v62, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v58, v30, s4
; VI-NEXT: v_perm_b32 v1, v5, v59, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v58, v30, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v56, v47, s4
; VI-NEXT: v_perm_b32 v1, v4, v57, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v56, v47, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v45, v29, s4
; VI-NEXT: v_perm_b32 v1, v8, v46, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v45, v29, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v43, v42, s4
; VI-NEXT: v_perm_b32 v1, v7, v44, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v43, v42, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v40, v28, s4
; VI-NEXT: v_perm_b32 v1, v11, v41, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v40, v28, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v54, v53, s4
; VI-NEXT: v_perm_b32 v1, v10, v55, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v54, v53, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v51, v27, s4
; VI-NEXT: v_perm_b32 v1, v14, v52, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v51, v27, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v49, v48, s4
; VI-NEXT: v_perm_b32 v1, v13, v50, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v49, v48, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v38, v26, s4
; VI-NEXT: v_perm_b32 v1, v17, v39, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v38, v26, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v36, v35, s4
; VI-NEXT: v_perm_b32 v1, v16, v37, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v36, v35, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v33, v25, s4
; VI-NEXT: v_perm_b32 v1, v20, v34, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v33, v25, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v21, v18, s4
; VI-NEXT: v_perm_b32 v1, v19, v32, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v21, v18, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v12, v24, s4
; VI-NEXT: v_perm_b32 v1, v23, v15, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v12, v24, s4
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
@@ -88754,8 +87915,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -89348,15 +88508,12 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v17, v31, v17, s4
; GFX9-NEXT: v_perm_b32 v3, v30, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v17
+; GFX9-NEXT: v_lshl_or_b32 v3, v17, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v16, v37, v16, s4
; GFX9-NEXT: v_perm_b32 v1, v47, v1, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_perm_b32 v2, v44, v2, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_readlane_b32 s30, v63, 14
; GFX9-NEXT: v_readlane_b32 s31, v63, 15
; GFX9-NEXT: v_readlane_b32 s55, v63, 13
@@ -89378,73 +88535,60 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v4, v26, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_perm_b32 v3, v35, v10, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v29, v25, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v16, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v3, v32, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v36, v12, s4
+; GFX9-NEXT: v_perm_b32 v4, v29, v25, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_perm_b32 v3, v50, v14, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v27, v62, s4
+; GFX9-NEXT: v_perm_b32 v4, v36, v12, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v3, v28, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v38, v8, s4
+; GFX9-NEXT: v_perm_b32 v4, v27, v62, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_perm_b32 v3, v48, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v33, v61, s4
+; GFX9-NEXT: v_perm_b32 v4, v38, v8, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v34, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v51, v7, s4
+; GFX9-NEXT: v_perm_b32 v4, v33, v61, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_perm_b32 v3, v53, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v39, v60, s4
+; GFX9-NEXT: v_perm_b32 v4, v51, v7, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v3, v49, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v55, v6, s4
+; GFX9-NEXT: v_perm_b32 v4, v39, v60, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: v_perm_b32 v3, v41, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v52, v59, s4
+; GFX9-NEXT: v_perm_b32 v4, v55, v6, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v3, v54, v24, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v43, v5, s4
+; GFX9-NEXT: v_perm_b32 v4, v52, v59, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_perm_b32 v3, v45, v58, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v40, v18, s4
+; GFX9-NEXT: v_perm_b32 v4, v43, v5, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v42, v57, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v40, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_perm_b32 v3, v56, v13, s4
-; GFX9-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v46, v9, s4
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -89981,64 +89125,57 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v24, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v27, v12, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v16, v2, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v14, 16, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v25, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v22, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v25, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v21, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v26, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v32, v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v23, v6, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v3, v13
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v20, v4, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v17
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v31, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v5, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v29, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v20, v4, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v31, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v6, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v36, v10, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v33, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v38, v9, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v28, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v35, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v30, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v48, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v6, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v37, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v29, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v28, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v36, v10, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v35, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v17, v18
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v50, v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v39, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v54, v7, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v53, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v5, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v37, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v50, v8, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v34, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v10, 16, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v55, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v39, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v54, v7, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v49, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v52, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v8, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v20, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v21, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v5, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v9
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v10, 16, v20
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v21
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v22
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-TRUE16-NEXT: s_clause 0x3
@@ -90580,62 +89717,55 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v22, v11, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v14, v2, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v27, v10, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v19, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v12, 16, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v27, v10, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v23, v86, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v25, v85, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v32, v9, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v18, v4, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v25, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v84, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v18, v4, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v30, v83, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v35, v8, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v80, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v17
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v28, v70, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v82, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v35, v8, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v34, v71, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v38, v7, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v28, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v37, v69, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v65, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v52, v5, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v51, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v8, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v7, 16, v18
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v31, v67, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v53, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v36, v64, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v50, v54, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v49, v13, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v18, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v19, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v22, v23
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v20
@@ -91557,28 +90687,17 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_perm_b32 v9, v44, v42, s6
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v57, v46, s6
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v11, v58, v47, s6
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v33, v62, s6
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v35, v34, s6
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v49, v48, s6
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v51, v50, s6
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; kill: killed $vgpr18
; VI-NEXT: ; implicit-def: $vgpr18
@@ -91611,16 +90730,14 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -91629,8 +90746,7 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -91638,37 +90754,35 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v17, v4, s6
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v16, v4, s6
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_perm_b32 v10, v61, v60, s6
-; VI-NEXT: v_or_b32_e32 v10, v10, v11
+; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
; VI-NEXT: v_perm_b32 v11, v59, v56, s6
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: v_perm_b32 v12, v31, v63, s6
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
-; VI-NEXT: v_or_b32_e32 v13, v13, v14
+; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; VI-NEXT: v_perm_b32 v14, v39, v38, s6
-; VI-NEXT: v_perm_b32 v16, v32, v54, s6
-; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
; VI-NEXT: v_perm_b32 v15, v53, v52, s6
-; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; VI-NEXT: v_or_b32_e32 v15, v15, v16
+; VI-NEXT: v_perm_b32 v16, v32, v54, s6
+; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr16
; VI-NEXT: ; implicit-def: $vgpr16
@@ -93907,96 +93021,80 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB111_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v3
-; VI-NEXT: v_mov_b32_e32 v3, s27
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v2, s25
-; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_mov_b32_e32 v3, s27
; VI-NEXT: v_perm_b32 v2, s24, v2, v11
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s45
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, s26, v3, v11
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s29
-; VI-NEXT: v_perm_b32 v4, s57, v4, v11
+; VI-NEXT: v_mov_b32_e32 v4, s45
; VI-NEXT: v_perm_b32 v3, s28, v3, v11
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s47
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, s57, v4, v11
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_perm_b32 v5, s59, v5, v11
+; VI-NEXT: v_mov_b32_e32 v5, s47
; VI-NEXT: v_perm_b32 v4, s56, v4, v11
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s60
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, s59, v5, v11
+; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_perm_b32 v6, s63, v6, v11
+; VI-NEXT: v_mov_b32_e32 v6, s60
; VI-NEXT: v_perm_b32 v5, s61, v5, v11
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s72
-; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, s63, v6, v11
+; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s62
-; VI-NEXT: v_perm_b32 v7, s75, v7, v11
+; VI-NEXT: v_mov_b32_e32 v7, s72
; VI-NEXT: v_perm_b32 v6, s73, v6, v11
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s42
-; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, s75, v7, v11
+; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s74
-; VI-NEXT: v_perm_b32 v8, s43, v8, v11
+; VI-NEXT: v_mov_b32_e32 v8, s42
; VI-NEXT: v_perm_b32 v7, s76, v7, v11
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s7
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, s43, v8, v11
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s6
-; VI-NEXT: v_perm_b32 v9, s9, v9, v11
+; VI-NEXT: v_mov_b32_e32 v9, s7
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, s9, v9, v11
+; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s8
-; VI-NEXT: v_perm_b32 v10, s13, v10, v11
+; VI-NEXT: v_mov_b32_e32 v10, s10
; VI-NEXT: v_perm_b32 v9, s11, v9, v11
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_mov_b32_e32 v12, s14
-; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_perm_b32 v10, s13, v10, v11
+; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s12
-; VI-NEXT: v_perm_b32 v12, s40, v12, v11
+; VI-NEXT: v_mov_b32_e32 v12, s14
; VI-NEXT: v_perm_b32 v10, s15, v10, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_perm_b32 v12, s40, v12, v11
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_or_b32_e32 v10, v10, v12
-; VI-NEXT: v_perm_b32 v12, v18, v17, s4
+; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; VI-NEXT: v_perm_b32 v11, s41, v16, v11
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_or_b32_e32 v11, v11, v12
+; VI-NEXT: v_perm_b32 v12, v18, v17, s4
+; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v25, v20, s4
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v22, v19, s4
-; VI-NEXT: v_or_b32_e32 v12, v13, v12
+; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; VI-NEXT: v_perm_b32 v13, v30, v24, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v27, v21, s4
-; VI-NEXT: v_or_b32_e32 v13, v14, v13
+; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
; VI-NEXT: v_perm_b32 v14, v32, v26, s4
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v29, v23, s4
-; VI-NEXT: v_or_b32_e32 v14, v15, v14
+; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
; VI-NEXT: v_perm_b32 v15, v34, v31, s4
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v33, v28, s4
-; VI-NEXT: v_or_b32_e32 v15, v35, v15
+; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
; VI-NEXT: s_cbranch_execnz .LBB111_3
; VI-NEXT: .LBB111_2: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v34
@@ -94550,16 +93648,14 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB111_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
@@ -94580,53 +93676,52 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v34, 8, v10
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v50, 8, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v48, 8, v14
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v31, 8, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v32, 8, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v35, 8, v16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB111_3
; GFX11-TRUE16-NEXT: .LBB111_2: ; %cmp.true
@@ -94837,23 +93932,23 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
+; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
+; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
@@ -94864,35 +93959,29 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v34, 8, s79
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v31, 8, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v35, 8, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v38, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v33, 8, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 8, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index 77c047f492cac..9662b0eb88db5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -3043,14 +3043,12 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB26_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v2, v3, s6
; VI-NEXT: v_perm_b32 v0, v9, v10, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v2, v3, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -3237,37 +3235,34 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB26_2
; GFX11-FAKE16-NEXT: .LBB26_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -3354,19 +3349,17 @@ define inreg i64 @bitcast_v8i8_to_i64_scalar(<8 x i8> inreg %a, i32 inreg %b) #0
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB27_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v2, s18, v2, v1
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_perm_b32 v2, s18, v2, v1
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: s_cbranch_execnz .LBB27_3
; VI-NEXT: .LBB27_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -3402,19 +3395,17 @@ define inreg i64 @bitcast_v8i8_to_i64_scalar(<8 x i8> inreg %a, i32 inreg %b) #0
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -3480,14 +3471,13 @@ define inreg i64 @bitcast_v8i8_to_i64_scalar(<8 x i8> inreg %a, i32 inreg %b) #0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB27_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -6221,14 +6211,12 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB50_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v2, v3, s6
; VI-NEXT: v_perm_b32 v0, v9, v10, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v2, v3, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -6415,37 +6403,34 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6532,19 +6517,17 @@ define inreg double @bitcast_v8i8_to_f64_scalar(<8 x i8> inreg %a, i32 inreg %b)
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v2, s18, v2, v1
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_perm_b32 v2, s18, v2, v1
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -6580,19 +6563,17 @@ define inreg double @bitcast_v8i8_to_f64_scalar(<8 x i8> inreg %a, i32 inreg %b)
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -6658,14 +6639,13 @@ define inreg double @bitcast_v8i8_to_f64_scalar(<8 x i8> inreg %a, i32 inreg %b)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB51_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -9078,14 +9058,12 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB70_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v2, v3, s6
; VI-NEXT: v_perm_b32 v0, v9, v10, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v2, v3, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -9272,37 +9250,34 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB70_2
; GFX11-FAKE16-NEXT: .LBB70_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9389,19 +9364,17 @@ define inreg <2 x i32> @bitcast_v8i8_to_v2i32_scalar(<8 x i8> inreg %a, i32 inre
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB71_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v2, s18, v2, v1
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_perm_b32 v2, s18, v2, v1
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: s_cbranch_execnz .LBB71_3
; VI-NEXT: .LBB71_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -9437,19 +9410,17 @@ define inreg <2 x i32> @bitcast_v8i8_to_v2i32_scalar(<8 x i8> inreg %a, i32 inre
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9515,14 +9486,13 @@ define inreg <2 x i32> @bitcast_v8i8_to_v2i32_scalar(<8 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB71_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11644,14 +11614,12 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB86_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v2, v3, s6
; VI-NEXT: v_perm_b32 v0, v9, v10, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v2, v3, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -11838,37 +11806,34 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB86_2
; GFX11-FAKE16-NEXT: .LBB86_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -11955,19 +11920,17 @@ define inreg <2 x float> @bitcast_v8i8_to_v2f32_scalar(<8 x i8> inreg %a, i32 in
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB87_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v2, s18, v2, v1
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_perm_b32 v2, s18, v2, v1
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: s_cbranch_execnz .LBB87_3
; VI-NEXT: .LBB87_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -12003,19 +11966,17 @@ define inreg <2 x float> @bitcast_v8i8_to_v2f32_scalar(<8 x i8> inreg %a, i32 in
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -12081,14 +12042,13 @@ define inreg <2 x float> @bitcast_v8i8_to_v2f32_scalar(<8 x i8> inreg %a, i32 in
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB87_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -13446,14 +13406,12 @@ define <8 x i8> @bitcast_v4i16_to_v8i8(<4 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB96_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v2, 3
-; VI-NEXT: v_add_u16_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v8, 3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; VI-NEXT: v_add_u16_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v9, 3, v0
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v8, v1
-; VI-NEXT: v_or_b32_e32 v0, v9, v0
+; VI-NEXT: v_add_u16_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v8
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v9
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v4, 8, v0
@@ -13906,14 +13864,12 @@ define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB98_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v2, v3, s6
; VI-NEXT: v_perm_b32 v0, v9, v10, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v2, v3, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -14100,37 +14056,34 @@ define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB98_2
; GFX11-FAKE16-NEXT: .LBB98_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -14230,19 +14183,17 @@ define inreg <4 x i16> @bitcast_v8i8_to_v4i16_scalar(<8 x i8> inreg %a, i32 inre
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB99_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v2, s18, v2, v1
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_perm_b32 v2, s18, v2, v1
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: s_cbranch_execnz .LBB99_3
; VI-NEXT: .LBB99_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -14278,19 +14229,17 @@ define inreg <4 x i16> @bitcast_v8i8_to_v4i16_scalar(<8 x i8> inreg %a, i32 inre
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB99_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB99_3
; GFX9-NEXT: .LBB99_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -14356,14 +14305,13 @@ define inreg <4 x i16> @bitcast_v8i8_to_v4i16_scalar(<8 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB99_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -15305,13 +15253,11 @@ define <8 x i8> @bitcast_v4f16_to_v8i8(<4 x half> %a, i32 %b) #0 {
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v0, 0x200
; VI-NEXT: v_add_f16_sdwa v6, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_sdwa v2, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; VI-NEXT: v_add_f16_sdwa v2, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT: v_or_b32_e32 v1, v9, v1
-; VI-NEXT: v_or_b32_e32 v0, v8, v0
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v9
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v8
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
@@ -15539,13 +15485,11 @@ define inreg <8 x i8> @bitcast_v4f16_to_v8i8_scalar(<4 x half> inreg %a, i32 inr
; VI-NEXT: v_mov_b32_e32 v0, 0x200
; VI-NEXT: v_add_f16_e32 v6, s4, v0
; VI-NEXT: s_lshr_b32 s4, s16, 16
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
; VI-NEXT: v_add_f16_e32 v8, s17, v0
; VI-NEXT: v_add_f16_e32 v2, s4, v0
-; VI-NEXT: v_or_b32_e32 v10, v8, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; VI-NEXT: v_add_f16_e32 v0, s16, v0
-; VI-NEXT: v_or_b32_e32 v9, v0, v1
+; VI-NEXT: v_lshl_or_b32 v10, v6, 16, v8
+; VI-NEXT: v_lshl_or_b32 v9, v2, 16, v0
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[9:10]
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v10
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v9
@@ -15775,14 +15719,12 @@ define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB106_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v2, v3, s6
; VI-NEXT: v_perm_b32 v0, v9, v10, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v2, v3, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -15969,37 +15911,34 @@ define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB106_2
; GFX11-FAKE16-NEXT: .LBB106_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -16099,19 +16038,17 @@ define inreg <4 x half> @bitcast_v8i8_to_v4f16_scalar(<8 x i8> inreg %a, i32 inr
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB107_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v2, s18, v2, v1
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_perm_b32 v2, s18, v2, v1
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: s_cbranch_execnz .LBB107_3
; VI-NEXT: .LBB107_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -16147,19 +16084,17 @@ define inreg <4 x half> @bitcast_v8i8_to_v4f16_scalar(<8 x i8> inreg %a, i32 inr
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB107_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB107_3
; GFX9-NEXT: .LBB107_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -16225,14 +16160,13 @@ define inreg <4 x half> @bitcast_v8i8_to_v4f16_scalar(<8 x i8> inreg %a, i32 inr
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB107_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -17136,14 +17070,12 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB110_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v2, v3, s6
; VI-NEXT: v_perm_b32 v0, v9, v10, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v2, v3, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -17330,37 +17262,34 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB110_2
; GFX11-FAKE16-NEXT: .LBB110_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -17458,19 +17387,17 @@ define inreg <4 x bfloat> @bitcast_v8i8_to_v4bf16_scalar(<8 x i8> inreg %a, i32
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB111_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v2, s18, v2, v1
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_perm_b32 v2, s18, v2, v1
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: s_cbranch_execnz .LBB111_3
; VI-NEXT: .LBB111_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -17506,19 +17433,17 @@ define inreg <4 x bfloat> @bitcast_v8i8_to_v4bf16_scalar(<8 x i8> inreg %a, i32
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB111_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB111_3
; GFX9-NEXT: .LBB111_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -17584,14 +17509,13 @@ define inreg <4 x bfloat> @bitcast_v8i8_to_v4bf16_scalar(<8 x i8> inreg %a, i32
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB111_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index a1c0db086bf3c..353df14c2f25d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -975,18 +975,15 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB6_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v15, v3, s6
; VI-NEXT: v_perm_b32 v0, v14, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v15, v3, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
@@ -1229,42 +1226,39 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v15, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1374,25 +1368,22 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: s_cmp_lg_u32 s28, 0
; VI-NEXT: s_cbranch_scc0 .LBB7_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
; VI-NEXT: v_perm_b32 v0, s16, v0, v2
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s22, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_mov_b32_e32 v3, s25
; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v3, s24, v3, v2
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; VI-NEXT: s_cbranch_execnz .LBB7_3
; VI-NEXT: .LBB7_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -1438,25 +1429,22 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB7_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: s_cbranch_execnz .LBB7_3
; GFX9-NEXT: .LBB7_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -1534,20 +1522,18 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
; GFX11-NEXT: v_perm_b32 v0, s22, s23, v0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB7_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4138,18 +4124,15 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB22_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v15, v3, s6
; VI-NEXT: v_perm_b32 v0, v14, v13, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v15, v3, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
@@ -4392,42 +4375,39 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v15, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4537,25 +4517,22 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; VI-NEXT: s_cmp_lg_u32 s28, 0
; VI-NEXT: s_cbranch_scc0 .LBB23_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
; VI-NEXT: v_perm_b32 v0, s16, v0, v2
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s22, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_mov_b32_e32 v3, s25
; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v3, s24, v3, v2
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; VI-NEXT: s_cbranch_execnz .LBB23_3
; VI-NEXT: .LBB23_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -4601,25 +4578,22 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB23_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: s_cbranch_execnz .LBB23_3
; GFX9-NEXT: .LBB23_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -4697,20 +4671,18 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
; GFX11-NEXT: v_perm_b32 v0, s22, s23, v0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -6823,18 +6795,15 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB36_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v13, v16, s6
; VI-NEXT: v_perm_b32 v0, v15, v14, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v13, v16, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
@@ -7079,42 +7048,39 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -7241,25 +7207,22 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; VI-NEXT: s_cmp_lg_u32 s28, 0
; VI-NEXT: s_cbranch_scc0 .LBB37_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
; VI-NEXT: v_perm_b32 v0, s16, v0, v2
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s22, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_mov_b32_e32 v3, s25
; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v3, s24, v3, v2
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; VI-NEXT: s_cbranch_execnz .LBB37_3
; VI-NEXT: .LBB37_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -7305,25 +7268,22 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB37_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: s_cbranch_execnz .LBB37_3
; GFX9-NEXT: .LBB37_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -7401,20 +7361,18 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
; GFX11-NEXT: v_perm_b32 v0, s22, s23, v0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8647,18 +8605,15 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB40_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v13, v16, s6
; VI-NEXT: v_perm_b32 v0, v15, v14, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v13, v16, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
@@ -8903,42 +8858,39 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9068,25 +9020,22 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; VI-NEXT: s_cmp_lg_u32 s28, 0
; VI-NEXT: s_cbranch_scc0 .LBB41_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
; VI-NEXT: v_perm_b32 v0, s16, v0, v2
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s22, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_mov_b32_e32 v3, s25
; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v3, s24, v3, v2
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; VI-NEXT: s_cbranch_execnz .LBB41_3
; VI-NEXT: .LBB41_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -9132,25 +9081,22 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB41_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: s_cbranch_execnz .LBB41_3
; GFX9-NEXT: .LBB41_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9228,20 +9174,18 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
; GFX11-NEXT: v_perm_b32 v0, s22, s23, v0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB41_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -9384,17 +9328,14 @@ define <12 x i8> @bitcast_v6f16_to_v12i8(<6 x half> %a, i32 %b) #0 {
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v3, 0x200
; VI-NEXT: v_add_f16_sdwa v6, v14, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
; VI-NEXT: v_add_f16_sdwa v2, v13, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_sdwa v10, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_or_b32_e32 v1, v14, v0
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; VI-NEXT: v_add_f16_sdwa v10, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT: v_or_b32_e32 v0, v13, v0
-; VI-NEXT: v_or_b32_e32 v11, v8, v3
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v14
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v13
+; VI-NEXT: v_lshl_or_b32 v11, v10, 16, v8
; VI-NEXT: v_mov_b32_e32 v12, 0x7e007e00
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v11
@@ -9693,18 +9634,15 @@ define inreg <12 x i8> @bitcast_v6f16_to_v12i8_scalar(<6 x half> inreg %a, i32 i
; VI-NEXT: v_mov_b32_e32 v1, 0x200
; VI-NEXT: v_add_f16_e32 v6, s4, v1
; VI-NEXT: s_lshr_b32 s4, s16, 16
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
-; VI-NEXT: v_add_f16_e32 v13, s17, v1
; VI-NEXT: v_add_f16_e32 v2, s4, v1
; VI-NEXT: s_lshr_b32 s4, s18, 16
-; VI-NEXT: v_or_b32_e32 v12, v13, v0
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; VI-NEXT: v_add_f16_e32 v13, s17, v1
; VI-NEXT: v_add_f16_e32 v0, s16, v1
; VI-NEXT: v_add_f16_e32 v10, s4, v1
-; VI-NEXT: v_or_b32_e32 v11, v0, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; VI-NEXT: v_add_f16_e32 v8, s18, v1
-; VI-NEXT: v_or_b32_e32 v14, v8, v3
+; VI-NEXT: v_lshl_or_b32 v12, v6, 16, v13
+; VI-NEXT: v_lshl_or_b32 v11, v2, 16, v0
+; VI-NEXT: v_lshl_or_b32 v14, v10, 16, v8
; VI-NEXT: v_mov_b32_e32 v15, 0x7e007e00
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[11:12]
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v12
@@ -10010,18 +9948,15 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB44_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v13, v16, s6
; VI-NEXT: v_perm_b32 v0, v15, v14, s6
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v13, v16, s6
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_perm_b32 v1, v4, v5, s6
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v6, v7, s6
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; VI-NEXT: v_perm_b32 v2, v8, v9, s6
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v10, v11, s6
+; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
@@ -10266,42 +10201,39 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -10431,25 +10363,22 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: s_cmp_lg_u32 s28, 0
; VI-NEXT: s_cbranch_scc0 .LBB45_4
; VI-NEXT: ; %bb.1: ; %cmp.false
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v0, s17
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
; VI-NEXT: v_perm_b32 v0, s16, v0, v2
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v3, s22, v3, v2
+; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_perm_b32 v3, s22, v3, v2
+; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-NEXT: v_mov_b32_e32 v3, s25
; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v3, s24, v3, v2
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; VI-NEXT: s_cbranch_execnz .LBB45_3
; VI-NEXT: .LBB45_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -10495,25 +10424,22 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB45_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: s_cbranch_execnz .LBB45_3
; GFX9-NEXT: .LBB45_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -10591,20 +10517,18 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
; GFX11-NEXT: v_perm_b32 v0, s22, s23, v0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB45_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10745,19 +10669,16 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB46_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v3, 3
-; VI-NEXT: v_add_u16_sdwa v6, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_sdwa v13, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v14, 3, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; VI-NEXT: v_add_u16_sdwa v6, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v16, 3, v0
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v13
-; VI-NEXT: v_or_b32_e32 v1, v14, v1
-; VI-NEXT: v_or_b32_e32 v0, v16, v0
-; VI-NEXT: v_add_u16_sdwa v10, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v13, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v14
+; VI-NEXT: v_lshl_or_b32 v0, v13, 16, v16
; VI-NEXT: v_add_u16_e32 v8, 3, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
+; VI-NEXT: v_add_u16_sdwa v10, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
-; VI-NEXT: v_or_b32_e32 v2, v8, v2
+; VI-NEXT: v_lshl_or_b32 v2, v10, 16, v8
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3]
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v2
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index b883f82c0ca27..cda20e5a04c9c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -4695,12 +4695,11 @@ define amdgpu_kernel void @udiv_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v0
; GFX9-NEXT: v_mad_f32 v0, -v0, v1, v6
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1
-; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v5, vcc
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
-; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 15, v3
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
@@ -4885,21 +4884,20 @@ define amdgpu_kernel void @urem_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v4
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mad_f32 v4, -v4, v3, v6
-; GFX9-NEXT: s_lshr_b32 s4, s6, 15
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3
+; GFX9-NEXT: s_lshr_b32 s4, s6, 15
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s4
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v3, s3
; GFX9-NEXT: s_lshr_b32 s3, s2, 15
; GFX9-NEXT: v_sub_u32_e32 v4, s2, v0
; GFX9-NEXT: v_sub_u32_e32 v5, s3, v1
; GFX9-NEXT: v_sub_u32_e32 v0, s8, v3
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v4
; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v5
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 15, v3
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
@@ -5114,11 +5112,10 @@ define amdgpu_kernel void @sdiv_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
; GFX9-NEXT: s_cselect_b32 s2, s4, 0
; GFX9-NEXT: v_add_u32_e32 v0, s2, v5
-; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 15, v3
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
@@ -5359,11 +5356,10 @@ define amdgpu_kernel void @srem_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: v_sub_u32_e32 v5, s3, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: v_sub_u32_e32 v0, s9, v2
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v2, 0x7fff, v4
; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v5
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 15, v2
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
; GFX9-NEXT: global_store_dword v3, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index aed1e4fe685f5..695e48407d4bb 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -11904,10 +11904,9 @@ define amdgpu_kernel void @uniform_fadd_f16(ptr addrspace(1) %result, ptr addrsp
; GFX8-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: v_lshrrev_b32_e32 v0, s10, v1
-; GFX8-NEXT: v_add_f16_e32 v0, s11, v0
; GFX8-NEXT: v_and_b32_e32 v2, s2, v1
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, s10, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_add_f16_e32 v0, s11, v0
+; GFX8-NEXT: v_lshl_or_b32 v0, v0, s10, v2
; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: v_mov_b32_e32 v2, v0
; GFX8-NEXT: buffer_atomic_cmpswap v[2:3], off, s[4:7], 0 glc
diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
index ca7e358fc0314..34c465875eb83 100644
--- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
+++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
@@ -379,9 +379,8 @@ define amdgpu_kernel void @call_with_private_to_flat_addrspacecast_cc_kernel(ptr
; GFX8-NEXT: s_add_u32 s16, s16, with_private_to_flat_addrspacecast at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GFX8-NEXT: v_or_b32_e32 v31, v0, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s15
@@ -400,9 +399,8 @@ define amdgpu_kernel void @call_with_private_to_flat_addrspacecast_cc_kernel(ptr
; GFX8-ARCH-FLAT-NEXT: s_add_u32 s4, s4, with_private_to_flat_addrspacecast at gotpcrel32@lo+4
; GFX8-ARCH-FLAT-NEXT: s_addc_u32 s5, s5, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
; GFX8-ARCH-FLAT-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX8-ARCH-FLAT-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX8-ARCH-FLAT-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX8-ARCH-FLAT-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-ARCH-FLAT-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GFX8-ARCH-FLAT-NEXT: s_mov_b32 s14, s10
; GFX8-ARCH-FLAT-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX8-ARCH-FLAT-NEXT: v_or_b32_e32 v31, v0, v2
@@ -744,9 +742,8 @@ define amdgpu_kernel void @call_calls_intrin_ascast_cc_kernel(ptr addrspace(3) %
; GFX8-NEXT: s_add_u32 s16, s16, calls_intrin_ascast at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, calls_intrin_ascast at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GFX8-NEXT: v_or_b32_e32 v31, v0, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s15
@@ -765,9 +762,8 @@ define amdgpu_kernel void @call_calls_intrin_ascast_cc_kernel(ptr addrspace(3) %
; GFX8-ARCH-FLAT-NEXT: s_add_u32 s4, s4, calls_intrin_ascast at gotpcrel32@lo+4
; GFX8-ARCH-FLAT-NEXT: s_addc_u32 s5, s5, calls_intrin_ascast at gotpcrel32@hi+12
; GFX8-ARCH-FLAT-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; GFX8-ARCH-FLAT-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX8-ARCH-FLAT-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX8-ARCH-FLAT-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-ARCH-FLAT-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GFX8-ARCH-FLAT-NEXT: s_mov_b32 s14, s10
; GFX8-ARCH-FLAT-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX8-ARCH-FLAT-NEXT: v_or_b32_e32 v31, v0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
index b5844049fd287..156ca17782c35 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
@@ -3660,10 +3660,9 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__amdgpu_no_fine_gr
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, s6, v2
-; GFX8-NEXT: v_add_f16_e32 v1, v1, v0
; GFX8-NEXT: v_and_b32_e32 v3, s7, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, s6, v1
-; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX8-NEXT: v_add_f16_e32 v1, v1, v0
+; GFX8-NEXT: v_lshl_or_b32 v1, v1, s6, v3
; GFX8-NEXT: v_mov_b32_e32 v4, v2
; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: buffer_atomic_cmpswap v[3:4], v5, s[16:19], 0 offen glc
@@ -4086,10 +4085,9 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f16__offset__amdgpu_no_fine_
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, s6, v2
-; GFX8-NEXT: v_add_f16_e32 v1, v1, v0
; GFX8-NEXT: v_and_b32_e32 v4, s7, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, s6, v1
-; GFX8-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX8-NEXT: v_add_f16_e32 v1, v1, v0
+; GFX8-NEXT: v_lshl_or_b32 v1, v1, s6, v4
; GFX8-NEXT: v_mov_b32_e32 v5, v2
; GFX8-NEXT: v_mov_b32_e32 v4, v1
; GFX8-NEXT: buffer_atomic_cmpswap v[4:5], v3, s[16:19], 0 offen glc
@@ -4802,9 +4800,8 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v6, v4, v7
; GFX8-NEXT: v_add_f16_e32 v6, v6, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, v4, v6
; GFX8-NEXT: v_and_b32_e32 v8, v7, v11
-; GFX8-NEXT: v_or_b32_e32 v6, v8, v6
+; GFX8-NEXT: v_lshl_or_b32 v6, v6, v4, v8
; GFX8-NEXT: v_mov_b32_e32 v9, v7
; GFX8-NEXT: s_mov_b64 s[12:13], exec
; GFX8-NEXT: v_mov_b32_e32 v8, v6
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
index 3d85bf7019426..21f719d0b2997 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
@@ -2758,10 +2758,9 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v0, s6, v1
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX8-NEXT: v_max_f16_e32 v0, v0, v5
; GFX8-NEXT: v_and_b32_e32 v2, s7, v1
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, s6, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_max_f16_e32 v0, v0, v5
+; GFX8-NEXT: v_lshl_or_b32 v0, v0, s6, v2
; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: v_mov_b32_e32 v2, v0
; GFX8-NEXT: buffer_atomic_cmpswap v[2:3], v4, s[16:19], 0 offen glc
@@ -3205,10 +3204,9 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v0, s6, v1
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX8-NEXT: v_max_f16_e32 v0, v0, v3
; GFX8-NEXT: v_and_b32_e32 v4, s7, v1
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, s6, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX8-NEXT: v_max_f16_e32 v0, v0, v3
+; GFX8-NEXT: v_lshl_or_b32 v0, v0, s6, v4
; GFX8-NEXT: v_mov_b32_e32 v5, v1
; GFX8-NEXT: v_mov_b32_e32 v4, v0
; GFX8-NEXT: buffer_atomic_cmpswap v[4:5], v2, s[16:19], 0 offen glc
@@ -3943,9 +3941,8 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v7, v6
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
; GFX8-NEXT: v_max_f16_e32 v4, v4, v10
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX8-NEXT: v_and_b32_e32 v5, v6, v9
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v4
+; GFX8-NEXT: v_lshl_or_b32 v5, v4, v7, v5
; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: s_mov_b64 s[12:13], exec
; GFX8-NEXT: v_mov_b32_e32 v5, v6
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
index 3f15d35320573..3dda7c7272276 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
@@ -2758,10 +2758,9 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v0, s6, v1
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX8-NEXT: v_min_f16_e32 v0, v0, v5
; GFX8-NEXT: v_and_b32_e32 v2, s7, v1
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, s6, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_min_f16_e32 v0, v0, v5
+; GFX8-NEXT: v_lshl_or_b32 v0, v0, s6, v2
; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: v_mov_b32_e32 v2, v0
; GFX8-NEXT: buffer_atomic_cmpswap v[2:3], v4, s[16:19], 0 offen glc
@@ -3205,10 +3204,9 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v0, s6, v1
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX8-NEXT: v_min_f16_e32 v0, v0, v3
; GFX8-NEXT: v_and_b32_e32 v4, s7, v1
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, s6, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v4, v0
+; GFX8-NEXT: v_min_f16_e32 v0, v0, v3
+; GFX8-NEXT: v_lshl_or_b32 v0, v0, s6, v4
; GFX8-NEXT: v_mov_b32_e32 v5, v1
; GFX8-NEXT: v_mov_b32_e32 v4, v0
; GFX8-NEXT: buffer_atomic_cmpswap v[4:5], v2, s[16:19], 0 offen glc
@@ -3943,9 +3941,8 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v7, v6
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
; GFX8-NEXT: v_min_f16_e32 v4, v4, v10
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX8-NEXT: v_and_b32_e32 v5, v6, v9
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v4
+; GFX8-NEXT: v_lshl_or_b32 v5, v4, v7, v5
; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: s_mov_b64 s[12:13], exec
; GFX8-NEXT: v_mov_b32_e32 v5, v6
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index 77ee1ada2af94..ccf84c5cd5a27 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -244,11 +244,10 @@ define amdgpu_kernel void @call_coldcc() #0 {
; VI-NEXT: s_add_u32 s4, s4, coldcc at gotpcrel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, coldcc at gotpcrel32@hi+12
; VI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; VI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b64 s[10:11], s[6:7]
; VI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; VI-NEXT: s_mov_b64 s[4:5], s[0:1]
; VI-NEXT: s_mov_b64 s[6:7], s[2:3]
; VI-NEXT: s_mov_b64 s[0:1], s[88:89]
@@ -356,11 +355,10 @@ define amdgpu_kernel void @call_fastcc() #0 {
; VI-NEXT: s_add_u32 s4, s4, fastcc at gotpcrel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, fastcc at gotpcrel32@hi+12
; VI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
-; VI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b64 s[10:11], s[6:7]
; VI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; VI-NEXT: s_mov_b64 s[4:5], s[0:1]
; VI-NEXT: s_mov_b64 s[6:7], s[2:3]
; VI-NEXT: s_mov_b64 s[0:1], s[88:89]
@@ -3805,18 +3803,18 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 3, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 3, v14
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 4, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v11, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 3, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v7, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 4, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 15, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 15, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 4, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 15, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 12, v5
@@ -3830,11 +3828,9 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: global_store_b32 v[0:1], v0, off
; GFX11-FAKE16-NEXT: s_endpgm
;
@@ -3973,13 +3969,13 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
; GFX1250-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
; GFX1250-FAKE16-NEXT: v_or_b32_e32 v11, v14, v11
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v12, v28, v15, 1 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 4, v3
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v4
; GFX1250-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v6, v16, v8, 1 bitop3:0xec
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v7, v5, 3 bitop3:0xec
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v7, v10, 15, v9 bitop3:0xc8
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v8, v12, v11, 3 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 4, v3
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v4
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v2, v6, v2, 3 bitop3:0xec
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 4, v5
@@ -3994,9 +3990,8 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v2, v3, 0xff bitop3:0xec
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX1250-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX1250-FAKE16-NEXT: global_store_b32 v[0:1], v0, off
; GFX1250-FAKE16-NEXT: s_endpgm
store <32 x i1> %arg0, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/cc-update.ll b/llvm/test/CodeGen/AMDGPU/cc-update.ll
index ee1feccc6334c..cd41775e036ad 100644
--- a/llvm/test/CodeGen/AMDGPU/cc-update.ll
+++ b/llvm/test/CodeGen/AMDGPU/cc-update.ll
@@ -70,10 +70,9 @@ define amdgpu_kernel void @test_kern_call() local_unnamed_addr #0 {
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s17
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_mov_b32 s13, s15
; GFX803-NEXT: s_mov_b32 s12, s14
@@ -154,10 +153,9 @@ define amdgpu_kernel void @test_kern_stack_and_call() local_unnamed_addr #0 {
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s17
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_mov_b32 s13, s15
; GFX803-NEXT: s_mov_b32 s12, s14
@@ -321,10 +319,9 @@ define amdgpu_kernel void @test_force_fp_kern_call() local_unnamed_addr #2 {
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s17
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_mov_b32 s13, s15
; GFX803-NEXT: s_mov_b32 s12, s14
@@ -427,10 +424,9 @@ define amdgpu_kernel void @test_force_fp_kern_stack_and_call() local_unnamed_add
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s17
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GFX803-NEXT: s_mov_b32 s33, 0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_mov_b32 s13, s15
diff --git a/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll b/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
index 7a576b1c58c55..cb2e86c9c6b01 100644
--- a/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
+++ b/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
@@ -297,18 +297,17 @@ define amdgpu_kernel void @test_copy_v4i8_extra_use(ptr addrspace(1) %out0, ptr
; VI-NEXT: s_mov_b32 s9, s3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; VI-NEXT: v_add_u16_e32 v3, 9, v0
; VI-NEXT: v_and_b32_e32 v4, 0xffffff00, v1
; VI-NEXT: v_add_u16_e32 v1, 9, v1
-; VI-NEXT: v_add_u16_e32 v3, 9, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
; VI-NEXT: v_and_b32_e32 v2, 0xffffff00, v0
; VI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; VI-NEXT: v_or_b32_e32 v1, v4, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
; VI-NEXT: v_or_b32_e32 v2, v2, v3
-; VI-NEXT: v_add_u16_e32 v1, 0x900, v1
+; VI-NEXT: v_or_b32_e32 v1, v4, v1
; VI-NEXT: v_add_u16_e32 v2, 0x900, v2
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_add_u16_e32 v1, 0x900, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: buffer_store_dword v1, off, s[8:11], 0
; VI-NEXT: s_endpgm
@@ -383,18 +382,17 @@ define amdgpu_kernel void @test_copy_v4i8_x2_extra_use(ptr addrspace(1) %out0, p
; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; VI-NEXT: v_add_u16_e32 v3, 9, v0
; VI-NEXT: v_and_b32_e32 v4, 0xffffff00, v1
; VI-NEXT: v_add_u16_e32 v1, 9, v1
-; VI-NEXT: v_add_u16_e32 v3, 9, v0
-; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
; VI-NEXT: v_and_b32_e32 v2, 0xffffff00, v0
; VI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; VI-NEXT: v_or_b32_e32 v1, v4, v1
+; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
; VI-NEXT: v_or_b32_e32 v2, v2, v3
-; VI-NEXT: v_add_u16_e32 v1, 0x900, v1
+; VI-NEXT: v_or_b32_e32 v1, v4, v1
; VI-NEXT: v_add_u16_e32 v2, 0x900, v2
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_add_u16_e32 v1, 0x900, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: buffer_store_dword v1, off, s[12:15], 0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
diff --git a/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll b/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll
index 3ca7dea0c4b08..cbbda05e7f732 100644
--- a/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll
@@ -105,8 +105,7 @@ define double @copysign_known_signmask_f64_known_positive_mag(double nofpclass(n
; GFX9-LABEL: copysign_known_signmask_f64_known_positive_mag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 31, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 31, v1
; GFX9-NEXT: s_setpc_b64 s[30:31]
%signmask = shl i64 %sign, 63
%signmask.bitcast = bitcast i64 %signmask to double
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz.ll b/llvm/test/CodeGen/AMDGPU/ctlz.ll
index 2318155c3c078..a23131a10909b 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz.ll
@@ -1830,10 +1830,8 @@ define amdgpu_kernel void @v_ctlz_i17_sel_ne_bitwidth(ptr addrspace(1) noalias %
; VI-NEXT: v_mov_b32_e32 v1, 0x1ffff
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: v_ffbh_u32_e32 v0, v0
; VI-NEXT: v_min_u32_e32 v0, 32, v0
; VI-NEXT: v_add_u32_e32 v0, vcc, -15, v0
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
index 867bd8ee26227..e67d314fb4727 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
@@ -840,10 +840,8 @@ define amdgpu_kernel void @v_ctlz_zero_poison_i32_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v5, v[6:7]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1002,20 +1000,16 @@ define amdgpu_kernel void @v_ctlz_zero_poison_i64_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v3, v[4:5]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_waitcnt vmcnt(7)
-; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v10
; VI-NEXT: s_waitcnt vmcnt(6)
-; VI-NEXT: v_or_b32_e32 v4, v4, v11
+; VI-NEXT: v_lshl_or_b32 v4, v10, 8, v11
; VI-NEXT: s_waitcnt vmcnt(5)
; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v12
; VI-NEXT: s_waitcnt vmcnt(4)
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v5, v4
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v7
; VI-NEXT: v_ffbh_u32_e32 v4, v4
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_or_b32_e32 v5, v5, v8
+; VI-NEXT: v_lshl_or_b32 v5, v7, 8, v8
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/ctpop16.ll b/llvm/test/CodeGen/AMDGPU/ctpop16.ll
index 3b3f59363e252..2267294721d88 100644
--- a/llvm/test/CodeGen/AMDGPU/ctpop16.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctpop16.ll
@@ -502,9 +502,8 @@ define amdgpu_kernel void @v_ctpop_v2i16(ptr addrspace(1) noalias %out, ptr addr
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
;
@@ -572,10 +571,9 @@ define amdgpu_kernel void @v_ctpop_v2i16(ptr addrspace(1) noalias %out, ptr addr
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; VI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
+; VI-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -630,17 +628,15 @@ define amdgpu_kernel void @v_ctpop_v4i16(ptr addrspace(1) noalias %out, ptr addr
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
-; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
+; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v3
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
@@ -744,14 +740,12 @@ define amdgpu_kernel void @v_ctpop_v4i16(ptr addrspace(1) noalias %out, ptr addr
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v2, v2, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v3, v3, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v2, v2, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
-; VI-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v3, v3, 0
+; VI-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; VI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -818,29 +812,25 @@ define amdgpu_kernel void @v_ctpop_v8i16(ptr addrspace(1) noalias %out, ptr addr
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; VI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v0
; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: v_bcnt_u32_b32 v4, v4, 0
-; VI-NEXT: v_bcnt_u32_b32 v5, v5, 0
-; VI-NEXT: v_bcnt_u32_b32 v6, v6, 0
-; VI-NEXT: v_bcnt_u32_b32 v7, v7, 0
; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
+; VI-NEXT: v_bcnt_u32_b32 v5, v5, 0
; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; VI-NEXT: v_bcnt_u32_b32 v6, v6, 0
; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
+; VI-NEXT: v_bcnt_u32_b32 v7, v7, 0
; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: v_or_b32_e32 v3, v3, v4
-; VI-NEXT: v_or_b32_e32 v2, v2, v5
-; VI-NEXT: v_or_b32_e32 v1, v1, v6
-; VI-NEXT: v_or_b32_e32 v0, v0, v7
+; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshl_or_b32 v2, v5, 16, v2
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
+; VI-NEXT: v_lshl_or_b32 v0, v7, 16, v0
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
@@ -996,22 +986,18 @@ define amdgpu_kernel void @v_ctpop_v8i16(ptr addrspace(1) noalias %out, ptr addr
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v4, v4, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v5, v5, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v6, v6, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v7, v7, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v4, v4, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v5, v5, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v6, v6, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v3, v3, 0
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v4
-; VI-GISEL-NEXT: v_or_b32_e32 v1, v1, v5
-; VI-GISEL-NEXT: v_or_b32_e32 v2, v2, v6
-; VI-GISEL-NEXT: v_or_b32_e32 v3, v3, v7
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v7, v7, 0
+; VI-GISEL-NEXT: v_lshl_or_b32 v0, v4, 16, v0
+; VI-GISEL-NEXT: v_lshl_or_b32 v1, v5, 16, v1
+; VI-GISEL-NEXT: v_lshl_or_b32 v2, v6, 16, v2
+; VI-GISEL-NEXT: v_lshl_or_b32 v3, v7, 16, v3
; VI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1108,54 +1094,46 @@ define amdgpu_kernel void @v_ctpop_v16i16(ptr addrspace(1) noalias %out, ptr add
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
-; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v0
; VI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v0
; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v6
-; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v5
-; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; VI-NEXT: v_bcnt_u32_b32 v8, v8, 0
-; VI-NEXT: v_bcnt_u32_b32 v9, v9, 0
-; VI-NEXT: v_bcnt_u32_b32 v10, v10, 0
-; VI-NEXT: v_bcnt_u32_b32 v11, v11, 0
; VI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v6
; VI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v5
; VI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v4
; VI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; VI-NEXT: v_bcnt_u32_b32 v8, v8, 0
; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
+; VI-NEXT: v_bcnt_u32_b32 v9, v9, 0
; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; VI-NEXT: v_bcnt_u32_b32 v10, v10, 0
; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
+; VI-NEXT: v_bcnt_u32_b32 v11, v11, 0
; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
; VI-NEXT: v_bcnt_u32_b32 v12, v12, 0
-; VI-NEXT: v_bcnt_u32_b32 v13, v13, 0
-; VI-NEXT: v_bcnt_u32_b32 v14, v14, 0
-; VI-NEXT: v_bcnt_u32_b32 v15, v15, 0
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_bcnt_u32_b32 v7, v7, 0
+; VI-NEXT: v_bcnt_u32_b32 v13, v13, 0
; VI-NEXT: v_bcnt_u32_b32 v6, v6, 0
+; VI-NEXT: v_bcnt_u32_b32 v14, v14, 0
; VI-NEXT: v_bcnt_u32_b32 v5, v5, 0
+; VI-NEXT: v_bcnt_u32_b32 v15, v15, 0
; VI-NEXT: v_bcnt_u32_b32 v4, v4, 0
-; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_or_b32_e32 v3, v3, v8
-; VI-NEXT: v_or_b32_e32 v2, v2, v9
-; VI-NEXT: v_or_b32_e32 v1, v1, v10
-; VI-NEXT: v_or_b32_e32 v0, v0, v11
-; VI-NEXT: v_or_b32_e32 v7, v7, v12
-; VI-NEXT: v_or_b32_e32 v6, v6, v13
-; VI-NEXT: v_or_b32_e32 v5, v5, v14
-; VI-NEXT: v_or_b32_e32 v4, v4, v15
+; VI-NEXT: v_lshl_or_b32 v3, v8, 16, v3
+; VI-NEXT: v_lshl_or_b32 v2, v9, 16, v2
+; VI-NEXT: v_lshl_or_b32 v1, v10, 16, v1
+; VI-NEXT: v_lshl_or_b32 v0, v11, 16, v0
+; VI-NEXT: v_lshl_or_b32 v7, v12, 16, v7
+; VI-NEXT: v_lshl_or_b32 v6, v13, 16, v6
+; VI-NEXT: v_lshl_or_b32 v5, v14, 16, v5
+; VI-NEXT: v_lshl_or_b32 v4, v15, 16, v4
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; VI-NEXT: s_endpgm
@@ -1426,42 +1404,34 @@ define amdgpu_kernel void @v_ctpop_v16i16(ptr addrspace(1) noalias %out, ptr add
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v13, 16, v5
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v14, 16, v6
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v8, v8, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v9, v9, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v10, v10, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v11, v11, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v8, v8, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v9, v9, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v10, v10, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v3, v3, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v11, v11, 0
; VI-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6
; VI-GISEL-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v12, v12, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v13, v13, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v14, v14, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v15, v15, 0
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-GISEL-NEXT: v_bcnt_u32_b32 v4, v4, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v12, v12, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v5, v5, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v13, v13, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v6, v6, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v14, v14, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v7, v7, 0
-; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v8
-; VI-GISEL-NEXT: v_or_b32_e32 v1, v1, v9
-; VI-GISEL-NEXT: v_or_b32_e32 v2, v2, v10
-; VI-GISEL-NEXT: v_or_b32_e32 v3, v3, v11
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v8, 16, v12
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v9, 16, v13
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v10, 16, v14
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v11, 16, v15
-; VI-GISEL-NEXT: v_or_b32_e32 v4, v4, v8
-; VI-GISEL-NEXT: v_or_b32_e32 v5, v5, v9
-; VI-GISEL-NEXT: v_or_b32_e32 v6, v6, v10
-; VI-GISEL-NEXT: v_or_b32_e32 v7, v7, v11
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v15, v15, 0
+; VI-GISEL-NEXT: v_lshl_or_b32 v0, v8, 16, v0
+; VI-GISEL-NEXT: v_lshl_or_b32 v1, v9, 16, v1
+; VI-GISEL-NEXT: v_lshl_or_b32 v2, v10, 16, v2
+; VI-GISEL-NEXT: v_lshl_or_b32 v3, v11, 16, v3
+; VI-GISEL-NEXT: v_lshl_or_b32 v4, v12, 16, v4
+; VI-GISEL-NEXT: v_lshl_or_b32 v5, v13, 16, v5
+; VI-GISEL-NEXT: v_lshl_or_b32 v6, v14, 16, v6
+; VI-GISEL-NEXT: v_lshl_or_b32 v7, v15, 16, v7
; VI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; VI-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
index 60d87fe22f208..5f2f677399ae1 100644
--- a/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
+++ b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
@@ -682,10 +682,8 @@ define amdgpu_kernel void @v_cttz_zero_poison_i16_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
; VI-NEXT: v_ffbl_b32_e32 v3, v2
; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
@@ -805,10 +803,8 @@ define amdgpu_kernel void @v_cttz_zero_poison_i32_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v5, v[6:7]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -967,19 +963,15 @@ define amdgpu_kernel void @v_cttz_zero_poison_i64_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_waitcnt vmcnt(7)
-; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v12
; VI-NEXT: s_waitcnt vmcnt(6)
-; VI-NEXT: v_or_b32_e32 v3, v3, v13
+; VI-NEXT: v_lshl_or_b32 v3, v12, 8, v13
; VI-NEXT: s_waitcnt vmcnt(5)
; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; VI-NEXT: s_waitcnt vmcnt(4)
; VI-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v4, v3
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v6
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_or_b32_e32 v4, v4, v7
+; VI-NEXT: v_lshl_or_b32 v4, v6, 8, v7
; VI-NEXT: v_ffbl_b32_e32 v3, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v3
; VI-NEXT: s_waitcnt vmcnt(1)
@@ -1139,10 +1131,8 @@ define amdgpu_kernel void @v_cttz_i32_sel_eq_neg1(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_load_ubyte v5, v[6:7]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1269,10 +1259,8 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_neg1(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_load_ubyte v5, v[6:7]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1402,10 +1390,8 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %
; VI-NEXT: flat_load_ubyte v5, v[6:7]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1602,10 +1588,8 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %
; VI-NEXT: flat_load_ubyte v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_lshl_or_b32 v2, v4, 8, v2
; VI-NEXT: v_ffbl_b32_e32 v2, v2
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index 0eed0ba50092b..9f2ecf285c7ac 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -1483,7 +1483,6 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned_multiuse(ptr addrspace(1
; VI-NEXT: s_mov_b32 s8, s2
; VI-NEXT: s_mov_b32 s9, s3
; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v6
; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v6
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_lshlrev_b32_e32 v7, 8, v2
@@ -1491,7 +1490,7 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned_multiuse(ptr addrspace(1
; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v4
-; VI-NEXT: v_or_b32_e32 v4, v5, v4
+; VI-NEXT: v_lshl_or_b32 v4, v6, 8, v4
; VI-NEXT: v_or_b32_e32 v5, v7, v3
; VI-NEXT: v_mov_b32_e32 v3, v1
; VI-NEXT: v_perm_b32 v4, v4, v5, s12
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2.ll b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
index 9f1b55ea3b1ef..30f1d49362b42 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
@@ -1497,11 +1497,9 @@ define amdgpu_kernel void @read2_v2i32_align1_odd_offset(ptr addrspace(1) %out)
; GFX9-ALIGNED-NEXT: ds_read_u8 v8, v2 offset:71
; GFX9-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX9-ALIGNED-NEXT: v_or_b32_e32 v1, v1, v6
+; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v0, v3, 8, v0
+; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v1, v1, 8, v6
; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v6, 8, v7
-; GFX9-ALIGNED-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v5
; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
diff --git a/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll b/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
index 217868d5b7b59..9af0548bc43a1 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
@@ -19,8 +19,7 @@ define void @extract_multiple_v16i8(ptr addrspace(1) %out) {
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s0
; GFX9-NEXT: v_perm_b32 v3, v4, v5, s0
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -34,9 +33,8 @@ define void @extract_multiple_v16i8(ptr addrspace(1) %out) {
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
; GFX12-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX12-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
; GFX12-NEXT: s_set_pc_i64 s[30:31]
%ptr = getelementptr inbounds i8, ptr addrspace(3) @lds, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 3f6750546618f..818b5e4154ecc 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -3911,9 +3911,8 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2bf16_sign_v2f64(<2 x bfloat> %m
; GFX8-LABEL: v_copysign_out_v2bf16_mag_v2bf16_sign_v2f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; GFX8-NEXT: v_and_b32_e32 v2, 0x8000, v2
-; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-NEXT: v_lshl_or_b32 v1, v4, 16, v2
; GFX8-NEXT: s_mov_b32 s4, 0x7fff7fff
; GFX8-NEXT: v_bfi_b32 v0, s4, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -7152,14 +7151,12 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4bf16_sign_v4f64(<4 x bfloat> %m
; GFX8-LABEL: v_copysign_out_v4bf16_mag_v4bf16_sign_v4f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; GFX8-NEXT: v_and_b32_e32 v3, 0x8000, v3
-; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v2, v5, 16, v3
; GFX8-NEXT: s_mov_b32 s4, 0x7fff7fff
-; GFX8-NEXT: v_bfi_b32 v0, s4, v0, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v9
; GFX8-NEXT: v_and_b32_e32 v3, 0x8000, v7
-; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX8-NEXT: v_bfi_b32 v0, s4, v0, v2
+; GFX8-NEXT: v_lshl_or_b32 v2, v9, 16, v3
; GFX8-NEXT: v_bfi_b32 v1, s4, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -7989,9 +7986,8 @@ define <2 x bfloat> @v_copysign_v2bf16_0_v2bf64(<2 x double> %sign) {
; GFX8-LABEL: v_copysign_v2bf16_0_v2bf64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v3
; GFX8-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-NEXT: v_lshl_or_b32 v0, v3, 16, v1
; GFX8-NEXT: s_mov_b32 s4, 0x7fff7fff
; GFX8-NEXT: v_bfi_b32 v0, s4, 0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 0ae807783a151..718c55d8ad397 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -913,9 +913,8 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v1, vcc, s4, v1
-; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v1
; VI-NEXT: v_or_b32_e32 v3, v5, v3
-; VI-NEXT: v_or_b32_e32 v4, v0, v4
+; VI-NEXT: v_lshl_or_b32 v4, v1, 12, v0
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; VI-NEXT: v_and_b32_e32 v4, 7, v3
@@ -3049,9 +3048,8 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; VI-NEXT: s_movk_i32 s5, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v6, 12, v3
; VI-NEXT: v_or_b32_e32 v5, v7, v5
-; VI-NEXT: v_or_b32_e32 v6, v2, v6
+; VI-NEXT: v_lshl_or_b32 v6, v3, 12, v2
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; VI-NEXT: v_and_b32_e32 v6, 7, v5
@@ -3087,9 +3085,8 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
; VI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v1, vcc, s5, v1
-; VI-NEXT: v_lshlrev_b32_e32 v5, 12, v1
; VI-NEXT: v_or_b32_e32 v3, v8, v3
-; VI-NEXT: v_or_b32_e32 v5, v0, v5
+; VI-NEXT: v_lshl_or_b32 v5, v1, 12, v0
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; VI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-NEXT: v_and_b32_e32 v5, 7, v3
@@ -3456,9 +3453,8 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f16_sign_v2f64(<2 x half> %mag, <2
; VI-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; VI-NEXT: v_and_b32_e32 v2, 0x8000, v2
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v2
; VI-NEXT: s_mov_b32 s4, 0x7fff7fff
; VI-NEXT: v_bfi_b32 v0, s4, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -4690,9 +4686,8 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI-NEXT: s_movk_i32 s5, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v5, vcc, s5, v5
-; VI-NEXT: v_lshlrev_b32_e32 v9, 12, v5
; VI-NEXT: v_or_b32_e32 v8, v10, v8
-; VI-NEXT: v_or_b32_e32 v9, v4, v9
+; VI-NEXT: v_lshl_or_b32 v9, v5, 12, v4
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; VI-NEXT: v_and_b32_e32 v9, 7, v8
@@ -4728,9 +4723,8 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v8, v5
; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v1, vcc, s5, v1
-; VI-NEXT: v_lshlrev_b32_e32 v8, 12, v1
; VI-NEXT: v_or_b32_e32 v5, v11, v5
-; VI-NEXT: v_or_b32_e32 v8, v0, v8
+; VI-NEXT: v_lshl_or_b32 v8, v1, 12, v0
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; VI-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc
; VI-NEXT: v_and_b32_e32 v8, 7, v5
@@ -4763,9 +4757,8 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v2
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v5, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v8, v2
-; VI-NEXT: v_or_b32_e32 v5, v1, v5
+; VI-NEXT: v_lshl_or_b32 v5, v3, 12, v1
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; VI-NEXT: v_and_b32_e32 v5, 7, v2
@@ -4782,9 +4775,8 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v3
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_mov_b32 s4, 0x7fff7fff
; VI-NEXT: v_bfi_b32 v0, s4, v0, v6
; VI-NEXT: v_bfi_b32 v1, s4, v4, v7
@@ -5839,9 +5831,8 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: s_movk_i32 s5, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v5, vcc, s5, v5
-; VI-NEXT: v_lshlrev_b32_e32 v11, 12, v5
; VI-NEXT: v_or_b32_e32 v10, v12, v10
-; VI-NEXT: v_or_b32_e32 v11, v4, v11
+; VI-NEXT: v_lshl_or_b32 v11, v5, 12, v4
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; VI-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc
; VI-NEXT: v_and_b32_e32 v11, 7, v10
@@ -5877,9 +5868,8 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v10, v6
; VI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v7, vcc, s5, v7
-; VI-NEXT: v_lshlrev_b32_e32 v10, 12, v7
; VI-NEXT: v_or_b32_e32 v6, v13, v6
-; VI-NEXT: v_or_b32_e32 v10, v5, v10
+; VI-NEXT: v_lshl_or_b32 v10, v7, 12, v5
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7
; VI-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; VI-NEXT: v_and_b32_e32 v10, 7, v6
@@ -5912,9 +5902,8 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v7, v6
; VI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v1, vcc, s5, v1
-; VI-NEXT: v_lshlrev_b32_e32 v7, 12, v1
; VI-NEXT: v_or_b32_e32 v6, v10, v6
-; VI-NEXT: v_or_b32_e32 v7, v0, v7
+; VI-NEXT: v_lshl_or_b32 v7, v1, 12, v0
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; VI-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; VI-NEXT: v_and_b32_e32 v7, 7, v6
@@ -5947,9 +5936,8 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v6, v2
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v6, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v7, v2
-; VI-NEXT: v_or_b32_e32 v6, v1, v6
+; VI-NEXT: v_lshl_or_b32 v6, v3, 12, v1
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; VI-NEXT: v_and_b32_e32 v6, 7, v2
@@ -5966,13 +5954,11 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v3
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
; VI-NEXT: v_and_b32_e32 v2, 0x7fff, v4
+; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_mov_b32 s4, 0x7fff7fff
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v2
; VI-NEXT: v_bfi_b32 v0, s4, v0, v8
; VI-NEXT: v_bfi_b32 v1, s4, v1, v9
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -6576,14 +6562,12 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f16_sign_v4f64(<4 x half> %mag, <4
; VI-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; VI-NEXT: v_and_b32_e32 v3, 0x8000, v3
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_lshl_or_b32 v2, v5, 16, v3
; VI-NEXT: s_mov_b32 s4, 0x7fff7fff
-; VI-NEXT: v_bfi_b32 v0, s4, v0, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
; VI-NEXT: v_and_b32_e32 v3, 0x8000, v7
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_bfi_b32 v0, s4, v0, v2
+; VI-NEXT: v_lshl_or_b32 v2, v9, 16, v3
; VI-NEXT: v_bfi_b32 v1, s4, v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -7258,9 +7242,8 @@ define <2 x half> @v_copysign_v2f16_0_v2bf64(<2 x double> %sign) {
; VI-LABEL: v_copysign_v2f16_0_v2bf64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
; VI-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; VI-NEXT: v_or_b32_e32 v0, v1, v0
+; VI-NEXT: v_lshl_or_b32 v0, v3, 16, v1
; VI-NEXT: s_mov_b32 s4, 0x7fff7fff
; VI-NEXT: v_bfi_b32 v0, s4, 0, v0
; VI-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
index f01879d98da41..90c6048e74e3e 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
@@ -8711,10 +8711,9 @@ define half @flat_agent_atomic_fadd_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9090,10 +9089,9 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9472,10 +9470,9 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9832,10 +9829,9 @@ define void @flat_agent_atomic_fadd_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -10199,10 +10195,9 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -10569,10 +10564,9 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -11507,10 +11501,9 @@ define half @flat_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -11882,10 +11875,9 @@ define void @flat_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
index 4e3d7947bfbbd..5ce36037c41b7 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
@@ -6359,10 +6359,9 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6763,10 +6762,9 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7170,10 +7168,9 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7550,10 +7547,9 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_max_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_max_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7942,10 +7938,9 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8337,10 +8332,9 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9340,10 +9334,9 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9740,10 +9733,9 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
index 40f58f5ce5902..01c236cbd27c8 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
@@ -6359,10 +6359,9 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6763,10 +6762,9 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7170,10 +7168,9 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7550,10 +7547,9 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_min_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_min_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7942,10 +7938,9 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8337,10 +8332,9 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9340,10 +9334,9 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9740,10 +9733,9 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
index d2bc7b3f4e48e..5e2a6e56eab91 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
@@ -6142,10 +6142,9 @@ define half @flat_agent_atomic_fsub_ret_f16(ptr %ptr, half %val) #0 {
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6521,10 +6520,9 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6903,10 +6901,9 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_neg(ptr %ptr, half %val)
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7263,10 +7260,9 @@ define void @flat_agent_atomic_fsub_noret_f16(ptr %ptr, half %val) #0 {
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7630,10 +7626,9 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %val
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8000,10 +7995,9 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_neg(ptr %ptr, half %val
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8938,10 +8932,9 @@ define half @flat_system_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9313,10 +9306,9 @@ define void @flat_system_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %va
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
index 13e4206ab7f57..d1467f5615c7b 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
@@ -3527,12 +3527,10 @@ define <4 x half> @v_fneg_fmad_v4f32(<4 x half> %a, <4 x half> %b, <4 x half> %c
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; VI-NEXT: v_fma_f16 v7, v9, v8, v7
-; VI-NEXT: v_fma_f16 v0, v0, v2, v4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; VI-NEXT: v_fma_f16 v1, v1, v3, v5
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_fma_f16 v0, v0, v2, v4
+; VI-NEXT: v_lshl_or_b32 v0, v7, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; VI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -3612,12 +3610,10 @@ define <4 x half> @v_fneg_fmad_v4f32_nsz(<4 x half> %a, <4 x half> %b, <4 x half
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; VI-NEXT: v_fma_f16 v7, v9, -v8, -v7
-; VI-NEXT: v_fma_f16 v0, v0, -v2, -v4
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; VI-NEXT: v_fma_f16 v1, v1, -v3, -v5
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_fma_f16 v0, v0, -v2, -v4
+; VI-NEXT: v_lshl_or_b32 v0, v7, 16, v0
+; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fneg_fmad_v4f32_nsz:
@@ -3988,9 +3984,8 @@ define half @v_fneg_fp_round_f64_to_f16(double %a) #0 {
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v3
-; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v5, v2
-; VI-NEXT: v_or_b32_e32 v4, v0, v4
+; VI-NEXT: v_lshl_or_b32 v4, v3, 12, v0
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-NEXT: v_and_b32_e32 v4, 7, v2
@@ -4137,9 +4132,8 @@ define half @v_fneg_fp_round_fneg_f64_to_f16(double %a) #0 {
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v3
-; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v5, v2
-; VI-NEXT: v_or_b32_e32 v4, v0, v4
+; VI-NEXT: v_lshl_or_b32 v4, v3, 12, v0
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-NEXT: v_and_b32_e32 v4, 7, v2
@@ -4292,9 +4286,8 @@ define { half, double } @v_fneg_fp_round_store_use_fneg_f64_to_f16(double %a) #0
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v5, vcc, s4, v5
-; VI-NEXT: v_lshlrev_b32_e32 v6, 12, v5
; VI-NEXT: v_or_b32_e32 v4, v7, v4
-; VI-NEXT: v_or_b32_e32 v6, v0, v6
+; VI-NEXT: v_lshl_or_b32 v6, v5, 12, v0
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; VI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; VI-NEXT: v_and_b32_e32 v6, 7, v4
@@ -4451,9 +4444,8 @@ define { half, double } @v_fneg_fp_round_multi_use_fneg_f64_to_f16(double %a, do
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, s4, v6
-; VI-NEXT: v_lshlrev_b32_e32 v7, 12, v6
; VI-NEXT: v_or_b32_e32 v5, v8, v5
-; VI-NEXT: v_or_b32_e32 v7, v4, v7
+; VI-NEXT: v_lshl_or_b32 v7, v6, 12, v4
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6
; VI-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
; VI-NEXT: v_and_b32_e32 v7, 7, v5
@@ -4608,9 +4600,8 @@ define { half, half } @v_fneg_multi_use_fp_round_fneg_f64_to_f16(double %a) #0 {
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v3
-; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v5, v2
-; VI-NEXT: v_or_b32_e32 v4, v0, v4
+; VI-NEXT: v_lshl_or_b32 v4, v3, 12, v0
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-NEXT: v_and_b32_e32 v4, 7, v2
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index a893711ce0942..690983f0be8e1 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -2020,10 +2020,9 @@ define <2 x i8> @test_s_signed_v2f64_v2i8(<2 x double> inreg %f) {
; GFX11-NEXT: s_movk_i32 s0, 0xff80
; GFX11-NEXT: v_med3_i32 v2, v0, s0, 0x7f
; GFX11-NEXT: v_med3_i32 v0, v1, s0, 0x7f
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v2
-; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 8, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_v2f64_v2i8:
@@ -2039,10 +2038,9 @@ define <2 x i8> @test_s_signed_v2f64_v2i8(<2 x double> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT: v_med3_i32 v2, v0, s0, 0x7f
; GFX12-ISEL-NEXT: v_med3_i32 v0, v1, s0, 0x7f
-; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v2
-; GFX12-ISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-ISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX12-ISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX12-ISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX12-ISEL-NEXT: v_lshl_or_b32 v0, v2, 8, v0
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_v2f64_v2i8:
@@ -3566,24 +3564,23 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-FAKE16-LABEL: test_s_signed_v4f16_v4i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, s1
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s2
+; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s2
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, s1
; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-FAKE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
+; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-FAKE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
+; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX11-FAKE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX11-FAKE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
; GFX11-FAKE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3597,24 +3594,23 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-TRUE16-LABEL: test_s_signed_v4f16_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
+; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-TRUE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
+; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
+; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v0, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3632,27 +3628,25 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, s1
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s2
+; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s2
; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, s1
; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-FAKE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX12-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
+; GFX12-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
+; GFX12-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX12-FAKE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX12-FAKE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v0, v1
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
; GFX12-FAKE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3670,27 +3664,25 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
+; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-TRUE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
+; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
+; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX12-TRUE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v0, v1
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
; GFX12-TRUE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -6970,18 +6962,17 @@ define <4 x i8> @test_s_signed_v4f32_v4i8(<4 x float> inreg %f) {
; GFX11-LABEL: test_s_signed_v4f32_v4i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_i32_f32_e32 v0, s3
; GFX11-NEXT: v_cvt_i32_f32_e32 v1, s2
; GFX11-NEXT: s_movk_i32 s2, 0xff80
+; GFX11-NEXT: v_cvt_i32_f32_e32 v0, s3
; GFX11-NEXT: v_cvt_i32_f32_e32 v2, s1
; GFX11-NEXT: v_cvt_i32_f32_e32 v3, s0
-; GFX11-NEXT: v_med3_i32 v0, v0, s2, 0x7f
; GFX11-NEXT: v_med3_i32 v1, v1, s2, 0x7f
+; GFX11-NEXT: v_med3_i32 v0, v0, s2, 0x7f
; GFX11-NEXT: v_med3_i32 v2, v2, s2, 0x7f
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX11-NEXT: v_lshl_or_b32 v2, v0, 8, v1
; GFX11-NEXT: v_med3_i32 v0, v3, s2, 0x7f
; GFX11-NEXT: v_and_b32_e32 v1, 0xff00, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -7000,20 +6991,19 @@ define <4 x i8> @test_s_signed_v4f32_v4i8(<4 x float> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT: v_mov_b32_e32 v0, 0x7f
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s3, s3
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s2, s2
; GFX12-ISEL-NEXT: s_cvt_i32_f32 s1, s1
+; GFX12-ISEL-NEXT: s_cvt_i32_f32 s2, s2
+; GFX12-ISEL-NEXT: s_cvt_i32_f32 s3, s3
; GFX12-ISEL-NEXT: s_cvt_i32_f32 s0, s0
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_med3_i32 v1, 0xffffff80, s3, v0
-; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX12-ISEL-NEXT: v_med3_i32 v2, 0xffffff80, s2, v0
; GFX12-ISEL-NEXT: v_med3_i32 v3, 0xffffff80, s1, v0
+; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX12-ISEL-NEXT: v_med3_i32 v2, 0xffffff80, s2, v0
+; GFX12-ISEL-NEXT: v_med3_i32 v1, 0xffffff80, s3, v0
; GFX12-ISEL-NEXT: v_med3_i32 v0, 0xffffff80, s0, v0
; GFX12-ISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX12-ISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-ISEL-NEXT: v_or_b32_e32 v2, v2, v1
+; GFX12-ISEL-NEXT: v_lshl_or_b32 v2, v1, 8, v2
; GFX12-ISEL-NEXT: v_and_b32_e32 v1, 0xff00, v3
; GFX12-ISEL-NEXT: v_or_b32_e32 v0, v0, v3
; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v2
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index 14094c50e2290..c3f7283bc00f8 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -1891,12 +1891,11 @@ define <2 x i8> @test_s_unsigned_v2f64_v2i8(<2 x double> inreg %f) {
; GFX9-LABEL: test_s_unsigned_v2f64_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_u32_f64_e32 v1, s[18:19]
; GFX9-NEXT: v_cvt_u32_f64_e32 v0, s[16:17]
-; GFX9-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX9-NEXT: v_cvt_u32_f64_e32 v1, s[18:19]
; GFX9-NEXT: v_min_u32_e32 v0, 0xff, v0
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_unsigned_v2f64_v2i8:
@@ -1906,8 +1905,7 @@ define <2 x i8> @test_s_unsigned_v2f64_v2i8(<2 x double> inreg %f) {
; GFX11-NEXT: v_cvt_u32_f64_e32 v2, s[0:1]
; GFX11-NEXT: v_min_u32_e32 v1, 0xff, v0
; GFX11-NEXT: v_min_u32_e32 v0, 0xff, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v1
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 8, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_unsigned_v2f64_v2i8:
@@ -1921,8 +1919,7 @@ define <2 x i8> @test_s_unsigned_v2f64_v2i8(<2 x double> inreg %f) {
; GFX12-ISEL-NEXT: v_cvt_u32_f64_e32 v2, s[0:1]
; GFX12-ISEL-NEXT: v_min_u32_e32 v1, 0xff, v0
; GFX12-ISEL-NEXT: v_min_u32_e32 v0, 0xff, v2
-; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v1
-; GFX12-ISEL-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX12-ISEL-NEXT: v_lshl_or_b32 v0, v1, 8, v0
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_unsigned_v2f64_v2i8:
@@ -3280,14 +3277,13 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
; GFX9-NEXT: s_lshr_b32 s5, s17, 16
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_cvt_u16_f16_e32 v3, s5
; GFX9-NEXT: v_cvt_u16_f16_e32 v2, s17
-; GFX9-NEXT: v_min_u32_sdwa v3, v3, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_cvt_u16_f16_e32 v3, s5
; GFX9-NEXT: v_min_u32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX9-NEXT: v_min_u32_sdwa v3, v3, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s16
; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3312,8 +3308,7 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v0, 8, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3339,8 +3334,7 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v0, 8, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3372,8 +3366,7 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v0, 8, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3405,8 +3398,7 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v2, v0, 8, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -5394,30 +5386,27 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_lshr_b32 s5, s18, 16
+; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s18
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
-; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s18
-; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: s_lshr_b32 s5, s19, 16
-; GFX9-NEXT: v_or_b32_e32 v8, v0, v1
-; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
+; GFX9-NEXT: v_lshl_or_b32 v8, v1, 8, v0
; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s19
+; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
+; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: s_lshr_b32 s5, s17, 16
-; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_cvt_u16_f16_e32 v2, s5
-; GFX9-NEXT: v_or_b32_e32 v6, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v6, v1, 8, v0
; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s17
-; GFX9-NEXT: v_min_u32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_cvt_u16_f16_e32 v2, s5
; GFX9-NEXT: s_lshr_b32 s5, s16, 16
; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX9-NEXT: v_min_u32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_cvt_u16_f16_e32 v7, s5
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v2, v0, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 8, v0
; GFX9-NEXT: v_min_u32_sdwa v7, v7, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -5447,38 +5436,35 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v5, s1
; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v6, s1
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_min_u32_e32 v7, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v1, v0
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 8, v1
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v4, 8, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v1, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v8
@@ -5498,38 +5484,35 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s1
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v6.l, s1
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX11-TRUE16-NEXT: v_min_u32_e32 v7, 0xff, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX11-TRUE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v1, v0
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v0, 8, v1
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v3
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v4, 8, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 8, v5
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v3, v7
; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v3, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v1, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v8
@@ -5554,39 +5537,36 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v5, s1
; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v6, s1
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX12-FAKE16-NEXT: v_min_u32_e32 v7, 0xff, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX12-FAKE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, v1, v0
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 8, v1
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s0
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v6
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v6, v4, 8, v7
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 8, v5
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, v1, v4
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX12-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v8
@@ -5611,39 +5591,36 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s1
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v6.l, s1
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX12-TRUE16-NEXT: v_min_u32_e32 v7, 0xff, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX12-TRUE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, v1, v0
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v8, v0, 8, v1
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v5, v3
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v6
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v6, v4, 8, v7
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 8, v5
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, v3, v7
; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, v3, v7
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, v1, v4
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX12-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v8
@@ -6395,15 +6372,14 @@ define <4 x i8> @test_s_unsigned_v4f32_v4i8(<4 x float> inreg %f) {
; GFX9-LABEL: test_s_unsigned_v4f32_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_u32_f32_e32 v3, s19
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, s18
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, s19
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, s17
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, s16
-; GFX9-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX9-NEXT: v_min_u32_e32 v2, 0xff, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX9-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX9-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX9-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -6422,8 +6398,7 @@ define <4 x i8> @test_s_unsigned_v4f32_v4i8(<4 x float> inreg %f) {
; GFX11-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-NEXT: v_min_u32_e32 v3, 0xff, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX11-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX11-NEXT: v_lshl_or_b32 v2, v0, 8, v1
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, s0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2
diff --git a/llvm/test/CodeGen/AMDGPU/function-args.ll b/llvm/test/CodeGen/AMDGPU/function-args.ll
index 07dcad993ffe2..6ebfb95856361 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args.ll
@@ -1049,34 +1049,19 @@ define void @void_func_v4i8(<4 x i8> %arg0) #0 {
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: void_func_v4i8:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v0, v1, s4
-; VI-NEXT: v_perm_b32 v1, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: s_mov_b64 s[4:5], 0
-; VI-NEXT: s_mov_b32 s7, 0xf000
-; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: void_func_v4i8:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX9-NEXT: v_perm_b32 v1, v2, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: s_mov_b64 s[4:5], 0
-; GFX9-NEXT: s_mov_b32 s7, 0xf000
-; GFX9-NEXT: s_mov_b32 s6, -1
-; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: void_func_v4i8:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX89-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX89-NEXT: v_perm_b32 v1, v2, v3, s4
+; GFX89-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX89-NEXT: s_mov_b64 s[4:5], 0
+; GFX89-NEXT: s_mov_b32 s7, 0xf000
+; GFX89-NEXT: s_mov_b32 s6, -1
+; GFX89-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX89-NEXT: s_waitcnt vmcnt(0)
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: void_func_v4i8:
; GFX11: ; %bb.0:
@@ -1116,38 +1101,21 @@ define void @void_func_v5i8(<5 x i8> %arg0) #0 {
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: void_func_v5i8:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v0, v1, s4
-; VI-NEXT: v_perm_b32 v1, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: s_mov_b64 s[4:5], 4
-; VI-NEXT: s_mov_b32 s7, 0xf000
-; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
-; VI-NEXT: buffer_store_byte v4, off, s[4:7], 0
-; VI-NEXT: s_mov_b64 s[4:5], 0
-; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: void_func_v5i8:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX9-NEXT: v_perm_b32 v1, v2, v3, s4
-; GFX9-NEXT: s_mov_b64 s[4:5], 4
-; GFX9-NEXT: s_mov_b32 s7, 0xf000
-; GFX9-NEXT: s_mov_b32 s6, -1
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: buffer_store_byte v4, off, s[4:7], 0
-; GFX9-NEXT: s_mov_b64 s[4:5], 0
-; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: void_func_v5i8:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX89-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX89-NEXT: v_perm_b32 v1, v2, v3, s4
+; GFX89-NEXT: s_mov_b64 s[4:5], 4
+; GFX89-NEXT: s_mov_b32 s7, 0xf000
+; GFX89-NEXT: s_mov_b32 s6, -1
+; GFX89-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX89-NEXT: buffer_store_byte v4, off, s[4:7], 0
+; GFX89-NEXT: s_mov_b64 s[4:5], 0
+; GFX89-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX89-NEXT: s_waitcnt vmcnt(0)
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: void_func_v5i8:
; GFX11: ; %bb.0:
@@ -1196,41 +1164,22 @@ define void @void_func_v8i8(<8 x i8> %arg0) #0 {
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: void_func_v8i8:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v4, v4, v5, s4
-; VI-NEXT: v_perm_b32 v5, v6, v7, s4
-; VI-NEXT: v_perm_b32 v0, v0, v1, s4
-; VI-NEXT: v_perm_b32 v1, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v4, v4, v5
-; VI-NEXT: v_or_b32_e32 v3, v0, v1
-; VI-NEXT: s_mov_b64 s[4:5], 0
-; VI-NEXT: s_mov_b32 s7, 0xf000
-; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: buffer_store_dwordx2 v[3:4], off, s[4:7], 0
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: void_func_v8i8:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_perm_b32 v5, v6, v7, s4
-; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX9-NEXT: v_perm_b32 v1, v2, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v0
-; GFX9-NEXT: s_mov_b64 s[4:5], 0
-; GFX9-NEXT: s_mov_b32 s7, 0xf000
-; GFX9-NEXT: s_mov_b32 s6, -1
-; GFX9-NEXT: buffer_store_dwordx2 v[3:4], off, s[4:7], 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: void_func_v8i8:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX89-NEXT: v_perm_b32 v4, v4, v5, s4
+; GFX89-NEXT: v_perm_b32 v5, v6, v7, s4
+; GFX89-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX89-NEXT: v_perm_b32 v1, v2, v3, s4
+; GFX89-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX89-NEXT: v_lshl_or_b32 v3, v1, 16, v0
+; GFX89-NEXT: s_mov_b64 s[4:5], 0
+; GFX89-NEXT: s_mov_b32 s7, 0xf000
+; GFX89-NEXT: s_mov_b32 s6, -1
+; GFX89-NEXT: buffer_store_dwordx2 v[3:4], off, s[4:7], 0
+; GFX89-NEXT: s_waitcnt vmcnt(0)
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: void_func_v8i8:
; GFX11: ; %bb.0:
@@ -1297,55 +1246,28 @@ define void @void_func_v16i8(<16 x i8> %arg0) #0 {
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; VI-LABEL: void_func_v16i8:
-; VI: ; %bb.0:
-; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v12, v12, v13, s4
-; VI-NEXT: v_perm_b32 v13, v14, v15, s4
-; VI-NEXT: v_perm_b32 v8, v8, v9, s4
-; VI-NEXT: v_perm_b32 v9, v10, v11, s4
-; VI-NEXT: v_perm_b32 v4, v4, v5, s4
-; VI-NEXT: v_perm_b32 v5, v6, v7, s4
-; VI-NEXT: v_perm_b32 v0, v0, v1, s4
-; VI-NEXT: v_perm_b32 v1, v2, v3, s4
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; VI-NEXT: v_or_b32_e32 v12, v12, v13
-; VI-NEXT: v_or_b32_e32 v11, v8, v9
-; VI-NEXT: v_or_b32_e32 v10, v4, v5
-; VI-NEXT: v_or_b32_e32 v9, v0, v1
-; VI-NEXT: s_mov_b64 s[4:5], 0
-; VI-NEXT: s_mov_b32 s7, 0xf000
-; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: buffer_store_dwordx4 v[9:12], off, s[4:7], 0
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX9-LABEL: void_func_v16i8:
-; GFX9: ; %bb.0:
-; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX9-NEXT: v_perm_b32 v13, v14, v15, s4
-; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX9-NEXT: v_perm_b32 v9, v10, v11, s4
-; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_perm_b32 v5, v6, v7, s4
-; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX9-NEXT: v_perm_b32 v1, v2, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
-; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v8
-; GFX9-NEXT: v_lshl_or_b32 v10, v5, 16, v4
-; GFX9-NEXT: v_lshl_or_b32 v9, v1, 16, v0
-; GFX9-NEXT: s_mov_b64 s[4:5], 0
-; GFX9-NEXT: s_mov_b32 s7, 0xf000
-; GFX9-NEXT: s_mov_b32 s6, -1
-; GFX9-NEXT: buffer_store_dwordx4 v[9:12], off, s[4:7], 0
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: s_setpc_b64 s[30:31]
+; GFX89-LABEL: void_func_v16i8:
+; GFX89: ; %bb.0:
+; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX89-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX89-NEXT: v_perm_b32 v12, v12, v13, s4
+; GFX89-NEXT: v_perm_b32 v13, v14, v15, s4
+; GFX89-NEXT: v_perm_b32 v8, v8, v9, s4
+; GFX89-NEXT: v_perm_b32 v9, v10, v11, s4
+; GFX89-NEXT: v_perm_b32 v4, v4, v5, s4
+; GFX89-NEXT: v_perm_b32 v5, v6, v7, s4
+; GFX89-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX89-NEXT: v_perm_b32 v1, v2, v3, s4
+; GFX89-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX89-NEXT: v_lshl_or_b32 v11, v9, 16, v8
+; GFX89-NEXT: v_lshl_or_b32 v10, v5, 16, v4
+; GFX89-NEXT: v_lshl_or_b32 v9, v1, 16, v0
+; GFX89-NEXT: s_mov_b64 s[4:5], 0
+; GFX89-NEXT: s_mov_b32 s7, 0xf000
+; GFX89-NEXT: s_mov_b32 s6, -1
+; GFX89-NEXT: buffer_store_dwordx4 v[9:12], off, s[4:7], 0
+; GFX89-NEXT: s_waitcnt vmcnt(0)
+; GFX89-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: void_func_v16i8:
; GFX11-TRUE16: ; %bb.0:
@@ -1487,40 +1409,36 @@ define void @void_func_v32i8(<32 x i8> %arg0) #0 {
; VI-NEXT: v_perm_b32 v8, v8, v9, s8
; VI-NEXT: v_perm_b32 v9, v10, v11, s8
; VI-NEXT: buffer_load_ubyte v10, off, s[0:3], s32
+; VI-NEXT: v_perm_b32 v12, v12, v13, s8
+; VI-NEXT: v_perm_b32 v13, v14, v15, s8
; VI-NEXT: v_perm_b32 v0, v0, v1, s8
; VI-NEXT: v_perm_b32 v1, v2, v3, s8
; VI-NEXT: v_perm_b32 v2, v26, v27, s8
-; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; VI-NEXT: v_perm_b32 v12, v12, v13, s8
-; VI-NEXT: v_perm_b32 v13, v14, v15, s8
-; VI-NEXT: v_perm_b32 v4, v4, v5, s8
-; VI-NEXT: v_perm_b32 v5, v6, v7, s8
; VI-NEXT: v_perm_b32 v3, v22, v23, s8
-; VI-NEXT: v_perm_b32 v14, v16, v17, s8
; VI-NEXT: v_perm_b32 v15, v18, v19, s8
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v2
-; VI-NEXT: v_or_b32_e32 v2, v8, v9
+; VI-NEXT: v_perm_b32 v4, v4, v5, s8
+; VI-NEXT: v_perm_b32 v5, v6, v7, s8
; VI-NEXT: v_perm_b32 v7, v28, v29, s8
; VI-NEXT: v_perm_b32 v6, v24, v25, s8
; VI-NEXT: v_perm_b32 v11, v20, v21, s8
-; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_perm_b32 v14, v16, v17, s8
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v2
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_lshl_or_b32 v2, v9, 16, v8
; VI-NEXT: s_mov_b64 s[4:5], 16
; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1
-; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v1
-; VI-NEXT: v_or_b32_e32 v1, v4, v5
+; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v4
; VI-NEXT: v_or_b32_e32 v6, v6, v17
; VI-NEXT: v_or_b32_e32 v5, v11, v18
; VI-NEXT: v_or_b32_e32 v4, v14, v15
-; VI-NEXT: v_or_b32_e32 v3, v12, v13
+; VI-NEXT: v_lshl_or_b32 v3, v13, 16, v12
; VI-NEXT: v_or_b32_e32 v0, v0, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v10, s8
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
index dbf99aa1c8577..9a6825fdae9dd 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
@@ -9230,10 +9230,9 @@ define half @global_agent_atomic_fadd_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9745,10 +9744,9 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -10266,10 +10264,9 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -10760,10 +10757,9 @@ define void @global_agent_atomic_fadd_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -11259,10 +11255,9 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -11764,10 +11759,9 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -13040,10 +13034,9 @@ define half @global_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -13549,10 +13542,9 @@ define void @global_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
index 93443914d3f97..681519b86e88b 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
@@ -4782,10 +4782,9 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -5234,10 +5233,9 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -5691,10 +5689,9 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6121,10 +6118,9 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_max_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_max_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6561,10 +6557,9 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7005,10 +7000,9 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8132,10 +8126,9 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8582,10 +8575,9 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
index b8217cf862b3a..79704b99691b2 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
@@ -4782,10 +4782,9 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -5234,10 +5233,9 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -5691,10 +5689,9 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6121,10 +6118,9 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_min_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_min_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6561,10 +6557,9 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7005,10 +7000,9 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8132,10 +8126,9 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8582,10 +8575,9 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
-; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
+; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
+; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
index 4ab68e8822676..16ded66cf0106 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
@@ -5514,10 +5514,9 @@ define half @global_agent_atomic_fsub_ret_f16(ptr addrspace(1) %ptr, half %val)
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -5941,10 +5940,9 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %p
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6373,10 +6371,9 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_neg(ptr addrspace(1) %p
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6783,10 +6780,9 @@ define void @global_agent_atomic_fsub_noret_f16(ptr addrspace(1) %ptr, half %val
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7198,10 +7194,9 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7617,10 +7612,9 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_neg(ptr addrspace(1)
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8679,10 +8673,9 @@ define half @global_system_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
+; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
+; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9104,10 +9097,9 @@ define void @global_system_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
index a6bcafd0361ff..a3499833115ef 100644
--- a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
@@ -23,9 +23,7 @@ define void @test_i8load_v4i8store(ptr addrspace(1) %ptr_a, ptr addrspace(1) %pt
; GCN-SDAG-FAKE16-NEXT: v_perm_b32 v1, v10, v7, 0xc0c0004
; GCN-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GCN-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v6, v0
-; GCN-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GCN-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
+; GCN-SDAG-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GCN-SDAG-FAKE16-NEXT: global_store_b32 v[8:9], v0, off
; GCN-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -61,9 +59,7 @@ define void @test_i8load_v4i8store(ptr addrspace(1) %ptr_a, ptr addrspace(1) %pt
; GCN-SDAG-REAL16-NEXT: v_perm_b32 v1, v10, v7, 0xc0c0004
; GCN-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GCN-SDAG-REAL16-NEXT: v_or_b16 v0.l, v6.l, v0.l
-; GCN-SDAG-REAL16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GCN-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GCN-SDAG-REAL16-NEXT: v_or_b32_e32 v0, v1, v0
+; GCN-SDAG-REAL16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GCN-SDAG-REAL16-NEXT: global_store_b32 v[8:9], v0, off
; GCN-SDAG-REAL16-NEXT: s_set_pc_i64 s[30:31]
%a = load i8, ptr addrspace(1) %ptr_a
diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll
index b67c40b2d8333..bddcd2ff4e329 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll
@@ -2759,14 +2759,13 @@ define amdgpu_kernel void @udot4_acc8_vecMul(ptr addrspace(1) %src1,
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-DL-FAKE16-NEXT: v_or_b32_e32 v6, v6, v5
; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-DL-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 8, v6
-; GFX11-DL-FAKE16-NEXT: v_add_nc_u16 v0, v0, v6
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT: v_add_nc_u16 v0, v0, v6
; GFX11-DL-FAKE16-NEXT: v_mad_u16 v0, v4, v7, v0
+; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-DL-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
; GFX11-DL-FAKE16-NEXT: global_store_b8 v2, v0, s[4:5]
; GFX11-DL-FAKE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index 3ef7238576a65..96dd8bd52dbf3 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -720,17 +720,16 @@ define <2 x i16> @clpeak_imad_pat_v2i16(<2 x i16> %x, <2 x i16> %y) {
; GFX8-SDAG-NEXT: v_add_u16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v0, v3
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, v0
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v2, v1
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, v0
; GFX8-SDAG-NEXT: v_mad_u16 v2, v2, v1, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v3
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v2, v1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v0, v4, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v1, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v2
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v3
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_imad_pat_v2i16:
@@ -959,22 +958,21 @@ define <3 x i16> @clpeak_imad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) {
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-SDAG-NEXT: v_add_u16_e32 v1, 1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v6, v0, v5
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v5, v0
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v3
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v8, v4, v2
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v5, v0
; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v2, v4
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v3
; GFX8-SDAG-NEXT: v_mad_u16 v1, v1, v3, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v5
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v4, v2
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; GFX8-SDAG-NEXT: v_mad_u16 v3, v0, v6, v0
; GFX8-SDAG-NEXT: v_mad_u16 v4, v2, v8, v2
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v3, v0, v3
; GFX8-SDAG-NEXT: v_mad_u16 v5, v1, v7, v1
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v3, v0, v3
; GFX8-SDAG-NEXT: v_mad_u16 v2, v4, v2, v4
; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, v5
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_imad_pat_v3i16:
@@ -1480,36 +1478,34 @@ define <4 x i16> @clpeak_imad_pat_v4i16(<4 x i16> %x, <4 x i16> %y) {
; GFX8-SDAG: ; %bb.0: ; %entry
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_mov_b32_e32 v6, 1
+; GFX8-SDAG-NEXT: v_add_u16_e32 v4, 1, v1
; GFX8-SDAG-NEXT: v_add_u16_e32 v5, 1, v0
; GFX8-SDAG-NEXT: v_add_u16_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX8-SDAG-NEXT: v_add_u16_e32 v4, 1, v1
; GFX8-SDAG-NEXT: v_add_u16_sdwa v1, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v9, v0, v8
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v8, v0
+; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v6
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v9, v0, v8
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v10, v5, v2
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v11, v4, v3
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v8, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v1, v6, v1
-; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v3, v4
; GFX8-SDAG-NEXT: v_mad_u16 v5, v5, v2, v5
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v8
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v11, v4, v3
+; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v3, v4
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v6
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v8
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v5, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v3, v4, v3
; GFX8-SDAG-NEXT: v_mad_u16 v4, v0, v9, v0
; GFX8-SDAG-NEXT: v_mad_u16 v5, v1, v7, v1
; GFX8-SDAG-NEXT: v_mad_u16 v7, v2, v10, v2
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, v4
; GFX8-SDAG-NEXT: v_mad_u16 v6, v3, v11, v3
-; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, v5
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, v4
; GFX8-SDAG-NEXT: v_mad_u16 v2, v7, v2, v7
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, v5
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX8-SDAG-NEXT: v_mad_u16 v2, v6, v3, v6
-; GFX8-SDAG-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_imad_pat_v4i16:
@@ -2241,17 +2237,16 @@ define <2 x i16> @clpeak_umad_pat_v2i16(<2 x i16> %x, <2 x i16> %y) {
; GFX8-SDAG-NEXT: v_add_u16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v0, v3
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, v0
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v2, v1
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, v0
; GFX8-SDAG-NEXT: v_mad_u16 v2, v2, v1, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v3
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v2, v1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v0, v4, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v1, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v2
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v3
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_umad_pat_v2i16:
@@ -2480,22 +2475,21 @@ define <3 x i16> @clpeak_umad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) {
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-SDAG-NEXT: v_add_u16_e32 v1, 1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v6, v0, v5
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v5, v0
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v3
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v8, v4, v2
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v5, v0
; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v2, v4
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v3
; GFX8-SDAG-NEXT: v_mad_u16 v1, v1, v3, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v5
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v4, v2
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; GFX8-SDAG-NEXT: v_mad_u16 v3, v0, v6, v0
; GFX8-SDAG-NEXT: v_mad_u16 v4, v2, v8, v2
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v3, v0, v3
; GFX8-SDAG-NEXT: v_mad_u16 v5, v1, v7, v1
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v3, v0, v3
; GFX8-SDAG-NEXT: v_mad_u16 v2, v4, v2, v4
; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, v5
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_umad_pat_v3i16:
@@ -3001,36 +2995,34 @@ define <4 x i16> @clpeak_umad_pat_v4i16(<4 x i16> %x, <4 x i16> %y) {
; GFX8-SDAG: ; %bb.0: ; %entry
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_mov_b32_e32 v6, 1
+; GFX8-SDAG-NEXT: v_add_u16_e32 v4, 1, v1
; GFX8-SDAG-NEXT: v_add_u16_e32 v5, 1, v0
; GFX8-SDAG-NEXT: v_add_u16_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX8-SDAG-NEXT: v_add_u16_e32 v4, 1, v1
; GFX8-SDAG-NEXT: v_add_u16_sdwa v1, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v9, v0, v8
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v8, v0
+; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v6
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v9, v0, v8
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v10, v5, v2
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v11, v4, v3
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v8, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v1, v6, v1
-; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v3, v4
; GFX8-SDAG-NEXT: v_mad_u16 v5, v5, v2, v5
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v8
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v11, v4, v3
+; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v3, v4
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v6
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v8
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v5, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v3, v4, v3
; GFX8-SDAG-NEXT: v_mad_u16 v4, v0, v9, v0
; GFX8-SDAG-NEXT: v_mad_u16 v5, v1, v7, v1
; GFX8-SDAG-NEXT: v_mad_u16 v7, v2, v10, v2
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, v4
; GFX8-SDAG-NEXT: v_mad_u16 v6, v3, v11, v3
-; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, v5
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, v4
; GFX8-SDAG-NEXT: v_mad_u16 v2, v7, v2, v7
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, v5
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX8-SDAG-NEXT: v_mad_u16 v2, v6, v3, v6
-; GFX8-SDAG-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_umad_pat_v4i16:
@@ -10982,27 +10974,26 @@ define <2 x i16> @clpeak_imad_pat_v2i16_x2(<2 x i16> %x, <2 x i16> %y) {
; GFX8-SDAG-NEXT: v_mad_u16 v4, v0, v3, v0
; GFX8-SDAG-NEXT: v_mad_u16 v5, v2, v1, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v4, v3
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, 1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v5, v1
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, 1
; GFX8-SDAG-NEXT: v_mad_u16 v1, v2, v1, 1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v4, v0, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v5, v1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v2, v4
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, 1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v3, v3, v5
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, 1
; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, 1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v2, v0
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v0
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v3, v1
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; GFX8-SDAG-NEXT: v_mad_u16 v2, v0, v4, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v1, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v2
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v3
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_imad_pat_v2i16_x2:
@@ -11331,27 +11322,26 @@ define <2 x i16> @clpeak_umad_pat_v2i16_x2(<2 x i16> %x, <2 x i16> %y) {
; GFX8-SDAG-NEXT: v_mad_u16 v4, v0, v3, v0
; GFX8-SDAG-NEXT: v_mad_u16 v5, v2, v1, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v4, v3
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, 1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v5, v1
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, 1
; GFX8-SDAG-NEXT: v_mad_u16 v1, v2, v1, 1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v4, v0, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v5, v1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v2, v4
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, 1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v3, v3, v5
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, 1
; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, 1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v2, v0
-; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v0
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v3, v1
+; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; GFX8-SDAG-NEXT: v_mad_u16 v2, v0, v4, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v1, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v2
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v3
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_umad_pat_v2i16_x2:
@@ -11618,8 +11608,7 @@ define <2 x i16> @multi_use_mul_mad_i16_var(i16 %x, i16 %y, i16 %z0, i16 %z1) {
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_mad_u16 v3, v0, v1, v3
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v1, v2
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v3
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: multi_use_mul_mad_i16_var:
@@ -11627,8 +11616,7 @@ define <2 x i16> @multi_use_mul_mad_i16_var(i16 %x, i16 %y, i16 %z0, i16 %z1) {
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_mad_u16 v2, v0, v1, v2
; GFX8-GISEL-NEXT: v_mad_u16 v0, v0, v1, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: multi_use_mul_mad_i16_var:
@@ -12101,14 +12089,12 @@ define <4 x i16> @multi_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX8-SDAG-NEXT: v_mad_u16 v6, v5, v4, v6
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX8-SDAG-NEXT: v_mad_u16 v2, v0, v1, v2
-; GFX8-SDAG-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v2, v6, 16, v2
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GFX8-SDAG-NEXT: v_mad_u16 v4, v5, v4, v6
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v1, v3
-; GFX8-SDAG-NEXT: v_or_b32_e32 v1, v0, v4
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v1, v4, 16, v0
; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, v2
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -12118,15 +12104,13 @@ define <4 x i16> @multi_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX8-GISEL-NEXT: v_mad_u16 v6, v4, v5, v6
; GFX8-GISEL-NEXT: v_mad_u16 v2, v0, v1, v2
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX8-GISEL-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX8-GISEL-NEXT: v_mad_u16 v6, v4, v5, v6
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v2, v6, 16, v2
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GFX8-GISEL-NEXT: v_mad_u16 v0, v0, v1, v3
; GFX8-GISEL-NEXT: v_mad_u16 v1, v4, v5, v6
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v1, v1, 16, v0
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v2
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -12244,9 +12228,8 @@ define <2 x i16> @other_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
; GFX8-SDAG-NEXT: v_or_b32_e32 v6, v7, v6
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX8-SDAG-NEXT: v_mad_u16 v4, v5, v4, v7
-; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v1, v2
-; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v4, 16, v0
; GFX8-SDAG-NEXT: s_mov_b32 m0, -1
; GFX8-SDAG-NEXT: ds_write_b32 v3, v6
; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
@@ -12263,8 +12246,7 @@ define <2 x i16> @other_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX8-GISEL-NEXT: v_mad_u16 v0, v0, v1, v2
; GFX8-GISEL-NEXT: v_mad_u16 v1, v4, v5, v7
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-GISEL-NEXT: s_mov_b32 m0, -1
; GFX8-GISEL-NEXT: ds_write_b32 v3, v6
; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
index c46bd6c7687c2..d7cfa46a0d6ef 100644
--- a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
@@ -640,10 +640,9 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_and_or_b32 v0, v0, 1, v4
; SDAG-NEXT: v_add_co_u32_e32 v4, vcc, 1, v0
; SDAG-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
-; SDAG-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
; SDAG-NEXT: v_lshrrev_b64 v[0:1], 2, v[4:5]
-; SDAG-NEXT: v_lshlrev_b32_e32 v7, 30, v6
-; SDAG-NEXT: v_or_b32_e32 v10, v1, v7
+; SDAG-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
+; SDAG-NEXT: v_lshl_or_b32 v10, v6, 30, v1
; SDAG-NEXT: v_and_b32_e32 v1, 0x800000, v5
; SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -672,9 +671,8 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: s_branch .LBB2_2
; SDAG-NEXT: .LBB2_14: ; %itofp-if-then20
; SDAG-NEXT: v_lshrrev_b64 v[0:1], 3, v[4:5]
-; SDAG-NEXT: v_lshlrev_b32_e32 v4, 29, v6
-; SDAG-NEXT: v_or_b32_e32 v10, v1, v4
; SDAG-NEXT: v_mov_b32_e32 v8, v2
+; SDAG-NEXT: v_lshl_or_b32 v10, v6, 29, v1
; SDAG-NEXT: s_branch .LBB2_10
;
; GISEL-LABEL: sitofp_i128_to_f64:
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-args.ll b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
index ea0a8cbe663fd..d4f4f66fb4077 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
@@ -5201,8 +5201,7 @@ define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_store_dwordx2 v[2:3], v[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v8
-; VI-NEXT: v_or_b32_e32 v4, v4, v9
+; VI-NEXT: v_lshl_or_b32 v4, v8, 8, v9
; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v10
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v5, v4
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
index 3fbba4848703f..345de7ba1b2b7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
@@ -147,8 +147,7 @@ define void @ds_bpermute_or_shl(ptr addrspace(1) %out, i32 %base_index, i32 %src
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-GISEL-NEXT: v_and_b32_e32 v2, 62, v2
-; CHECK-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v2
-; CHECK-GISEL-NEXT: v_or_b32_e32 v2, 4, v2
+; CHECK-GISEL-NEXT: v_lshl_or_b32 v2, v2, 2, 4
; CHECK-GISEL-NEXT: ds_bpermute_b32 v2, v2, v3
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
index e8bf198f89855..47b6a09a70650 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
@@ -702,9 +702,8 @@ define amdgpu_kernel void @fma_v2f16(
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; VI-NEXT: v_fma_f16 v3, v5, v4, v3
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_fma_f16 v0, v2, v1, v0
-; VI-NEXT: v_or_b32_e32 v0, v0, v3
+; VI-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: s_endpgm
;
@@ -894,9 +893,8 @@ define amdgpu_kernel void @fma_v2f16_imm_a(
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_fma_f16 v2, v3, s2, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_fma_f16 v0, v1, s2, v0
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm
;
@@ -1079,9 +1077,8 @@ define amdgpu_kernel void @fma_v2f16_imm_b(
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_fma_f16 v2, v3, s2, v2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_fma_f16 v0, v1, s2, v0
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm
;
@@ -1264,9 +1261,8 @@ define amdgpu_kernel void @fma_v2f16_imm_c(
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_fma_f16 v2, v3, v2, s2
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_fma_f16 v0, v1, v0, s2
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm
;
@@ -1575,10 +1571,8 @@ define amdgpu_kernel void @fma_v4f16(
; VI-NEXT: v_fma_f16 v0, v4, v2, v0
; VI-NEXT: v_fma_f16 v2, v8, v7, v6
; VI-NEXT: v_fma_f16 v3, v9, v5, v3
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v1, v1, v2
-; VI-NEXT: v_or_b32_e32 v0, v0, v3
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
index 146956c5908ea..c84221b6d3afd 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
@@ -840,9 +840,8 @@ define amdgpu_kernel void @fmuladd_v2f16(
; VI-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-FLUSH-NEXT: s_waitcnt vmcnt(0)
; VI-FLUSH-NEXT: v_mac_f16_sdwa v3, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; VI-FLUSH-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-FLUSH-NEXT: v_mac_f16_e32 v1, v0, v2
-; VI-FLUSH-NEXT: v_or_b32_e32 v0, v1, v3
+; VI-FLUSH-NEXT: v_lshl_or_b32 v0, v3, 16, v1
; VI-FLUSH-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-FLUSH-NEXT: s_endpgm
;
@@ -876,9 +875,8 @@ define amdgpu_kernel void @fmuladd_v2f16(
; VI-DENORM-NEXT: s_waitcnt vmcnt(0)
; VI-DENORM-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; VI-DENORM-NEXT: v_fma_f16 v3, v5, v4, v3
-; VI-DENORM-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-DENORM-NEXT: v_fma_f16 v0, v2, v1, v0
-; VI-DENORM-NEXT: v_or_b32_e32 v0, v0, v3
+; VI-DENORM-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; VI-DENORM-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-DENORM-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
index 9e0870ad62358..840a1df32c3a9 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
@@ -703,36 +703,21 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GCN-NOHSA-VI-NEXT: flat_load_ushort v21, v[4:5]
; GCN-NOHSA-VI-NEXT: flat_load_ushort v22, v[6:7]
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(14)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v3, v17, v1
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(13)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
+; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v3, v16, 16, v17
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(12)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v2, v19, v1
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(11)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v8
+; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v2, v18, 16, v19
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(10)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v1, v9, v1
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(9)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v4, 16, v10
+; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v1, v8, 16, v9
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(8)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v7, v11, v4
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(7)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
+; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v7, v10, 16, v11
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(6)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v6, v13, v4
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(5)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
+; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v6, v12, 16, v13
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(4)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v5, v15, v4
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v5, v14, 16, v15
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(2)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v4, v20, v0
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v21
+; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v4, v0, 16, v20
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v0, v22, v0
+; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v0, v21, 16, v22
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
index 33defc2ecf6a9..b0cc4db127994 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
@@ -729,9 +729,6 @@ define amdgpu_kernel void @global_load_v16i16_align2(ptr addrspace(1) %in, ptr a
; GCN-NOHSA-VI-NEXT: buffer_load_ushort v15, off, s[4:7], 0 offset:16
; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s2
; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s3
-; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(14)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(13)
; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v16, 16, v2
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(12)
@@ -745,9 +742,9 @@ define amdgpu_kernel void @global_load_v16i16_align2(ptr addrspace(1) %in, ptr a
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(8)
; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v19, 16, v7
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(7)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v3, v8, v0
+; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v3, v0, 16, v8
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(6)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v2, v9, v1
+; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v2, v1, 16, v9
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(5)
; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v1, v10, v16
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(4)
diff --git a/llvm/test/CodeGen/AMDGPU/load-hi16.ll b/llvm/test/CodeGen/AMDGPU/load-hi16.ll
index 91ed52b564d15..e856dc9fc0ba2 100644
--- a/llvm/test/CodeGen/AMDGPU/load-hi16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-hi16.ll
@@ -109,9 +109,8 @@ define <2 x i16> @load_local_lo_hi_v2i16_multi_use_hi(ptr addrspace(3) noalias %
; GFX803-NEXT: v_mov_b32_e32 v2, 0
; GFX803-NEXT: s_waitcnt lgkmcnt(1)
; GFX803-NEXT: ds_write_b16 v2, v1
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(1)
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
@@ -2256,8 +2255,7 @@ define <2 x i16> @load_local_v2i16_split_multi_chain(ptr addrspace(3) %in) #0 {
; GFX803-NEXT: ds_read_u16 v1, v0
; GFX803-NEXT: ds_read_u16 v0, v0 offset:2
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_v2i16_split_multi_chain:
@@ -2305,10 +2303,8 @@ define <2 x i16> @load_local_lo_hi_v2i16_samechain(ptr addrspace(3) %in) #0 {
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v1, v0 offset:16
; GFX803-NEXT: ds_read_u16 v0, v0
-; GFX803-NEXT: s_waitcnt lgkmcnt(1)
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_lo_hi_v2i16_samechain:
@@ -2355,8 +2351,7 @@ define <2 x i16> @load_local_v2i16_broadcast(ptr addrspace(3) %in) #0 {
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v0, v0
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v0
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v0
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_v2i16_broadcast:
@@ -2409,8 +2404,7 @@ define <2 x i16> @load_local_lo_hi_v2i16_side_effect(ptr addrspace(3) %in, ptr a
; GFX803-NEXT: ds_write_b16 v1, v3
; GFX803-NEXT: ds_read_u16 v0, v0 offset:16
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX803-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v2
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_lo_hi_v2i16_side_effect:
@@ -2466,8 +2460,7 @@ define <2 x i16> @load_global_v2i16_split(ptr addrspace(1) %in) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: flat_load_ushort v1, v[2:3] glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_global_v2i16_split:
@@ -2521,8 +2514,7 @@ define <2 x i16> @load_flat_v2i16_split(ptr %in) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: flat_load_ushort v1, v[2:3] glc
; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_flat_v2i16_split:
@@ -2573,8 +2565,7 @@ define <2 x i16> @load_constant_v2i16_split(ptr addrspace(4) %in) #0 {
; GFX803-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX803-NEXT: flat_load_ushort v1, v[2:3] glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_constant_v2i16_split:
@@ -2625,8 +2616,7 @@ define <2 x i16> @load_private_v2i16_split(ptr addrspace(5) byval(i16) %in) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:2 glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_private_v2i16_split:
diff --git a/llvm/test/CodeGen/AMDGPU/load-lo16.ll b/llvm/test/CodeGen/AMDGPU/load-lo16.ll
index 311ce242926a9..485adc5c5a758 100644
--- a/llvm/test/CodeGen/AMDGPU/load-lo16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-lo16.ll
@@ -56,9 +56,8 @@ define <2 x i16> @load_local_lo_v2i16_reglo(ptr addrspace(3) %in, i16 %reg) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v0, v0
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_lo_v2i16_reglo:
@@ -105,9 +104,8 @@ define void @load_local_lo_v2i16_reglo_vreg(ptr addrspace(3) %in, i16 %reg) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v0, v0
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -263,9 +261,8 @@ define void @load_local_lo_v2f16_reglo_vreg(ptr addrspace(3) %in, half %reg) #0
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v0, v0
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -357,9 +354,8 @@ define void @load_local_lo_v2i16_reglo_vreg_zexti8(ptr addrspace(3) %in, i16 %re
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u8 v0, v0
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -506,9 +502,8 @@ define void @load_local_lo_v2f16_reglo_vreg_zexti8(ptr addrspace(3) %in, half %r
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u8 v0, v0
-; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -1343,9 +1338,8 @@ define void @load_private_lo_v2i16_reghi_vreg(ptr addrspace(5) byval(i16) %in, i
; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
-; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
index b0da72184f050..72f1ab0b6fb82 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
@@ -1532,10 +1532,9 @@ define half @local_atomic_fadd_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX8-NEXT: v_add_f16_e32 v3, 4.0, v3
; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_add_f16_e32 v3, 4.0, v3
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -1924,10 +1923,9 @@ define half @local_atomic_fadd_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX8-NEXT: v_add_f16_e32 v3, 4.0, v3
; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_add_f16_e32 v3, 4.0, v3
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -2297,10 +2295,9 @@ define void @local_atomic_fadd_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v0, v3
-; GFX8-NEXT: v_add_f16_e32 v4, 4.0, v4
; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, v0, v4
-; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_add_f16_e32 v4, 4.0, v4
+; GFX8-NEXT: v_lshl_or_b32 v4, v4, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
@@ -2676,10 +2673,9 @@ define void @local_atomic_fadd_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v1, v3
-; GFX8-NEXT: v_add_f16_e32 v4, 4.0, v4
; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, v1, v4
-; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_add_f16_e32 v4, 4.0, v4
+; GFX8-NEXT: v_lshl_or_b32 v4, v4, v1, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
index 43d77d0afa8c6..ba446c13cd2e4 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
@@ -1073,10 +1073,9 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_max_f16_e32 v3, 4.0, v3
; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_max_f16_e32 v3, 4.0, v3
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -1476,10 +1475,9 @@ define half @local_atomic_fmax_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_max_f16_e32 v3, 4.0, v3
; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_max_f16_e32 v3, 4.0, v3
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -1860,10 +1858,9 @@ define void @local_atomic_fmax_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v0, v3
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
-; GFX8-NEXT: v_max_f16_e32 v4, 4.0, v4
; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, v0, v4
-; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_max_f16_e32 v4, 4.0, v4
+; GFX8-NEXT: v_lshl_or_b32 v4, v4, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
@@ -2250,10 +2247,9 @@ define void @local_atomic_fmax_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
-; GFX8-NEXT: v_max_f16_e32 v4, 4.0, v4
; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, v1, v4
-; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_max_f16_e32 v4, 4.0, v4
+; GFX8-NEXT: v_lshl_or_b32 v4, v4, v1, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
index 1759a212c6ea3..2e4339b30d9e6 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
@@ -1073,10 +1073,9 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_min_f16_e32 v3, 4.0, v3
; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_min_f16_e32 v3, 4.0, v3
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -1476,10 +1475,9 @@ define half @local_atomic_fmin_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_min_f16_e32 v3, 4.0, v3
; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_min_f16_e32 v3, 4.0, v3
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -1860,10 +1858,9 @@ define void @local_atomic_fmin_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v0, v3
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
-; GFX8-NEXT: v_min_f16_e32 v4, 4.0, v4
; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, v0, v4
-; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_min_f16_e32 v4, 4.0, v4
+; GFX8-NEXT: v_lshl_or_b32 v4, v4, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
@@ -2250,10 +2247,9 @@ define void @local_atomic_fmin_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
-; GFX8-NEXT: v_min_f16_e32 v4, 4.0, v4
; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, v1, v4
-; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_min_f16_e32 v4, 4.0, v4
+; GFX8-NEXT: v_lshl_or_b32 v4, v4, v1, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
index 5feb76edf3d17..1d46b5536a2fa 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
@@ -1994,10 +1994,9 @@ define half @local_atomic_fsub_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX8-NEXT: v_add_f16_e32 v3, -4.0, v3
; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_add_f16_e32 v3, -4.0, v3
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -2386,10 +2385,9 @@ define half @local_atomic_fsub_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX8-NEXT: v_add_f16_e32 v3, -4.0, v3
; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
-; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_add_f16_e32 v3, -4.0, v3
+; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -2759,10 +2757,9 @@ define void @local_atomic_fsub_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v0, v3
-; GFX8-NEXT: v_add_f16_e32 v4, -4.0, v4
; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, v0, v4
-; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_add_f16_e32 v4, -4.0, v4
+; GFX8-NEXT: v_lshl_or_b32 v4, v4, v0, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
@@ -3138,10 +3135,9 @@ define void @local_atomic_fsub_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v1, v3
-; GFX8-NEXT: v_add_f16_e32 v4, -4.0, v4
; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v4, v1, v4
-; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
+; GFX8-NEXT: v_add_f16_e32 v4, -4.0, v4
+; GFX8-NEXT: v_lshl_or_b32 v4, v4, v1, v5
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
index 4b658de512f81..c58bdd75e5cdc 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
@@ -469,28 +469,27 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_xor_b32 s4, exec_lo, s4
; CHECK-NEXT: s_cbranch_execz .LBB0_31
; CHECK-NEXT: ; %bb.30: ; in Loop: Header=BB0_28 Depth=1
-; CHECK-NEXT: v_xor_b32_e32 v5, v60, v58
-; CHECK-NEXT: v_lshrrev_b64 v[3:4], 16, v[45:46]
; CHECK-NEXT: v_mad_u64_u32 v[7:8], null, 0x180, v73, s[66:67]
+; CHECK-NEXT: v_xor_b32_e32 v5, v60, v58
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 5, v0
+; CHECK-NEXT: v_lshrrev_b64 v[3:4], 16, v[45:46]
; CHECK-NEXT: v_lshrrev_b64 v[1:2], 16, v[56:57]
-; CHECK-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; CHECK-NEXT: v_lshlrev_b32_e32 v9, 6, v72
; CHECK-NEXT: v_lshlrev_b32_e32 v11, 12, v63
; CHECK-NEXT: v_xor_b32_e32 v6, v61, v59
-; CHECK-NEXT: ; implicit-def: $vgpr42
-; CHECK-NEXT: ; implicit-def: $vgpr43
-; CHECK-NEXT: ; implicit-def: $vgpr44
+; CHECK-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; CHECK-NEXT: v_add_co_u32 v7, vcc_lo, v7, v0
-; CHECK-NEXT: v_or_b32_e32 v4, v10, v4
-; CHECK-NEXT: v_lshlrev_b32_e32 v10, 16, v45
; CHECK-NEXT: v_or3_b32 v9, v9, v11, v62
; CHECK-NEXT: v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
; CHECK-NEXT: v_lshrrev_b64 v[5:6], 16, v[5:6]
-; CHECK-NEXT: v_or_b32_e32 v2, v10, v2
+; CHECK-NEXT: v_or_b32_e32 v4, v10, v4
+; CHECK-NEXT: v_lshl_or_b32 v2, v45, 16, v2
; CHECK-NEXT: global_store_dword v[7:8], v9, off offset:4
; CHECK-NEXT: global_store_dwordx4 v[7:8], v[1:4], off offset:8
; CHECK-NEXT: global_store_dwordx2 v[7:8], v[5:6], off offset:24
+; CHECK-NEXT: ; implicit-def: $vgpr42
+; CHECK-NEXT: ; implicit-def: $vgpr43
+; CHECK-NEXT: ; implicit-def: $vgpr44
; CHECK-NEXT: .LBB0_31: ; %Flow
; CHECK-NEXT: ; in Loop: Header=BB0_28 Depth=1
; CHECK-NEXT: s_andn2_saveexec_b32 s4, s4
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
index 30ad3be46053c..60b206ba91589 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
@@ -19,19 +19,15 @@ define amdgpu_kernel void @ctlz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX9-NEXT: s_waitcnt vmcnt(7)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v6
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 8, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
@@ -57,23 +53,20 @@ define amdgpu_kernel void @ctlz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3]
; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:4
-; GFX10-NEXT: s_waitcnt vmcnt(7)
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX10-NEXT: s_waitcnt vmcnt(4)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX10-NEXT: s_waitcnt vmcnt(2)
+; GFX10-NEXT: v_lshl_or_b32 v4, v4, 8, v6
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v8
-; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX10-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v8
; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v3, v5, v4
+; GFX10-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX10-NEXT: v_ffbh_u32_e32 v2, v3
+; GFX10-NEXT: v_or_b32_e32 v3, v5, v4
; GFX10-NEXT: v_ffbh_u32_e32 v0, v0
+; GFX10-NEXT: v_ffbh_u32_e32 v2, v3
; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, 32 clamp
; GFX10-NEXT: v_min_u32_e32 v0, v2, v0
; GFX10-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
@@ -98,19 +91,15 @@ define amdgpu_kernel void @ctlz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX9-NEXT: s_waitcnt vmcnt(7)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v6
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 8, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
@@ -137,23 +126,20 @@ define amdgpu_kernel void @ctlz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3]
; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:4
-; GFX10-NEXT: s_waitcnt vmcnt(7)
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX10-NEXT: s_waitcnt vmcnt(4)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX10-NEXT: s_waitcnt vmcnt(2)
+; GFX10-NEXT: v_lshl_or_b32 v4, v4, 8, v6
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v8
-; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX10-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v8
; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v3, v5, v4
+; GFX10-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX10-NEXT: v_ffbh_u32_e32 v2, v3
+; GFX10-NEXT: v_or_b32_e32 v3, v5, v4
; GFX10-NEXT: v_ffbh_u32_e32 v0, v0
+; GFX10-NEXT: v_ffbh_u32_e32 v2, v3
; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, 32 clamp
; GFX10-NEXT: v_min_u32_e32 v0, v2, v0
; GFX10-NEXT: v_min_u32_e32 v0, 64, v0
@@ -179,19 +165,15 @@ define amdgpu_kernel void @cttz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX9-NEXT: s_waitcnt vmcnt(7)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v6
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 8, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
@@ -217,19 +199,15 @@ define amdgpu_kernel void @cttz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX10-NEXT: s_waitcnt vmcnt(7)
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(6)
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX10-NEXT: s_waitcnt vmcnt(4)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX10-NEXT: s_waitcnt vmcnt(2)
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v6
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v6
; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX10-NEXT: v_lshl_or_b32 v3, v4, 8, v7
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
@@ -260,19 +238,15 @@ define amdgpu_kernel void @cttz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX9-NEXT: s_waitcnt vmcnt(7)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v6
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 8, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
@@ -299,19 +273,15 @@ define amdgpu_kernel void @cttz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX10-NEXT: s_waitcnt vmcnt(7)
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(6)
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX10-NEXT: s_waitcnt vmcnt(4)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX10-NEXT: s_waitcnt vmcnt(2)
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v6
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v6
; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX10-NEXT: v_lshl_or_b32 v3, v4, 8, v7
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
diff --git a/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll b/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
index e065b8e4c5f97..0756bf624f763 100644
--- a/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
@@ -411,8 +411,7 @@ define amdgpu_kernel void @v_pack_v2i16_inline_imm_lo(ptr addrspace(1) %in1) #0
; GFX803-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX803-NEXT: flat_load_dword v0, v[0:1] glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX803-NEXT: v_or_b32_e32 v0, 64, v0
+; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, 64
; GFX803-NEXT: ;;#ASMSTART
; GFX803-NEXT: ; use v0
; GFX803-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/permute_i8.ll b/llvm/test/CodeGen/AMDGPU/permute_i8.ll
index b54d80a03abd0..1c7642bb05bac 100644
--- a/llvm/test/CodeGen/AMDGPU/permute_i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/permute_i8.ll
@@ -615,7 +615,6 @@ define amdgpu_kernel void @shuffle8i8(ptr addrspace(1) %in0, ptr addrspace(1) %i
; GFX10-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_bfe_u32 s0, s4, 0x80008
-; GFX10-NEXT: v_perm_b32 v0, s4, s8, v0
; GFX10-NEXT: s_lshl_b32 s1, s9, 8
; GFX10-NEXT: s_bfe_u32 s2, s5, 0x80008
; GFX10-NEXT: s_lshl_b32 s3, s8, 8
@@ -624,13 +623,13 @@ define amdgpu_kernel void @shuffle8i8(ptr addrspace(1) %in0, ptr addrspace(1) %i
; GFX10-NEXT: s_or_b32 s1, s2, s1
; GFX10-NEXT: s_lshl_b32 s2, s9, 8
; GFX10-NEXT: s_or_b32 s0, s0, s3
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: v_perm_b32 v0, s4, s8, v0
; GFX10-NEXT: s_or_b32 s2, s5, s2
; GFX10-NEXT: s_and_b32 s0, s0, 0xffff
; GFX10-NEXT: s_lshl_b32 s1, s1, 16
; GFX10-NEXT: s_and_b32 s2, s2, 0xffff
; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: v_or_b32_e32 v1, s2, v0
+; GFX10-NEXT: v_lshl_or_b32 v1, v0, 16, s2
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX10-NEXT: s_endpgm
@@ -654,15 +653,14 @@ define amdgpu_kernel void @shuffle8i8(ptr addrspace(1) %in0, ptr addrspace(1) %i
; GFX9-NEXT: s_and_b32 s5, s4, 0xff
; GFX9-NEXT: s_or_b32 s0, s0, s3
; GFX9-NEXT: s_lshl_b32 s2, s2, 8
-; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: s_or_b32 s2, s5, s2
-; GFX9-NEXT: v_perm_b32 v0, s4, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_perm_b32 v0, s4, v0, v1
; GFX9-NEXT: s_and_b32 s2, s2, 0xffff
; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: v_or_b32_e32 v1, s2, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v0, 16, s2
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX9-NEXT: s_endpgm
@@ -3873,8 +3871,7 @@ define amdgpu_kernel void @any_extend_to_perm(i8 %arg, <4 x i8> %arg1) {
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_perm_b32 v0, s1, s0, v0
; GFX10-NEXT: s_and_b32 s0, s1, 0xffff
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, s0
; GFX10-NEXT: ds_write_b32 v1, v0
; GFX10-NEXT: s_endpgm
;
@@ -3884,10 +3881,9 @@ define amdgpu_kernel void @any_extend_to_perm(i8 %arg, <4 x i8> %arg1) {
; GFX9-NEXT: v_mov_b32_e32 v0, 0xc0c0006
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s0
-; GFX9-NEXT: v_perm_b32 v0, s1, v1, v0
; GFX9-NEXT: s_and_b32 s2, s1, 0xffff
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: v_or_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_perm_b32 v0, s1, v1, v0
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, s2
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: ds_write_b32 v1, v0
; GFX9-NEXT: s_endpgm
@@ -3908,15 +3904,13 @@ define amdgpu_kernel void @more_any_extend_to_perm(i8 %arg, <4 x i8> %arg1, i8 %
; GFX10-NEXT: v_mov_b32_e32 v1, 0xc0c0104
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_perm_b32 v2, s6, s7, v0
-; GFX10-NEXT: v_perm_b32 v0, s0, s7, v0
; GFX10-NEXT: v_perm_b32 v3, s0, s7, v1
+; GFX10-NEXT: v_perm_b32 v0, s0, s7, v0
; GFX10-NEXT: v_perm_b32 v1, s6, s7, v1
; GFX10-NEXT: v_mov_b32_e32 v4, s1
-; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_mov_b32_e32 v5, s2
-; GFX10-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX10-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX10-NEXT: ds_write_b32 v4, v2
; GFX10-NEXT: ds_write_b32 v5, v0
; GFX10-NEXT: s_endpgm
@@ -3925,19 +3919,17 @@ define amdgpu_kernel void @more_any_extend_to_perm(i8 %arg, <4 x i8> %arg1, i8 %
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0304
; GFX9-NEXT: v_mov_b32_e32 v0, 0xc0c0104
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0304
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s7
-; GFX9-NEXT: v_perm_b32 v4, s6, v2, v1
-; GFX9-NEXT: v_perm_b32 v1, s0, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s0, v2, v0
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_perm_b32 v4, s6, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s6, v2, v0
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v1, s0, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: ds_write_b32 v4, v3
; GFX9-NEXT: ds_write_b32 v1, v0
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
index 5c043eadf6096..2546557e99083 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
@@ -19,10 +19,9 @@ body: |
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3
- ; GFX1250-NEXT: renamable $vgpr1 = V_LSHLREV_B32_e32 8, $vgpr0, implicit $exec
+ ; GFX1250-NEXT: $vgpr1 = V_LSHL_OR_B32_e64 $vgpr0, 8, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 256, $vgpr0, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr3, $sgpr_null = V_ADDC_U32_e64 0, killed $vgpr0, killed $vcc_lo, 0, implicit $exec
- ; GFX1250-NEXT: renamable $vgpr1 = disjoint V_OR_B32_e32 0, killed $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr0 = V_ADD_U32_e32 -256, $vgpr1, implicit $exec
; GFX1250-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr1, $vgpr2_vgpr3, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
; GFX1250-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr0, killed $vgpr2_vgpr3, 256, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
@@ -59,10 +58,9 @@ body: |
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4
- ; GFX1250-NEXT: renamable $vgpr1 = V_LSHLREV_B32_e32 8, $vgpr0, implicit $exec
+ ; GFX1250-NEXT: $vgpr1 = V_LSHL_OR_B32_e64 $vgpr0, 8, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 256, $vgpr0, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr3, $sgpr_null = V_ADDC_U32_e64 0, killed $vgpr0, killed $vcc_lo, 0, implicit $exec
- ; GFX1250-NEXT: renamable $vgpr1 = disjoint V_OR_B32_e32 0, killed $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr0 = V_ADD_U32_e32 -256, $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr4 = V_ADD_U32_e32 -260, $vgpr1, implicit $exec
; GFX1250-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr1, $vgpr2_vgpr3, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
@@ -154,10 +152,9 @@ body: |
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4
- ; GFX1250-NEXT: renamable $vgpr1 = V_LSHLREV_B32_e32 8, $vgpr0, implicit $exec
+ ; GFX1250-NEXT: $vgpr1 = V_LSHL_OR_B32_e64 $vgpr0, 8, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 256, $vgpr0, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr3, $sgpr_null = V_ADDC_U32_e64 0, killed $vgpr0, killed $vcc_lo, 0, implicit $exec
- ; GFX1250-NEXT: renamable $vgpr1 = disjoint V_OR_B32_e32 0, killed $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr0 = V_ADD_U32_e32 -256, $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr4 = V_ADD_U32_e32 -512, $vgpr1, implicit $exec
; GFX1250-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr1, $vgpr2_vgpr3, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
@@ -203,10 +200,9 @@ body: |
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3
- ; GFX1250-NEXT: renamable $vgpr1 = V_LSHLREV_B32_e32 8, $vgpr0, implicit $exec
+ ; GFX1250-NEXT: $vgpr1 = V_LSHL_OR_B32_e64 $vgpr0, 8, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 256, $vgpr0, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr3, $sgpr_null = V_ADDC_U32_e64 0, killed $vgpr0, killed $vcc_lo, 0, implicit $exec
- ; GFX1250-NEXT: renamable $vgpr1 = disjoint V_OR_B32_e32 0, killed $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr0 = V_ADD_U32_e32 -256, $vgpr1, implicit $exec
; GFX1250-NEXT: GLOBAL_STORE_ASYNC_FROM_LDS_B128 $vgpr2_vgpr3, killed $vgpr1, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
; GFX1250-NEXT: GLOBAL_STORE_ASYNC_FROM_LDS_B128 killed $vgpr2_vgpr3, killed $vgpr0, 256, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
diff --git a/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll b/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
index 74bd338c7c022..f8b6a0109ebb3 100644
--- a/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
+++ b/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
@@ -2656,9 +2656,8 @@ define <2 x i16> @v_mul_add_1_v2i16(<2 x i16> %x, <2 x i16> %y) {
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX8-NEXT: v_mad_u16 v2, v3, v2, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_mad_u16 v0, v0, v1, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_add_1_v2i16:
@@ -2724,9 +2723,8 @@ define <2 x i16> @v_mul_add_1_v2i16_commute(<2 x i16> %x, <2 x i16> %y) {
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX8-NEXT: v_mad_u16 v2, v3, v2, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_mad_u16 v0, v0, v1, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_add_1_v2i16_commute:
@@ -2789,9 +2787,8 @@ define <2 x i16> @v_mul_add_x_v2i16(<2 x i16> %x, <2 x i16> %y) {
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX8-NEXT: v_mad_u16 v2, v3, v2, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_mad_u16 v0, v0, v1, v0
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_add_x_v2i16:
@@ -4331,10 +4328,9 @@ define <2 x i16> @v_mul_9_add_52_v2i16(<2 x i16> %arg) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX8-NEXT: v_mad_u16 v1, v1, 9, 52
; GFX8-NEXT: v_mad_u16 v0, v0, 9, 52
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_mad_u16 v1, v1, 9, 52
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_9_add_52_v2i16:
@@ -4717,10 +4713,9 @@ define <2 x i16> @v_mul_5_add_1_v2i16(<2 x i16> %arg) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX8-NEXT: v_mad_u16 v1, v1, 5, 1
; GFX8-NEXT: v_mad_u16 v0, v0, 5, 1
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_mad_u16 v1, v1, 5, 1
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_5_add_1_v2i16:
@@ -4778,10 +4773,9 @@ define <2 x i16> @v_mul_284_add_82_v2i16(<2 x i16> %arg) {
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-NEXT: s_movk_i32 s4, 0x11c
; GFX8-NEXT: v_mov_b32_e32 v2, 0x52
-; GFX8-NEXT: v_mad_u16 v1, v1, s4, v2
; GFX8-NEXT: v_mad_u16 v0, v0, s4, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-NEXT: v_mad_u16 v1, v1, s4, v2
+; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_284_add_82_v2i16:
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
index a82415e2e8303..1d0fcd3a962ea 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
@@ -322,24 +322,22 @@ define amdgpu_kernel void @scalar_to_vector_v4f16() {
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; kill: def $vgpr1_hi16 killed $sgpr0 killed $exec
; GFX11-NEXT: buffer_load_d16_u8 v0, off, s[0:3], 0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 8, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: ; kill: def $vgpr1_hi16 killed $sgpr0 killed $exec
; GFX11-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v1
; GFX11-NEXT: s_and_b32 s1, s0, 0xff00
; GFX11-NEXT: s_bfe_u32 s4, s0, 0x80008
; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
; GFX11-NEXT: s_or_b32 s1, s4, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshl_b32 s4, s1, 16
; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
; GFX11-NEXT: s_or_b32 s0, s0, s4
; GFX11-NEXT: s_or_b32 s1, s1, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX11-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll
index b690879dab99b..c0b0f9ad13107 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll
@@ -1653,10 +1653,8 @@ define amdgpu_kernel void @v_sdiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: s_mov_b32 s1, s5
; TONGA-NEXT: s_waitcnt vmcnt(3)
; TONGA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; TONGA-NEXT: s_waitcnt vmcnt(2)
-; TONGA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; TONGA-NEXT: s_waitcnt vmcnt(1)
-; TONGA-NEXT: v_or_b32_e32 v1, v2, v1
+; TONGA-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; TONGA-NEXT: v_bfe_i32 v1, v1, 0, 23
; TONGA-NEXT: v_cvt_f32_i32_e32 v2, v1
; TONGA-NEXT: s_waitcnt vmcnt(0)
@@ -1696,10 +1694,8 @@ define amdgpu_kernel void @v_sdiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_mov_b32 s1, s9
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 23
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -1838,18 +1834,14 @@ define amdgpu_kernel void @v_sdiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: buffer_load_ushort v3, off, s[8:11], 0
; TONGA-NEXT: s_mov_b32 s0, s4
; TONGA-NEXT: s_mov_b32 s1, s5
-; TONGA-NEXT: s_waitcnt vmcnt(3)
-; TONGA-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; TONGA-NEXT: s_waitcnt vmcnt(2)
-; TONGA-NEXT: v_or_b32_e32 v1, v1, v4
+; TONGA-NEXT: v_lshl_or_b32 v1, v0, 16, v1
; TONGA-NEXT: v_cvt_f32_i32_e32 v1, v1
-; TONGA-NEXT: s_waitcnt vmcnt(1)
-; TONGA-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_or_b32_e32 v3, v3, v4
+; TONGA-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; TONGA-NEXT: v_cvt_f32_i32_e32 v3, v3
-; TONGA-NEXT: v_rcp_f32_e32 v4, v1
; TONGA-NEXT: v_xor_b32_e32 v0, v2, v0
+; TONGA-NEXT: v_rcp_f32_e32 v4, v1
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; TONGA-NEXT: v_or_b32_e32 v0, 1, v0
; TONGA-NEXT: v_mul_f32_e32 v2, v3, v4
@@ -1879,18 +1871,14 @@ define amdgpu_kernel void @v_sdiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: buffer_load_ushort v3, off, s[4:7], 0
; GFX9-NEXT: s_mov_b32 s0, s8
; GFX9-NEXT: s_mov_b32 s1, s9
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v4
+; GFX9-NEXT: v_lshl_or_b32 v1, v0, 16, v1
; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v2, 16, v3
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v3
-; GFX9-NEXT: v_rcp_f32_e32 v4, v1
; GFX9-NEXT: v_xor_b32_e32 v0, v2, v0
+; GFX9-NEXT: v_rcp_f32_e32 v4, v1
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mul_f32_e32 v2, v3, v4
diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
index fa705fb455ba8..0d8788c781a1c 100644
--- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
@@ -312,8 +312,7 @@ define amdgpu_kernel void @mul_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in
; NOSDWA-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, v4, v2
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; NOSDWA-NEXT: v_or_b32_e32 v2, v3, v2
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -406,10 +405,8 @@ define amdgpu_kernel void @mul_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in
; NOSDWA-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; NOSDWA-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; NOSDWA-NEXT: v_mul_lo_u16_e32 v0, v0, v2
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; NOSDWA-NEXT: v_or_b32_e32 v1, v6, v1
-; NOSDWA-NEXT: v_or_b32_e32 v0, v7, v0
+; NOSDWA-NEXT: v_lshl_or_b32 v1, v1, 16, v6
+; NOSDWA-NEXT: v_lshl_or_b32 v0, v0, 16, v7
; NOSDWA-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; NOSDWA-NEXT: s_endpgm
;
@@ -515,14 +512,10 @@ define amdgpu_kernel void @mul_v8i16(ptr addrspace(1) %out, ptr addrspace(1) %in
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, v2, v6
; NOSDWA-NEXT: v_mul_lo_u16_e32 v1, v1, v5
; NOSDWA-NEXT: v_mul_lo_u16_e32 v0, v0, v4
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; NOSDWA-NEXT: v_or_b32_e32 v3, v10, v3
-; NOSDWA-NEXT: v_or_b32_e32 v2, v11, v2
-; NOSDWA-NEXT: v_or_b32_e32 v1, v12, v1
-; NOSDWA-NEXT: v_or_b32_e32 v0, v13, v0
+; NOSDWA-NEXT: v_lshl_or_b32 v3, v3, 16, v10
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v2, 16, v11
+; NOSDWA-NEXT: v_lshl_or_b32 v1, v1, 16, v12
+; NOSDWA-NEXT: v_lshl_or_b32 v0, v0, 16, v13
; NOSDWA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; NOSDWA-NEXT: s_endpgm
;
@@ -695,9 +688,8 @@ define amdgpu_kernel void @mul_v2half(ptr addrspace(1) %out, ptr addrspace(1) %i
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
; NOSDWA-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; NOSDWA-NEXT: v_mul_f16_e32 v4, v5, v4
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; NOSDWA-NEXT: v_mul_f16_e32 v2, v3, v2
-; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v4
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -780,10 +772,8 @@ define amdgpu_kernel void @mul_v4half(ptr addrspace(1) %out, ptr addrspace(1) %i
; NOSDWA-NEXT: v_mul_f16_e32 v0, v0, v2
; NOSDWA-NEXT: v_mul_f16_e32 v2, v7, v6
; NOSDWA-NEXT: v_mul_f16_e32 v3, v8, v3
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; NOSDWA-NEXT: v_or_b32_e32 v1, v1, v2
-; NOSDWA-NEXT: v_or_b32_e32 v0, v0, v3
+; NOSDWA-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; NOSDWA-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; NOSDWA-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; NOSDWA-NEXT: s_endpgm
;
@@ -879,14 +869,10 @@ define amdgpu_kernel void @mul_v8half(ptr addrspace(1) %out, ptr addrspace(1) %i
; NOSDWA-NEXT: v_mul_f16_e32 v7, v12, v7
; NOSDWA-NEXT: v_mul_f16_e32 v6, v13, v6
; NOSDWA-NEXT: v_mul_f16_e32 v4, v4, v5
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v5, 16, v10
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; NOSDWA-NEXT: v_or_b32_e32 v3, v3, v5
-; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v7
-; NOSDWA-NEXT: v_or_b32_e32 v1, v1, v6
-; NOSDWA-NEXT: v_or_b32_e32 v0, v0, v4
+; NOSDWA-NEXT: v_lshl_or_b32 v3, v10, 16, v3
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v7, 16, v2
+; NOSDWA-NEXT: v_lshl_or_b32 v1, v6, 16, v1
+; NOSDWA-NEXT: v_lshl_or_b32 v0, v4, 16, v0
; NOSDWA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; NOSDWA-NEXT: s_endpgm
;
@@ -1157,26 +1143,25 @@ define amdgpu_kernel void @mul_v4i8(ptr addrspace(1) %out, ptr addrspace(1) %ina
; NOSDWA-NEXT: v_mov_b32_e32 v0, s0
; NOSDWA-NEXT: v_mov_b32_e32 v1, s1
; NOSDWA-NEXT: s_waitcnt vmcnt(1)
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v6, 8, v4
; NOSDWA-NEXT: v_lshrrev_b32_e32 v3, 16, v4
; NOSDWA-NEXT: v_lshrrev_b32_e32 v5, 24, v4
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v6, 8, v4
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v9, 8, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v8, 24, v2
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v9, 8, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, v4, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v4, v6, v9
+; NOSDWA-NEXT: v_and_b32_e32 v2, 0xff, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v5, v5, v8
; NOSDWA-NEXT: v_mul_lo_u16_e32 v3, v3, v7
-; NOSDWA-NEXT: v_and_b32_e32 v2, 0xff, v2
; NOSDWA-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; NOSDWA-NEXT: v_lshlrev_b16_e32 v5, 8, v5
; NOSDWA-NEXT: v_and_b32_e32 v3, 0xff, v3
; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v4
; NOSDWA-NEXT: v_or_b32_e32 v3, v3, v5
; NOSDWA-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v3
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -1286,45 +1271,43 @@ define amdgpu_kernel void @mul_v8i8(ptr addrspace(1) %out, ptr addrspace(1) %ina
; NOSDWA-NEXT: v_mov_b32_e32 v4, s0
; NOSDWA-NEXT: v_mov_b32_e32 v5, s1
; NOSDWA-NEXT: s_waitcnt vmcnt(1)
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v8, 8, v0
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v11, 8, v1
+; NOSDWA-NEXT: s_waitcnt vmcnt(0)
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v14, 8, v2
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v17, 8, v3
; NOSDWA-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; NOSDWA-NEXT: v_lshrrev_b32_e32 v7, 24, v0
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v8, 8, v0
; NOSDWA-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; NOSDWA-NEXT: v_lshrrev_b32_e32 v10, 24, v1
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v11, 8, v1
-; NOSDWA-NEXT: s_waitcnt vmcnt(0)
; NOSDWA-NEXT: v_lshrrev_b32_e32 v12, 16, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v13, 24, v2
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v14, 8, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v15, 16, v3
; NOSDWA-NEXT: v_lshrrev_b32_e32 v16, 24, v3
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v17, 8, v3
; NOSDWA-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; NOSDWA-NEXT: v_mul_lo_u16_e32 v0, v0, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, v11, v17
+; NOSDWA-NEXT: v_mul_lo_u16_e32 v8, v8, v14
+; NOSDWA-NEXT: v_and_b32_e32 v1, 0xff, v1
; NOSDWA-NEXT: v_mul_lo_u16_e32 v3, v10, v16
; NOSDWA-NEXT: v_mul_lo_u16_e32 v9, v9, v15
-; NOSDWA-NEXT: v_mul_lo_u16_e32 v8, v8, v14
+; NOSDWA-NEXT: v_and_b32_e32 v0, 0xff, v0
; NOSDWA-NEXT: v_mul_lo_u16_e32 v7, v7, v13
; NOSDWA-NEXT: v_mul_lo_u16_e32 v6, v6, v12
-; NOSDWA-NEXT: v_and_b32_e32 v1, 0xff, v1
-; NOSDWA-NEXT: v_and_b32_e32 v0, 0xff, v0
; NOSDWA-NEXT: v_lshlrev_b16_e32 v2, 8, v2
+; NOSDWA-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; NOSDWA-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; NOSDWA-NEXT: v_and_b32_e32 v9, 0xff, v9
-; NOSDWA-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; NOSDWA-NEXT: v_lshlrev_b16_e32 v7, 8, v7
; NOSDWA-NEXT: v_and_b32_e32 v6, 0xff, v6
; NOSDWA-NEXT: v_or_b32_e32 v1, v1, v2
-; NOSDWA-NEXT: v_or_b32_e32 v2, v9, v3
; NOSDWA-NEXT: v_or_b32_e32 v0, v0, v8
+; NOSDWA-NEXT: v_or_b32_e32 v2, v9, v3
; NOSDWA-NEXT: v_or_b32_e32 v3, v6, v7
; NOSDWA-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; NOSDWA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; NOSDWA-NEXT: v_or_b32_e32 v1, v1, v2
-; NOSDWA-NEXT: v_or_b32_e32 v0, v0, v3
+; NOSDWA-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; NOSDWA-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; NOSDWA-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; NOSDWA-NEXT: s_endpgm
;
@@ -1459,9 +1442,8 @@ define amdgpu_kernel void @sitofp_v2i16_to_v2f16(
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
; NOSDWA-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; NOSDWA-NEXT: v_cvt_f16_i16_e32 v3, v3
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; NOSDWA-NEXT: v_cvt_f16_i16_e32 v2, v2
-; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v3
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -1535,9 +1517,8 @@ define amdgpu_kernel void @mac_v2half(ptr addrspace(1) %out, ptr addrspace(1) %i
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
; NOSDWA-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; NOSDWA-NEXT: v_mac_f16_e32 v4, v5, v4
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; NOSDWA-NEXT: v_mac_f16_e32 v2, v3, v2
-; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v4
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -1558,9 +1539,8 @@ define amdgpu_kernel void @mac_v2half(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX89-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX89-NEXT: s_waitcnt vmcnt(0)
; GFX89-NEXT: v_mac_f16_sdwa v4, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX89-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX89-NEXT: v_mac_f16_e32 v2, v3, v2
-; GFX89-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX89-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX89-NEXT: flat_store_dword v[0:1], v2
; GFX89-NEXT: s_endpgm
;
@@ -1618,8 +1598,7 @@ define amdgpu_kernel void @immediate_mul_v2i16(ptr addrspace(1) %out, ptr addrsp
; NOSDWA-NEXT: v_mul_lo_u16_e32 v3, 0x7b, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, 0x141, v2
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; NOSDWA-NEXT: v_or_b32_e32 v2, v3, v2
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -1701,8 +1680,7 @@ define amdgpu_kernel void @mulmul_v2i16(ptr addrspace(1) %out, ptr addrspace(1)
; NOSDWA-NEXT: v_mul_lo_u16_e32 v5, v5, v4
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, v3, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v3, v5, v4
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v3
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -1791,10 +1769,9 @@ define amdgpu_kernel void @add_bb_v2i16(ptr addrspace(1) %out, ptr addrspace(1)
; NOSDWA-NEXT: v_add_u32_e32 v3, vcc, v1, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; NOSDWA-NEXT: v_add_u32_e32 v1, vcc, v1, v2
; NOSDWA-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; NOSDWA-NEXT: v_or_b32_e32 v2, v3, v1
+; NOSDWA-NEXT: v_add_u32_e32 v1, vcc, v1, v2
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v1, 16, v3
; NOSDWA-NEXT: v_mov_b32_e32 v1, s1
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
@@ -2222,9 +2199,8 @@ define amdgpu_kernel void @mac_v2half_same_srcop(ptr addrspace(1) %out, ptr addr
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
; NOSDWA-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; NOSDWA-NEXT: v_mac_f16_e32 v5, v4, v4
-; NOSDWA-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; NOSDWA-NEXT: v_mac_f16_e32 v3, v2, v2
-; NOSDWA-NEXT: v_or_b32_e32 v2, v3, v4
+; NOSDWA-NEXT: v_lshl_or_b32 v2, v5, 16, v3
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -2245,9 +2221,8 @@ define amdgpu_kernel void @mac_v2half_same_srcop(ptr addrspace(1) %out, ptr addr
; GFX89-NEXT: v_lshrrev_b32_e32 v3, 16, v4
; GFX89-NEXT: s_waitcnt vmcnt(0)
; GFX89-NEXT: v_mac_f16_sdwa v3, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; GFX89-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX89-NEXT: v_mac_f16_e32 v4, v2, v2
-; GFX89-NEXT: v_or_b32_e32 v2, v4, v3
+; GFX89-NEXT: v_lshl_or_b32 v2, v3, 16, v4
; GFX89-NEXT: flat_store_dword v[0:1], v2
; GFX89-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
index c026a42993d48..0f10241e3bccc 100644
--- a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
@@ -3697,9 +3697,8 @@ define <2 x half> @select_fneg_posk_src_fma_v2f16(<2 x i32> %c, <2 x half> %x, <
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; VI-NEXT: v_fma_f16 v1, v4, 4.0, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_fma_f16 v2, v2, 4.0, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; VI-NEXT: v_mov_b32_e32 v2, 0x4000
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
@@ -3797,9 +3796,8 @@ define <2 x half> @select_fneg_posk_src_fmad_v2f16(<2 x i32> %c, <2 x half> %x,
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; VI-NEXT: v_fma_f16 v1, v4, 4.0, v1
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_fma_f16 v2, v2, 4.0, v3
-; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; VI-NEXT: v_mov_b32_e32 v2, 0x4000
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/shl.ll b/llvm/test/CodeGen/AMDGPU/shl.ll
index 7278247d9b45f..0960e64ecd8f2 100644
--- a/llvm/test/CodeGen/AMDGPU/shl.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl.ll
@@ -2135,8 +2135,7 @@ define void @shl_or_k(ptr addrspace(1) %out, i32 %in) {
; VI-LABEL: shl_or_k:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v2
-; VI-NEXT: v_or_b32_e32 v2, 4, v2
+; VI-NEXT: v_lshl_or_b32 v2, v2, 2, 4
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/shl_or.ll b/llvm/test/CodeGen/AMDGPU/shl_or.ll
index efb28c8860853..3c147a53f1ccd 100644
--- a/llvm/test/CodeGen/AMDGPU/shl_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl_or.ll
@@ -11,8 +11,7 @@
define amdgpu_ps float @shl_or(i32 %a, i32 %b, i32 %c) {
; VI-LABEL: shl_or:
; VI: ; %bb.0:
-; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
-; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_lshl_or_b32 v0, v0, v1, v2
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or:
@@ -56,8 +55,7 @@ define amdgpu_ps float @shl_or_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) {
; VI-LABEL: shl_or_vgpr_all2:
; VI: ; %bb.0:
-; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
-; VI-NEXT: v_or_b32_e32 v0, v2, v0
+; VI-NEXT: v_lshl_or_b32 v0, v0, v1, v2
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or_vgpr_all2:
@@ -78,8 +76,7 @@ define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) {
define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
; VI-LABEL: shl_or_vgpr_ac:
; VI: ; %bb.0:
-; VI-NEXT: v_lshlrev_b32_e32 v0, s2, v0
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v0, s2, v1
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or_vgpr_ac:
@@ -100,8 +97,7 @@ define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) {
; VI-LABEL: shl_or_vgpr_const:
; VI: ; %bb.0:
-; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
-; VI-NEXT: v_or_b32_e32 v0, 6, v0
+; VI-NEXT: v_lshl_or_b32 v0, v0, v1, 6
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or_vgpr_const:
@@ -122,8 +118,7 @@ define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) {
define amdgpu_ps float @shl_or_vgpr_const2(i32 %a, i32 %b) {
; VI-LABEL: shl_or_vgpr_const2:
; VI: ; %bb.0:
-; VI-NEXT: v_lshlrev_b32_e32 v0, 6, v0
-; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshl_or_b32 v0, v0, 6, v1
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or_vgpr_const2:
@@ -166,8 +161,7 @@ define amdgpu_ps float @shl_or_vgpr_const_scalar1(i32 inreg %a, i32 %b) {
define amdgpu_ps float @shl_or_vgpr_const_scalar2(i32 %a, i32 inreg %b) {
; VI-LABEL: shl_or_vgpr_const_scalar2:
; VI: ; %bb.0:
-; VI-NEXT: v_lshlrev_b32_e32 v0, 6, v0
-; VI-NEXT: v_or_b32_e32 v0, s2, v0
+; VI-NEXT: v_lshl_or_b32 v0, v0, 6, s2
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or_vgpr_const_scalar2:
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
index 9304154d30ad7..3a0d3a1abba03 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
@@ -2320,14 +2320,13 @@ define amdgpu_kernel void @v_test_v2i16_x_sub_7_0(ptr addrspace(1) %out, ptr add
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1]
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; VI-GISEL-NEXT: v_add_u16_e32 v3, -7, v3
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-GISEL-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
@@ -3088,14 +3087,13 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg32_0(ptr addrspace(1) %out, ptr
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1]
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; VI-GISEL-NEXT: v_add_u16_e32 v3, 0xffe0, v3
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-GISEL-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
@@ -3463,14 +3461,13 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg16_0(ptr addrspace(1) %out, ptr
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1]
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
+; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; VI-GISEL-NEXT: v_add_u16_e32 v3, -16, v3
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-GISEL-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-GISEL-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
index 76f8f484fc763..814b0723aab1b 100644
--- a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
@@ -861,20 +861,19 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-NEXT: v_cmp_gt_i32_sdwa vcc, sext(v1), sext(v2) src0_sel:WORD_0 src1_sel:WORD_0
-; GFX9-NEXT: v_cmp_gt_i32_sdwa s[0:1], sext(v1), sext(v2) src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX9-NEXT: v_cndmask_b32_e32 v5, v2, v1, vcc
+; GFX9-NEXT: v_cmp_gt_i32_sdwa s[0:1], sext(v1), sext(v2) src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v6, v4, v3, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v5
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2
; GFX9-NEXT: v_lshl_or_b32 v4, v6, 16, v4
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 1, v5
; GFX9-NEXT: global_store_dword v0, v4, s[8:9]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v0, v1, s[10:11]
@@ -916,11 +915,10 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[0:1]
; VI-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_lshlrev_b32_e32 v5, 1, v5
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: flat_store_dword v[0:1], v6
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_e32 v0, v9, v5
+; VI-NEXT: v_lshl_or_b32 v0, v5, 1, v9
; VI-NEXT: v_or_b32_sdwa v4, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_and_b32_e32 v0, 3, v0
; VI-NEXT: flat_store_dword v[2:3], v4
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
index f08b68f9b8c38..1b655c6a52335 100644
--- a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
@@ -569,8 +569,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:1124 ; 4-byte Folded Reload
; CHECK-NEXT: v_accvgpr_write_b32 a16, v58
; CHECK-NEXT: v_accvgpr_write_b32 a17, v59
-; CHECK-NEXT: v_accvgpr_read_b32 v60, a36
; CHECK-NEXT: v_accvgpr_read_b32 v58, a40
+; CHECK-NEXT: v_accvgpr_read_b32 v60, a36
; CHECK-NEXT: s_xor_b64 s[54:55], exec, -1
; CHECK-NEXT: s_waitcnt vmcnt(29)
; CHECK-NEXT: v_xor_b32_e32 v28, v28, v18
@@ -592,46 +592,44 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_xor_b32_e32 v34, v36, v10
; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
-; CHECK-NEXT: v_accvgpr_read_b32 v31, a39
; CHECK-NEXT: v_accvgpr_read_b32 v30, a46
-; CHECK-NEXT: v_xor_b32_e32 v33, v35, v9
-; CHECK-NEXT: s_waitcnt vmcnt(20)
-; CHECK-NEXT: v_xor_b32_e32 v35, v39, v13
+; CHECK-NEXT: v_accvgpr_read_b32 v31, a39
; CHECK-NEXT: s_waitcnt vmcnt(15)
; CHECK-NEXT: v_xor_b32_e32 v10, v44, v30
; CHECK-NEXT: v_accvgpr_read_b32 v30, a44
+; CHECK-NEXT: v_xor_b32_e32 v33, v35, v9
+; CHECK-NEXT: v_xor_b32_e32 v35, v39, v13
; CHECK-NEXT: s_waitcnt vmcnt(11)
; CHECK-NEXT: v_xor_b32_e32 v6, v48, v30
; CHECK-NEXT: v_accvgpr_read_b32 v30, a42
-; CHECK-NEXT: v_xor_b32_e32 v9, v47, v21
-; CHECK-NEXT: s_waitcnt vmcnt(8)
-; CHECK-NEXT: v_xor_b32_e32 v21, v51, v25
-; CHECK-NEXT: v_accvgpr_write_b32 a36, v0
+; CHECK-NEXT: v_xor_b32_e32 v8, v46, v20
+; CHECK-NEXT: s_waitcnt vmcnt(9)
+; CHECK-NEXT: v_xor_b32_e32 v20, v50, v30
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a38
; CHECK-NEXT: s_waitcnt vmcnt(6)
; CHECK-NEXT: v_xor_b32_e32 v13, v53, v31
; CHECK-NEXT: v_accvgpr_read_b32 v31, a29
; CHECK-NEXT: s_waitcnt vmcnt(4)
; CHECK-NEXT: v_xor_b32_e32 v1, v55, v31
-; CHECK-NEXT: s_waitcnt vmcnt(3)
-; CHECK-NEXT: v_xor_b32_e32 v25, v56, v60
-; CHECK-NEXT: v_xor_b32_e32 v8, v46, v20
-; CHECK-NEXT: v_xor_b32_e32 v20, v50, v30
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a38
-; CHECK-NEXT: v_xor_b32_e32 v0, v54, v58
-; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; CHECK-NEXT: v_xor_b32_e32 v11, v45, v19
; CHECK-NEXT: v_xor_b32_e32 v19, v27, v5
+; CHECK-NEXT: v_accvgpr_write_b32 a36, v0
; CHECK-NEXT: v_xor_b32_e32 v4, v52, v30
-; CHECK-NEXT: v_xor_b32_e32 v30, v26, v2
-; CHECK-NEXT: v_lshlrev_b32_e32 v5, 17, v25
-; CHECK-NEXT: v_lshrrev_b64 v[2:3], 14, v[0:1]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v5
+; CHECK-NEXT: v_xor_b32_e32 v0, v54, v58
+; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffffff, v13
; CHECK-NEXT: v_xor_b32_e32 v18, v38, v12
+; CHECK-NEXT: v_xor_b32_e32 v30, v26, v2
+; CHECK-NEXT: v_lshrrev_b64 v[2:3], 14, v[0:1]
; CHECK-NEXT: v_lshlrev_b32_e32 v12, 18, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 13, v[4:5]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v12
+; CHECK-NEXT: v_xor_b32_e32 v9, v47, v21
; CHECK-NEXT: v_xor_b32_e32 v7, v49, v23
+; CHECK-NEXT: v_xor_b32_e32 v21, v51, v25
+; CHECK-NEXT: s_waitcnt vmcnt(3)
+; CHECK-NEXT: v_xor_b32_e32 v25, v56, v60
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v12
+; CHECK-NEXT: v_lshl_or_b32 v3, v25, 17, v3
; CHECK-NEXT: v_and_b32_e32 v21, 0x7fffffff, v21
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
@@ -662,21 +660,18 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_addc_co_u32_e64 v13, s[38:39], 0, v37, s[38:39]
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:80
; CHECK-NEXT: s_movk_i32 s38, 0x7c
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 19, v4
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 12, v[20:21]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v0
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 20, v20
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 11, v[6:7]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v4, 19, v3
+; CHECK-NEXT: v_lshl_or_b32 v1, v20, 20, v1
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:64
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 22, v8
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 21, v6
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a12
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 10, v[8:9]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 9, v[10:11]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v6, 21, v3
+; CHECK-NEXT: v_lshl_or_b32 v1, v8, 22, v1
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:48
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 26, v18
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a36
; CHECK-NEXT: v_add_co_u32_e64 v0, s[38:39], s38, v36
; CHECK-NEXT: v_addc_co_u32_e64 v1, s[38:39], 0, v37, s[38:39]
; CHECK-NEXT: v_lshrrev_b32_e32 v2, 15, v23
@@ -687,51 +682,42 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_addc_co_u32_e64 v1, s[38:39], 0, v37, s[38:39]
; CHECK-NEXT: flat_store_dword v[0:1], v2
; CHECK-NEXT: v_and_b32_e32 v0, 0x7fffffff, v19
-; CHECK-NEXT: v_lshlrev_b32_e32 v1, 31, v28
-; CHECK-NEXT: v_or_b32_e32 v31, v0, v1
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 23, v10
+; CHECK-NEXT: v_lshl_or_b32 v31, v28, 31, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 8, v[16:17]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_lshl_or_b32 v1, v10, 23, v1
; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:64
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 24, v16
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 7, v[14:15]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_lshl_or_b32 v1, v16, 24, v1
; CHECK-NEXT: v_and_b32_e32 v19, 0x7fffffff, v35
+; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v62
; CHECK-NEXT: flat_store_dwordx2 v[12:13], v[0:1] offset:32
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 25, v14
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 6, v[18:19]
-; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v62
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 5, v[34:35]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v14, 25, v3
+; CHECK-NEXT: v_lshl_or_b32 v1, v18, 26, v1
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:16
-; CHECK-NEXT: v_accvgpr_read_b32 v6, a36
+; CHECK-NEXT: s_nop 0
; CHECK-NEXT: v_mov_b32_e32 v0, v33
; CHECK-NEXT: v_and_b32_e32 v33, 0x7fffffff, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 4, v[32:33]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 27, v34
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_lshl_or_b32 v1, v34, 27, v1
; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:32
; CHECK-NEXT: v_accvgpr_read_b32 v0, a27
; CHECK-NEXT: v_accvgpr_read_b32 v2, a36
; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 3, v[2:3]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 28, v32
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_lshl_or_b32 v1, v32, 28, v1
; CHECK-NEXT: flat_store_dwordx2 v[12:13], v[0:1]
; CHECK-NEXT: v_mov_b32_e32 v0, v29
; CHECK-NEXT: v_accvgpr_read_b32 v2, a12
; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[2:3]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v6
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_lshl_or_b32 v1, v6, 29, v1
; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:16
; CHECK-NEXT: v_accvgpr_read_b32 v0, a9
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a12
; CHECK-NEXT: v_and_b32_e32 v29, 0x7fffffff, v0
; CHECK-NEXT: v_lshrrev_b64 v[32:33], 1, v[28:29]
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v4
-; CHECK-NEXT: v_or_b32_e32 v33, v33, v0
+; CHECK-NEXT: v_lshl_or_b32 v33, v4, 30, v33
; CHECK-NEXT: flat_store_dwordx4 v[36:37], v[30:33]
; CHECK-NEXT: .LBB0_3: ; %Flow52
; CHECK-NEXT: s_or_b64 exec, exec, s[52:53]
@@ -930,65 +916,53 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: flat_store_dword v[0:1], v2
; CHECK-NEXT: v_accvgpr_read_b32 v2, a26
; CHECK-NEXT: v_accvgpr_read_b32 v3, a27
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 31, v10
-; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v9
; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; CHECK-NEXT: v_or_b32_e32 v9, v1, v0
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 17, v4
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 14, v[2:3]
; CHECK-NEXT: v_and_b32_e32 v37, 0x7fffffff, v37
+; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v9
; CHECK-NEXT: v_or_b32_e32 v5, v5, v0
; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v34
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 18, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 13, v[36:37]
+; CHECK-NEXT: v_lshl_or_b32 v9, v10, 31, v1
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v35, vcc
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:80
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 20, v30
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v36
+; CHECK-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 12, v[30:31]
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 11, v[32:33]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_lshl_or_b32 v5, v36, 19, v5
+; CHECK-NEXT: v_lshl_or_b32 v3, v30, 20, v3
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:64
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 22, v28
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 21, v32
+; CHECK-NEXT: v_lshl_or_b32 v11, v12, 30, v11
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 10, v[28:29]
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 9, v[20:21]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_lshl_or_b32 v5, v32, 21, v5
+; CHECK-NEXT: v_lshl_or_b32 v3, v28, 22, v3
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:48
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 26, v24
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v20
+; CHECK-NEXT: flat_store_dwordx4 v[34:35], v[8:11]
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[26:27]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v20, 23, v3
; CHECK-NEXT: flat_store_dwordx2 v[34:35], v[2:3] offset:64
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v26
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[18:19]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v26, 24, v3
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3] offset:32
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 25, v18
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 6, v[24:25]
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 5, v[16:17]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_lshl_or_b32 v5, v18, 25, v5
+; CHECK-NEXT: v_lshl_or_b32 v3, v24, 26, v3
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:16
-; CHECK-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v16
+; CHECK-NEXT: s_nop 0
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[22:23]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v16, 27, v3
; CHECK-NEXT: flat_store_dwordx2 v[34:35], v[2:3] offset:32
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v22
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 3, v[14:15]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v22, 28, v3
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v14
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[12:13]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_lshl_or_b32 v1, v14, 29, v1
; CHECK-NEXT: flat_store_dwordx2 v[34:35], v[0:1] offset:16
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v12
-; CHECK-NEXT: v_or_b32_e32 v11, v11, v0
-; CHECK-NEXT: flat_store_dwordx4 v[34:35], v[8:11]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: ; kill: killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: .LBB0_41: ; %Flow
@@ -1043,7 +1017,7 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_and_b32_e32 v31, 0x7fffffff, v31
; CHECK-NEXT: v_and_b32_e32 v33, 0x7fffffff, v33
; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v35
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 18, v36
+; CHECK-NEXT: v_and_b32_e32 v37, 0x7fffffff, v37
; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v52
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v53, vcc
; CHECK-NEXT: v_lshrrev_b32_e32 v2, 15, v39
@@ -1052,63 +1026,49 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_alignbit_b32 v2, v39, v38, 15
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v53, vcc
; CHECK-NEXT: flat_store_dword v[0:1], v2
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 31, v10
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v9
-; CHECK-NEXT: v_and_b32_e32 v37, 0x7fffffff, v37
-; CHECK-NEXT: v_or_b32_e32 v9, v1, v0
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 17, v38
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 14, v[36:37]
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v0
; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v52
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 13, v[34:35]
+; CHECK-NEXT: v_lshl_or_b32 v9, v10, 31, v1
+; CHECK-NEXT: v_lshl_or_b32 v5, v38, 17, v5
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v53, vcc
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_lshl_or_b32 v3, v36, 18, v3
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:80
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 20, v32
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v34
+; CHECK-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 12, v[32:33]
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 11, v[30:31]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_lshl_or_b32 v5, v34, 19, v5
+; CHECK-NEXT: v_lshl_or_b32 v3, v32, 20, v3
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:64
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 22, v28
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 21, v30
+; CHECK-NEXT: v_lshl_or_b32 v11, v12, 30, v11
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 10, v[28:29]
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 9, v[26:27]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_lshl_or_b32 v5, v30, 21, v5
+; CHECK-NEXT: v_lshl_or_b32 v3, v28, 22, v3
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:48
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 26, v20
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v26
+; CHECK-NEXT: flat_store_dwordx4 v[52:53], v[8:11]
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[24:25]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v26, 23, v3
; CHECK-NEXT: flat_store_dwordx2 v[52:53], v[2:3] offset:64
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v24
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[22:23]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v24, 24, v3
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3] offset:32
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 25, v22
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 6, v[20:21]
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 5, v[18:19]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_lshl_or_b32 v5, v22, 25, v5
+; CHECK-NEXT: v_lshl_or_b32 v3, v20, 26, v3
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:16
-; CHECK-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v18
+; CHECK-NEXT: s_nop 0
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[16:17]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v18, 27, v3
; CHECK-NEXT: flat_store_dwordx2 v[52:53], v[2:3] offset:32
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v16
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 3, v[14:15]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v16, 28, v3
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v14
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[12:13]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_lshl_or_b32 v1, v14, 29, v1
; CHECK-NEXT: flat_store_dwordx2 v[52:53], v[0:1] offset:16
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v12
-; CHECK-NEXT: v_or_b32_e32 v11, v11, v0
-; CHECK-NEXT: flat_store_dwordx4 v[52:53], v[8:11]
; CHECK-NEXT: .LBB0_43: ; %Flow48
; CHECK-NEXT: s_or_b64 exec, exec, s[56:57]
; CHECK-NEXT: s_andn2_b64 s[48:49], s[48:49], exec
@@ -1157,12 +1117,12 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1620 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1624 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1628 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:1488 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:1492 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1480 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1484 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 17, v32
; CHECK-NEXT: v_and_b32_e32 v59, 0x7fffffff, v59
@@ -1171,15 +1131,10 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_and_b32_e32 v49, 0x7fffffff, v49
; CHECK-NEXT: v_and_b32_e32 v43, 0x7fffffff, v43
; CHECK-NEXT: v_and_b32_e32 v4, 0x7fffffff, v1
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v10
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
-; CHECK-NEXT: flat_store_short v[0:1], v33
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x78, v10
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
-; CHECK-NEXT: flat_store_dword v[0:1], v36
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 31, v42
+; CHECK-NEXT: v_lshl_or_b32 v41, v42, 31, v4
+; CHECK-NEXT: v_lshrrev_b64 v[42:43], 1, v[42:43]
+; CHECK-NEXT: v_lshl_or_b32 v43, v48, 30, v43
; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
-; CHECK-NEXT: v_or_b32_e32 v41, v4, v0
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 14, v[2:3]
; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
; CHECK-NEXT: v_or_b32_e32 v5, v5, v6
@@ -1188,74 +1143,67 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:1472 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1476 ; 4-byte Folded Reload
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v10
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
+; CHECK-NEXT: flat_store_short v[0:1], v33
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x78, v10
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
+; CHECK-NEXT: flat_store_dword v[0:1], v36
; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v10
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:80
-; CHECK-NEXT: v_lshrrev_b64 v[42:43], 1, v[42:43]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v8
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a32
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a33
-; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
+; CHECK-NEXT: flat_store_dwordx4 v[10:11], v[40:43]
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 12, v[6:7]
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 20, v6
+; CHECK-NEXT: v_lshl_or_b32 v5, v8, 19, v5
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a32
+; CHECK-NEXT: v_accvgpr_read_b32 v9, a33
+; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 11, v[8:9]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_lshl_or_b32 v3, v6, 20, v3
; CHECK-NEXT: v_accvgpr_read_b32 v6, a34
-; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:64
; CHECK-NEXT: v_accvgpr_read_b32 v7, a35
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 21, v8
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a24
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a25
+; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:64
+; CHECK-NEXT: s_nop 0
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 10, v[6:7]
+; CHECK-NEXT: v_lshl_or_b32 v5, v8, 21, v5
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a24
+; CHECK-NEXT: v_accvgpr_read_b32 v9, a25
; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 22, v6
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 9, v[8:9]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_lshl_or_b32 v3, v6, 22, v3
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:48
; CHECK-NEXT: v_accvgpr_read_b32 v6, a22
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v8
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[58:59]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v8, 23, v3
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a20
; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[2:3] offset:64
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v58
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[50:51]
; CHECK-NEXT: v_accvgpr_read_b32 v7, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a20
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
-; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: v_accvgpr_read_b32 v9, a21
+; CHECK-NEXT: v_lshl_or_b32 v3, v58, 24, v3
+; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
+; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3] offset:32
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 25, v50
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 6, v[6:7]
-; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
-; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 26, v6
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 5, v[8:9]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
+; CHECK-NEXT: v_lshl_or_b32 v5, v50, 25, v5
+; CHECK-NEXT: v_lshl_or_b32 v3, v6, 26, v3
; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:16
; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v8
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[56:57]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v8, 27, v3
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[2:3] offset:32
-; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v56
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 3, v[6:7]
-; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
+; CHECK-NEXT: v_lshl_or_b32 v3, v56, 28, v3
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
-; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v6
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[48:49]
-; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
+; CHECK-NEXT: v_lshl_or_b32 v1, v6, 29, v1
; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[0:1] offset:16
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v48
-; CHECK-NEXT: v_or_b32_e32 v43, v43, v0
-; CHECK-NEXT: flat_store_dwordx4 v[10:11], v[40:43]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: ; kill: killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
index c975f3a9ba946..2222a3a7baff4 100644
--- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll
+++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
@@ -155,9 +155,8 @@ define amdgpu_kernel void @kernel_call_align16_from_8() #0 {
; GCN-NEXT: s_add_u32 s14, s14, needs_align16_default_stack_align at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s15, s15, needs_align16_default_stack_align at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[18:19], s[14:15], 0x0
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GCN-NEXT: v_mov_b32_e32 v3, 2
; GCN-NEXT: v_or_b32_e32 v31, v0, v2
; GCN-NEXT: s_mov_b32 s14, s16
@@ -188,9 +187,8 @@ define amdgpu_kernel void @kernel_call_align16_from_5() #6 {
; GCN-NEXT: s_add_u32 s14, s14, needs_align16_default_stack_align at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s15, s15, needs_align16_default_stack_align at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[18:19], s[14:15], 0x0
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GCN-NEXT: v_mov_b32_e32 v3, 2
; GCN-NEXT: v_or_b32_e32 v31, v0, v2
; GCN-NEXT: s_mov_b32 s14, s16
@@ -221,9 +219,8 @@ define amdgpu_kernel void @kernel_call_align4_from_5() #6 {
; GCN-NEXT: s_add_u32 s14, s14, needs_align16_stack_align4 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s15, s15, needs_align16_stack_align4 at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[18:19], s[14:15], 0x0
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_or_b32_e32 v0, v0, v1
+; GCN-NEXT: v_lshl_or_b32 v0, v1, 10, v0
; GCN-NEXT: v_mov_b32_e32 v3, 2
; GCN-NEXT: v_or_b32_e32 v31, v0, v2
; GCN-NEXT: s_mov_b32 s14, s16
diff --git a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
index 480eb0dd5fe9c..e56dd62834280 100644
--- a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
@@ -94,8 +94,7 @@ define amdgpu_kernel void @local_store_i55(ptr addrspace(3) %ptr, i55 %arg) #0 {
; FIJI-NEXT: v_mov_b32_e32 v1, s2
; FIJI-NEXT: ds_write_b16 v1, v2 offset:4
; FIJI-NEXT: s_waitcnt vmcnt(0)
-; FIJI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; FIJI-NEXT: v_or_b32_e32 v0, s4, v0
+; FIJI-NEXT: v_lshl_or_b32 v0, v0, 16, s4
; FIJI-NEXT: v_bfe_u32 v0, v0, 16, 7
; FIJI-NEXT: ds_write_b8 v1, v0 offset:6
; FIJI-NEXT: ds_write_b32 v1, v3
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
index f695526737311..eec02c141ca3e 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
@@ -47,9 +47,8 @@ define <2 x half> @v_constained_fma_v2f16_fpexcept_strict(<2 x half> %x, <2 x ha
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX8-NEXT: v_fma_f16 v3, v5, v4, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX8-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_constained_fma_v2f16_fpexcept_strict:
@@ -82,9 +81,8 @@ define <3 x half> @v_constained_fma_v3f16_fpexcept_strict(<3 x half> %x, <3 x ha
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX8-NEXT: v_fma_f16 v6, v8, v7, v6
-; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v6
+; GFX8-NEXT: v_lshl_or_b32 v0, v6, 16, v0
; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -143,12 +141,10 @@ define <4 x half> @v_constained_fma_v4f16_fpexcept_strict(<4 x half> %x, <4 x ha
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; GFX8-NEXT: v_fma_f16 v7, v9, v8, v7
-; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v7
; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
-; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v6
-; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
+; GFX8-NEXT: v_lshl_or_b32 v0, v7, 16, v0
+; GFX8-NEXT: v_lshl_or_b32 v1, v6, 16, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_constained_fma_v4f16_fpexcept_strict:
@@ -301,9 +297,8 @@ define <2 x half> @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg(<2 x half> %
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX8-NEXT: v_fma_f16 v3, -v5, -v4, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX8-NEXT: v_fma_f16 v0, -v0, -v1, v2
-; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
+; GFX8-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg:
diff --git a/llvm/test/CodeGen/AMDGPU/trunc-store.ll b/llvm/test/CodeGen/AMDGPU/trunc-store.ll
index b22a824b1a3c7..fdf10b1d52188 100644
--- a/llvm/test/CodeGen/AMDGPU/trunc-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/trunc-store.ll
@@ -59,30 +59,26 @@ define amdgpu_kernel void @truncstore_arg_v16i32_to_v16i8(ptr addrspace(1) %out,
; VI-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_perm_b32 v2, s22, v2, v0
+; VI-NEXT: v_mov_b32_e32 v2, s23
; VI-NEXT: v_perm_b32 v1, s20, v1, v0
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v3, v1, v2
-; VI-NEXT: v_mov_b32_e32 v2, s19
+; VI-NEXT: v_perm_b32 v2, s22, v2, v0
+; VI-NEXT: v_lshl_or_b32 v3, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v1, s17
-; VI-NEXT: v_perm_b32 v2, s18, v2, v0
+; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v1, s16, v1, v0
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v4, s15
-; VI-NEXT: v_or_b32_e32 v2, v1, v2
+; VI-NEXT: v_perm_b32 v2, s18, v2, v0
+; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v1, s13
-; VI-NEXT: v_perm_b32 v4, s14, v4, v0
+; VI-NEXT: v_mov_b32_e32 v4, s15
; VI-NEXT: v_perm_b32 v1, s12, v1, v0
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v1, v1, v4
+; VI-NEXT: v_perm_b32 v4, s14, v4, v0
+; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
; VI-NEXT: v_mov_b32_e32 v4, s9
; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_perm_b32 v4, s8, v4, v0
; VI-NEXT: v_perm_b32 v0, s10, v5, v0
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_or_b32_e32 v0, v4, v0
+; VI-NEXT: v_lshl_or_b32 v0, v0, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -147,34 +143,30 @@ define amdgpu_kernel void @truncstore_arg_v16i64_to_v16i8(ptr addrspace(1) %out,
; VI-LABEL: truncstore_arg_v16i64_to_v16i8:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx16 s[16:31], s[4:5], 0xe4
-; VI-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; VI-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
; VI-NEXT: s_load_dwordx16 s[0:15], s[4:5], 0xa4
+; VI-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v2, s30
; VI-NEXT: v_mov_b32_e32 v1, s26
-; VI-NEXT: v_perm_b32 v2, s28, v2, v0
+; VI-NEXT: v_mov_b32_e32 v2, s30
; VI-NEXT: v_perm_b32 v1, s24, v1, v0
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_or_b32_e32 v3, v1, v2
-; VI-NEXT: v_mov_b32_e32 v2, s22
+; VI-NEXT: v_perm_b32 v2, s28, v2, v0
+; VI-NEXT: v_lshl_or_b32 v3, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v1, s18
-; VI-NEXT: v_perm_b32 v2, s20, v2, v0
+; VI-NEXT: v_mov_b32_e32 v2, s22
; VI-NEXT: v_perm_b32 v1, s16, v1, v0
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_mov_b32_e32 v4, s14
-; VI-NEXT: v_or_b32_e32 v2, v1, v2
+; VI-NEXT: v_perm_b32 v2, s20, v2, v0
+; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v1
; VI-NEXT: v_mov_b32_e32 v1, s10
-; VI-NEXT: v_perm_b32 v4, s12, v4, v0
+; VI-NEXT: v_mov_b32_e32 v4, s14
; VI-NEXT: v_perm_b32 v1, s8, v1, v0
-; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; VI-NEXT: v_or_b32_e32 v1, v1, v4
+; VI-NEXT: v_perm_b32 v4, s12, v4, v0
+; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s0, v4, v0
; VI-NEXT: v_perm_b32 v0, s4, v5, v0
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; VI-NEXT: v_or_b32_e32 v0, v4, v0
+; VI-NEXT: v_lshl_or_b32 v0, v0, 16, v4
; VI-NEXT: v_mov_b32_e32 v4, s34
; VI-NEXT: v_mov_b32_e32 v5, s35
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -261,8 +253,7 @@ define void @truncstore_v5i32_to_v5i8(ptr addrspace(1) %out, <5 x i32> %val) {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v3, v4, v5, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v4, v2, v3
+; VI-NEXT: v_lshl_or_b32 v4, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: flat_store_byte v[2:3], v6
@@ -360,8 +351,7 @@ define void @truncstore_v6i32_to_v6i8(ptr addrspace(1) %out, <6 x i32> %val) {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v3, v4, v5, s4
-; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; VI-NEXT: v_or_b32_e32 v4, v2, v3
+; VI-NEXT: v_lshl_or_b32 v4, v3, 16, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: v_perm_b32 v5, v6, v7, s4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index 859a65f88800d..0dec2e18b9569 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -1727,15 +1727,11 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: buffer_load_ushort v3, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_or_b32_e32 v0, v1, v0
+; VI-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; VI-NEXT: v_cvt_f32_u32_e32 v0, v0
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_e32 v1, v3, v1
+; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v3
; VI-NEXT: v_cvt_f32_u32_e32 v1, v1
; VI-NEXT: v_rcp_f32_e32 v2, v0
; VI-NEXT: v_mul_f32_e32 v2, v1, v2
@@ -1773,15 +1769,11 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: flat_load_ubyte v0, v[0:1]
; GCN-NEXT: flat_load_ushort v1, v[2:3]
-; GCN-NEXT: s_waitcnt vmcnt(3)
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v6
; GCN-NEXT: s_waitcnt vmcnt(2)
-; GCN-NEXT: v_or_b32_e32 v2, v4, v2
+; GCN-NEXT: v_lshl_or_b32 v2, v6, 16, v4
; GCN-NEXT: v_cvt_f32_u32_e32 v2, v2
-; GCN-NEXT: s_waitcnt vmcnt(1)
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_or_b32_e32 v0, v1, v0
+; GCN-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0
; GCN-NEXT: v_rcp_f32_e32 v4, v2
; GCN-NEXT: v_mov_b32_e32 v0, s0
@@ -1806,17 +1798,13 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1030-NEXT: global_load_ushort v2, v0, s[2:3] offset:4
; GFX1030-NEXT: global_load_ubyte v3, v0, s[2:3] offset:2
; GFX1030-NEXT: global_load_ushort v4, v0, s[2:3]
-; GFX1030-NEXT: s_waitcnt vmcnt(3)
-; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1030-NEXT: s_waitcnt vmcnt(2)
-; GFX1030-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX1030-NEXT: s_waitcnt vmcnt(1)
-; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX1030-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX1030-NEXT: s_waitcnt vmcnt(0)
-; GFX1030-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX1030-NEXT: v_rcp_f32_e32 v3, v1
+; GFX1030-NEXT: v_lshl_or_b32 v2, v3, 16, v4
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX1030-NEXT: v_rcp_f32_e32 v3, v1
; GFX1030-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1030-NEXT: v_trunc_f32_e32 v3, v3
; GFX1030-NEXT: v_fma_f32 v2, -v3, v1, v2
@@ -1937,17 +1925,13 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: buffer_load_ushort v3, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_or_b32_e32 v0, v1, v0
+; VI-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; VI-NEXT: v_cvt_f32_u32_e32 v1, v0
; VI-NEXT: v_sub_u32_e32 v4, vcc, 0, v0
-; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; VI-NEXT: v_rcp_f32_e32 v1, v1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_e32 v2, v3, v2
+; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-NEXT: v_rcp_f32_e32 v1, v1
; VI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
; VI-NEXT: v_mul_lo_u32 v4, v4, v1
@@ -1993,17 +1977,13 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mov_b32_e32 v1, s3
; GCN-NEXT: flat_load_ubyte v2, v[2:3]
; GCN-NEXT: flat_load_ushort v0, v[0:1]
-; GCN-NEXT: s_waitcnt vmcnt(3)
-; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; GCN-NEXT: s_waitcnt vmcnt(2)
-; GCN-NEXT: v_or_b32_e32 v3, v5, v1
+; GCN-NEXT: v_lshl_or_b32 v3, v4, 16, v5
; GCN-NEXT: v_cvt_f32_u32_e32 v1, v3
; GCN-NEXT: v_sub_u32_e32 v4, vcc, 0, v3
-; GCN-NEXT: s_waitcnt vmcnt(1)
-; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_rcp_f32_e32 v1, v1
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_or_b32_e32 v2, v0, v2
+; GCN-NEXT: v_lshl_or_b32 v2, v2, 16, v0
; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
; GCN-NEXT: v_mul_lo_u32 v4, v4, v1
diff --git a/llvm/test/CodeGen/AMDGPU/v_lshl_or_b32.mir b/llvm/test/CodeGen/AMDGPU/v_lshl_or_b32.mir
new file mode 100644
index 0000000000000..3d2a15b689dcf
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/v_lshl_or_b32.mir
@@ -0,0 +1,131 @@
+# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
+# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX10P %s
+# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx1201 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX10P %s
+
+# Post-RA fusion of v_lshlrev_b32 + v_or_b32 into v_lshl_or_b32 in
+# SIShrinkInstructions::matchLshlOr.
+
+---
+# Simple adjacent pair, shift amount is an inline immediate.
+# GCN-LABEL: name: lshl_or_adjacent
+# GCN: $vgpr0 = V_LSHL_OR_B32_e64 $vgpr1, 16, $vgpr2, implicit $exec
+# GCN-NOT: V_LSHLREV_B32
+# GCN-NOT: V_OR_B32
+name: lshl_or_adjacent
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr1, $vgpr2, $sgpr30_sgpr31
+ $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
+ $vgpr0 = V_OR_B32_e32 killed $vgpr0, $vgpr2, implicit $exec
+ S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+...
+
+---
+# Same as above but with the killed source on the other side of the or
+# (v_or_b32 is commutative).
+# GCN-LABEL: name: lshl_or_commuted
+# GCN: $vgpr0 = V_LSHL_OR_B32_e64 $vgpr1, 16, $vgpr2, implicit $exec
+# GCN-NOT: V_LSHLREV_B32
+# GCN-NOT: V_OR_B32
+name: lshl_or_commuted
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr1, $vgpr2, $sgpr30_sgpr31
+ $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
+ $vgpr0 = V_OR_B32_e32 $vgpr2, killed $vgpr0, implicit $exec
+ S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+...
+
+---
+# A few intervening instructions that don't touch the shift result. Still fuses
+# because the search window is 16 instructions.
+# GCN-LABEL: name: lshl_or_sparse
+# GCN: $vgpr0 = V_LSHL_OR_B32_e64 $vgpr1, 16, $vgpr2, implicit $exec
+# GCN-NOT: V_LSHLREV_B32
+name: lshl_or_sparse
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31
+ $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
+ $vgpr3 = V_ADD_U32_e32 $vgpr4, $vgpr5, implicit $exec
+ $vgpr4 = V_MUL_U32_U24_e32 $vgpr5, $vgpr3, implicit $exec
+ $vgpr0 = V_OR_B32_e32 killed $vgpr0, $vgpr2, implicit $exec
+ S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr3, implicit $vgpr4
+...
+
+---
+# Negative: another instruction reads the shift result before the or, so the
+# shift cannot be removed. Pair must remain unfused.
+# GCN-LABEL: name: lshl_or_multiuse_blocks
+# GCN: $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
+# GCN: V_MOV_B32_e32 $vgpr0, implicit $exec
+# GCN: V_OR_B32_e32 killed $vgpr0, $vgpr2, implicit $exec
+# GCN-NOT: V_LSHL_OR_B32_e64
+name: lshl_or_multiuse_blocks
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr1, $vgpr2, $sgpr30_sgpr31
+ $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
+ $vgpr3 = V_MOV_B32_e32 $vgpr0, implicit $exec
+ $vgpr0 = V_OR_B32_e32 killed $vgpr0, $vgpr2, implicit $exec
+ S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr3
+...
+
+---
+# Negative: shift destination is not killed at the or, so the value escapes.
+# Conservatively keep the original sequence.
+# GCN-LABEL: name: lshl_or_not_killed
+# GCN: $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
+# GCN: V_OR_B32_e32 $vgpr0, $vgpr2, implicit $exec
+# GCN-NOT: V_LSHL_OR_B32_e64
+name: lshl_or_not_killed
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr1, $vgpr2, $sgpr30_sgpr31
+ $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
+ $vgpr3 = V_OR_B32_e32 $vgpr0, $vgpr2, implicit $exec
+ S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr3
+...
+
+---
+# Constant-bus check: two distinct SGPR sources (plus an inline-immediate shift
+# amount) is over the limit on GFX9 (constant-bus limit 1) but within the
+# limit on GFX10+ (limit 2). The peephole must therefore bail on GFX9 and
+# fuse on GFX10+.
+# GCN-LABEL: name: lshl_or_two_sgprs
+# GFX9: V_LSHLREV_B32
+# GFX9: V_OR_B32
+# GFX9-NOT: V_LSHL_OR_B32_e64
+# GFX10P: V_LSHL_OR_B32_e64 $sgpr4, 16, $sgpr5, implicit $exec
+# GFX10P-NOT: V_LSHLREV_B32
+name: lshl_or_two_sgprs
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr4, $sgpr5, $sgpr30_sgpr31
+ $vgpr0 = V_LSHLREV_B32_e64 16, $sgpr4, implicit $exec
+ $vgpr0 = V_OR_B32_e64 killed $vgpr0, $sgpr5, implicit $exec
+ S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+...
+
+---
+# Variable (VGPR) shift amount: should still fuse, since the shift amount is a
+# VGPR (does not consume a constant-bus slot) and both shifted value and or
+# operand are VGPRs.
+# GCN-LABEL: name: lshl_or_var_shift
+# GCN: $vgpr0 = V_LSHL_OR_B32_e64 $vgpr1, $vgpr3, $vgpr2, implicit $exec
+# GCN-NOT: V_LSHLREV_B32
+name: lshl_or_var_shift
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
+ $vgpr0 = V_LSHLREV_B32_e32 $vgpr3, $vgpr1, implicit $exec
+ $vgpr0 = V_OR_B32_e32 killed $vgpr0, $vgpr2, implicit $exec
+ S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll b/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
index f32db0dd5f473..53e01648588e8 100644
--- a/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
@@ -9,11 +9,10 @@ define <2 x half> @v_mac_f16_fpdp_rounding(<2 x half> %a, <2 x half> %c, <2 x ha
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; CHECK-NEXT: v_mac_f16_sdwa v6, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
-; CHECK-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; CHECK-NEXT: v_mac_f16_e32 v1, v0, v2
; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1
; CHECK-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CHECK-NEXT: v_or_b32_e32 v0, v1, v6
+; CHECK-NEXT: v_lshl_or_b32 v0, v6, 16, v1
; CHECK-NEXT: flat_store_short v[4:5], v3
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll b/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
index 8e1a4bf2a2d9f..ea95cc3436840 100644
--- a/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
@@ -365,9 +365,8 @@ entry:
; VI-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
; VI-DAG: v_mac_f16_sdwa v[[C_F16_1]], v[[A_V2_F16]], v[[B_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-DAG: v_mac_f16_e32 v[[C_V2_F16]], v[[A_V2_F16]], v[[B_V2_F16]]
-; VI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[C_F16_1]]
; VI-NOT: and
-; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[C_V2_F16]], v[[R_F16_HI]]
+; VI-DAG: v_lshl_or_b32 v[[R_V2_F16:[0-9]+]], v[[C_F16_1]], 16, v[[C_V2_F16]]
; VI: {{buffer|flat}}_store_dword v[[R_V2_F16]]
; VI: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index 99b6ab7a6401b..ae2dc9beb2f6a 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -166,8 +166,7 @@ define amdgpu_kernel void @basic_smax_smin_sgpr(ptr addrspace(1) %out, i32 inreg
; SDAG-VI-NEXT: s_sext_i32_i16 s3, s3
; SDAG-VI-NEXT: v_med3_i32 v1, s2, 0, v0
; SDAG-VI-NEXT: v_med3_i32 v0, s3, 0, v0
-; SDAG-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; SDAG-VI-NEXT: v_or_b32_e32 v2, v1, v0
+; SDAG-VI-NEXT: v_lshl_or_b32 v2, v0, 16, v1
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
; SDAG-VI-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index efad5770a0261..b19432807ea40 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -355,14 +355,12 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX8-GISEL-NEXT: v_max_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smax_v4i8:
@@ -658,17 +656,15 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX8-GISEL-NEXT: v_max_i16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_i16_e32 v1, s4, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
+; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_max_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smax_v8i8:
@@ -1101,17 +1097,15 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX8-GISEL-NEXT: v_max_i16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_i16_e32 v1, s4, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
+; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_max_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smax_v16i8:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index 2be894755078a..dce58bf30547b 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -355,14 +355,12 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX8-GISEL-NEXT: v_min_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smin_v4i8:
@@ -658,17 +656,15 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX8-GISEL-NEXT: v_min_i16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_min_i16_e32 v1, s4, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
+; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_min_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smin_v8i8:
@@ -1101,17 +1097,15 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX8-GISEL-NEXT: v_min_i16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_min_i16_e32 v1, s4, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
+; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_min_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smin_v16i8:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 2b4a226274b41..489ef64a86369 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -331,14 +331,12 @@ define i8 @test_vector_reduce_umax_v4i8(<4 x i8> %v) {
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX8-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umax_v4i8:
@@ -617,17 +615,15 @@ define i8 @test_vector_reduce_umax_v8i8(<8 x i8> %v) {
; GFX8-GISEL-NEXT: v_max_u16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_u16_e32 v1, 0, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
+; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
; GFX8-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umax_v8i8:
@@ -1023,17 +1019,15 @@ define i8 @test_vector_reduce_umax_v16i8(<16 x i8> %v) {
; GFX8-GISEL-NEXT: v_max_u16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_u16_e32 v1, 0, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
+; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
; GFX8-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
-; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umax_v16i8:
diff --git a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
index 20789232b1f25..fa7447933d5b3 100644
--- a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
+++ b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
@@ -760,20 +760,19 @@ define amdgpu_kernel void @v8i8_multiuse_multiblock(ptr addrspace(1) %src1, ptr
; GFX942-NEXT: ; %bb.3: ; %bb.2
; GFX942-NEXT: v_lshlrev_b16_e32 v3, 8, v1
; GFX942-NEXT: v_and_b32_e32 v4, 0xffffff00, v1
-; GFX942-NEXT: v_and_b32_e32 v5, 0xffffff00, v0
-; GFX942-NEXT: s_mov_b32 s2, 0xc0c0001
; GFX942-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v5, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX942-NEXT: v_perm_b32 v1, 0, v1, s2
+; GFX942-NEXT: v_and_b32_e32 v5, 0xffffff00, v0
+; GFX942-NEXT: s_mov_b32 s2, 0xc0c0001
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v5, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT: v_perm_b32 v6, 0, v0, s2
; GFX942-NEXT: s_mov_b32 s3, 0xffff0000
-; GFX942-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX942-NEXT: v_perm_b32 v1, 0, v1, s2
; GFX942-NEXT: v_and_or_b32 v7, v0, s3, v6
; GFX942-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_e32 v1, v6, v1
+; GFX942-NEXT: v_lshl_or_b32 v1, v1, 16, v6
; GFX942-NEXT: global_store_dword v2, v3, s[14:15]
; GFX942-NEXT: global_store_dword v2, v4, s[14:15] offset:8
; GFX942-NEXT: global_store_dword v2, v7, s[14:15] offset:16
>From ea13ad2868dbd529815eccee49cceb453bbbcacc Mon Sep 17 00:00:00 2001
From: Barbara Mitic <Barbara.Mitic at amd.com>
Date: Wed, 10 Jun 2026 12:13:52 +0200
Subject: [PATCH 2/3] Revert "[AMDGPU] Add post-RA peephole to fuse
v_lshlrev_b32 + v_or_b32 into v_lshl_or_b32"
This reverts commit 29148f8273e3447b2d73ab7475c3cc0119ad89a7.
---
.../Target/AMDGPU/SIShrinkInstructions.cpp | 154 -
.../CodeGen/AMDGPU/GlobalISel/add.v2i16.ll | 6 +-
.../AMDGPU/GlobalISel/atomic_load_flat.ll | 3 +-
.../AMDGPU/GlobalISel/atomic_load_global.ll | 3 +-
.../AMDGPU/GlobalISel/atomic_load_local_2.ll | 3 +-
.../AMDGPU/GlobalISel/cvt_f32_ubyte.ll | 10 +-
.../CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll | 122 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll | 25 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll | 39 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 35 +-
.../test/CodeGen/AMDGPU/GlobalISel/saddsat.ll | 14 +-
.../CodeGen/AMDGPU/GlobalISel/sext_inreg.ll | 3 +-
.../test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll | 14 +-
.../AMDGPU/GlobalISel/strict_fma.f16.ll | 16 +-
.../test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll | 5 +-
.../test/CodeGen/AMDGPU/GlobalISel/usubsat.ll | 5 +-
.../abi-attribute-hints-undefined-behavior.ll | 9 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 9914 ++++++++++-------
.../CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll | 528 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 1338 ++-
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 2402 ++--
.../CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll | 167 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 4733 ++++----
.../CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll | 444 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 497 +-
.../AMDGPU/amdgpu-codegenprepare-idiv.ll | 26 +-
.../atomic_optimizations_global_pointer.ll | 5 +-
...tor-flatscratchinit-undefined-behavior2.ll | 12 +-
.../buffer-fat-pointer-atomicrmw-fadd.ll | 13 +-
.../buffer-fat-pointer-atomicrmw-fmax.ll | 13 +-
.../buffer-fat-pointer-atomicrmw-fmin.ll | 13 +-
.../CodeGen/AMDGPU/calling-conventions.ll | 25 +-
llvm/test/CodeGen/AMDGPU/cc-update.ll | 12 +-
llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll | 22 +-
.../AMDGPU/copysign-to-disjoint-or-combine.ll | 3 +-
llvm/test/CodeGen/AMDGPU/ctlz.ll | 4 +-
llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll | 12 +-
llvm/test/CodeGen/AMDGPU/ctpop16.ll | 162 +-
llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll | 32 +-
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll | 3 +-
llvm/test/CodeGen/AMDGPU/ds_read2.ll | 6 +-
.../test/CodeGen/AMDGPU/extract-i8-codegen.ll | 8 +-
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll | 14 +-
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 53 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fadd.ll | 40 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmax.ll | 40 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fmin.ll | 40 +-
.../CodeGen/AMDGPU/flat-atomicrmw-fsub.ll | 40 +-
llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll | 31 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 84 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 171 +-
llvm/test/CodeGen/AMDGPU/function-args.ll | 234 +-
.../CodeGen/AMDGPU/global-atomicrmw-fadd.ll | 40 +-
.../CodeGen/AMDGPU/global-atomicrmw-fmax.ll | 40 +-
.../CodeGen/AMDGPU/global-atomicrmw-fmin.ll | 40 +-
.../CodeGen/AMDGPU/global-atomicrmw-fsub.ll | 40 +-
llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll | 8 +-
llvm/test/CodeGen/AMDGPU/idot4u.ll | 7 +-
.../CodeGen/AMDGPU/integer-mad-patterns.ll | 124 +-
llvm/test/CodeGen/AMDGPU/itofp.i128.ll | 8 +-
llvm/test/CodeGen/AMDGPU/kernel-args.ll | 3 +-
.../CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll | 3 +-
llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll | 18 +-
llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll | 6 +-
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll | 31 +-
llvm/test/CodeGen/AMDGPU/load-global-i16.ll | 7 +-
llvm/test/CodeGen/AMDGPU/load-hi16.ll | 28 +-
llvm/test/CodeGen/AMDGPU/load-lo16.ll | 18 +-
.../CodeGen/AMDGPU/local-atomicrmw-fadd.ll | 20 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmax.ll | 20 +-
.../CodeGen/AMDGPU/local-atomicrmw-fmin.ll | 20 +-
.../CodeGen/AMDGPU/local-atomicrmw-fsub.ll | 20 +-
...ne-sink-temporal-divergence-swdev407790.ll | 17 +-
.../CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll | 86 +-
llvm/test/CodeGen/AMDGPU/pack.v2i16.ll | 3 +-
llvm/test/CodeGen/AMDGPU/permute_i8.ll | 40 +-
.../promote-constOffset-to-imm-gfx12.mir | 12 +-
.../AMDGPU/reassoc-mul-add-1-to-mad.ll | 24 +-
llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 8 +-
llvm/test/CodeGen/AMDGPU/sdiv.ll | 28 +-
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll | 103 +-
.../AMDGPU/select-fabs-fneg-extract.v2f16.ll | 6 +-
llvm/test/CodeGen/AMDGPU/shl.ll | 3 +-
llvm/test/CodeGen/AMDGPU/shl_or.ll | 18 +-
.../CodeGen/AMDGPU/shrink-add-sub-constant.ll | 15 +-
llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll | 10 +-
.../splitkit-getsubrangeformask-phi-extend.ll | 262 +-
llvm/test/CodeGen/AMDGPU/stack-realign.ll | 9 +-
llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll | 3 +-
llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll | 17 +-
llvm/test/CodeGen/AMDGPU/trunc-store.ll | 56 +-
llvm/test/CodeGen/AMDGPU/udiv.ll | 46 +-
llvm/test/CodeGen/AMDGPU/v_lshl_or_b32.mir | 131 -
.../AMDGPU/v_mac_f16-fpdp-rounding-mode.ll | 3 +-
llvm/test/CodeGen/AMDGPU/v_mac_f16.ll | 3 +-
llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll | 3 +-
.../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 24 +-
.../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 24 +-
.../test/CodeGen/AMDGPU/vector-reduce-umax.ll | 24 +-
.../test/CodeGen/AMDGPU/vni8-across-blocks.ll | 11 +-
100 files changed, 13573 insertions(+), 9524 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/v_lshl_or_b32.mir
diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 85765df01d4b2..d1ed1831cfbec 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -58,7 +58,6 @@ class SIShrinkInstructions {
unsigned I) const;
void dropInstructionKeepingImpDefs(MachineInstr &MI) const;
MachineInstr *matchSwap(MachineInstr &MovT) const;
- MachineInstr *matchLshlOr(MachineInstr &Shift) const;
public:
SIShrinkInstructions() = default;
@@ -851,147 +850,6 @@ MachineInstr *SIShrinkInstructions::matchSwap(MachineInstr &MovT) const {
return nullptr;
}
-// Fuse v_lshlrev_b32 vDst, vAmt, vSrc + v_or_b32 vRes, vDst, vOther
-// into v_lshl_or_b32 vRes, vSrc, vAmt, vOther (GFX9+).
-// Requires the shift result to be dead after the or and the combined operand
-// list to satisfy the V_LSHL_OR_B32 constant-bus / literal-encoding rules.
-// Complements the SDAG ThreeOpFrag cshl_32+or pattern, which is blocked by
-// HasOneUseBinOp when the shift's DAG node has other consumers.
-MachineInstr *SIShrinkInstructions::matchLshlOr(MachineInstr &Shift) const {
- if (TII->pseudoToMCOpcode(AMDGPU::V_LSHL_OR_B32_e64) == -1)
- return nullptr;
-
- assert(Shift.getOpcode() == AMDGPU::V_LSHLREV_B32_e32 ||
- Shift.getOpcode() == AMDGPU::V_LSHLREV_B32_e64);
-
- // V_LSHLREV / V_OR layout: 0 = vdst, 1 = src0, 2 = src1.
- MachineOperand *ShDst = &Shift.getOperand(0);
- MachineOperand *ShAmt = &Shift.getOperand(1);
- MachineOperand *ShVal = &Shift.getOperand(2);
- if (!ShDst->isReg())
- return nullptr;
-
- Register ShDstReg = ShDst->getReg();
- unsigned ShDstSub = ShDst->getSubReg();
-
- if (!TRI->isVGPR(*MRI, ShDstReg))
- return nullptr;
-
- // Search up to 16 instructions forward for the OR. Limit prevents
- // unbounded scans while covering the vast majority of fusion opportunities.
- // Matches the search window used in matchSwap.
- const unsigned SearchLimit = 16;
- unsigned Count = 0;
-
- for (auto Iter = std::next(Shift.getIterator()),
- E = Shift.getParent()->instr_end();
- Iter != E && Count < SearchLimit; ++Iter) {
- if (Iter->isDebugInstr())
- continue;
- ++Count;
-
- bool IsOr = (Iter->getOpcode() == AMDGPU::V_OR_B32_e32 ||
- Iter->getOpcode() == AMDGPU::V_OR_B32_e64);
-
- if (!IsOr) {
- // Reject intervening hazards.
- if (instReadsReg(&*Iter, ShDstReg, ShDstSub) ||
- instModifiesReg(&*Iter, ShDstReg, ShDstSub))
- return nullptr;
- if (ShVal->isReg() && Iter->modifiesRegister(ShVal->getReg(), TRI))
- return nullptr;
- if (ShAmt->isReg() && Iter->modifiesRegister(ShAmt->getReg(), TRI))
- return nullptr;
- continue;
- }
- if (Iter->getNumExplicitOperands() < 3)
- return nullptr;
- MachineOperand *OrDst = &Iter->getOperand(0);
- MachineOperand *OrSrc0 = &Iter->getOperand(1);
- MachineOperand *OrSrc1 = &Iter->getOperand(2);
- if (!OrDst->isReg())
- return nullptr;
-
- if (!TRI->isVGPR(*MRI, OrDst->getReg()))
- return nullptr;
-
- // Find which OR source uses the shift result (commutative).
- MachineOperand *KillUse;
- MachineOperand *Other;
- if (OrSrc0->isReg() && OrSrc0->getReg() == ShDstReg &&
- OrSrc0->getSubReg() == ShDstSub) {
- KillUse = OrSrc0;
- Other = OrSrc1;
- } else if (OrSrc1->isReg() && OrSrc1->getReg() == ShDstReg &&
- OrSrc1->getSubReg() == ShDstSub) {
- KillUse = OrSrc1;
- Other = OrSrc0;
- } else {
- return nullptr;
- }
-
- // The other operand can't be the shift result itself (e.g. "or x, x"):
- // fusion deletes the shift, leaving it undefined.
- if (Other->isReg() && TRI->regsOverlap(Other->getReg(), ShDstReg))
- return nullptr;
-
- // Fusion deletes the shift, so its result must be dead after the OR. Trust
- // a kill flag; otherwise query liveness just past the OR (catches later
- // reads, read-modify uses, and live-out).
- if (!KillUse->isKill()) {
- if (ShDstSub != 0)
- return nullptr;
- MachineBasicBlock::iterator AfterOr =
- std::next(MachineBasicBlock::iterator(*Iter));
- MachineBasicBlock::LivenessQueryResult LQR =
- Iter->getParent()->computeRegisterLiveness(TRI, ShDstReg, AfterOr,
- /*Neighborhood=*/16);
- if (LQR != MachineBasicBlock::LQR_Dead)
- return nullptr;
- }
-
- LLVM_DEBUG(dbgs() << "Matched v_lshl_or:\n" << Shift << *Iter);
-
- // Build the fused instruction and validate all operands are legal
- // (constant-bus limits, VOP3 literal constraints, register classes). Bail
- // if illegal.
- MachineBasicBlock &MBB = *Iter->getParent();
- MachineInstrBuilder MIB =
- BuildMI(MBB, Iter->getIterator(), Iter->getDebugLoc(),
- TII->get(AMDGPU::V_LSHL_OR_B32_e64))
- .addReg(OrDst->getReg(), RegState::Define, OrDst->getSubReg());
- MIB.add(*ShVal);
- MIB.add(*ShAmt);
- MIB.add(*Other);
- MachineInstr *NewMI = MIB.getInstr();
-
- const int SrcIdx[] = {AMDGPU::getNamedOperandIdx(AMDGPU::V_LSHL_OR_B32_e64,
- AMDGPU::OpName::src0),
- AMDGPU::getNamedOperandIdx(AMDGPU::V_LSHL_OR_B32_e64,
- AMDGPU::OpName::src1),
- AMDGPU::getNamedOperandIdx(AMDGPU::V_LSHL_OR_B32_e64,
- AMDGPU::OpName::src2)};
- for (int Idx : SrcIdx) {
- if (Idx < 0 || !TII->isOperandLegal(*NewMI, Idx)) {
- NewMI->eraseFromParent();
- return nullptr;
- }
- }
-
- auto ResumeIt = std::next(Shift.getIterator());
- // Resume from the newly created instruction if Shift and OR were adjacent;
- // otherwise continue from the instruction after the Shift.
- MachineInstr *Next =
- (ResumeIt != MBB.end() && &*ResumeIt == &*Iter) ? NewMI : &*ResumeIt;
-
- Iter->eraseFromParent();
- Shift.eraseFromParent();
- return Next;
- }
-
- return nullptr;
-}
-
// If an instruction has dead sdst replace it with NULL register on gfx1030+
bool SIShrinkInstructions::tryReplaceDeadSDST(MachineInstr &MI) const {
if (!ST->hasGFX10_3Insts())
@@ -1058,18 +916,6 @@ bool SIShrinkInstructions::run(MachineFunction &MF) {
}
}
- // Fuse v_lshlrev_b32 + v_or_b32 into v_lshl_or_b32. Post-RA only:
- // earlier passes / SDAG patterns get first crack pre-RA, and post-RA
- // we have accurate kill flags and final register classes.
- if (IsPostRA && (MI.getOpcode() == AMDGPU::V_LSHLREV_B32_e32 ||
- MI.getOpcode() == AMDGPU::V_LSHLREV_B32_e64)) {
- if (auto *NextMI = matchLshlOr(MI)) {
- Next = NextMI->getIterator();
- Changed = true;
- continue;
- }
- }
-
// Shrink scalar logic operations.
if (MI.getOpcode() == AMDGPU::S_AND_B32 ||
MI.getOpcode() == AMDGPU::S_OR_B32 ||
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
index d9f3be3966832..b65f71ab20b1a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll
@@ -673,7 +673,8 @@ define <2 x i16> @add_inline_imm_neg1_0(<2 x i16> %x) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-NEXT: v_add_u16_e32 v0, -1, v0
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: add_inline_imm_neg1_0:
@@ -707,7 +708,8 @@ define <2 x i16> @add_inline_imm_1_0(<2 x i16> %x) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-NEXT: v_add_u16_e32 v0, 1, v0
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: add_inline_imm_1_0:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
index 34ab5a3a1502f..a28b217607eec 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_flat.ll
@@ -209,8 +209,9 @@ define i32 @atomic_load_flat_monotonic_i16_d16_lo_or(ptr %ptr, i16 %high) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_flat_monotonic_i16_d16_lo_or:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
index c2d857a2c8656..2be9e29530ace 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_global.ll
@@ -551,8 +551,9 @@ define i32 @atomic_load_global_monotonic_i16_d16_lo_or(ptr addrspace(1) %ptr, i1
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-NEXT: s_waitcnt vmcnt(0)
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_global_monotonic_i16_d16_lo_or:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
index 0b4284c8d4896..08be9df3e5c5c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_load_local_2.ll
@@ -424,8 +424,9 @@ define i32 @atomic_load_local_monotonic_i16_d16_lo_or(ptr addrspace(3) %ptr, i16
; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: ds_read_u16 v0, v0
; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: atomic_load_local_monotonic_i16_d16_lo_or:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
index 9433e3fda3c4d..de586a5921724 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
@@ -795,13 +795,15 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
; VI-NEXT: v_cvt_f32_ubyte0_sdwa v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
; VI-NEXT: v_add_u16_e32 v8, 9, v8
-; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: v_and_b32_e32 v10, 0xff, v10
+; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; VI-NEXT: v_and_b32_e32 v6, 0xff, v6
; VI-NEXT: v_lshlrev_b32_sdwa v0, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v10
; VI-NEXT: v_or_b32_sdwa v0, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; VI-NEXT: v_and_b32_e32 v6, 0xff, v6
-; VI-NEXT: v_lshl_or_b32 v0, v10, 16, v0
-; VI-NEXT: v_lshl_or_b32 v2, v6, 24, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 24, v6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v2, v0, v2
; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
index 509641b0b15e3..805053c7d19fc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
@@ -855,7 +855,8 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v4, v6, v3
-; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_fdiv_v2f16:
@@ -887,7 +888,8 @@ define <2 x half> @v_fdiv_v2f16(<2 x half> %a, <2 x half> %b) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v6, v3
-; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_fdiv_v2f16:
@@ -1238,7 +1240,8 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v2, v1, v0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v4, v6, v3
-; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_fdiv_v2f16_ulp25:
@@ -1270,7 +1273,8 @@ define <2 x half> @v_fdiv_v2f16_ulp25(<2 x half> %a, <2 x half> %b) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v4, v4
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v2, v1, v0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v4, v6, v3
-; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_fdiv_v2f16_ulp25:
@@ -1544,7 +1548,8 @@ define <2 x half> @v_rcp_v2f16(<2 x half> %x) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_rcp_v2f16:
@@ -1571,7 +1576,8 @@ define <2 x half> @v_rcp_v2f16(<2 x half> %x) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_rcp_v2f16:
@@ -1829,7 +1835,8 @@ define <2 x half> @v_neg_rcp_v2f16(<2 x half> %x) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, -1.0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, -1.0
-; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_neg_rcp_v2f16:
@@ -1856,7 +1863,8 @@ define <2 x half> @v_neg_rcp_v2f16(<2 x half> %x) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, -1.0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, -1.0
-; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_neg_rcp_v2f16:
@@ -2117,7 +2125,8 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_rcp_v2f16_fabs:
@@ -2145,7 +2154,8 @@ define <2 x half> @v_rcp_v2f16_fabs(<2 x half> %x) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_rcp_v2f16_fabs:
@@ -2415,7 +2425,8 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, -1.0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, -1.0
-; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_neg_rcp_v2f16_fabs:
@@ -2443,7 +2454,8 @@ define <2 x half> @v_neg_rcp_v2f16_fabs(<2 x half> %x) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, -1.0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, -1.0
-; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_neg_rcp_v2f16_fabs:
@@ -2873,7 +2885,8 @@ define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_rcp_v2f16_ulp25:
@@ -2900,7 +2913,8 @@ define <2 x half> @v_rcp_v2f16_ulp25(<2 x half> %x) {
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v1, v0, 1.0
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v3, v2, 1.0
-; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_rcp_v2f16_ulp25:
@@ -5409,27 +5423,28 @@ define <2 x half> @v_rsq_v2f16(<2 x half> %a) {
; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v3
; GFX8-IEEE-NEXT: v_mul_f32_e64 v6, -v2, v4
; GFX8-IEEE-NEXT: v_mul_f32_e64 v7, -v3, v5
-; GFX8-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX8-IEEE-NEXT: v_add_f32_e32 v7, 1.0, v7
-; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4
+; GFX8-IEEE-NEXT: v_add_f32_e32 v6, 1.0, v6
; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5
-; GFX8-IEEE-NEXT: v_add_f32_e32 v6, v6, v4
+; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4
; GFX8-IEEE-NEXT: v_add_f32_e32 v7, v7, v5
-; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6
+; GFX8-IEEE-NEXT: v_add_f32_e32 v6, v6, v4
; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7
-; GFX8-IEEE-NEXT: v_add_f32_e32 v2, 1.0, v2
+; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6
; GFX8-IEEE-NEXT: v_add_f32_e32 v3, 1.0, v3
-; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4
+; GFX8-IEEE-NEXT: v_add_f32_e32 v2, 1.0, v2
; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5
-; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2
; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v7
-; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v6
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0
+; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0
-; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0
+; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_rsq_v2f16:
@@ -5443,21 +5458,22 @@ define <2 x half> @v_rsq_v2f16(<2 x half> %a) {
; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v3
; GFX8-FLUSH-NEXT: v_mad_f32 v6, -v2, v4, 1.0
; GFX8-FLUSH-NEXT: v_mad_f32 v7, -v3, v5, 1.0
-; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v4
; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, v5
-; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, 1.0
+; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, v4
; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, 1.0
-; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
+; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, 1.0
; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5
-; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2
; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v7
-; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v6
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0
+; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, 1.0
-; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, 1.0
+; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_rsq_v2f16:
@@ -5706,27 +5722,28 @@ define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {
; GFX8-IEEE-NEXT: v_rcp_f32_e32 v5, v3
; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4
; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v3, v5
-; GFX8-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v6
; GFX8-IEEE-NEXT: v_add_f32_e32 v7, -1.0, v7
-; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4
+; GFX8-IEEE-NEXT: v_add_f32_e32 v6, -1.0, v6
; GFX8-IEEE-NEXT: v_mul_f32_e32 v7, v7, v5
-; GFX8-IEEE-NEXT: v_sub_f32_e32 v6, v6, v4
+; GFX8-IEEE-NEXT: v_mul_f32_e32 v6, v6, v4
; GFX8-IEEE-NEXT: v_sub_f32_e32 v7, v7, v5
-; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6
+; GFX8-IEEE-NEXT: v_sub_f32_e32 v6, v6, v4
; GFX8-IEEE-NEXT: v_mul_f32_e64 v3, -v3, v7
-; GFX8-IEEE-NEXT: v_add_f32_e32 v2, -1.0, v2
+; GFX8-IEEE-NEXT: v_mul_f32_e64 v2, -v2, v6
; GFX8-IEEE-NEXT: v_add_f32_e32 v3, -1.0, v3
-; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4
+; GFX8-IEEE-NEXT: v_add_f32_e32 v2, -1.0, v2
; GFX8-IEEE-NEXT: v_mul_f32_e32 v3, v3, v5
-; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX8-IEEE-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX8-IEEE-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX8-IEEE-NEXT: v_and_b32_e32 v2, 0xff800000, v2
; GFX8-IEEE-NEXT: v_add_f32_e32 v3, v3, v7
-; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX8-IEEE-NEXT: v_add_f32_e32 v2, v2, v6
; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, -1.0
+; GFX8-IEEE-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX8-IEEE-NEXT: v_div_fixup_f16 v0, v3, v0, -1.0
-; GFX8-IEEE-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX8-IEEE-NEXT: v_div_fixup_f16 v1, v2, v1, -1.0
+; GFX8-IEEE-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-IEEE-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-IEEE-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-FLUSH-LABEL: v_neg_rsq_v2f16:
@@ -5740,21 +5757,22 @@ define <2 x half> @v_neg_rsq_v2f16(<2 x half> %a) {
; GFX8-FLUSH-NEXT: v_rcp_f32_e32 v5, v3
; GFX8-FLUSH-NEXT: v_mad_f32 v6, v2, v4, -1.0
; GFX8-FLUSH-NEXT: v_mad_f32 v7, v3, v5, -1.0
-; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v4
; GFX8-FLUSH-NEXT: v_mad_f32 v7, v7, v5, -v5
-; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, -1.0
+; GFX8-FLUSH-NEXT: v_mad_f32 v6, v6, v4, -v4
; GFX8-FLUSH-NEXT: v_mad_f32 v3, -v3, v7, -1.0
-; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
+; GFX8-FLUSH-NEXT: v_mad_f32 v2, -v2, v6, -1.0
; GFX8-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v5
-; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2
+; GFX8-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
; GFX8-FLUSH-NEXT: v_and_b32_e32 v3, 0xff800000, v3
-; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v6
+; GFX8-FLUSH-NEXT: v_and_b32_e32 v2, 0xff800000, v2
; GFX8-FLUSH-NEXT: v_add_f32_e32 v3, v3, v7
-; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2
+; GFX8-FLUSH-NEXT: v_add_f32_e32 v2, v2, v6
; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v3, v3
-; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, -1.0
+; GFX8-FLUSH-NEXT: v_cvt_f16_f32_e32 v2, v2
; GFX8-FLUSH-NEXT: v_div_fixup_f16 v0, v3, v0, -1.0
-; GFX8-FLUSH-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX8-FLUSH-NEXT: v_div_fixup_f16 v1, v2, v1, -1.0
+; GFX8-FLUSH-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-FLUSH-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-IEEE-LABEL: v_neg_rsq_v2f16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
index a417f5f6c44c0..24f3e0c85c519 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
@@ -388,7 +388,8 @@ define <2 x half> @v_fma_v2f16(<2 x half> %x, <2 x half> %y, <2 x half> %z) {
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v3, v4, v5
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v2f16:
@@ -459,7 +460,8 @@ define <2 x half> @v_fma_v2f16_fneg_lhs(<2 x half> %x, <2 x half> %y, <2 x half>
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v3, v4, v5
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v2f16_fneg_lhs:
@@ -531,7 +533,8 @@ define <2 x half> @v_fma_v2f16_fneg_rhs(<2 x half> %x, <2 x half> %y, <2 x half>
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v3, v4, v5
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v2f16_fneg_rhs:
@@ -601,7 +604,8 @@ define <2 x half> @v_fma_v2f16_fneg_lhs_rhs(<2 x half> %x, <2 x half> %y, <2 x h
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v3, v4, v5
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v2f16_fneg_lhs_rhs:
@@ -677,8 +681,9 @@ define <3 x half> @v_fma_v3f16(<3 x half> %x, <3 x half> %y, <3 x half> %z) {
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v4
; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
; GFX8-NEXT: v_fma_f16 v2, v6, v7, v8
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
-; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v3f16:
@@ -763,17 +768,19 @@ define <4 x half> @v_fma_v4f16(<4 x half> %x, <4 x half> %y, <4 x half> %z) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0
-; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v5
; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
; GFX8-NEXT: v_fma_f16 v2, v6, v8, v10
; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
; GFX8-NEXT: v_fma_f16 v3, v7, v9, v11
-; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX8-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fma_v4f16:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
index 6f43ae7438a39..6b1b797e3cfec 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
@@ -1410,32 +1410,34 @@ define i32 @v_fshl_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX8-NEXT: v_and_b32_e32 v5, 7, v5
; GFX8-NEXT: v_lshlrev_b16_e32 v3, v9, v3
; GFX8-NEXT: v_lshrrev_b16_e32 v4, v5, v4
+; GFX8-NEXT: v_mov_b32_e32 v7, 0xff
; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
; GFX8-NEXT: v_mov_b32_e32 v4, 7
; GFX8-NEXT: v_mov_b32_e32 v8, -1
-; GFX8-NEXT: v_mov_b32_e32 v7, 0xff
; GFX8-NEXT: v_and_b32_sdwa v5, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_sdwa v7, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_xor_b32_sdwa v9, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX8-NEXT: v_xor_b32_sdwa v2, v2, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_sdwa v7, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v7
+; GFX8-NEXT: v_and_b32_e32 v9, 7, v9
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 25, v1
; GFX8-NEXT: v_and_b32_e32 v2, 7, v2
; GFX8-NEXT: v_lshlrev_b16_sdwa v5, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, 1, v7
-; GFX8-NEXT: v_and_b32_e32 v9, 7, v9
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, v9, v7
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v1
-; GFX8-NEXT: v_lshrrev_b16_e32 v7, v9, v7
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 8
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v7
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX8-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX8-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX8-NEXT: v_lshl_or_b32 v0, v0, 24, v1
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshl_v4i8:
@@ -5817,7 +5819,8 @@ define i64 @v_fshl_i64_48(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v0
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 16, v[2:3]
-; GFX8-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v4
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshl_i64_48:
@@ -6530,14 +6533,15 @@ define i128 @v_fshl_i128(i128 %lhs, i128 %rhs, i128 %amt) {
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v16
-; GFX8-NEXT: v_mov_b32_e32 v15, 0x7f
; GFX8-NEXT: v_cndmask_b32_e32 v10, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v13, v1, v3, vcc
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[4:5]
+; GFX8-NEXT: v_mov_b32_e32 v15, 0x7f
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 31, v6
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[6:7]
; GFX8-NEXT: v_bfi_b32 v14, v8, 0, v15
; GFX8-NEXT: v_not_b32_e32 v17, 63
-; GFX8-NEXT: v_lshl_or_b32 v1, v6, 31, v1
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, 64, v14
; GFX8-NEXT: v_add_u32_e32 v15, vcc, v14, v17
; GFX8-NEXT: v_lshrrev_b64 v[4:5], v14, v[0:1]
@@ -7047,13 +7051,14 @@ define amdgpu_ps <4 x float> @v_fshl_i128_svs(i128 inreg %lhs, i128 %rhs, i128 i
; GFX8-NEXT: s_cselect_b64 s[6:7], s[6:7], 0
; GFX8-NEXT: s_cselect_b64 s[0:1], s[8:9], s[0:1]
; GFX8-NEXT: s_cmp_lg_u32 s5, 0
-; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
; GFX8-NEXT: s_cselect_b64 s[0:1], s[2:3], s[0:1]
+; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[0:1]
; GFX8-NEXT: s_andn2_b32 s2, 0x7f, s4
-; GFX8-NEXT: v_lshl_or_b32 v1, v2, 31, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 31, v2
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[2:3]
; GFX8-NEXT: s_sub_i32 s3, s2, 64
; GFX8-NEXT: s_sub_i32 s4, 64, s2
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
; GFX8-NEXT: s_cmp_lt_u32 s2, 64
; GFX8-NEXT: s_cselect_b32 s5, 1, 0
; GFX8-NEXT: s_cmp_eq_u32 s2, 0
@@ -8241,7 +8246,8 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX8-NEXT: v_cndmask_b32_e64 v23, v1, v3, s[4:5]
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 1, v[8:9]
; GFX8-NEXT: v_mov_b32_e32 v17, 0x7f
-; GFX8-NEXT: v_lshl_or_b32 v1, v10, 31, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 31, v10
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: v_lshrrev_b64 v[2:3], 1, v[10:11]
; GFX8-NEXT: v_bfi_b32 v10, v16, 0, v17
; GFX8-NEXT: v_cndmask_b32_e32 v24, 0, v21, vcc
@@ -8281,8 +8287,9 @@ define <2 x i128> @v_fshl_v2i128(<2 x i128> %lhs, <2 x i128> %rhs, <2 x i128> %a
; GFX8-NEXT: v_cndmask_b32_e64 v6, v8, v6, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v7, v9, v7, s[4:5]
; GFX8-NEXT: v_lshrrev_b64 v[8:9], 1, v[12:13]
+; GFX8-NEXT: v_lshlrev_b32_e32 v10, 31, v14
+; GFX8-NEXT: v_or_b32_e32 v9, v9, v10
; GFX8-NEXT: v_lshrrev_b64 v[10:11], 1, v[14:15]
-; GFX8-NEXT: v_lshl_or_b32 v9, v14, 31, v9
; GFX8-NEXT: v_bfi_b32 v14, v20, 0, v17
; GFX8-NEXT: v_add_u32_e32 v18, vcc, v14, v18
; GFX8-NEXT: v_sub_u32_e32 v16, vcc, 64, v14
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 28ea57c30a777..cf58ba6658321 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -1422,27 +1422,29 @@ define i32 @v_fshr_v4i8(i32 %lhs.arg, i32 %rhs.arg, i32 %amt.arg) {
; GFX8-NEXT: v_xor_b32_sdwa v9, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_sdwa v5, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_and_b32_e32 v9, 7, v9
+; GFX8-NEXT: v_mov_b32_e32 v8, 0xff
; GFX8-NEXT: v_lshlrev_b16_e32 v5, v9, v5
; GFX8-NEXT: v_mov_b32_e32 v9, 7
; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
; GFX8-NEXT: v_xor_b32_sdwa v4, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX8-NEXT: v_mov_b32_e32 v8, 0xff
; GFX8-NEXT: v_and_b32_sdwa v10, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_sdwa v8, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v4, 7, v4
; GFX8-NEXT: v_and_b32_sdwa v2, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
-; GFX8-NEXT: v_and_b32_sdwa v8, v1, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, v10, v8
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v4, v0
; GFX8-NEXT: v_lshrrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_3
-; GFX8-NEXT: v_lshrrev_b16_e32 v8, v10, v8
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v8
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_mov_b32_e32 v1, 8
-; GFX8-NEXT: v_or_b32_e32 v5, v5, v8
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v5
-; GFX8-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX8-NEXT: v_or_b32_sdwa v1, v6, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX8-NEXT: v_lshl_or_b32 v0, v0, 24, v1
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 24, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_v4i8:
@@ -1886,10 +1888,10 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v3
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_not_b32_e32 v4, 23
-; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3
; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffffff, v1
; GFX8-NEXT: v_readfirstlane_b32 s4, v3
; GFX8-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX8-NEXT: v_mul_hi_u32 v3, v3, s5
@@ -1907,8 +1909,9 @@ define i24 @v_fshr_i24(i24 %lhs, i24 %rhs, i24 %amt) {
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, 23, v2
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, v3, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v1, v2, v1
-; GFX8-NEXT: v_lshl_or_b32 v0, v0, v3, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_i24:
@@ -2824,11 +2827,11 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cvt_u32_f32_e32 v6, v6
; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
-; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1
; GFX8-NEXT: v_readfirstlane_b32 s4, v6
; GFX8-NEXT: s_mul_i32 s5, s4, 0xffffffe8
; GFX8-NEXT: v_mul_hi_u32 v6, v6, s5
-; GFX8-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffffff, v3
; GFX8-NEXT: v_readfirstlane_b32 s5, v6
; GFX8-NEXT: s_add_i32 s4, s4, s5
; GFX8-NEXT: v_mul_hi_u32 v6, v4, s4
@@ -2856,10 +2859,11 @@ define <2 x i24> @v_fshr_v2i24(<2 x i24> %lhs, <2 x i24> %rhs, <2 x i24> %amt) {
; GFX8-NEXT: v_cmp_le_u32_e32 vcc, 24, v2
; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 23, v2
-; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
; GFX8-NEXT: v_and_b32_e32 v4, 0xffffff, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, v4, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v2, v3
-; GFX8-NEXT: v_lshl_or_b32 v1, v1, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_v2i24:
@@ -5463,7 +5467,8 @@ define i64 @v_fshr_i64_5(i64 %lhs, i64 %rhs) {
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v0
; GFX8-NEXT: v_lshrrev_b64 v[0:1], 5, v[2:3]
-; GFX8-NEXT: v_lshl_or_b32 v1, v4, 27, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 27, v4
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_fshr_i64_5:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
index fc7b6777bce8c..4d0662098c261 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll
@@ -688,20 +688,22 @@ define i32 @v_saddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX8-NEXT: v_lshlrev_b16_e32 v5, 8, v8
; GFX8-NEXT: v_max_i16_e32 v6, 0, v4
; GFX8-NEXT: v_sub_u16_e32 v7, 0x8000, v7
+; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
; GFX8-NEXT: v_sub_u16_e32 v6, 0x7fff, v6
; GFX8-NEXT: v_max_i16_e32 v5, v7, v5
-; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
-; GFX8-NEXT: v_min_i16_e32 v5, v5, v6
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX8-NEXT: v_ashrrev_i16_e32 v3, 8, v3
-; GFX8-NEXT: v_add_u16_e32 v4, v4, v5
+; GFX8-NEXT: v_min_i16_e32 v5, v5, v6
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_ashrrev_i16_e32 v4, 8, v4
+; GFX8-NEXT: v_add_u16_e32 v4, v4, v5
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_ashrrev_i16_e32 v4, 8, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_saddsat_v4i8:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
index 03107a08fe5ba..ab7e11a78ed57 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sext_inreg.ll
@@ -1345,8 +1345,9 @@ define i65 @v_sext_inreg_i65_22(i65 %value) {
; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
; GFX8-NEXT: v_bfe_u32 v1, v1, 0, 10
-; GFX8-NEXT: v_lshl_or_b32 v1, v2, 10, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, 10, v2
; GFX8-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3]
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_sext_inreg_i65_22:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
index 10376d2599d95..5409743ce85ee 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll
@@ -688,20 +688,22 @@ define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX8-NEXT: v_lshlrev_b16_e32 v5, 8, v8
; GFX8-NEXT: v_add_u16_e32 v6, 0x8001, v6
; GFX8-NEXT: v_min_i16_e32 v7, -1, v4
+; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
; GFX8-NEXT: v_add_u16_e32 v7, 0x8000, v7
; GFX8-NEXT: v_max_i16_e32 v5, v6, v5
-; GFX8-NEXT: v_ashrrev_i16_e32 v1, 8, v1
-; GFX8-NEXT: v_min_i16_e32 v5, v5, v7
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX8-NEXT: v_ashrrev_i16_e32 v3, 8, v3
-; GFX8-NEXT: v_sub_u16_e32 v4, v4, v5
+; GFX8-NEXT: v_min_i16_e32 v5, v5, v7
; GFX8-NEXT: v_lshlrev_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-NEXT: v_ashrrev_i16_e32 v4, 8, v4
+; GFX8-NEXT: v_sub_u16_e32 v4, v4, v5
; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_ashrrev_i16_e32 v4, 8, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v4
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v4i8:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
index 64bfb9b6db44e..92d87a0d74efb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
@@ -199,7 +199,8 @@ define void @v_constained_fma_v2f16_fpexcept_strict_div(<2 x half> %x, <2 x half
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v5, v6, v7
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: flat_store_dword v[3:4], v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -424,17 +425,19 @@ define void @v_constained_fma_v4f16_fpexcept_strict_div(<4 x half> %x, <4 x half
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
-; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1
+; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v13, 16, v5
; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
; GFX8-NEXT: v_fma_f16 v2, v8, v10, v12
; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
; GFX8-NEXT: v_fma_f16 v3, v9, v11, v13
-; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX8-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v3
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -913,7 +916,8 @@ define void @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg_div(<2 x half> %x,
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
; GFX8-NEXT: v_fma_f16 v1, v5, v6, v7
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: flat_store_dword v[3:4], v0
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
index 336efe6ee2de5..567656635b726 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll
@@ -591,9 +591,10 @@ define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7
; GFX8-NEXT: v_add_u16_e64 v3, v3, v4 clamp
; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
-; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 8, v0
+; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_sdwa v1, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
index 8c8370927d294..e17706ba6dd67 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll
@@ -579,9 +579,10 @@ define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7
; GFX8-NEXT: v_sub_u16_e64 v3, v3, v4 clamp
; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
-; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 8, v0
+; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_sdwa v1, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
diff --git a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
index 9c5907d9ec72a..ca96693fc44e9 100644
--- a/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
+++ b/llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
@@ -50,9 +50,10 @@ define amdgpu_kernel void @parent_kernel_missing_inputs() #0 {
; FIXEDABI-SDAG-NEXT: s_add_i32 s4, s4, s9
; FIXEDABI-SDAG-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
; FIXEDABI-SDAG-NEXT: s_add_u32 s0, s0, s9
+; FIXEDABI-SDAG-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; FIXEDABI-SDAG-NEXT: s_addc_u32 s1, s1, 0
; FIXEDABI-SDAG-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; FIXEDABI-SDAG-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; FIXEDABI-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; FIXEDABI-SDAG-NEXT: s_mov_b32 flat_scratch_lo, s5
; FIXEDABI-SDAG-NEXT: s_mov_b32 s14, s8
; FIXEDABI-SDAG-NEXT: s_getpc_b64 s[4:5]
@@ -71,11 +72,13 @@ define amdgpu_kernel void @parent_kernel_missing_inputs() #0 {
; FIXEDABI-GISEL-NEXT: s_add_i32 s4, s4, s9
; FIXEDABI-GISEL-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
; FIXEDABI-GISEL-NEXT: s_add_u32 s0, s0, s9
+; FIXEDABI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; FIXEDABI-GISEL-NEXT: s_addc_u32 s1, s1, 0
-; FIXEDABI-GISEL-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; FIXEDABI-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; FIXEDABI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 20, v2
; FIXEDABI-GISEL-NEXT: s_mov_b32 flat_scratch_lo, s5
; FIXEDABI-GISEL-NEXT: s_mov_b32 s14, s8
-; FIXEDABI-GISEL-NEXT: v_lshl_or_b32 v31, v2, 20, v0
+; FIXEDABI-GISEL-NEXT: v_or_b32_e32 v31, v0, v1
; FIXEDABI-GISEL-NEXT: s_getpc_b64 s[4:5]
; FIXEDABI-GISEL-NEXT: s_add_u32 s4, s4, requires_all_inputs at rel32@lo+4
; FIXEDABI-GISEL-NEXT: s_addc_u32 s5, s5, requires_all_inputs at rel32@hi+12
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index dd574a62201f1..8fb907a94fb4a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -5742,41 +5742,49 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v55, v57, v41, s4
; VI-NEXT: v_perm_b32 v1, v1, v48, s4
-; VI-NEXT: v_lshl_or_b32 v1, v55, 16, v1
-; VI-NEXT: v_perm_b32 v2, v2, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v55
+; VI-NEXT: v_or_b32_e32 v1, v1, v48
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v34, v56, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_perm_b32 v2, v2, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v47, v40, s4
; VI-NEXT: v_perm_b32 v2, v3, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v52, s4
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v52, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v33, v39, s4
; VI-NEXT: v_perm_b32 v2, v5, v37, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v51, s4
; VI-NEXT: v_perm_b32 v2, v44, v43, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v51, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v50, v54, s4
; VI-NEXT: v_perm_b32 v2, v7, v63, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v36, s4
; VI-NEXT: v_perm_b32 v2, v62, v61, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -5784,12 +5792,14 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v49, s4
; VI-NEXT: v_perm_b32 v1, v60, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v35, s4
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
@@ -5798,19 +5808,21 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v11, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v12, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v12, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -5819,19 +5831,21 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v14, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
@@ -5840,19 +5854,21 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v16, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -5861,19 +5877,21 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v18, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -5882,19 +5900,21 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v20, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
@@ -5904,17 +5924,19 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v22, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -5924,17 +5946,19 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v23, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v24, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v24, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
@@ -5944,70 +5968,74 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v26, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v26, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v27, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v27, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v28, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v28, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v29, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v29, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v30, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v30, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v31, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
@@ -6017,7 +6045,8 @@ define <128 x i8> @bitcast_v32i32_to_v128i8(<32 x i32> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v32, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v42, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -9440,121 +9469,136 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24
; VI-NEXT: .LBB13_3: ; %end
; VI-NEXT: v_mov_b32_e32 v9, s48
-; VI-NEXT: v_mov_b32_e32 v2, s82
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; VI-NEXT: v_mov_b32_e32 v4, s67
-; VI-NEXT: v_perm_b32 v3, s16, v2, v1
+; VI-NEXT: v_mov_b32_e32 v2, s82
; VI-NEXT: v_perm_b32 v9, s53, v9, v1
+; VI-NEXT: v_perm_b32 v3, s16, v2, v1
; VI-NEXT: v_mov_b32_e32 v24, s83
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_mov_b32_e32 v4, s67
+; VI-NEXT: v_perm_b32 v24, s85, v24, v1
+; VI-NEXT: v_or_b32_e32 v3, v3, v9
; VI-NEXT: v_perm_b32 v2, s17, v4, v1
; VI-NEXT: v_mov_b32_e32 v13, s38
+; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v24
; VI-NEXT: v_mov_b32_e32 v4, s47
-; VI-NEXT: v_perm_b32 v24, s85, v24, v1
-; VI-NEXT: v_lshl_or_b32 v3, v9, 16, v3
-; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_perm_b32 v5, s18, v4, v1
; VI-NEXT: v_perm_b32 v13, s81, v13, v1
-; VI-NEXT: v_mov_b32_e32 v25, s80
-; VI-NEXT: v_mov_b32_e32 v26, s68
-; VI-NEXT: v_readlane_b32 s16, v33, 57
-; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v24, 16, v2
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
+; VI-NEXT: v_perm_b32 v5, s18, v4, v1
+; VI-NEXT: v_mov_b32_e32 v25, s80
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
+; VI-NEXT: v_mov_b32_e32 v6, s46
+; VI-NEXT: v_perm_b32 v25, s87, v25, v1
+; VI-NEXT: v_or_b32_e32 v2, v5, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: v_perm_b32 v4, s19, v6, v1
; VI-NEXT: v_mov_b32_e32 v17, s36
-; VI-NEXT: v_mov_b32_e32 v6, s69
-; VI-NEXT: v_mov_b32_e32 v19, s34
-; VI-NEXT: v_perm_b32 v25, s87, v25, v1
-; VI-NEXT: v_perm_b32 v26, s16, v26, v1
-; VI-NEXT: v_readlane_b32 s16, v33, 56
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v13, 16, v5
-; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
-; VI-NEXT: v_mov_b32_e32 v8, s65
-; VI-NEXT: v_perm_b32 v7, s20, v6, v1
-; VI-NEXT: v_mov_b32_e32 v20, s30
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v25
+; VI-NEXT: v_mov_b32_e32 v6, s69
; VI-NEXT: v_perm_b32 v17, s84, v17, v1
-; VI-NEXT: v_perm_b32 v19, s16, v19, v1
-; VI-NEXT: v_readlane_b32 s16, v33, 55
-; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v25, 16, v4
+; VI-NEXT: v_or_b32_e32 v2, v4, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
-; VI-NEXT: v_perm_b32 v6, s21, v8, v1
-; VI-NEXT: v_mov_b32_e32 v8, s55
-; VI-NEXT: v_perm_b32 v20, s16, v20, v1
-; VI-NEXT: v_readlane_b32 s16, v33, 53
+; VI-NEXT: v_perm_b32 v7, s20, v6, v1
+; VI-NEXT: v_mov_b32_e32 v26, s68
+; VI-NEXT: v_readlane_b32 s16, v33, 57
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v17, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; VI-NEXT: v_mov_b32_e32 v8, s65
+; VI-NEXT: v_perm_b32 v26, s16, v26, v1
+; VI-NEXT: v_or_b32_e32 v2, v7, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
-; VI-NEXT: v_mov_b32_e32 v11, s52
+; VI-NEXT: v_perm_b32 v6, s21, v8, v1
+; VI-NEXT: v_mov_b32_e32 v19, s34
+; VI-NEXT: v_readlane_b32 s16, v33, 56
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
+; VI-NEXT: v_mov_b32_e32 v8, s55
+; VI-NEXT: v_perm_b32 v19, s16, v19, v1
+; VI-NEXT: v_or_b32_e32 v2, v6, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
; VI-NEXT: v_perm_b32 v10, s22, v8, v1
; VI-NEXT: v_mov_b32_e32 v27, s71
-; VI-NEXT: v_mov_b32_e32 v28, s16
-; VI-NEXT: v_readlane_b32 s16, v33, 54
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v26, 16, v6
-; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
+; VI-NEXT: v_mov_b32_e32 v11, s52
+; VI-NEXT: v_perm_b32 v27, s70, v27, v1
+; VI-NEXT: v_or_b32_e32 v2, v10, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
; VI-NEXT: v_perm_b32 v8, s23, v11, v1
+; VI-NEXT: v_mov_b32_e32 v20, s30
+; VI-NEXT: v_readlane_b32 s16, v33, 55
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
; VI-NEXT: v_mov_b32_e32 v11, s54
-; VI-NEXT: v_mov_b32_e32 v21, s90
-; VI-NEXT: v_perm_b32 v27, s70, v27, v1
+; VI-NEXT: v_perm_b32 v20, s16, v20, v1
+; VI-NEXT: v_readlane_b32 s16, v33, 53
+; VI-NEXT: v_or_b32_e32 v2, v8, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
+; VI-NEXT: v_perm_b32 v12, s24, v11, v1
+; VI-NEXT: v_mov_b32_e32 v28, s16
+; VI-NEXT: v_readlane_b32 s16, v33, 54
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; VI-NEXT: v_mov_b32_e32 v14, s66
; VI-NEXT: v_perm_b32 v28, s16, v28, v1
+; VI-NEXT: v_or_b32_e32 v2, v12, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
+; VI-NEXT: v_perm_b32 v11, s25, v14, v1
+; VI-NEXT: v_mov_b32_e32 v21, s90
; VI-NEXT: v_readlane_b32 s16, v33, 52
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v19, 16, v10
-; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
-; VI-NEXT: v_mov_b32_e32 v14, s66
-; VI-NEXT: v_perm_b32 v12, s24, v11, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v28
+; VI-NEXT: v_mov_b32_e32 v14, s51
; VI-NEXT: v_perm_b32 v21, s16, v21, v1
; VI-NEXT: v_readlane_b32 s16, v33, 50
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v27, 16, v8
-; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
-; VI-NEXT: v_perm_b32 v11, s25, v14, v1
-; VI-NEXT: v_mov_b32_e32 v14, s51
+; VI-NEXT: v_or_b32_e32 v2, v11, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
+; VI-NEXT: v_perm_b32 v15, s26, v14, v1
; VI-NEXT: v_mov_b32_e32 v29, s16
; VI-NEXT: v_readlane_b32 s16, v33, 51
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v20, 16, v12
-; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
; VI-NEXT: v_mov_b32_e32 v16, s86
-; VI-NEXT: v_perm_b32 v15, s26, v14, v1
-; VI-NEXT: v_mov_b32_e32 v22, s88
; VI-NEXT: v_perm_b32 v29, s16, v29, v1
+; VI-NEXT: v_or_b32_e32 v2, v15, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
+; VI-NEXT: v_perm_b32 v14, s27, v16, v1
+; VI-NEXT: v_mov_b32_e32 v22, s88
; VI-NEXT: v_readlane_b32 s16, v33, 49
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v28, 16, v11
-; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
-; VI-NEXT: v_perm_b32 v14, s27, v16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
; VI-NEXT: v_mov_b32_e32 v16, s50
; VI-NEXT: v_perm_b32 v22, s16, v22, v1
; VI-NEXT: v_readlane_b32 s16, v33, 47
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v21, 16, v15
-; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
-; VI-NEXT: v_mov_b32_e32 v23, s64
+; VI-NEXT: v_or_b32_e32 v2, v14, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
; VI-NEXT: v_perm_b32 v18, s28, v16, v1
; VI-NEXT: v_mov_b32_e32 v30, s16
; VI-NEXT: v_readlane_b32 s16, v33, 48
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v29, 16, v14
-; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
-; VI-NEXT: v_perm_b32 v16, s29, v23, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
+; VI-NEXT: v_mov_b32_e32 v23, s64
; VI-NEXT: v_perm_b32 v30, s16, v30, v1
; VI-NEXT: v_readlane_b32 s16, v33, 46
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v22, 16, v18
+; VI-NEXT: v_or_b32_e32 v2, v18, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, 48, v0
+; VI-NEXT: v_perm_b32 v16, s29, v23, v1
; VI-NEXT: v_mov_b32_e32 v23, s78
; VI-NEXT: v_mov_b32_e32 v31, s16
; VI-NEXT: v_readlane_b32 s16, v33, 45
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v30, 16, v16
-; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
; VI-NEXT: v_perm_b32 v3, s16, v23, v1
+; VI-NEXT: v_or_b32_e32 v2, v16, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, s44, v31, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: v_readlane_b32 s16, v33, 44
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9562,18 +9606,20 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 42
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 43
-; VI-NEXT: v_perm_b32 v2, s45, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s45, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 60, v0
; VI-NEXT: v_readlane_b32 s16, v33, 41
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s76
; VI-NEXT: v_readlane_b32 s16, v33, 40
-; VI-NEXT: v_perm_b32 v2, s42, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s42, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 64, v0
; VI-NEXT: v_readlane_b32 s16, v33, 39
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9581,18 +9627,20 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 37
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 38
-; VI-NEXT: v_perm_b32 v2, s43, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s43, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x44, v0
; VI-NEXT: v_readlane_b32 s16, v33, 36
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_readlane_b32 s16, v33, 35
-; VI-NEXT: v_perm_b32 v2, s40, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s40, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x48, v0
; VI-NEXT: v_readlane_b32 s16, v33, 34
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9600,9 +9648,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 32
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 33
-; VI-NEXT: v_perm_b32 v2, s41, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s41, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x4c, v0
; VI-NEXT: v_readlane_b32 s16, v33, 31
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9611,7 +9660,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: v_readlane_b32 s14, v33, 30
; VI-NEXT: v_perm_b32 v3, s14, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x50, v0
; VI-NEXT: v_readlane_b32 s14, v33, 29
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9619,9 +9669,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s14, v33, 27
; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_readlane_b32 s14, v33, 28
-; VI-NEXT: v_perm_b32 v2, s15, v2, v1
; VI-NEXT: v_perm_b32 v3, s14, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s15, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x54, v0
; VI-NEXT: v_readlane_b32 s14, v33, 26
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9630,7 +9681,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s62
; VI-NEXT: v_readlane_b32 s12, v33, 25
; VI-NEXT: v_perm_b32 v3, s12, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x58, v0
; VI-NEXT: v_readlane_b32 s12, v33, 24
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9638,9 +9690,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s12, v33, 22
; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_readlane_b32 s12, v33, 23
-; VI-NEXT: v_perm_b32 v2, s13, v2, v1
; VI-NEXT: v_perm_b32 v3, s12, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s13, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x5c, v0
; VI-NEXT: v_readlane_b32 s12, v33, 21
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9649,7 +9702,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s60
; VI-NEXT: v_readlane_b32 s10, v33, 20
; VI-NEXT: v_perm_b32 v3, s10, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x60, v0
; VI-NEXT: v_readlane_b32 s10, v33, 19
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9657,9 +9711,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s10, v33, 17
; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_readlane_b32 s10, v33, 18
-; VI-NEXT: v_perm_b32 v2, s11, v2, v1
; VI-NEXT: v_perm_b32 v3, s10, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s11, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x64, v0
; VI-NEXT: v_readlane_b32 s10, v33, 16
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9668,7 +9723,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s58
; VI-NEXT: v_readlane_b32 s8, v33, 15
; VI-NEXT: v_perm_b32 v3, s8, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x68, v0
; VI-NEXT: v_readlane_b32 s8, v33, 14
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9676,9 +9732,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s8, v33, 12
; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_readlane_b32 s8, v33, 13
-; VI-NEXT: v_perm_b32 v2, s9, v2, v1
; VI-NEXT: v_perm_b32 v3, s8, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s9, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x6c, v0
; VI-NEXT: v_readlane_b32 s8, v33, 11
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9687,7 +9744,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_readlane_b32 s6, v33, 10
; VI-NEXT: v_perm_b32 v3, s6, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x70, v0
; VI-NEXT: v_readlane_b32 s6, v33, 9
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9695,9 +9753,10 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s6, v33, 7
; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_readlane_b32 s6, v33, 8
-; VI-NEXT: v_perm_b32 v2, s7, v2, v1
; VI-NEXT: v_perm_b32 v3, s6, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s7, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x74, v0
; VI-NEXT: v_readlane_b32 s6, v33, 6
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9707,7 +9766,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_readlane_b32 s4, v33, 5
; VI-NEXT: v_perm_b32 v3, s4, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x78, v0
; VI-NEXT: v_readlane_b32 s4, v33, 4
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -9717,7 +9777,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; VI-NEXT: v_readlane_b32 s4, v33, 3
; VI-NEXT: v_perm_b32 v2, s5, v2, v1
; VI-NEXT: v_perm_b32 v1, s4, v3, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_readlane_b32 s30, v32, 30
; VI-NEXT: v_readlane_b32 s7, v33, 1
@@ -10309,146 +10370,166 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24
; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24
; GFX9-NEXT: .LBB13_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v2, s85
-; GFX9-NEXT: v_mov_b32_e32 v4, s71
+; GFX9-NEXT: v_mov_b32_e32 v8, s36
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX9-NEXT: v_mov_b32_e32 v21, s52
+; GFX9-NEXT: v_mov_b32_e32 v2, s85
+; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
+; GFX9-NEXT: v_mov_b32_e32 v21, s52
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_mov_b32_e32 v4, s71
+; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v8
; GFX9-NEXT: v_perm_b32 v2, s17, v4, v1
; GFX9-NEXT: v_mov_b32_e32 v11, s34
+; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v21
; GFX9-NEXT: v_mov_b32_e32 v4, s69
-; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
-; GFX9-NEXT: v_mov_b32_e32 v6, s68
-; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
; GFX9-NEXT: v_perm_b32 v11, s54, v11, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
; GFX9-NEXT: v_mov_b32_e32 v22, s48
-; GFX9-NEXT: v_lshl_or_b32 v2, v21, 16, v2
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s68
+; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
; GFX9-NEXT: v_perm_b32 v4, s19, v6, v1
; GFX9-NEXT: v_mov_b32_e32 v14, s30
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; GFX9-NEXT: v_mov_b32_e32 v6, s70
-; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshl_or_b32 v2, v11, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v9, s80
-; GFX9-NEXT: v_perm_b32 v7, s20, v6, v1
; GFX9-NEXT: v_perm_b32 v14, s39, v14, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX9-NEXT: v_perm_b32 v7, s20, v6, v1
; GFX9-NEXT: v_mov_b32_e32 v23, s49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: v_lshl_or_b32 v2, v22, 16, v4
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v14
+; GFX9-NEXT: v_mov_b32_e32 v9, s80
+; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v7, v2
; GFX9-NEXT: v_perm_b32 v6, s21, v9, v1
; GFX9-NEXT: v_mov_b32_e32 v15, s94
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v9, s64
-; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshl_or_b32 v2, v14, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v12, s66
-; GFX9-NEXT: v_perm_b32 v10, s22, v9, v1
; GFX9-NEXT: v_perm_b32 v15, s97, v15, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v6, v2
+; GFX9-NEXT: v_perm_b32 v10, s22, v9, v1
; GFX9-NEXT: v_mov_b32_e32 v24, s98
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: v_lshl_or_b32 v2, v23, 16, v6
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v15
+; GFX9-NEXT: v_mov_b32_e32 v12, s66
+; GFX9-NEXT: v_perm_b32 v24, s87, v24, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v10, v2
; GFX9-NEXT: v_perm_b32 v9, s23, v12, v1
; GFX9-NEXT: v_mov_b32_e32 v16, s92
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v24
; GFX9-NEXT: v_mov_b32_e32 v12, s55
-; GFX9-NEXT: v_perm_b32 v24, s87, v24, v1
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshl_or_b32 v2, v15, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v17, s65
-; GFX9-NEXT: v_perm_b32 v13, s24, v12, v1
; GFX9-NEXT: v_perm_b32 v16, s86, v16, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v9, v2
+; GFX9-NEXT: v_perm_b32 v13, s24, v12, v1
; GFX9-NEXT: v_mov_b32_e32 v25, s84
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: v_lshl_or_b32 v2, v24, 16, v9
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v16
+; GFX9-NEXT: v_mov_b32_e32 v17, s65
+; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v13, v2
; GFX9-NEXT: v_perm_b32 v12, s25, v17, v1
; GFX9-NEXT: v_mov_b32_e32 v17, s90
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v25
; GFX9-NEXT: v_mov_b32_e32 v18, s67
-; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshl_or_b32 v2, v16, 16, v13
-; GFX9-NEXT: v_mov_b32_e32 v8, s36
-; GFX9-NEXT: v_mov_b32_e32 v19, s53
-; GFX9-NEXT: v_perm_b32 v18, s26, v18, v1
; GFX9-NEXT: v_perm_b32 v17, s82, v17, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v12, v2
+; GFX9-NEXT: v_perm_b32 v18, s26, v18, v1
; GFX9-NEXT: v_mov_b32_e32 v26, s81
; GFX9-NEXT: v_readlane_b32 s16, v30, 49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: v_lshl_or_b32 v2, v25, 16, v12
-; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
-; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX9-NEXT: v_mov_b32_e32 v19, s53
; GFX9-NEXT: v_perm_b32 v26, s16, v26, v1
; GFX9-NEXT: v_readlane_b32 s16, v30, 47
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshl_or_b32 v2, v17, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v2, v18, v2
+; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
; GFX9-NEXT: v_mov_b32_e32 v20, s88
-; GFX9-NEXT: v_mov_b32_e32 v27, s83
; GFX9-NEXT: v_mov_b32_e32 v28, s16
-; GFX9-NEXT: v_lshl_or_b32 v3, v8, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 48
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: v_lshl_or_b32 v2, v26, 16, v19
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v26
+; GFX9-NEXT: v_mov_b32_e32 v27, s83
; GFX9-NEXT: v_perm_b32 v3, s16, v20, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v19, v2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_perm_b32 v2, s28, v27, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 45
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 46
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v2, s29, v28, v1
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 44
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s78
; GFX9-NEXT: v_readlane_b32 s16, v30, 43
-; GFX9-NEXT: v_perm_b32 v2, s44, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s44, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 42
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 40
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 41
-; GFX9-NEXT: v_perm_b32 v2, s45, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s45, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 39
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s76
; GFX9-NEXT: v_readlane_b32 s16, v30, 38
-; GFX9-NEXT: v_perm_b32 v2, s42, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s42, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 37
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 35
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 36
-; GFX9-NEXT: v_perm_b32 v2, s43, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s43, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 34
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: v_readlane_b32 s16, v30, 33
-; GFX9-NEXT: v_perm_b32 v2, s40, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s40, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 32
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 30
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 31
-; GFX9-NEXT: v_perm_b32 v2, s41, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s41, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 29
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: v_mov_b32_e32 v2, s16
@@ -10456,16 +10537,18 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: v_readlane_b32 s14, v30, 28
; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s14, v30, 27
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: v_mov_b32_e32 v2, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 25
; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 26
-; GFX9-NEXT: v_perm_b32 v2, s15, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s15, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s14, v30, 24
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: v_mov_b32_e32 v2, s14
@@ -10473,16 +10556,18 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s62
; GFX9-NEXT: v_readlane_b32 s12, v30, 23
; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s12, v30, 22
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: v_mov_b32_e32 v2, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 20
; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 21
-; GFX9-NEXT: v_perm_b32 v2, s13, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s13, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s12, v30, 19
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: v_mov_b32_e32 v2, s12
@@ -10490,16 +10575,18 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s60
; GFX9-NEXT: v_readlane_b32 s10, v30, 18
; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s10, v30, 17
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: v_mov_b32_e32 v2, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 15
; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 16
-; GFX9-NEXT: v_perm_b32 v2, s11, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s11, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s10, v30, 14
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: v_mov_b32_e32 v2, s10
@@ -10507,16 +10594,18 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s58
; GFX9-NEXT: v_readlane_b32 s8, v30, 13
; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s8, v30, 12
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: v_mov_b32_e32 v2, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 10
; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 11
-; GFX9-NEXT: v_perm_b32 v2, s9, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s9, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s8, v30, 9
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: v_mov_b32_e32 v2, s8
@@ -10524,16 +10613,18 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_readlane_b32 s6, v30, 8
; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s6, v30, 7
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 5
; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 6
-; GFX9-NEXT: v_perm_b32 v2, s7, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s7, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s6, v30, 4
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: v_mov_b32_e32 v2, s6
@@ -10541,7 +10632,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: v_readlane_b32 s4, v30, 3
; GFX9-NEXT: v_perm_b32 v3, s4, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s4, v30, 2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_mov_b32_e32 v2, s4
@@ -10550,7 +10642,8 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_readlane_b32 s4, v30, 1
; GFX9-NEXT: v_perm_b32 v2, s5, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s4, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: v_readlane_b32 s30, v29, 34
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: v_readlane_b32 s31, v29, 35
@@ -11141,65 +11234,70 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: s_lshr_b64 s[42:43], s[4:5], 24
; GFX11-NEXT: .LBB13_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v2, s103, s30, v1
+; GFX11-NEXT: v_readlane_b32 s30, v24, 7
+; GFX11-NEXT: v_readlane_b32 s31, v24, 8
+; GFX11-NEXT: v_readlane_b32 s103, v24, 5
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_perm_b32 v18, s84, s83, v1
; GFX11-NEXT: v_perm_b32 v3, s0, s104, v1
; GFX11-NEXT: v_perm_b32 v4, s1, s102, v1
; GFX11-NEXT: v_perm_b32 v5, s100, s94, v1
+; GFX11-NEXT: v_perm_b32 v19, s81, s80, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-NEXT: v_perm_b32 v6, s2, s101, v1
; GFX11-NEXT: v_perm_b32 v7, s3, s99, v1
-; GFX11-NEXT: v_perm_b32 v18, s84, s83, v1
-; GFX11-NEXT: v_perm_b32 v19, s81, s80, v1
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-NEXT: v_perm_b32 v8, s97, s92, v1
+; GFX11-NEXT: v_or_b32_e32 v3, v4, v18
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v19
+; GFX11-NEXT: v_perm_b32 v11, s86, s90, v1
+; GFX11-NEXT: v_perm_b32 v20, s71, s70, v1
+; GFX11-NEXT: v_perm_b32 v21, s67, s66, v1
+; GFX11-NEXT: v_or_b32_e32 v4, v6, v4
+; GFX11-NEXT: v_or_b32_e32 v5, v7, v5
; GFX11-NEXT: v_perm_b32 v9, s16, s98, v1
; GFX11-NEXT: v_perm_b32 v10, s17, s96, v1
-; GFX11-NEXT: v_perm_b32 v11, s86, s90, v1
; GFX11-NEXT: v_perm_b32 v12, s18, s87, v1
; GFX11-NEXT: v_perm_b32 v13, s19, s85, v1
-; GFX11-NEXT: v_perm_b32 v20, s71, s70, v1
-; GFX11-NEXT: v_perm_b32 v21, s67, s66, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, v2, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v3, v18, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v4, v5, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v5, v19, 16, v7
-; GFX11-NEXT: v_readlane_b32 s0, v25, 6
-; GFX11-NEXT: v_readlane_b32 s1, v25, 4
-; GFX11-NEXT: v_readlane_b32 s30, v24, 7
-; GFX11-NEXT: v_readlane_b32 s31, v24, 8
+; GFX11-NEXT: v_perm_b32 v22, s64, s55, v1
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off
-; GFX11-NEXT: v_lshl_or_b32 v2, v8, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v3, v20, 16, v10
-; GFX11-NEXT: v_lshl_or_b32 v4, v11, 16, v12
-; GFX11-NEXT: v_lshl_or_b32 v5, v21, 16, v13
-; GFX11-NEXT: v_readlane_b32 s104, v24, 6
-; GFX11-NEXT: v_readlane_b32 s103, v24, 5
-; GFX11-NEXT: v_readlane_b32 s102, v24, 4
-; GFX11-NEXT: v_readlane_b32 s101, v24, 3
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:16
-; GFX11-NEXT: v_perm_b32 v5, s50, s72, v1
-; GFX11-NEXT: v_readlane_b32 s100, v24, 2
-; GFX11-NEXT: v_readlane_b32 s99, v24, 1
-; GFX11-NEXT: v_readlane_b32 s98, v24, 0
-; GFX11-NEXT: v_readlane_b32 s97, v23, 31
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-NEXT: v_perm_b32 v8, s48, s39, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v11
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v21
; GFX11-NEXT: v_perm_b32 v14, s82, s88, v1
+; GFX11-NEXT: v_perm_b32 v17, s21, s65, v1
+; GFX11-NEXT: v_or_b32_e32 v2, v9, v2
+; GFX11-NEXT: v_or_b32_e32 v3, v10, v3
+; GFX11-NEXT: v_or_b32_e32 v4, v12, v4
+; GFX11-NEXT: v_or_b32_e32 v5, v13, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v22
; GFX11-NEXT: v_perm_b32 v15, s69, s78, v1
; GFX11-NEXT: v_perm_b32 v16, s20, s68, v1
-; GFX11-NEXT: v_perm_b32 v17, s21, s65, v1
-; GFX11-NEXT: v_perm_b32 v22, s64, s55, v1
; GFX11-NEXT: v_perm_b32 v6, s53, s52, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v14
+; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:16
+; GFX11-NEXT: v_or_b32_e32 v3, v17, v8
+; GFX11-NEXT: v_perm_b32 v8, s48, s39, v1
; GFX11-NEXT: v_perm_b32 v9, s22, s54, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v15
+; GFX11-NEXT: v_or_b32_e32 v2, v16, v7
+; GFX11-NEXT: v_perm_b32 v5, s50, s72, v1
; GFX11-NEXT: v_perm_b32 v7, s23, s51, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v11, s25, s38, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v2, v14, 16, v16
-; GFX11-NEXT: v_lshl_or_b32 v3, v22, 16, v17
-; GFX11-NEXT: v_lshl_or_b32 v4, v15, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v7
+; GFX11-NEXT: v_readlane_b32 s0, v25, 6
+; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-NEXT: v_or_b32_e32 v7, v11, v8
; GFX11-NEXT: v_perm_b32 v11, s0, s74, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 3
+; GFX11-NEXT: v_readlane_b32 s1, v25, 4
; GFX11-NEXT: v_perm_b32 v9, s24, s49, v1
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:32
; GFX11-NEXT: v_perm_b32 v12, s37, s76, v1
@@ -11208,102 +11306,109 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: v_readlane_b32 s0, v25, 7
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_perm_b32 v10, s34, vcc_hi, v1
-; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; GFX11-NEXT: v_perm_b32 v4, s28, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 5
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-NEXT: v_perm_b32 v9, s27, s35, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s29, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 1
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_readlane_b32 s1, v26, 31
; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
-; GFX11-NEXT: v_readlane_b32 s96, v23, 30
; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s62, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 2
+; GFX11-NEXT: v_readlane_b32 s104, v24, 6
; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:48
-; GFX11-NEXT: v_readlane_b32 s87, v23, 29
-; GFX11-NEXT: v_readlane_b32 s86, v23, 28
-; GFX11-NEXT: v_readlane_b32 s85, v23, 27
+; GFX11-NEXT: v_readlane_b32 s102, v24, 4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
; GFX11-NEXT: v_perm_b32 v4, s40, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 30
-; GFX11-NEXT: v_readlane_b32 s84, v23, 26
-; GFX11-NEXT: v_readlane_b32 s83, v23, 25
-; GFX11-NEXT: v_readlane_b32 s82, v23, 24
-; GFX11-NEXT: v_lshl_or_b32 v4, v12, 16, v4
+; GFX11-NEXT: v_readlane_b32 s101, v24, 3
+; GFX11-NEXT: v_readlane_b32 s100, v24, 2
+; GFX11-NEXT: v_readlane_b32 s99, v24, 1
+; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 0
; GFX11-NEXT: v_readlane_b32 s1, v26, 26
-; GFX11-NEXT: v_readlane_b32 s81, v23, 23
-; GFX11-NEXT: v_readlane_b32 s80, v23, 22
+; GFX11-NEXT: v_readlane_b32 s98, v24, 0
+; GFX11-NEXT: v_readlane_b32 s97, v23, 31
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v10
; GFX11-NEXT: v_perm_b32 v5, s41, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 28
-; GFX11-NEXT: v_readlane_b32 s71, v23, 21
-; GFX11-NEXT: v_readlane_b32 s70, v23, 20
-; GFX11-NEXT: v_readlane_b32 s69, v23, 19
+; GFX11-NEXT: v_readlane_b32 s96, v23, 30
+; GFX11-NEXT: v_readlane_b32 s87, v23, 29
+; GFX11-NEXT: v_readlane_b32 s86, v23, 28
; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-NEXT: v_perm_b32 v11, s0, s60, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 25
-; GFX11-NEXT: v_readlane_b32 s68, v23, 18
-; GFX11-NEXT: v_readlane_b32 s67, v23, 17
+; GFX11-NEXT: v_readlane_b32 s85, v23, 27
+; GFX11-NEXT: v_readlane_b32 s84, v23, 26
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:64
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v11
; GFX11-NEXT: v_perm_b32 v6, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 29
; GFX11-NEXT: v_readlane_b32 s1, v26, 21
-; GFX11-NEXT: v_readlane_b32 s66, v23, 16
-; GFX11-NEXT: v_readlane_b32 s65, v23, 15
+; GFX11-NEXT: v_readlane_b32 s83, v23, 25
+; GFX11-NEXT: v_readlane_b32 s82, v23, 24
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v6
; GFX11-NEXT: v_perm_b32 v8, s14, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 27
-; GFX11-NEXT: v_readlane_b32 s64, v23, 14
-; GFX11-NEXT: v_readlane_b32 s55, v23, 13
-; GFX11-NEXT: v_readlane_b32 s54, v23, 12
+; GFX11-NEXT: v_readlane_b32 s81, v23, 23
+; GFX11-NEXT: v_readlane_b32 s80, v23, 22
+; GFX11-NEXT: v_readlane_b32 s71, v23, 21
; GFX11-NEXT: v_or_b32_e32 v6, v8, v9
; GFX11-NEXT: v_perm_b32 v10, s15, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 23
-; GFX11-NEXT: v_readlane_b32 s53, v23, 11
-; GFX11-NEXT: v_readlane_b32 s52, v23, 10
-; GFX11-NEXT: v_readlane_b32 s51, v23, 9
+; GFX11-NEXT: v_readlane_b32 s70, v23, 20
+; GFX11-NEXT: v_readlane_b32 s69, v23, 19
+; GFX11-NEXT: v_readlane_b32 s68, v23, 18
; GFX11-NEXT: v_or_b32_e32 v7, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s58, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 24
-; GFX11-NEXT: v_readlane_b32 s50, v23, 8
-; GFX11-NEXT: v_readlane_b32 s49, v23, 7
-; GFX11-NEXT: v_readlane_b32 s48, v23, 6
-; GFX11-NEXT: v_readlane_b32 s39, v23, 5
+; GFX11-NEXT: v_readlane_b32 s67, v23, 17
+; GFX11-NEXT: v_readlane_b32 s66, v23, 16
+; GFX11-NEXT: v_readlane_b32 s65, v23, 15
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
; GFX11-NEXT: v_perm_b32 v8, s12, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 20
-; GFX11-NEXT: v_readlane_b32 s38, v23, 4
-; GFX11-NEXT: v_readlane_b32 s37, v23, 3
-; GFX11-NEXT: v_readlane_b32 s36, v23, 2
-; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v8
+; GFX11-NEXT: v_readlane_b32 s64, v23, 14
+; GFX11-NEXT: v_readlane_b32 s55, v23, 13
+; GFX11-NEXT: v_readlane_b32 s54, v23, 12
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 22
; GFX11-NEXT: v_readlane_b32 s1, v26, 16
-; GFX11-NEXT: v_readlane_b32 s35, v23, 1
-; GFX11-NEXT: v_readlane_b32 s34, v23, 0
+; GFX11-NEXT: v_readlane_b32 s53, v23, 11
+; GFX11-NEXT: v_readlane_b32 s52, v23, 10
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; GFX11-NEXT: v_perm_b32 v9, s13, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 18
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readlane_b32 s51, v23, 9
+; GFX11-NEXT: v_readlane_b32 s50, v23, 8
+; GFX11-NEXT: v_readlane_b32 s49, v23, 7
; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
; GFX11-NEXT: v_perm_b32 v11, s0, s56, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 15
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readlane_b32 s48, v23, 6
+; GFX11-NEXT: v_readlane_b32 s39, v23, 5
+; GFX11-NEXT: v_readlane_b32 s38, v23, 4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; GFX11-NEXT: v_perm_b32 v2, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 19
; GFX11-NEXT: v_readlane_b32 s1, v26, 11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_readlane_b32 s37, v23, 3
+; GFX11-NEXT: v_readlane_b32 s36, v23, 2
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX11-NEXT: v_perm_b32 v4, s10, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 17
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readlane_b32 s35, v23, 1
+; GFX11-NEXT: v_readlane_b32 s34, v23, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s11, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 13
@@ -11311,45 +11416,53 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s46, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
; GFX11-NEXT: v_perm_b32 v4, s8, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 10
-; GFX11-NEXT: v_lshl_or_b32 v4, v12, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 12
; GFX11-NEXT: v_readlane_b32 s1, v26, 6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v5, s9, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshl_or_b32 v5, v10, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v5, v5, v10
; GFX11-NEXT: v_perm_b32 v11, s0, s44, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 9
; GFX11-NEXT: v_readlane_b32 s1, v26, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v12, s6, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 7
-; GFX11-NEXT: v_lshl_or_b32 v10, v11, 16, v12
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v10, v12, v11
; GFX11-NEXT: v_perm_b32 v14, s7, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v11, v14, v13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v12, s0, s42, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_perm_b32 v13, s4, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX11-NEXT: v_or_b32_e32 v12, v13, v12
; GFX11-NEXT: v_perm_b32 v13, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-NEXT: v_perm_b32 v1, s5, s0, v1
-; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v13, v1, v13
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:80
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:96
@@ -13352,12 +13465,19 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v33, v62, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v63, v60, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v53, v58, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v51, v56, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v45, v44, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v49, v48, s6
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr62
; VI-NEXT: ; implicit-def: $vgpr63
@@ -13378,18 +13498,21 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v16, v17, v16, s6
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13398,7 +13521,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13407,7 +13531,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13416,7 +13541,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13425,7 +13551,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13434,7 +13561,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13442,23 +13570,24 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v41, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v55, v34, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v61, v32, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v59, v54, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v57, v52, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v47, v38, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v35, v46, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_perm_b32 v14, v43, v50, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: v_perm_b32 v15, v39, v42, s6
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr41
@@ -13483,7 +13612,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
-; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13492,7 +13622,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
-; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; VI-NEXT: v_or_b32_e32 v17, v17, v18
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13501,7 +13632,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13510,7 +13642,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13519,7 +13652,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13528,7 +13662,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13537,7 +13672,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s6
-; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v22, v23
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13546,7 +13682,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13555,7 +13692,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s6
-; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v24, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13564,7 +13702,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v25, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13573,7 +13712,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v26, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13582,7 +13722,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13591,7 +13732,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v28, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13600,7 +13742,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13609,7 +13752,8 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v30, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -13682,9 +13826,10 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
+; VI-NEXT: v_or_b32_e32 v31, v31, v32
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
@@ -16886,18 +17031,18 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
@@ -16920,28 +17065,28 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -16956,16 +17101,18 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
@@ -16984,27 +17131,28 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
@@ -17019,12 +17167,13 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
@@ -17047,27 +17196,28 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
@@ -17082,12 +17232,13 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v18, 16, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
@@ -17110,27 +17261,28 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
@@ -17145,12 +17297,13 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
@@ -17173,27 +17326,28 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
@@ -17208,11 +17362,12 @@ define <32 x i32> @bitcast_v128i8_to_v32i32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
@@ -18734,103 +18889,127 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB15_2
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s73
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s73
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s61
+; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s61
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s57
+; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s57
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s45
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s45
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s41
+; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s13
+; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s13
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s9
+; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s9
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s6, v15, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v14, v13, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s6, v15, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v52, v51, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v54, v53, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v48, v39, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v50, v49, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v36, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v38, v37, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v32, v16, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_perm_b32 v16, v60, v17, s4
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: v_perm_b32 v17, v62, v61, s4
-; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_perm_b32 v17, v59, v18, s4
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: v_perm_b32 v18, v41, v40, s4
-; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v18
+; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_perm_b32 v18, v57, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v19, v42, v58, s4
-; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_perm_b32 v19, v45, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: v_perm_b32 v20, v56, v47, s4
-; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_perm_b32 v20, v44, v21, s4
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: v_perm_b32 v21, v46, v26, s4
-; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_perm_b32 v21, v31, v22, s4
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: v_perm_b32 v22, v24, v43, s4
-; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_perm_b32 v22, v28, v23, s4
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; VI-NEXT: v_perm_b32 v23, v30, v29, s4
-; VI-NEXT: v_mov_b32_e32 v44, v24
-; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_perm_b32 v23, v25, v63, s4
+; VI-NEXT: v_mov_b32_e32 v44, v24
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; VI-NEXT: v_perm_b32 v24, v27, v55, s4
-; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v45, v26
@@ -18840,72 +19019,80 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v24, v25, v24, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
-; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
-; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
-; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
-; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v29, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
-; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v30, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
-; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v31, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v43, v46, v43, s4
-; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; VI-NEXT: v_or_b32_e32 v31, v43, v31
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB15_3
; VI-NEXT: .LBB15_2:
@@ -19626,103 +19813,127 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB15_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
-; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s73
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s73
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s61
+; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s61
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s57
+; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s57
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s45
+; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s45
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s41
+; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s41
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
-; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s13
+; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v9, s13
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s9
+; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_mov_b32_e32 v10, s9
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
+; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
+; GFX9-NEXT: v_mov_b32_e32 v44, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v45, v26
@@ -19732,72 +19943,80 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB15_3
; GFX9-NEXT: .LBB15_2:
@@ -20337,49 +20556,56 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -20471,132 +20697,143 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB15_3
; GFX11-TRUE16-NEXT: .LBB15_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v11, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -20893,49 +21130,56 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -21027,132 +21271,143 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB15_3
; GFX11-FAKE16-NEXT: .LBB15_2: ; %cmp.true
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -40479,41 +40734,49 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v55, v57, v41, s4
; VI-NEXT: v_perm_b32 v1, v1, v48, s4
-; VI-NEXT: v_lshl_or_b32 v1, v55, 16, v1
-; VI-NEXT: v_perm_b32 v2, v2, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v55
+; VI-NEXT: v_or_b32_e32 v1, v1, v48
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v34, v56, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_perm_b32 v2, v2, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v47, v40, s4
; VI-NEXT: v_perm_b32 v2, v3, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v52, s4
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v52, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v33, v39, s4
; VI-NEXT: v_perm_b32 v2, v5, v37, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v51, s4
; VI-NEXT: v_perm_b32 v2, v44, v43, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v51, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v50, v54, s4
; VI-NEXT: v_perm_b32 v2, v7, v63, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v36, s4
; VI-NEXT: v_perm_b32 v2, v62, v61, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -40521,12 +40784,14 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v49, s4
; VI-NEXT: v_perm_b32 v1, v60, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v35, s4
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
@@ -40535,19 +40800,21 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v11, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v12, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v12, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -40556,19 +40823,21 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v14, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
@@ -40577,19 +40846,21 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v16, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -40598,19 +40869,21 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v18, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -40619,19 +40892,21 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v20, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
@@ -40641,17 +40916,19 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v22, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -40661,17 +40938,19 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v23, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v24, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v24, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
@@ -40681,70 +40960,74 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v26, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v26, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v27, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v27, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v28, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v28, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v29, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v29, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v30, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v30, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v31, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
@@ -40754,7 +41037,8 @@ define <128 x i8> @bitcast_v32f32_to_v128i8(<32 x float> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v32, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v42, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -44769,46 +45053,55 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v33, v33, v41, s4
; VI-NEXT: v_perm_b32 v31, v31, v61, s4
-; VI-NEXT: v_lshl_or_b32 v31, v33, 16, v31
-; VI-NEXT: v_perm_b32 v32, v32, v60, s4
+; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v33
+; VI-NEXT: v_or_b32_e32 v31, v31, v33
; VI-NEXT: buffer_store_dword v31, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v31, v50, v59, s4
-; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v32
+; VI-NEXT: v_perm_b32 v32, v32, v60, s4
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v31, v32, v31
; VI-NEXT: v_add_u32_e32 v32, vcc, 4, v0
; VI-NEXT: buffer_store_dword v31, v32, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v31, v48, v40, s4
; VI-NEXT: v_perm_b32 v29, v29, v58, s4
-; VI-NEXT: v_lshl_or_b32 v29, v31, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v29, v29, v31
; VI-NEXT: v_add_u32_e32 v31, vcc, 8, v0
; VI-NEXT: buffer_store_dword v29, v31, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v29, v30, v52, s4
; VI-NEXT: v_perm_b32 v30, v56, v57, s4
-; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: v_add_u32_e32 v30, vcc, 12, v0
; VI-NEXT: buffer_store_dword v29, v30, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v29, v47, v39, s4
; VI-NEXT: v_perm_b32 v27, v27, v46, s4
-; VI-NEXT: v_lshl_or_b32 v27, v29, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v27, v27, v29
; VI-NEXT: v_add_u32_e32 v29, vcc, 16, v0
; VI-NEXT: buffer_store_dword v27, v29, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v27, v28, v45, s4
; VI-NEXT: v_perm_b32 v28, v43, v44, s4
-; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: v_add_u32_e32 v28, vcc, 20, v0
; VI-NEXT: buffer_store_dword v27, v28, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v27, v42, v54, s4
; VI-NEXT: v_perm_b32 v25, v25, v49, s4
-; VI-NEXT: v_lshl_or_b32 v25, v27, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; VI-NEXT: v_or_b32_e32 v25, v25, v27
; VI-NEXT: v_add_u32_e32 v27, vcc, 24, v0
; VI-NEXT: buffer_store_dword v25, v27, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v25, v26, v51, s4
; VI-NEXT: v_perm_b32 v26, v38, v55, s4
-; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v25, v26
; VI-NEXT: v_add_u32_e32 v26, vcc, 28, v0
; VI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v25, v37, v53, s4
; VI-NEXT: v_perm_b32 v23, v23, v36, s4
-; VI-NEXT: v_lshl_or_b32 v23, v25, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; VI-NEXT: v_or_b32_e32 v23, v23, v25
; VI-NEXT: v_add_u32_e32 v25, vcc, 32, v0
; VI-NEXT: buffer_store_dword v23, v25, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
@@ -44847,7 +45140,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s4
; VI-NEXT: v_perm_b32 v24, v34, v35, s4
-; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: v_add_u32_e32 v24, vcc, 36, v0
; VI-NEXT: buffer_store_dword v23, v24, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
@@ -44856,9 +45150,10 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s4
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v21, v24, s4
-; VI-NEXT: v_lshl_or_b32 v21, v23, 16, v21
+; VI-NEXT: v_or_b32_e32 v21, v21, v23
; VI-NEXT: v_add_u32_e32 v23, vcc, 40, v0
; VI-NEXT: buffer_store_dword v21, v23, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
@@ -44868,7 +45163,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v22, v23, s4
-; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: v_add_u32_e32 v22, vcc, 44, v0
; VI-NEXT: buffer_store_dword v21, v22, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
@@ -44877,9 +45173,10 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s4
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v19, v22, s4
-; VI-NEXT: v_lshl_or_b32 v19, v21, 16, v19
+; VI-NEXT: v_or_b32_e32 v19, v19, v21
; VI-NEXT: v_add_u32_e32 v21, vcc, 48, v0
; VI-NEXT: buffer_store_dword v19, v21, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
@@ -44889,7 +45186,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v20, v21, s4
-; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: v_add_u32_e32 v20, vcc, 52, v0
; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
@@ -44898,9 +45196,10 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s4
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v17, v20, s4
-; VI-NEXT: v_lshl_or_b32 v17, v19, 16, v17
+; VI-NEXT: v_or_b32_e32 v17, v17, v19
; VI-NEXT: v_add_u32_e32 v19, vcc, 56, v0
; VI-NEXT: buffer_store_dword v17, v19, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -44910,7 +45209,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v18, v19, s4
-; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; VI-NEXT: v_or_b32_e32 v17, v17, v18
; VI-NEXT: v_add_u32_e32 v18, vcc, 60, v0
; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
@@ -44919,9 +45219,10 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s4
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v15, v18, s4
-; VI-NEXT: v_lshl_or_b32 v15, v17, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v17
; VI-NEXT: v_add_u32_e32 v17, vcc, 64, v0
; VI-NEXT: buffer_store_dword v15, v17, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
@@ -44931,7 +45232,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v16, v16, v17, s4
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
@@ -44940,9 +45242,10 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s4
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v13, v16, s4
-; VI-NEXT: v_lshl_or_b32 v13, v15, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v15
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v13, v15, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
@@ -44952,7 +45255,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v14, v14, v15, s4
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_add_u32_e32 v14, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
@@ -44963,7 +45267,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v14, v13, s4
-; VI-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; VI-NEXT: v_or_b32_e32 v11, v11, v13
; VI-NEXT: v_add_u32_e32 v13, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
@@ -44973,7 +45278,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v12, v12, v13, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
@@ -44984,7 +45290,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v11, v12, v11, s4
-; VI-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v11
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v9, v11, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
@@ -44994,7 +45301,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v10, v10, v11, s4
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -45005,7 +45313,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v9, v10, v9, s4
-; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
@@ -45015,7 +45324,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v9, s4
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -45026,7 +45336,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s4
-; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
@@ -45036,7 +45347,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v6, v7, s4
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
@@ -45047,7 +45359,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s4
-; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v3, v3, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
@@ -45057,7 +45370,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v4, v5, s4
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -45068,7 +45382,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
@@ -45079,7 +45394,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -45976,9 +46292,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_perm_b32 v35, v51, v40, s4
; GFX9-NEXT: v_perm_b32 v55, v55, v42, s4
; GFX9-NEXT: v_perm_b32 v20, v48, v20, s4
-; GFX9-NEXT: v_lshl_or_b32 v20, v55, 16, v20
; GFX9-NEXT: v_perm_b32 v48, v52, v41, s4
-; GFX9-NEXT: v_lshl_or_b32 v18, v48, 16, v18
; GFX9-NEXT: v_perm_b32 v17, v36, v17, s4
; GFX9-NEXT: v_perm_b32 v33, v33, v61, s4
; GFX9-NEXT: v_perm_b32 v31, v31, v60, s4
@@ -46047,89 +46361,110 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v15, v15, v50, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v50, 16, v55
+; GFX9-NEXT: v_or_b32_e32 v20, v20, v50
; GFX9-NEXT: buffer_store_dword v20, v0, s[0:3], 0 offen
; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v20, v20, v50, s4
-; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX9-NEXT: v_or_b32_e32 v19, v19, v20
; GFX9-NEXT: buffer_store_dword v19, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v48
+; GFX9-NEXT: v_or_b32_e32 v18, v18, v19
; GFX9-NEXT: buffer_store_dword v18, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v18, v19, s4
-; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v17, v17, v18
; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshl_or_b32 v17, v35, 16, v33
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v35
+; GFX9-NEXT: v_or_b32_e32 v17, v33, v17
; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX9-NEXT: v_or_b32_e32 v16, v16, v17
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshl_or_b32 v16, v34, 16, v31
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v34
+; GFX9-NEXT: v_or_b32_e32 v16, v31, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v32
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v32, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshl_or_b32 v16, v36, 16, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v36
+; GFX9-NEXT: v_or_b32_e32 v16, v29, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v30, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshl_or_b32 v16, v37, 16, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v37
+; GFX9-NEXT: v_or_b32_e32 v16, v27, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v28
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v28, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshl_or_b32 v16, v38, 16, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v38
+; GFX9-NEXT: v_or_b32_e32 v16, v25, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v26, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshl_or_b32 v16, v39, 16, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v39
+; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v24, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshl_or_b32 v16, v49, 16, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v49
+; GFX9-NEXT: v_or_b32_e32 v16, v21, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v15, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46138,7 +46473,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v14, v15, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46148,7 +46484,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46157,7 +46494,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46167,7 +46505,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46176,7 +46515,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v10, v11, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46186,7 +46526,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46195,7 +46536,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46205,7 +46547,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46214,7 +46557,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v6, v7, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46224,7 +46568,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46233,7 +46578,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46243,7 +46589,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46252,7 +46599,8 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -46946,106 +47294,138 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: v_readlane_b32 s0, v77, 7
; GFX11-NEXT: v_mov_b32_e32 v70, s0
; GFX11-NEXT: .LBB37_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v67, v73, v67, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v66, v60, v66, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v33, v33, v72, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v34, v34, v63, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v68, v61, v62, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v66, v60, v66, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v57, v31, v57, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v67
+; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v66
; GFX11-NEXT: v_perm_b32 v58, v58, v59, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v56, v32, v56, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v31, v67, 16, v33
-; GFX11-NEXT: v_lshl_or_b32 v32, v68, 16, v34
+; GFX11-NEXT: v_perm_b32 v34, v34, v63, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX11-NEXT: v_or_b32_e32 v31, v33, v67
; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v33, v66, 16, v57
-; GFX11-NEXT: v_perm_b32 v27, v27, v46, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v33, v57, v66
; GFX11-NEXT: v_perm_b32 v66, v44, v45, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v28, v28, v42, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v67, v40, v41, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v56, v32, v56, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v58, 16, v58
+; GFX11-NEXT: v_perm_b32 v53, v177, v53, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v32, v34, v68
+; GFX11-NEXT: v_perm_b32 v27, v27, v46, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v65
+; GFX11-NEXT: v_perm_b32 v28, v28, v42, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v66
; GFX11-NEXT: v_perm_b32 v68, v25, v183, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
; GFX11-NEXT: v_perm_b32 v182, v26, v182, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v34, v58, 16, v56
-; GFX11-NEXT: v_perm_b32 v53, v177, v53, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v67
+; GFX11-NEXT: v_or_b32_e32 v34, v56, v58
; GFX11-NEXT: v_perm_b32 v21, v21, v167, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v25, v65, 16, v27
-; GFX11-NEXT: v_lshl_or_b32 v26, v66, 16, v28
-; GFX11-NEXT: v_lshl_or_b32 v27, v64, 16, v68
-; GFX11-NEXT: v_lshl_or_b32 v28, v67, 16, v182
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v53
+; GFX11-NEXT: v_or_b32_e32 v25, v27, v65
+; GFX11-NEXT: v_or_b32_e32 v26, v28, v66
+; GFX11-NEXT: v_or_b32_e32 v27, v68, v64
+; GFX11-NEXT: v_or_b32_e32 v28, v182, v67
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_store_b128 v0, v[31:34], off
; GFX11-NEXT: scratch_store_b128 v0, v[25:28], off offset:16
; GFX11-NEXT: v_perm_b32 v26, v165, v166, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v25, v53, 16, v21
+; GFX11-NEXT: v_or_b32_e32 v25, v21, v53
; GFX11-NEXT: v_perm_b32 v21, v22, v164, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v163, v52, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v19, v19, v160, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v28, v151, v51, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v17, v17, v149, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v27, v161, v162, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-NEXT: v_perm_b32 v19, v19, v160, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-NEXT: v_perm_b32 v17, v17, v149, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-NEXT: v_perm_b32 v20, v20, v150, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v26, v26, 16, v21
-; GFX11-NEXT: v_lshl_or_b32 v19, v22, 16, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-NEXT: v_or_b32_e32 v26, v21, v26
+; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
; GFX11-NEXT: v_perm_b32 v22, v147, v148, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v21, v28, 16, v17
+; GFX11-NEXT: v_or_b32_e32 v21, v17, v28
; GFX11-NEXT: v_perm_b32 v17, v18, v146, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v145, v50, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v15, v133, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v28, v134, v49, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v132, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v20, v27, 16, v20
+; GFX11-NEXT: v_or_b32_e32 v20, v20, v27
; GFX11-NEXT: v_perm_b32 v27, v135, v144, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-NEXT: v_perm_b32 v15, v15, v133, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v13, v13, v132, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-NEXT: v_perm_b32 v16, v16, v131, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v22, v22, 16, v17
-; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
+; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
; GFX11-NEXT: v_perm_b32 v18, v129, v130, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v17, v28, 16, v13
-; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v17, v13, v28
; GFX11-NEXT: v_perm_b32 v28, v116, v38, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v9, v114, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v16, v27, 16, v16
+; GFX11-NEXT: v_or_b32_e32 v16, v16, v27
+; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v14, v119, v48, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v27, v117, v118, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v9, v9, v114, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-NEXT: v_perm_b32 v11, v11, v115, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v113, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v13
-; GFX11-NEXT: v_lshl_or_b32 v13, v28, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
+; GFX11-NEXT: v_or_b32_e32 v13, v9, v28
; GFX11-NEXT: v_perm_b32 v9, v10, v102, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v101, v37, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v97, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v54, v181, v54, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v179, v180, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v23, v178, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v24, v176, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
+; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
; GFX11-NEXT: v_perm_b32 v14, v103, v112, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v12, v27, 16, v12
+; GFX11-NEXT: v_or_b32_e32 v12, v12, v27
; GFX11-NEXT: v_perm_b32 v27, v99, v100, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v28, v98, v36, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v97, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v54, v181, v54, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v179, v180, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v87, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX11-NEXT: v_perm_b32 v5, v5, v96, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
; GFX11-NEXT: v_perm_b32 v10, v85, v86, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v80, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v23, v54, 16, v23
-; GFX11-NEXT: v_lshl_or_b32 v24, v64, 16, v24
-; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v8, v27, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v9, v28, 16, v5
+; GFX11-NEXT: v_perm_b32 v23, v23, v178, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v54
+; GFX11-NEXT: v_perm_b32 v24, v24, v176, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
+; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v27
+; GFX11-NEXT: v_or_b32_e32 v9, v5, v28
; GFX11-NEXT: v_perm_b32 v5, v84, v35, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v27, v81, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v28, v71, v29, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v29, v69, v70, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v6, v80, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_or_b32_e32 v23, v23, v54
+; GFX11-NEXT: v_or_b32_e32 v24, v24, v64
+; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX11-NEXT: v_perm_b32 v30, v1, v30, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-NEXT: v_perm_b32 v31, v2, v39, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v27, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v3, v28, 16, v30
-; GFX11-NEXT: v_lshl_or_b32 v4, v29, 16, v31
+; GFX11-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v27
+; GFX11-NEXT: v_or_b32_e32 v3, v30, v28
+; GFX11-NEXT: v_or_b32_e32 v4, v31, v29
; GFX11-NEXT: s_clause 0x5
; GFX11-NEXT: scratch_store_b128 v0, v[23:26], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
@@ -48973,12 +49353,19 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v33, v62, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v63, v60, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v53, v58, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v51, v56, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v45, v44, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v49, v48, s6
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr62
; VI-NEXT: ; implicit-def: $vgpr63
@@ -48999,18 +49386,21 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v16, v17, v16, s6
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49019,7 +49409,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49028,7 +49419,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49037,7 +49429,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49046,7 +49439,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49055,7 +49449,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49063,23 +49458,24 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v41, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v55, v34, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v61, v32, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v59, v54, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v57, v52, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v47, v38, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v35, v46, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_perm_b32 v14, v43, v50, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: v_perm_b32 v15, v39, v42, s6
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr41
@@ -49104,7 +49500,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
-; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49113,7 +49510,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
-; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; VI-NEXT: v_or_b32_e32 v17, v17, v18
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49122,7 +49520,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49131,7 +49530,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49140,7 +49540,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49149,7 +49550,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49158,7 +49560,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s6
-; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v22, v23
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49167,7 +49570,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49176,7 +49580,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s6
-; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v24, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49185,7 +49590,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v25, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49194,7 +49600,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v26, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49203,7 +49610,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49212,7 +49620,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v28, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49221,7 +49630,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49230,7 +49640,8 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v30, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -49303,9 +49714,10 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
+; VI-NEXT: v_or_b32_e32 v31, v31, v32
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
@@ -52507,18 +52919,18 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
@@ -52541,28 +52953,28 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -52577,16 +52989,18 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
@@ -52605,27 +53019,28 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
@@ -52640,12 +53055,13 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
@@ -52668,27 +53084,28 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
@@ -52703,12 +53120,13 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v18, 16, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
@@ -52731,27 +53149,28 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
@@ -52766,12 +53185,13 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
@@ -52794,27 +53214,28 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
@@ -52829,11 +53250,12 @@ define <32 x float> @bitcast_v128i8_to_v32f32(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
@@ -54355,103 +54777,127 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB39_2
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s73
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s73
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s61
+; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s61
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s57
+; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s57
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s45
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s45
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s41
+; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s13
+; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s13
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s9
+; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s9
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s6, v15, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v14, v13, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s6, v15, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v52, v51, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v54, v53, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v48, v39, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v50, v49, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v36, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v38, v37, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v32, v16, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_perm_b32 v16, v60, v17, s4
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: v_perm_b32 v17, v62, v61, s4
-; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_perm_b32 v17, v59, v18, s4
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: v_perm_b32 v18, v41, v40, s4
-; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v18
+; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_perm_b32 v18, v57, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v19, v42, v58, s4
-; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_perm_b32 v19, v45, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: v_perm_b32 v20, v56, v47, s4
-; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_perm_b32 v20, v44, v21, s4
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: v_perm_b32 v21, v46, v26, s4
-; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_perm_b32 v21, v31, v22, s4
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: v_perm_b32 v22, v24, v43, s4
-; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_perm_b32 v22, v28, v23, s4
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; VI-NEXT: v_perm_b32 v23, v30, v29, s4
-; VI-NEXT: v_mov_b32_e32 v44, v24
-; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_perm_b32 v23, v25, v63, s4
+; VI-NEXT: v_mov_b32_e32 v44, v24
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; VI-NEXT: v_perm_b32 v24, v27, v55, s4
-; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v45, v26
@@ -54461,72 +54907,80 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; VI-NEXT: v_perm_b32 v24, v25, v24, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
-; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
-; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
-; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
-; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v29, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
-; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v30, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
-; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v31, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v43, v46, v43, s4
-; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; VI-NEXT: v_or_b32_e32 v31, v43, v31
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB39_3
; VI-NEXT: .LBB39_2:
@@ -55247,103 +55701,127 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB39_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
-; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s73
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s73
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s61
+; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s61
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s57
+; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s57
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s45
+; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s45
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s41
+; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s41
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
-; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s13
+; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v9, s13
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s9
+; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_mov_b32_e32 v10, s9
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
+; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
+; GFX9-NEXT: v_mov_b32_e32 v44, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v45, v26
@@ -55353,72 +55831,80 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB39_3
; GFX9-NEXT: .LBB39_2:
@@ -55958,49 +56444,56 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -56092,132 +56585,143 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB39_3
; GFX11-TRUE16-NEXT: .LBB39_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v11, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -56514,49 +57018,56 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -56648,132 +57159,143 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB39_3
; GFX11-FAKE16-NEXT: .LBB39_2: ; %cmp.true
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -74962,41 +75484,49 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v55, v57, v41, s4
; VI-NEXT: v_perm_b32 v1, v1, v48, s4
-; VI-NEXT: v_lshl_or_b32 v1, v55, 16, v1
-; VI-NEXT: v_perm_b32 v2, v2, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v48, 16, v55
+; VI-NEXT: v_or_b32_e32 v1, v1, v48
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v34, v56, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_perm_b32 v2, v2, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v47, v40, s4
; VI-NEXT: v_perm_b32 v2, v3, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v52, s4
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v52, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v33, v39, s4
; VI-NEXT: v_perm_b32 v2, v5, v37, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v51, s4
; VI-NEXT: v_perm_b32 v2, v44, v43, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v51, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v50, v54, s4
; VI-NEXT: v_perm_b32 v2, v7, v63, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v36, s4
; VI-NEXT: v_perm_b32 v2, v62, v61, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -75004,12 +75534,14 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v49, s4
; VI-NEXT: v_perm_b32 v1, v60, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v35, s4
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
@@ -75018,19 +75550,21 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v11, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v12, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v12, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -75039,19 +75573,21 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v14, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
@@ -75060,19 +75596,21 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v16, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -75081,19 +75619,21 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v18, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -75102,19 +75642,21 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v20, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
@@ -75124,17 +75666,19 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v22, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -75144,17 +75688,19 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v23, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v24, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v24, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
@@ -75164,70 +75710,74 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v26, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v26, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v27, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v27, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v28, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v28, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v29, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v29, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v30, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v30, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v31, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
@@ -75237,7 +75787,8 @@ define <128 x i8> @bitcast_v16i64_to_v128i8(<16 x i64> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v32, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v42, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -78676,121 +79227,136 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: s_lshr_b64 s[48:49], s[16:17], 24
; VI-NEXT: .LBB57_3: ; %end
; VI-NEXT: v_mov_b32_e32 v9, s48
-; VI-NEXT: v_mov_b32_e32 v2, s82
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; VI-NEXT: v_mov_b32_e32 v4, s67
-; VI-NEXT: v_perm_b32 v3, s16, v2, v1
+; VI-NEXT: v_mov_b32_e32 v2, s82
; VI-NEXT: v_perm_b32 v9, s53, v9, v1
+; VI-NEXT: v_perm_b32 v3, s16, v2, v1
; VI-NEXT: v_mov_b32_e32 v24, s83
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_mov_b32_e32 v4, s67
+; VI-NEXT: v_perm_b32 v24, s85, v24, v1
+; VI-NEXT: v_or_b32_e32 v3, v3, v9
; VI-NEXT: v_perm_b32 v2, s17, v4, v1
; VI-NEXT: v_mov_b32_e32 v13, s38
+; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v24
; VI-NEXT: v_mov_b32_e32 v4, s47
-; VI-NEXT: v_perm_b32 v24, s85, v24, v1
-; VI-NEXT: v_lshl_or_b32 v3, v9, 16, v3
-; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_perm_b32 v5, s18, v4, v1
; VI-NEXT: v_perm_b32 v13, s81, v13, v1
-; VI-NEXT: v_mov_b32_e32 v25, s80
-; VI-NEXT: v_mov_b32_e32 v26, s68
-; VI-NEXT: v_readlane_b32 s16, v33, 57
-; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v24, 16, v2
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
+; VI-NEXT: v_perm_b32 v5, s18, v4, v1
+; VI-NEXT: v_mov_b32_e32 v25, s80
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
+; VI-NEXT: v_mov_b32_e32 v6, s46
+; VI-NEXT: v_perm_b32 v25, s87, v25, v1
+; VI-NEXT: v_or_b32_e32 v2, v5, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: v_perm_b32 v4, s19, v6, v1
; VI-NEXT: v_mov_b32_e32 v17, s36
-; VI-NEXT: v_mov_b32_e32 v6, s69
-; VI-NEXT: v_mov_b32_e32 v19, s34
-; VI-NEXT: v_perm_b32 v25, s87, v25, v1
-; VI-NEXT: v_perm_b32 v26, s16, v26, v1
-; VI-NEXT: v_readlane_b32 s16, v33, 56
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v13, 16, v5
-; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
-; VI-NEXT: v_mov_b32_e32 v8, s65
-; VI-NEXT: v_perm_b32 v7, s20, v6, v1
-; VI-NEXT: v_mov_b32_e32 v20, s30
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v25
+; VI-NEXT: v_mov_b32_e32 v6, s69
; VI-NEXT: v_perm_b32 v17, s84, v17, v1
-; VI-NEXT: v_perm_b32 v19, s16, v19, v1
-; VI-NEXT: v_readlane_b32 s16, v33, 55
-; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v25, 16, v4
+; VI-NEXT: v_or_b32_e32 v2, v4, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
-; VI-NEXT: v_perm_b32 v6, s21, v8, v1
-; VI-NEXT: v_mov_b32_e32 v8, s55
-; VI-NEXT: v_perm_b32 v20, s16, v20, v1
-; VI-NEXT: v_readlane_b32 s16, v33, 53
+; VI-NEXT: v_perm_b32 v7, s20, v6, v1
+; VI-NEXT: v_mov_b32_e32 v26, s68
+; VI-NEXT: v_readlane_b32 s16, v33, 57
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v17, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; VI-NEXT: v_mov_b32_e32 v8, s65
+; VI-NEXT: v_perm_b32 v26, s16, v26, v1
+; VI-NEXT: v_or_b32_e32 v2, v7, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
-; VI-NEXT: v_mov_b32_e32 v11, s52
+; VI-NEXT: v_perm_b32 v6, s21, v8, v1
+; VI-NEXT: v_mov_b32_e32 v19, s34
+; VI-NEXT: v_readlane_b32 s16, v33, 56
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
+; VI-NEXT: v_mov_b32_e32 v8, s55
+; VI-NEXT: v_perm_b32 v19, s16, v19, v1
+; VI-NEXT: v_or_b32_e32 v2, v6, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
; VI-NEXT: v_perm_b32 v10, s22, v8, v1
; VI-NEXT: v_mov_b32_e32 v27, s71
-; VI-NEXT: v_mov_b32_e32 v28, s16
-; VI-NEXT: v_readlane_b32 s16, v33, 54
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v26, 16, v6
-; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
+; VI-NEXT: v_mov_b32_e32 v11, s52
+; VI-NEXT: v_perm_b32 v27, s70, v27, v1
+; VI-NEXT: v_or_b32_e32 v2, v10, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
; VI-NEXT: v_perm_b32 v8, s23, v11, v1
+; VI-NEXT: v_mov_b32_e32 v20, s30
+; VI-NEXT: v_readlane_b32 s16, v33, 55
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
; VI-NEXT: v_mov_b32_e32 v11, s54
-; VI-NEXT: v_mov_b32_e32 v21, s90
-; VI-NEXT: v_perm_b32 v27, s70, v27, v1
+; VI-NEXT: v_perm_b32 v20, s16, v20, v1
+; VI-NEXT: v_readlane_b32 s16, v33, 53
+; VI-NEXT: v_or_b32_e32 v2, v8, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
+; VI-NEXT: v_perm_b32 v12, s24, v11, v1
+; VI-NEXT: v_mov_b32_e32 v28, s16
+; VI-NEXT: v_readlane_b32 s16, v33, 54
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; VI-NEXT: v_mov_b32_e32 v14, s66
; VI-NEXT: v_perm_b32 v28, s16, v28, v1
+; VI-NEXT: v_or_b32_e32 v2, v12, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
+; VI-NEXT: v_perm_b32 v11, s25, v14, v1
+; VI-NEXT: v_mov_b32_e32 v21, s90
; VI-NEXT: v_readlane_b32 s16, v33, 52
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v19, 16, v10
-; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
-; VI-NEXT: v_mov_b32_e32 v14, s66
-; VI-NEXT: v_perm_b32 v12, s24, v11, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v28
+; VI-NEXT: v_mov_b32_e32 v14, s51
; VI-NEXT: v_perm_b32 v21, s16, v21, v1
; VI-NEXT: v_readlane_b32 s16, v33, 50
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v27, 16, v8
-; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
-; VI-NEXT: v_perm_b32 v11, s25, v14, v1
-; VI-NEXT: v_mov_b32_e32 v14, s51
+; VI-NEXT: v_or_b32_e32 v2, v11, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
+; VI-NEXT: v_perm_b32 v15, s26, v14, v1
; VI-NEXT: v_mov_b32_e32 v29, s16
; VI-NEXT: v_readlane_b32 s16, v33, 51
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v20, 16, v12
-; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
; VI-NEXT: v_mov_b32_e32 v16, s86
-; VI-NEXT: v_perm_b32 v15, s26, v14, v1
-; VI-NEXT: v_mov_b32_e32 v22, s88
; VI-NEXT: v_perm_b32 v29, s16, v29, v1
+; VI-NEXT: v_or_b32_e32 v2, v15, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
+; VI-NEXT: v_perm_b32 v14, s27, v16, v1
+; VI-NEXT: v_mov_b32_e32 v22, s88
; VI-NEXT: v_readlane_b32 s16, v33, 49
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v28, 16, v11
-; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
-; VI-NEXT: v_perm_b32 v14, s27, v16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
; VI-NEXT: v_mov_b32_e32 v16, s50
; VI-NEXT: v_perm_b32 v22, s16, v22, v1
; VI-NEXT: v_readlane_b32 s16, v33, 47
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v21, 16, v15
-; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
-; VI-NEXT: v_mov_b32_e32 v23, s64
+; VI-NEXT: v_or_b32_e32 v2, v14, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
; VI-NEXT: v_perm_b32 v18, s28, v16, v1
; VI-NEXT: v_mov_b32_e32 v30, s16
; VI-NEXT: v_readlane_b32 s16, v33, 48
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v29, 16, v14
-; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
-; VI-NEXT: v_perm_b32 v16, s29, v23, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
+; VI-NEXT: v_mov_b32_e32 v23, s64
; VI-NEXT: v_perm_b32 v30, s16, v30, v1
; VI-NEXT: v_readlane_b32 s16, v33, 46
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v22, 16, v18
+; VI-NEXT: v_or_b32_e32 v2, v18, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, 48, v0
+; VI-NEXT: v_perm_b32 v16, s29, v23, v1
; VI-NEXT: v_mov_b32_e32 v23, s78
; VI-NEXT: v_mov_b32_e32 v31, s16
; VI-NEXT: v_readlane_b32 s16, v33, 45
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v30, 16, v16
-; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
; VI-NEXT: v_perm_b32 v3, s16, v23, v1
+; VI-NEXT: v_or_b32_e32 v2, v16, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, s44, v31, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: v_readlane_b32 s16, v33, 44
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78798,18 +79364,20 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 42
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 43
-; VI-NEXT: v_perm_b32 v2, s45, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s45, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 60, v0
; VI-NEXT: v_readlane_b32 s16, v33, 41
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s76
; VI-NEXT: v_readlane_b32 s16, v33, 40
-; VI-NEXT: v_perm_b32 v2, s42, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s42, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 64, v0
; VI-NEXT: v_readlane_b32 s16, v33, 39
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78817,18 +79385,20 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 37
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 38
-; VI-NEXT: v_perm_b32 v2, s43, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s43, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x44, v0
; VI-NEXT: v_readlane_b32 s16, v33, 36
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v2, s16
; VI-NEXT: v_mov_b32_e32 v3, s74
; VI-NEXT: v_readlane_b32 s16, v33, 35
-; VI-NEXT: v_perm_b32 v2, s40, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s40, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x48, v0
; VI-NEXT: v_readlane_b32 s16, v33, 34
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78836,9 +79406,10 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 32
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 33
-; VI-NEXT: v_perm_b32 v2, s41, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s41, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x4c, v0
; VI-NEXT: v_readlane_b32 s16, v33, 31
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78847,7 +79418,8 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: v_readlane_b32 s14, v33, 30
; VI-NEXT: v_perm_b32 v3, s14, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x50, v0
; VI-NEXT: v_readlane_b32 s14, v33, 29
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78855,9 +79427,10 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s14, v33, 27
; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_readlane_b32 s14, v33, 28
-; VI-NEXT: v_perm_b32 v2, s15, v2, v1
; VI-NEXT: v_perm_b32 v3, s14, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s15, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x54, v0
; VI-NEXT: v_readlane_b32 s14, v33, 26
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78866,7 +79439,8 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s62
; VI-NEXT: v_readlane_b32 s12, v33, 25
; VI-NEXT: v_perm_b32 v3, s12, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x58, v0
; VI-NEXT: v_readlane_b32 s12, v33, 24
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78874,9 +79448,10 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s12, v33, 22
; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_readlane_b32 s12, v33, 23
-; VI-NEXT: v_perm_b32 v2, s13, v2, v1
; VI-NEXT: v_perm_b32 v3, s12, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s13, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x5c, v0
; VI-NEXT: v_readlane_b32 s12, v33, 21
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78885,7 +79460,8 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s60
; VI-NEXT: v_readlane_b32 s10, v33, 20
; VI-NEXT: v_perm_b32 v3, s10, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x60, v0
; VI-NEXT: v_readlane_b32 s10, v33, 19
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78893,9 +79469,10 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s10, v33, 17
; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_readlane_b32 s10, v33, 18
-; VI-NEXT: v_perm_b32 v2, s11, v2, v1
; VI-NEXT: v_perm_b32 v3, s10, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s11, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x64, v0
; VI-NEXT: v_readlane_b32 s10, v33, 16
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78904,7 +79481,8 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s58
; VI-NEXT: v_readlane_b32 s8, v33, 15
; VI-NEXT: v_perm_b32 v3, s8, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x68, v0
; VI-NEXT: v_readlane_b32 s8, v33, 14
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78912,9 +79490,10 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s8, v33, 12
; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_readlane_b32 s8, v33, 13
-; VI-NEXT: v_perm_b32 v2, s9, v2, v1
; VI-NEXT: v_perm_b32 v3, s8, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s9, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x6c, v0
; VI-NEXT: v_readlane_b32 s8, v33, 11
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78923,7 +79502,8 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_readlane_b32 s6, v33, 10
; VI-NEXT: v_perm_b32 v3, s6, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x70, v0
; VI-NEXT: v_readlane_b32 s6, v33, 9
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78931,9 +79511,10 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s6, v33, 7
; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_readlane_b32 s6, v33, 8
-; VI-NEXT: v_perm_b32 v2, s7, v2, v1
; VI-NEXT: v_perm_b32 v3, s6, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s7, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x74, v0
; VI-NEXT: v_readlane_b32 s6, v33, 6
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78943,7 +79524,8 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_readlane_b32 s4, v33, 5
; VI-NEXT: v_perm_b32 v3, s4, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x78, v0
; VI-NEXT: v_readlane_b32 s4, v33, 4
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -78953,7 +79535,8 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; VI-NEXT: v_readlane_b32 s4, v33, 3
; VI-NEXT: v_perm_b32 v2, s5, v2, v1
; VI-NEXT: v_perm_b32 v1, s4, v3, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_readlane_b32 s30, v32, 30
; VI-NEXT: v_readlane_b32 s7, v33, 1
@@ -79545,146 +80128,166 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24
; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24
; GFX9-NEXT: .LBB57_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v2, s85
-; GFX9-NEXT: v_mov_b32_e32 v4, s71
+; GFX9-NEXT: v_mov_b32_e32 v8, s36
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX9-NEXT: v_mov_b32_e32 v21, s52
+; GFX9-NEXT: v_mov_b32_e32 v2, s85
+; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
+; GFX9-NEXT: v_mov_b32_e32 v21, s52
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_mov_b32_e32 v4, s71
+; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v8
; GFX9-NEXT: v_perm_b32 v2, s17, v4, v1
; GFX9-NEXT: v_mov_b32_e32 v11, s34
+; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v21
; GFX9-NEXT: v_mov_b32_e32 v4, s69
-; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
-; GFX9-NEXT: v_mov_b32_e32 v6, s68
-; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
; GFX9-NEXT: v_perm_b32 v11, s54, v11, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
; GFX9-NEXT: v_mov_b32_e32 v22, s48
-; GFX9-NEXT: v_lshl_or_b32 v2, v21, 16, v2
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s68
+; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
; GFX9-NEXT: v_perm_b32 v4, s19, v6, v1
; GFX9-NEXT: v_mov_b32_e32 v14, s30
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; GFX9-NEXT: v_mov_b32_e32 v6, s70
-; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshl_or_b32 v2, v11, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v9, s80
-; GFX9-NEXT: v_perm_b32 v7, s20, v6, v1
; GFX9-NEXT: v_perm_b32 v14, s39, v14, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
+; GFX9-NEXT: v_perm_b32 v7, s20, v6, v1
; GFX9-NEXT: v_mov_b32_e32 v23, s49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: v_lshl_or_b32 v2, v22, 16, v4
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v14
+; GFX9-NEXT: v_mov_b32_e32 v9, s80
+; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v7, v2
; GFX9-NEXT: v_perm_b32 v6, s21, v9, v1
; GFX9-NEXT: v_mov_b32_e32 v15, s94
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v23
; GFX9-NEXT: v_mov_b32_e32 v9, s64
-; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshl_or_b32 v2, v14, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v12, s66
-; GFX9-NEXT: v_perm_b32 v10, s22, v9, v1
; GFX9-NEXT: v_perm_b32 v15, s97, v15, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v6, v2
+; GFX9-NEXT: v_perm_b32 v10, s22, v9, v1
; GFX9-NEXT: v_mov_b32_e32 v24, s98
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: v_lshl_or_b32 v2, v23, 16, v6
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v15
+; GFX9-NEXT: v_mov_b32_e32 v12, s66
+; GFX9-NEXT: v_perm_b32 v24, s87, v24, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v10, v2
; GFX9-NEXT: v_perm_b32 v9, s23, v12, v1
; GFX9-NEXT: v_mov_b32_e32 v16, s92
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v24
; GFX9-NEXT: v_mov_b32_e32 v12, s55
-; GFX9-NEXT: v_perm_b32 v24, s87, v24, v1
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshl_or_b32 v2, v15, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v17, s65
-; GFX9-NEXT: v_perm_b32 v13, s24, v12, v1
; GFX9-NEXT: v_perm_b32 v16, s86, v16, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v9, v2
+; GFX9-NEXT: v_perm_b32 v13, s24, v12, v1
; GFX9-NEXT: v_mov_b32_e32 v25, s84
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: v_lshl_or_b32 v2, v24, 16, v9
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v16
+; GFX9-NEXT: v_mov_b32_e32 v17, s65
+; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v13, v2
; GFX9-NEXT: v_perm_b32 v12, s25, v17, v1
; GFX9-NEXT: v_mov_b32_e32 v17, s90
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v25
; GFX9-NEXT: v_mov_b32_e32 v18, s67
-; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshl_or_b32 v2, v16, 16, v13
-; GFX9-NEXT: v_mov_b32_e32 v8, s36
-; GFX9-NEXT: v_mov_b32_e32 v19, s53
-; GFX9-NEXT: v_perm_b32 v18, s26, v18, v1
; GFX9-NEXT: v_perm_b32 v17, s82, v17, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v12, v2
+; GFX9-NEXT: v_perm_b32 v18, s26, v18, v1
; GFX9-NEXT: v_mov_b32_e32 v26, s81
; GFX9-NEXT: v_readlane_b32 s16, v30, 49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: v_lshl_or_b32 v2, v25, 16, v12
-; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
-; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; GFX9-NEXT: v_mov_b32_e32 v19, s53
; GFX9-NEXT: v_perm_b32 v26, s16, v26, v1
; GFX9-NEXT: v_readlane_b32 s16, v30, 47
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshl_or_b32 v2, v17, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v2, v18, v2
+; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
; GFX9-NEXT: v_mov_b32_e32 v20, s88
-; GFX9-NEXT: v_mov_b32_e32 v27, s83
; GFX9-NEXT: v_mov_b32_e32 v28, s16
-; GFX9-NEXT: v_lshl_or_b32 v3, v8, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 48
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: v_lshl_or_b32 v2, v26, 16, v19
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v26
+; GFX9-NEXT: v_mov_b32_e32 v27, s83
; GFX9-NEXT: v_perm_b32 v3, s16, v20, v1
+; GFX9-NEXT: v_or_b32_e32 v2, v19, v2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_perm_b32 v2, s28, v27, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 45
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 46
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v2, s29, v28, v1
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 44
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s78
; GFX9-NEXT: v_readlane_b32 s16, v30, 43
-; GFX9-NEXT: v_perm_b32 v2, s44, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s44, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 42
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 40
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 41
-; GFX9-NEXT: v_perm_b32 v2, s45, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s45, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 39
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s76
; GFX9-NEXT: v_readlane_b32 s16, v30, 38
-; GFX9-NEXT: v_perm_b32 v2, s42, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s42, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 37
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 35
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 36
-; GFX9-NEXT: v_perm_b32 v2, s43, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s43, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 34
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: v_readlane_b32 s16, v30, 33
-; GFX9-NEXT: v_perm_b32 v2, s40, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s40, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 32
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 30
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 31
-; GFX9-NEXT: v_perm_b32 v2, s41, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s41, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 29
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: v_mov_b32_e32 v2, s16
@@ -79692,16 +80295,18 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: v_readlane_b32 s14, v30, 28
; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s14, v30, 27
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: v_mov_b32_e32 v2, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 25
; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 26
-; GFX9-NEXT: v_perm_b32 v2, s15, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s15, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s14, v30, 24
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: v_mov_b32_e32 v2, s14
@@ -79709,16 +80314,18 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s62
; GFX9-NEXT: v_readlane_b32 s12, v30, 23
; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s12, v30, 22
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: v_mov_b32_e32 v2, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 20
; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 21
-; GFX9-NEXT: v_perm_b32 v2, s13, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s13, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s12, v30, 19
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: v_mov_b32_e32 v2, s12
@@ -79726,16 +80333,18 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s60
; GFX9-NEXT: v_readlane_b32 s10, v30, 18
; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s10, v30, 17
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: v_mov_b32_e32 v2, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 15
; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 16
-; GFX9-NEXT: v_perm_b32 v2, s11, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s11, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s10, v30, 14
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: v_mov_b32_e32 v2, s10
@@ -79743,16 +80352,18 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s58
; GFX9-NEXT: v_readlane_b32 s8, v30, 13
; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s8, v30, 12
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: v_mov_b32_e32 v2, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 10
; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 11
-; GFX9-NEXT: v_perm_b32 v2, s9, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s9, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s8, v30, 9
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: v_mov_b32_e32 v2, s8
@@ -79760,16 +80371,18 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_readlane_b32 s6, v30, 8
; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s6, v30, 7
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 5
; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 6
-; GFX9-NEXT: v_perm_b32 v2, s7, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s7, v2, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s6, v30, 4
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: v_mov_b32_e32 v2, s6
@@ -79777,7 +80390,8 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: v_readlane_b32 s4, v30, 3
; GFX9-NEXT: v_perm_b32 v3, s4, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_readlane_b32 s4, v30, 2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_mov_b32_e32 v2, s4
@@ -79786,7 +80400,8 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_readlane_b32 s4, v30, 1
; GFX9-NEXT: v_perm_b32 v2, s5, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s4, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: v_readlane_b32 s30, v29, 34
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: v_readlane_b32 s31, v29, 35
@@ -80382,65 +80997,70 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: s_lshr_b64 s[42:43], s[4:5], 24
; GFX11-NEXT: .LBB57_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v2, s103, s30, v1
+; GFX11-NEXT: v_readlane_b32 s30, v24, 7
+; GFX11-NEXT: v_readlane_b32 s31, v24, 8
+; GFX11-NEXT: v_readlane_b32 s103, v24, 5
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_perm_b32 v18, s84, s83, v1
; GFX11-NEXT: v_perm_b32 v3, s0, s104, v1
; GFX11-NEXT: v_perm_b32 v4, s1, s102, v1
; GFX11-NEXT: v_perm_b32 v5, s100, s94, v1
+; GFX11-NEXT: v_perm_b32 v19, s81, s80, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-NEXT: v_perm_b32 v6, s2, s101, v1
; GFX11-NEXT: v_perm_b32 v7, s3, s99, v1
-; GFX11-NEXT: v_perm_b32 v18, s84, s83, v1
-; GFX11-NEXT: v_perm_b32 v19, s81, s80, v1
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-NEXT: v_perm_b32 v8, s97, s92, v1
+; GFX11-NEXT: v_or_b32_e32 v3, v4, v18
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v19
+; GFX11-NEXT: v_perm_b32 v11, s86, s90, v1
+; GFX11-NEXT: v_perm_b32 v20, s71, s70, v1
+; GFX11-NEXT: v_perm_b32 v21, s67, s66, v1
+; GFX11-NEXT: v_or_b32_e32 v4, v6, v4
+; GFX11-NEXT: v_or_b32_e32 v5, v7, v5
; GFX11-NEXT: v_perm_b32 v9, s16, s98, v1
; GFX11-NEXT: v_perm_b32 v10, s17, s96, v1
-; GFX11-NEXT: v_perm_b32 v11, s86, s90, v1
; GFX11-NEXT: v_perm_b32 v12, s18, s87, v1
; GFX11-NEXT: v_perm_b32 v13, s19, s85, v1
-; GFX11-NEXT: v_perm_b32 v20, s71, s70, v1
-; GFX11-NEXT: v_perm_b32 v21, s67, s66, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, v2, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v3, v18, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v4, v5, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v5, v19, 16, v7
-; GFX11-NEXT: v_readlane_b32 s0, v25, 6
-; GFX11-NEXT: v_readlane_b32 s1, v25, 4
-; GFX11-NEXT: v_readlane_b32 s30, v24, 7
-; GFX11-NEXT: v_readlane_b32 s31, v24, 8
+; GFX11-NEXT: v_perm_b32 v22, s64, s55, v1
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off
-; GFX11-NEXT: v_lshl_or_b32 v2, v8, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v3, v20, 16, v10
-; GFX11-NEXT: v_lshl_or_b32 v4, v11, 16, v12
-; GFX11-NEXT: v_lshl_or_b32 v5, v21, 16, v13
-; GFX11-NEXT: v_readlane_b32 s104, v24, 6
-; GFX11-NEXT: v_readlane_b32 s103, v24, 5
-; GFX11-NEXT: v_readlane_b32 s102, v24, 4
-; GFX11-NEXT: v_readlane_b32 s101, v24, 3
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:16
-; GFX11-NEXT: v_perm_b32 v5, s50, s72, v1
-; GFX11-NEXT: v_readlane_b32 s100, v24, 2
-; GFX11-NEXT: v_readlane_b32 s99, v24, 1
-; GFX11-NEXT: v_readlane_b32 s98, v24, 0
-; GFX11-NEXT: v_readlane_b32 s97, v23, 31
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-NEXT: v_perm_b32 v8, s48, s39, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v20
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v11
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v21
; GFX11-NEXT: v_perm_b32 v14, s82, s88, v1
+; GFX11-NEXT: v_perm_b32 v17, s21, s65, v1
+; GFX11-NEXT: v_or_b32_e32 v2, v9, v2
+; GFX11-NEXT: v_or_b32_e32 v3, v10, v3
+; GFX11-NEXT: v_or_b32_e32 v4, v12, v4
+; GFX11-NEXT: v_or_b32_e32 v5, v13, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v22
; GFX11-NEXT: v_perm_b32 v15, s69, s78, v1
; GFX11-NEXT: v_perm_b32 v16, s20, s68, v1
-; GFX11-NEXT: v_perm_b32 v17, s21, s65, v1
-; GFX11-NEXT: v_perm_b32 v22, s64, s55, v1
; GFX11-NEXT: v_perm_b32 v6, s53, s52, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v14
+; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:16
+; GFX11-NEXT: v_or_b32_e32 v3, v17, v8
+; GFX11-NEXT: v_perm_b32 v8, s48, s39, v1
; GFX11-NEXT: v_perm_b32 v9, s22, s54, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v15
+; GFX11-NEXT: v_or_b32_e32 v2, v16, v7
+; GFX11-NEXT: v_perm_b32 v5, s50, s72, v1
; GFX11-NEXT: v_perm_b32 v7, s23, s51, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v11, s25, s38, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v2, v14, 16, v16
-; GFX11-NEXT: v_lshl_or_b32 v3, v22, 16, v17
-; GFX11-NEXT: v_lshl_or_b32 v4, v15, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v7
+; GFX11-NEXT: v_readlane_b32 s0, v25, 6
+; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-NEXT: v_or_b32_e32 v7, v11, v8
; GFX11-NEXT: v_perm_b32 v11, s0, s74, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 3
+; GFX11-NEXT: v_readlane_b32 s1, v25, 4
; GFX11-NEXT: v_perm_b32 v9, s24, s49, v1
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:32
; GFX11-NEXT: v_perm_b32 v12, s37, s76, v1
@@ -80449,102 +81069,109 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: v_readlane_b32 s0, v25, 7
; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
; GFX11-NEXT: v_perm_b32 v10, s34, vcc_hi, v1
-; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; GFX11-NEXT: v_perm_b32 v4, s28, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 5
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-NEXT: v_perm_b32 v9, s27, s35, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s29, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 1
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_readlane_b32 s1, v26, 31
; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
-; GFX11-NEXT: v_readlane_b32 s96, v23, 30
; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s62, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 2
+; GFX11-NEXT: v_readlane_b32 s104, v24, 6
; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:48
-; GFX11-NEXT: v_readlane_b32 s87, v23, 29
-; GFX11-NEXT: v_readlane_b32 s86, v23, 28
-; GFX11-NEXT: v_readlane_b32 s85, v23, 27
+; GFX11-NEXT: v_readlane_b32 s102, v24, 4
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
; GFX11-NEXT: v_perm_b32 v4, s40, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 30
-; GFX11-NEXT: v_readlane_b32 s84, v23, 26
-; GFX11-NEXT: v_readlane_b32 s83, v23, 25
-; GFX11-NEXT: v_readlane_b32 s82, v23, 24
-; GFX11-NEXT: v_lshl_or_b32 v4, v12, 16, v4
+; GFX11-NEXT: v_readlane_b32 s101, v24, 3
+; GFX11-NEXT: v_readlane_b32 s100, v24, 2
+; GFX11-NEXT: v_readlane_b32 s99, v24, 1
+; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v25, 0
; GFX11-NEXT: v_readlane_b32 s1, v26, 26
-; GFX11-NEXT: v_readlane_b32 s81, v23, 23
-; GFX11-NEXT: v_readlane_b32 s80, v23, 22
+; GFX11-NEXT: v_readlane_b32 s98, v24, 0
+; GFX11-NEXT: v_readlane_b32 s97, v23, 31
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v10
; GFX11-NEXT: v_perm_b32 v5, s41, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 28
-; GFX11-NEXT: v_readlane_b32 s71, v23, 21
-; GFX11-NEXT: v_readlane_b32 s70, v23, 20
-; GFX11-NEXT: v_readlane_b32 s69, v23, 19
+; GFX11-NEXT: v_readlane_b32 s96, v23, 30
+; GFX11-NEXT: v_readlane_b32 s87, v23, 29
+; GFX11-NEXT: v_readlane_b32 s86, v23, 28
; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-NEXT: v_perm_b32 v11, s0, s60, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 25
-; GFX11-NEXT: v_readlane_b32 s68, v23, 18
-; GFX11-NEXT: v_readlane_b32 s67, v23, 17
+; GFX11-NEXT: v_readlane_b32 s85, v23, 27
+; GFX11-NEXT: v_readlane_b32 s84, v23, 26
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:64
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v11
; GFX11-NEXT: v_perm_b32 v6, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 29
; GFX11-NEXT: v_readlane_b32 s1, v26, 21
-; GFX11-NEXT: v_readlane_b32 s66, v23, 16
-; GFX11-NEXT: v_readlane_b32 s65, v23, 15
+; GFX11-NEXT: v_readlane_b32 s83, v23, 25
+; GFX11-NEXT: v_readlane_b32 s82, v23, 24
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v6
; GFX11-NEXT: v_perm_b32 v8, s14, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 27
-; GFX11-NEXT: v_readlane_b32 s64, v23, 14
-; GFX11-NEXT: v_readlane_b32 s55, v23, 13
-; GFX11-NEXT: v_readlane_b32 s54, v23, 12
+; GFX11-NEXT: v_readlane_b32 s81, v23, 23
+; GFX11-NEXT: v_readlane_b32 s80, v23, 22
+; GFX11-NEXT: v_readlane_b32 s71, v23, 21
; GFX11-NEXT: v_or_b32_e32 v6, v8, v9
; GFX11-NEXT: v_perm_b32 v10, s15, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 23
-; GFX11-NEXT: v_readlane_b32 s53, v23, 11
-; GFX11-NEXT: v_readlane_b32 s52, v23, 10
-; GFX11-NEXT: v_readlane_b32 s51, v23, 9
+; GFX11-NEXT: v_readlane_b32 s70, v23, 20
+; GFX11-NEXT: v_readlane_b32 s69, v23, 19
+; GFX11-NEXT: v_readlane_b32 s68, v23, 18
; GFX11-NEXT: v_or_b32_e32 v7, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s58, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 24
-; GFX11-NEXT: v_readlane_b32 s50, v23, 8
-; GFX11-NEXT: v_readlane_b32 s49, v23, 7
-; GFX11-NEXT: v_readlane_b32 s48, v23, 6
-; GFX11-NEXT: v_readlane_b32 s39, v23, 5
+; GFX11-NEXT: v_readlane_b32 s67, v23, 17
+; GFX11-NEXT: v_readlane_b32 s66, v23, 16
+; GFX11-NEXT: v_readlane_b32 s65, v23, 15
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
; GFX11-NEXT: v_perm_b32 v8, s12, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 20
-; GFX11-NEXT: v_readlane_b32 s38, v23, 4
-; GFX11-NEXT: v_readlane_b32 s37, v23, 3
-; GFX11-NEXT: v_readlane_b32 s36, v23, 2
-; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v8
+; GFX11-NEXT: v_readlane_b32 s64, v23, 14
+; GFX11-NEXT: v_readlane_b32 s55, v23, 13
+; GFX11-NEXT: v_readlane_b32 s54, v23, 12
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 22
; GFX11-NEXT: v_readlane_b32 s1, v26, 16
-; GFX11-NEXT: v_readlane_b32 s35, v23, 1
-; GFX11-NEXT: v_readlane_b32 s34, v23, 0
+; GFX11-NEXT: v_readlane_b32 s53, v23, 11
+; GFX11-NEXT: v_readlane_b32 s52, v23, 10
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; GFX11-NEXT: v_perm_b32 v9, s13, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 18
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readlane_b32 s51, v23, 9
+; GFX11-NEXT: v_readlane_b32 s50, v23, 8
+; GFX11-NEXT: v_readlane_b32 s49, v23, 7
; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
; GFX11-NEXT: v_perm_b32 v11, s0, s56, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 15
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readlane_b32 s48, v23, 6
+; GFX11-NEXT: v_readlane_b32 s39, v23, 5
+; GFX11-NEXT: v_readlane_b32 s38, v23, 4
; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
; GFX11-NEXT: v_perm_b32 v2, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 19
; GFX11-NEXT: v_readlane_b32 s1, v26, 11
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_readlane_b32 s37, v23, 3
+; GFX11-NEXT: v_readlane_b32 s36, v23, 2
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX11-NEXT: v_perm_b32 v4, s10, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 17
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_readlane_b32 s35, v23, 1
+; GFX11-NEXT: v_readlane_b32 s34, v23, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s11, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 13
@@ -80552,45 +81179,53 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
; GFX11-NEXT: v_perm_b32 v12, s0, s46, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 14
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
; GFX11-NEXT: v_perm_b32 v4, s8, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 10
-; GFX11-NEXT: v_lshl_or_b32 v4, v12, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 12
; GFX11-NEXT: v_readlane_b32 s1, v26, 6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v5, s9, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 8
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshl_or_b32 v5, v10, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v5, v5, v10
; GFX11-NEXT: v_perm_b32 v11, s0, s44, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 9
; GFX11-NEXT: v_readlane_b32 s1, v26, 1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v12, s6, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 7
-; GFX11-NEXT: v_lshl_or_b32 v10, v11, 16, v12
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v10, v12, v11
; GFX11-NEXT: v_perm_b32 v14, s7, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_or_b32_e32 v11, v14, v13
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v12, s0, s42, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_perm_b32 v13, s4, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX11-NEXT: v_or_b32_e32 v12, v13, v12
; GFX11-NEXT: v_perm_b32 v13, s1, s0, v1
; GFX11-NEXT: v_readlane_b32 s0, v26, 2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-NEXT: v_perm_b32 v1, s5, s0, v1
-; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v13, v1, v13
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:80
; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:96
@@ -82593,12 +83228,19 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v33, v62, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v63, v60, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v53, v58, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v51, v56, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v45, v44, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v49, v48, s6
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr62
; VI-NEXT: ; implicit-def: $vgpr63
@@ -82619,18 +83261,21 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v16, v17, v16, s6
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82639,7 +83284,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82648,7 +83294,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82657,7 +83304,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82666,7 +83314,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82675,7 +83324,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82683,23 +83333,24 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v41, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v55, v34, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v61, v32, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v59, v54, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v57, v52, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v47, v38, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v35, v46, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_perm_b32 v14, v43, v50, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: v_perm_b32 v15, v39, v42, s6
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr41
@@ -82724,7 +83375,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
-; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82733,7 +83385,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
-; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; VI-NEXT: v_or_b32_e32 v17, v17, v18
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82742,7 +83395,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82751,7 +83405,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82760,7 +83415,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82769,7 +83425,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82778,7 +83435,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s6
-; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v22, v23
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82787,7 +83445,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82796,7 +83455,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s6
-; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v24, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82805,7 +83465,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v25, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82814,7 +83475,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v26, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82823,7 +83485,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82832,7 +83495,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v28, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82841,7 +83505,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82850,7 +83515,8 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v30, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -82923,9 +83589,10 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
+; VI-NEXT: v_or_b32_e32 v31, v31, v32
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
@@ -86127,18 +86794,18 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
@@ -86161,28 +86828,28 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -86197,16 +86864,18 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
@@ -86225,27 +86894,28 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
@@ -86260,12 +86930,13 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
@@ -86288,27 +86959,28 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
@@ -86323,12 +86995,13 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v18, 16, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
@@ -86351,27 +87024,28 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
@@ -86386,12 +87060,13 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
@@ -86414,27 +87089,28 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
@@ -86449,11 +87125,12 @@ define <16 x i64> @bitcast_v128i8_to_v16i64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
@@ -87975,103 +88652,127 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB59_2
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s73
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s73
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s61
+; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s61
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s57
+; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s57
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s45
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s45
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s41
+; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s13
+; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s13
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s9
+; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s9
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s6, v15, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v14, v13, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s6, v15, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v52, v51, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v54, v53, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v48, v39, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v50, v49, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v36, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v38, v37, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v32, v16, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_perm_b32 v16, v60, v17, s4
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: v_perm_b32 v17, v62, v61, s4
-; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_perm_b32 v17, v59, v18, s4
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: v_perm_b32 v18, v41, v40, s4
-; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v18
+; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_perm_b32 v18, v57, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v19, v42, v58, s4
-; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_perm_b32 v19, v45, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: v_perm_b32 v20, v56, v47, s4
-; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_perm_b32 v20, v44, v21, s4
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: v_perm_b32 v21, v46, v26, s4
-; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_perm_b32 v21, v31, v22, s4
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: v_perm_b32 v22, v24, v43, s4
-; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_perm_b32 v22, v28, v23, s4
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; VI-NEXT: v_perm_b32 v23, v30, v29, s4
-; VI-NEXT: v_mov_b32_e32 v44, v24
-; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_perm_b32 v23, v25, v63, s4
+; VI-NEXT: v_mov_b32_e32 v44, v24
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; VI-NEXT: v_perm_b32 v24, v27, v55, s4
-; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v45, v26
@@ -88081,72 +88782,80 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v24, v25, v24, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
-; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
-; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
-; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
-; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v29, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
-; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v30, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
-; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v31, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v43, v46, v43, s4
-; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; VI-NEXT: v_or_b32_e32 v31, v43, v31
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB59_3
; VI-NEXT: .LBB59_2:
@@ -88867,103 +89576,127 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB59_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
-; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s73
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s73
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s61
+; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s61
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s57
+; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s57
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s45
+; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s45
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s41
+; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s41
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
-; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s13
+; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v9, s13
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s9
+; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_mov_b32_e32 v10, s9
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
+; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
+; GFX9-NEXT: v_mov_b32_e32 v44, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v45, v26
@@ -88973,72 +89706,80 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB59_3
; GFX9-NEXT: .LBB59_2:
@@ -89578,49 +90319,56 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -89712,132 +90460,143 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB59_3
; GFX11-TRUE16-NEXT: .LBB59_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v11, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -90134,49 +90893,56 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -90268,132 +91034,143 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB59_3
; GFX11-FAKE16-NEXT: .LBB59_2: ; %cmp.true
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -106748,31 +107525,37 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v55, v55, v41, s4
; VI-NEXT: v_perm_b32 v1, v1, v47, s4
-; VI-NEXT: v_lshl_or_b32 v1, v55, 16, v1
; VI-NEXT: v_perm_b32 v2, v2, v54, s4
+; VI-NEXT: v_lshlrev_b32_e32 v54, 16, v55
+; VI-NEXT: v_or_b32_e32 v1, v1, v54
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v48, v46, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v53, v40, s4
; VI-NEXT: v_perm_b32 v2, v3, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v34, s4
; VI-NEXT: v_perm_b32 v2, v44, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v52, v39, s4
; VI-NEXT: v_perm_b32 v2, v5, v43, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v63, s4
; VI-NEXT: v_perm_b32 v2, v62, v37, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v63, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
@@ -106780,12 +107563,14 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v7, v51, s4
; VI-NEXT: v_perm_b32 v1, v33, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v61, s4
; VI-NEXT: v_perm_b32 v2, v60, v59, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v61, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -106793,12 +107578,14 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v50, s4
; VI-NEXT: v_perm_b32 v1, v36, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v58, s4
; VI-NEXT: v_perm_b32 v2, v35, v49, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v58, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
@@ -106807,17 +107594,19 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: v_perm_b32 v2, v11, v57, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v12, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v12, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -106826,19 +107615,21 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v14, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
@@ -106847,19 +107638,21 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v16, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
@@ -106868,19 +107661,21 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v18, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
@@ -106889,19 +107684,21 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v20, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -106912,17 +107709,19 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v22, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
@@ -106932,17 +107731,19 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v23, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v24, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v24, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
@@ -106952,28 +107753,30 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v26, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v26, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v27, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v27, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
@@ -106982,39 +107785,41 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v28, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v56, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v29, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v29, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v30, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v30, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v31, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -107024,7 +107829,8 @@ define <128 x i8> @bitcast_v16f64_to_v128i8(<16 x double> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v32, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v42, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -111067,11 +111873,13 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v41, v45, v42, s4
; VI-NEXT: v_perm_b32 v31, v31, v46, s4
-; VI-NEXT: v_lshl_or_b32 v31, v41, 16, v31
; VI-NEXT: v_perm_b32 v32, v32, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v36, 16, v41
+; VI-NEXT: v_or_b32_e32 v31, v31, v36
; VI-NEXT: buffer_store_dword v31, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v31, v55, v61, s4
-; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v32
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v31, v32, v31
; VI-NEXT: v_add_u32_e32 v32, vcc, 4, v0
; VI-NEXT: buffer_store_dword v31, v32, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
@@ -111112,24 +111920,28 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
-; VI-NEXT: v_lshl_or_b32 v29, v31, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v29, v29, v31
; VI-NEXT: v_add_u32_e32 v31, vcc, 8, v0
; VI-NEXT: buffer_store_dword v29, v31, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v29, v30, v60, s4
; VI-NEXT: v_perm_b32 v30, v40, v59, s4
-; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: v_add_u32_e32 v30, vcc, 12, v0
; VI-NEXT: buffer_store_dword v29, v30, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v29, v50, v29, s4
-; VI-NEXT: v_lshl_or_b32 v27, v29, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v27, v27, v29
; VI-NEXT: v_add_u32_e32 v29, vcc, 16, v0
; VI-NEXT: buffer_store_dword v27, v29, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v27, v28, v49, s4
; VI-NEXT: v_perm_b32 v28, v58, v39, s4
-; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: v_add_u32_e32 v28, vcc, 20, v0
; VI-NEXT: buffer_store_dword v27, v28, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
@@ -111138,14 +111950,16 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v25, v28, s4
-; VI-NEXT: v_lshl_or_b32 v25, v27, 16, v25
+; VI-NEXT: v_or_b32_e32 v25, v25, v27
; VI-NEXT: v_add_u32_e32 v27, vcc, 24, v0
; VI-NEXT: buffer_store_dword v25, v27, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v25, v26, v35, s4
; VI-NEXT: v_perm_b32 v26, v57, v54, s4
-; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v25, v26
; VI-NEXT: v_add_u32_e32 v26, vcc, 28, v0
; VI-NEXT: buffer_store_dword v25, v26, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -111154,14 +111968,16 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v23, v26, s4
-; VI-NEXT: v_lshl_or_b32 v23, v25, 16, v23
+; VI-NEXT: v_or_b32_e32 v23, v23, v25
; VI-NEXT: v_add_u32_e32 v25, vcc, 32, v0
; VI-NEXT: buffer_store_dword v23, v25, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v23, v24, v48, s4
; VI-NEXT: v_perm_b32 v24, v56, v34, s4
-; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: v_add_u32_e32 v24, vcc, 36, v0
; VI-NEXT: buffer_store_dword v23, v24, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
@@ -111170,14 +111986,16 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s4
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v21, v24, s4
-; VI-NEXT: v_lshl_or_b32 v21, v23, 16, v21
+; VI-NEXT: v_or_b32_e32 v21, v21, v23
; VI-NEXT: v_add_u32_e32 v23, vcc, 40, v0
; VI-NEXT: buffer_store_dword v21, v23, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v21, v22, v47, s4
; VI-NEXT: v_perm_b32 v22, v38, v53, s4
-; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: v_add_u32_e32 v22, vcc, 44, v0
; VI-NEXT: buffer_store_dword v21, v22, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
@@ -111186,14 +112004,16 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s4
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v19, v22, s4
-; VI-NEXT: v_lshl_or_b32 v19, v21, 16, v19
+; VI-NEXT: v_or_b32_e32 v19, v19, v21
; VI-NEXT: v_add_u32_e32 v21, vcc, 48, v0
; VI-NEXT: buffer_store_dword v19, v21, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v19, v20, v52, s4
; VI-NEXT: v_perm_b32 v20, v37, v51, s4
-; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: v_add_u32_e32 v20, vcc, 52, v0
; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
@@ -111202,9 +112022,10 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s4
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v17, v20, s4
-; VI-NEXT: v_lshl_or_b32 v17, v19, 16, v17
+; VI-NEXT: v_or_b32_e32 v17, v17, v19
; VI-NEXT: v_add_u32_e32 v19, vcc, 56, v0
; VI-NEXT: buffer_store_dword v17, v19, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
@@ -111214,7 +112035,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s4
-; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; VI-NEXT: v_or_b32_e32 v17, v17, v18
; VI-NEXT: v_add_u32_e32 v18, vcc, 60, v0
; VI-NEXT: buffer_store_dword v17, v18, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
@@ -111223,9 +112045,10 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s4
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v15, v18, s4
-; VI-NEXT: v_lshl_or_b32 v15, v17, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v17
; VI-NEXT: v_add_u32_e32 v17, vcc, 64, v0
; VI-NEXT: buffer_store_dword v15, v17, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
@@ -111235,7 +112058,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v16, v17, v16, s4
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: v_add_u32_e32 v16, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
@@ -111244,9 +112068,10 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s4
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v11, v11, v16, s4
-; VI-NEXT: v_lshl_or_b32 v11, v15, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v15
; VI-NEXT: v_add_u32_e32 v15, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v11, v15, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -111256,7 +112081,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v12, v15, v12, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_add_u32_e32 v12, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -111267,7 +112093,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v11, v11, v15, s4
-; VI-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v11
; VI-NEXT: v_add_u32_e32 v11, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v9, v11, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
@@ -111277,7 +112104,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v10, v11, v10, s4
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_add_u32_e32 v10, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -111288,7 +112116,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v9, v9, v10, s4
-; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_u32_e32 v9, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
@@ -111298,7 +112127,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v9, v8, s4
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_add_u32_e32 v8, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
@@ -111309,7 +112139,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v7, v7, v8, s4
-; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
@@ -111319,7 +112150,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s4
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
@@ -111330,7 +112162,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v5, v5, v6, s4
-; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v3, v3, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
@@ -111340,7 +112173,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s4
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -111351,7 +112185,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v3, v3, v4, s4
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
@@ -111361,29 +112196,31 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_perm_b32 v1, v13, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v13, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v14, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -112292,12 +113129,14 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v48, v48, v60, s4
-; GFX9-NEXT: v_perm_b32 v37, v37, v44, s4
; GFX9-NEXT: v_perm_b32 v25, v41, v25, s4
-; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v37
+; GFX9-NEXT: v_perm_b32 v37, v37, v44, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX9-NEXT: v_or_b32_e32 v25, v37, v25
; GFX9-NEXT: v_perm_b32 v26, v26, v42, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: v_perm_b32 v38, v38, v40, s4
-; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v39
+; GFX9-NEXT: v_or_b32_e32 v26, v39, v26
; GFX9-NEXT: v_perm_b32 v24, v24, v58, s4
; GFX9-NEXT: v_perm_b32 v22, v22, v55, s4
; GFX9-NEXT: v_readlane_b32 s30, v63, 34
@@ -112347,7 +113186,6 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_perm_b32 v45, v59, v52, s4
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshl_or_b32 v48, v45, 16, v48
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v35, v15, v19, s4
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
@@ -112357,7 +113195,6 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_perm_b32 v56, v56, v59, s4
; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshl_or_b32 v38, v56, 16, v38
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_perm_b32 v19, v51, v19, s4
; GFX9-NEXT: v_perm_b32 v32, v32, v15, s4
@@ -112399,67 +113236,86 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v15, v15, v51, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v45
; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshl_or_b32 v25, v27, 16, v34
-; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: v_perm_b32 v25, v47, v54, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v27
+; GFX9-NEXT: v_or_b32_e32 v48, v48, v51
+; GFX9-NEXT: v_or_b32_e32 v25, v34, v25
; GFX9-NEXT: buffer_store_dword v48, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v48, v43, v61, s4
-; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v30
-; GFX9-NEXT: v_lshl_or_b32 v48, v48, 16, v49
+; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: v_perm_b32 v25, v47, v54, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v48
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX9-NEXT: v_or_b32_e32 v48, v49, v48
+; GFX9-NEXT: v_or_b32_e32 v25, v30, v25
+; GFX9-NEXT: buffer_store_dword v48, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v56
; GFX9-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshl_or_b32 v26, v40, 16, v36
+; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v40
; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshl_or_b32 v25, v35, 16, v32
-; GFX9-NEXT: buffer_store_dword v48, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v35
+; GFX9-NEXT: v_or_b32_e32 v38, v38, v48
+; GFX9-NEXT: v_or_b32_e32 v26, v36, v26
+; GFX9-NEXT: v_or_b32_e32 v25, v32, v25
; GFX9-NEXT: buffer_store_dword v38, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v31, v25, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v25, 16, v16
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX9-NEXT: v_or_b32_e32 v16, v16, v25
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshl_or_b32 v16, v19, 16, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19
+; GFX9-NEXT: v_or_b32_e32 v16, v20, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v19, v16, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v28
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v28, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshl_or_b32 v16, v29, 16, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29
+; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v19, v16, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v24, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshl_or_b32 v16, v33, 16, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v33
+; GFX9-NEXT: v_or_b32_e32 v16, v21, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v19, v16, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshl_or_b32 v16, v50, 16, v17
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v50
+; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v17, v16, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v18
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v18, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v15, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112468,7 +113324,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112478,7 +113335,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v13, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v13
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112487,7 +113345,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v13, v10, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112497,7 +113356,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112506,7 +113366,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112516,7 +113377,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v7, v7, v8, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112525,7 +113387,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112535,7 +113398,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v5, v6, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112544,7 +113408,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112554,7 +113419,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v3, v4, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -112563,27 +113429,28 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v1, v11, v1, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v57, v2, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, v11, v1, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v1, v12, v1, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v1, v12, v1, s4
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -113266,108 +114133,135 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_perm_b32 v69, v41, v69, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v48, v48, v42, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v49, v49, v73, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v70, v72, v63, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v68, v181, v68, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v181, v62, v60, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX11-NEXT: v_perm_b32 v49, v49, v73, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX11-NEXT: v_perm_b32 v35, v35, v180, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v60, v69, 16, v48
+; GFX11-NEXT: v_lshlrev_b32_e32 v180, 16, v181
+; GFX11-NEXT: v_or_b32_e32 v60, v48, v69
; GFX11-NEXT: v_perm_b32 v48, v178, v67, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v35, v35, v180, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v61, v70, 16, v49
-; GFX11-NEXT: v_lshl_or_b32 v63, v181, 16, v36
+; GFX11-NEXT: v_or_b32_e32 v61, v49, v70
; GFX11-NEXT: v_perm_b32 v49, v56, v46, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v63, v36, v180
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v48
; GFX11-NEXT: v_perm_b32 v48, v166, v66, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v62, v68, 16, v35
-; GFX11-NEXT: v_perm_b32 v35, v59, v58, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v31, v31, v177, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v27, v27, v165, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v48
; GFX11-NEXT: v_perm_b32 v28, v28, v47, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v49, 16, v49
-; GFX11-NEXT: v_perm_b32 v32, v32, v57, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v35
+; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v48
+; GFX11-NEXT: v_or_b32_e32 v62, v35, v68
+; GFX11-NEXT: v_perm_b32 v35, v59, v58, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v66, v31, v36
+; GFX11-NEXT: v_or_b32_e32 v69, v28, v49
; GFX11-NEXT: v_or_b32_e32 v68, v27, v48
; GFX11-NEXT: v_perm_b32 v27, v161, v65, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v69, v28, v49
; GFX11-NEXT: v_perm_b32 v28, v45, v44, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v23, v160, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v31, v151, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v32, v57, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v35
+; GFX11-NEXT: v_perm_b32 v23, v23, v160, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX11-NEXT: v_perm_b32 v24, v24, v43, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-NEXT: v_perm_b32 v21, v21, v149, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX11-NEXT: v_or_b32_e32 v67, v32, v35
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_store_b128 v0, v[60:63], off
; GFX11-NEXT: scratch_store_b128 v0, v[66:69], off offset:16
-; GFX11-NEXT: v_lshl_or_b32 v64, v27, 16, v23
+; GFX11-NEXT: v_or_b32_e32 v64, v23, v27
; GFX11-NEXT: v_perm_b32 v23, v40, v182, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v65, v28, 16, v24
-; GFX11-NEXT: v_lshl_or_b32 v66, v31, 16, v21
+; GFX11-NEXT: v_or_b32_e32 v65, v24, v28
+; GFX11-NEXT: v_or_b32_e32 v66, v21, v31
; GFX11-NEXT: v_perm_b32 v21, v22, v183, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v146, v54, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v179, v176, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v19, v19, v135, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v27, v133, v53, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_perm_b32 v19, v19, v135, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v20, v20, v167, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v17, v17, v132, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v67, v23, 16, v21
-; GFX11-NEXT: v_lshl_or_b32 v19, v22, 16, v19
+; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-NEXT: v_or_b32_e32 v67, v21, v23
+; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
; GFX11-NEXT: v_perm_b32 v22, v164, v162, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v20, v24, 16, v20
-; GFX11-NEXT: v_lshl_or_b32 v21, v27, 16, v17
+; GFX11-NEXT: v_or_b32_e32 v20, v20, v24
+; GFX11-NEXT: v_or_b32_e32 v21, v17, v27
; GFX11-NEXT: v_perm_b32 v17, v18, v163, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v128, v52, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v15, v119, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v118, v51, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v117, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v150, v148, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-NEXT: v_perm_b32 v15, v15, v119, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v13, v13, v117, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v16, v16, v147, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v22, v22, 16, v17
-; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
+; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
; GFX11-NEXT: v_perm_b32 v18, v145, v134, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v17, v24, 16, v13
-; GFX11-NEXT: v_perm_b32 v13, v14, v144, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v17, v13, v24
; GFX11-NEXT: v_perm_b32 v24, v100, v38, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v9, v99, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v16, v23, 16, v16
+; GFX11-NEXT: v_or_b32_e32 v16, v16, v23
+; GFX11-NEXT: v_perm_b32 v13, v14, v144, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v14, v113, v50, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v131, v130, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v9, v9, v99, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v11, v11, v112, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v129, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v13
-; GFX11-NEXT: v_lshl_or_b32 v13, v24, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
+; GFX11-NEXT: v_or_b32_e32 v13, v9, v24
; GFX11-NEXT: v_perm_b32 v9, v10, v115, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v96, v37, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v87, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
+; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
; GFX11-NEXT: v_perm_b32 v14, v116, v114, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v12, v23, 16, v12
+; GFX11-NEXT: v_or_b32_e32 v12, v12, v23
; GFX11-NEXT: v_perm_b32 v23, v103, v102, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v85, v33, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v87, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v101, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v5, v5, v84, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
; GFX11-NEXT: v_perm_b32 v10, v98, v97, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v86, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v8, v23, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v9, v24, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v23
+; GFX11-NEXT: v_or_b32_e32 v9, v5, v24
; GFX11-NEXT: v_perm_b32 v5, v80, v29, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v3, v3, v71, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v83, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v30, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v4, v4, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v25, v55, v39, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v6, v86, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v3, v3, v71, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, v4, v81, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v26, v1, v26, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v27, v2, v34, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v23, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v3, v24, 16, v26
-; GFX11-NEXT: v_lshl_or_b32 v4, v25, 16, v27
+; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v23
+; GFX11-NEXT: v_or_b32_e32 v3, v26, v24
+; GFX11-NEXT: v_or_b32_e32 v4, v27, v25
; GFX11-NEXT: s_clause 0x5
; GFX11-NEXT: scratch_store_b128 v0, v[64:67], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
@@ -115295,12 +116189,19 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v33, v62, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v63, v60, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v53, v58, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v51, v56, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v45, v44, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v49, v48, s6
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr62
; VI-NEXT: ; implicit-def: $vgpr63
@@ -115321,18 +116222,21 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v16, v17, v16, s6
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:776 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:744 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115341,7 +116245,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:728 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:712 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115350,7 +116255,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115359,7 +116265,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115368,7 +116275,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115377,7 +116285,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115385,23 +116294,24 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v41, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v55, v34, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v61, v32, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v59, v54, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v57, v52, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v47, v38, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v35, v46, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_perm_b32 v14, v43, v50, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: v_perm_b32 v15, v39, v42, s6
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr41
@@ -115426,7 +116336,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
-; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115435,7 +116346,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
-; VI-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; VI-NEXT: v_or_b32_e32 v17, v17, v18
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:760 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:768 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115444,7 +116356,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115453,7 +116366,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115462,7 +116376,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115471,7 +116386,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115480,7 +116396,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v24, v23, s6
-; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v22, v23
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115489,7 +116406,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115498,7 +116416,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s6
-; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v24, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115507,7 +116426,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v25, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115516,7 +116436,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v26, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115525,7 +116446,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115534,7 +116456,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v28, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115543,7 +116466,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115552,7 +116476,8 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v30, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -115625,9 +116550,10 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr40
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
-; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
+; VI-NEXT: v_or_b32_e32 v31, v31, v32
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr40
; VI-NEXT: ; implicit-def: $vgpr40
@@ -118829,18 +119755,18 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v70, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v67
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v68
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v66, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v54, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v65, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v2
@@ -118863,28 +119789,28 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v52, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v51
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v50, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v49, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v48
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, v38, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v37, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v9, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v36
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v35
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
@@ -118899,16 +119825,18 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v33, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v127
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v126, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v125, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v10, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v11, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v124
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v123
@@ -118927,27 +119855,28 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v120, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v111
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v110, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v109, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v107
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v13
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v108
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v106, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, v105, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v104
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v95
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v9
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
@@ -118962,12 +119891,13 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v93, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v92
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v91
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v90, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v13, v89, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v16, v12
@@ -118990,27 +119920,28 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v76, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, 0x300, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v17
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v17, 8, v75
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v74, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v73, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v63
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v18
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v18, 8, v72
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, v62, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, v61, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v16, 0x300, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v18, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xff, v20
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v19, 8, v60
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xff, v21
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v59
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v15
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, 0x300, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
@@ -119025,12 +119956,13 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v17, v57, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v20, 8, v56
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v21, 8, v47
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v46, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v18, 16, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v16, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v18, v45, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v20, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v21, v17
@@ -119053,27 +119985,28 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v40, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v17
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v20, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xff, v22
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v22, 8, v183
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v182, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v18
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, v181, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v179
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v22, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v23, 8, v180
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xff, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, v178, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, v177, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v21, 0x300, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v22
; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v24, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xff, v25
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v24, 8, v176
; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xff, v26
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v167
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, 0x300, v22
; GFX11-FAKE16-NEXT: v_add_nc_u16 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
@@ -119088,12 +120021,13 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v22, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v22, v165, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v25, 8, v164
; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xff, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v26, 8, v163
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v162, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v21, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v23, v161, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v24
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v26, v22
@@ -119116,27 +120050,28 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v148, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v24, v22
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v25, 0x300, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v27
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v27, 8, v147
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v146, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v24, v23
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, v145, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v135
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v26
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v28
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v28, 8, v144
; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v134, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v31, v133, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v26, 0x300, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v28, v27
; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v29, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v30
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v29, 8, v132
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v31
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v131
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v25, 0xffff, v25
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, 0x300, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v24, 0x300, v24
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
@@ -119151,11 +120086,12 @@ define <16 x double> @bitcast_v128i8_to_v16f64(<128 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v30
; GFX11-FAKE16-NEXT: v_add_nc_u16 v27, v129, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xff, v29
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v30, 8, v128
; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v27
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v26
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v31, 8, v119
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v26, v28
; GFX11-FAKE16-NEXT: v_add_nc_u16 v28, v118, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v30, v29
; GFX11-FAKE16-NEXT: v_add_nc_u16 v30, v117, 3
@@ -120677,103 +121613,127 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB75_2
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s73
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s73
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s61
+; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s61
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s57
+; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s57
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s45
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s45
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s41
+; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s13
+; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s13
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s9
+; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s9
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s6, v15, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v14, v13, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s6, v15, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v52, v51, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v54, v53, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v48, v39, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v50, v49, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v36, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v38, v37, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v32, v16, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_perm_b32 v16, v60, v17, s4
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: v_perm_b32 v17, v62, v61, s4
-; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v17, v16
; VI-NEXT: v_perm_b32 v17, v59, v18, s4
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; VI-NEXT: v_perm_b32 v18, v41, v40, s4
-; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v18
+; VI-NEXT: v_or_b32_e32 v17, v18, v17
; VI-NEXT: v_perm_b32 v18, v57, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v19, v42, v58, s4
-; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_perm_b32 v19, v45, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: v_perm_b32 v20, v56, v47, s4
-; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_perm_b32 v20, v44, v21, s4
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: v_perm_b32 v21, v46, v26, s4
-; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_perm_b32 v21, v31, v22, s4
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; VI-NEXT: v_perm_b32 v22, v24, v43, s4
-; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_perm_b32 v22, v28, v23, s4
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; VI-NEXT: v_perm_b32 v23, v30, v29, s4
-; VI-NEXT: v_mov_b32_e32 v44, v24
-; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_perm_b32 v23, v25, v63, s4
+; VI-NEXT: v_mov_b32_e32 v44, v24
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; VI-NEXT: v_perm_b32 v24, v27, v55, s4
-; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v45, v26
@@ -120783,72 +121743,80 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; VI-NEXT: v_perm_b32 v24, v25, v24, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
-; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
-; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s4
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
-; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
-; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v29, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s4
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
-; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v30, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
-; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v31, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v43, v31, s4
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v43, v46, v43, s4
-; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; VI-NEXT: v_or_b32_e32 v31, v43, v31
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: s_branch .LBB75_3
; VI-NEXT: .LBB75_2:
@@ -121569,103 +122537,127 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB75_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
-; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s73
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s73
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s61
+; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s61
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s57
+; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s57
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s45
+; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s45
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s41
+; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s41
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
-; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s13
+; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v9, s13
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s9
+; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_mov_b32_e32 v10, s9
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
+; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
+; GFX9-NEXT: v_mov_b32_e32 v44, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v45, v26
@@ -121675,72 +122667,80 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB75_3
; GFX9-NEXT: .LBB75_2:
@@ -122280,49 +123280,56 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -122414,132 +123421,143 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB75_3
; GFX11-TRUE16-NEXT: .LBB75_2: ; %cmp.true
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s22, s23, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: s_add_i32 s58, s58, 3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-TRUE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v11, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -122836,49 +123854,56 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v8, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v11, 16, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
@@ -122970,132 +123995,143 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB75_3
; GFX11-FAKE16-NEXT: .LBB75_2: ; %cmp.true
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s0, s0, 3
; GFX11-FAKE16-NEXT: s_add_i32 s16, s16, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-FAKE16-NEXT: s_add_i32 s18, s18, 3
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-FAKE16-NEXT: s_add_i32 s28, s28, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_add_i32 s72, s72, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
-; GFX11-FAKE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s62, s62, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s22, s23, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: s_add_i32 s60, s60, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: s_add_i32 s58, s58, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-FAKE16-NEXT: s_add_i32 s46, s46, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: s_add_i32 s44, s44, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
-; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
; GFX11-FAKE16-NEXT: s_add_i32 s42, s42, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: s_add_i32 s40, s40, 3
; GFX11-FAKE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: s_add_i32 s10, s10, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-FAKE16-NEXT: s_add_i32 s6, s6, 3
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 3, v167
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 3, v165
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_add_i32 s4, s4, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v13, v177, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v14, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v19
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
@@ -140167,12 +141203,19 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v10, v37, v36, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v59, v34, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v57, v32, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v47, v46, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v43, v42, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v55, v54, s6
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v51, v50, s6
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr59
@@ -140194,14 +141237,16 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140210,7 +141255,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140219,7 +141265,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140228,7 +141275,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140237,7 +141285,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140246,7 +141295,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140255,22 +141305,24 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v9, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_perm_b32 v8, v38, v61, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_perm_b32 v9, v39, v62, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, v38, v61, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v35, v60, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v33, v58, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v63, v56, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v45, v44, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v41, v40, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_perm_b32 v14, v53, v52, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr61
@@ -140289,7 +141341,7 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v49, v15, s6
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr49
@@ -140301,14 +141353,16 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v17, v18, v19
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140317,7 +141371,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140326,7 +141381,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140335,7 +141391,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140344,7 +141401,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140353,7 +141411,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v23, v24, s6
-; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v22, v23
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140362,7 +141421,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140371,7 +141431,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v25, v26, s6
-; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v24, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140380,7 +141441,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v25, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140389,7 +141451,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v26, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140398,7 +141461,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140407,7 +141471,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v28, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140416,7 +141481,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -140425,7 +141491,8 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v30, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
@@ -140490,13 +141557,14 @@ define <64 x bfloat> @bitcast_v128i8_to_v64bf16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: ; kill: killed $vgpr48
-; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v32, v33, v32, s6
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; VI-NEXT: ; kill: killed $vgpr48
+; VI-NEXT: ; implicit-def: $vgpr48
+; VI-NEXT: v_or_b32_e32 v31, v31, v32
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
@@ -145902,70 +146970,82 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB89_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s19
+; VI-NEXT: v_mov_b32_e32 v3, s23
+; VI-NEXT: v_mov_b32_e32 v0, s17
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_mov_b32_e32 v3, s23
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s8, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s7
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s10
-; VI-NEXT: v_perm_b32 v4, s11, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_perm_b32 v5, s14, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s13
+; VI-NEXT: v_perm_b32 v4, s11, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s41
-; VI-NEXT: v_perm_b32 v5, s42, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s13
; VI-NEXT: v_perm_b32 v6, s46, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s45
+; VI-NEXT: v_perm_b32 v5, s42, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s57
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s45
; VI-NEXT: v_perm_b32 v7, s63, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s62
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s61
-; VI-NEXT: v_perm_b32 v7, s74, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s62
; VI-NEXT: v_perm_b32 v8, s73, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s9
+; VI-NEXT: v_perm_b32 v7, s74, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s12
-; VI-NEXT: v_perm_b32 v8, s76, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s9
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
+; VI-NEXT: v_perm_b32 v8, s76, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v43, v10
; VI-NEXT: v_mov_b32_e32 v10, s43
-; VI-NEXT: v_perm_b32 v9, s44, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v10, s56, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s47
+; VI-NEXT: v_perm_b32 v9, s44, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v35, v12
; VI-NEXT: v_mov_b32_e32 v12, s59
-; VI-NEXT: v_perm_b32 v10, s60, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s47
; VI-NEXT: v_perm_b32 v12, s72, v12, v11
+; VI-NEXT: v_perm_b32 v10, s60, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s75, v13, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v15, v14, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s75, v13, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
@@ -145974,22 +147054,26 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: v_perm_b32 v23, v51, v33, s4
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v12, v56, v12, s4
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v14, v59, v14, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v13, v47, v13, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v14, v59, v14, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v15, v32, v15, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v61, v13, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v17, v60, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v21, v16, s4
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v17, v28, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v21, v58, v46, s4
; VI-NEXT: v_perm_b32 v24, v36, v49, s4
; VI-NEXT: v_mov_b32_e32 v28, v52
@@ -145997,36 +147081,44 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v16, v19, v16, s4
; VI-NEXT: v_perm_b32 v19, v26, v22, s4
-; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v19
+; VI-NEXT: v_or_b32_e32 v17, v19, v17
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_perm_b32 v16, v25, v20, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v16, v18, v16
; VI-NEXT: v_perm_b32 v18, v45, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v20, v44, v29, s4
; VI-NEXT: v_perm_b32 v22, v53, v42, s4
; VI-NEXT: v_mov_b32_e32 v45, v34
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v19, v30, v19, s4
-; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_perm_b32 v19, v55, v31, s4
-; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_perm_b32 v20, v39, v57, s4
-; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_perm_b32 v21, v38, v63, s4
-; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_perm_b32 v22, v54, v37, s4
-; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_perm_b32 v23, v40, v50, s4
-; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_perm_b32 v24, v48, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_mov_b32_e32 v48, v25
; VI-NEXT: v_perm_b32 v25, v25, v41, s4
-; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v34, v33
; VI-NEXT: v_mov_b32_e32 v33, v26
@@ -146038,40 +147130,45 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
-; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v28, v29, s4
-; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v28, v28, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v62, v29, s4
-; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v29, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v62, v44
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v43, v29, s4
-; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v29, v30, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
@@ -146079,16 +147176,18 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
-; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v31, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_mov_b32_e32 v35, v43
; VI-NEXT: v_perm_b32 v43, v44, v43, s4
-; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; VI-NEXT: v_or_b32_e32 v31, v43, v31
; VI-NEXT: v_mov_b32_e32 v43, v39
; VI-NEXT: v_mov_b32_e32 v39, v34
; VI-NEXT: v_mov_b32_e32 v34, v52
@@ -147588,11 +148687,12 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB89_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
@@ -147606,117 +148706,134 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s88 :: v_dual_and_b32 v29, 0xff, v166
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v37, 8, v10
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v86, 8, s88
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v70, 8, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v33, 8, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v32, 8, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v39, 8, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v119, 8, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v82, 8, v26
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v64, 8, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v128, 8, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v101, 8, v28
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v87, 8, v10
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v150, 8, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v102, 8, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v132, 8, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v183, v129, 8, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v41, v133, 8, v29
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v178, 8, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
@@ -148088,11 +149205,10 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s74, 0xff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v33
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v48
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
@@ -148108,52 +149224,61 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s11, s8, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v35
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v35, 8, s76
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s76, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v33, 8, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v32, 8, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v37
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v9, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v49
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v36
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v11, 16, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v37, 8, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v36, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v34, 8, v14
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v14, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v82, v64, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v9, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v96, v85, 0xc0c0004
@@ -148163,18 +149288,18 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v117
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v144
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v10, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v84, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v19, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v87, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v135
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v150
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v11, 16, v9
@@ -148190,72 +149315,82 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v11, 16, v22
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v117, 8, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v134
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v119
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-FAKE16-NEXT: s_and_b32 s77, s62, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v114, 8, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v119, 8, v10
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s59, 8
; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s45, 8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v24, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v114
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_and_b32 s78, s56, 0xff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v24, v25
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
; GFX11-FAKE16-NEXT: s_and_b32 s79, s63, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s61, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v144, 8, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v147, 8, v10
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v147
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v133, 8, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v26, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v133
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v26, v27
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v177
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v164
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v151
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v164, 8, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v135, 8, v28
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v28, v29
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v176
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v161
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v161, 8, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v28, v29
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v179, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v165
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v178
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v165, 8, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v166, 8, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v150, 8, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v30, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v166
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v11, v31
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v40
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB89_3
@@ -151756,10 +152891,12 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v2, v2, v35, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v45, v39, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v45, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v33, 16, v45
+; VI-NEXT: v_or_b32_e32 v1, v1, v33
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v53, v49, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
@@ -151767,12 +152904,14 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
; VI-NEXT: v_perm_b32 v1, v36, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v61, s4
; VI-NEXT: v_perm_b32 v2, v43, v37, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v61, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
@@ -151780,17 +152919,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v5, v55, s4
; VI-NEXT: v_perm_b32 v1, v48, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v6, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v6, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
@@ -151798,12 +152939,14 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v7, v54, s4
; VI-NEXT: v_perm_b32 v1, v44, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v56, s4
; VI-NEXT: v_perm_b32 v2, v51, v47, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v56, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -151812,17 +152955,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: v_perm_b32 v2, v9, v63, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v10, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v10, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -151831,19 +152976,21 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v11, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v12, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v12, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
@@ -151852,19 +152999,21 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v14, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v14, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
@@ -151873,19 +153022,21 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v16, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
@@ -151893,17 +153044,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v60, s4
; VI-NEXT: v_perm_b32 v1, v41, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v18, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
@@ -151912,19 +153065,21 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v20, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
@@ -151935,17 +153090,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v22, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -151956,17 +153113,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v23, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v24, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v24, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
@@ -151977,17 +153136,19 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v26, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v26, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
@@ -151995,12 +153156,14 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v27, v50, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v59, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v28, v58, s4
; VI-NEXT: v_perm_b32 v2, v34, v57, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v28, v58, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -152008,7 +153171,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v29, v38, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v42, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
@@ -152016,7 +153180,8 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v30, v52, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
@@ -152027,18 +153192,20 @@ define <128 x i8> @bitcast_v64bf16_to_v128i8(<64 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v32, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v32, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -159296,23 +160463,27 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_mov_b32_e32 v20, v10
; VI-NEXT: .LBB91_5: ; %end
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v26, v26, v58, s4
; VI-NEXT: v_perm_b32 v6, v33, v6, s4
-; VI-NEXT: v_lshl_or_b32 v6, v6, 16, v26
-; VI-NEXT: v_perm_b32 v33, v47, v50, s4
+; VI-NEXT: v_perm_b32 v26, v26, v58, s4
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v6, v26, v6
; VI-NEXT: buffer_store_dword v6, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v6, v25, v30, s4
-; VI-NEXT: v_lshl_or_b32 v6, v6, 16, v33
+; VI-NEXT: v_perm_b32 v33, v47, v50, s4
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v6, v33, v6
; VI-NEXT: v_add_u32_e32 v25, vcc, 4, v0
+; VI-NEXT: v_perm_b32 v5, v24, v5, s4
; VI-NEXT: buffer_store_dword v6, v25, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v6, v29, v2, s4
-; VI-NEXT: v_perm_b32 v5, v24, v5, s4
-; VI-NEXT: v_lshl_or_b32 v5, v5, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v5, v6, v5
; VI-NEXT: v_add_u32_e32 v6, vcc, 8, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v5, v23, v31, s4
; VI-NEXT: v_perm_b32 v6, v11, v28, s4
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_perm_b32 v5, v23, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 12, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
@@ -159351,7 +160522,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v2, v4, s4
-; VI-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_add_u32_e32 v5, vcc, 16, v0
; VI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
@@ -159359,7 +160531,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v4, v60, v20, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v5, v2, s4
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 20, v0
; VI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
@@ -159368,7 +160541,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
@@ -159378,7 +160552,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v4, v2, s4
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
@@ -159389,17 +160564,19 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v4, s4
-; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v2, v37, v2, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v3, v4, v3, s4
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v2, v37, v2, s4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
@@ -159408,17 +160585,19 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v2, v49, v2, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v3, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v48, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v48, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
@@ -159428,7 +160607,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v52, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
@@ -159437,7 +160617,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v51, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v22, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
@@ -159447,17 +160628,19 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v44, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v19, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v19, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -159465,12 +160648,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v59, v53, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v36, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v56, v57, s4
; VI-NEXT: v_perm_b32 v2, v55, v15, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v56, v57, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -159478,12 +160663,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v41, v9, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v21, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v14, v40, s4
; VI-NEXT: v_perm_b32 v2, v39, v54, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v14, v40, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
@@ -159491,7 +160678,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v18, v17, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v7, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
@@ -159499,7 +160687,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v12, v13, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
@@ -159510,17 +160699,19 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v8, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v8, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -159531,7 +160722,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: v_perm_b32 v1, v42, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
@@ -159543,7 +160735,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
@@ -159556,7 +160749,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
@@ -159568,7 +160762,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
@@ -159581,7 +160776,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
@@ -159593,7 +160789,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
@@ -159605,16 +160802,18 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v61, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_perm_b32 v1, v1, v43, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -161115,7 +162314,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v26, v34, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v26, v50, 16, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v34, 16, v50
+; GFX9-NEXT: v_or_b32_e32 v26, v26, v34
; GFX9-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
@@ -161125,12 +162325,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v27, v9, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v26
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v9, v26, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s4
-; GFX9-NEXT: v_lshl_or_b32 v8, v49, 16, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v49
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
; GFX9-NEXT: buffer_store_dword v8, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -161138,12 +162340,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v60, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v48
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v48, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161152,12 +162356,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v7, v7, v53, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v38
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v54, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v38, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161166,12 +162372,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v7, v7, v55, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v15, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v40, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v12, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161180,12 +162388,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v7, v7, v41, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v47, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v42, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v36, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161194,30 +162404,36 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v7, v7, v43, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v46, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v8, v56, v51, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v14
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v44, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v14, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v8, v56, v51, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v45, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_perm_b32 v7, v13, v39, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v30, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v30
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, v58, v32, s4
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v7, v61, v35, s4
-; GFX9-NEXT: v_perm_b32 v8, v58, v32, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v7, v1, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v33, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v33
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v7
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -161225,12 +162441,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v22, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v1, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v31, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161239,7 +162457,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v24, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161248,7 +162467,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v1, v1, v5, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v20, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161257,7 +162477,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v29, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161267,7 +162488,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v10, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161276,7 +162498,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v1, v1, v11, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v28, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161286,7 +162509,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161295,7 +162519,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_perm_b32 v1, v1, v17, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v25, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161305,17 +162530,18 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:104
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v1, v1, v19, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v1, v1, v19, s4
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161327,7 +162553,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161338,7 +162565,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161350,7 +162578,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -161361,7 +162590,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -162630,70 +163860,93 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_perm_b32 v115, v117, v63, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_perm_b32 v117, v114, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v37, v132, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v114, v129, v62, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v132, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
; GFX11-TRUE16-NEXT: v_perm_b32 v118, v118, v60, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v128, v116, v61, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v148, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v163, v30, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v114
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v114, v2, 16, v38
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v114, v38, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v144, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v116, v37, 16, v118
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
+; GFX11-TRUE16-NEXT: v_perm_b32 v128, v116, v61, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v33, v130, v59, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v32, v148, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v115, v117, v115
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v116, v118, v37
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v117, v128, v129
; GFX11-TRUE16-NEXT: v_perm_b32 v37, v133, v58, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v38, v119, v57, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v119, v135, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v118, v145, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v131, v131, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v96, v18, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v115, v115, 16, v117
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v117, v128, v129
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v128, v2, 16, v33
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v129, v37, 16, v38
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v130, v32, 16, v119
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v128, v33, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v160, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v149, v43, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v130, v119, v32
; GFX11-TRUE16-NEXT: v_perm_b32 v32, v146, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v163, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v118, v145, v56, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v129, v38, v37
; GFX11-TRUE16-NEXT: v_perm_b32 v33, v134, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v37, v150, v40, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v131, v118, 16, v131
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v32, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v161, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v131, v131, v47, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v150, v40, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v167, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v33, v31
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v147, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v177, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v131, v131, v118
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, v37, v38
+; GFX11-TRUE16-NEXT: v_perm_b32 v38, v166, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v69, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v68, v5, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v82, v9, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v100, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v96, v18, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[114:117], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[128:131], off offset:16
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v2, 16, v32
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v161, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v31, 16, v33
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, v37, v38
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v147, v182, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v167, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v38, v166, v180, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v177, v25, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v116, v165, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, v33, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v176, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v114, v38, v26
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v51, v45, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v68, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v84, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v82, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v100, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v164, v181, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v116, v116, v25
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v162, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v4, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v83, v7, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v23, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v5, v23
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v80, v29, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v86, v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v9, v18
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v97, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v37, v164, v181, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v115, v151, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v33, v2, 16, v33
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v114, v26, 16, v38
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v176, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v116, v25, 16, v116
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v162, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v51, v45, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v4, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v22, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v53, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v66, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v117, v25, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v55, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v26
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v67, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v22
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v85, v28, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v17
@@ -162702,17 +163955,15 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v101, v21, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v113, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v112, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v115, v37, 16, v115
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v53, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v115, v115, v37
; GFX11-TRUE16-NEXT: v_perm_b32 v34, v52, v44, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v66, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v37, v64, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v117, v2, 16, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v55, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v26, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v54, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v67, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v65, v6, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v70, v8, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v10, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
@@ -162725,10 +163976,10 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v99, v19, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v34
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v37
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v25, 16, v4
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v26, 16, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v34, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v37, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v25
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v26
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v22
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v23
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v12, v17
@@ -164077,63 +165328,83 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v35, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v35, v112, v73, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v112, v114, v63, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v103, v103, v72, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v34, v129, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v103, v103, v72, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v114, v118, v62, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v115, v115, v60, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v112
-; GFX11-FAKE16-NEXT: v_perm_b32 v118, v113, v61, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v115, v115, v60, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v112, v35, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v134, v33, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v118, v113, v61, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v129, 16, v114
-; GFX11-FAKE16-NEXT: v_perm_b32 v32, v147, v32, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v113, v103, v117
-; GFX11-FAKE16-NEXT: v_perm_b32 v103, v133, v56, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v112, v2, 16, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v134, v33, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v114, v115, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v115, v118, v129
; GFX11-FAKE16-NEXT: v_perm_b32 v33, v128, v59, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v34, v130, v58, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v32, v147, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v103, v133, v56, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v115, v118, v129
; GFX11-FAKE16-NEXT: v_perm_b32 v35, v116, v57, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
; GFX11-FAKE16-NEXT: v_perm_b32 v116, v132, v46, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v118, v119, v47, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v66, v21, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v65, v5, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v85, v19, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v2, 16, v33
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v33, v34, 16, v35
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v116, v117
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v33, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v150, v28, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v118, v103
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v145, v42, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v35, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v116, v117
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v118, v103
; GFX11-FAKE16-NEXT: v_perm_b32 v103, v144, v40, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v27, v162, v27, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v116, v131, v183, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v66, v21, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v117, v148, v182, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v81, v20, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v80, v7, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v21, 16, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v69, v31, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v71, v9, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v18, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX11-FAKE16-NEXT: s_clause 0x1
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[112:115], off
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[32:35], off offset:16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v2, 16, v103
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v103, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v149, v181, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v33, v28, 16, v116
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v34, v27, 16, v117
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v135, v180, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v116, v28
; GFX11-FAKE16-NEXT: v_perm_b32 v26, v164, v26, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v163, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v65, v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v81, v20, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v85, v19, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v117, v27
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v135, v180, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v103, v161, v178, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v25, v166, v25, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; GFX11-FAKE16-NEXT: v_perm_b32 v112, v146, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v20, 16, v7
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v80, v7, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v21
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v69, v31, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v71, v9, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v18, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v114, 16, v25
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v27, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v103, v26
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v165, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v112, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v151, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v36, v48, v45, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v48, v49, v44, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v20
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v67, v8, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v30, 0xc0c0004
@@ -164141,16 +165412,13 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v19
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v24, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v114, 16, v25
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v35, v2, 16, v27
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v26, 16, v103
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v165, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v28, 16, v112
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v151, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v36, v48, v45, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v48, v49, v44, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v55, v3, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v39, v4, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v48, v1
+; GFX11-FAKE16-NEXT: v_perm_b32 v48, v52, v41, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v37, v64, v37, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v68, v10, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v20
@@ -164161,15 +165429,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v13, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v101, v29, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v113, v160, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v55, v3, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v39, v53, v43, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v2, 16, v28
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v48
-; GFX11-FAKE16-NEXT: v_perm_b32 v48, v52, v41, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v36, 16, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v36
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v37, v64, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v48
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v70, v12, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v21
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v16, 0xc0c0004
@@ -164181,9 +165448,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v15, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v113, v114
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v39
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v48, 16, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v37, 16, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v39, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v36
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v37
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v16, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v19
@@ -166617,12 +167884,19 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v10, v37, v36, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v59, v34, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v57, v32, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v47, v46, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v43, v42, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v55, v54, s6
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v51, v50, s6
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr59
@@ -166644,14 +167918,16 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166660,7 +167936,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166669,7 +167946,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166678,7 +167956,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166687,7 +167966,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166696,7 +167976,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166705,22 +167986,24 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v9, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_perm_b32 v8, v38, v61, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_perm_b32 v9, v39, v62, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, v38, v61, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v35, v60, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v33, v58, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v63, v56, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v45, v44, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v41, v40, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_perm_b32 v14, v53, v52, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr61
@@ -166739,7 +168022,7 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v49, v15, s6
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr49
@@ -166751,14 +168034,16 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v17, v18, v19
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166767,7 +168052,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166776,7 +168062,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166785,7 +168072,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166794,7 +168082,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166803,7 +168092,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v23, v24, s6
-; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v22, v23
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166812,7 +168102,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166821,7 +168112,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v25, v26, s6
-; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v24, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166830,7 +168122,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v25, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166839,7 +168132,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v26, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166848,7 +168142,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166857,7 +168152,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v28, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166866,7 +168162,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -166875,7 +168172,8 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v30, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
@@ -166940,13 +168238,14 @@ define <64 x half> @bitcast_v128i8_to_v64f16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: ; kill: killed $vgpr48
-; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v32, v33, v32, s6
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; VI-NEXT: ; kill: killed $vgpr48
+; VI-NEXT: ; implicit-def: $vgpr48
+; VI-NEXT: v_or_b32_e32 v31, v31, v32
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
@@ -172407,70 +173706,82 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB93_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s19
+; VI-NEXT: v_mov_b32_e32 v3, s23
+; VI-NEXT: v_mov_b32_e32 v0, s17
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_mov_b32_e32 v3, s23
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s8, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s7
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s10
-; VI-NEXT: v_perm_b32 v4, s11, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_perm_b32 v5, s14, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s13
+; VI-NEXT: v_perm_b32 v4, s11, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s41
-; VI-NEXT: v_perm_b32 v5, s42, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s13
; VI-NEXT: v_perm_b32 v6, s46, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s45
+; VI-NEXT: v_perm_b32 v5, s42, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s57
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s45
; VI-NEXT: v_perm_b32 v7, s63, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s62
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s61
-; VI-NEXT: v_perm_b32 v7, s74, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s62
; VI-NEXT: v_perm_b32 v8, s73, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s9
+; VI-NEXT: v_perm_b32 v7, s74, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s12
-; VI-NEXT: v_perm_b32 v8, s76, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s9
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
+; VI-NEXT: v_perm_b32 v8, s76, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v43, v10
; VI-NEXT: v_mov_b32_e32 v10, s43
-; VI-NEXT: v_perm_b32 v9, s44, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v10, s56, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s47
+; VI-NEXT: v_perm_b32 v9, s44, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v35, v12
; VI-NEXT: v_mov_b32_e32 v12, s59
-; VI-NEXT: v_perm_b32 v10, s60, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s47
; VI-NEXT: v_perm_b32 v12, s72, v12, v11
+; VI-NEXT: v_perm_b32 v10, s60, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s75, v13, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v15, v14, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s75, v13, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
@@ -172479,22 +173790,26 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: v_perm_b32 v23, v51, v33, s4
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v12, v56, v12, s4
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v14, v59, v14, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v13, v47, v13, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v14, v59, v14, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v15, v32, v15, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v61, v13, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v17, v60, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v21, v16, s4
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v17, v28, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v21, v58, v46, s4
; VI-NEXT: v_perm_b32 v24, v36, v49, s4
; VI-NEXT: v_mov_b32_e32 v28, v52
@@ -172502,36 +173817,44 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v16, v19, v16, s4
; VI-NEXT: v_perm_b32 v19, v26, v22, s4
-; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v19
+; VI-NEXT: v_or_b32_e32 v17, v19, v17
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_perm_b32 v16, v25, v20, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v16, v18, v16
; VI-NEXT: v_perm_b32 v18, v45, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v20, v44, v29, s4
; VI-NEXT: v_perm_b32 v22, v53, v42, s4
; VI-NEXT: v_mov_b32_e32 v45, v34
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v19, v30, v19, s4
-; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_perm_b32 v19, v55, v31, s4
-; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_perm_b32 v20, v39, v57, s4
-; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_perm_b32 v21, v38, v63, s4
-; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_perm_b32 v22, v54, v37, s4
-; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_perm_b32 v23, v40, v50, s4
-; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_perm_b32 v24, v48, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_mov_b32_e32 v48, v25
; VI-NEXT: v_perm_b32 v25, v25, v41, s4
-; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v34, v33
; VI-NEXT: v_mov_b32_e32 v33, v26
@@ -172543,40 +173866,45 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
-; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v28, v29, s4
-; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v28, v28, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v62, v29, s4
-; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v29, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v62, v44
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v43, v29, s4
-; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v29, v30, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
@@ -172584,16 +173912,18 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
-; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v31, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_mov_b32_e32 v35, v43
; VI-NEXT: v_perm_b32 v43, v44, v43, s4
-; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; VI-NEXT: v_or_b32_e32 v31, v43, v31
; VI-NEXT: v_mov_b32_e32 v43, v39
; VI-NEXT: v_mov_b32_e32 v39, v34
; VI-NEXT: v_mov_b32_e32 v34, v52
@@ -174093,11 +175423,12 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB93_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
@@ -174111,117 +175442,134 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s88 :: v_dual_and_b32 v29, 0xff, v166
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v37, 8, v10
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v86, 8, s88
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v70, 8, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v33, 8, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v32, 8, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v39, 8, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v119, 8, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v82, 8, v26
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v64, 8, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v128, 8, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v101, 8, v28
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v87, 8, v10
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v150, 8, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v102, 8, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v132, 8, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v183, v129, 8, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v41, v133, 8, v29
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v178, 8, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
@@ -174593,11 +175941,10 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s74, 0xff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v33
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v48
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
@@ -174613,52 +175960,61 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s11, s8, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v35
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v35, 8, s76
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s76, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v33, 8, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v32, 8, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v37
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v9, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v49
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v36
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v11, 16, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v37, 8, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v36, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v34, 8, v14
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v14, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v82, v64, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v9, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v96, v85, 0xc0c0004
@@ -174668,18 +176024,18 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v117
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v144
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v10, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v84, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v19, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v87, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v135
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v150
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v11, 16, v9
@@ -174695,72 +176051,82 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v11, 16, v22
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v117, 8, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v134
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v119
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-FAKE16-NEXT: s_and_b32 s77, s62, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v114, 8, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v119, 8, v10
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s59, 8
; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s45, 8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v24, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v114
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_and_b32 s78, s56, 0xff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v24, v25
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
; GFX11-FAKE16-NEXT: s_and_b32 s79, s63, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s61, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v144, 8, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v147, 8, v10
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v147
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v133, 8, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v26, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v133
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v26, v27
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v177
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v164
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v151
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v164, 8, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v135, 8, v28
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v28, v29
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v176
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v161
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v161, 8, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v28, v29
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v179, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v165
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v178
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v165, 8, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v166, 8, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v150, 8, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v30, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v166
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v11, v31
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v40
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB93_3
@@ -177360,138 +178726,172 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v42, 0x200
; VI-NEXT: v_add_f16_sdwa v23, v18, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v18, 0x200, v18
; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v57, v23, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
+; VI-NEXT: v_add_f16_e32 v18, 0x200, v18
; VI-NEXT: v_add_f16_sdwa v23, v17, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v17, 0x200, v17
+; VI-NEXT: v_or_b32_e32 v57, v18, v29
; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v56, v23, 16, v17
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
+; VI-NEXT: v_add_f16_e32 v17, 0x200, v17
; VI-NEXT: v_add_f16_sdwa v23, v20, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v20, 0x200, v20
+; VI-NEXT: v_or_b32_e32 v56, v17, v29
; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v59, v23, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
+; VI-NEXT: v_add_f16_e32 v20, 0x200, v20
; VI-NEXT: v_add_f16_sdwa v23, v19, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v19, 0x200, v19
+; VI-NEXT: v_or_b32_e32 v59, v20, v29
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; VI-NEXT: v_add_f16_sdwa v20, v51, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v51, 0x200, v51
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; VI-NEXT: v_add_f16_sdwa v37, v10, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
; VI-NEXT: v_add_f16_sdwa v45, v14, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
-; VI-NEXT: v_lshl_or_b32 v32, v45, 16, v14
-; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
-; VI-NEXT: v_lshl_or_b32 v53, v37, 16, v10
-; VI-NEXT: v_lshl_or_b32 v58, v23, 16, v19
+; VI-NEXT: v_or_b32_e32 v58, v19, v29
; VI-NEXT: v_add_f16_sdwa v19, v22, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v22, 0x200, v22
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v55, v19, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
+; VI-NEXT: v_add_f16_e32 v22, 0x200, v22
; VI-NEXT: v_add_f16_sdwa v19, v21, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v21, 0x200, v21
-; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; VI-NEXT: v_or_b32_e32 v55, v22, v29
; VI-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_sdwa v22, v8, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT: v_lshl_or_b32 v54, v19, 16, v21
-; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
+; VI-NEXT: s_waitcnt vmcnt(5)
; VI-NEXT: v_add_f16_sdwa v19, v24, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v24, 0x200, v24
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v61, v19, 16, v24
+; VI-NEXT: v_add_f16_e32 v24, 0x200, v24
+; VI-NEXT: v_add_f16_sdwa v22, v8, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
+; VI-NEXT: v_or_b32_e32 v54, v21, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
; VI-NEXT: v_add_f16_sdwa v19, v23, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v23, 0x200, v23
+; VI-NEXT: v_or_b32_e32 v61, v24, v29
; VI-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
+; VI-NEXT: v_add_f16_sdwa v19, v26, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; VI-NEXT: v_add_f16_e32 v26, 0x200, v26
; VI-NEXT: v_add_f16_sdwa v24, v4, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_add_f16_sdwa v21, v6, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
-; VI-NEXT: v_lshl_or_b32 v49, v21, 16, v6
-; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
-; VI-NEXT: v_lshl_or_b32 v44, v24, 16, v4
-; VI-NEXT: v_lshl_or_b32 v60, v19, 16, v23
-; VI-NEXT: v_add_f16_sdwa v19, v26, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v26, 0x200, v26
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v63, v19, 16, v26
+; VI-NEXT: v_or_b32_e32 v60, v23, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
; VI-NEXT: v_add_f16_sdwa v19, v25, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v25, 0x200, v25
+; VI-NEXT: v_or_b32_e32 v63, v26, v29
; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
+; VI-NEXT: v_add_f16_sdwa v19, v28, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; VI-NEXT: v_add_f16_e32 v28, 0x200, v28
; VI-NEXT: v_add_f16_sdwa v26, v31, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v31, 0x200, v31
; VI-NEXT: v_add_f16_sdwa v23, v12, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v34, v26, 16, v31
; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
-; VI-NEXT: v_lshl_or_b32 v41, v23, 16, v12
-; VI-NEXT: v_lshl_or_b32 v62, v19, 16, v25
-; VI-NEXT: v_add_f16_sdwa v19, v28, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v28, 0x200, v28
-; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v39, v19, 16, v28
+; VI-NEXT: v_or_b32_e32 v62, v25, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
; VI-NEXT: v_add_f16_sdwa v19, v27, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v27, 0x200, v27
+; VI-NEXT: v_or_b32_e32 v39, v28, v29
; VI-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_sdwa v25, v30, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v30, 0x200, v30
-; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v33, v25, 16, v30
-; VI-NEXT: v_add_f16_sdwa v25, v16, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
-; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v38, v19, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
; VI-NEXT: v_add_f16_sdwa v19, v50, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_f16_e32 v50, 0x200, v50
; VI-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v27, v30
+; VI-NEXT: v_add_f16_sdwa v25, v30, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_e32 v30, 0x200, v30
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
-; VI-NEXT: v_mov_b32_e32 v28, v31
-; VI-NEXT: v_lshl_or_b32 v30, v25, 16, v16
-; VI-NEXT: v_lshl_or_b32 v36, v20, 16, v51
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v38, v27, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v26
+; VI-NEXT: v_or_b32_e32 v34, v31, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v25
+; VI-NEXT: v_or_b32_e32 v33, v30, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
+; VI-NEXT: v_or_b32_e32 v36, v51, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
+; VI-NEXT: v_add_f16_sdwa v19, v2, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v35, v50, v29
+; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: v_add_f16_sdwa v20, v1, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v19
; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
+; VI-NEXT: v_or_b32_e32 v47, v2, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v46, v20, 16, v1
+; VI-NEXT: v_or_b32_e32 v46, v1, v29
; VI-NEXT: v_add_f16_sdwa v20, v3, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v24
; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
+; VI-NEXT: v_or_b32_e32 v44, v4, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v43, v20, 16, v3
+; VI-NEXT: v_or_b32_e32 v43, v3, v29
; VI-NEXT: v_add_f16_sdwa v20, v5, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v21
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
+; VI-NEXT: v_or_b32_e32 v49, v6, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v48, v20, 16, v5
+; VI-NEXT: v_or_b32_e32 v48, v5, v29
; VI-NEXT: v_add_f16_sdwa v20, v7, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v22
; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
-; VI-NEXT: v_lshl_or_b32 v35, v19, 16, v50
+; VI-NEXT: v_or_b32_e32 v51, v8, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v50, v20, 16, v7
+; VI-NEXT: v_or_b32_e32 v50, v7, v29
; VI-NEXT: v_add_f16_sdwa v20, v9, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v37
; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
+; VI-NEXT: v_or_b32_e32 v53, v10, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v52, v20, 16, v9
+; VI-NEXT: v_or_b32_e32 v52, v9, v29
; VI-NEXT: v_add_f16_sdwa v20, v11, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v23
; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
-; VI-NEXT: v_add_f16_sdwa v19, v2, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v41, v12, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v40, v20, 16, v11
+; VI-NEXT: v_or_b32_e32 v40, v11, v29
; VI-NEXT: v_add_f16_sdwa v20, v13, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v45
; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
+; VI-NEXT: v_or_b32_e32 v32, v14, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v20
+; VI-NEXT: v_mov_b32_e32 v27, v30
+; VI-NEXT: v_add_f16_sdwa v25, v16, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_mov_b32_e32 v28, v31
+; VI-NEXT: v_or_b32_e32 v31, v13, v29
+; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
; VI-NEXT: v_add_f16_sdwa v42, v15, v42 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v25
; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
+; VI-NEXT: v_or_b32_e32 v30, v16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v42
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v31, v20, 16, v13
-; VI-NEXT: v_lshl_or_b32 v29, v42, 16, v15
+; VI-NEXT: v_or_b32_e32 v29, v15, v29
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v30
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v29
@@ -177505,7 +178905,6 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v40
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v53
-; VI-NEXT: v_lshl_or_b32 v51, v22, 16, v8
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v52
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
@@ -177516,10 +178915,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v49
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v48
-; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v44
-; VI-NEXT: v_lshl_or_b32 v47, v19, 16, v2
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v20, 8, v43
; VI-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
@@ -177630,6 +179027,7 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_bfe_u32 v19, v19, 8, 8
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v56, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; VI-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v58, v21
@@ -177663,9 +179061,10 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v24, v46, s4
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v24, s4
-; VI-NEXT: v_lshl_or_b32 v1, v29, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v29
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
@@ -177673,7 +179072,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v2, v2, v24, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v35, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
@@ -177682,7 +179082,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v43, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
@@ -177691,7 +179092,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v4, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v34, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
@@ -177700,7 +179102,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v48, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v5, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
@@ -177709,7 +179112,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v6, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v58, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -177718,9 +179122,10 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v7, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
@@ -177729,7 +179134,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v8, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v37, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
@@ -177738,9 +179144,10 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v9, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
@@ -177749,7 +179156,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v10, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v59, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
@@ -177758,9 +179166,10 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v11, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
@@ -177769,7 +179178,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v12, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v45, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
@@ -177778,9 +179188,10 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v13, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
@@ -177789,7 +179200,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v14, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v40, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
@@ -177798,61 +179210,69 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v15, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_perm_b32 v1, v16, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v63, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v47, v38, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v18, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v56, v54, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v49, v57, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v20, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v39, v60, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v21, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v53, v33, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v22, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
@@ -177861,7 +179281,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v2, v1, s4
; VI-NEXT: v_perm_b32 v2, v36, v62, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
@@ -177870,7 +179291,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v3, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v41, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
@@ -177880,7 +179302,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v25, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -177889,7 +179312,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v26, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v42, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
@@ -177899,7 +179323,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v27, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
@@ -177908,7 +179333,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v28, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v32, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -177918,7 +179344,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v1, v30, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
@@ -177927,17 +179354,18 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v31, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v52, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v1, v50, v1, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v61, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v50, v1, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
@@ -177947,7 +179375,8 @@ define <128 x i8> @bitcast_v64f16_to_v128i8(<64 x half> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v51, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v44, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -181701,173 +183130,206 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_lshr_b32 s46, s45, 16
; VI-NEXT: v_mov_b32_e32 v7, 0x200
; VI-NEXT: v_add_f16_e32 v36, s46, v7
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
; VI-NEXT: v_add_f16_e32 v2, s45, v7
; VI-NEXT: s_lshr_b32 s45, s44, 16
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v23, v36, 16, v2
+; VI-NEXT: v_or_b32_e32 v23, v2, v1
; VI-NEXT: v_add_f16_e32 v1, s45, v7
; VI-NEXT: v_add_f16_e32 v2, s44, v7
; VI-NEXT: s_lshr_b32 s44, s43, 16
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v22, v1, 16, v2
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v53, s44, v7
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v22, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v53
; VI-NEXT: v_add_f16_e32 v2, s43, v7
; VI-NEXT: s_lshr_b32 s43, s42, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v25, v53, 16, v2
+; VI-NEXT: v_or_b32_e32 v25, v2, v1
; VI-NEXT: v_add_f16_e32 v1, s43, v7
; VI-NEXT: v_add_f16_e32 v2, s42, v7
; VI-NEXT: s_lshr_b32 s42, s41, 16
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v24, v1, 16, v2
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v50, s42, v7
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v24, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v50
; VI-NEXT: v_add_f16_e32 v2, s41, v7
; VI-NEXT: s_lshr_b32 s41, s40, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v27, v50, 16, v2
+; VI-NEXT: v_or_b32_e32 v27, v2, v1
; VI-NEXT: v_add_f16_e32 v1, s41, v7
; VI-NEXT: v_add_f16_e32 v2, s40, v7
; VI-NEXT: s_lshr_b32 s40, s15, 16
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v26, v1, 16, v2
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v61, s40, v7
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v26, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v61
; VI-NEXT: v_add_f16_e32 v2, s15, v7
; VI-NEXT: s_lshr_b32 s15, s14, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v29, v61, 16, v2
+; VI-NEXT: v_or_b32_e32 v29, v2, v1
; VI-NEXT: v_add_f16_e32 v1, s15, v7
; VI-NEXT: v_add_f16_e32 v2, s14, v7
; VI-NEXT: s_lshr_b32 s14, s13, 16
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v28, v1, 16, v2
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v51, s14, v7
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v28, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v51
; VI-NEXT: v_add_f16_e32 v2, s13, v7
; VI-NEXT: s_lshr_b32 s13, s12, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v6, v51, 16, v2
+; VI-NEXT: v_or_b32_e32 v6, v2, v1
; VI-NEXT: v_add_f16_e32 v1, s13, v7
; VI-NEXT: v_add_f16_e32 v2, s12, v7
; VI-NEXT: s_lshr_b32 s12, s11, 16
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v5, v1, 16, v2
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v41, s12, v7
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v5, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v41
; VI-NEXT: v_add_f16_e32 v2, s11, v7
; VI-NEXT: s_lshr_b32 s11, s10, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v31, v41, 16, v2
+; VI-NEXT: v_or_b32_e32 v31, v2, v1
; VI-NEXT: v_add_f16_e32 v1, s11, v7
; VI-NEXT: v_add_f16_e32 v2, s10, v7
; VI-NEXT: s_lshr_b32 s10, s9, 16
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v30, v1, 16, v2
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v37, s10, v7
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v30, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v37
; VI-NEXT: v_add_f16_e32 v2, s9, v7
; VI-NEXT: s_lshr_b32 s9, s8, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v4, v37, 16, v2
+; VI-NEXT: v_or_b32_e32 v4, v2, v1
; VI-NEXT: v_add_f16_e32 v1, s9, v7
; VI-NEXT: v_add_f16_e32 v2, s8, v7
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v3, v1, 16, v2
; VI-NEXT: s_lshr_b32 s8, s7, 16
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_add_f16_e32 v52, s8, v7
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v3, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v52
; VI-NEXT: v_add_f16_e32 v2, s7, v7
; VI-NEXT: s_lshr_b32 s7, s6, 16
+; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v2, v2, v1
+; VI-NEXT: v_add_f16_e32 v1, s7, v7
; VI-NEXT: v_add_f16_e32 v8, s6, v7
; VI-NEXT: s_lshr_b32 s6, s17, 16
+; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_add_f16_e32 v42, s6, v7
-; VI-NEXT: v_add_f16_e32 v9, s17, v7
; VI-NEXT: s_lshr_b32 s6, s16, 16
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v33, v42, 16, v9
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v1, v8, v1
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v42
+; VI-NEXT: v_add_f16_e32 v9, s17, v7
; VI-NEXT: v_add_f16_e32 v11, s6, v7
-; VI-NEXT: v_add_f16_e32 v9, s16, v7
; VI-NEXT: s_lshr_b32 s6, s19, 16
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v32, v11, 16, v9
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v33, v9, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; VI-NEXT: v_add_f16_e32 v9, s16, v7
; VI-NEXT: v_add_f16_e32 v60, s6, v7
-; VI-NEXT: v_add_f16_e32 v9, s19, v7
; VI-NEXT: s_lshr_b32 s6, s18, 16
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v21, v60, 16, v9
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v32, v9, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v60
+; VI-NEXT: v_add_f16_e32 v9, s19, v7
; VI-NEXT: v_add_f16_e32 v55, s6, v7
-; VI-NEXT: v_add_f16_e32 v9, s18, v7
; VI-NEXT: s_lshr_b32 s6, s21, 16
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; VI-NEXT: v_add_f16_e32 v1, s7, v7
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v20, v55, 16, v9
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v21, v9, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v55
+; VI-NEXT: v_add_f16_e32 v9, s18, v7
; VI-NEXT: s_lshr_b32 s7, s20, 16
; VI-NEXT: v_add_f16_e32 v39, s6, v7
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v20, v9, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v39
; VI-NEXT: v_add_f16_e32 v9, s21, v7
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v35, v39, 16, v9
; VI-NEXT: v_add_f16_e32 v38, s7, v7
-; VI-NEXT: v_add_f16_e32 v9, s20, v7
; VI-NEXT: s_lshr_b32 s6, s23, 16
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v34, v38, 16, v9
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v35, v9, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; VI-NEXT: v_add_f16_e32 v9, s20, v7
; VI-NEXT: s_lshr_b32 s7, s22, 16
; VI-NEXT: v_add_f16_e32 v49, s6, v7
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v34, v9, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v49
; VI-NEXT: v_add_f16_e32 v9, s23, v7
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v19, v49, 16, v9
; VI-NEXT: v_add_f16_e32 v48, s7, v7
-; VI-NEXT: v_add_f16_e32 v9, s22, v7
; VI-NEXT: s_lshr_b32 s6, s25, 16
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v19, v9, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v48
+; VI-NEXT: v_add_f16_e32 v9, s22, v7
+; VI-NEXT: v_add_f16_e32 v45, s6, v7
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v18, v48, 16, v9
+; VI-NEXT: v_or_b32_e32 v18, v9, v8
; VI-NEXT: s_lshr_b32 s7, s24, 16
-; VI-NEXT: v_add_f16_e32 v45, s6, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v45
; VI-NEXT: v_add_f16_e32 v9, s25, v7
-; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v8
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v16, v45, 16, v9
+; VI-NEXT: v_or_b32_e32 v16, v9, v8
; VI-NEXT: v_add_f16_e32 v8, s7, v7
-; VI-NEXT: v_add_f16_e32 v9, s24, v7
; VI-NEXT: s_lshr_b32 s6, s27, 16
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_add_f16_e32 v9, s24, v7
+; VI-NEXT: v_add_f16_e32 v47, s6, v7
; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v15, v8, 16, v9
+; VI-NEXT: v_or_b32_e32 v15, v9, v8
; VI-NEXT: s_lshr_b32 s7, s26, 16
-; VI-NEXT: v_add_f16_e32 v47, s6, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v47
; VI-NEXT: v_add_f16_e32 v9, s27, v7
-; VI-NEXT: s_lshr_b32 s6, s29, 16
-; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v13, v47, 16, v9
+; VI-NEXT: v_or_b32_e32 v13, v9, v8
; VI-NEXT: v_add_f16_e32 v8, s7, v7
+; VI-NEXT: s_lshr_b32 s6, s29, 16
+; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_add_f16_e32 v54, s26, v7
-; VI-NEXT: s_lshr_b32 s7, s28, 16
; VI-NEXT: v_add_f16_e32 v57, s6, v7
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v12, v54, v8
+; VI-NEXT: s_lshr_b32 s7, s28, 16
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v57
; VI-NEXT: v_add_f16_e32 v9, s29, v7
-; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v12, v8, 16, v54
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v10, v57, 16, v9
+; VI-NEXT: v_or_b32_e32 v10, v9, v8
; VI-NEXT: v_add_f16_e32 v8, s7, v7
-; VI-NEXT: v_add_f16_e32 v9, s28, v7
; VI-NEXT: s_lshr_b32 s6, s5, 16
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v9, v8, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_add_f16_e32 v9, s28, v7
; VI-NEXT: s_lshr_b32 s7, s4, 16
; VI-NEXT: v_add_f16_e32 v59, s6, v7
+; VI-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v9, v9, v8
; VI-NEXT: v_add_f16_e32 v8, s5, v7
; VI-NEXT: v_add_f16_e32 v14, s7, v7
; VI-NEXT: v_add_f16_e32 v17, s4, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v59
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v8, v59, 16, v8
-; VI-NEXT: v_add_f16_e32 v52, s8, v7
+; VI-NEXT: v_or_b32_e32 v8, v8, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v14
; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v7, v14, 16, v17
+; VI-NEXT: v_or_b32_e32 v7, v17, v7
; VI-NEXT: v_lshrrev_b32_e32 v14, 8, v8
; VI-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v14, 8, v7
@@ -181886,8 +183348,7 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v16
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v15
-; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v2, v52, 16, v2
+; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[16:17], 24, v[15:16]
; VI-NEXT: v_lshrrev_b32_e32 v8, 8, v19
@@ -182381,12 +183842,19 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v20, v23, v20, s4
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: v_perm_b32 v30, v42, v30, s4
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: v_perm_b32 v19, v55, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
; VI-NEXT: v_perm_b32 v18, v38, v18, s4
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v15, v39, v15, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v12, v49, v12, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v9, v45, v9, s4
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_readlane_b32 s30, v63, 30
; VI-NEXT: v_readlane_b32 s31, v63, 31
; VI-NEXT: v_readlane_b32 s87, v63, 29
@@ -182421,51 +183889,53 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v58, v23, v58, s4
-; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v58
+; VI-NEXT: v_or_b32_e32 v20, v58, v20
; VI-NEXT: buffer_store_dword v20, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v20, v56, s4
-; VI-NEXT: v_lshl_or_b32 v20, v30, 16, v20
+; VI-NEXT: v_or_b32_e32 v20, v20, v30
; VI-NEXT: v_add_u32_e32 v30, vcc, 4, v0
; VI-NEXT: buffer_store_dword v20, v30, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v20, v46, s4
-; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_add_u32_e32 v20, vcc, 8, v0
; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v20, v60, v22, s4
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v19, v40, s4
-; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: v_add_u32_e32 v20, vcc, 12, v0
; VI-NEXT: buffer_store_dword v19, v20, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v19, v44, s4
-; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_add_u32_e32 v19, vcc, 16, v0
; VI-NEXT: buffer_store_dword v18, v19, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v18, v43, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v18
+; VI-NEXT: v_or_b32_e32 v15, v18, v15
; VI-NEXT: v_add_u32_e32 v18, vcc, 20, v0
; VI-NEXT: buffer_store_dword v15, v18, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v15, v48, v17, s4
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v17, v17, v10, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v17
+; VI-NEXT: v_or_b32_e32 v15, v17, v15
; VI-NEXT: v_add_u32_e32 v17, vcc, 24, v0
; VI-NEXT: buffer_store_dword v15, v17, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v15, v10, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v15
+; VI-NEXT: v_or_b32_e32 v12, v15, v12
; VI-NEXT: v_add_u32_e32 v15, vcc, 28, v0
; VI-NEXT: buffer_store_dword v12, v15, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
@@ -182473,16 +183943,17 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v12, v10, v16, s4
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v15, v10, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v15
+; VI-NEXT: v_or_b32_e32 v12, v15, v12
; VI-NEXT: v_add_u32_e32 v15, vcc, 32, v0
; VI-NEXT: buffer_store_dword v12, v15, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v12, v12, v10, s4
-; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v12
+; VI-NEXT: v_or_b32_e32 v9, v12, v9
; VI-NEXT: v_add_u32_e32 v12, vcc, 36, v0
; VI-NEXT: buffer_store_dword v9, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
@@ -182491,15 +183962,17 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v9, v9, v13, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v12, v54, v10, s4
-; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v12
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v12, v9
; VI-NEXT: v_add_u32_e32 v12, vcc, 40, v0
; VI-NEXT: buffer_store_dword v9, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v12, v47, v28, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v9, v9, v10, s4
-; VI-NEXT: v_lshl_or_b32 v9, v12, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v12
; VI-NEXT: v_add_u32_e32 v12, vcc, 44, v0
; VI-NEXT: buffer_store_dword v9, v12, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
@@ -182507,17 +183980,19 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v9, v9, v7, s4
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v10, v7, v10, s4
-; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: v_add_u32_e32 v10, vcc, 48, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v10, v57, v26, s4
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v9, v7, v9, s4
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_add_u32_e32 v10, vcc, 52, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
@@ -182527,9 +184002,10 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v7, v7, v9, s4
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v9, v9, v10, s4
-; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; VI-NEXT: v_or_b32_e32 v7, v9, v7
; VI-NEXT: v_add_u32_e32 v9, vcc, 56, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
@@ -182537,14 +184013,16 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v7, v9, s4
; VI-NEXT: v_perm_b32 v9, v59, v11, s4
-; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_u32_e32 v9, vcc, 60, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v7, v53, v14, s4
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v9, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v7, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
@@ -182553,7 +184031,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v21, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v7, v27, s4
-; VI-NEXT: v_lshl_or_b32 v1, v7, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v1, v1, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
@@ -182562,14 +184041,16 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v24, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v7, v35, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v7, v1
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v7, v36, v25, s4
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v34, s4
-; VI-NEXT: v_lshl_or_b32 v1, v7, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
@@ -182578,7 +184059,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v6, v8, s4
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v1, v1, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
@@ -182587,7 +184069,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v29, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v50, v6, s4
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v1, v1, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
@@ -182596,7 +184079,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v33, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s4
-; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v1, v1, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
@@ -182605,7 +184089,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v61, v5, s4
-; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v1, v1, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
@@ -182614,7 +184099,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s4
-; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v1, v1, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
@@ -182624,7 +184110,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v51, v4, s4
-; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v1, v1, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
@@ -182634,7 +184121,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
@@ -182644,7 +184132,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v41, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
@@ -182654,7 +184143,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -182664,7 +184154,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v37, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
@@ -182676,7 +184167,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
@@ -182687,7 +184179,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v52, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -183610,8 +185103,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v39, v39, v44, s4
-; GFX9-NEXT: v_lshl_or_b32 v39, v39, 16, v48
-; GFX9-NEXT: v_lshl_or_b32 v37, v50, 16, v37
+; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
+; GFX9-NEXT: v_or_b32_e32 v39, v48, v39
; GFX9-NEXT: v_perm_b32 v23, v34, v23, s4
; GFX9-NEXT: v_perm_b32 v32, v32, v59, s4
; GFX9-NEXT: v_perm_b32 v29, v29, v57, s4
@@ -183665,7 +185158,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: v_perm_b32 v18, v18, v54, s4
; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v18, v21, v18
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v38, v47, v52, s4
; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -183696,17 +185190,22 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v39, v39, v48, s4
-; GFX9-NEXT: v_lshl_or_b32 v39, v39, 16, v49
+; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
+; GFX9-NEXT: v_or_b32_e32 v39, v49, v39
; GFX9-NEXT: buffer_store_dword v39, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v50
+; GFX9-NEXT: v_or_b32_e32 v37, v37, v39
; GFX9-NEXT: buffer_store_dword v37, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v37, v37, v39, s4
-; GFX9-NEXT: v_lshl_or_b32 v24, v37, 16, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v37, 16, v37
+; GFX9-NEXT: v_or_b32_e32 v24, v24, v37
; GFX9-NEXT: buffer_store_dword v24, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: buffer_store_dword v18, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -183714,66 +185213,79 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v18, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v18, 16, v16
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v16, v16, v18
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshl_or_b32 v16, v35, 16, v33
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v35
+; GFX9-NEXT: v_or_b32_e32 v16, v33, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshl_or_b32 v16, v34, 16, v31
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v34
+; GFX9-NEXT: v_or_b32_e32 v16, v31, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v32
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v32, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshl_or_b32 v16, v36, 16, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v36
+; GFX9-NEXT: v_or_b32_e32 v16, v29, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v30, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshl_or_b32 v16, v38, 16, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v38
+; GFX9-NEXT: v_or_b32_e32 v16, v27, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshl_or_b32 v16, v28, 16, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28
+; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v25, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshl_or_b32 v16, v26, 16, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26
+; GFX9-NEXT: v_or_b32_e32 v16, v19, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v20, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v15, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183782,7 +185294,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v14, v15, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183792,7 +185305,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183801,7 +185315,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183811,7 +185326,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183820,7 +185336,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v10, v11, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183830,7 +185347,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183839,7 +185357,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183849,7 +185368,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183858,7 +185378,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v6, v7, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183868,7 +185389,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -183877,7 +185399,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -183885,11 +185408,13 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_perm_b32 v1, v2, v41, s4
; GFX9-NEXT: v_perm_b32 v2, v40, v42, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -184584,105 +186109,136 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: v_mov_b32_e32 v148, s0
; GFX11-NEXT: .LBB95_5: ; %end
; GFX11-NEXT: v_perm_b32 v68, v73, v70, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v35, v35, v63, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v70, v62, v72, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v69, v60, v69, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX11-NEXT: v_perm_b32 v35, v35, v63, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
; GFX11-NEXT: v_perm_b32 v56, v33, v56, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
; GFX11-NEXT: v_perm_b32 v58, v58, v59, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v57, v34, v57, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v33, v68, 16, v35
-; GFX11-NEXT: v_lshl_or_b32 v34, v70, 16, v36
-; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v35, v69, 16, v56
+; GFX11-NEXT: v_or_b32_e32 v34, v36, v70
; GFX11-NEXT: v_perm_b32 v29, v29, v45, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v65
+; GFX11-NEXT: v_perm_b32 v70, v27, v182, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
+; GFX11-NEXT: v_or_b32_e32 v33, v35, v68
+; GFX11-NEXT: v_or_b32_e32 v35, v56, v69
; GFX11-NEXT: v_perm_b32 v68, v44, v46, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v30, v30, v40, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v69, v41, v42, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v70, v27, v182, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v182, v28, v183, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v36, v58, 16, v57
-; GFX11-NEXT: v_lshl_or_b32 v27, v65, 16, v29
-; GFX11-NEXT: v_lshl_or_b32 v28, v68, 16, v30
-; GFX11-NEXT: v_lshl_or_b32 v29, v64, 16, v70
-; GFX11-NEXT: v_lshl_or_b32 v30, v69, 16, v182
+; GFX11-NEXT: v_lshlrev_b32_e32 v58, 16, v58
+; GFX11-NEXT: v_or_b32_e32 v27, v29, v65
+; GFX11-NEXT: v_or_b32_e32 v29, v70, v64
; GFX11-NEXT: v_perm_b32 v54, v181, v54, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v64, v179, v180, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v23, v177, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v53, v178, v53, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v30, v40, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX11-NEXT: v_perm_b32 v182, v28, v183, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX11-NEXT: v_or_b32_e32 v36, v57, v58
+; GFX11-NEXT: v_perm_b32 v23, v23, v177, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; GFX11-NEXT: v_perm_b32 v24, v24, v167, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
; GFX11-NEXT: v_perm_b32 v21, v21, v176, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v53
+; GFX11-NEXT: v_or_b32_e32 v28, v30, v68
+; GFX11-NEXT: v_or_b32_e32 v30, v182, v69
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_store_b128 v0, v[33:36], off
; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:16
-; GFX11-NEXT: v_perm_b32 v30, v160, v51, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v27, v54, 16, v23
+; GFX11-NEXT: v_or_b32_e32 v27, v23, v54
; GFX11-NEXT: v_perm_b32 v23, v165, v166, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v28, v64, 16, v24
-; GFX11-NEXT: v_lshl_or_b32 v29, v53, 16, v21
+; GFX11-NEXT: v_or_b32_e32 v28, v24, v64
+; GFX11-NEXT: v_or_b32_e32 v29, v21, v53
; GFX11-NEXT: v_perm_b32 v21, v22, v164, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v163, v52, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v161, v162, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v160, v51, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v17, v17, v150, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v30
-; GFX11-NEXT: v_lshl_or_b32 v30, v23, 16, v21
-; GFX11-NEXT: v_lshl_or_b32 v19, v22, 16, v19
+; GFX11-NEXT: v_or_b32_e32 v30, v21, v23
+; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
; GFX11-NEXT: v_perm_b32 v22, v147, v148, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v20, v24, 16, v20
+; GFX11-NEXT: v_or_b32_e32 v20, v20, v24
; GFX11-NEXT: v_or_b32_e32 v21, v17, v33
; GFX11-NEXT: v_perm_b32 v17, v18, v146, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v145, v67, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v15, v134, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v133, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v131, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v135, v144, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-NEXT: v_perm_b32 v15, v15, v134, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v13, v13, v131, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v16, v16, v132, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v22, v22, 16, v17
-; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
+; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
; GFX11-NEXT: v_perm_b32 v18, v129, v130, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v17, v24, 16, v13
-; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v17, v13, v24
; GFX11-NEXT: v_perm_b32 v24, v115, v48, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v9, v113, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v16, v23, 16, v16
+; GFX11-NEXT: v_or_b32_e32 v16, v16, v23
+; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v14, v119, v49, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v117, v118, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v9, v9, v113, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v11, v11, v116, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v114, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v13
-; GFX11-NEXT: v_lshl_or_b32 v13, v24, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
+; GFX11-NEXT: v_or_b32_e32 v13, v9, v24
; GFX11-NEXT: v_perm_b32 v9, v10, v102, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v101, v38, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v98, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
+; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
; GFX11-NEXT: v_perm_b32 v14, v103, v112, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v12, v23, 16, v12
+; GFX11-NEXT: v_or_b32_e32 v12, v12, v23
; GFX11-NEXT: v_perm_b32 v23, v99, v100, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v97, v37, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v98, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v96, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v5, v5, v87, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
; GFX11-NEXT: v_perm_b32 v10, v85, v86, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v83, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v8, v23, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v9, v24, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v23
+; GFX11-NEXT: v_or_b32_e32 v9, v5, v24
; GFX11-NEXT: v_perm_b32 v5, v84, v31, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v80, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v71, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v25, v39, v50, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v6, v83, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v31, v1, v32, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v26, v2, v26, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v23, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v3, v24, 16, v31
-; GFX11-NEXT: v_lshl_or_b32 v4, v25, 16, v26
+; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v23
+; GFX11-NEXT: v_or_b32_e32 v3, v31, v24
+; GFX11-NEXT: v_or_b32_e32 v4, v26, v25
; GFX11-NEXT: s_clause 0x5
; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
@@ -187111,12 +188667,19 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:772 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v10, v37, v36, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v59, v34, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v57, v32, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v47, v46, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v43, v42, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v55, v54, s6
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v16, v51, v50, s6
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
; VI-NEXT: ; implicit-def: $vgpr59
@@ -187138,14 +188701,16 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:780 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:788 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:792 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:796 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:752 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:756 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187154,7 +188719,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:764 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:736 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:740 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187163,7 +188729,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:748 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v5, v4, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:720 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:724 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187172,7 +188739,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:732 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v5, v6, v5, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:704 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:708 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187181,7 +188749,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:716 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v6, v7, v6, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187190,7 +188759,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187199,22 +188769,24 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:832 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v9, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_perm_b32 v8, v38, v61, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_perm_b32 v9, v39, v62, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_perm_b32 v8, v38, v61, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v35, v60, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v33, v58, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v63, v56, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v45, v44, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v41, v40, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_perm_b32 v14, v53, v52, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:836 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr61
@@ -187233,7 +188805,7 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr52
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v49, v15, s6
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:800 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:804 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr49
@@ -187245,14 +188817,16 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v17, v18, v17, s6
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:812 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:820 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_or_b32_e32 v16, v16, v17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v18, v19, v18, s6
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:824 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:828 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v17, v18, v19
; VI-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187261,7 +188835,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v19, v20, v19, s6
-; VI-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v18, v19
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187270,7 +188845,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v20, v21, v20, s6
-; VI-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v19, v19, v20
; VI-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187279,7 +188855,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v21, v22, v21, s6
-; VI-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v20, v20, v21
; VI-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187288,7 +188865,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v22, v23, v22, s6
-; VI-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v21, v21, v22
; VI-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187297,7 +188875,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v23, v23, v24, s6
-; VI-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_or_b32_e32 v22, v22, v23
; VI-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187306,7 +188885,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v24, v25, v24, s6
-; VI-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; VI-NEXT: v_or_b32_e32 v23, v23, v24
; VI-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187315,7 +188895,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v25, v25, v26, s6
-; VI-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v24, v25
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187324,7 +188905,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s6
-; VI-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v25, v26
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187333,7 +188915,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v28, v27, s6
-; VI-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v26, v27
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187342,7 +188925,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v29, v28, s6
-; VI-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v27, v28
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187351,7 +188935,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v30, v29, s6
-; VI-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v28, v29
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187360,7 +188945,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v30, v31, v30, s6
-; VI-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; VI-NEXT: v_or_b32_e32 v29, v29, v30
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -187369,7 +188955,8 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v30, v31
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
@@ -187434,13 +189021,14 @@ define <64 x i16> @bitcast_v128i8_to_v64i16(<128 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: ; kill: killed $vgpr48
-; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v32, v33, v32, s6
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
-; VI-NEXT: v_lshl_or_b32 v31, v32, 16, v31
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v32
+; VI-NEXT: ; kill: killed $vgpr48
+; VI-NEXT: ; implicit-def: $vgpr48
+; VI-NEXT: v_or_b32_e32 v31, v31, v32
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; kill: killed $vgpr48
; VI-NEXT: ; implicit-def: $vgpr48
@@ -192901,70 +194489,82 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; VI-NEXT: s_cbranch_scc0 .LBB97_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v1, s19
+; VI-NEXT: v_mov_b32_e32 v3, s23
+; VI-NEXT: v_mov_b32_e32 v0, s17
+; VI-NEXT: v_perm_b32 v1, s18, v1, v11
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
; VI-NEXT: v_mov_b32_e32 v2, s21
-; VI-NEXT: v_mov_b32_e32 v3, s23
+; VI-NEXT: v_perm_b32 v3, s22, v3, v11
; VI-NEXT: v_perm_b32 v0, s16, v0, v11
-; VI-NEXT: v_perm_b32 v1, s18, v1, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, s20, v2, v11
-; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s8, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s7
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s10
-; VI-NEXT: v_perm_b32 v4, s11, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_perm_b32 v5, s14, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s13
+; VI-NEXT: v_perm_b32 v4, s11, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s41
-; VI-NEXT: v_perm_b32 v5, s42, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s13
; VI-NEXT: v_perm_b32 v6, s46, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s45
+; VI-NEXT: v_perm_b32 v5, s42, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s57
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s45
; VI-NEXT: v_perm_b32 v7, s63, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s62
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s61
-; VI-NEXT: v_perm_b32 v7, s74, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s62
; VI-NEXT: v_perm_b32 v8, s73, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s9
+; VI-NEXT: v_perm_b32 v7, s74, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s12
-; VI-NEXT: v_perm_b32 v8, s76, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s9
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s15
+; VI-NEXT: v_perm_b32 v8, s76, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v43, v10
; VI-NEXT: v_mov_b32_e32 v10, s43
-; VI-NEXT: v_perm_b32 v9, s44, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s15
; VI-NEXT: v_perm_b32 v10, s56, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s47
+; VI-NEXT: v_perm_b32 v9, s44, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v35, v12
; VI-NEXT: v_mov_b32_e32 v12, s59
-; VI-NEXT: v_perm_b32 v10, s60, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s47
; VI-NEXT: v_perm_b32 v12, s72, v12, v11
+; VI-NEXT: v_perm_b32 v10, s60, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s75, v13, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v15, v14, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s75, v13, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
@@ -192973,22 +194573,26 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v23, v51, v33, s4
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v12, v56, v12, s4
-; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_perm_b32 v14, v59, v14, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v13, v47, v13, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; VI-NEXT: v_perm_b32 v14, v59, v14, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v15, v32, v15, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v61, v13, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v17, v60, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v21, v16, s4
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v17, v28, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v21, v58, v46, s4
; VI-NEXT: v_perm_b32 v24, v36, v49, s4
; VI-NEXT: v_mov_b32_e32 v28, v52
@@ -192996,36 +194600,44 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v16, v19, v16, s4
; VI-NEXT: v_perm_b32 v19, v26, v22, s4
-; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v19
+; VI-NEXT: v_or_b32_e32 v17, v19, v17
; VI-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_perm_b32 v16, v25, v20, s4
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v16, v16, 16, v18
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v16, v18, v16
; VI-NEXT: v_perm_b32 v18, v45, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; VI-NEXT: v_perm_b32 v20, v44, v29, s4
; VI-NEXT: v_perm_b32 v22, v53, v42, s4
; VI-NEXT: v_mov_b32_e32 v45, v34
; VI-NEXT: buffer_load_dword v44, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(3)
; VI-NEXT: v_perm_b32 v19, v30, v19, s4
-; VI-NEXT: v_lshl_or_b32 v18, v18, 16, v19
+; VI-NEXT: v_or_b32_e32 v18, v19, v18
; VI-NEXT: v_perm_b32 v19, v55, v31, s4
-; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_or_b32_e32 v19, v20, v19
; VI-NEXT: v_perm_b32 v20, v39, v57, s4
-; VI-NEXT: v_lshl_or_b32 v20, v20, 16, v21
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; VI-NEXT: v_or_b32_e32 v20, v21, v20
; VI-NEXT: v_perm_b32 v21, v38, v63, s4
-; VI-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v21, v22, v21
; VI-NEXT: v_perm_b32 v22, v54, v37, s4
-; VI-NEXT: v_lshl_or_b32 v22, v22, 16, v23
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v22, v23, v22
; VI-NEXT: v_perm_b32 v23, v40, v50, s4
-; VI-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; VI-NEXT: v_or_b32_e32 v23, v24, v23
; VI-NEXT: v_perm_b32 v24, v48, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_mov_b32_e32 v48, v25
; VI-NEXT: v_perm_b32 v25, v25, v41, s4
-; VI-NEXT: v_lshl_or_b32 v24, v24, 16, v25
+; VI-NEXT: v_or_b32_e32 v24, v25, v24
; VI-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v34, v33
; VI-NEXT: v_mov_b32_e32 v33, v26
@@ -193037,40 +194649,45 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v25, v26, v25, s4
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
-; VI-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; VI-NEXT: v_or_b32_e32 v25, v26, v25
; VI-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v26, v27, v26, s4
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v26
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
-; VI-NEXT: v_lshl_or_b32 v26, v26, 16, v27
+; VI-NEXT: v_or_b32_e32 v26, v27, v26
; VI-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v27, v29, v27, s4
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v28, v28, v29, s4
-; VI-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; VI-NEXT: v_or_b32_e32 v27, v28, v27
; VI-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v28, v28, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v28
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v62, v29, s4
-; VI-NEXT: v_lshl_or_b32 v28, v28, 16, v29
+; VI-NEXT: v_or_b32_e32 v28, v29, v28
; VI-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; VI-NEXT: v_mov_b32_e32 v62, v44
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v29, v43, v29, s4
-; VI-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; VI-NEXT: v_or_b32_e32 v29, v30, v29
; VI-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
@@ -193078,16 +194695,18 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; VI-NEXT: v_perm_b32 v30, v31, v30, s4
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v30, 16, v30
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
-; VI-NEXT: v_lshl_or_b32 v30, v30, 16, v31
+; VI-NEXT: v_or_b32_e32 v30, v31, v30
; VI-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v31, v35, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v31, 16, v31
; VI-NEXT: v_mov_b32_e32 v35, v43
; VI-NEXT: v_perm_b32 v43, v44, v43, s4
-; VI-NEXT: v_lshl_or_b32 v31, v31, 16, v43
+; VI-NEXT: v_or_b32_e32 v31, v43, v31
; VI-NEXT: v_mov_b32_e32 v43, v39
; VI-NEXT: v_mov_b32_e32 v39, v34
; VI-NEXT: v_mov_b32_e32 v34, v52
@@ -194587,11 +196206,12 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB97_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
@@ -194605,117 +196225,134 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, s88 :: v_dual_and_b32 v29, 0xff, v166
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v37, 8, v10
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v86, 8, s88
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v70, 8, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v33, 8, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v32, 8, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v39, 8, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v119, 8, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v82, 8, v26
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v64, 8, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v128, 8, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v101, 8, v28
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v87, 8, v10
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v150, 8, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v102, 8, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v132, 8, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v183, v129, 8, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v41, v133, 8, v29
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v178, 8, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
@@ -195087,11 +196724,10 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s74, 0xff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v33
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v48
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
@@ -195107,52 +196743,61 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s11, s8, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v35
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v35, 8, s76
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s76, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v33, 8, v11
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v32, 8, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v37
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v9, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v49
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v36
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v11, 16, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v37, 8, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v15
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v34
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v36, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v34, 8, v14
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v14, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v82, v64, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v14
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v9, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v96, v85, 0xc0c0004
@@ -195162,18 +196807,18 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v117
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v144
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v10, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v84, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v19, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v87, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v135
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v150
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v11, 16, v9
@@ -195189,72 +196834,82 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_or_b32 s77, s78, s79
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v11, 16, v22
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v117, 8, v24
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v134
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v119
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-FAKE16-NEXT: s_and_b32 s77, s62, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v114, 8, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v119, 8, v10
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s59, 8
; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s45, 8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v24, v25
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v114
; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_and_b32 s78, s56, 0xff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v24, v25
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
; GFX11-FAKE16-NEXT: s_and_b32 s79, s63, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s61, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v144, 8, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v147, 8, v10
; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v147
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v133, 8, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v26, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v133
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v26, v27
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v177
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v164
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v27, 16, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v151
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v164, 8, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v135, 8, v28
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v28, v29
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v176
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v161
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v161, 8, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v28, v29
; GFX11-FAKE16-NEXT: v_perm_b32 v28, v179, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v11, 16, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v165
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v29, 16, v30
; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v178
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v165, 8, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v166, 8, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v150, 8, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v30, v31
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v166
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v11, v31
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v40
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB97_3
@@ -197960,151 +199615,181 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB98_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v31, 3
-; VI-NEXT: v_add_u16_e32 v32, 3, v18
; VI-NEXT: v_add_u16_sdwa v55, v18, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v32, 3, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v55
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v18, v55, 16, v32
+; VI-NEXT: v_or_b32_e32 v18, v32, v18
; VI-NEXT: v_add_u16_e32 v32, 3, v17
; VI-NEXT: v_add_u16_sdwa v17, v17, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; VI-NEXT: v_add_u16_sdwa v54, v20, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v17, v17, 16, v32
+; VI-NEXT: v_or_b32_e32 v17, v32, v17
; VI-NEXT: v_add_u16_e32 v32, 3, v20
-; VI-NEXT: v_add_u16_sdwa v54, v20, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v20, 16, v54
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v20, v54, 16, v32
+; VI-NEXT: v_or_b32_e32 v20, v32, v20
; VI-NEXT: v_add_u16_e32 v32, 3, v19
; VI-NEXT: v_add_u16_sdwa v19, v19, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; VI-NEXT: v_lshlrev_b32_e32 v19, 16, v19
+; VI-NEXT: v_add_u16_sdwa v57, v22, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v19, v19, 16, v32
+; VI-NEXT: v_or_b32_e32 v19, v32, v19
; VI-NEXT: v_add_u16_e32 v32, 3, v22
-; VI-NEXT: v_add_u16_sdwa v57, v22, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v57
+; VI-NEXT: v_add_u16_sdwa v52, v21, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v22, v57, 16, v32
+; VI-NEXT: v_or_b32_e32 v22, v32, v22
; VI-NEXT: v_add_u16_e32 v32, 3, v21
-; VI-NEXT: v_add_u16_sdwa v52, v21, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v52
+; VI-NEXT: v_add_u16_sdwa v56, v24, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v21, v52, 16, v32
+; VI-NEXT: v_or_b32_e32 v21, v32, v21
; VI-NEXT: v_add_u16_e32 v32, 3, v24
-; VI-NEXT: v_add_u16_sdwa v56, v24, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v24, 16, v56
+; VI-NEXT: v_add_u16_sdwa v50, v23, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v24, v56, 16, v32
+; VI-NEXT: v_or_b32_e32 v24, v32, v24
; VI-NEXT: v_add_u16_e32 v32, 3, v23
-; VI-NEXT: v_add_u16_sdwa v50, v23, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v23, 16, v50
+; VI-NEXT: v_add_u16_sdwa v49, v26, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v23, v50, 16, v32
+; VI-NEXT: v_or_b32_e32 v23, v32, v23
; VI-NEXT: v_add_u16_e32 v32, 3, v26
-; VI-NEXT: v_add_u16_sdwa v49, v26, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v26, 16, v49
+; VI-NEXT: v_add_u16_sdwa v59, v25, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v26, v49, 16, v32
+; VI-NEXT: v_or_b32_e32 v26, v32, v26
; VI-NEXT: v_add_u16_e32 v32, 3, v25
-; VI-NEXT: v_add_u16_sdwa v59, v25, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v25, 16, v59
+; VI-NEXT: v_add_u16_sdwa v38, v28, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v25, v59, 16, v32
+; VI-NEXT: v_or_b32_e32 v25, v32, v25
; VI-NEXT: v_add_u16_e32 v32, 3, v28
-; VI-NEXT: v_add_u16_sdwa v38, v28, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v28, 16, v38
+; VI-NEXT: v_add_u16_sdwa v35, v27, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v28, v38, 16, v32
+; VI-NEXT: v_or_b32_e32 v28, v32, v28
; VI-NEXT: v_add_u16_e32 v32, 3, v27
-; VI-NEXT: v_add_u16_sdwa v35, v27, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v33, 3, v29
-; VI-NEXT: v_add_u16_sdwa v34, v29, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v27, 16, v35
+; VI-NEXT: v_add_u16_sdwa v48, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v27, v35, 16, v32
+; VI-NEXT: v_or_b32_e32 v27, v32, v27
; VI-NEXT: v_add_u16_e32 v32, 3, v30
-; VI-NEXT: v_add_u16_sdwa v48, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v33, 3, v29
+; VI-NEXT: v_add_u16_sdwa v34, v29, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v48
+; VI-NEXT: v_or_b32_e32 v30, v32, v29
+; VI-NEXT: v_lshlrev_b32_e32 v29, 16, v34
+; VI-NEXT: v_add_u16_sdwa v53, v37, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v29, v34, 16, v33
+; VI-NEXT: v_or_b32_e32 v29, v33, v29
; VI-NEXT: v_add_u16_e32 v34, 3, v37
-; VI-NEXT: v_add_u16_sdwa v53, v37, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v39, 3, v36
; VI-NEXT: v_add_u16_sdwa v33, v36, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v30, v48, 16, v32
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v53
+; VI-NEXT: v_add_u16_e32 v39, 3, v36
+; VI-NEXT: v_or_b32_e32 v37, v34, v32
+; VI-NEXT: v_lshlrev_b32_e32 v32, 16, v33
+; VI-NEXT: v_add_u16_sdwa v47, v2, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v37, v53, 16, v34
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v36, v33, 16, v39
+; VI-NEXT: v_or_b32_e32 v36, v39, v32
; VI-NEXT: v_add_u16_e32 v33, 3, v2
-; VI-NEXT: v_add_u16_sdwa v47, v2, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v34, 3, v1
; VI-NEXT: v_add_u16_sdwa v32, v1, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v47
+; VI-NEXT: v_or_b32_e32 v2, v33, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v32
+; VI-NEXT: v_add_u16_sdwa v46, v4, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v2, v47, 16, v33
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v1, v32, 16, v34
+; VI-NEXT: v_or_b32_e32 v1, v34, v1
; VI-NEXT: v_add_u16_e32 v33, 3, v4
-; VI-NEXT: v_add_u16_sdwa v46, v4, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v34, 3, v3
; VI-NEXT: v_add_u16_sdwa v32, v3, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v46
+; VI-NEXT: v_or_b32_e32 v4, v33, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v32
+; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v3, v34, v3
+; VI-NEXT: v_add_u16_sdwa v34, v6, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v4, v46, 16, v33
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v3, v32, 16, v34
; VI-NEXT: v_add_u16_e32 v33, 3, v6
-; VI-NEXT: v_add_u16_sdwa v34, v6, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v39, 3, v5
; VI-NEXT: v_add_u16_sdwa v32, v5, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v34
+; VI-NEXT: v_or_b32_e32 v6, v33, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v32
+; VI-NEXT: v_add_u16_sdwa v62, v8, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v6, v34, 16, v33
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v5, v32, 16, v39
+; VI-NEXT: v_or_b32_e32 v5, v39, v5
; VI-NEXT: v_add_u16_e32 v39, 3, v8
-; VI-NEXT: v_add_u16_sdwa v62, v8, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v33, 3, v7
; VI-NEXT: v_add_u16_sdwa v32, v7, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v62
+; VI-NEXT: v_or_b32_e32 v8, v39, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v32
+; VI-NEXT: v_add_u16_sdwa v61, v10, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v8, v62, 16, v39
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v7, v32, 16, v33
+; VI-NEXT: v_or_b32_e32 v7, v33, v7
+; VI-NEXT: v_add_u16_e32 v33, 3, v10
; VI-NEXT: v_add_u16_e32 v39, 3, v9
; VI-NEXT: v_add_u16_sdwa v32, v9, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v33, 3, v10
-; VI-NEXT: v_add_u16_sdwa v61, v10, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v61
+; VI-NEXT: v_or_b32_e32 v10, v33, v9
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v32
+; VI-NEXT: v_add_u16_sdwa v60, v12, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v9, v32, 16, v39
+; VI-NEXT: v_or_b32_e32 v9, v39, v9
+; VI-NEXT: v_add_u16_e32 v33, 3, v12
; VI-NEXT: v_add_u16_e32 v39, 3, v11
; VI-NEXT: v_add_u16_sdwa v32, v11, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v10, v61, 16, v33
-; VI-NEXT: v_add_u16_e32 v33, 3, v12
-; VI-NEXT: v_add_u16_sdwa v60, v12, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v60
+; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v12, v33, v11
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v32
+; VI-NEXT: v_add_u16_sdwa v33, v14, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v11, v32, 16, v39
+; VI-NEXT: v_or_b32_e32 v11, v39, v11
+; VI-NEXT: v_add_u16_e32 v39, 3, v14
; VI-NEXT: v_add_u16_e32 v40, 3, v13
; VI-NEXT: v_add_u16_sdwa v32, v13, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v33
; VI-NEXT: v_add_u16_sdwa v63, v16, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v16, 3, v16
-; VI-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v12, v60, 16, v33
-; VI-NEXT: v_add_u16_sdwa v33, v14, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v14, v39, v13
; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v13, v32, 16, v40
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v32
; VI-NEXT: v_add_u16_sdwa v31, v15, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v16, 3, v16
; VI-NEXT: v_add_u16_e32 v32, 3, v15
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v63
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v16, v63, 16, v16
+; VI-NEXT: v_or_b32_e32 v16, v16, v15
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v31
; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
-; VI-NEXT: v_lshl_or_b32 v15, v31, 16, v32
+; VI-NEXT: v_or_b32_e32 v15, v32, v15
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v16
; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v31, 8, v15
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[15:16]
-; VI-NEXT: v_add_u16_e32 v39, 3, v14
-; VI-NEXT: v_lshl_or_b32 v14, v33, 16, v39
; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; VI-NEXT: v_or_b32_e32 v13, v40, v13
; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v14
; VI-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v15, 8, v13
@@ -198136,6 +199821,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v4
+; VI-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v3
@@ -198212,6 +199898,7 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; VI-NEXT: v_bfe_u32 v1, v49, 8, 8
; VI-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; VI-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[39:40], 24, v[23:24]
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v56, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
@@ -198243,7 +199930,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v41, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
@@ -198252,7 +199940,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v47, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
@@ -198262,7 +199951,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
@@ -198272,7 +199962,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v46, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
@@ -198282,9 +199973,10 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
@@ -198294,7 +199986,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v34, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
@@ -198304,9 +199997,10 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
@@ -198316,7 +200010,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v62, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
@@ -198326,9 +200021,10 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
@@ -198338,7 +200034,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v61, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
@@ -198348,9 +200045,10 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -198360,7 +200058,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v60, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
@@ -198370,9 +200069,10 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
@@ -198382,7 +200082,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v33, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
@@ -198392,9 +200093,10 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
@@ -198404,7 +200106,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v63, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
@@ -198413,14 +200116,16 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v44, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v58, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v57, v48, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v40, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
@@ -198429,7 +200134,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v1, v43, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v32, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
@@ -198437,7 +200143,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: v_perm_b32 v2, v55, v49, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
@@ -198445,7 +200152,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: v_perm_b32 v2, v52, v42, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x50, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
@@ -198453,7 +200161,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: v_perm_b32 v2, v51, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x54, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
@@ -198461,7 +200170,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v1, v2, s4
; VI-NEXT: v_perm_b32 v2, v50, v39, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x58, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -198471,7 +200181,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v56, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x5c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
@@ -198482,7 +200193,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v59, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x60, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
@@ -198493,7 +200205,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x64, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
@@ -198504,7 +200217,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v35, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x68, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
@@ -198514,7 +200228,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v45, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x6c, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
@@ -198526,7 +200241,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x70, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
@@ -198537,7 +200253,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x74, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
@@ -198549,7 +200266,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 0x78, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
@@ -198560,7 +200278,8 @@ define <128 x i8> @bitcast_v64i16_to_v128i8(<64 x i16> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v53, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
@@ -202514,99 +204233,114 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 27
; VI-NEXT: v_mov_b32_e32 v24, s16
; VI-NEXT: v_readlane_b32 s16, v33, 28
-; VI-NEXT: v_mov_b32_e32 v13, s38
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v24, s16, v24, v1
+; VI-NEXT: v_or_b32_e32 v3, v3, v10
+; VI-NEXT: v_mov_b32_e32 v13, s38
; VI-NEXT: v_readlane_b32 s16, v33, 26
+; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v24
; VI-NEXT: v_perm_b32 v13, s16, v13, v1
; VI-NEXT: v_readlane_b32 s16, v33, 24
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: v_mov_b32_e32 v25, s16
; VI-NEXT: v_readlane_b32 s16, v33, 25
-; VI-NEXT: v_mov_b32_e32 v16, s36
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
; VI-NEXT: v_perm_b32 v25, s16, v25, v1
+; VI-NEXT: v_or_b32_e32 v2, v5, v2
+; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
+; VI-NEXT: v_mov_b32_e32 v16, s36
; VI-NEXT: v_readlane_b32 s16, v33, 23
+; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v25
; VI-NEXT: v_perm_b32 v16, s16, v16, v1
; VI-NEXT: v_readlane_b32 s16, v33, 21
+; VI-NEXT: v_or_b32_e32 v2, v4, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
; VI-NEXT: v_mov_b32_e32 v26, s16
; VI-NEXT: v_readlane_b32 s16, v33, 22
-; VI-NEXT: v_mov_b32_e32 v19, s34
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v16
; VI-NEXT: v_perm_b32 v26, s16, v26, v1
+; VI-NEXT: v_or_b32_e32 v2, v7, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
+; VI-NEXT: v_mov_b32_e32 v19, s34
; VI-NEXT: v_readlane_b32 s16, v33, 20
-; VI-NEXT: v_lshl_or_b32 v3, v10, 16, v3
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
; VI-NEXT: v_perm_b32 v19, s16, v19, v1
; VI-NEXT: v_readlane_b32 s16, v33, 18
-; VI-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v24, 16, v2
-; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
+; VI-NEXT: v_or_b32_e32 v2, v6, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
; VI-NEXT: v_mov_b32_e32 v27, s16
; VI-NEXT: v_readlane_b32 s16, v33, 19
-; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v13, 16, v5
-; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
-; VI-NEXT: v_mov_b32_e32 v20, s30
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
; VI-NEXT: v_perm_b32 v27, s16, v27, v1
+; VI-NEXT: v_or_b32_e32 v2, v9, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
+; VI-NEXT: v_mov_b32_e32 v20, s30
; VI-NEXT: v_readlane_b32 s16, v33, 17
-; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v25, 16, v4
-; VI-NEXT: v_add_u32_e32 v4, vcc, 12, v0
+; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v27
; VI-NEXT: v_perm_b32 v20, s16, v20, v1
; VI-NEXT: v_readlane_b32 s16, v33, 15
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v16, 16, v7
-; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
+; VI-NEXT: v_or_b32_e32 v2, v8, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
; VI-NEXT: v_mov_b32_e32 v28, s16
; VI-NEXT: v_readlane_b32 s16, v33, 16
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v26, 16, v6
-; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
-; VI-NEXT: v_mov_b32_e32 v21, s90
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
; VI-NEXT: v_perm_b32 v28, s16, v28, v1
+; VI-NEXT: v_or_b32_e32 v2, v12, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
+; VI-NEXT: v_mov_b32_e32 v21, s90
; VI-NEXT: v_readlane_b32 s16, v33, 13
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v19, 16, v9
-; VI-NEXT: v_add_u32_e32 v4, vcc, 24, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v28
; VI-NEXT: v_perm_b32 v21, s16, v21, v1
; VI-NEXT: v_readlane_b32 s16, v33, 10
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v27, 16, v8
-; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
+; VI-NEXT: v_or_b32_e32 v2, v11, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
; VI-NEXT: v_mov_b32_e32 v29, s16
; VI-NEXT: v_readlane_b32 s16, v33, 11
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v20, 16, v12
-; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
-; VI-NEXT: v_mov_b32_e32 v22, s88
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
; VI-NEXT: v_perm_b32 v29, s16, v29, v1
+; VI-NEXT: v_or_b32_e32 v2, v15, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
+; VI-NEXT: v_mov_b32_e32 v22, s88
; VI-NEXT: v_readlane_b32 s16, v33, 8
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v28, 16, v11
-; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
; VI-NEXT: v_perm_b32 v22, s16, v22, v1
; VI-NEXT: v_readlane_b32 s16, v33, 5
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v21, 16, v15
-; VI-NEXT: v_add_u32_e32 v4, vcc, 40, v0
+; VI-NEXT: v_or_b32_e32 v2, v14, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
; VI-NEXT: v_perm_b32 v18, s28, v17, v1
; VI-NEXT: v_mov_b32_e32 v30, s16
; VI-NEXT: v_readlane_b32 s16, v33, 6
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v29, 16, v14
-; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
-; VI-NEXT: v_perm_b32 v17, s29, v23, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
; VI-NEXT: v_perm_b32 v30, s16, v30, v1
; VI-NEXT: v_readlane_b32 s16, v33, 4
-; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v22, 16, v18
+; VI-NEXT: v_or_b32_e32 v2, v18, v2
; VI-NEXT: v_add_u32_e32 v4, vcc, 48, v0
+; VI-NEXT: v_perm_b32 v17, s29, v23, v1
; VI-NEXT: v_mov_b32_e32 v23, s78
; VI-NEXT: v_mov_b32_e32 v31, s16
; VI-NEXT: v_readlane_b32 s16, v33, 3
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
-; VI-NEXT: v_lshl_or_b32 v2, v30, 16, v17
-; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v30
; VI-NEXT: v_perm_b32 v3, s16, v23, v1
+; VI-NEXT: v_or_b32_e32 v2, v17, v2
+; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
; VI-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, s44, v31, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: v_readlane_b32 s16, v33, 2
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202614,37 +204348,42 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s16, v33, 0
; VI-NEXT: v_mov_b32_e32 v3, s16
; VI-NEXT: v_readlane_b32 s16, v33, 1
-; VI-NEXT: v_perm_b32 v2, s45, v2, v1
; VI-NEXT: v_perm_b32 v3, s16, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s45, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 60, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_mov_b32_e32 v3, s76
-; VI-NEXT: v_perm_b32 v2, s42, v2, v1
+; VI-NEXT: v_mov_b32_e32 v2, s70
; VI-NEXT: v_perm_b32 v3, s53, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s42, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 64, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v2, s52
; VI-NEXT: v_mov_b32_e32 v3, s55
-; VI-NEXT: v_perm_b32 v2, s43, v2, v1
+; VI-NEXT: v_mov_b32_e32 v2, s52
; VI-NEXT: v_perm_b32 v3, s65, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s43, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x44, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v2, s85
; VI-NEXT: v_mov_b32_e32 v3, s74
-; VI-NEXT: v_perm_b32 v2, s40, v2, v1
+; VI-NEXT: v_mov_b32_e32 v2, s85
; VI-NEXT: v_perm_b32 v3, s50, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s40, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x48, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v2, s51
; VI-NEXT: v_mov_b32_e32 v3, s84
-; VI-NEXT: v_perm_b32 v2, s41, v2, v1
+; VI-NEXT: v_mov_b32_e32 v2, s51
; VI-NEXT: v_perm_b32 v3, s80, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s41, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x4c, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v2, s83
@@ -202652,16 +204391,18 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: v_readlane_b32 s14, v33, 57
; VI-NEXT: v_perm_b32 v3, s14, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x50, v0
; VI-NEXT: v_readlane_b32 s14, v33, 55
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v2, s69
; VI-NEXT: v_mov_b32_e32 v3, s14
; VI-NEXT: v_readlane_b32 s14, v33, 56
-; VI-NEXT: v_perm_b32 v2, s15, v2, v1
+; VI-NEXT: v_mov_b32_e32 v2, s69
; VI-NEXT: v_perm_b32 v3, s14, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s15, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x54, v0
; VI-NEXT: v_readlane_b32 s14, v33, 54
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202670,7 +204411,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s62
; VI-NEXT: v_readlane_b32 s12, v33, 53
; VI-NEXT: v_perm_b32 v3, s12, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x58, v0
; VI-NEXT: v_readlane_b32 s12, v33, 52
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202678,9 +204420,10 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s12, v33, 50
; VI-NEXT: v_mov_b32_e32 v3, s12
; VI-NEXT: v_readlane_b32 s12, v33, 51
-; VI-NEXT: v_perm_b32 v2, s13, v2, v1
; VI-NEXT: v_perm_b32 v3, s12, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s13, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x5c, v0
; VI-NEXT: v_readlane_b32 s12, v33, 49
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202689,7 +204432,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s60
; VI-NEXT: v_readlane_b32 s10, v33, 48
; VI-NEXT: v_perm_b32 v3, s10, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x60, v0
; VI-NEXT: v_readlane_b32 s10, v33, 47
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202697,9 +204441,10 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s10, v33, 45
; VI-NEXT: v_mov_b32_e32 v3, s10
; VI-NEXT: v_readlane_b32 s10, v33, 46
-; VI-NEXT: v_perm_b32 v2, s11, v2, v1
; VI-NEXT: v_perm_b32 v3, s10, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s11, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x64, v0
; VI-NEXT: v_readlane_b32 s10, v33, 44
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202708,7 +204453,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s58
; VI-NEXT: v_readlane_b32 s8, v33, 43
; VI-NEXT: v_perm_b32 v3, s8, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x68, v0
; VI-NEXT: v_readlane_b32 s8, v33, 42
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202716,9 +204462,10 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s8, v33, 40
; VI-NEXT: v_mov_b32_e32 v3, s8
; VI-NEXT: v_readlane_b32 s8, v33, 41
-; VI-NEXT: v_perm_b32 v2, s9, v2, v1
; VI-NEXT: v_perm_b32 v3, s8, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s9, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x6c, v0
; VI-NEXT: v_readlane_b32 s8, v33, 39
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202727,7 +204474,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_readlane_b32 s6, v33, 38
; VI-NEXT: v_perm_b32 v3, s6, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x70, v0
; VI-NEXT: v_readlane_b32 s6, v33, 37
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202735,9 +204483,10 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s6, v33, 35
; VI-NEXT: v_mov_b32_e32 v3, s6
; VI-NEXT: v_readlane_b32 s6, v33, 36
-; VI-NEXT: v_perm_b32 v2, s7, v2, v1
; VI-NEXT: v_perm_b32 v3, s6, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, s7, v2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x74, v0
; VI-NEXT: v_readlane_b32 s6, v33, 34
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202746,7 +204495,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_mov_b32_e32 v3, s46
; VI-NEXT: v_readlane_b32 s4, v33, 33
; VI-NEXT: v_perm_b32 v3, s4, v3, v1
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 0x78, v0
; VI-NEXT: v_readlane_b32 s4, v33, 32
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
@@ -202756,7 +204506,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; VI-NEXT: v_readlane_b32 s4, v33, 31
; VI-NEXT: v_perm_b32 v2, s5, v2, v1
; VI-NEXT: v_perm_b32 v1, s4, v3, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7c, v0
; VI-NEXT: v_readlane_b32 s30, v32, 30
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -203853,8 +205604,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v39, v39, v44, s4
-; GFX9-NEXT: v_lshl_or_b32 v39, v39, 16, v48
-; GFX9-NEXT: v_lshl_or_b32 v37, v50, 16, v37
+; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
+; GFX9-NEXT: v_or_b32_e32 v39, v48, v39
; GFX9-NEXT: v_perm_b32 v23, v34, v23, s4
; GFX9-NEXT: v_perm_b32 v32, v32, v59, s4
; GFX9-NEXT: v_perm_b32 v29, v29, v57, s4
@@ -203908,7 +205659,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: v_perm_b32 v18, v18, v54, s4
; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshl_or_b32 v18, v18, 16, v21
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v18, v21, v18
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_perm_b32 v38, v47, v52, s4
; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
@@ -203939,17 +205691,22 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v39, v39, v48, s4
-; GFX9-NEXT: v_lshl_or_b32 v39, v39, 16, v49
+; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
+; GFX9-NEXT: v_or_b32_e32 v39, v49, v39
; GFX9-NEXT: buffer_store_dword v39, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v50
+; GFX9-NEXT: v_or_b32_e32 v37, v37, v39
; GFX9-NEXT: buffer_store_dword v37, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v37, v37, v39, s4
-; GFX9-NEXT: v_lshl_or_b32 v24, v37, 16, v24
+; GFX9-NEXT: v_lshlrev_b32_e32 v37, 16, v37
+; GFX9-NEXT: v_or_b32_e32 v24, v24, v37
; GFX9-NEXT: buffer_store_dword v24, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: buffer_store_dword v18, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
@@ -203957,66 +205714,79 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v18, v18, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v18, 16, v16
+; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v16, v16, v18
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshl_or_b32 v16, v35, 16, v33
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v35
+; GFX9-NEXT: v_or_b32_e32 v16, v33, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v23
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshl_or_b32 v16, v34, 16, v31
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v34
+; GFX9-NEXT: v_or_b32_e32 v16, v31, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v32
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v32, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshl_or_b32 v16, v36, 16, v29
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v36
+; GFX9-NEXT: v_or_b32_e32 v16, v29, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v30
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v30, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshl_or_b32 v16, v38, 16, v27
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v38
+; GFX9-NEXT: v_or_b32_e32 v16, v27, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v17
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshl_or_b32 v16, v28, 16, v22
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28
+; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v25
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v25, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshl_or_b32 v16, v26, 16, v19
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26
+; GFX9-NEXT: v_or_b32_e32 v16, v19, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v16, v16, 16, v20
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v16, v20, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v15, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204025,7 +205795,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v14, v15, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204035,7 +205806,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204044,7 +205816,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204054,7 +205827,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204063,7 +205837,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v10, v11, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204073,7 +205848,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204082,7 +205858,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204092,7 +205869,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204101,7 +205879,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v6, v7, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204111,7 +205890,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -204120,7 +205900,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -204128,11 +205909,13 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_perm_b32 v1, v2, v41, s4
; GFX9-NEXT: v_perm_b32 v2, v40, v42, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -204827,105 +206610,136 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX11-NEXT: v_mov_b32_e32 v148, s0
; GFX11-NEXT: .LBB99_5: ; %end
; GFX11-NEXT: v_perm_b32 v68, v73, v70, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v35, v35, v63, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v70, v62, v72, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v69, v60, v69, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v70
+; GFX11-NEXT: v_perm_b32 v35, v35, v63, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
; GFX11-NEXT: v_perm_b32 v56, v33, v56, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
; GFX11-NEXT: v_perm_b32 v58, v58, v59, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v57, v34, v57, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v33, v68, 16, v35
-; GFX11-NEXT: v_lshl_or_b32 v34, v70, 16, v36
-; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v35, v69, 16, v56
+; GFX11-NEXT: v_or_b32_e32 v34, v36, v70
; GFX11-NEXT: v_perm_b32 v29, v29, v45, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v65
+; GFX11-NEXT: v_perm_b32 v70, v27, v182, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
+; GFX11-NEXT: v_or_b32_e32 v33, v35, v68
+; GFX11-NEXT: v_or_b32_e32 v35, v56, v69
; GFX11-NEXT: v_perm_b32 v68, v44, v46, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v30, v30, v40, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v69, v41, v42, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v70, v27, v182, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v182, v28, v183, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v36, v58, 16, v57
-; GFX11-NEXT: v_lshl_or_b32 v27, v65, 16, v29
-; GFX11-NEXT: v_lshl_or_b32 v28, v68, 16, v30
-; GFX11-NEXT: v_lshl_or_b32 v29, v64, 16, v70
-; GFX11-NEXT: v_lshl_or_b32 v30, v69, 16, v182
+; GFX11-NEXT: v_lshlrev_b32_e32 v58, 16, v58
+; GFX11-NEXT: v_or_b32_e32 v27, v29, v65
+; GFX11-NEXT: v_or_b32_e32 v29, v70, v64
; GFX11-NEXT: v_perm_b32 v54, v181, v54, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v64, v179, v180, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v23, v177, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v53, v178, v53, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v30, v40, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
+; GFX11-NEXT: v_perm_b32 v182, v28, v183, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
+; GFX11-NEXT: v_or_b32_e32 v36, v57, v58
+; GFX11-NEXT: v_perm_b32 v23, v23, v177, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v54
; GFX11-NEXT: v_perm_b32 v24, v24, v167, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
; GFX11-NEXT: v_perm_b32 v21, v21, v176, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v53
+; GFX11-NEXT: v_or_b32_e32 v28, v30, v68
+; GFX11-NEXT: v_or_b32_e32 v30, v182, v69
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: scratch_store_b128 v0, v[33:36], off
; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:16
-; GFX11-NEXT: v_perm_b32 v30, v160, v51, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v27, v54, 16, v23
+; GFX11-NEXT: v_or_b32_e32 v27, v23, v54
; GFX11-NEXT: v_perm_b32 v23, v165, v166, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v28, v64, 16, v24
-; GFX11-NEXT: v_lshl_or_b32 v29, v53, 16, v21
+; GFX11-NEXT: v_or_b32_e32 v28, v24, v64
+; GFX11-NEXT: v_or_b32_e32 v29, v21, v53
; GFX11-NEXT: v_perm_b32 v21, v22, v164, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v163, v52, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v161, v162, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v160, v51, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v17, v17, v150, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v30
-; GFX11-NEXT: v_lshl_or_b32 v30, v23, 16, v21
-; GFX11-NEXT: v_lshl_or_b32 v19, v22, 16, v19
+; GFX11-NEXT: v_or_b32_e32 v30, v21, v23
+; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
; GFX11-NEXT: v_perm_b32 v22, v147, v148, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v20, v24, 16, v20
+; GFX11-NEXT: v_or_b32_e32 v20, v20, v24
; GFX11-NEXT: v_or_b32_e32 v21, v17, v33
; GFX11-NEXT: v_perm_b32 v17, v18, v146, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v145, v67, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v15, v134, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v133, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v131, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v135, v144, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-NEXT: v_perm_b32 v15, v15, v134, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v13, v13, v131, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v16, v16, v132, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v22, v22, 16, v17
-; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
+; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
; GFX11-NEXT: v_perm_b32 v18, v129, v130, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v17, v24, 16, v13
-; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v17, v13, v24
; GFX11-NEXT: v_perm_b32 v24, v115, v48, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v9, v113, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v16, v23, 16, v16
+; GFX11-NEXT: v_or_b32_e32 v16, v16, v23
+; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v14, v119, v49, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v117, v118, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_perm_b32 v9, v9, v113, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v11, v11, v116, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v114, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v13
-; GFX11-NEXT: v_lshl_or_b32 v13, v24, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
+; GFX11-NEXT: v_or_b32_e32 v13, v9, v24
; GFX11-NEXT: v_perm_b32 v9, v10, v102, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v101, v38, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v98, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
+; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
; GFX11-NEXT: v_perm_b32 v14, v103, v112, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v12, v23, 16, v12
+; GFX11-NEXT: v_or_b32_e32 v12, v12, v23
; GFX11-NEXT: v_perm_b32 v23, v99, v100, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v97, v37, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v98, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v96, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v5, v5, v87, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
; GFX11-NEXT: v_perm_b32 v10, v85, v86, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v83, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v8, v23, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v9, v24, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v23
+; GFX11-NEXT: v_or_b32_e32 v9, v5, v24
; GFX11-NEXT: v_perm_b32 v5, v84, v31, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v23, v80, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v71, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v25, v39, v50, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v6, v83, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
; GFX11-NEXT: v_perm_b32 v31, v1, v32, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
; GFX11-NEXT: v_perm_b32 v26, v2, v26, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v23, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v3, v24, 16, v31
-; GFX11-NEXT: v_lshl_or_b32 v4, v25, 16, v26
+; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v23
+; GFX11-NEXT: v_or_b32_e32 v3, v31, v24
+; GFX11-NEXT: v_or_b32_e32 v4, v26, v25
; GFX11-NEXT: s_clause 0x5
; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index 9e9b7ab09c7d7..7e231f48de12a 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -4107,18 +4107,22 @@ define <4 x i32> @bitcast_v16i8_to_v4i32(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB26_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v19, v18, s6
; VI-NEXT: v_perm_b32 v1, v17, v20, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v19, v18, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -4605,27 +4609,31 @@ define inreg <4 x i32> @bitcast_v16i8_to_v4i32_scalar(<16 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB27_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v3
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v3
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v4, s26, v4, v3
-; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v2, v2, v4
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: s_cbranch_execnz .LBB27_3
; VI-NEXT: .LBB27_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -4684,27 +4692,31 @@ define inreg <4 x i32> @bitcast_v16i8_to_v4i32_scalar(<16 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
-; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -8622,18 +8634,22 @@ define <4 x float> @bitcast_v16i8_to_v4f32(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB50_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v19, v18, s6
; VI-NEXT: v_perm_b32 v1, v17, v20, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v19, v18, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -9120,27 +9136,31 @@ define inreg <4 x float> @bitcast_v16i8_to_v4f32_scalar(<16 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v3
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v3
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v4, s26, v4, v3
-; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v2, v2, v4
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -9199,27 +9219,31 @@ define inreg <4 x float> @bitcast_v16i8_to_v4f32_scalar(<16 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
-; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -12722,18 +12746,22 @@ define <2 x i64> @bitcast_v16i8_to_v2i64(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB70_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v19, v18, s6
; VI-NEXT: v_perm_b32 v1, v17, v20, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v19, v18, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -13220,27 +13248,31 @@ define inreg <2 x i64> @bitcast_v16i8_to_v2i64_scalar(<16 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB71_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v3
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v3
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v4, s26, v4, v3
-; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v2, v2, v4
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: s_cbranch_execnz .LBB71_3
; VI-NEXT: .LBB71_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -13299,27 +13331,31 @@ define inreg <2 x i64> @bitcast_v16i8_to_v2i64_scalar(<16 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
-; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -16460,18 +16496,22 @@ define <2 x double> @bitcast_v16i8_to_v2f64(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB86_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v19, v18, s6
; VI-NEXT: v_perm_b32 v1, v17, v20, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v19, v18, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -16958,27 +16998,31 @@ define inreg <2 x double> @bitcast_v16i8_to_v2f64_scalar(<16 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB87_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v3
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v3
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v4, s26, v4, v3
-; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v2, v2, v4
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: s_cbranch_execnz .LBB87_3
; VI-NEXT: .LBB87_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -17037,27 +17081,31 @@ define inreg <2 x double> @bitcast_v16i8_to_v2f64_scalar(<16 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
-; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -19222,18 +19270,22 @@ define <16 x i8> @bitcast_v8i16_to_v16i8(<8 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB96_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v3, 3
-; VI-NEXT: v_add_u16_e32 v17, 3, v1
; VI-NEXT: v_add_u16_sdwa v6, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v16, 3, v0
; VI-NEXT: v_add_u16_sdwa v2, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v21, 3, v19
; VI-NEXT: v_add_u16_sdwa v14, v19, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v8, 3, v18
; VI-NEXT: v_add_u16_sdwa v10, v18, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v17
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v16
-; VI-NEXT: v_lshl_or_b32 v19, v14, 16, v21
-; VI-NEXT: v_lshl_or_b32 v18, v10, 16, v8
+; VI-NEXT: v_add_u16_e32 v17, 3, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; VI-NEXT: v_add_u16_e32 v16, 3, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; VI-NEXT: v_add_u16_e32 v21, 3, v19
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
+; VI-NEXT: v_add_u16_e32 v8, 3, v18
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
+; VI-NEXT: v_or_b32_e32 v1, v17, v1
+; VI-NEXT: v_or_b32_e32 v0, v16, v0
+; VI-NEXT: v_or_b32_e32 v19, v21, v4
+; VI-NEXT: v_or_b32_e32 v18, v8, v3
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[18:19]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v19
@@ -19963,18 +20015,22 @@ define <8 x i16> @bitcast_v16i8_to_v8i16(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB98_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v19, v18, s6
; VI-NEXT: v_perm_b32 v1, v17, v20, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v19, v18, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -20488,27 +20544,31 @@ define inreg <8 x i16> @bitcast_v16i8_to_v8i16_scalar(<16 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB99_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v3
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v3
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v4, s26, v4, v3
-; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v2, v2, v4
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: s_cbranch_execnz .LBB99_3
; VI-NEXT: .LBB99_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -20567,27 +20627,31 @@ define inreg <8 x i16> @bitcast_v16i8_to_v8i16_scalar(<16 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB99_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
-; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
; GFX9-NEXT: s_cbranch_execnz .LBB99_3
; GFX9-NEXT: .LBB99_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -22182,17 +22246,21 @@ define <16 x i8> @bitcast_v8f16_to_v16i8(<8 x half> %a, i32 %b) #0 {
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v3, 0x200
; VI-NEXT: v_add_f16_sdwa v6, v19, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
; VI-NEXT: v_add_f16_e32 v19, 0x200, v19
; VI-NEXT: v_add_f16_sdwa v2, v18, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v18, 0x200, v18
; VI-NEXT: v_add_f16_sdwa v14, v17, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v17, 0x200, v17
; VI-NEXT: v_add_f16_sdwa v10, v16, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v1, v19, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; VI-NEXT: v_add_f16_e32 v18, 0x200, v18
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
+; VI-NEXT: v_add_f16_e32 v17, 0x200, v17
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v19
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v18
-; VI-NEXT: v_lshl_or_b32 v8, v14, 16, v17
-; VI-NEXT: v_lshl_or_b32 v7, v10, 16, v16
+; VI-NEXT: v_or_b32_e32 v0, v18, v0
+; VI-NEXT: v_or_b32_e32 v8, v17, v4
+; VI-NEXT: v_or_b32_e32 v7, v16, v3
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[7:8]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v8
@@ -22553,19 +22621,23 @@ define inreg <16 x i8> @bitcast_v8f16_to_v16i8_scalar(<8 x half> inreg %a, i32 i
; VI-NEXT: v_mov_b32_e32 v1, 0x200
; VI-NEXT: v_add_f16_e32 v6, s4, v1
; VI-NEXT: s_lshr_b32 s4, s16, 16
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
+; VI-NEXT: v_add_f16_e32 v17, s17, v1
; VI-NEXT: v_add_f16_e32 v2, s4, v1
; VI-NEXT: s_lshr_b32 s4, s19, 16
+; VI-NEXT: v_or_b32_e32 v19, v17, v0
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; VI-NEXT: v_add_f16_e32 v0, s16, v1
; VI-NEXT: v_add_f16_e32 v14, s4, v1
; VI-NEXT: s_lshr_b32 s4, s18, 16
-; VI-NEXT: v_add_f16_e32 v17, s17, v1
-; VI-NEXT: v_add_f16_e32 v0, s16, v1
+; VI-NEXT: v_or_b32_e32 v18, v0, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
; VI-NEXT: v_add_f16_e32 v16, s19, v1
; VI-NEXT: v_add_f16_e32 v10, s4, v1
+; VI-NEXT: v_or_b32_e32 v21, v16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; VI-NEXT: v_add_f16_e32 v8, s18, v1
-; VI-NEXT: v_lshl_or_b32 v19, v6, 16, v17
-; VI-NEXT: v_lshl_or_b32 v18, v2, 16, v0
-; VI-NEXT: v_lshl_or_b32 v21, v14, 16, v16
-; VI-NEXT: v_lshl_or_b32 v20, v10, 16, v8
+; VI-NEXT: v_or_b32_e32 v20, v8, v3
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[20:21]
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[18:19]
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v21
@@ -22939,18 +23011,22 @@ define <8 x half> @bitcast_v16i8_to_v8f16(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB106_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v19, v18, s6
; VI-NEXT: v_perm_b32 v1, v17, v20, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v19, v18, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -23464,27 +23540,31 @@ define inreg <8 x half> @bitcast_v16i8_to_v8f16_scalar(<16 x i8> inreg %a, i32 i
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB107_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v3
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v3
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v4, s26, v4, v3
-; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v2, v2, v4
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: s_cbranch_execnz .LBB107_3
; VI-NEXT: .LBB107_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -23543,27 +23623,31 @@ define inreg <8 x half> @bitcast_v16i8_to_v8f16_scalar(<16 x i8> inreg %a, i32 i
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB107_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
-; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
; GFX9-NEXT: s_cbranch_execnz .LBB107_3
; GFX9-NEXT: .LBB107_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -25232,18 +25316,22 @@ define <8 x bfloat> @bitcast_v16i8_to_v8bf16(<16 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB110_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v19, v18, s6
; VI-NEXT: v_perm_b32 v1, v17, v20, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v19, v18, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: ; implicit-def: $vgpr19
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; implicit-def: $vgpr17
@@ -25753,27 +25841,31 @@ define inreg <8 x bfloat> @bitcast_v16i8_to_v8bf16_scalar(<16 x i8> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s7, v0
; VI-NEXT: s_cbranch_scc0 .LBB111_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v3
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v3
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v3
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v4, s26, v4, v3
-; VI-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; VI-NEXT: v_perm_b32 v2, s24, v2, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v2, v2, v4
; VI-NEXT: v_mov_b32_e32 v4, s29
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s28, v4, v3
; VI-NEXT: v_perm_b32 v3, s7, v5, v3
-; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: s_cbranch_execnz .LBB111_3
; VI-NEXT: .LBB111_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -25832,27 +25924,31 @@ define inreg <8 x bfloat> @bitcast_v16i8_to_v8bf16_scalar(<16 x i8> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB111_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
-; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
; GFX9-NEXT: s_cbranch_execnz .LBB111_3
; GFX9-NEXT: .LBB111_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index cfa0d58088341..224b73353c3bc 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -6267,31 +6267,39 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB26_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v38, v37, s6
; VI-NEXT: v_perm_b32 v1, v36, v35, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v34, v33, s6
+; VI-NEXT: v_perm_b32 v0, v38, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v34, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
@@ -6842,61 +6850,62 @@ define <8 x i32> @bitcast_v32i8_to_v8i32(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
@@ -7193,47 +7202,55 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s47, v0
; VI-NEXT: s_cbranch_scc0 .LBB27_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v7
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v7
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v7
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s47, v4, v7
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s44
+; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s42
-; VI-NEXT: v_perm_b32 v4, s45, v4, v7
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s44
; VI-NEXT: v_perm_b32 v5, s43, v5, v7
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s40
+; VI-NEXT: v_perm_b32 v4, s45, v4, v7
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s14
-; VI-NEXT: v_perm_b32 v5, s41, v5, v7
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s40
; VI-NEXT: v_perm_b32 v6, s15, v6, v7
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s12
+; VI-NEXT: v_perm_b32 v5, s41, v5, v7
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s10
-; VI-NEXT: v_perm_b32 v6, s13, v6, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s12
; VI-NEXT: v_perm_b32 v8, s11, v8, v7
-; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; VI-NEXT: v_perm_b32 v6, s13, v6, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_mov_b32_e32 v8, s8
; VI-NEXT: v_mov_b32_e32 v9, s6
; VI-NEXT: v_perm_b32 v8, s9, v8, v7
; VI-NEXT: v_perm_b32 v7, s7, v9, v7
-; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_cbranch_execnz .LBB27_3
; VI-NEXT: .LBB27_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -7348,47 +7365,55 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s44
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s44
; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s40
+; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s40
; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s12
+; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s12
; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
-; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -7494,31 +7519,33 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB27_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
@@ -7529,40 +7556,43 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-NEXT: .LBB27_2: ; %cmp.true
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
+; GFX11-NEXT: s_add_i32 s22, s22, 3
+; GFX11-NEXT: s_add_i32 s24, s24, 3
+; GFX11-NEXT: s_add_i32 s26, s26, 3
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: s_add_i32 s28, s28, 3
+; GFX11-NEXT: s_add_i32 s41, s41, 3
+; GFX11-NEXT: s_add_i32 s15, s15, 3
+; GFX11-NEXT: s_add_i32 s13, s13, 3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: s_add_i32 s11, s11, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
@@ -13505,31 +13535,39 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB50_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v38, v37, s6
; VI-NEXT: v_perm_b32 v1, v36, v35, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v34, v33, s6
+; VI-NEXT: v_perm_b32 v0, v38, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v34, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
@@ -14080,61 +14118,62 @@ define <8 x float> @bitcast_v32i8_to_v8f32(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
@@ -14431,47 +14470,55 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s47, v0
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v7
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v7
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v7
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s47, v4, v7
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s44
+; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s42
-; VI-NEXT: v_perm_b32 v4, s45, v4, v7
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s44
; VI-NEXT: v_perm_b32 v5, s43, v5, v7
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s40
+; VI-NEXT: v_perm_b32 v4, s45, v4, v7
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s14
-; VI-NEXT: v_perm_b32 v5, s41, v5, v7
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s40
; VI-NEXT: v_perm_b32 v6, s15, v6, v7
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s12
+; VI-NEXT: v_perm_b32 v5, s41, v5, v7
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s10
-; VI-NEXT: v_perm_b32 v6, s13, v6, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s12
; VI-NEXT: v_perm_b32 v8, s11, v8, v7
-; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; VI-NEXT: v_perm_b32 v6, s13, v6, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_mov_b32_e32 v8, s8
; VI-NEXT: v_mov_b32_e32 v9, s6
; VI-NEXT: v_perm_b32 v8, s9, v8, v7
; VI-NEXT: v_perm_b32 v7, s7, v9, v7
-; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -14586,47 +14633,55 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s44
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s44
; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s40
+; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s40
; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s12
+; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s12
; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
-; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -14732,31 +14787,33 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB51_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
@@ -14767,40 +14824,43 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-NEXT: .LBB51_2: ; %cmp.true
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
+; GFX11-NEXT: s_add_i32 s22, s22, 3
+; GFX11-NEXT: s_add_i32 s24, s24, 3
+; GFX11-NEXT: s_add_i32 s26, s26, 3
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: s_add_i32 s28, s28, 3
+; GFX11-NEXT: s_add_i32 s41, s41, 3
+; GFX11-NEXT: s_add_i32 s15, s15, 3
+; GFX11-NEXT: s_add_i32 s13, s13, 3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: s_add_i32 s11, s11, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
@@ -20204,31 +20264,39 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB70_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v38, v37, s6
; VI-NEXT: v_perm_b32 v1, v36, v35, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v34, v33, s6
+; VI-NEXT: v_perm_b32 v0, v38, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v34, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
@@ -20779,61 +20847,62 @@ define <4 x i64> @bitcast_v32i8_to_v4i64(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
@@ -21130,47 +21199,55 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s47, v0
; VI-NEXT: s_cbranch_scc0 .LBB71_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v7
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v7
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v7
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s47, v4, v7
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s44
+; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s42
-; VI-NEXT: v_perm_b32 v4, s45, v4, v7
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s44
; VI-NEXT: v_perm_b32 v5, s43, v5, v7
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s40
+; VI-NEXT: v_perm_b32 v4, s45, v4, v7
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s14
-; VI-NEXT: v_perm_b32 v5, s41, v5, v7
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s40
; VI-NEXT: v_perm_b32 v6, s15, v6, v7
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s12
+; VI-NEXT: v_perm_b32 v5, s41, v5, v7
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s10
-; VI-NEXT: v_perm_b32 v6, s13, v6, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s12
; VI-NEXT: v_perm_b32 v8, s11, v8, v7
-; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; VI-NEXT: v_perm_b32 v6, s13, v6, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_mov_b32_e32 v8, s8
; VI-NEXT: v_mov_b32_e32 v9, s6
; VI-NEXT: v_perm_b32 v8, s9, v8, v7
; VI-NEXT: v_perm_b32 v7, s7, v9, v7
-; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_cbranch_execnz .LBB71_3
; VI-NEXT: .LBB71_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -21285,47 +21362,55 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s44
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s44
; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s40
+; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s40
; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s12
+; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s12
; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
-; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -21431,31 +21516,33 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB71_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
@@ -21466,40 +21553,43 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-NEXT: .LBB71_2: ; %cmp.true
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
+; GFX11-NEXT: s_add_i32 s22, s22, 3
+; GFX11-NEXT: s_add_i32 s24, s24, 3
+; GFX11-NEXT: s_add_i32 s26, s26, 3
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: s_add_i32 s28, s28, 3
+; GFX11-NEXT: s_add_i32 s41, s41, 3
+; GFX11-NEXT: s_add_i32 s15, s15, 3
+; GFX11-NEXT: s_add_i32 s13, s13, 3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: s_add_i32 s11, s11, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
@@ -26436,31 +26526,39 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB86_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v38, v37, s6
; VI-NEXT: v_perm_b32 v1, v36, v35, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v34, v33, s6
+; VI-NEXT: v_perm_b32 v0, v38, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v34, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr37
; VI-NEXT: ; implicit-def: $vgpr36
@@ -27011,61 +27109,62 @@ define <4 x double> @bitcast_v32i8_to_v4f64(<32 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v10, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v6, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v12, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v4, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v14, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 8, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v16, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v15
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v18, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v19
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v20, 3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v26, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v9, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v28, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v30, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, v24, 3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v10, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v27
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v16, 8, v29
@@ -27362,47 +27461,55 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s47, v0
; VI-NEXT: s_cbranch_scc0 .LBB87_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v7
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v7
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v7
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s46
-; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s47, v4, v7
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s44
+; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s42
-; VI-NEXT: v_perm_b32 v4, s45, v4, v7
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s44
; VI-NEXT: v_perm_b32 v5, s43, v5, v7
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s40
+; VI-NEXT: v_perm_b32 v4, s45, v4, v7
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s14
-; VI-NEXT: v_perm_b32 v5, s41, v5, v7
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s40
; VI-NEXT: v_perm_b32 v6, s15, v6, v7
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s12
+; VI-NEXT: v_perm_b32 v5, s41, v5, v7
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s10
-; VI-NEXT: v_perm_b32 v6, s13, v6, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s12
; VI-NEXT: v_perm_b32 v8, s11, v8, v7
-; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; VI-NEXT: v_perm_b32 v6, s13, v6, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_mov_b32_e32 v8, s8
; VI-NEXT: v_mov_b32_e32 v9, s6
; VI-NEXT: v_perm_b32 v8, s9, v8, v7
; VI-NEXT: v_perm_b32 v7, s7, v9, v7
-; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_cbranch_execnz .LBB87_3
; VI-NEXT: .LBB87_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -27517,47 +27624,55 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s44
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s44
; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s40
+; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s40
; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s12
+; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s12
; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
-; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -27663,31 +27778,33 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB87_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
+; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
@@ -27698,40 +27815,43 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-NEXT: .LBB87_2: ; %cmp.true
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-NEXT: s_add_i32 s18, s18, 3
; GFX11-NEXT: s_add_i32 s0, s0, 3
+; GFX11-NEXT: s_add_i32 s2, s2, 3
; GFX11-NEXT: s_add_i32 s16, s16, 3
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: s_add_i32 s20, s20, 3
-; GFX11-NEXT: s_add_i32 s2, s2, 3
+; GFX11-NEXT: s_add_i32 s22, s22, 3
+; GFX11-NEXT: s_add_i32 s24, s24, 3
+; GFX11-NEXT: s_add_i32 s26, s26, 3
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: s_add_i32 s28, s28, 3
+; GFX11-NEXT: s_add_i32 s41, s41, 3
+; GFX11-NEXT: s_add_i32 s15, s15, 3
+; GFX11-NEXT: s_add_i32 s13, s13, 3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
-; GFX11-NEXT: s_add_i32 s18, s18, 3
-; GFX11-NEXT: s_add_i32 s22, s22, 3
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
+; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
-; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u32_e32 v6, 0x300, v6
+; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-NEXT: s_add_i32 s24, s24, 3
-; GFX11-NEXT: s_add_i32 s26, s26, 3
-; GFX11-NEXT: s_add_i32 s28, s28, 3
-; GFX11-NEXT: s_add_i32 s41, s41, 3
-; GFX11-NEXT: s_add_i32 s15, s15, 3
-; GFX11-NEXT: s_add_i32 s13, s13, 3
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: s_add_i32 s11, s11, 3
; GFX11-NEXT: s_add_i32 s9, s9, 3
; GFX11-NEXT: s_add_i32 s7, s7, 3
; GFX11-NEXT: s_add_i32 s5, s5, 3
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
+; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: v_perm_b32 v4, s24, s25, v3
; GFX11-NEXT: v_perm_b32 v5, s26, s27, v3
; GFX11-NEXT: v_perm_b32 v6, s28, s29, v3
@@ -31189,30 +31309,38 @@ define <32 x i8> @bitcast_v16i16_to_v32i8(<16 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB96_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v9, 3
-; VI-NEXT: v_add_u16_e32 v48, 3, v1
; VI-NEXT: v_add_u16_sdwa v36, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v50, 3, v0
; VI-NEXT: v_add_u16_sdwa v32, v0, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v35, 3, v3
; VI-NEXT: v_add_u16_sdwa v14, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v8, 3, v2
; VI-NEXT: v_add_u16_sdwa v10, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v49, 3, v5
; VI-NEXT: v_add_u16_sdwa v22, v5, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v16, 3, v4
; VI-NEXT: v_add_u16_sdwa v18, v4, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v51, 3, v7
; VI-NEXT: v_add_u16_sdwa v30, v7, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v24, 3, v6
; VI-NEXT: v_add_u16_sdwa v26, v6, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v1, v36, 16, v48
-; VI-NEXT: v_lshl_or_b32 v0, v32, 16, v50
-; VI-NEXT: v_lshl_or_b32 v3, v14, 16, v35
-; VI-NEXT: v_lshl_or_b32 v2, v10, 16, v8
-; VI-NEXT: v_lshl_or_b32 v5, v22, 16, v49
-; VI-NEXT: v_lshl_or_b32 v4, v18, 16, v16
-; VI-NEXT: v_lshl_or_b32 v7, v30, 16, v51
-; VI-NEXT: v_lshl_or_b32 v6, v26, 16, v24
+; VI-NEXT: v_add_u16_e32 v48, 3, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v36
+; VI-NEXT: v_add_u16_e32 v50, 3, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v32
+; VI-NEXT: v_add_u16_e32 v35, 3, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v14
+; VI-NEXT: v_add_u16_e32 v8, 3, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
+; VI-NEXT: v_add_u16_e32 v49, 3, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v22
+; VI-NEXT: v_add_u16_e32 v16, 3, v4
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v18
+; VI-NEXT: v_add_u16_e32 v51, 3, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v30
+; VI-NEXT: v_add_u16_e32 v24, 3, v6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v26
+; VI-NEXT: v_or_b32_e32 v1, v48, v1
+; VI-NEXT: v_or_b32_e32 v0, v50, v0
+; VI-NEXT: v_or_b32_e32 v3, v35, v3
+; VI-NEXT: v_or_b32_e32 v2, v8, v2
+; VI-NEXT: v_or_b32_e32 v5, v49, v5
+; VI-NEXT: v_or_b32_e32 v4, v16, v4
+; VI-NEXT: v_or_b32_e32 v7, v51, v7
+; VI-NEXT: v_or_b32_e32 v6, v24, v6
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[6:7]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[4:5]
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3]
@@ -32492,31 +32620,39 @@ define <16 x i16> @bitcast_v32i8_to_v16i16(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB98_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v32, v38, s6
; VI-NEXT: v_perm_b32 v1, v34, v35, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v36, v37, s6
+; VI-NEXT: v_perm_b32 v0, v32, v38, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v31, v33, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v36, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr34
@@ -33478,47 +33614,55 @@ define inreg <16 x i16> @bitcast_v32i8_to_v16i16_scalar(<32 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s10, v0
; VI-NEXT: s_cbranch_scc0 .LBB99_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v7
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v7
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v7
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s10, v4, v7
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s7
+; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s8
-; VI-NEXT: v_perm_b32 v4, s9, v4, v7
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_perm_b32 v5, s12, v5, v7
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s11
+; VI-NEXT: v_perm_b32 v4, s9, v4, v7
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s13
-; VI-NEXT: v_perm_b32 v5, s14, v5, v7
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_perm_b32 v6, s40, v6, v7
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s15
+; VI-NEXT: v_perm_b32 v5, s14, v5, v7
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v6, s42, v6, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s15
; VI-NEXT: v_perm_b32 v8, s44, v8, v7
-; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; VI-NEXT: v_perm_b32 v6, s42, v6, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_mov_b32_e32 v9, s46
; VI-NEXT: v_perm_b32 v8, s45, v8, v7
; VI-NEXT: v_perm_b32 v7, s47, v9, v7
-; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_cbranch_execnz .LBB99_3
; VI-NEXT: .LBB99_2: ; %cmp.true
; VI-NEXT: s_add_i32 s47, s47, 3
@@ -36590,30 +36734,38 @@ define <32 x i8> @bitcast_v16f16_to_v32i8(<16 x half> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB104_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v5, 0x200
-; VI-NEXT: v_add_f16_sdwa v36, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
-; VI-NEXT: v_add_f16_sdwa v2, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
; VI-NEXT: v_add_f16_sdwa v14, v33, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_sdwa v36, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v14
; VI-NEXT: v_add_f16_e32 v33, 0x200, v33
; VI-NEXT: v_add_f16_sdwa v10, v32, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v36
+; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
+; VI-NEXT: v_or_b32_e32 v12, v33, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; VI-NEXT: v_add_f16_e32 v32, 0x200, v32
; VI-NEXT: v_add_f16_sdwa v22, v35, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v4, v1, v2
+; VI-NEXT: v_add_f16_sdwa v2, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v11, v32, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v22
; VI-NEXT: v_add_f16_e32 v35, 0x200, v35
; VI-NEXT: v_add_f16_sdwa v18, v34, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v34, 0x200, v34
; VI-NEXT: v_add_f16_sdwa v30, v7, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_add_f16_sdwa v26, v6, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
+; VI-NEXT: v_or_b32_e32 v9, v35, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v18
+; VI-NEXT: v_add_f16_e32 v34, 0x200, v34
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v30
+; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
-; VI-NEXT: v_lshl_or_b32 v4, v36, 16, v1
-; VI-NEXT: v_lshl_or_b32 v3, v2, 16, v0
-; VI-NEXT: v_lshl_or_b32 v12, v14, 16, v33
-; VI-NEXT: v_lshl_or_b32 v11, v10, 16, v32
-; VI-NEXT: v_lshl_or_b32 v9, v22, 16, v35
-; VI-NEXT: v_lshl_or_b32 v8, v18, 16, v34
-; VI-NEXT: v_lshl_or_b32 v16, v30, 16, v7
-; VI-NEXT: v_lshl_or_b32 v15, v26, 16, v6
+; VI-NEXT: v_or_b32_e32 v3, v0, v3
+; VI-NEXT: v_or_b32_e32 v8, v34, v8
+; VI-NEXT: v_or_b32_e32 v16, v7, v13
+; VI-NEXT: v_or_b32_e32 v15, v6, v5
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[15:16]
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v9
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[8:9]
@@ -37235,31 +37387,39 @@ define inreg <32 x i8> @bitcast_v16f16_to_v32i8_scalar(<16 x half> inreg %a, i32
; VI-NEXT: s_lshr_b32 s4, s19, 16
; VI-NEXT: v_add_f16_e32 v14, s4, v1
; VI-NEXT: s_lshr_b32 s4, s18, 16
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v14
+; VI-NEXT: v_add_f16_e32 v34, s19, v1
; VI-NEXT: v_add_f16_e32 v10, s4, v1
; VI-NEXT: s_lshr_b32 s4, s21, 16
+; VI-NEXT: v_or_b32_e32 v12, v34, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v10
+; VI-NEXT: v_add_f16_e32 v8, s18, v1
; VI-NEXT: v_add_f16_e32 v22, s4, v1
; VI-NEXT: s_lshr_b32 s4, s20, 16
+; VI-NEXT: v_or_b32_e32 v11, v8, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v22
+; VI-NEXT: v_add_f16_e32 v33, s21, v1
; VI-NEXT: v_add_f16_e32 v18, s4, v1
; VI-NEXT: s_lshr_b32 s4, s23, 16
+; VI-NEXT: v_or_b32_e32 v20, v33, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v18
+; VI-NEXT: v_add_f16_e32 v16, s20, v1
; VI-NEXT: v_add_f16_e32 v30, s4, v1
; VI-NEXT: s_lshr_b32 s4, s22, 16
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
; VI-NEXT: v_add_f16_e32 v35, s17, v1
-; VI-NEXT: v_add_f16_e32 v0, s16, v1
-; VI-NEXT: v_add_f16_e32 v34, s19, v1
-; VI-NEXT: v_add_f16_e32 v8, s18, v1
-; VI-NEXT: v_add_f16_e32 v33, s21, v1
-; VI-NEXT: v_add_f16_e32 v16, s20, v1
+; VI-NEXT: v_or_b32_e32 v19, v16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v30
; VI-NEXT: v_add_f16_e32 v32, s23, v1
; VI-NEXT: v_add_f16_e32 v26, s4, v1
+; VI-NEXT: v_or_b32_e32 v4, v35, v0
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; VI-NEXT: v_add_f16_e32 v0, s16, v1
+; VI-NEXT: v_or_b32_e32 v37, v32, v5
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v26
; VI-NEXT: v_add_f16_e32 v24, s22, v1
-; VI-NEXT: v_lshl_or_b32 v4, v6, 16, v35
-; VI-NEXT: v_lshl_or_b32 v3, v2, 16, v0
-; VI-NEXT: v_lshl_or_b32 v12, v14, 16, v34
-; VI-NEXT: v_lshl_or_b32 v11, v10, 16, v8
-; VI-NEXT: v_lshl_or_b32 v20, v22, 16, v33
-; VI-NEXT: v_lshl_or_b32 v19, v18, 16, v16
-; VI-NEXT: v_lshl_or_b32 v37, v30, 16, v32
-; VI-NEXT: v_lshl_or_b32 v36, v26, 16, v24
+; VI-NEXT: v_or_b32_e32 v3, v0, v3
+; VI-NEXT: v_or_b32_e32 v36, v24, v5
; VI-NEXT: v_lshrrev_b64 v[27:28], 24, v[36:37]
; VI-NEXT: v_lshrrev_b32_e32 v21, 8, v20
; VI-NEXT: v_lshrrev_b32_e32 v17, 8, v19
@@ -37919,31 +38079,39 @@ define <16 x half> @bitcast_v32i8_to_v16f16(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB106_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v32, v38, s6
; VI-NEXT: v_perm_b32 v1, v34, v35, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v36, v37, s6
+; VI-NEXT: v_perm_b32 v0, v32, v38, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v31, v33, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v36, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr34
@@ -38905,47 +39073,55 @@ define inreg <16 x half> @bitcast_v32i8_to_v16f16_scalar(<32 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s10, v0
; VI-NEXT: s_cbranch_scc0 .LBB107_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v7
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v7
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v7
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s10, v4, v7
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s7
+; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s8
-; VI-NEXT: v_perm_b32 v4, s9, v4, v7
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_perm_b32 v5, s12, v5, v7
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s11
+; VI-NEXT: v_perm_b32 v4, s9, v4, v7
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s13
-; VI-NEXT: v_perm_b32 v5, s14, v5, v7
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_perm_b32 v6, s40, v6, v7
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s15
+; VI-NEXT: v_perm_b32 v5, s14, v5, v7
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v6, s42, v6, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s15
; VI-NEXT: v_perm_b32 v8, s44, v8, v7
-; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; VI-NEXT: v_perm_b32 v6, s42, v6, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_mov_b32_e32 v9, s46
; VI-NEXT: v_perm_b32 v8, s45, v8, v7
; VI-NEXT: v_perm_b32 v7, s47, v9, v7
-; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_cbranch_execnz .LBB107_3
; VI-NEXT: .LBB107_2: ; %cmp.true
; VI-NEXT: s_add_i32 s47, s47, 3
@@ -42291,31 +42467,39 @@ define <16 x bfloat> @bitcast_v32i8_to_v16bf16(<32 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB110_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v32, v38, s6
; VI-NEXT: v_perm_b32 v1, v34, v35, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v36, v37, s6
+; VI-NEXT: v_perm_b32 v0, v32, v38, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v31, v33, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v36, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v39, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: ; implicit-def: $vgpr32
; VI-NEXT: ; implicit-def: $vgpr38
; VI-NEXT: ; implicit-def: $vgpr34
@@ -43269,47 +43453,55 @@ define inreg <16 x bfloat> @bitcast_v32i8_to_v16bf16_scalar(<32 x i8> inreg %a,
; VI-NEXT: v_readfirstlane_b32 s10, v0
; VI-NEXT: s_cbranch_scc0 .LBB111_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v7
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v7
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v7
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v7
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v7
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v7
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s10, v4, v7
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s7
+; VI-NEXT: v_perm_b32 v3, s28, v3, v7
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s8
-; VI-NEXT: v_perm_b32 v4, s9, v4, v7
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_perm_b32 v5, s12, v5, v7
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s11
+; VI-NEXT: v_perm_b32 v4, s9, v4, v7
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s13
-; VI-NEXT: v_perm_b32 v5, s14, v5, v7
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_perm_b32 v6, s40, v6, v7
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s15
+; VI-NEXT: v_perm_b32 v5, s14, v5, v7
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v8, s41
-; VI-NEXT: v_perm_b32 v6, s42, v6, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s15
; VI-NEXT: v_perm_b32 v8, s44, v8, v7
-; VI-NEXT: v_lshl_or_b32 v6, v8, 16, v6
+; VI-NEXT: v_perm_b32 v6, s42, v6, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v6, v6, v8
; VI-NEXT: v_mov_b32_e32 v8, s43
; VI-NEXT: v_mov_b32_e32 v9, s46
; VI-NEXT: v_perm_b32 v8, s45, v8, v7
; VI-NEXT: v_perm_b32 v7, s47, v9, v7
-; VI-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v7, v8, v7
; VI-NEXT: s_cbranch_execnz .LBB111_3
; VI-NEXT: .LBB111_2: ; %cmp.true
; VI-NEXT: s_add_i32 s47, s47, 3
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index 576ce576c73e1..aba9755a4f357 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -2734,51 +2734,61 @@ define <40 x i8> @bitcast_v10i32_to_v40i8(<10 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v48, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
-; VI-NEXT: v_lshl_or_b32 v1, v15, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v1, v1, v15
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v39, s4
; VI-NEXT: v_perm_b32 v2, v38, v37, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v3, v36, s4
; VI-NEXT: v_perm_b32 v2, v35, v14, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v3, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v34, s4
; VI-NEXT: v_perm_b32 v2, v33, v32, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v31, s4
; VI-NEXT: v_perm_b32 v2, v30, v13, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v29, s4
; VI-NEXT: v_perm_b32 v2, v28, v27, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v26, s4
; VI-NEXT: v_perm_b32 v2, v25, v12, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v26, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v24, s4
; VI-NEXT: v_perm_b32 v2, v23, v22, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v21, s4
; VI-NEXT: v_perm_b32 v2, v20, v11, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v21, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v19, s4
; VI-NEXT: v_perm_b32 v2, v18, v17, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -3562,74 +3572,84 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; VI-NEXT: s_lshr_b32 s75, s16, 16
; VI-NEXT: s_lshr_b32 s76, s16, 8
; VI-NEXT: .LBB13_3: ; %end
-; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s12
-; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_perm_b32 v3, s75, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s74
-; VI-NEXT: v_mov_b32_e32 v3, s72
-; VI-NEXT: v_perm_b32 v1, s17, v1, v2
; VI-NEXT: v_perm_b32 v3, s73, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s17, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_mov_b32_e32 v3, s10
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_perm_b32 v3, s62, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s61
; VI-NEXT: v_mov_b32_e32 v3, s59
-; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s61
; VI-NEXT: v_perm_b32 v3, s60, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_mov_b32_e32 v3, s8
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_perm_b32 v3, s57, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s56
; VI-NEXT: v_mov_b32_e32 v3, s46
-; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s56
; VI-NEXT: v_perm_b32 v3, s47, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s45
; VI-NEXT: v_mov_b32_e32 v3, s6
-; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s45
; VI-NEXT: v_perm_b32 v3, s44, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s43
; VI-NEXT: v_mov_b32_e32 v3, s41
-; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s43
; VI-NEXT: v_perm_b32 v3, s42, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s40
; VI-NEXT: v_mov_b32_e32 v3, s4
-; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s40
; VI-NEXT: v_perm_b32 v3, s29, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s28
; VI-NEXT: v_mov_b32_e32 v3, s26
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
; VI-NEXT: v_perm_b32 v2, s27, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -3746,66 +3766,76 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; GFX9-NEXT: s_lshr_b32 s75, s16, 16
; GFX9-NEXT: s_lshr_b32 s76, s16, 8
; GFX9-NEXT: .LBB13_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v1, s76
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s12
-; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v1, s76
; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s74
-; GFX9-NEXT: v_mov_b32_e32 v3, s72
-; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s73, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s59
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s61
-; GFX9-NEXT: v_mov_b32_e32 v3, s59
-; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s60, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s58
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s57, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s56
-; GFX9-NEXT: v_mov_b32_e32 v3, s46
-; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s47, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s45
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
-; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s44, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s41
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s43
-; GFX9-NEXT: v_mov_b32_e32 v3, s41
-; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s42, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s40
-; GFX9-NEXT: v_mov_b32_e32 v3, s4
-; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s29, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s28
; GFX9-NEXT: v_mov_b32_e32 v3, s26
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s27, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -3924,37 +3954,47 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; GFX11-NEXT: s_lshr_b32 s62, s0, 8
; GFX11-NEXT: .LBB13_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v6, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v1, s0, s62, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v2, s61, s12, v6
-; GFX11-NEXT: v_perm_b32 v3, s1, s60, v6
; GFX11-NEXT: v_perm_b32 v4, s59, s58, v6
+; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
+; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
+; GFX11-NEXT: v_perm_b32 v1, s0, s62, v6
+; GFX11-NEXT: v_perm_b32 v3, s1, s60, v6
; GFX11-NEXT: v_perm_b32 v5, s2, s57, v6
-; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
; GFX11-NEXT: v_perm_b32 v8, s3, s47, v6
-; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
; GFX11-NEXT: v_perm_b32 v10, s16, s44, v6
-; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
-; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v3, v7, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: v_perm_b32 v12, s24, s4, v6
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
+; GFX11-NEXT: v_or_b32_e32 v3, v5, v7
; GFX11-NEXT: v_perm_b32 v7, s42, s41, v6
-; GFX11-NEXT: v_lshl_or_b32 v4, v9, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-NEXT: v_or_b32_e32 v4, v8, v9
+; GFX11-NEXT: v_or_b32_e32 v5, v10, v11
; GFX11-NEXT: v_perm_b32 v8, s29, s6, v6
+; GFX11-NEXT: v_perm_b32 v11, s27, s26, v6
+; GFX11-NEXT: v_perm_b32 v14, s22, s14, v6
; GFX11-NEXT: v_perm_b32 v9, s17, s40, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v10, s18, s28, v6
-; GFX11-NEXT: v_perm_b32 v11, s27, s26, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_perm_b32 v13, s19, s25, v6
-; GFX11-NEXT: v_perm_b32 v12, s24, s4, v6
-; GFX11-NEXT: v_perm_b32 v14, s22, s14, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v15, s20, s23, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_perm_b32 v16, s21, s15, v6
-; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v10
-; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v13
-; GFX11-NEXT: v_lshl_or_b32 v9, v12, 16, v15
-; GFX11-NEXT: v_lshl_or_b32 v10, v14, 16, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-NEXT: v_or_b32_e32 v7, v10, v8
+; GFX11-NEXT: v_or_b32_e32 v8, v13, v11
+; GFX11-NEXT: v_or_b32_e32 v9, v15, v12
+; GFX11-NEXT: v_or_b32_e32 v10, v16, v14
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -4337,37 +4377,48 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB14_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v48, v39, s6
; VI-NEXT: v_perm_b32 v1, v38, v37, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v36, v35, s6
+; VI-NEXT: v_perm_b32 v0, v48, v39, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v34, v33, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v32, v31, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v36, v35, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v32, v31, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_perm_b32 v9, v54, v53, s6
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_perm_b32 v9, v54, v53, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_perm_b32 v9, v52, v51, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v50, v49, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v52, v51, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
@@ -5110,11 +5161,12 @@ define <10 x i32> @bitcast_v40i8_to_v10i32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
@@ -5500,57 +5552,67 @@ define inreg <10 x i32> @bitcast_v40i8_to_v10i32_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s63, v0
; VI-NEXT: s_cbranch_scc0 .LBB15_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v9
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v9
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v9
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s62
-; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s63, v4, v9
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s60
+; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_perm_b32 v4, s61, v4, v9
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s60
; VI-NEXT: v_perm_b32 v5, s59, v5, v9
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s56
+; VI-NEXT: v_perm_b32 v4, s61, v4, v9
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_perm_b32 v5, s57, v5, v9
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s56
; VI-NEXT: v_perm_b32 v6, s47, v6, v9
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s44
+; VI-NEXT: v_perm_b32 v5, s57, v5, v9
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s42
-; VI-NEXT: v_perm_b32 v6, s45, v6, v9
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s44
; VI-NEXT: v_perm_b32 v7, s43, v7, v9
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s40
+; VI-NEXT: v_perm_b32 v6, s45, v6, v9
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s14
-; VI-NEXT: v_perm_b32 v7, s41, v7, v9
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s40
; VI-NEXT: v_perm_b32 v8, s15, v8, v9
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s12
+; VI-NEXT: v_perm_b32 v7, s41, v7, v9
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_perm_b32 v8, s13, v8, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s12
; VI-NEXT: v_perm_b32 v10, s11, v10, v9
-; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
+; VI-NEXT: v_perm_b32 v8, s13, v8, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v8, v8, v10
; VI-NEXT: v_mov_b32_e32 v10, s8
; VI-NEXT: v_mov_b32_e32 v11, s6
; VI-NEXT: v_perm_b32 v10, s9, v10, v9
; VI-NEXT: v_perm_b32 v9, s7, v11, v9
-; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: s_cbranch_execnz .LBB15_3
; VI-NEXT: .LBB15_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -5693,57 +5755,67 @@ define inreg <10 x i32> @bitcast_v40i8_to_v10i32_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB15_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s60
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s60
; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s56
+; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s56
; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s44
+; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s44
; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s40
+; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s40
; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s12
+; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s12
; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
-; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
+; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
; GFX9-NEXT: s_cbranch_execnz .LBB15_3
; GFX9-NEXT: .LBB15_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -5875,37 +5947,47 @@ define inreg <10 x i32> @bitcast_v40i8_to_v10i32_scalar(<40 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB15_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
-; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
+; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v12
-; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v14
-; GFX11-NEXT: v_lshl_or_b32 v9, v13, 16, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB15_3
; GFX11-NEXT: .LBB15_2: ; %cmp.true
@@ -9287,51 +9369,61 @@ define <40 x i8> @bitcast_v10f32_to_v40i8(<10 x float> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v48, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
-; VI-NEXT: v_lshl_or_b32 v1, v15, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v1, v1, v15
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v39, s4
; VI-NEXT: v_perm_b32 v2, v38, v37, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v3, v36, s4
; VI-NEXT: v_perm_b32 v2, v35, v14, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v3, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v34, s4
; VI-NEXT: v_perm_b32 v2, v33, v32, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v31, s4
; VI-NEXT: v_perm_b32 v2, v30, v13, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v29, s4
; VI-NEXT: v_perm_b32 v2, v28, v27, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v26, s4
; VI-NEXT: v_perm_b32 v2, v25, v12, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v26, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v24, s4
; VI-NEXT: v_perm_b32 v2, v23, v22, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v21, s4
; VI-NEXT: v_perm_b32 v2, v20, v11, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v21, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v19, s4
; VI-NEXT: v_perm_b32 v2, v18, v17, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -10212,51 +10304,61 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v48, v15, s4
; VI-NEXT: v_perm_b32 v9, v9, v39, s4
-; VI-NEXT: v_lshl_or_b32 v9, v15, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v9, v9, v15
; VI-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v9, v10, v38, s4
; VI-NEXT: v_perm_b32 v10, v36, v37, s4
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_add_u32_e32 v10, vcc, 4, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v7, v7, v35, s4
; VI-NEXT: v_perm_b32 v9, v34, v14, s4
-; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; VI-NEXT: v_perm_b32 v7, v7, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_u32_e32 v9, vcc, 8, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v7, v8, v33, s4
; VI-NEXT: v_perm_b32 v8, v31, v32, s4
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_add_u32_e32 v8, vcc, 12, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v5, v5, v30, s4
; VI-NEXT: v_perm_b32 v7, v29, v13, s4
-; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; VI-NEXT: v_perm_b32 v5, v5, v30, s4
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 16, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v6, v28, s4
; VI-NEXT: v_perm_b32 v6, v26, v27, s4
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 20, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v3, v3, v25, s4
; VI-NEXT: v_perm_b32 v5, v24, v12, s4
-; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; VI-NEXT: v_perm_b32 v3, v3, v25, s4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v3, v3, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 24, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v3, v4, v23, s4
; VI-NEXT: v_perm_b32 v4, v21, v22, s4
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v1, v20, s4
; VI-NEXT: v_perm_b32 v3, v19, v11, s4
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, v1, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v18, s4
; VI-NEXT: v_perm_b32 v2, v16, v17, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -10418,43 +10520,53 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v39, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v38, s4
; GFX9-NEXT: v_perm_b32 v10, v36, v37, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v33, s4
; GFX9-NEXT: v_perm_b32 v8, v31, v32, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v28, s4
; GFX9-NEXT: v_perm_b32 v6, v26, v27, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v23, s4
; GFX9-NEXT: v_perm_b32 v4, v21, v22, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v18, s4
; GFX9-NEXT: v_perm_b32 v2, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10602,8 +10714,8 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX11-NEXT: v_perm_b32 v14, v34, v14, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v15
; GFX11-NEXT: v_perm_b32 v15, v32, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v36
; GFX11-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v14
@@ -10612,15 +10724,17 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX11-NEXT: v_perm_b32 v5, v5, v29, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-NEXT: v_or_b32_e32 v8, v10, v31
-; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v10, v14, v15
; GFX11-NEXT: v_perm_b32 v14, v22, v23, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v13, v5, v13
; GFX11-NEXT: v_perm_b32 v5, v26, v12, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v6, v6, v25, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v27
; GFX11-NEXT: v_perm_b32 v3, v3, v24, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v20, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-NEXT: v_perm_b32 v1, v1, v17, 0xc0c0004
@@ -10628,8 +10742,8 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX11-NEXT: v_perm_b32 v2, v2, v16, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v15
; GFX11-NEXT: v_or_b32_e32 v9, v35, v9
-; GFX11-NEXT: v_lshl_or_b32 v14, v27, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v15, v5, 16, v3
+; GFX11-NEXT: v_or_b32_e32 v14, v6, v12
+; GFX11-NEXT: v_or_b32_e32 v15, v3, v5
; GFX11-NEXT: v_or_b32_e32 v16, v4, v18
; GFX11-NEXT: v_or_b32_e32 v1, v1, v11
; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
@@ -10983,37 +11097,48 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB34_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v48, v39, s6
; VI-NEXT: v_perm_b32 v1, v38, v37, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v36, v35, s6
+; VI-NEXT: v_perm_b32 v0, v48, v39, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v34, v33, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v32, v31, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v36, v35, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v32, v31, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v14, v15, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v12, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_perm_b32 v9, v54, v53, s6
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_perm_b32 v9, v54, v53, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_perm_b32 v9, v52, v51, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v50, v49, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v52, v51, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: ; implicit-def: $vgpr48
; VI-NEXT: ; implicit-def: $vgpr39
; VI-NEXT: ; implicit-def: $vgpr38
@@ -11756,11 +11881,12 @@ define <10 x float> @bitcast_v40i8_to_v10f32(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
@@ -12146,57 +12272,67 @@ define inreg <10 x float> @bitcast_v40i8_to_v10f32_scalar(<40 x i8> inreg %a, i3
; VI-NEXT: v_readfirstlane_b32 s63, v0
; VI-NEXT: s_cbranch_scc0 .LBB35_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v9
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v9
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v9
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s62
-; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s63, v4, v9
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s60
+; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_perm_b32 v4, s61, v4, v9
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s60
; VI-NEXT: v_perm_b32 v5, s59, v5, v9
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s56
+; VI-NEXT: v_perm_b32 v4, s61, v4, v9
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_perm_b32 v5, s57, v5, v9
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s56
; VI-NEXT: v_perm_b32 v6, s47, v6, v9
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s44
+; VI-NEXT: v_perm_b32 v5, s57, v5, v9
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s42
-; VI-NEXT: v_perm_b32 v6, s45, v6, v9
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s44
; VI-NEXT: v_perm_b32 v7, s43, v7, v9
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s40
+; VI-NEXT: v_perm_b32 v6, s45, v6, v9
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s14
-; VI-NEXT: v_perm_b32 v7, s41, v7, v9
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s40
; VI-NEXT: v_perm_b32 v8, s15, v8, v9
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s12
+; VI-NEXT: v_perm_b32 v7, s41, v7, v9
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_perm_b32 v8, s13, v8, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s12
; VI-NEXT: v_perm_b32 v10, s11, v10, v9
-; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
+; VI-NEXT: v_perm_b32 v8, s13, v8, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v8, v8, v10
; VI-NEXT: v_mov_b32_e32 v10, s8
; VI-NEXT: v_mov_b32_e32 v11, s6
; VI-NEXT: v_perm_b32 v10, s9, v10, v9
; VI-NEXT: v_perm_b32 v9, s7, v11, v9
-; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: s_cbranch_execnz .LBB35_3
; VI-NEXT: .LBB35_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -12339,57 +12475,67 @@ define inreg <10 x float> @bitcast_v40i8_to_v10f32_scalar(<40 x i8> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB35_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s60
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s60
; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s56
+; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s56
; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s44
+; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s44
; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s40
+; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s40
; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s12
+; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s12
; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
-; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
+; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
; GFX9-NEXT: s_cbranch_execnz .LBB35_3
; GFX9-NEXT: .LBB35_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -12521,37 +12667,47 @@ define inreg <10 x float> @bitcast_v40i8_to_v10f32_scalar(<40 x i8> inreg %a, i3
; GFX11-NEXT: s_cbranch_scc0 .LBB35_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
-; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
+; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v12
-; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v14
-; GFX11-NEXT: v_lshl_or_b32 v9, v13, 16, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB35_3
; GFX11-NEXT: .LBB35_2: ; %cmp.true
@@ -15369,39 +15525,49 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB48_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v11, 3
-; VI-NEXT: v_add_u16_e32 v42, 3, v10
; VI-NEXT: v_add_u16_sdwa v17, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v43, 3, v9
; VI-NEXT: v_add_u16_sdwa v20, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v54, 3, v8
; VI-NEXT: v_add_u16_sdwa v18, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v40, 3, v7
; VI-NEXT: v_add_u16_sdwa v22, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v10, v17, 16, v42
-; VI-NEXT: v_lshl_or_b32 v9, v20, 16, v43
+; VI-NEXT: v_add_u16_e32 v42, 3, v10
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v17
+; VI-NEXT: v_add_u16_e32 v43, 3, v9
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v20
+; VI-NEXT: v_add_u16_sdwa v19, v6, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v24, v5, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v54, 3, v8
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v18
+; VI-NEXT: v_add_u16_e32 v40, 3, v7
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v22
+; VI-NEXT: v_or_b32_e32 v10, v42, v10
+; VI-NEXT: v_or_b32_e32 v9, v43, v9
; VI-NEXT: v_add_u16_sdwa v23, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v26, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v21, v4, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v25, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v49, 3, v6
-; VI-NEXT: v_add_u16_sdwa v19, v6, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v19
; VI-NEXT: v_add_u16_e32 v51, 3, v5
-; VI-NEXT: v_add_u16_sdwa v24, v5, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v8, v18, 16, v54
-; VI-NEXT: v_lshl_or_b32 v7, v22, 16, v40
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v24
+; VI-NEXT: v_or_b32_e32 v8, v54, v8
+; VI-NEXT: v_or_b32_e32 v7, v40, v7
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[9:10]
; VI-NEXT: v_add_u16_e32 v37, 3, v4
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v21
; VI-NEXT: v_add_u16_e32 v38, 3, v3
-; VI-NEXT: v_lshl_or_b32 v6, v19, 16, v49
-; VI-NEXT: v_lshl_or_b32 v5, v24, 16, v51
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v25
+; VI-NEXT: v_or_b32_e32 v6, v49, v6
+; VI-NEXT: v_or_b32_e32 v5, v51, v5
; VI-NEXT: v_lshrrev_b64 v[12:13], 24, v[7:8]
; VI-NEXT: v_add_u16_e32 v32, 3, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
; VI-NEXT: v_add_u16_e32 v33, 3, v1
-; VI-NEXT: v_lshl_or_b32 v4, v21, 16, v37
-; VI-NEXT: v_lshl_or_b32 v3, v25, 16, v38
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v26
+; VI-NEXT: v_or_b32_e32 v4, v37, v4
+; VI-NEXT: v_or_b32_e32 v3, v38, v3
; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[5:6]
-; VI-NEXT: v_lshl_or_b32 v2, v23, 16, v32
-; VI-NEXT: v_lshl_or_b32 v1, v26, 16, v33
+; VI-NEXT: v_or_b32_e32 v2, v32, v2
+; VI-NEXT: v_or_b32_e32 v1, v33, v1
; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v10
@@ -15422,53 +15588,63 @@ define <40 x i8> @bitcast_v20i16_to_v40i8(<20 x i16> %a, i32 %b) #0 {
; VI-NEXT: .LBB48_4: ; %end
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v1, v33, v55, s4
; VI-NEXT: v_perm_b32 v2, v26, v15, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v33, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v23, v41, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v32, v53, s4
-; VI-NEXT: v_perm_b32 v2, v23, v41, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v38, v50, s4
; VI-NEXT: v_perm_b32 v2, v25, v14, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v38, v50, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v37, v48, s4
; VI-NEXT: v_perm_b32 v2, v21, v52, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v37, v48, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v51, v36, s4
; VI-NEXT: v_perm_b32 v2, v24, v13, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v51, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v49, v34, s4
; VI-NEXT: v_perm_b32 v2, v19, v39, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v49, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v40, v31, s4
; VI-NEXT: v_perm_b32 v2, v22, v12, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v40, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v54, v29, s4
; VI-NEXT: v_perm_b32 v2, v18, v35, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v54, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v43, v28, s4
; VI-NEXT: v_perm_b32 v2, v20, v11, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v43, v28, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v42, v27, s4
; VI-NEXT: v_perm_b32 v2, v17, v30, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v42, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v43, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -16386,74 +16562,84 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; VI-NEXT: s_lshr_b32 s75, s16, 16
; VI-NEXT: s_lshr_b32 s76, s16, 8
; VI-NEXT: .LBB49_3: ; %end
-; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s12
-; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_perm_b32 v3, s75, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s74
-; VI-NEXT: v_mov_b32_e32 v3, s72
-; VI-NEXT: v_perm_b32 v1, s17, v1, v2
; VI-NEXT: v_perm_b32 v3, s73, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s17, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_mov_b32_e32 v3, s10
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_perm_b32 v3, s62, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s61
; VI-NEXT: v_mov_b32_e32 v3, s59
-; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s61
; VI-NEXT: v_perm_b32 v3, s60, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_mov_b32_e32 v3, s8
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_perm_b32 v3, s57, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s56
; VI-NEXT: v_mov_b32_e32 v3, s46
-; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s56
; VI-NEXT: v_perm_b32 v3, s47, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s45
; VI-NEXT: v_mov_b32_e32 v3, s6
-; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s45
; VI-NEXT: v_perm_b32 v3, s44, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s43
; VI-NEXT: v_mov_b32_e32 v3, s41
-; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s43
; VI-NEXT: v_perm_b32 v3, s42, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s40
; VI-NEXT: v_mov_b32_e32 v3, s4
-; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s40
; VI-NEXT: v_perm_b32 v3, s29, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s28
; VI-NEXT: v_mov_b32_e32 v3, s26
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
; VI-NEXT: v_perm_b32 v2, s27, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -16647,43 +16833,53 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v39, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v38, s4
; GFX9-NEXT: v_perm_b32 v10, v36, v37, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v33, s4
; GFX9-NEXT: v_perm_b32 v8, v31, v32, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v28, s4
; GFX9-NEXT: v_perm_b32 v6, v26, v27, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v23, s4
; GFX9-NEXT: v_perm_b32 v4, v21, v22, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v18, s4
; GFX9-NEXT: v_perm_b32 v2, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -16831,8 +17027,8 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v14, v34, v14, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v15
; GFX11-NEXT: v_perm_b32 v15, v32, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v36
; GFX11-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v14
@@ -16841,15 +17037,17 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v5, v5, v29, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-NEXT: v_or_b32_e32 v8, v10, v31
-; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v10, v14, v15
; GFX11-NEXT: v_perm_b32 v14, v22, v23, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v13, v5, v13
; GFX11-NEXT: v_perm_b32 v5, v26, v12, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v6, v6, v25, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v27
; GFX11-NEXT: v_perm_b32 v3, v3, v24, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v20, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-NEXT: v_perm_b32 v1, v1, v17, 0xc0c0004
@@ -16857,8 +17055,8 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v2, v2, v16, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v15
; GFX11-NEXT: v_or_b32_e32 v9, v35, v9
-; GFX11-NEXT: v_lshl_or_b32 v14, v27, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v15, v5, 16, v3
+; GFX11-NEXT: v_or_b32_e32 v14, v6, v12
+; GFX11-NEXT: v_or_b32_e32 v15, v3, v5
; GFX11-NEXT: v_or_b32_e32 v16, v4, v18
; GFX11-NEXT: v_or_b32_e32 v1, v1, v11
; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
@@ -17303,37 +17501,48 @@ define <20 x i16> @bitcast_v40i8_to_v20i16(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB50_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v31, v33, s6
; VI-NEXT: v_perm_b32 v1, v37, v36, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v35, v34, s6
+; VI-NEXT: v_perm_b32 v0, v31, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v49, v48, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v39, v38, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v35, v34, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v53, v52, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v51, v50, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v39, v38, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v32, v54, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v51, v50, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_perm_b32 v9, v44, v42, s6
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_perm_b32 v9, v44, v42, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_perm_b32 v9, v45, v43, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v47, v46, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v45, v43, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr37
@@ -18607,57 +18816,67 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s10, v0
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v9
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
-; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_mov_b32_e32 v2, s23
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v9
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v9
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s10, v4, v9
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s7
+; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s8
-; VI-NEXT: v_perm_b32 v4, s9, v4, v9
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_perm_b32 v5, s12, v5, v9
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s11
+; VI-NEXT: v_perm_b32 v4, s9, v4, v9
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s13
-; VI-NEXT: v_perm_b32 v5, s14, v5, v9
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_perm_b32 v6, s40, v6, v9
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s15
+; VI-NEXT: v_perm_b32 v5, s14, v5, v9
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s41
-; VI-NEXT: v_perm_b32 v6, s42, v6, v9
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s15
; VI-NEXT: v_perm_b32 v7, s44, v7, v9
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s43
+; VI-NEXT: v_perm_b32 v6, s42, v6, v9
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s45
-; VI-NEXT: v_perm_b32 v7, s46, v7, v9
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_perm_b32 v8, s56, v8, v9
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s47
+; VI-NEXT: v_perm_b32 v7, s46, v7, v9
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s57
-; VI-NEXT: v_perm_b32 v8, s58, v8, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s47
; VI-NEXT: v_perm_b32 v10, s60, v10, v9
-; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
+; VI-NEXT: v_perm_b32 v8, s58, v8, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v8, v8, v10
; VI-NEXT: v_mov_b32_e32 v10, s59
; VI-NEXT: v_mov_b32_e32 v11, s62
; VI-NEXT: v_perm_b32 v10, s61, v10, v9
; VI-NEXT: v_perm_b32 v9, s63, v11, v9
-; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s63, s63, 3
@@ -21589,39 +21808,49 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB60_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v11, 0x200
-; VI-NEXT: v_add_f16_sdwa v17, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
-; VI-NEXT: v_add_f16_sdwa v20, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
-; VI-NEXT: v_add_f16_sdwa v18, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT: v_add_f16_sdwa v22, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
-; VI-NEXT: v_lshl_or_b32 v29, v17, 16, v10
-; VI-NEXT: v_lshl_or_b32 v28, v20, 16, v9
; VI-NEXT: v_add_f16_sdwa v23, v2, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v23
+; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: v_add_f16_sdwa v26, v1, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v39, v2, v12
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v26
+; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v21, v4, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v38, v1, v12
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v21
+; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_add_f16_sdwa v25, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v36, v4, v12
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v25
+; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
; VI-NEXT: v_add_f16_sdwa v19, v6, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v35, v3, v12
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v19
; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_add_f16_sdwa v24, v5, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v34, v6, v12
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v24
; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
-; VI-NEXT: v_lshl_or_b32 v31, v18, 16, v8
-; VI-NEXT: v_lshl_or_b32 v30, v22, 16, v7
+; VI-NEXT: v_add_f16_sdwa v18, v8, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v33, v5, v12
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v18
+; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
+; VI-NEXT: v_add_f16_sdwa v22, v7, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v31, v8, v12
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v22
+; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
+; VI-NEXT: v_add_f16_sdwa v17, v10, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_sdwa v20, v9, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v30, v7, v12
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v17
+; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v20
+; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
+; VI-NEXT: v_or_b32_e32 v29, v10, v12
+; VI-NEXT: v_or_b32_e32 v28, v9, v11
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[28:29]
-; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
-; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
-; VI-NEXT: v_lshl_or_b32 v34, v19, 16, v6
-; VI-NEXT: v_lshl_or_b32 v33, v24, 16, v5
; VI-NEXT: v_lshrrev_b64 v[12:13], 24, v[30:31]
-; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
-; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
-; VI-NEXT: v_lshl_or_b32 v36, v21, 16, v4
-; VI-NEXT: v_lshl_or_b32 v35, v25, 16, v3
; VI-NEXT: v_lshrrev_b64 v[13:14], 24, v[33:34]
-; VI-NEXT: v_lshl_or_b32 v39, v23, 16, v2
-; VI-NEXT: v_lshl_or_b32 v38, v26, 16, v1
; VI-NEXT: v_lshrrev_b64 v[14:15], 24, v[35:36]
; VI-NEXT: v_lshrrev_b64 v[15:16], 24, v[38:39]
; VI-NEXT: v_lshrrev_b32_e32 v27, 8, v29
@@ -21644,51 +21873,61 @@ define <40 x i8> @bitcast_v20f16_to_v40i8(<20 x half> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v26, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
-; VI-NEXT: v_lshl_or_b32 v1, v15, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v1, v1, v15
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v39, s4
; VI-NEXT: v_perm_b32 v2, v23, v48, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v3, v37, s4
; VI-NEXT: v_perm_b32 v2, v25, v14, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v3, v37, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v36, s4
; VI-NEXT: v_perm_b32 v2, v21, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v34, s4
; VI-NEXT: v_perm_b32 v2, v24, v13, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v32, s4
; VI-NEXT: v_perm_b32 v2, v19, v35, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v32, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v31, s4
; VI-NEXT: v_perm_b32 v2, v22, v12, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v29, s4
; VI-NEXT: v_perm_b32 v2, v18, v33, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v28, s4
; VI-NEXT: v_perm_b32 v2, v20, v11, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v28, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v27, s4
; VI-NEXT: v_perm_b32 v2, v17, v30, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -22574,46 +22813,56 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; VI-NEXT: v_mov_b32_e32 v1, 0x200
; VI-NEXT: v_add_f16_e32 v7, s4, v1
; VI-NEXT: s_lshr_b32 s4, s16, 16
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; VI-NEXT: v_add_f16_e32 v14, s17, v1
; VI-NEXT: v_add_f16_e32 v12, s4, v1
; VI-NEXT: s_lshr_b32 s4, s19, 16
+; VI-NEXT: v_or_b32_e32 v39, v14, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v12
+; VI-NEXT: v_add_f16_e32 v21, s16, v1
; VI-NEXT: v_add_f16_e32 v8, s4, v1
; VI-NEXT: s_lshr_b32 s4, s18, 16
+; VI-NEXT: v_or_b32_e32 v38, v21, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v8
+; VI-NEXT: v_add_f16_e32 v16, s19, v1
; VI-NEXT: v_add_f16_e32 v13, s4, v1
; VI-NEXT: s_lshr_b32 s4, s21, 16
+; VI-NEXT: v_or_b32_e32 v36, v16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
+; VI-NEXT: v_add_f16_e32 v23, s18, v1
; VI-NEXT: v_add_f16_e32 v9, s4, v1
; VI-NEXT: s_lshr_b32 s4, s20, 16
+; VI-NEXT: v_or_b32_e32 v35, v23, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
+; VI-NEXT: v_add_f16_e32 v18, s21, v1
; VI-NEXT: v_add_f16_e32 v15, s4, v1
; VI-NEXT: s_lshr_b32 s4, s23, 16
+; VI-NEXT: v_or_b32_e32 v33, v18, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v15
+; VI-NEXT: v_add_f16_e32 v24, s20, v1
; VI-NEXT: v_add_f16_e32 v10, s4, v1
; VI-NEXT: s_lshr_b32 s4, s22, 16
+; VI-NEXT: v_or_b32_e32 v32, v24, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
+; VI-NEXT: v_add_f16_e32 v20, s23, v1
; VI-NEXT: v_add_f16_e32 v17, s4, v1
; VI-NEXT: s_lshr_b32 s4, s25, 16
+; VI-NEXT: v_or_b32_e32 v31, v20, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; VI-NEXT: v_add_f16_e32 v25, s22, v1
; VI-NEXT: v_add_f16_e32 v11, s4, v1
; VI-NEXT: s_lshr_b32 s4, s24, 16
+; VI-NEXT: v_or_b32_e32 v30, v25, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
; VI-NEXT: v_add_f16_e32 v22, s25, v1
; VI-NEXT: v_add_f16_e32 v19, s4, v1
+; VI-NEXT: v_or_b32_e32 v28, v22, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
; VI-NEXT: v_add_f16_e32 v26, s24, v1
-; VI-NEXT: v_add_f16_e32 v20, s23, v1
-; VI-NEXT: v_add_f16_e32 v25, s22, v1
-; VI-NEXT: v_lshl_or_b32 v28, v11, 16, v22
-; VI-NEXT: v_lshl_or_b32 v27, v19, 16, v26
-; VI-NEXT: v_add_f16_e32 v14, s17, v1
-; VI-NEXT: v_add_f16_e32 v21, s16, v1
-; VI-NEXT: v_add_f16_e32 v16, s19, v1
-; VI-NEXT: v_add_f16_e32 v23, s18, v1
-; VI-NEXT: v_add_f16_e32 v18, s21, v1
-; VI-NEXT: v_add_f16_e32 v24, s20, v1
-; VI-NEXT: v_lshl_or_b32 v31, v10, 16, v20
-; VI-NEXT: v_lshl_or_b32 v30, v17, 16, v25
+; VI-NEXT: v_or_b32_e32 v27, v26, v2
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[27:28]
-; VI-NEXT: v_lshl_or_b32 v33, v9, 16, v18
-; VI-NEXT: v_lshl_or_b32 v32, v15, 16, v24
; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[30:31]
-; VI-NEXT: v_lshl_or_b32 v36, v8, 16, v16
-; VI-NEXT: v_lshl_or_b32 v35, v13, 16, v23
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[32:33]
-; VI-NEXT: v_lshl_or_b32 v39, v7, 16, v14
-; VI-NEXT: v_lshl_or_b32 v38, v12, 16, v21
; VI-NEXT: v_lshrrev_b64 v[4:5], 24, v[35:36]
; VI-NEXT: v_lshrrev_b64 v[5:6], 24, v[38:39]
; VI-NEXT: v_lshrrev_b32_e32 v6, 8, v28
@@ -22709,51 +22958,61 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v5, v12, v5, s4
; VI-NEXT: v_perm_b32 v12, v21, v48, s4
-; VI-NEXT: v_lshl_or_b32 v5, v5, 16, v12
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v5, v12, v5
+; VI-NEXT: v_perm_b32 v7, v7, v38, s4
; VI-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v14, v39, s4
-; VI-NEXT: v_perm_b32 v7, v7, v38, s4
-; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 4, v0
+; VI-NEXT: v_perm_b32 v4, v13, v4, s4
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v23, v37, s4
-; VI-NEXT: v_perm_b32 v4, v13, v4, s4
-; VI-NEXT: v_lshl_or_b32 v4, v4, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_add_u32_e32 v5, vcc, 8, v0
; VI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v4, v16, v36, s4
; VI-NEXT: v_perm_b32 v5, v8, v35, s4
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_perm_b32 v4, v16, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 12, v0
+; VI-NEXT: v_perm_b32 v3, v15, v3, s4
; VI-NEXT: buffer_store_dword v4, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v4, v24, v34, s4
-; VI-NEXT: v_perm_b32 v3, v15, v3, s4
-; VI-NEXT: v_lshl_or_b32 v3, v3, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v3, v4, v3
; VI-NEXT: v_add_u32_e32 v4, vcc, 16, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v3, v18, v33, s4
; VI-NEXT: v_perm_b32 v4, v9, v32, s4
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_perm_b32 v3, v18, v33, s4
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 20, v0
+; VI-NEXT: v_perm_b32 v2, v17, v2, s4
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v3, v25, v31, s4
-; VI-NEXT: v_perm_b32 v2, v17, v2, s4
-; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v2, v20, v29, s4
; VI-NEXT: v_perm_b32 v3, v10, v30, s4
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_perm_b32 v2, v20, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
+; VI-NEXT: v_perm_b32 v1, v19, v1, s4
; VI-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, v26, v28, s4
-; VI-NEXT: v_perm_b32 v1, v19, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v22, v6, s4
; VI-NEXT: v_perm_b32 v2, v11, v27, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v22, v6, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -22916,43 +23175,53 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v39, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v38, s4
; GFX9-NEXT: v_perm_b32 v10, v36, v37, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v33, s4
; GFX9-NEXT: v_perm_b32 v8, v31, v32, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v28, s4
; GFX9-NEXT: v_perm_b32 v6, v26, v27, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v23, s4
; GFX9-NEXT: v_perm_b32 v4, v21, v22, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v18, s4
; GFX9-NEXT: v_perm_b32 v2, v16, v17, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -23100,8 +23369,8 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v14, v34, v14, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v15
; GFX11-NEXT: v_perm_b32 v15, v32, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v36
; GFX11-NEXT: v_or_b32_e32 v7, v9, v7
; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v14
@@ -23110,15 +23379,17 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v5, v5, v29, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-NEXT: v_or_b32_e32 v8, v10, v31
-; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v10, v14, v15
; GFX11-NEXT: v_perm_b32 v14, v22, v23, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
; GFX11-NEXT: v_or_b32_e32 v13, v5, v13
; GFX11-NEXT: v_perm_b32 v5, v26, v12, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v6, v6, v25, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v27
; GFX11-NEXT: v_perm_b32 v3, v3, v24, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v4, v4, v20, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-NEXT: v_perm_b32 v1, v1, v17, 0xc0c0004
@@ -23126,8 +23397,8 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v2, v2, v16, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v15
; GFX11-NEXT: v_or_b32_e32 v9, v35, v9
-; GFX11-NEXT: v_lshl_or_b32 v14, v27, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v15, v5, 16, v3
+; GFX11-NEXT: v_or_b32_e32 v14, v6, v12
+; GFX11-NEXT: v_or_b32_e32 v15, v3, v5
; GFX11-NEXT: v_or_b32_e32 v16, v4, v18
; GFX11-NEXT: v_or_b32_e32 v1, v1, v11
; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
@@ -23572,37 +23843,48 @@ define <20 x half> @bitcast_v40i8_to_v20f16(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB62_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v31, v33, s6
; VI-NEXT: v_perm_b32 v1, v37, v36, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v35, v34, s6
+; VI-NEXT: v_perm_b32 v0, v31, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v49, v48, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v39, v38, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v35, v34, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v53, v52, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v51, v50, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v39, v38, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v32, v54, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v51, v50, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_perm_b32 v9, v44, v42, s6
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_perm_b32 v9, v44, v42, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_perm_b32 v9, v45, v43, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v47, v46, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v45, v43, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: ; implicit-def: $vgpr31
; VI-NEXT: ; implicit-def: $vgpr33
; VI-NEXT: ; implicit-def: $vgpr37
@@ -24876,57 +25158,67 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s10, v0
; VI-NEXT: s_cbranch_scc0 .LBB63_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v9
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v9
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v9
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s6
-; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s10, v4, v9
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s7
+; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s8
-; VI-NEXT: v_perm_b32 v4, s9, v4, v9
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s7
; VI-NEXT: v_perm_b32 v5, s12, v5, v9
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s11
-; VI-NEXT: v_mov_b32_e32 v6, s13
-; VI-NEXT: v_perm_b32 v5, s14, v5, v9
+; VI-NEXT: v_perm_b32 v4, s9, v4, v9
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_mov_b32_e32 v6, s13
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_perm_b32 v6, s40, v6, v9
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s15
+; VI-NEXT: v_perm_b32 v5, s14, v5, v9
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s41
-; VI-NEXT: v_perm_b32 v6, s42, v6, v9
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s15
; VI-NEXT: v_perm_b32 v7, s44, v7, v9
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s43
+; VI-NEXT: v_perm_b32 v6, s42, v6, v9
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s45
-; VI-NEXT: v_perm_b32 v7, s46, v7, v9
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s43
; VI-NEXT: v_perm_b32 v8, s56, v8, v9
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s47
+; VI-NEXT: v_perm_b32 v7, s46, v7, v9
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s57
-; VI-NEXT: v_perm_b32 v8, s58, v8, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s47
; VI-NEXT: v_perm_b32 v10, s60, v10, v9
-; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
+; VI-NEXT: v_perm_b32 v8, s58, v8, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v8, v8, v10
; VI-NEXT: v_mov_b32_e32 v10, s59
; VI-NEXT: v_mov_b32_e32 v11, s62
; VI-NEXT: v_perm_b32 v10, s61, v10, v9
; VI-NEXT: v_perm_b32 v9, s63, v11, v9
-; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: s_cbranch_execnz .LBB63_3
; VI-NEXT: .LBB63_2: ; %cmp.true
; VI-NEXT: s_add_i32 s63, s63, 3
@@ -27947,37 +28239,48 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB72_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v54, v53, s6
; VI-NEXT: v_perm_b32 v1, v52, v51, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v50, v49, s6
+; VI-NEXT: v_perm_b32 v0, v54, v53, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v48, v39, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v50, v49, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v36, v35, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v45, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_perm_b32 v9, v44, v43, s6
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v47, v46, s6
-; VI-NEXT: v_perm_b32 v9, v44, v43, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_perm_b32 v9, v42, v41, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v40, v55, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v42, v41, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -28754,11 +29057,12 @@ define <5 x double> @bitcast_v40i8_to_v5f64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
@@ -29168,57 +29472,67 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; VI-NEXT: v_readfirstlane_b32 s63, v0
; VI-NEXT: s_cbranch_scc0 .LBB73_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v9
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v9
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v9
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s62
-; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s63, v4, v9
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s60
+; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_perm_b32 v4, s61, v4, v9
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s60
; VI-NEXT: v_perm_b32 v5, s59, v5, v9
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s56
+; VI-NEXT: v_perm_b32 v4, s61, v4, v9
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_perm_b32 v5, s57, v5, v9
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s56
; VI-NEXT: v_perm_b32 v6, s47, v6, v9
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s44
+; VI-NEXT: v_perm_b32 v5, s57, v5, v9
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s42
-; VI-NEXT: v_perm_b32 v6, s45, v6, v9
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s44
; VI-NEXT: v_perm_b32 v7, s43, v7, v9
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s40
+; VI-NEXT: v_perm_b32 v6, s45, v6, v9
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s14
-; VI-NEXT: v_perm_b32 v7, s41, v7, v9
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s40
; VI-NEXT: v_perm_b32 v8, s15, v8, v9
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s12
+; VI-NEXT: v_perm_b32 v7, s41, v7, v9
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_perm_b32 v8, s13, v8, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s12
; VI-NEXT: v_perm_b32 v10, s11, v10, v9
-; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
+; VI-NEXT: v_perm_b32 v8, s13, v8, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v8, v8, v10
; VI-NEXT: v_mov_b32_e32 v10, s8
; VI-NEXT: v_mov_b32_e32 v11, s6
; VI-NEXT: v_perm_b32 v10, s9, v10, v9
; VI-NEXT: v_perm_b32 v9, s7, v11, v9
-; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: s_cbranch_execnz .LBB73_3
; VI-NEXT: .LBB73_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -29361,57 +29675,67 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB73_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s60
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s60
; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s56
+; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s56
; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s44
+; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s44
; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s40
+; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s40
; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s12
+; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s12
; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
-; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
+; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
; GFX9-NEXT: s_cbranch_execnz .LBB73_3
; GFX9-NEXT: .LBB73_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -29543,37 +29867,47 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB73_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
-; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
+; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v12
-; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v14
-; GFX11-NEXT: v_lshl_or_b32 v9, v13, 16, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB73_3
; GFX11-NEXT: .LBB73_2: ; %cmp.true
@@ -30033,51 +30367,61 @@ define <40 x i8> @bitcast_v5f64_to_v40i8(<5 x double> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v48, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
-; VI-NEXT: v_lshl_or_b32 v1, v15, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v1, v1, v15
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v39, s4
; VI-NEXT: v_perm_b32 v2, v38, v37, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v3, v36, s4
; VI-NEXT: v_perm_b32 v2, v35, v14, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v3, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v34, s4
; VI-NEXT: v_perm_b32 v2, v33, v32, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v31, s4
; VI-NEXT: v_perm_b32 v2, v30, v13, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v29, s4
; VI-NEXT: v_perm_b32 v2, v28, v27, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v26, s4
; VI-NEXT: v_perm_b32 v2, v25, v12, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v26, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v24, s4
; VI-NEXT: v_perm_b32 v2, v23, v22, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v21, s4
; VI-NEXT: v_perm_b32 v2, v20, v11, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v21, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v19, s4
; VI-NEXT: v_perm_b32 v2, v18, v17, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -30936,51 +31280,61 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v34, v15, s4
; VI-NEXT: v_perm_b32 v9, v9, v36, s4
-; VI-NEXT: v_lshl_or_b32 v9, v15, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v9, v9, v15
; VI-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v9, v10, v48, s4
; VI-NEXT: v_perm_b32 v10, v39, v38, s4
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_add_u32_e32 v10, vcc, 4, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v7, v7, v32, s4
; VI-NEXT: v_perm_b32 v9, v31, v14, s4
-; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; VI-NEXT: v_perm_b32 v7, v7, v32, s4
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_u32_e32 v9, vcc, 8, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v7, v8, v37, s4
; VI-NEXT: v_perm_b32 v8, v35, v33, s4
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_add_u32_e32 v8, vcc, 12, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v5, v5, v27, s4
; VI-NEXT: v_perm_b32 v7, v26, v13, s4
-; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
-; VI-NEXT: v_add_u32_e32 v7, vcc, 16, v0
+; VI-NEXT: v_perm_b32 v5, v5, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v7
+; VI-NEXT: v_add_u32_e32 v7, vcc, 16, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v6, v30, s4
; VI-NEXT: v_perm_b32 v6, v29, v28, s4
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 20, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v3, v3, v22, s4
; VI-NEXT: v_perm_b32 v5, v21, v12, s4
-; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; VI-NEXT: v_perm_b32 v3, v3, v22, s4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v3, v3, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 24, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v3, v4, v25, s4
; VI-NEXT: v_perm_b32 v4, v24, v23, s4
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 28, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v1, v19, s4
; VI-NEXT: v_perm_b32 v3, v18, v11, s4
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, v1, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v20, s4
; VI-NEXT: v_perm_b32 v2, v17, v16, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -31137,43 +31491,53 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v33, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v35, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v48, s4
; GFX9-NEXT: v_perm_b32 v10, v39, v38, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v7, v7, v32, s4
; GFX9-NEXT: v_perm_b32 v9, v30, v14, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_perm_b32 v7, v7, v32, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v37, s4
; GFX9-NEXT: v_perm_b32 v8, v36, v34, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v5, v5, v27, s4
; GFX9-NEXT: v_perm_b32 v7, v26, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_perm_b32 v5, v5, v27, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v31, s4
; GFX9-NEXT: v_perm_b32 v6, v29, v28, s4
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v3, v3, v22, s4
; GFX9-NEXT: v_perm_b32 v5, v21, v12, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_perm_b32 v3, v3, v22, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v25, s4
; GFX9-NEXT: v_perm_b32 v4, v24, v23, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v1, v1, v19, s4
; GFX9-NEXT: v_perm_b32 v3, v17, v11, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, v1, v19, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v20, s4
; GFX9-NEXT: v_perm_b32 v2, v18, v16, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -31308,37 +31672,47 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v33, s24 :: v_dual_mov_b32 v38, s23
; GFX11-NEXT: v_dual_mov_b32 v39, s22 :: v_dual_mov_b32 v48, s15
; GFX11-NEXT: .LBB75_5: ; %end
-; GFX11-NEXT: v_perm_b32 v7, v7, v32, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v16, v34, v16, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v12, v35, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v31, v37, v36, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v32, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-NEXT: v_perm_b32 v14, v28, v14, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-NEXT: v_perm_b32 v8, v8, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v16, v34, v16, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v12, v12, v35, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v34, v39, v38, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v12, v12, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
; GFX11-NEXT: v_perm_b32 v5, v5, v26, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v14
-; GFX11-NEXT: v_lshl_or_b32 v14, v15, 16, v7
+; GFX11-NEXT: v_or_b32_e32 v14, v7, v15
; GFX11-NEXT: v_perm_b32 v7, v30, v29, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v15, v31, 16, v8
+; GFX11-NEXT: v_or_b32_e32 v15, v8, v16
; GFX11-NEXT: v_perm_b32 v8, v23, v10, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v27, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v3, v3, v22, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v25, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v12, v16, 16, v12
; GFX11-NEXT: v_perm_b32 v9, v19, v9, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v16, v20, v18, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v34
+; GFX11-NEXT: v_perm_b32 v6, v6, v27, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_perm_b32 v3, v3, v22, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v1, v1, v11, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v13, v34, 16, v13
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v16
+; GFX11-NEXT: v_or_b32_e32 v13, v13, v28
; GFX11-NEXT: v_or_b32_e32 v5, v5, v26
-; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v8, v10, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v1, v9, 16, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, v16, 16, v2
+; GFX11-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX11-NEXT: v_or_b32_e32 v7, v3, v8
+; GFX11-NEXT: v_or_b32_e32 v8, v4, v10
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v9
+; GFX11-NEXT: v_or_b32_e32 v2, v2, v11
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[12:15], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -31712,37 +32086,48 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB76_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v54, v53, s6
; VI-NEXT: v_perm_b32 v1, v52, v51, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v50, v49, s6
+; VI-NEXT: v_perm_b32 v0, v54, v53, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v48, v39, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v50, v49, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v36, v35, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_perm_b32 v6, v24, v25, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v45, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_perm_b32 v7, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_perm_b32 v9, v44, v43, s6
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v47, v46, s6
-; VI-NEXT: v_perm_b32 v9, v44, v43, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_perm_b32 v9, v42, v41, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v40, v55, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_perm_b32 v9, v42, v41, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -32519,11 +32904,12 @@ define <5 x i64> @bitcast_v40i8_to_v5i64(<40 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v8
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, v22, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v7
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v24, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v26, 3
@@ -32933,57 +33319,67 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; VI-NEXT: v_readfirstlane_b32 s63, v0
; VI-NEXT: s_cbranch_scc0 .LBB77_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v9
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v9
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v9
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v1, s20, v1, v9
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v9
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v9
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s62
-; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s63, v4, v9
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s60
+; VI-NEXT: v_perm_b32 v3, s28, v3, v9
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s58
-; VI-NEXT: v_perm_b32 v4, s61, v4, v9
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s60
; VI-NEXT: v_perm_b32 v5, s59, v5, v9
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s56
+; VI-NEXT: v_perm_b32 v4, s61, v4, v9
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s46
-; VI-NEXT: v_perm_b32 v5, s57, v5, v9
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s56
; VI-NEXT: v_perm_b32 v6, s47, v6, v9
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s44
+; VI-NEXT: v_perm_b32 v5, s57, v5, v9
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s42
-; VI-NEXT: v_perm_b32 v6, s45, v6, v9
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s44
; VI-NEXT: v_perm_b32 v7, s43, v7, v9
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s40
+; VI-NEXT: v_perm_b32 v6, s45, v6, v9
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s14
-; VI-NEXT: v_perm_b32 v7, s41, v7, v9
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s40
; VI-NEXT: v_perm_b32 v8, s15, v8, v9
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s12
+; VI-NEXT: v_perm_b32 v7, s41, v7, v9
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_perm_b32 v8, s13, v8, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s12
; VI-NEXT: v_perm_b32 v10, s11, v10, v9
-; VI-NEXT: v_lshl_or_b32 v8, v10, 16, v8
+; VI-NEXT: v_perm_b32 v8, s13, v8, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v8, v8, v10
; VI-NEXT: v_mov_b32_e32 v10, s8
; VI-NEXT: v_mov_b32_e32 v11, s6
; VI-NEXT: v_perm_b32 v10, s9, v10, v9
; VI-NEXT: v_perm_b32 v9, s7, v11, v9
-; VI-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v10, v9
; VI-NEXT: s_cbranch_execnz .LBB77_3
; VI-NEXT: .LBB77_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -33126,57 +33522,67 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB77_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s60
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s60
; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s56
+; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s56
; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s44
+; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s44
; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s40
+; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s40
; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s12
+; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s12
; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
-; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
+; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
; GFX9-NEXT: s_cbranch_execnz .LBB77_3
; GFX9-NEXT: .LBB77_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -33308,37 +33714,47 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB77_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
-; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
+; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
+; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
+; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v12
-; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v14
-; GFX11-NEXT: v_lshl_or_b32 v9, v13, 16, v15
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
+; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
+; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
+; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB77_3
; GFX11-NEXT: .LBB77_2: ; %cmp.true
@@ -33808,51 +34224,61 @@ define <40 x i8> @bitcast_v5i64_to_v40i8(<5 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v15, v48, v15, s4
; VI-NEXT: v_perm_b32 v1, v1, v16, s4
-; VI-NEXT: v_lshl_or_b32 v1, v15, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v1, v1, v15
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v39, s4
; VI-NEXT: v_perm_b32 v2, v38, v37, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v3, v36, s4
; VI-NEXT: v_perm_b32 v2, v35, v14, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v3, v36, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v34, s4
; VI-NEXT: v_perm_b32 v2, v33, v32, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v31, s4
; VI-NEXT: v_perm_b32 v2, v30, v13, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v29, s4
; VI-NEXT: v_perm_b32 v2, v28, v27, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v26, s4
; VI-NEXT: v_perm_b32 v2, v25, v12, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v26, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v24, s4
; VI-NEXT: v_perm_b32 v2, v23, v22, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v21, s4
; VI-NEXT: v_perm_b32 v2, v20, v11, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v21, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v19, s4
; VI-NEXT: v_perm_b32 v2, v18, v17, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -34642,74 +35068,84 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; VI-NEXT: s_lshr_b32 s75, s16, 16
; VI-NEXT: s_lshr_b32 s76, s16, 8
; VI-NEXT: .LBB79_3: ; %end
-; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s12
-; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_perm_b32 v3, s75, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_mov_b32_e32 v3, s72
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s74
-; VI-NEXT: v_mov_b32_e32 v3, s72
-; VI-NEXT: v_perm_b32 v1, s17, v1, v2
; VI-NEXT: v_perm_b32 v3, s73, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s17, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_mov_b32_e32 v3, s10
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_perm_b32 v3, s62, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s61
; VI-NEXT: v_mov_b32_e32 v3, s59
-; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s61
; VI-NEXT: v_perm_b32 v3, s60, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_mov_b32_e32 v3, s8
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_perm_b32 v3, s57, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s56
; VI-NEXT: v_mov_b32_e32 v3, s46
-; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s56
; VI-NEXT: v_perm_b32 v3, s47, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s45
; VI-NEXT: v_mov_b32_e32 v3, s6
-; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s45
; VI-NEXT: v_perm_b32 v3, s44, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s43
; VI-NEXT: v_mov_b32_e32 v3, s41
-; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s43
; VI-NEXT: v_perm_b32 v3, s42, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s40
; VI-NEXT: v_mov_b32_e32 v3, s4
-; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s40
; VI-NEXT: v_perm_b32 v3, s29, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s28
; VI-NEXT: v_mov_b32_e32 v3, s26
; VI-NEXT: v_perm_b32 v1, s25, v1, v2
; VI-NEXT: v_perm_b32 v2, s27, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -34826,66 +35262,76 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; GFX9-NEXT: s_lshr_b32 s75, s16, 16
; GFX9-NEXT: s_lshr_b32 s76, s16, 8
; GFX9-NEXT: .LBB79_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v1, s76
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s12
-; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v1, s76
; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s74
-; GFX9-NEXT: v_mov_b32_e32 v3, s72
-; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s73, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s59
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s61
-; GFX9-NEXT: v_mov_b32_e32 v3, s59
-; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s60, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s58
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s57, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s56
-; GFX9-NEXT: v_mov_b32_e32 v3, s46
-; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s47, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s45
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
-; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s44, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s41
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s43
-; GFX9-NEXT: v_mov_b32_e32 v3, s41
-; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s42, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s40
-; GFX9-NEXT: v_mov_b32_e32 v3, s4
-; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s29, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s28
; GFX9-NEXT: v_mov_b32_e32 v3, s26
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s27, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -35004,37 +35450,47 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; GFX11-NEXT: s_lshr_b32 s62, s0, 8
; GFX11-NEXT: .LBB79_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v6, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v1, s0, s62, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v2, s61, s12, v6
-; GFX11-NEXT: v_perm_b32 v3, s1, s60, v6
; GFX11-NEXT: v_perm_b32 v4, s59, s58, v6
+; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
+; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
+; GFX11-NEXT: v_perm_b32 v1, s0, s62, v6
+; GFX11-NEXT: v_perm_b32 v3, s1, s60, v6
; GFX11-NEXT: v_perm_b32 v5, s2, s57, v6
-; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
; GFX11-NEXT: v_perm_b32 v8, s3, s47, v6
-; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
; GFX11-NEXT: v_perm_b32 v10, s16, s44, v6
-; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
-; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v3, v7, 16, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: v_perm_b32 v12, s24, s4, v6
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
+; GFX11-NEXT: v_or_b32_e32 v3, v5, v7
; GFX11-NEXT: v_perm_b32 v7, s42, s41, v6
-; GFX11-NEXT: v_lshl_or_b32 v4, v9, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-NEXT: v_or_b32_e32 v4, v8, v9
+; GFX11-NEXT: v_or_b32_e32 v5, v10, v11
; GFX11-NEXT: v_perm_b32 v8, s29, s6, v6
+; GFX11-NEXT: v_perm_b32 v11, s27, s26, v6
+; GFX11-NEXT: v_perm_b32 v14, s22, s14, v6
; GFX11-NEXT: v_perm_b32 v9, s17, s40, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-NEXT: v_perm_b32 v10, s18, s28, v6
-; GFX11-NEXT: v_perm_b32 v11, s27, s26, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_perm_b32 v13, s19, s25, v6
-; GFX11-NEXT: v_perm_b32 v12, s24, s4, v6
-; GFX11-NEXT: v_perm_b32 v14, s22, s14, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v15, s20, s23, v6
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-NEXT: v_perm_b32 v16, s21, s15, v6
-; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v10
-; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v13
-; GFX11-NEXT: v_lshl_or_b32 v9, v12, 16, v15
-; GFX11-NEXT: v_lshl_or_b32 v10, v14, 16, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
+; GFX11-NEXT: v_or_b32_e32 v7, v10, v8
+; GFX11-NEXT: v_or_b32_e32 v8, v13, v11
+; GFX11-NEXT: v_or_b32_e32 v9, v15, v12
+; GFX11-NEXT: v_or_b32_e32 v10, v16, v14
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
index c25ad3ffd6e38..123d1042e27c9 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
@@ -2232,7 +2232,8 @@ define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -2376,9 +2377,11 @@ define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -2447,7 +2450,8 @@ define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) #0
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_cbranch_execnz .LBB23_3
; VI-NEXT: .LBB23_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -2478,7 +2482,8 @@ define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) #0
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_cbranch_execnz .LBB23_3
; GFX9-NEXT: .LBB23_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -2506,10 +2511,12 @@ define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) #0
; GFX11-NEXT: s_cbranch_scc0 .LBB23_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB23_3
; GFX11-NEXT: .LBB23_2: ; %cmp.true
@@ -2523,8 +2530,9 @@ define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) #0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB23_4:
@@ -4487,7 +4495,8 @@ define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -4631,9 +4640,11 @@ define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4702,7 +4713,8 @@ define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b)
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_cbranch_execnz .LBB43_3
; VI-NEXT: .LBB43_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -4733,7 +4745,8 @@ define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b)
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_cbranch_execnz .LBB43_3
; GFX9-NEXT: .LBB43_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -4761,10 +4774,12 @@ define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b)
; GFX11-NEXT: s_cbranch_scc0 .LBB43_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB43_3
; GFX11-NEXT: .LBB43_2: ; %cmp.true
@@ -4778,8 +4793,9 @@ define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-NEXT: .LBB43_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB43_4:
@@ -6139,9 +6155,10 @@ define <4 x i8> @bitcast_v2i16_to_v4i8(<2 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB56_2
; VI-NEXT: .LBB56_4: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v1, 3
-; VI-NEXT: v_add_u16_e32 v0, 3, v4
; VI-NEXT: v_add_u16_sdwa v2, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v0
+; VI-NEXT: v_add_u16_e32 v0, 3, v4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v0, v1
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; VI-NEXT: v_bfe_u32 v3, v2, 8, 8
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -6459,7 +6476,8 @@ define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -6603,9 +6621,11 @@ define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6680,7 +6700,8 @@ define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inre
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_cbranch_execnz .LBB59_3
; VI-NEXT: .LBB59_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -6711,7 +6732,8 @@ define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inre
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_cbranch_execnz .LBB59_3
; GFX9-NEXT: .LBB59_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -6739,10 +6761,12 @@ define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_cbranch_scc0 .LBB59_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB59_3
; GFX11-NEXT: .LBB59_2: ; %cmp.true
@@ -6756,8 +6780,9 @@ define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-NEXT: .LBB59_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB59_4:
@@ -7786,8 +7811,9 @@ define <4 x i8> @bitcast_v2f16_to_v4i8(<2 x half> %a, i32 %b) #0 {
; VI-NEXT: .LBB68_4: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v1, 0x200
; VI-NEXT: v_add_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; VI-NEXT: v_add_f16_e32 v0, 0x200, v0
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v0
+; VI-NEXT: v_or_b32_e32 v1, v0, v1
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; VI-NEXT: v_bfe_u32 v3, v2, 8, 8
; VI-NEXT: s_or_b64 exec, exec, s[4:5]
@@ -7951,8 +7977,9 @@ define inreg <4 x i8> @bitcast_v2f16_to_v4i8_scalar(<2 x half> inreg %a, i32 inr
; VI-NEXT: s_lshr_b32 s4, s16, 16
; VI-NEXT: v_mov_b32_e32 v0, 0x200
; VI-NEXT: v_add_f16_e32 v2, s4, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; VI-NEXT: v_add_f16_e32 v0, s16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v0
+; VI-NEXT: v_or_b32_e32 v1, v0, v1
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; VI-NEXT: v_bfe_u32 v3, v2, 8, 8
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -8108,7 +8135,8 @@ define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -8252,9 +8280,11 @@ define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -8329,7 +8359,8 @@ define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inr
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_cbranch_execnz .LBB71_3
; VI-NEXT: .LBB71_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -8360,7 +8391,8 @@ define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inr
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -8388,10 +8420,12 @@ define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inr
; GFX11-NEXT: s_cbranch_scc0 .LBB71_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-NEXT: .LBB71_2: ; %cmp.true
@@ -8405,8 +8439,9 @@ define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inr
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-NEXT: .LBB71_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB71_4:
@@ -9543,7 +9578,8 @@ define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -9687,9 +9723,11 @@ define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9760,7 +9798,8 @@ define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_cbranch_execnz .LBB79_3
; VI-NEXT: .LBB79_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -9791,7 +9830,8 @@ define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_cbranch_execnz .LBB79_3
; GFX9-NEXT: .LBB79_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9819,10 +9859,12 @@ define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB79_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB79_3
; GFX11-NEXT: .LBB79_2: ; %cmp.true
@@ -9836,8 +9878,9 @@ define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-NEXT: .LBB79_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB79_4:
@@ -10219,7 +10262,8 @@ define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v0, v5, v1, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: ; implicit-def: $vgpr5
; VI-NEXT: ; implicit-def: $vgpr1
; VI-NEXT: ; implicit-def: $vgpr2
@@ -10363,9 +10407,11 @@ define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -10434,7 +10480,8 @@ define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inre
; VI-NEXT: v_mov_b32_e32 v2, s19
; VI-NEXT: v_perm_b32 v0, s16, v0, v1
; VI-NEXT: v_perm_b32 v1, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_cbranch_execnz .LBB83_3
; VI-NEXT: .LBB83_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -10465,7 +10512,8 @@ define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inre
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: s_cbranch_execnz .LBB83_3
; GFX9-NEXT: .LBB83_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -10493,10 +10541,12 @@ define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_cbranch_scc0 .LBB83_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB83_3
; GFX11-NEXT: .LBB83_2: ; %cmp.true
@@ -10510,8 +10560,9 @@ define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-NEXT: .LBB83_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
; GFX11-NEXT: .LBB83_4:
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index f7641f6cb6724..d43b0226756d5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -9097,86 +9097,102 @@ define <64 x i8> @bitcast_v16i32_to_v64i8(<16 x i32> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
-; VI-NEXT: v_lshl_or_b32 v1, v21, 16, v1
-; VI-NEXT: v_perm_b32 v2, v2, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v1, v1, v21
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_perm_b32 v2, v2, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v60, s4
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v60, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v57, s4
; VI-NEXT: v_perm_b32 v2, v56, v26, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v57, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v47, s4
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v47, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v44, s4
; VI-NEXT: v_perm_b32 v2, v43, v25, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v44, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v42, s4
; VI-NEXT: v_perm_b32 v2, v41, v40, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v42, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v55, s4
; VI-NEXT: v_perm_b32 v2, v54, v22, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v53, s4
; VI-NEXT: v_perm_b32 v2, v52, v51, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v11, v50, s4
; VI-NEXT: v_perm_b32 v2, v49, v19, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v11, v50, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v12, v48, s4
; VI-NEXT: v_perm_b32 v2, v39, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v12, v48, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v13, v37, s4
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v13, v37, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v14, v35, s4
; VI-NEXT: v_perm_b32 v2, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v14, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -10524,116 +10540,132 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; VI-NEXT: s_lshr_b32 s66, s16, 16
; VI-NEXT: s_lshr_b32 s67, s16, 8
; VI-NEXT: .LBB25_3: ; %end
-; VI-NEXT: v_mov_b32_e32 v1, s67
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s44
-; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s67
; VI-NEXT: v_perm_b32 v3, s66, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_mov_b32_e32 v3, s55
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s65
-; VI-NEXT: v_mov_b32_e32 v3, s55
-; VI-NEXT: v_perm_b32 v1, s17, v1, v2
; VI-NEXT: v_perm_b32 v3, s64, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s17, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s54
; VI-NEXT: v_mov_b32_e32 v3, s42
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s54
; VI-NEXT: v_perm_b32 v3, s53, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s52
; VI-NEXT: v_mov_b32_e32 v3, s50
-; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s52
; VI-NEXT: v_perm_b32 v3, s51, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s49
; VI-NEXT: v_mov_b32_e32 v3, s40
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s49
; VI-NEXT: v_perm_b32 v3, s48, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s39
; VI-NEXT: v_mov_b32_e32 v3, s37
-; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s39
; VI-NEXT: v_perm_b32 v3, s38, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s36
; VI-NEXT: v_mov_b32_e32 v3, s14
-; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s36
; VI-NEXT: v_perm_b32 v3, s35, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s34
; VI-NEXT: v_mov_b32_e32 v3, s30
-; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s34
; VI-NEXT: v_perm_b32 v3, s31, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s91
; VI-NEXT: v_mov_b32_e32 v3, s12
-; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s91
; VI-NEXT: v_perm_b32 v3, s90, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s89
; VI-NEXT: v_mov_b32_e32 v3, s79
-; VI-NEXT: v_perm_b32 v1, s25, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s89
; VI-NEXT: v_perm_b32 v3, s88, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s25, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s78
; VI-NEXT: v_mov_b32_e32 v3, s10
-; VI-NEXT: v_perm_b32 v1, s26, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s78
; VI-NEXT: v_perm_b32 v3, s77, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s26, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_mov_b32_e32 v3, s74
-; VI-NEXT: v_perm_b32 v1, s27, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_perm_b32 v3, s75, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s27, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s73
; VI-NEXT: v_mov_b32_e32 v3, s8
-; VI-NEXT: v_perm_b32 v1, s28, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s73
; VI-NEXT: v_perm_b32 v3, s72, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s28, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_mov_b32_e32 v3, s61
-; VI-NEXT: v_perm_b32 v1, s29, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_perm_b32 v3, s62, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s29, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s60
; VI-NEXT: v_mov_b32_e32 v3, s6
-; VI-NEXT: v_perm_b32 v1, s4, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s60
; VI-NEXT: v_perm_b32 v3, s59, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s4, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_perm_b32 v1, s5, v1, v2
; VI-NEXT: v_perm_b32 v2, s57, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: v_readlane_b32 s30, v4, 18
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -10855,102 +10887,118 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX9-NEXT: s_lshr_b32 s54, s16, 16
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
; GFX9-NEXT: .LBB25_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v1, s55
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s44
-; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v1, s55
; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s51
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s53
-; GFX9-NEXT: v_mov_b32_e32 v3, s51
-; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s42
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s50
-; GFX9-NEXT: v_mov_b32_e32 v3, s42
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s38
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s48
-; GFX9-NEXT: v_mov_b32_e32 v3, s38
-; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s40
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s37
-; GFX9-NEXT: v_mov_b32_e32 v3, s40
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s31
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s35
-; GFX9-NEXT: v_mov_b32_e32 v3, s31
-; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s30
-; GFX9-NEXT: v_mov_b32_e32 v3, s14
-; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s92
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s94
-; GFX9-NEXT: v_mov_b32_e32 v3, s92
-; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s91
-; GFX9-NEXT: v_mov_b32_e32 v3, s12
-; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s79
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s89
-; GFX9-NEXT: v_mov_b32_e32 v3, s79
-; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: v_mov_b32_e32 v1, s78
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
-; GFX9-NEXT: v_perm_b32 v1, s26, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s26, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_mov_b32_e32 v1, s76
-; GFX9-NEXT: v_mov_b32_e32 v3, s74
-; GFX9-NEXT: v_perm_b32 v1, s27, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s27, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_mov_b32_e32 v1, s73
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
-; GFX9-NEXT: v_perm_b32 v1, s28, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s28, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s61
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_mov_b32_e32 v3, s61
-; GFX9-NEXT: v_perm_b32 v1, s29, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s29, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v1, s60
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
-; GFX9-NEXT: v_perm_b32 v1, s4, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s4, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v1, s58
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_perm_b32 v1, s5, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s57, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_readlane_b32 s30, v4, 14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_readlane_b32 s31, v4, 15
@@ -11160,59 +11208,72 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
; GFX11-NEXT: .LBB25_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v12, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v1, s0, s48, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
+; GFX11-NEXT: v_readlane_b32 s34, v23, 0
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
-; GFX11-NEXT: v_perm_b32 v3, s1, s38, v12
; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
-; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
+; GFX11-NEXT: v_perm_b32 v1, s0, s48, v12
+; GFX11-NEXT: v_perm_b32 v3, s1, s38, v12
; GFX11-NEXT: v_perm_b32 v6, s2, s35, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_perm_b32 v8, s30, vcc_hi, v12
-; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
-; GFX11-NEXT: v_lshl_or_b32 v3, v5, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
+; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
+; GFX11-NEXT: v_or_b32_e32 v3, v6, v5
; GFX11-NEXT: v_perm_b32 v5, s93, s92, v12
-; GFX11-NEXT: v_perm_b32 v8, s90, s12, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
; GFX11-NEXT: v_perm_b32 v6, s16, s94, v12
-; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
-; GFX11-NEXT: v_perm_b32 v13, s18, s89, v12
+; GFX11-NEXT: v_perm_b32 v8, s90, s12, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v5
+; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
+; GFX11-NEXT: v_perm_b32 v13, s18, s89, v12
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-NEXT: v_or_b32_e32 v5, v6, v9
; GFX11-NEXT: v_perm_b32 v9, s88, s78, v12
; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v8
-; GFX11-NEXT: v_perm_b32 v8, s19, s79, v12
; GFX11-NEXT: v_perm_b32 v10, s77, s10, v12
; GFX11-NEXT: v_perm_b32 v11, s75, s74, v12
+; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
+; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-NEXT: v_or_b32_e32 v7, v13, v8
+; GFX11-NEXT: v_perm_b32 v8, s19, s79, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_perm_b32 v13, s20, s76, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v15, s21, s73, v12
-; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v16, s22, s63, v12
-; GFX11-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v9, v10, 16, v13
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-NEXT: v_or_b32_e32 v9, v13, v10
; GFX11-NEXT: v_perm_b32 v13, s62, s61, v12
-; GFX11-NEXT: v_lshl_or_b32 v10, v11, 16, v15
-; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
-; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v16
+; GFX11-NEXT: v_or_b32_e32 v10, v15, v11
+; GFX11-NEXT: v_or_b32_e32 v11, v16, v14
; GFX11-NEXT: v_perm_b32 v14, s59, s6, v12
-; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
; GFX11-NEXT: v_perm_b32 v17, s57, s56, v12
; GFX11-NEXT: v_perm_b32 v18, s46, s4, v12
-; GFX11-NEXT: v_perm_b32 v19, s25, s47, v12
; GFX11-NEXT: v_perm_b32 v20, s44, s42, v12
+; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-NEXT: v_perm_b32 v19, s25, s47, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v21, s26, s45, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-NEXT: v_perm_b32 v22, s27, s43, v12
-; GFX11-NEXT: v_lshl_or_b32 v12, v13, 16, v15
-; GFX11-NEXT: v_lshl_or_b32 v13, v14, 16, v16
-; GFX11-NEXT: v_lshl_or_b32 v14, v17, 16, v19
-; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v21
-; GFX11-NEXT: v_lshl_or_b32 v16, v20, 16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-NEXT: v_or_b32_e32 v12, v15, v13
+; GFX11-NEXT: v_or_b32_e32 v13, v16, v14
+; GFX11-NEXT: v_or_b32_e32 v14, v19, v17
+; GFX11-NEXT: v_or_b32_e32 v15, v21, v18
+; GFX11-NEXT: v_or_b32_e32 v16, v22, v20
; GFX11-NEXT: v_readlane_b32 s30, v23, 7
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
@@ -11226,7 +11287,6 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: v_readlane_b32 s37, v23, 3
; GFX11-NEXT: v_readlane_b32 s36, v23, 2
; GFX11-NEXT: v_readlane_b32 s35, v23, 1
-; GFX11-NEXT: v_readlane_b32 s34, v23, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v23, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -11991,33 +12051,44 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB26_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v54, v53, s6
; VI-NEXT: v_perm_b32 v1, v52, v51, s6
-; VI-NEXT: v_perm_b32 v2, v50, v49, s6
; VI-NEXT: v_perm_b32 v3, v48, v39, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_perm_b32 v0, v54, v53, s6
+; VI-NEXT: v_perm_b32 v2, v50, v49, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_perm_b32 v3, v36, v35, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -12057,9 +12128,11 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -12067,19 +12140,20 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr24
@@ -12115,7 +12189,8 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -12138,9 +12213,10 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
@@ -13394,9 +13470,9 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
@@ -13409,12 +13485,13 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
@@ -13438,27 +13515,28 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
@@ -13473,11 +13551,12 @@ define <16 x i32> @bitcast_v64i8_to_v16i32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
@@ -14057,80 +14136,96 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB27_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s73
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s73
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s61
+; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s61
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s57
+; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s57
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s45
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s45
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s41
+; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s13
+; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s13
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s9
+; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s9
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s6, v26, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v24, v22, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s6, v26, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; VI-NEXT: v_or_b32_e32 v15, v35, v15
; VI-NEXT: s_cbranch_execnz .LBB27_3
; VI-NEXT: .LBB27_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -14352,81 +14447,98 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
-; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s73
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s73
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s61
+; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s61
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s57
+; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s57
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s45
+; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s45
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s41
+; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s41
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
-; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s13
+; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v9, s13
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s9
+; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_mov_b32_e32 v10, s9
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -14635,63 +14747,74 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-TRUE16-NEXT: .LBB27_2: ; %cmp.true
@@ -14706,17 +14829,18 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -14907,63 +15031,74 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-FAKE16-NEXT: .LBB27_2: ; %cmp.true
@@ -14978,17 +15113,18 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -23729,86 +23865,102 @@ define <64 x i8> @bitcast_v16f32_to_v64i8(<16 x float> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
-; VI-NEXT: v_lshl_or_b32 v1, v21, 16, v1
-; VI-NEXT: v_perm_b32 v2, v2, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v1, v1, v21
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_perm_b32 v2, v2, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v60, s4
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v60, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v57, s4
; VI-NEXT: v_perm_b32 v2, v56, v26, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v57, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v47, s4
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v47, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v44, s4
; VI-NEXT: v_perm_b32 v2, v43, v25, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v44, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v42, s4
; VI-NEXT: v_perm_b32 v2, v41, v40, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v42, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v55, s4
; VI-NEXT: v_perm_b32 v2, v54, v22, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v53, s4
; VI-NEXT: v_perm_b32 v2, v52, v51, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v11, v50, s4
; VI-NEXT: v_perm_b32 v2, v49, v19, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v11, v50, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v12, v48, s4
; VI-NEXT: v_perm_b32 v2, v39, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v12, v48, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v13, v37, s4
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v13, v37, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v14, v35, s4
; VI-NEXT: v_perm_b32 v2, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v14, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -25326,61 +25478,73 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v18, v18, v24, s4
; VI-NEXT: v_perm_b32 v15, v15, v17, s4
-; VI-NEXT: v_lshl_or_b32 v15, v18, 16, v15
-; VI-NEXT: v_perm_b32 v16, v16, v62, s4
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v18
+; VI-NEXT: v_or_b32_e32 v15, v15, v17
; VI-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v15, v60, v61, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; VI-NEXT: v_perm_b32 v16, v16, v62, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_add_u32_e32 v16, vcc, 4, v0
; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v15, v59, v23, s4
; VI-NEXT: v_perm_b32 v13, v13, v58, s4
-; VI-NEXT: v_lshl_or_b32 v13, v15, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v13, v13, v15
; VI-NEXT: v_add_u32_e32 v15, vcc, 8, v0
; VI-NEXT: buffer_store_dword v13, v15, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v13, v14, v57, s4
; VI-NEXT: v_perm_b32 v14, v47, v56, s4
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_add_u32_e32 v14, vcc, 12, v0
; VI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v11, v11, v46, s4
; VI-NEXT: v_perm_b32 v13, v45, v22, s4
-; VI-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; VI-NEXT: v_perm_b32 v11, v11, v46, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; VI-NEXT: v_or_b32_e32 v11, v11, v13
; VI-NEXT: v_add_u32_e32 v13, vcc, 16, v0
; VI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v11, v12, v44, s4
; VI-NEXT: v_perm_b32 v12, v42, v43, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_add_u32_e32 v12, vcc, 20, v0
; VI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v9, v9, v41, s4
; VI-NEXT: v_perm_b32 v11, v40, v21, s4
-; VI-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; VI-NEXT: v_perm_b32 v9, v9, v41, s4
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v11
; VI-NEXT: v_add_u32_e32 v11, vcc, 24, v0
; VI-NEXT: buffer_store_dword v9, v11, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v9, v10, v55, s4
; VI-NEXT: v_perm_b32 v10, v53, v54, s4
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_add_u32_e32 v10, vcc, 28, v0
; VI-NEXT: buffer_store_dword v9, v10, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v7, v7, v52, s4
; VI-NEXT: v_perm_b32 v9, v51, v20, s4
-; VI-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; VI-NEXT: v_perm_b32 v7, v7, v52, s4
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_or_b32_e32 v7, v7, v9
; VI-NEXT: v_add_u32_e32 v9, vcc, 32, v0
; VI-NEXT: buffer_store_dword v7, v9, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v7, v8, v50, s4
; VI-NEXT: v_perm_b32 v8, v48, v49, s4
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_add_u32_e32 v8, vcc, 36, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v5, v5, v39, s4
; VI-NEXT: v_perm_b32 v7, v38, v19, s4
-; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; VI-NEXT: v_perm_b32 v5, v5, v39, s4
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 40, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v6, v37, s4
; VI-NEXT: v_perm_b32 v6, v35, v36, s4
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 44, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
@@ -25409,24 +25573,28 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v5, v33, v5, s4
-; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v3, v3, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 48, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v3, v4, v32, s4
; VI-NEXT: v_perm_b32 v4, v30, v31, s4
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 52, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v3, v28, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v27, s4
; VI-NEXT: v_perm_b32 v2, v25, v26, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -25737,53 +25905,65 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v21, s14
; GFX9-NEXT: .LBB49_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
+; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v19, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v18
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -25808,22 +25988,26 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -26066,55 +26250,71 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
; GFX11-NEXT: .LBB49_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v82, v24, 16, v13
+; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
+; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v81, v86, 16, v18
; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
+; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v83, v84, 16, v13
-; GFX11-NEXT: v_lshl_or_b32 v13, v22, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
+; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v80, v25, 16, v17
-; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
+; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v12, v18, 16, v12
+; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v8, v17, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v9, v18, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
+; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v17, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v3, v15, 16, v19
-; GFX11-NEXT: v_lshl_or_b32 v4, v18, 16, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
+; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
+; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
@@ -26844,33 +27044,44 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB50_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v54, v53, s6
; VI-NEXT: v_perm_b32 v1, v52, v51, s6
-; VI-NEXT: v_perm_b32 v2, v50, v49, s6
; VI-NEXT: v_perm_b32 v3, v48, v39, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_perm_b32 v0, v54, v53, s6
+; VI-NEXT: v_perm_b32 v2, v50, v49, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_perm_b32 v3, v36, v35, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -26910,9 +27121,11 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -26920,19 +27133,20 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr24
@@ -26968,7 +27182,8 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -26991,9 +27206,10 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
@@ -28247,9 +28463,9 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
@@ -28262,12 +28478,13 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
@@ -28291,27 +28508,28 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
@@ -28326,11 +28544,12 @@ define <16 x float> @bitcast_v64i8_to_v16f32(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
@@ -28910,80 +29129,96 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s73
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s73
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s61
+; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s61
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s57
+; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s57
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s45
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s45
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s41
+; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s13
+; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s13
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s9
+; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s9
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s6, v26, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v24, v22, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s6, v26, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; VI-NEXT: v_or_b32_e32 v15, v35, v15
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -29205,81 +29440,98 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
-; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s73
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s73
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s61
+; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s61
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s57
+; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s57
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s45
+; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s45
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s41
+; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s41
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
-; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s13
+; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v9, s13
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s9
+; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_mov_b32_e32 v10, s9
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -29488,63 +29740,74 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-TRUE16-NEXT: .LBB51_2: ; %cmp.true
@@ -29559,17 +29822,18 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -29760,63 +30024,74 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-FAKE16-NEXT: .LBB51_2: ; %cmp.true
@@ -29831,17 +30106,18 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -37715,86 +37991,102 @@ define <64 x i8> @bitcast_v8i64_to_v64i8(<8 x i64> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
-; VI-NEXT: v_lshl_or_b32 v1, v21, 16, v1
-; VI-NEXT: v_perm_b32 v2, v2, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v1, v1, v21
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_perm_b32 v2, v2, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v60, s4
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v60, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v57, s4
; VI-NEXT: v_perm_b32 v2, v56, v26, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v57, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v47, s4
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v47, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v44, s4
; VI-NEXT: v_perm_b32 v2, v43, v25, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v44, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v42, s4
; VI-NEXT: v_perm_b32 v2, v41, v40, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v42, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v55, s4
; VI-NEXT: v_perm_b32 v2, v54, v22, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v53, s4
; VI-NEXT: v_perm_b32 v2, v52, v51, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v11, v50, s4
; VI-NEXT: v_perm_b32 v2, v49, v19, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v11, v50, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v12, v48, s4
; VI-NEXT: v_perm_b32 v2, v39, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v12, v48, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v13, v37, s4
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v13, v37, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v14, v35, s4
; VI-NEXT: v_perm_b32 v2, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v14, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -39152,116 +39444,132 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; VI-NEXT: s_lshr_b32 s66, s16, 16
; VI-NEXT: s_lshr_b32 s67, s16, 8
; VI-NEXT: .LBB69_3: ; %end
-; VI-NEXT: v_mov_b32_e32 v1, s67
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s44
-; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s67
; VI-NEXT: v_perm_b32 v3, s66, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_mov_b32_e32 v3, s55
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s65
-; VI-NEXT: v_mov_b32_e32 v3, s55
-; VI-NEXT: v_perm_b32 v1, s17, v1, v2
; VI-NEXT: v_perm_b32 v3, s64, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s17, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s54
; VI-NEXT: v_mov_b32_e32 v3, s42
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s54
; VI-NEXT: v_perm_b32 v3, s53, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s52
; VI-NEXT: v_mov_b32_e32 v3, s50
-; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s52
; VI-NEXT: v_perm_b32 v3, s51, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s49
; VI-NEXT: v_mov_b32_e32 v3, s40
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s49
; VI-NEXT: v_perm_b32 v3, s48, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s39
; VI-NEXT: v_mov_b32_e32 v3, s37
-; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s39
; VI-NEXT: v_perm_b32 v3, s38, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s36
; VI-NEXT: v_mov_b32_e32 v3, s14
-; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s36
; VI-NEXT: v_perm_b32 v3, s35, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s34
; VI-NEXT: v_mov_b32_e32 v3, s30
-; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s34
; VI-NEXT: v_perm_b32 v3, s31, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s91
; VI-NEXT: v_mov_b32_e32 v3, s12
-; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s91
; VI-NEXT: v_perm_b32 v3, s90, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s89
; VI-NEXT: v_mov_b32_e32 v3, s79
-; VI-NEXT: v_perm_b32 v1, s25, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s89
; VI-NEXT: v_perm_b32 v3, s88, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s25, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s78
; VI-NEXT: v_mov_b32_e32 v3, s10
-; VI-NEXT: v_perm_b32 v1, s26, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s78
; VI-NEXT: v_perm_b32 v3, s77, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s26, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_mov_b32_e32 v3, s74
-; VI-NEXT: v_perm_b32 v1, s27, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_perm_b32 v3, s75, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s27, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s73
; VI-NEXT: v_mov_b32_e32 v3, s8
-; VI-NEXT: v_perm_b32 v1, s28, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s73
; VI-NEXT: v_perm_b32 v3, s72, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s28, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_mov_b32_e32 v3, s61
-; VI-NEXT: v_perm_b32 v1, s29, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_perm_b32 v3, s62, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s29, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s60
; VI-NEXT: v_mov_b32_e32 v3, s6
-; VI-NEXT: v_perm_b32 v1, s4, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s60
; VI-NEXT: v_perm_b32 v3, s59, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s4, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_perm_b32 v1, s5, v1, v2
; VI-NEXT: v_perm_b32 v2, s57, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: v_readlane_b32 s30, v4, 18
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -39483,102 +39791,118 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX9-NEXT: s_lshr_b32 s54, s16, 16
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
; GFX9-NEXT: .LBB69_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v1, s55
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s44
-; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
+; GFX9-NEXT: v_mov_b32_e32 v1, s55
; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s51
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s53
-; GFX9-NEXT: v_mov_b32_e32 v3, s51
-; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s42
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s50
-; GFX9-NEXT: v_mov_b32_e32 v3, s42
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s38
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s48
-; GFX9-NEXT: v_mov_b32_e32 v3, s38
-; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s40
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s37
-; GFX9-NEXT: v_mov_b32_e32 v3, s40
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s31
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s35
-; GFX9-NEXT: v_mov_b32_e32 v3, s31
-; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s30
-; GFX9-NEXT: v_mov_b32_e32 v3, s14
-; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s92
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s94
-; GFX9-NEXT: v_mov_b32_e32 v3, s92
-; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s91
-; GFX9-NEXT: v_mov_b32_e32 v3, s12
-; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s79
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s89
-; GFX9-NEXT: v_mov_b32_e32 v3, s79
-; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: v_mov_b32_e32 v1, s78
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
-; GFX9-NEXT: v_perm_b32 v1, s26, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s26, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_mov_b32_e32 v1, s76
-; GFX9-NEXT: v_mov_b32_e32 v3, s74
-; GFX9-NEXT: v_perm_b32 v1, s27, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s27, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_mov_b32_e32 v1, s73
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
-; GFX9-NEXT: v_perm_b32 v1, s28, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s28, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s61
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_mov_b32_e32 v3, s61
-; GFX9-NEXT: v_perm_b32 v1, s29, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s29, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v1, s60
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
-; GFX9-NEXT: v_perm_b32 v1, s4, v1, v2
; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s4, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v1, s58
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_perm_b32 v1, s5, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s57, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: v_readlane_b32 s30, v4, 14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_readlane_b32 s31, v4, 15
@@ -39788,59 +40112,72 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
; GFX11-NEXT: .LBB69_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v12, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v1, s0, s48, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
+; GFX11-NEXT: v_readlane_b32 s34, v23, 0
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
-; GFX11-NEXT: v_perm_b32 v3, s1, s38, v12
; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
-; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
+; GFX11-NEXT: v_perm_b32 v1, s0, s48, v12
+; GFX11-NEXT: v_perm_b32 v3, s1, s38, v12
; GFX11-NEXT: v_perm_b32 v6, s2, s35, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_perm_b32 v8, s30, vcc_hi, v12
-; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
-; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
-; GFX11-NEXT: v_lshl_or_b32 v3, v5, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
+; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
+; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
+; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
+; GFX11-NEXT: v_or_b32_e32 v3, v6, v5
; GFX11-NEXT: v_perm_b32 v5, s93, s92, v12
-; GFX11-NEXT: v_perm_b32 v8, s90, s12, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
; GFX11-NEXT: v_perm_b32 v6, s16, s94, v12
-; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
-; GFX11-NEXT: v_perm_b32 v13, s18, s89, v12
+; GFX11-NEXT: v_perm_b32 v8, s90, s12, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v5
+; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
+; GFX11-NEXT: v_perm_b32 v13, s18, s89, v12
; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
; GFX11-NEXT: v_or_b32_e32 v5, v6, v9
; GFX11-NEXT: v_perm_b32 v9, s88, s78, v12
; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v8
-; GFX11-NEXT: v_perm_b32 v8, s19, s79, v12
; GFX11-NEXT: v_perm_b32 v10, s77, s10, v12
; GFX11-NEXT: v_perm_b32 v11, s75, s74, v12
+; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
+; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
+; GFX11-NEXT: v_or_b32_e32 v7, v13, v8
+; GFX11-NEXT: v_perm_b32 v8, s19, s79, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_perm_b32 v13, s20, s76, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-NEXT: v_perm_b32 v15, s21, s73, v12
-; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; GFX11-NEXT: v_perm_b32 v16, s22, s63, v12
-; GFX11-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v9, v10, 16, v13
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX11-NEXT: v_or_b32_e32 v9, v13, v10
; GFX11-NEXT: v_perm_b32 v13, s62, s61, v12
-; GFX11-NEXT: v_lshl_or_b32 v10, v11, 16, v15
-; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
-; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v16
+; GFX11-NEXT: v_or_b32_e32 v10, v15, v11
+; GFX11-NEXT: v_or_b32_e32 v11, v16, v14
; GFX11-NEXT: v_perm_b32 v14, s59, s6, v12
-; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
; GFX11-NEXT: v_perm_b32 v17, s57, s56, v12
; GFX11-NEXT: v_perm_b32 v18, s46, s4, v12
-; GFX11-NEXT: v_perm_b32 v19, s25, s47, v12
; GFX11-NEXT: v_perm_b32 v20, s44, s42, v12
+; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-NEXT: v_perm_b32 v19, s25, s47, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v21, s26, s45, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-NEXT: v_perm_b32 v22, s27, s43, v12
-; GFX11-NEXT: v_lshl_or_b32 v12, v13, 16, v15
-; GFX11-NEXT: v_lshl_or_b32 v13, v14, 16, v16
-; GFX11-NEXT: v_lshl_or_b32 v14, v17, 16, v19
-; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v21
-; GFX11-NEXT: v_lshl_or_b32 v16, v20, 16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v20
+; GFX11-NEXT: v_or_b32_e32 v12, v15, v13
+; GFX11-NEXT: v_or_b32_e32 v13, v16, v14
+; GFX11-NEXT: v_or_b32_e32 v14, v19, v17
+; GFX11-NEXT: v_or_b32_e32 v15, v21, v18
+; GFX11-NEXT: v_or_b32_e32 v16, v22, v20
; GFX11-NEXT: v_readlane_b32 s30, v23, 7
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
@@ -39854,7 +40191,6 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: v_readlane_b32 s37, v23, 3
; GFX11-NEXT: v_readlane_b32 s36, v23, 2
; GFX11-NEXT: v_readlane_b32 s35, v23, 1
-; GFX11-NEXT: v_readlane_b32 s34, v23, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v23, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -40619,33 +40955,44 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB70_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v54, v53, s6
; VI-NEXT: v_perm_b32 v1, v52, v51, s6
-; VI-NEXT: v_perm_b32 v2, v50, v49, s6
; VI-NEXT: v_perm_b32 v3, v48, v39, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_perm_b32 v0, v54, v53, s6
+; VI-NEXT: v_perm_b32 v2, v50, v49, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_perm_b32 v3, v36, v35, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -40685,9 +41032,11 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -40695,19 +41044,20 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr24
@@ -40743,7 +41093,8 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -40766,9 +41117,10 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
@@ -42022,9 +42374,9 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
@@ -42037,12 +42389,13 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
@@ -42066,27 +42419,28 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
@@ -42101,11 +42455,12 @@ define <8 x i64> @bitcast_v64i8_to_v8i64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
@@ -42685,80 +43040,96 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB71_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s73
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s73
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s61
+; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s61
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s57
+; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s57
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s45
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s45
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s41
+; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s13
+; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s13
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s9
+; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s9
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s6, v26, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v24, v22, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s6, v26, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; VI-NEXT: v_or_b32_e32 v15, v35, v15
; VI-NEXT: s_cbranch_execnz .LBB71_3
; VI-NEXT: .LBB71_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -42980,81 +43351,98 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
-; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s73
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s73
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s61
+; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s61
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s57
+; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s57
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s45
+; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s45
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s41
+; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s41
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
-; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s13
+; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v9, s13
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s9
+; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_mov_b32_e32 v10, s9
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -43263,63 +43651,74 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-TRUE16-NEXT: .LBB71_2: ; %cmp.true
@@ -43334,17 +43733,18 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -43535,63 +43935,74 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-FAKE16-NEXT: .LBB71_2: ; %cmp.true
@@ -43606,17 +44017,18 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -50769,86 +51181,102 @@ define <64 x i8> @bitcast_v8f64_to_v64i8(<8 x double> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
-; VI-NEXT: v_lshl_or_b32 v1, v21, 16, v1
-; VI-NEXT: v_perm_b32 v2, v2, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v1, v1, v21
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_perm_b32 v2, v2, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v60, s4
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v60, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v57, s4
; VI-NEXT: v_perm_b32 v2, v56, v26, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v57, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v47, s4
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v47, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v44, s4
; VI-NEXT: v_perm_b32 v2, v43, v25, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v44, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v42, s4
; VI-NEXT: v_perm_b32 v2, v41, v40, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v42, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v55, s4
; VI-NEXT: v_perm_b32 v2, v54, v22, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v53, s4
; VI-NEXT: v_perm_b32 v2, v52, v51, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v11, v50, s4
; VI-NEXT: v_perm_b32 v2, v49, v19, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v11, v50, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v12, v48, s4
; VI-NEXT: v_perm_b32 v2, v39, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v12, v48, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v13, v37, s4
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v13, v37, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v14, v35, s4
; VI-NEXT: v_perm_b32 v2, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v14, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -52343,51 +52771,61 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v24, v57, v24, s4
; VI-NEXT: v_perm_b32 v15, v15, v58, s4
-; VI-NEXT: v_lshl_or_b32 v15, v24, 16, v15
; VI-NEXT: v_perm_b32 v16, v16, v18, s4
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v24
+; VI-NEXT: v_or_b32_e32 v15, v15, v18
; VI-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v15, v17, v62, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v16, v15
; VI-NEXT: v_add_u32_e32 v16, vcc, 4, v0
; VI-NEXT: buffer_store_dword v15, v16, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v15, v44, v23, s4
; VI-NEXT: v_perm_b32 v13, v13, v45, s4
-; VI-NEXT: v_lshl_or_b32 v13, v15, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v13, v13, v15
; VI-NEXT: v_add_u32_e32 v15, vcc, 8, v0
; VI-NEXT: buffer_store_dword v13, v15, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v13, v14, v61, s4
; VI-NEXT: v_perm_b32 v14, v60, v59, s4
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_add_u32_e32 v14, vcc, 12, v0
; VI-NEXT: buffer_store_dword v13, v14, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v11, v11, v40, s4
; VI-NEXT: v_perm_b32 v13, v55, v22, s4
-; VI-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; VI-NEXT: v_perm_b32 v11, v11, v40, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; VI-NEXT: v_or_b32_e32 v11, v11, v13
; VI-NEXT: v_add_u32_e32 v13, vcc, 16, v0
; VI-NEXT: buffer_store_dword v11, v13, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v11, v12, v56, s4
; VI-NEXT: v_perm_b32 v12, v47, v46, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_add_u32_e32 v12, vcc, 20, v0
; VI-NEXT: buffer_store_dword v11, v12, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v7, v7, v52, s4
; VI-NEXT: v_perm_b32 v11, v50, v21, s4
-; VI-NEXT: v_lshl_or_b32 v7, v11, 16, v7
+; VI-NEXT: v_perm_b32 v7, v7, v52, s4
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v11
; VI-NEXT: v_add_u32_e32 v11, vcc, 24, v0
; VI-NEXT: buffer_store_dword v7, v11, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v7, v8, v43, s4
; VI-NEXT: v_perm_b32 v8, v42, v41, s4
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_add_u32_e32 v8, vcc, 28, v0
; VI-NEXT: buffer_store_dword v7, v8, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v5, v5, v49, s4
; VI-NEXT: v_perm_b32 v7, v39, v20, s4
-; VI-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; VI-NEXT: v_perm_b32 v5, v5, v49, s4
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v5, v5, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 32, v0
; VI-NEXT: buffer_store_dword v5, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v5, v6, v54, s4
; VI-NEXT: v_perm_b32 v6, v53, v51, s4
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 36, v0
; VI-NEXT: buffer_store_dword v5, v6, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
@@ -52416,24 +52854,28 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v5, v35, v5, s4
-; VI-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v3, v3, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 40, v0
; VI-NEXT: buffer_store_dword v3, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v3, v4, v48, s4
; VI-NEXT: v_perm_b32 v4, v38, v37, s4
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 44, v0
; VI-NEXT: buffer_store_dword v3, v4, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v3, v30, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v2, v34, s4
; VI-NEXT: v_perm_b32 v2, v33, v32, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
@@ -52441,12 +52883,14 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; VI-NEXT: v_perm_b32 v1, v9, v28, s4
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v19, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v29, s4
; VI-NEXT: v_perm_b32 v2, v27, v25, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -52755,45 +53199,55 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: .LBB85_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX9-NEXT: v_perm_b32 v24, v57, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v15, v59, s4
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
; GFX9-NEXT: v_perm_b32 v18, v56, v23, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v24
+; GFX9-NEXT: v_or_b32_e32 v15, v15, v23
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v17, v62, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_perm_b32 v13, v13, v47, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v18, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v18
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v61, s4
; GFX9-NEXT: v_perm_b32 v14, v60, v58, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v9, v9, v43, s4
; GFX9-NEXT: v_perm_b32 v13, v42, v22, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v13, 16, v9
+; GFX9-NEXT: v_perm_b32 v9, v9, v43, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v13
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v9, v10, v46, s4
; GFX9-NEXT: v_perm_b32 v10, v45, v44, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v7, v7, v51, s4
; GFX9-NEXT: v_perm_b32 v9, v50, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_perm_b32 v7, v7, v51, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v7, v8, v41, s4
; GFX9-NEXT: v_perm_b32 v8, v40, v55, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_perm_b32 v24, v57, v24, s4
-; GFX9-NEXT: v_perm_b32 v15, v15, v59, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v5, v5, v48, s4
; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v24, 16, v15
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v17, v62, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v48, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v5, v6, v54, s4
; GFX9-NEXT: v_perm_b32 v6, v53, v52, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -52818,33 +53272,39 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v35, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v3, v4, v49, s4
; GFX9-NEXT: v_perm_b32 v4, v39, v37, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v30, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v1, v2, v34, s4
; GFX9-NEXT: v_perm_b32 v2, v33, v32, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v1, v11, v27, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v26, v2, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, v28, v19, s4
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v12, v29, s4
-; GFX9-NEXT: v_perm_b32 v2, v28, v19, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -53080,56 +53540,70 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v87, s45 :: v_dual_mov_b32 v86, s43
; GFX11-NEXT: .LBB85_5: ; %end
; GFX11-NEXT: v_perm_b32 v26, v69, v26, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v17, v17, v68, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_perm_b32 v27, v82, v27, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-NEXT: v_perm_b32 v82, v96, v87, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v17, v17, v68, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v21, v21, v81, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v22, v22, v86, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
; GFX11-NEXT: v_perm_b32 v68, v85, v84, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v86, v26, 16, v17
-; GFX11-NEXT: v_perm_b32 v17, v18, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v24, v54, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v11, v11, v53, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v84, v27, 16, v21
-; GFX11-NEXT: v_lshl_or_b32 v85, v82, 16, v22
+; GFX11-NEXT: v_perm_b32 v22, v22, v86, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v82
+; GFX11-NEXT: v_or_b32_e32 v86, v17, v26
+; GFX11-NEXT: v_perm_b32 v17, v18, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v64, v25, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v84, v21, v27
+; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v68
+; GFX11-NEXT: v_perm_b32 v11, v11, v53, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-NEXT: v_or_b32_e32 v85, v22, v69
; GFX11-NEXT: v_perm_b32 v22, v80, v71, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v15, v15, v55, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_or_b32_e32 v87, v17, v21
+; GFX11-NEXT: v_or_b32_e32 v17, v11, v24
+; GFX11-NEXT: v_perm_b32 v11, v12, v66, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v49, v23, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v16, v16, v70, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
+; GFX11-NEXT: v_perm_b32 v18, v67, v65, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v21, v52, v51, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v19, v37, v19, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v87, v68, 16, v17
-; GFX11-NEXT: v_lshl_or_b32 v17, v24, 16, v11
-; GFX11-NEXT: v_perm_b32 v11, v12, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v12, v49, v23, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v7, v7, v39, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v15, v18, 16, v15
-; GFX11-NEXT: v_perm_b32 v18, v67, v65, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v16, v22, 16, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-NEXT: v_or_b32_e32 v16, v16, v22
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-NEXT: v_perm_b32 v8, v8, v50, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v21
; GFX11-NEXT: v_perm_b32 v5, v5, v35, 0xc0c0004
; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT: v_lshl_or_b32 v21, v12, 16, v7
+; GFX11-NEXT: v_or_b32_e32 v21, v7, v12
; GFX11-NEXT: v_perm_b32 v7, v48, v38, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v36, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v11
+; GFX11-NEXT: v_or_b32_e32 v18, v11, v18
; GFX11-NEXT: v_or_b32_e32 v22, v8, v22
; GFX11-NEXT: v_or_b32_e32 v23, v5, v19
; GFX11-NEXT: v_perm_b32 v5, v31, v13, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v3, v3, v30, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v8, v34, v33, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v9, v14, v9, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v4, v4, v32, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v11, v29, v28, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v6, v36, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_perm_b32 v3, v3, v30, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, v4, v32, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-NEXT: v_perm_b32 v10, v1, v10, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-NEXT: v_perm_b32 v12, v2, v20, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v24, v7, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v8, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v3, v9, 16, v10
-; GFX11-NEXT: v_lshl_or_b32 v4, v11, 16, v12
+; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-NEXT: v_or_b32_e32 v24, v6, v7
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v8
+; GFX11-NEXT: v_or_b32_e32 v3, v10, v9
+; GFX11-NEXT: v_or_b32_e32 v4, v12, v11
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[84:87], off
@@ -53859,33 +54333,44 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB86_2
; VI-NEXT: ; %bb.1: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v54, v53, s6
; VI-NEXT: v_perm_b32 v1, v52, v51, s6
-; VI-NEXT: v_perm_b32 v2, v50, v49, s6
; VI-NEXT: v_perm_b32 v3, v48, v39, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_perm_b32 v0, v54, v53, s6
+; VI-NEXT: v_perm_b32 v2, v50, v49, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_perm_b32 v3, v36, v35, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_perm_b32 v2, v38, v37, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_perm_b32 v4, v32, v31, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_perm_b32 v3, v34, v33, s6
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_perm_b32 v4, v16, v17, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_perm_b32 v5, v20, v21, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v9, v26, v27, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v28, v29, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_perm_b32 v11, v43, v42, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v55, v63, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v60, v59, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: ; implicit-def: $vgpr54
; VI-NEXT: ; implicit-def: $vgpr53
; VI-NEXT: ; implicit-def: $vgpr52
@@ -53925,9 +54410,11 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v14, v15, v14, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v7, v8, v7, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -53935,19 +54422,20 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v8, v30, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v57, v56, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v47, v46, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v45, v44, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v41, v40, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v62, v61, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v58, v24, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr24
@@ -53983,7 +54471,8 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v15, v16, v15, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
; VI-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -54006,9 +54495,10 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: ; implicit-def: $vgpr25
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr25
; VI-NEXT: ; implicit-def: $vgpr25
@@ -55262,9 +55752,9 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v8, 8, v21
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v10
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, 0x300, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v10, v9
@@ -55277,12 +55767,13 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v6, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v9, 8, v25
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v27
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v28, 3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v7, v30, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v10, v6
@@ -55306,27 +55797,28 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v116, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, 0x300, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v11, 8, v115
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v114, 3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v8, v7
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v113, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v103
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v12, 8, v112
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v102, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v15, v101, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v10, 0x300, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v12, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v14
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v13, 8, v100
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v15
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v99
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, 0x300, v11
; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, 0x300, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
@@ -55341,11 +55833,12 @@ define <8 x double> @bitcast_v64i8_to_v8f64(<64 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v11, v97, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v14, 8, v96
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v15, 8, v87
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-FAKE16-NEXT: v_add_nc_u16 v12, v86, 3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v14, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v14, v85, 3
@@ -55925,80 +56418,96 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB87_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s75
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s76, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s73
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s63
-; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s73
; VI-NEXT: v_perm_b32 v5, s72, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s61
+; VI-NEXT: v_perm_b32 v4, s74, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s59
-; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s61
; VI-NEXT: v_perm_b32 v6, s60, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s57
+; VI-NEXT: v_perm_b32 v5, s62, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s47
-; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s57
; VI-NEXT: v_perm_b32 v7, s56, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s45
+; VI-NEXT: v_perm_b32 v6, s58, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s43
-; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s45
; VI-NEXT: v_perm_b32 v8, s44, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s41
+; VI-NEXT: v_perm_b32 v7, s46, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s15
-; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s41
; VI-NEXT: v_perm_b32 v9, s40, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s13
+; VI-NEXT: v_perm_b32 v8, s42, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s11
-; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s13
; VI-NEXT: v_perm_b32 v10, s12, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s9
+; VI-NEXT: v_perm_b32 v9, s14, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s7
-; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s9
; VI-NEXT: v_perm_b32 v12, s8, v12, v11
+; VI-NEXT: v_perm_b32 v10, s10, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s6, v26, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v24, v22, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s6, v26, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v32, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v28, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v30, v29, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v21, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v25, v23, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v17, v16, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v19, v18, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; VI-NEXT: v_or_b32_e32 v15, v35, v15
; VI-NEXT: s_cbranch_execnz .LBB87_3
; VI-NEXT: .LBB87_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -56220,81 +56729,98 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
-; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_mov_b32_e32 v2, s25
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v3, s29
; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s73
+; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_mov_b32_e32 v4, s73
; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s61
+; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_mov_b32_e32 v5, s61
; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s57
+; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_mov_b32_e32 v6, s57
; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
-; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s45
+; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v7, s45
; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s41
+; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_mov_b32_e32 v8, s41
; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
-; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s13
+; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v9, s13
; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s9
+; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_mov_b32_e32 v10, s9
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -56503,63 +57029,74 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-TRUE16-NEXT: .LBB87_2: ; %cmp.true
@@ -56574,17 +57111,18 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -56775,63 +57313,74 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v12
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v10, 16, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v13, 16, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v12, 16, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v17
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v16, 16, v19
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v18, 16, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-FAKE16-NEXT: .LBB87_2: ; %cmp.true
@@ -56846,17 +57395,18 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
; GFX11-FAKE16-NEXT: s_add_i32 s20, s20, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
; GFX11-FAKE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-FAKE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v5
@@ -63845,22 +64395,30 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB96_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v17, 3
-; VI-NEXT: v_add_u16_e32 v45, 3, v12
; VI-NEXT: v_add_u16_sdwa v28, v12, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v47, 3, v11
; VI-NEXT: v_add_u16_sdwa v33, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v62, 3, v16
; VI-NEXT: v_add_u16_sdwa v26, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v51, 3, v15
; VI-NEXT: v_add_u16_sdwa v29, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v41, 3, v10
; VI-NEXT: v_add_u16_sdwa v30, v10, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v43, 3, v9
; VI-NEXT: v_add_u16_sdwa v35, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v12, v28, 16, v45
-; VI-NEXT: v_lshl_or_b32 v11, v33, 16, v47
-; VI-NEXT: v_lshl_or_b32 v16, v26, 16, v62
-; VI-NEXT: v_lshl_or_b32 v15, v29, 16, v51
+; VI-NEXT: v_add_u16_e32 v45, 3, v12
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v28
+; VI-NEXT: v_add_u16_e32 v47, 3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v33
+; VI-NEXT: v_add_u16_e32 v62, 3, v16
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v26
+; VI-NEXT: v_add_u16_e32 v51, 3, v15
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v29
+; VI-NEXT: v_add_u16_sdwa v32, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_sdwa v37, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v41, 3, v10
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v30
+; VI-NEXT: v_add_u16_e32 v43, 3, v9
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v35
+; VI-NEXT: v_or_b32_e32 v12, v45, v12
+; VI-NEXT: v_or_b32_e32 v11, v47, v11
+; VI-NEXT: v_or_b32_e32 v16, v62, v16
+; VI-NEXT: v_or_b32_e32 v15, v51, v15
; VI-NEXT: v_add_u16_sdwa v38, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v49, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v36, v4, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
@@ -63868,40 +64426,48 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_add_u16_sdwa v34, v6, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v39, v5, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_e32 v50, 3, v8
-; VI-NEXT: v_add_u16_sdwa v32, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v32
; VI-NEXT: v_add_u16_e32 v52, 3, v7
-; VI-NEXT: v_add_u16_sdwa v37, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v10, v30, 16, v41
-; VI-NEXT: v_lshl_or_b32 v9, v35, 16, v43
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v37
+; VI-NEXT: v_or_b32_e32 v10, v41, v10
+; VI-NEXT: v_or_b32_e32 v9, v43, v9
; VI-NEXT: v_add_u16_sdwa v27, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_add_u16_sdwa v31, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
; VI-NEXT: v_add_u16_e32 v59, 3, v6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v34
; VI-NEXT: v_add_u16_e32 v61, 3, v5
-; VI-NEXT: v_lshl_or_b32 v8, v32, 16, v50
-; VI-NEXT: v_lshl_or_b32 v7, v37, 16, v52
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v39
+; VI-NEXT: v_or_b32_e32 v8, v50, v8
+; VI-NEXT: v_or_b32_e32 v7, v52, v7
; VI-NEXT: v_add_u16_e32 v58, 3, v14
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v27
; VI-NEXT: v_add_u16_e32 v60, 3, v13
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v31
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
; VI-NEXT: v_add_u16_e32 v46, 3, v4
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v36
; VI-NEXT: v_add_u16_e32 v56, 3, v3
-; VI-NEXT: v_lshl_or_b32 v6, v34, 16, v59
-; VI-NEXT: v_lshl_or_b32 v5, v39, 16, v61
-; VI-NEXT: v_lshl_or_b32 v14, v27, 16, v58
-; VI-NEXT: v_lshl_or_b32 v13, v31, 16, v60
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v48
+; VI-NEXT: v_or_b32_e32 v6, v59, v6
+; VI-NEXT: v_or_b32_e32 v5, v61, v5
+; VI-NEXT: v_or_b32_e32 v14, v58, v14
+; VI-NEXT: v_or_b32_e32 v13, v60, v13
; VI-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
; VI-NEXT: v_add_u16_e32 v53, 3, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v38
; VI-NEXT: v_add_u16_e32 v55, 3, v1
-; VI-NEXT: v_lshl_or_b32 v4, v36, 16, v46
-; VI-NEXT: v_lshl_or_b32 v3, v48, 16, v56
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v49
+; VI-NEXT: v_or_b32_e32 v4, v46, v4
+; VI-NEXT: v_or_b32_e32 v3, v56, v3
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[13:14]
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v13
; VI-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
-; VI-NEXT: v_lshl_or_b32 v2, v38, 16, v53
-; VI-NEXT: v_lshl_or_b32 v1, v49, 16, v55
+; VI-NEXT: v_or_b32_e32 v2, v53, v2
+; VI-NEXT: v_or_b32_e32 v1, v55, v1
; VI-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v13, 8, v12
; VI-NEXT: v_lshrrev_b64 v[23:24], 24, v[3:4]
@@ -63949,58 +64515,67 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v1, v49, v24, s4
; VI-NEXT: v_perm_b32 v2, v55, v57, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
+; VI-NEXT: v_perm_b32 v2, v38, v63, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v53, v44, s4
-; VI-NEXT: v_perm_b32 v2, v38, v63, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v48, v23, s4
; VI-NEXT: v_perm_b32 v2, v56, v42, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v46, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v39, v22, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v61, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v34, v40, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v59, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v37, v21, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v52, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v50, v17, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v32, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v35, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v43, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
@@ -64009,21 +64584,24 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v41, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v30, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v33, v19, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v47, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v28, v54, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v45, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
@@ -64032,7 +64610,8 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v31, v2, s4
; VI-NEXT: v_perm_b32 v1, v60, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
@@ -64041,7 +64620,8 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v58, v1, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v27, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
@@ -64050,15 +64630,17 @@ define <64 x i8> @bitcast_v32i16_to_v64i8(<32 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v29, v2, s4
; VI-NEXT: v_perm_b32 v1, v51, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v26, v25, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v62, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -65640,116 +66222,132 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; VI-NEXT: s_lshr_b32 s66, s16, 16
; VI-NEXT: s_lshr_b32 s67, s16, 8
; VI-NEXT: .LBB97_3: ; %end
-; VI-NEXT: v_mov_b32_e32 v1, s67
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v3, s44
-; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s67
; VI-NEXT: v_perm_b32 v3, s66, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s16, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
+; VI-NEXT: v_mov_b32_e32 v3, s55
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s65
-; VI-NEXT: v_mov_b32_e32 v3, s55
-; VI-NEXT: v_perm_b32 v1, s17, v1, v2
; VI-NEXT: v_perm_b32 v3, s64, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s17, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s54
; VI-NEXT: v_mov_b32_e32 v3, s42
-; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s54
; VI-NEXT: v_perm_b32 v3, s53, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s18, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s52
; VI-NEXT: v_mov_b32_e32 v3, s50
-; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s52
; VI-NEXT: v_perm_b32 v3, s51, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s19, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s49
; VI-NEXT: v_mov_b32_e32 v3, s40
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s49
; VI-NEXT: v_perm_b32 v3, s48, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s39
; VI-NEXT: v_mov_b32_e32 v3, s37
-; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s39
; VI-NEXT: v_perm_b32 v3, s38, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s21, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s36
; VI-NEXT: v_mov_b32_e32 v3, s14
-; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s36
; VI-NEXT: v_perm_b32 v3, s35, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s22, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s34
; VI-NEXT: v_mov_b32_e32 v3, s30
-; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s34
; VI-NEXT: v_perm_b32 v3, s31, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s23, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s91
; VI-NEXT: v_mov_b32_e32 v3, s12
-; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s91
; VI-NEXT: v_perm_b32 v3, s90, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s24, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s89
; VI-NEXT: v_mov_b32_e32 v3, s79
-; VI-NEXT: v_perm_b32 v1, s25, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s89
; VI-NEXT: v_perm_b32 v3, s88, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s25, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s78
; VI-NEXT: v_mov_b32_e32 v3, s10
-; VI-NEXT: v_perm_b32 v1, s26, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s78
; VI-NEXT: v_perm_b32 v3, s77, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s26, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_mov_b32_e32 v3, s74
-; VI-NEXT: v_perm_b32 v1, s27, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s76
; VI-NEXT: v_perm_b32 v3, s75, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s27, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s73
; VI-NEXT: v_mov_b32_e32 v3, s8
-; VI-NEXT: v_perm_b32 v1, s28, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s73
; VI-NEXT: v_perm_b32 v3, s72, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s28, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_mov_b32_e32 v3, s61
-; VI-NEXT: v_perm_b32 v1, s29, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s63
; VI-NEXT: v_perm_b32 v3, s62, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s29, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_mov_b32_e32 v1, s60
; VI-NEXT: v_mov_b32_e32 v3, s6
-; VI-NEXT: v_perm_b32 v1, s4, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s60
; VI-NEXT: v_perm_b32 v3, s59, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s4, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_mov_b32_e32 v1, s58
; VI-NEXT: v_mov_b32_e32 v3, s56
; VI-NEXT: v_perm_b32 v1, s5, v1, v2
; VI-NEXT: v_perm_b32 v2, s57, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: v_readlane_b32 s30, v4, 18
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
@@ -66115,53 +66713,65 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v21, s14
; GFX9-NEXT: .LBB97_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
+; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v19, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v18
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -66186,22 +66796,26 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -66444,55 +67058,71 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
; GFX11-NEXT: .LBB97_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v82, v24, 16, v13
+; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
+; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v81, v86, 16, v18
; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
+; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v83, v84, 16, v13
-; GFX11-NEXT: v_lshl_or_b32 v13, v22, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
+; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v80, v25, 16, v17
-; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
+; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v12, v18, 16, v12
+; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v8, v17, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v9, v18, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
+; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v17, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v3, v15, 16, v19
-; GFX11-NEXT: v_lshl_or_b32 v4, v18, 16, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
+; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
+; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
@@ -67399,17 +68029,28 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_perm_b32 v9, v44, v42, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v57, v46, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v11, v58, v47, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v33, v62, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v35, v34, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v49, v48, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v51, v50, s6
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; kill: killed $vgpr18
; VI-NEXT: ; implicit-def: $vgpr18
@@ -67442,14 +68083,16 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -67458,7 +68101,8 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -67466,35 +68110,37 @@ define <32 x i16> @bitcast_v64i8_to_v32i16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v17, v4, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v16, v4, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v61, v60, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v59, v56, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v31, v63, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_perm_b32 v14, v39, v38, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
-; VI-NEXT: v_perm_b32 v15, v53, v52, s6
; VI-NEXT: v_perm_b32 v16, v32, v54, s6
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_perm_b32 v15, v53, v52, s6
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr16
; VI-NEXT: ; implicit-def: $vgpr16
@@ -69824,80 +70470,96 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB99_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s45
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s57, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s46
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s47
-; VI-NEXT: v_perm_b32 v4, s56, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s46
; VI-NEXT: v_perm_b32 v5, s59, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s58
+; VI-NEXT: v_perm_b32 v4, s56, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s60
-; VI-NEXT: v_perm_b32 v5, s61, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s58
; VI-NEXT: v_perm_b32 v6, s63, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s62
+; VI-NEXT: v_perm_b32 v5, s61, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s72
-; VI-NEXT: v_perm_b32 v6, s73, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s62
; VI-NEXT: v_perm_b32 v7, s75, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s74
+; VI-NEXT: v_perm_b32 v6, s73, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s42
-; VI-NEXT: v_perm_b32 v7, s76, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s74
; VI-NEXT: v_perm_b32 v8, s43, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s6
+; VI-NEXT: v_perm_b32 v7, s76, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s7
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s6
; VI-NEXT: v_perm_b32 v9, s9, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_perm_b32 v9, s11, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s8
; VI-NEXT: v_perm_b32 v10, s13, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s12
+; VI-NEXT: v_perm_b32 v9, s11, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s14
-; VI-NEXT: v_perm_b32 v10, s15, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s12
; VI-NEXT: v_perm_b32 v12, s40, v12, v11
+; VI-NEXT: v_perm_b32 v10, s15, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s41, v16, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v18, v17, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s41, v16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v25, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v22, v19, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v30, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v27, v21, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v32, v26, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v29, v23, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v34, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v33, v28, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; VI-NEXT: v_or_b32_e32 v15, v35, v15
; VI-NEXT: s_cbranch_execnz .LBB99_3
; VI-NEXT: .LBB99_2: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v34
@@ -70451,14 +71113,16 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB99_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
@@ -70479,52 +71143,53 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v34, 8, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v50, 8, s78
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v48, 8, v14
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v31, 8, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v32, 8, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v35, 8, v16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB99_3
; GFX11-TRUE16-NEXT: .LBB99_2: ; %cmp.true
@@ -70735,23 +71400,23 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
@@ -70762,29 +71427,35 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v34, 8, s79
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v31, 8, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v35, 8, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v38, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v33, 8, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 8, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
@@ -76387,65 +77058,81 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB104_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v17, 0x200
-; VI-NEXT: v_add_f16_sdwa v29, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
-; VI-NEXT: v_add_f16_sdwa v32, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
-; VI-NEXT: v_add_f16_sdwa v30, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
-; VI-NEXT: v_add_f16_sdwa v34, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
-; VI-NEXT: v_lshl_or_b32 v43, v29, 16, v16
-; VI-NEXT: v_lshl_or_b32 v42, v32, 16, v15
; VI-NEXT: v_add_f16_sdwa v49, v2, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v49
+; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
; VI-NEXT: v_add_f16_sdwa v52, v1, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v28, v2, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v52
+; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
; VI-NEXT: v_add_f16_sdwa v39, v4, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v27, v1, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v39
+; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
; VI-NEXT: v_add_f16_sdwa v51, v3, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v23, v4, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v51
+; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
; VI-NEXT: v_add_f16_sdwa v37, v6, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v22, v3, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v37
+; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
; VI-NEXT: v_add_f16_sdwa v50, v5, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v54, v6, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v50
+; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
; VI-NEXT: v_add_f16_sdwa v35, v8, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v53, v5, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v35
+; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
; VI-NEXT: v_add_f16_sdwa v48, v7, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v25, v8, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v48
+; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
; VI-NEXT: v_add_f16_sdwa v33, v10, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v24, v7, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v33
+; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
; VI-NEXT: v_add_f16_sdwa v38, v9, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v46, v10, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v38
+; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
; VI-NEXT: v_add_f16_sdwa v31, v12, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v45, v9, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v31
+; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
; VI-NEXT: v_add_f16_sdwa v36, v11, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v41, v30, 16, v14
-; VI-NEXT: v_lshl_or_b32 v40, v34, 16, v13
+; VI-NEXT: v_or_b32_e32 v21, v12, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v36
+; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
+; VI-NEXT: v_add_f16_sdwa v30, v14, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v20, v11, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v30
+; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
+; VI-NEXT: v_add_f16_sdwa v34, v13, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v41, v14, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v34
+; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
+; VI-NEXT: v_add_f16_sdwa v29, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_f16_sdwa v32, v15, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v40, v13, v18
+; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v29
+; VI-NEXT: v_add_f16_e32 v16, 0x200, v16
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v32
+; VI-NEXT: v_add_f16_e32 v15, 0x200, v15
+; VI-NEXT: v_or_b32_e32 v43, v16, v18
+; VI-NEXT: v_or_b32_e32 v42, v15, v17
; VI-NEXT: v_lshrrev_b64 v[17:18], 24, v[42:43]
; VI-NEXT: v_lshrrev_b64 v[18:19], 24, v[40:41]
-; VI-NEXT: v_add_f16_e32 v12, 0x200, v12
-; VI-NEXT: v_add_f16_e32 v11, 0x200, v11
; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v43
-; VI-NEXT: v_add_f16_e32 v10, 0x200, v10
-; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
-; VI-NEXT: v_lshl_or_b32 v21, v31, 16, v12
-; VI-NEXT: v_lshl_or_b32 v20, v36, 16, v11
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v19, 8, v42
-; VI-NEXT: v_add_f16_e32 v4, 0x200, v4
-; VI-NEXT: v_add_f16_e32 v3, 0x200, v3
-; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT: v_add_f16_e32 v7, 0x200, v7
-; VI-NEXT: v_lshl_or_b32 v46, v33, 16, v10
-; VI-NEXT: v_lshl_or_b32 v45, v38, 16, v9
; VI-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v20
; VI-NEXT: v_lshrrev_b64 v[19:20], 24, v[20:21]
-; VI-NEXT: v_add_f16_e32 v2, 0x200, v2
-; VI-NEXT: v_add_f16_e32 v1, 0x200, v1
-; VI-NEXT: v_lshl_or_b32 v23, v39, 16, v4
-; VI-NEXT: v_lshl_or_b32 v22, v51, 16, v3
-; VI-NEXT: v_add_f16_e32 v6, 0x200, v6
-; VI-NEXT: v_add_f16_e32 v5, 0x200, v5
-; VI-NEXT: v_lshl_or_b32 v25, v35, 16, v8
-; VI-NEXT: v_lshl_or_b32 v24, v48, 16, v7
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v41
; VI-NEXT: v_lshrrev_b32_e32 v41, 8, v21
; VI-NEXT: v_lshrrev_b64 v[20:21], 24, v[45:46]
-; VI-NEXT: v_lshl_or_b32 v28, v49, 16, v2
-; VI-NEXT: v_lshl_or_b32 v27, v52, 16, v1
-; VI-NEXT: v_lshl_or_b32 v54, v37, 16, v6
-; VI-NEXT: v_lshl_or_b32 v53, v50, 16, v5
; VI-NEXT: v_lshrrev_b32_e32 v43, 8, v46
; VI-NEXT: v_lshrrev_b32_e32 v46, 8, v25
; VI-NEXT: v_lshrrev_b32_e32 v47, 8, v24
@@ -76474,86 +77161,102 @@ define <64 x i8> @bitcast_v32f16_to_v64i8(<32 x half> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v22, v52, v22, s4
; VI-NEXT: v_perm_b32 v1, v1, v26, s4
-; VI-NEXT: v_lshl_or_b32 v1, v22, 16, v1
-; VI-NEXT: v_perm_b32 v2, v2, v63, s4
+; VI-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; VI-NEXT: v_or_b32_e32 v1, v1, v22
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v49, v54, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_perm_b32 v2, v2, v63, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v51, v21, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v60, s4
; VI-NEXT: v_perm_b32 v2, v39, v53, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v60, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v58, s4
; VI-NEXT: v_perm_b32 v2, v50, v25, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v58, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v57, s4
; VI-NEXT: v_perm_b32 v2, v37, v61, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v57, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v47, s4
; VI-NEXT: v_perm_b32 v2, v48, v24, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v47, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v46, s4
; VI-NEXT: v_perm_b32 v2, v35, v59, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v46, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v44, s4
; VI-NEXT: v_perm_b32 v2, v38, v20, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v44, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v43, s4
; VI-NEXT: v_perm_b32 v2, v33, v56, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v43, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v11, v42, s4
; VI-NEXT: v_perm_b32 v2, v36, v19, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v11, v42, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v12, v41, s4
; VI-NEXT: v_perm_b32 v2, v31, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v12, v41, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v13, v40, s4
; VI-NEXT: v_perm_b32 v2, v34, v18, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v13, v40, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v14, v55, s4
; VI-NEXT: v_perm_b32 v2, v30, v28, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v14, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v32, v17, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v15, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v29, v27, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -78093,83 +78796,99 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; VI-NEXT: v_mov_b32_e32 v1, 0x200
; VI-NEXT: v_add_f16_e32 v11, s6, v1
; VI-NEXT: s_lshr_b32 s6, s16, 16
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; VI-NEXT: v_add_f16_e32 v25, s17, v1
; VI-NEXT: v_add_f16_e32 v18, s6, v1
; VI-NEXT: s_lshr_b32 s6, s19, 16
+; VI-NEXT: v_or_b32_e32 v10, v25, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v18
+; VI-NEXT: v_add_f16_e32 v33, s16, v1
; VI-NEXT: v_add_f16_e32 v12, s6, v1
; VI-NEXT: s_lshr_b32 s6, s18, 16
+; VI-NEXT: v_or_b32_e32 v9, v33, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v12
+; VI-NEXT: v_add_f16_e32 v27, s19, v1
; VI-NEXT: v_add_f16_e32 v20, s6, v1
; VI-NEXT: s_lshr_b32 s6, s21, 16
+; VI-NEXT: v_or_b32_e32 v52, v27, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v20
+; VI-NEXT: v_add_f16_e32 v35, s18, v1
; VI-NEXT: v_add_f16_e32 v13, s6, v1
; VI-NEXT: s_lshr_b32 s6, s20, 16
+; VI-NEXT: v_or_b32_e32 v51, v35, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v13
+; VI-NEXT: v_add_f16_e32 v28, s21, v1
; VI-NEXT: v_add_f16_e32 v21, s6, v1
; VI-NEXT: s_lshr_b32 s6, s23, 16
+; VI-NEXT: v_or_b32_e32 v8, v28, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v21
+; VI-NEXT: v_add_f16_e32 v37, s20, v1
; VI-NEXT: v_add_f16_e32 v14, s6, v1
; VI-NEXT: s_lshr_b32 s6, s22, 16
+; VI-NEXT: v_or_b32_e32 v7, v37, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v14
+; VI-NEXT: v_add_f16_e32 v30, s23, v1
; VI-NEXT: v_add_f16_e32 v22, s6, v1
; VI-NEXT: s_lshr_b32 s6, s25, 16
+; VI-NEXT: v_or_b32_e32 v57, v30, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v22
+; VI-NEXT: v_add_f16_e32 v38, s22, v1
; VI-NEXT: v_add_f16_e32 v15, s6, v1
; VI-NEXT: s_lshr_b32 s6, s24, 16
+; VI-NEXT: v_or_b32_e32 v56, v38, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v15
+; VI-NEXT: v_add_f16_e32 v31, s25, v1
; VI-NEXT: v_add_f16_e32 v23, s6, v1
; VI-NEXT: s_lshr_b32 s6, s27, 16
+; VI-NEXT: v_or_b32_e32 v6, v31, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v23
+; VI-NEXT: v_add_f16_e32 v39, s24, v1
; VI-NEXT: v_add_f16_e32 v16, s6, v1
; VI-NEXT: s_lshr_b32 s6, s26, 16
+; VI-NEXT: v_or_b32_e32 v5, v39, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v16
+; VI-NEXT: v_add_f16_e32 v32, s27, v1
; VI-NEXT: v_add_f16_e32 v24, s6, v1
; VI-NEXT: s_lshr_b32 s6, s29, 16
+; VI-NEXT: v_or_b32_e32 v42, v32, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v24
+; VI-NEXT: v_add_f16_e32 v48, s26, v1
; VI-NEXT: v_add_f16_e32 v17, s6, v1
; VI-NEXT: s_lshr_b32 s6, s28, 16
+; VI-NEXT: v_or_b32_e32 v41, v48, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v17
+; VI-NEXT: v_add_f16_e32 v34, s29, v1
; VI-NEXT: v_add_f16_e32 v26, s6, v1
; VI-NEXT: s_lshr_b32 s6, s5, 16
+; VI-NEXT: v_or_b32_e32 v55, v34, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v26
+; VI-NEXT: v_add_f16_e32 v49, s28, v1
+; VI-NEXT: v_add_f16_e32 v19, s6, v1
; VI-NEXT: v_add_f16_e32 v36, s5, v1
; VI-NEXT: s_lshr_b32 s5, s4, 16
-; VI-NEXT: v_add_f16_e32 v19, s6, v1
+; VI-NEXT: v_or_b32_e32 v54, v49, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v19
; VI-NEXT: v_add_f16_e32 v29, s5, v1
+; VI-NEXT: v_or_b32_e32 v44, v36, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v29
; VI-NEXT: v_add_f16_e32 v50, s4, v1
-; VI-NEXT: v_lshl_or_b32 v44, v19, 16, v36
-; VI-NEXT: v_lshl_or_b32 v43, v29, 16, v50
-; VI-NEXT: v_add_f16_e32 v25, s17, v1
-; VI-NEXT: v_add_f16_e32 v33, s16, v1
-; VI-NEXT: v_add_f16_e32 v27, s19, v1
-; VI-NEXT: v_add_f16_e32 v35, s18, v1
-; VI-NEXT: v_add_f16_e32 v28, s21, v1
-; VI-NEXT: v_add_f16_e32 v37, s20, v1
-; VI-NEXT: v_add_f16_e32 v30, s23, v1
-; VI-NEXT: v_add_f16_e32 v38, s22, v1
-; VI-NEXT: v_add_f16_e32 v31, s25, v1
-; VI-NEXT: v_add_f16_e32 v39, s24, v1
-; VI-NEXT: v_add_f16_e32 v32, s27, v1
-; VI-NEXT: v_add_f16_e32 v48, s26, v1
-; VI-NEXT: v_add_f16_e32 v34, s29, v1
-; VI-NEXT: v_add_f16_e32 v49, s28, v1
+; VI-NEXT: v_or_b32_e32 v43, v50, v2
; VI-NEXT: v_lshrrev_b64 v[1:2], 24, v[43:44]
-; VI-NEXT: v_lshl_or_b32 v55, v17, 16, v34
-; VI-NEXT: v_lshl_or_b32 v54, v26, 16, v49
; VI-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; VI-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[2:3], 24, v[54:55]
-; VI-NEXT: v_lshl_or_b32 v42, v16, 16, v32
-; VI-NEXT: v_lshl_or_b32 v41, v24, 16, v48
; VI-NEXT: v_lshrrev_b32_e32 v3, 8, v43
-; VI-NEXT: v_lshl_or_b32 v6, v15, 16, v31
-; VI-NEXT: v_lshl_or_b32 v5, v23, 16, v39
; VI-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[41:42]
-; VI-NEXT: v_lshl_or_b32 v57, v14, 16, v30
-; VI-NEXT: v_lshl_or_b32 v56, v22, 16, v38
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v44
; VI-NEXT: v_lshrrev_b32_e32 v44, 8, v5
; VI-NEXT: v_lshrrev_b64 v[4:5], 24, v[5:6]
-; VI-NEXT: v_lshl_or_b32 v8, v13, 16, v28
-; VI-NEXT: v_lshl_or_b32 v7, v21, 16, v37
; VI-NEXT: v_lshrrev_b32_e32 v53, 8, v55
; VI-NEXT: v_lshrrev_b32_e32 v55, 8, v42
; VI-NEXT: v_lshrrev_b32_e32 v42, 8, v6
; VI-NEXT: v_lshrrev_b64 v[5:6], 24, v[56:57]
-; VI-NEXT: v_lshl_or_b32 v52, v12, 16, v27
-; VI-NEXT: v_lshl_or_b32 v51, v20, 16, v35
; VI-NEXT: v_lshrrev_b32_e32 v58, 8, v7
; VI-NEXT: v_lshrrev_b64 v[6:7], 24, v[7:8]
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v25
-; VI-NEXT: v_lshl_or_b32 v9, v18, 16, v33
; VI-NEXT: v_lshrrev_b32_e32 v45, 8, v57
; VI-NEXT: v_lshrrev_b32_e32 v57, 8, v8
; VI-NEXT: v_lshrrev_b64 v[7:8], 24, v[51:52]
@@ -78313,71 +79032,85 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v8, v18, v8, s4
; VI-NEXT: v_perm_b32 v1, v33, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v8, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v1, v1, v8
+; VI-NEXT: v_perm_b32 v8, v11, v62, s4
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v25, v51, s4
-; VI-NEXT: v_perm_b32 v8, v11, v62, s4
-; VI-NEXT: v_lshl_or_b32 v1, v8, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v1, v1, v8
; VI-NEXT: v_add_u32_e32 v8, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v8, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v20, v7, s4
; VI-NEXT: v_perm_b32 v7, v35, v61, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v7, v1
; VI-NEXT: v_add_u32_e32 v7, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v27, v60, s4
; VI-NEXT: v_perm_b32 v7, v12, v59, s4
-; VI-NEXT: v_lshl_or_b32 v1, v7, 16, v1
+; VI-NEXT: v_perm_b32 v1, v27, v60, s4
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v1, v1, v7
; VI-NEXT: v_add_u32_e32 v7, vcc, 12, v0
+; VI-NEXT: v_perm_b32 v6, v21, v6, s4
; VI-NEXT: buffer_store_dword v1, v7, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v37, v58, s4
-; VI-NEXT: v_perm_b32 v6, v21, v6, s4
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v1, v1, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v28, v57, s4
; VI-NEXT: v_perm_b32 v6, v13, v56, s4
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
+; VI-NEXT: v_perm_b32 v1, v28, v57, s4
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_or_b32_e32 v1, v1, v6
; VI-NEXT: v_add_u32_e32 v6, vcc, 20, v0
+; VI-NEXT: v_perm_b32 v5, v22, v5, s4
; VI-NEXT: buffer_store_dword v1, v6, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v38, v47, s4
-; VI-NEXT: v_perm_b32 v5, v22, v5, s4
-; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v1, v1, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v30, v45, s4
; VI-NEXT: v_perm_b32 v5, v14, v46, s4
-; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v1
+; VI-NEXT: v_perm_b32 v1, v30, v45, s4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_or_b32_e32 v1, v1, v5
; VI-NEXT: v_add_u32_e32 v5, vcc, 28, v0
+; VI-NEXT: v_perm_b32 v4, v23, v4, s4
; VI-NEXT: buffer_store_dword v1, v5, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v39, v44, s4
-; VI-NEXT: v_perm_b32 v4, v23, v4, s4
-; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v1, v1, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v31, v42, s4
; VI-NEXT: v_perm_b32 v4, v15, v43, s4
-; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; VI-NEXT: v_perm_b32 v1, v31, v42, s4
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v1, v1, v4
; VI-NEXT: v_add_u32_e32 v4, vcc, 36, v0
+; VI-NEXT: v_perm_b32 v3, v24, v3, s4
; VI-NEXT: buffer_store_dword v1, v4, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v48, v40, s4
-; VI-NEXT: v_perm_b32 v3, v24, v3, s4
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v32, v55, s4
; VI-NEXT: v_perm_b32 v3, v16, v41, s4
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, v32, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 44, v0
+; VI-NEXT: v_perm_b32 v2, v26, v2, s4
; VI-NEXT: buffer_store_dword v1, v3, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v49, v54, s4
-; VI-NEXT: v_perm_b32 v2, v26, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v34, v53, s4
; VI-NEXT: v_perm_b32 v2, v17, v10, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v34, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
@@ -78406,12 +79139,14 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_perm_b32 v2, v29, v2, s4
; VI-NEXT: v_perm_b32 v1, v50, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v36, v52, s4
; VI-NEXT: v_perm_b32 v2, v19, v9, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v36, v52, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
@@ -78723,53 +79458,65 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v21, s14
; GFX9-NEXT: .LBB105_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
+; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v19, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
-; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
-; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
+; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
-; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
+; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
-; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
-; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
+; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
-; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v18
-; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -78794,22 +79541,26 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -79052,55 +79803,71 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
; GFX11-NEXT: .LBB105_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
+; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v82, v24, 16, v13
+; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
+; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v81, v86, 16, v18
; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
+; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
+; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v83, v84, 16, v13
-; GFX11-NEXT: v_lshl_or_b32 v13, v22, 16, v9
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
+; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v80, v25, 16, v17
-; GFX11-NEXT: v_lshl_or_b32 v11, v14, 16, v11
+; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v12, v18, 16, v12
+; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v7
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v9
-; GFX11-NEXT: v_lshl_or_b32 v8, v17, 16, v8
-; GFX11-NEXT: v_lshl_or_b32 v9, v18, 16, v5
+; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
+; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
+; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
+; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshl_or_b32 v10, v10, 16, v6
-; GFX11-NEXT: v_lshl_or_b32 v1, v5, 16, v3
-; GFX11-NEXT: v_lshl_or_b32 v2, v17, 16, v4
-; GFX11-NEXT: v_lshl_or_b32 v3, v15, 16, v19
-; GFX11-NEXT: v_lshl_or_b32 v4, v18, 16, v16
+; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
+; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
+; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
+; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
@@ -80007,17 +80774,28 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_perm_b32 v9, v44, v42, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v57, v46, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v11, v58, v47, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v33, v62, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v35, v34, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v49, v48, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v51, v50, s6
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; kill: killed $vgpr18
; VI-NEXT: ; implicit-def: $vgpr18
@@ -80050,14 +80828,16 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -80066,7 +80846,8 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -80074,35 +80855,37 @@ define <32 x half> @bitcast_v64i8_to_v32f16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v17, v4, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v16, v4, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v61, v60, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v59, v56, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v31, v63, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_perm_b32 v14, v39, v38, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
-; VI-NEXT: v_perm_b32 v15, v53, v52, s6
; VI-NEXT: v_perm_b32 v16, v32, v54, s6
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_perm_b32 v15, v53, v52, s6
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr16
; VI-NEXT: ; implicit-def: $vgpr16
@@ -82432,80 +83215,96 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB107_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s45
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s57, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s46
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s47
-; VI-NEXT: v_perm_b32 v4, s56, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s46
; VI-NEXT: v_perm_b32 v5, s59, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s58
+; VI-NEXT: v_perm_b32 v4, s56, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s60
-; VI-NEXT: v_perm_b32 v5, s61, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s58
; VI-NEXT: v_perm_b32 v6, s63, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s62
+; VI-NEXT: v_perm_b32 v5, s61, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s72
-; VI-NEXT: v_perm_b32 v6, s73, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s62
; VI-NEXT: v_perm_b32 v7, s75, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s74
+; VI-NEXT: v_perm_b32 v6, s73, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s42
-; VI-NEXT: v_perm_b32 v7, s76, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s74
; VI-NEXT: v_perm_b32 v8, s43, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s6
+; VI-NEXT: v_perm_b32 v7, s76, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s7
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s6
; VI-NEXT: v_perm_b32 v9, s9, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_perm_b32 v9, s11, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s8
; VI-NEXT: v_perm_b32 v10, s13, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s12
+; VI-NEXT: v_perm_b32 v9, s11, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s14
-; VI-NEXT: v_perm_b32 v10, s15, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s12
; VI-NEXT: v_perm_b32 v12, s40, v12, v11
+; VI-NEXT: v_perm_b32 v10, s15, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s41, v16, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v18, v17, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s41, v16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v25, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v22, v19, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v30, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v27, v21, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v32, v26, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v29, v23, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v34, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v33, v28, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; VI-NEXT: v_or_b32_e32 v15, v35, v15
; VI-NEXT: s_cbranch_execnz .LBB107_3
; VI-NEXT: .LBB107_2: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v34
@@ -83059,14 +83858,16 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB107_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
@@ -83087,52 +83888,53 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v34, 8, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v50, 8, s78
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v48, 8, v14
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v31, 8, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v32, 8, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v35, 8, v16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB107_3
; GFX11-TRUE16-NEXT: .LBB107_2: ; %cmp.true
@@ -83343,23 +84145,23 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
@@ -83370,29 +84172,35 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v34, 8, s79
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v31, 8, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v35, 8, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v38, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v33, 8, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 8, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
@@ -84872,86 +85680,102 @@ define <64 x i8> @bitcast_v32bf16_to_v64i8(<32 x bfloat> %a, i32 %b) #0 {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v21, v30, v23, s4
; VI-NEXT: v_perm_b32 v1, v1, v31, s4
-; VI-NEXT: v_lshl_or_b32 v1, v21, 16, v1
-; VI-NEXT: v_perm_b32 v2, v2, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; VI-NEXT: v_or_b32_e32 v1, v1, v21
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v28, v63, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_perm_b32 v2, v2, v29, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v1, v61, v20, s4
; VI-NEXT: v_perm_b32 v2, v3, v62, s4
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v60, s4
; VI-NEXT: v_perm_b32 v2, v59, v58, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v60, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v57, s4
; VI-NEXT: v_perm_b32 v2, v56, v26, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v57, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v6, v47, s4
; VI-NEXT: v_perm_b32 v2, v46, v45, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v6, v47, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v44, s4
; VI-NEXT: v_perm_b32 v2, v43, v25, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v44, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v42, s4
; VI-NEXT: v_perm_b32 v2, v41, v40, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v42, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v9, v55, s4
; VI-NEXT: v_perm_b32 v2, v54, v22, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v9, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v53, s4
; VI-NEXT: v_perm_b32 v2, v52, v51, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v53, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v11, v50, s4
; VI-NEXT: v_perm_b32 v2, v49, v19, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v11, v50, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v12, v48, s4
; VI-NEXT: v_perm_b32 v2, v39, v38, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v12, v48, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v13, v37, s4
; VI-NEXT: v_perm_b32 v2, v36, v18, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v13, v37, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v14, v35, s4
; VI-NEXT: v_perm_b32 v2, v34, v33, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v14, v35, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v1, v15, v32, s4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v2, v17, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; VI-NEXT: v_perm_b32 v2, v27, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_add_u32_e32 v0, vcc, 60, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v1, v16, v1, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v63, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -87815,78 +88639,93 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: v_mov_b32_e32 v31, s6
; VI-NEXT: .LBB109_5: ; %end
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_perm_b32 v2, v2, v6, s4
; VI-NEXT: v_perm_b32 v3, v3, v31, s4
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_perm_b32 v1, v1, v62, s4
+; VI-NEXT: v_perm_b32 v2, v2, v6, s4
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; VI-NEXT: v_perm_b32 v2, v61, v60, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v1, v62, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v5, v59, s4
; VI-NEXT: v_perm_b32 v2, v58, v30, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v5, v59, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v4, v57, s4
; VI-NEXT: v_perm_b32 v2, v56, v47, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v4, v57, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 12, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v8, v46, s4
; VI-NEXT: v_perm_b32 v2, v45, v29, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v8, v46, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 16, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v7, v44, s4
; VI-NEXT: v_perm_b32 v2, v43, v42, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v7, v44, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 20, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v11, v41, s4
; VI-NEXT: v_perm_b32 v2, v40, v28, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v11, v41, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 24, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v10, v55, s4
; VI-NEXT: v_perm_b32 v2, v54, v53, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v10, v55, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 28, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v14, v52, s4
; VI-NEXT: v_perm_b32 v2, v51, v27, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v14, v52, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 32, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v13, v50, s4
; VI-NEXT: v_perm_b32 v2, v49, v48, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v13, v50, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 36, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v17, v39, s4
; VI-NEXT: v_perm_b32 v2, v38, v26, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v17, v39, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 40, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v16, v37, s4
; VI-NEXT: v_perm_b32 v2, v36, v35, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v16, v37, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 44, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v20, v34, s4
; VI-NEXT: v_perm_b32 v2, v33, v25, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v20, v34, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 48, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v19, v32, s4
; VI-NEXT: v_perm_b32 v2, v21, v18, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v19, v32, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 52, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
-; VI-NEXT: v_perm_b32 v1, v23, v15, s4
; VI-NEXT: v_perm_b32 v2, v12, v24, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_perm_b32 v1, v23, v15, s4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_add_u32_e32 v2, vcc, 56, v0
; VI-NEXT: buffer_store_dword v1, v2, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
@@ -87915,7 +88754,8 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; VI-NEXT: v_readlane_b32 s34, v63, 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s4
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; VI-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -88508,12 +89348,15 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v17, v31, v17, s4
; GFX9-NEXT: v_perm_b32 v3, v30, v3, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v17, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v17
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v16, v37, v16, s4
; GFX9-NEXT: v_perm_b32 v1, v47, v1, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_perm_b32 v2, v44, v2, s4
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX9-NEXT: v_readlane_b32 s30, v63, 14
; GFX9-NEXT: v_readlane_b32 s31, v63, 15
; GFX9-NEXT: v_readlane_b32 s55, v63, 13
@@ -88535,60 +89378,73 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v4, v26, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_perm_b32 v3, v35, v10, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v16, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v16
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v29, v25, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v3, v32, v11, s4
-; GFX9-NEXT: v_perm_b32 v4, v29, v25, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v36, v12, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_perm_b32 v3, v50, v14, s4
-; GFX9-NEXT: v_perm_b32 v4, v36, v12, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v27, v62, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v3, v28, v15, s4
-; GFX9-NEXT: v_perm_b32 v4, v27, v62, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v38, v8, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_perm_b32 v3, v48, v19, s4
-; GFX9-NEXT: v_perm_b32 v4, v38, v8, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v33, v61, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v34, v20, s4
-; GFX9-NEXT: v_perm_b32 v4, v33, v61, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v51, v7, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_perm_b32 v3, v53, v21, s4
-; GFX9-NEXT: v_perm_b32 v4, v51, v7, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v39, v60, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v3, v49, v22, s4
-; GFX9-NEXT: v_perm_b32 v4, v39, v60, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v55, v6, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: v_perm_b32 v3, v41, v23, s4
-; GFX9-NEXT: v_perm_b32 v4, v55, v6, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v52, v59, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v3, v54, v24, s4
-; GFX9-NEXT: v_perm_b32 v4, v52, v59, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v43, v5, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_perm_b32 v3, v45, v58, s4
-; GFX9-NEXT: v_perm_b32 v4, v43, v5, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v40, v18, s4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v42, v57, s4
-; GFX9-NEXT: v_perm_b32 v4, v40, v18, s4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_perm_b32 v3, v56, v13, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v3, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v46, v9, s4
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -89125,57 +89981,64 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v24, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v27, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v16, v2, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v14, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v25, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v3, v22, v3, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v25, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v21, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v26, v5, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v11, v32, v11, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v23, v6, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v3, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v20, v4, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v31, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v5, v12
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v29, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, v20, v4, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v31, v85, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v6, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v36, v10, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v33, v82, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v9, v38, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v28, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v16, v17
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v35, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v30, v80, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v48, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v29, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v28, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v36, v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v35, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v6, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v37, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v16, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v17, v18
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v53, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v5, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v37, v70, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v50, v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v34, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v10, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v55, v68, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v39, v67, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v54, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v53, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v34, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v55, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v49, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v52, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v15, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v5, 16, v8
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v6, 16, v9
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v10, 16, v20
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v21
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v8, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v6
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v20, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v21, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v22
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-TRUE16-NEXT: s_clause 0x3
@@ -89717,55 +90580,62 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v22, v11, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v14, v2, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v19, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v12, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v10, v27, v10, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v19, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v23, v86, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v32, v9, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v18, v4, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v14, v25, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v32, v9, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v11
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v84, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v18, v4, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v30, v83, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v82, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v35, v8, 0xc0c0004
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v12
; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v28, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v82, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v35, v8, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; GFX11-FAKE16-NEXT: v_perm_b32 v16, v34, v71, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v38, v7, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v28, v70, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v37, v69, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v17
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v65, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v52, v5, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v20, v51, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v12
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v8, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v7, 16, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v7
; GFX11-FAKE16-NEXT: v_perm_b32 v7, v31, v67, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v18, v53, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v36, v64, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX11-FAKE16-NEXT: v_perm_b32 v22, v50, v54, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5
; GFX11-FAKE16-NEXT: v_perm_b32 v13, v49, v13, 0xc0c0004
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v8, 16, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v6, 16, v18
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v7, v8
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v18, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v19, v21
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v22, v23
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v20
@@ -90687,17 +91557,28 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
; VI-NEXT: v_perm_b32 v5, v18, v19, s6
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_perm_b32 v6, v22, v23, s6
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_perm_b32 v7, v26, v27, s6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_perm_b32 v8, v30, v55, s6
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_perm_b32 v9, v44, v42, s6
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_perm_b32 v10, v57, v46, s6
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v11, v58, v47, s6
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
; VI-NEXT: v_perm_b32 v12, v33, v62, s6
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: v_perm_b32 v13, v35, v34, s6
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v49, v48, s6
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v51, v50, s6
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: ; implicit-def: $vgpr18
; VI-NEXT: ; kill: killed $vgpr18
; VI-NEXT: ; implicit-def: $vgpr18
@@ -90730,14 +91611,16 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: v_perm_b32 v1, v2, v1, s6
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v2, v3, v2, s6
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -90746,7 +91629,8 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v3, v4, v3, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -90754,35 +91638,37 @@ define <32 x bfloat> @bitcast_v64i8_to_v32bf16(<64 x i8> %a, i32 %b) #0 {
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v17, v4, s6
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
; VI-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; VI-NEXT: ; implicit-def: $vgpr17
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v4, v16, v4, s6
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
; VI-NEXT: v_perm_b32 v5, v20, v21, s6
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
; VI-NEXT: v_perm_b32 v6, v24, v25, s6
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
; VI-NEXT: v_perm_b32 v7, v28, v29, s6
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: v_perm_b32 v8, v41, v40, s6
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
; VI-NEXT: v_perm_b32 v9, v45, v43, s6
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
; VI-NEXT: v_perm_b32 v10, v61, v60, s6
-; VI-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; VI-NEXT: v_or_b32_e32 v10, v10, v11
; VI-NEXT: v_perm_b32 v11, v59, v56, s6
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: v_perm_b32 v12, v31, v63, s6
-; VI-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
; VI-NEXT: v_perm_b32 v13, v37, v36, s6
-; VI-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; VI-NEXT: v_or_b32_e32 v13, v13, v14
; VI-NEXT: v_perm_b32 v14, v39, v38, s6
-; VI-NEXT: v_lshl_or_b32 v14, v15, 16, v14
-; VI-NEXT: v_perm_b32 v15, v53, v52, s6
; VI-NEXT: v_perm_b32 v16, v32, v54, s6
-; VI-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v14, v15
+; VI-NEXT: v_perm_b32 v15, v53, v52, s6
+; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; VI-NEXT: v_or_b32_e32 v15, v15, v16
; VI-NEXT: ; implicit-def: $vgpr16
; VI-NEXT: ; kill: killed $vgpr16
; VI-NEXT: ; implicit-def: $vgpr16
@@ -93021,80 +93907,96 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; VI-NEXT: s_and_b64 s[4:5], vcc, exec
; VI-NEXT: s_cbranch_scc0 .LBB111_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v11
-; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v11
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v2, s25
+; VI-NEXT: v_perm_b32 v0, s16, v0, v11
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_perm_b32 v2, s20, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v3
; VI-NEXT: v_mov_b32_e32 v3, s27
-; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_mov_b32_e32 v2, s25
; VI-NEXT: v_perm_b32 v3, s26, v3, v11
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
-; VI-NEXT: v_mov_b32_e32 v3, s29
+; VI-NEXT: v_perm_b32 v2, s24, v2, v11
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_mov_b32_e32 v4, s45
-; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
+; VI-NEXT: v_mov_b32_e32 v3, s29
; VI-NEXT: v_perm_b32 v4, s57, v4, v11
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_mov_b32_e32 v4, s46
+; VI-NEXT: v_perm_b32 v3, s28, v3, v11
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; VI-NEXT: v_mov_b32_e32 v5, s47
-; VI-NEXT: v_perm_b32 v4, s56, v4, v11
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_mov_b32_e32 v4, s46
; VI-NEXT: v_perm_b32 v5, s59, v5, v11
-; VI-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; VI-NEXT: v_mov_b32_e32 v5, s58
+; VI-NEXT: v_perm_b32 v4, s56, v4, v11
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_mov_b32_e32 v6, s60
-; VI-NEXT: v_perm_b32 v5, s61, v5, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s58
; VI-NEXT: v_perm_b32 v6, s63, v6, v11
-; VI-NEXT: v_lshl_or_b32 v5, v6, 16, v5
-; VI-NEXT: v_mov_b32_e32 v6, s62
+; VI-NEXT: v_perm_b32 v5, s61, v5, v11
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; VI-NEXT: v_mov_b32_e32 v7, s72
-; VI-NEXT: v_perm_b32 v6, s73, v6, v11
+; VI-NEXT: v_or_b32_e32 v5, v5, v6
+; VI-NEXT: v_mov_b32_e32 v6, s62
; VI-NEXT: v_perm_b32 v7, s75, v7, v11
-; VI-NEXT: v_lshl_or_b32 v6, v7, 16, v6
-; VI-NEXT: v_mov_b32_e32 v7, s74
+; VI-NEXT: v_perm_b32 v6, s73, v6, v11
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: v_mov_b32_e32 v8, s42
-; VI-NEXT: v_perm_b32 v7, s76, v7, v11
+; VI-NEXT: v_or_b32_e32 v6, v6, v7
+; VI-NEXT: v_mov_b32_e32 v7, s74
; VI-NEXT: v_perm_b32 v8, s43, v8, v11
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
-; VI-NEXT: v_mov_b32_e32 v8, s6
+; VI-NEXT: v_perm_b32 v7, s76, v7, v11
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; VI-NEXT: v_mov_b32_e32 v9, s7
-; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
+; VI-NEXT: v_mov_b32_e32 v8, s6
; VI-NEXT: v_perm_b32 v9, s9, v9, v11
-; VI-NEXT: v_lshl_or_b32 v8, v9, 16, v8
-; VI-NEXT: v_mov_b32_e32 v9, s8
+; VI-NEXT: v_perm_b32 v8, s44, v8, v11
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
; VI-NEXT: v_mov_b32_e32 v10, s10
-; VI-NEXT: v_perm_b32 v9, s11, v9, v11
+; VI-NEXT: v_or_b32_e32 v8, v8, v9
+; VI-NEXT: v_mov_b32_e32 v9, s8
; VI-NEXT: v_perm_b32 v10, s13, v10, v11
-; VI-NEXT: v_lshl_or_b32 v9, v10, 16, v9
-; VI-NEXT: v_mov_b32_e32 v10, s12
+; VI-NEXT: v_perm_b32 v9, s11, v9, v11
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
; VI-NEXT: v_mov_b32_e32 v12, s14
-; VI-NEXT: v_perm_b32 v10, s15, v10, v11
+; VI-NEXT: v_or_b32_e32 v9, v9, v10
+; VI-NEXT: v_mov_b32_e32 v10, s12
; VI-NEXT: v_perm_b32 v12, s40, v12, v11
+; VI-NEXT: v_perm_b32 v10, s15, v10, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
-; VI-NEXT: v_lshl_or_b32 v10, v12, 16, v10
-; VI-NEXT: v_perm_b32 v11, s41, v16, v11
+; VI-NEXT: v_or_b32_e32 v10, v10, v12
; VI-NEXT: v_perm_b32 v12, v18, v17, s4
-; VI-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; VI-NEXT: v_perm_b32 v11, s41, v16, v11
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_or_b32_e32 v11, v11, v12
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_perm_b32 v12, v25, v20, s4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v13, v22, v19, s4
-; VI-NEXT: v_lshl_or_b32 v12, v12, 16, v13
+; VI-NEXT: v_or_b32_e32 v12, v13, v12
; VI-NEXT: v_perm_b32 v13, v30, v24, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_perm_b32 v14, v27, v21, s4
-; VI-NEXT: v_lshl_or_b32 v13, v13, 16, v14
+; VI-NEXT: v_or_b32_e32 v13, v14, v13
; VI-NEXT: v_perm_b32 v14, v32, v26, s4
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
; VI-NEXT: v_perm_b32 v15, v29, v23, s4
-; VI-NEXT: v_lshl_or_b32 v14, v14, 16, v15
+; VI-NEXT: v_or_b32_e32 v14, v15, v14
; VI-NEXT: v_perm_b32 v15, v34, v31, s4
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; VI-NEXT: v_perm_b32 v35, v33, v28, s4
-; VI-NEXT: v_lshl_or_b32 v15, v15, 16, v35
+; VI-NEXT: v_or_b32_e32 v15, v35, v15
; VI-NEXT: s_cbranch_execnz .LBB111_3
; VI-NEXT: .LBB111_2: ; %cmp.true
; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v34
@@ -93648,14 +94550,16 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB111_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
@@ -93676,52 +94580,53 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v34, 8, v10
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v50, 8, s78
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v48, 8, v14
; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v31, 8, v10
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v32, 8, v14
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v35, 8, v16
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB111_3
; GFX11-TRUE16-NEXT: .LBB111_2: ; %cmp.true
@@ -93932,23 +94837,23 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
@@ -93959,29 +94864,35 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v34, 8, s79
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v31, 8, v11
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v35, 8, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v38, 8, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v33, 8, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 8, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index 9662b0eb88db5..77c047f492cac 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -3043,12 +3043,14 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB26_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v9, v10, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v9, v10, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -3235,34 +3237,37 @@ define i64 @bitcast_v8i8_to_i64(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB26_2
; GFX11-FAKE16-NEXT: .LBB26_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -3349,17 +3354,19 @@ define inreg i64 @bitcast_v8i8_to_i64_scalar(<8 x i8> inreg %a, i32 inreg %b) #0
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB27_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v2, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: s_cbranch_execnz .LBB27_3
; VI-NEXT: .LBB27_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -3395,17 +3402,19 @@ define inreg i64 @bitcast_v8i8_to_i64_scalar(<8 x i8> inreg %a, i32 inreg %b) #0
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -3471,13 +3480,14 @@ define inreg i64 @bitcast_v8i8_to_i64_scalar(<8 x i8> inreg %a, i32 inreg %b) #0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB27_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -6211,12 +6221,14 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB50_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v9, v10, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v9, v10, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -6403,34 +6415,37 @@ define double @bitcast_v8i8_to_f64(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB50_2
; GFX11-FAKE16-NEXT: .LBB50_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -6517,17 +6532,19 @@ define inreg double @bitcast_v8i8_to_f64_scalar(<8 x i8> inreg %a, i32 inreg %b)
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB51_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v2, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: s_cbranch_execnz .LBB51_3
; VI-NEXT: .LBB51_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -6563,17 +6580,19 @@ define inreg double @bitcast_v8i8_to_f64_scalar(<8 x i8> inreg %a, i32 inreg %b)
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -6639,13 +6658,14 @@ define inreg double @bitcast_v8i8_to_f64_scalar(<8 x i8> inreg %a, i32 inreg %b)
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB51_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -9058,12 +9078,14 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB70_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v9, v10, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v9, v10, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -9250,34 +9272,37 @@ define <2 x i32> @bitcast_v8i8_to_v2i32(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB70_2
; GFX11-FAKE16-NEXT: .LBB70_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9364,17 +9389,19 @@ define inreg <2 x i32> @bitcast_v8i8_to_v2i32_scalar(<8 x i8> inreg %a, i32 inre
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB71_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v2, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: s_cbranch_execnz .LBB71_3
; VI-NEXT: .LBB71_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -9410,17 +9437,19 @@ define inreg <2 x i32> @bitcast_v8i8_to_v2i32_scalar(<8 x i8> inreg %a, i32 inre
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9486,13 +9515,14 @@ define inreg <2 x i32> @bitcast_v8i8_to_v2i32_scalar(<8 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB71_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -11614,12 +11644,14 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB86_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v9, v10, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v9, v10, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -11806,34 +11838,37 @@ define <2 x float> @bitcast_v8i8_to_v2f32(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB86_2
; GFX11-FAKE16-NEXT: .LBB86_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -11920,17 +11955,19 @@ define inreg <2 x float> @bitcast_v8i8_to_v2f32_scalar(<8 x i8> inreg %a, i32 in
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB87_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v2, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: s_cbranch_execnz .LBB87_3
; VI-NEXT: .LBB87_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -11966,17 +12003,19 @@ define inreg <2 x float> @bitcast_v8i8_to_v2f32_scalar(<8 x i8> inreg %a, i32 in
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -12042,13 +12081,14 @@ define inreg <2 x float> @bitcast_v8i8_to_v2f32_scalar(<8 x i8> inreg %a, i32 in
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB87_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -13406,12 +13446,14 @@ define <8 x i8> @bitcast_v4i16_to_v8i8(<4 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB96_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v2, 3
-; VI-NEXT: v_add_u16_e32 v8, 3, v1
; VI-NEXT: v_add_u16_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v9, 3, v0
; VI-NEXT: v_add_u16_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v8
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v9
+; VI-NEXT: v_add_u16_e32 v8, 3, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; VI-NEXT: v_add_u16_e32 v9, 3, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v8, v1
+; VI-NEXT: v_or_b32_e32 v0, v9, v0
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v4, 8, v0
@@ -13864,12 +13906,14 @@ define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB98_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v9, v10, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v9, v10, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -14056,34 +14100,37 @@ define <4 x i16> @bitcast_v8i8_to_v4i16(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB98_2
; GFX11-FAKE16-NEXT: .LBB98_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -14183,17 +14230,19 @@ define inreg <4 x i16> @bitcast_v8i8_to_v4i16_scalar(<8 x i8> inreg %a, i32 inre
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB99_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v2, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: s_cbranch_execnz .LBB99_3
; VI-NEXT: .LBB99_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -14229,17 +14278,19 @@ define inreg <4 x i16> @bitcast_v8i8_to_v4i16_scalar(<8 x i8> inreg %a, i32 inre
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB99_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: s_cbranch_execnz .LBB99_3
; GFX9-NEXT: .LBB99_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -14305,13 +14356,14 @@ define inreg <4 x i16> @bitcast_v8i8_to_v4i16_scalar(<8 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB99_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -15253,11 +15305,13 @@ define <8 x i8> @bitcast_v4f16_to_v8i8(<4 x half> %a, i32 %b) #0 {
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v0, 0x200
; VI-NEXT: v_add_f16_sdwa v6, v9, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
; VI-NEXT: v_add_f16_sdwa v2, v8, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; VI-NEXT: v_add_f16_e32 v9, 0x200, v9
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v9
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v8
+; VI-NEXT: v_or_b32_e32 v1, v9, v1
+; VI-NEXT: v_or_b32_e32 v0, v8, v0
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
@@ -15485,11 +15539,13 @@ define inreg <8 x i8> @bitcast_v4f16_to_v8i8_scalar(<4 x half> inreg %a, i32 inr
; VI-NEXT: v_mov_b32_e32 v0, 0x200
; VI-NEXT: v_add_f16_e32 v6, s4, v0
; VI-NEXT: s_lshr_b32 s4, s16, 16
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
; VI-NEXT: v_add_f16_e32 v8, s17, v0
; VI-NEXT: v_add_f16_e32 v2, s4, v0
+; VI-NEXT: v_or_b32_e32 v10, v8, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; VI-NEXT: v_add_f16_e32 v0, s16, v0
-; VI-NEXT: v_lshl_or_b32 v10, v6, 16, v8
-; VI-NEXT: v_lshl_or_b32 v9, v2, 16, v0
+; VI-NEXT: v_or_b32_e32 v9, v0, v1
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[9:10]
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v10
; VI-NEXT: v_lshrrev_b32_e32 v1, 8, v9
@@ -15719,12 +15775,14 @@ define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB106_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v9, v10, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v9, v10, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -15911,34 +15969,37 @@ define <4 x half> @bitcast_v8i8_to_v4f16(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB106_2
; GFX11-FAKE16-NEXT: .LBB106_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -16038,17 +16099,19 @@ define inreg <4 x half> @bitcast_v8i8_to_v4f16_scalar(<8 x i8> inreg %a, i32 inr
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB107_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v2, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: s_cbranch_execnz .LBB107_3
; VI-NEXT: .LBB107_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -16084,17 +16147,19 @@ define inreg <4 x half> @bitcast_v8i8_to_v4f16_scalar(<8 x i8> inreg %a, i32 inr
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB107_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: s_cbranch_execnz .LBB107_3
; GFX9-NEXT: .LBB107_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -16160,13 +16225,14 @@ define inreg <4 x half> @bitcast_v8i8_to_v4f16_scalar(<8 x i8> inreg %a, i32 inr
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB107_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -17070,12 +17136,14 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB110_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v9, v10, s6
; VI-NEXT: v_perm_b32 v1, v2, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v9, v10, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: ; implicit-def: $vgpr9
; VI-NEXT: ; implicit-def: $vgpr10
; VI-NEXT: ; implicit-def: $vgpr2
@@ -17262,34 +17330,37 @@ define <4 x bfloat> @bitcast_v8i8_to_v4bf16(<8 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB110_2
; GFX11-FAKE16-NEXT: .LBB110_4: ; %cmp.true
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v9, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, v2, 3
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v2, 8, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v7, v6
; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -17387,17 +17458,19 @@ define inreg <4 x bfloat> @bitcast_v8i8_to_v4bf16_scalar(<8 x i8> inreg %a, i32
; VI-NEXT: s_cmp_lg_u32 s24, 0
; VI-NEXT: s_cbranch_scc0 .LBB111_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v2, s18, v2, v1
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_perm_b32 v0, s16, v0, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: v_mov_b32_e32 v2, s21
; VI-NEXT: v_mov_b32_e32 v3, s23
; VI-NEXT: v_perm_b32 v2, s20, v2, v1
; VI-NEXT: v_perm_b32 v1, s22, v3, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: s_cbranch_execnz .LBB111_3
; VI-NEXT: .LBB111_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -17433,17 +17506,19 @@ define inreg <4 x bfloat> @bitcast_v8i8_to_v4bf16_scalar(<8 x i8> inreg %a, i32
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB111_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: s_cbranch_execnz .LBB111_3
; GFX9-NEXT: .LBB111_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -17509,13 +17584,14 @@ define inreg <4 x bfloat> @bitcast_v8i8_to_v4bf16_scalar(<8 x i8> inreg %a, i32
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: .LBB111_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index 353df14c2f25d..a1c0db086bf3c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -975,15 +975,18 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB6_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v14, v13, s6
; VI-NEXT: v_perm_b32 v1, v15, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v14, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
@@ -1226,39 +1229,42 @@ define <3 x i32> @bitcast_v12i8_to_v3i32(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v15, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -1368,22 +1374,25 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: s_cmp_lg_u32 s28, 0
; VI-NEXT: s_cbranch_scc0 .LBB7_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v2
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_mov_b32_e32 v3, s25
; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v3, s24, v3, v2
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
-; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: s_cbranch_execnz .LBB7_3
; VI-NEXT: .LBB7_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -1429,22 +1438,25 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB7_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
; GFX9-NEXT: s_cbranch_execnz .LBB7_3
; GFX9-NEXT: .LBB7_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -1522,18 +1534,20 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
; GFX11-NEXT: v_perm_b32 v0, s22, s23, v0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB7_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -4124,15 +4138,18 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB22_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v14, v13, s6
; VI-NEXT: v_perm_b32 v1, v15, v3, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v14, v13, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
; VI-NEXT: ; implicit-def: $vgpr15
@@ -4375,39 +4392,42 @@ define <3 x float> @bitcast_v12i8_to_v3f32(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v13
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v15, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -4517,22 +4537,25 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; VI-NEXT: s_cmp_lg_u32 s28, 0
; VI-NEXT: s_cbranch_scc0 .LBB23_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v2
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_mov_b32_e32 v3, s25
; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v3, s24, v3, v2
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
-; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: s_cbranch_execnz .LBB23_3
; VI-NEXT: .LBB23_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -4578,22 +4601,25 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB23_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
; GFX9-NEXT: s_cbranch_execnz .LBB23_3
; GFX9-NEXT: .LBB23_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -4671,18 +4697,20 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
; GFX11-NEXT: v_perm_b32 v0, s22, s23, v0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB23_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -6795,15 +6823,18 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB36_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v15, v14, s6
; VI-NEXT: v_perm_b32 v1, v13, v16, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v15, v14, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
@@ -7048,39 +7079,42 @@ define <6 x bfloat> @bitcast_v12i8_to_v6bf16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -7207,22 +7241,25 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; VI-NEXT: s_cmp_lg_u32 s28, 0
; VI-NEXT: s_cbranch_scc0 .LBB37_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v2
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_mov_b32_e32 v3, s25
; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v3, s24, v3, v2
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
-; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: s_cbranch_execnz .LBB37_3
; VI-NEXT: .LBB37_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -7268,22 +7305,25 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB37_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
; GFX9-NEXT: s_cbranch_execnz .LBB37_3
; GFX9-NEXT: .LBB37_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -7361,18 +7401,20 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
; GFX11-NEXT: v_perm_b32 v0, s22, s23, v0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB37_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -8605,15 +8647,18 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB40_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v15, v14, s6
; VI-NEXT: v_perm_b32 v1, v13, v16, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v15, v14, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
@@ -8858,39 +8903,42 @@ define <6 x half> @bitcast_v12i8_to_v6f16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -9020,22 +9068,25 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; VI-NEXT: s_cmp_lg_u32 s28, 0
; VI-NEXT: s_cbranch_scc0 .LBB41_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v2
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_mov_b32_e32 v3, s25
; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v3, s24, v3, v2
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
-; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: s_cbranch_execnz .LBB41_3
; VI-NEXT: .LBB41_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -9081,22 +9132,25 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB41_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
; GFX9-NEXT: s_cbranch_execnz .LBB41_3
; GFX9-NEXT: .LBB41_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9174,18 +9228,20 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
; GFX11-NEXT: v_perm_b32 v0, s22, s23, v0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB41_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -9328,14 +9384,17 @@ define <12 x i8> @bitcast_v6f16_to_v12i8(<6 x half> %a, i32 %b) #0 {
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v3, 0x200
; VI-NEXT: v_add_f16_sdwa v6, v14, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
; VI-NEXT: v_add_f16_e32 v14, 0x200, v14
; VI-NEXT: v_add_f16_sdwa v2, v13, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
; VI-NEXT: v_add_f16_sdwa v10, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_or_b32_e32 v1, v14, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v2
+; VI-NEXT: v_add_f16_e32 v13, 0x200, v13
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; VI-NEXT: v_add_f16_e32 v8, 0x200, v8
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v14
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v13
-; VI-NEXT: v_lshl_or_b32 v11, v10, 16, v8
+; VI-NEXT: v_or_b32_e32 v0, v13, v0
+; VI-NEXT: v_or_b32_e32 v11, v8, v3
; VI-NEXT: v_mov_b32_e32 v12, 0x7e007e00
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v11
@@ -9634,15 +9693,18 @@ define inreg <12 x i8> @bitcast_v6f16_to_v12i8_scalar(<6 x half> inreg %a, i32 i
; VI-NEXT: v_mov_b32_e32 v1, 0x200
; VI-NEXT: v_add_f16_e32 v6, s4, v1
; VI-NEXT: s_lshr_b32 s4, s16, 16
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v6
+; VI-NEXT: v_add_f16_e32 v13, s17, v1
; VI-NEXT: v_add_f16_e32 v2, s4, v1
; VI-NEXT: s_lshr_b32 s4, s18, 16
-; VI-NEXT: v_add_f16_e32 v13, s17, v1
+; VI-NEXT: v_or_b32_e32 v12, v13, v0
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; VI-NEXT: v_add_f16_e32 v0, s16, v1
; VI-NEXT: v_add_f16_e32 v10, s4, v1
+; VI-NEXT: v_or_b32_e32 v11, v0, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v10
; VI-NEXT: v_add_f16_e32 v8, s18, v1
-; VI-NEXT: v_lshl_or_b32 v12, v6, 16, v13
-; VI-NEXT: v_lshl_or_b32 v11, v2, 16, v0
-; VI-NEXT: v_lshl_or_b32 v14, v10, 16, v8
+; VI-NEXT: v_or_b32_e32 v14, v8, v3
; VI-NEXT: v_mov_b32_e32 v15, 0x7e007e00
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[11:12]
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v12
@@ -9948,15 +10010,18 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; VI-NEXT: s_setpc_b64 s[30:31]
; VI-NEXT: .LBB44_3: ; %cmp.false
; VI-NEXT: s_mov_b32 s6, 0xc0c0004
-; VI-NEXT: v_perm_b32 v0, v15, v14, s6
; VI-NEXT: v_perm_b32 v1, v13, v16, s6
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_perm_b32 v0, v15, v14, s6
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_perm_b32 v2, v6, v7, s6
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_perm_b32 v1, v4, v5, s6
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_perm_b32 v3, v10, v11, s6
-; VI-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_perm_b32 v2, v8, v9, s6
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: ; implicit-def: $vgpr15
; VI-NEXT: ; implicit-def: $vgpr14
; VI-NEXT: ; implicit-def: $vgpr13
@@ -10201,39 +10266,42 @@ define <6 x i16> @bitcast_v12i8_to_v6i16(<12 x i8> %a, i32 %b) #0 {
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v14
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, v13, 3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, v4, 3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v8, v8, 3
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v16
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v6, v6, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v9
; GFX11-FAKE16-NEXT: v_add_nc_u16 v9, v10, 3
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v7, 8, v7
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v10, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xff, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v7, v6
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v10, v9
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, 0x300, v0
; GFX11-FAKE16-NEXT: v_add_nc_u16 v2, 0x300, v2
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v3, 0x300, v3
; GFX11-FAKE16-NEXT: v_add_nc_u16 v4, 0x300, v4
+; GFX11-FAKE16-NEXT: v_add_nc_u16 v1, 0x300, v1
; GFX11-FAKE16-NEXT: v_add_nc_u16 v5, 0x300, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v4, 16, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v6
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v6, v5
; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
%cmp = icmp eq i32 %b, 0
@@ -10363,22 +10431,25 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; VI-NEXT: s_cmp_lg_u32 s28, 0
; VI-NEXT: s_cbranch_scc0 .LBB45_4
; VI-NEXT: ; %bb.1: ; %cmp.false
-; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; VI-NEXT: v_mov_b32_e32 v1, s19
-; VI-NEXT: v_perm_b32 v0, s16, v0, v2
+; VI-NEXT: v_mov_b32_e32 v0, s17
; VI-NEXT: v_perm_b32 v1, s18, v1, v2
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; VI-NEXT: v_mov_b32_e32 v1, s21
+; VI-NEXT: v_perm_b32 v0, s16, v0, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_mov_b32_e32 v3, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v3, s22, v3, v2
-; VI-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-NEXT: v_perm_b32 v1, s20, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v3
; VI-NEXT: v_mov_b32_e32 v3, s25
; VI-NEXT: v_mov_b32_e32 v4, s27
; VI-NEXT: v_perm_b32 v3, s24, v3, v2
; VI-NEXT: v_perm_b32 v2, s26, v4, v2
-; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: s_cbranch_execnz .LBB45_3
; VI-NEXT: .LBB45_2: ; %cmp.true
; VI-NEXT: s_add_i32 s16, s16, 3
@@ -10424,22 +10495,25 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB45_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX9-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_mov_b32_e32 v1, s21
; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
; GFX9-NEXT: s_cbranch_execnz .LBB45_3
; GFX9-NEXT: .LBB45_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -10517,18 +10591,20 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
; GFX11-NEXT: v_perm_b32 v0, s22, s23, v0
; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x300, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0x300, v2
+; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
+; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
; GFX11-NEXT: v_add_nc_u32_e32 v5, 0x300, v5
; GFX11-NEXT: v_add_nc_u32_e32 v0, 0x300, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x300, v4
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_or_b32_e32 v1, v3, v4
; GFX11-NEXT: v_or_b32_e32 v2, v5, v6
; GFX11-NEXT: .LBB45_3: ; %end
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -10669,16 +10745,19 @@ define <12 x i8> @bitcast_v6i16_to_v12i8(<6 x i16> %a, i32 %b) #0 {
; VI-NEXT: s_cbranch_execz .LBB46_4
; VI-NEXT: ; %bb.3: ; %cmp.true
; VI-NEXT: v_mov_b32_e32 v3, 3
-; VI-NEXT: v_add_u16_e32 v14, 3, v1
; VI-NEXT: v_add_u16_sdwa v6, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_add_u16_e32 v16, 3, v0
; VI-NEXT: v_add_u16_sdwa v13, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v14
-; VI-NEXT: v_lshl_or_b32 v0, v13, 16, v16
-; VI-NEXT: v_add_u16_e32 v8, 3, v2
+; VI-NEXT: v_add_u16_e32 v14, 3, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v6
+; VI-NEXT: v_add_u16_e32 v16, 3, v0
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v13
+; VI-NEXT: v_or_b32_e32 v1, v14, v1
+; VI-NEXT: v_or_b32_e32 v0, v16, v0
; VI-NEXT: v_add_u16_sdwa v10, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; VI-NEXT: v_add_u16_e32 v8, 3, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v10
; VI-NEXT: v_lshrrev_b64 v[3:4], 24, v[0:1]
-; VI-NEXT: v_lshl_or_b32 v2, v10, 16, v8
+; VI-NEXT: v_or_b32_e32 v2, v8, v2
; VI-NEXT: v_lshrrev_b64 v[11:12], 24, v[2:3]
; VI-NEXT: v_lshrrev_b32_e32 v9, 8, v2
; VI-NEXT: v_lshrrev_b32_e32 v5, 8, v1
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index cda20e5a04c9c..b883f82c0ca27 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -4695,11 +4695,12 @@ define amdgpu_kernel void @udiv_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v0
; GFX9-NEXT: v_mad_f32 v0, -v0, v1, v6
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1
-; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
+; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v5, vcc
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
-; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 15, v3
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
@@ -4884,20 +4885,21 @@ define amdgpu_kernel void @urem_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v4
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mad_f32 v4, -v4, v3, v6
-; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3
; GFX9-NEXT: s_lshr_b32 s4, s6, 15
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s4
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v3, s3
; GFX9-NEXT: s_lshr_b32 s3, s2, 15
; GFX9-NEXT: v_sub_u32_e32 v4, s2, v0
; GFX9-NEXT: v_sub_u32_e32 v5, s3, v1
; GFX9-NEXT: v_sub_u32_e32 v0, s8, v3
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v4
; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v5
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 15, v3
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
@@ -5112,10 +5114,11 @@ define amdgpu_kernel void @sdiv_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
; GFX9-NEXT: s_cselect_b32 s2, s4, 0
; GFX9-NEXT: v_add_u32_e32 v0, s2, v5
+; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
-; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 15, v3
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
@@ -5356,10 +5359,11 @@ define amdgpu_kernel void @srem_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: v_sub_u32_e32 v5, s3, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: v_sub_u32_e32 v0, s9, v2
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v2, 0x7fff, v4
; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v5
-; GFX9-NEXT: v_lshl_or_b32 v2, v4, 15, v2
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
; GFX9-NEXT: global_store_dword v3, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index 695e48407d4bb..aed1e4fe685f5 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -11904,9 +11904,10 @@ define amdgpu_kernel void @uniform_fadd_f16(ptr addrspace(1) %result, ptr addrsp
; GFX8-NEXT: .LBB18_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: v_lshrrev_b32_e32 v0, s10, v1
-; GFX8-NEXT: v_and_b32_e32 v2, s2, v1
; GFX8-NEXT: v_add_f16_e32 v0, s11, v0
-; GFX8-NEXT: v_lshl_or_b32 v0, v0, s10, v2
+; GFX8-NEXT: v_and_b32_e32 v2, s2, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, s10, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: v_mov_b32_e32 v2, v0
; GFX8-NEXT: buffer_atomic_cmpswap v[2:3], off, s[4:7], 0 glc
diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
index 34c465875eb83..ca7e358fc0314 100644
--- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
+++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll
@@ -379,8 +379,9 @@ define amdgpu_kernel void @call_with_private_to_flat_addrspacecast_cc_kernel(ptr
; GFX8-NEXT: s_add_u32 s16, s16, with_private_to_flat_addrspacecast at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_or_b32_e32 v31, v0, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s15
@@ -399,8 +400,9 @@ define amdgpu_kernel void @call_with_private_to_flat_addrspacecast_cc_kernel(ptr
; GFX8-ARCH-FLAT-NEXT: s_add_u32 s4, s4, with_private_to_flat_addrspacecast at gotpcrel32@lo+4
; GFX8-ARCH-FLAT-NEXT: s_addc_u32 s5, s5, with_private_to_flat_addrspacecast at gotpcrel32@hi+12
; GFX8-ARCH-FLAT-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX8-ARCH-FLAT-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX8-ARCH-FLAT-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX8-ARCH-FLAT-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GFX8-ARCH-FLAT-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-ARCH-FLAT-NEXT: s_mov_b32 s14, s10
; GFX8-ARCH-FLAT-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX8-ARCH-FLAT-NEXT: v_or_b32_e32 v31, v0, v2
@@ -742,8 +744,9 @@ define amdgpu_kernel void @call_calls_intrin_ascast_cc_kernel(ptr addrspace(3) %
; GFX8-NEXT: s_add_u32 s16, s16, calls_intrin_ascast at gotpcrel32@lo+4
; GFX8-NEXT: s_addc_u32 s17, s17, calls_intrin_ascast at gotpcrel32@hi+12
; GFX8-NEXT: s_load_dwordx2 s[16:17], s[16:17], 0x0
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_or_b32_e32 v31, v0, v2
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s15
@@ -762,8 +765,9 @@ define amdgpu_kernel void @call_calls_intrin_ascast_cc_kernel(ptr addrspace(3) %
; GFX8-ARCH-FLAT-NEXT: s_add_u32 s4, s4, calls_intrin_ascast at gotpcrel32@lo+4
; GFX8-ARCH-FLAT-NEXT: s_addc_u32 s5, s5, calls_intrin_ascast at gotpcrel32@hi+12
; GFX8-ARCH-FLAT-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
+; GFX8-ARCH-FLAT-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX8-ARCH-FLAT-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX8-ARCH-FLAT-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GFX8-ARCH-FLAT-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-ARCH-FLAT-NEXT: s_mov_b32 s14, s10
; GFX8-ARCH-FLAT-NEXT: s_mov_b64 s[10:11], s[6:7]
; GFX8-ARCH-FLAT-NEXT: v_or_b32_e32 v31, v0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
index 156ca17782c35..b5844049fd287 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fadd.ll
@@ -3660,9 +3660,10 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__amdgpu_no_fine_gr
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, s6, v2
-; GFX8-NEXT: v_and_b32_e32 v3, s7, v2
; GFX8-NEXT: v_add_f16_e32 v1, v1, v0
-; GFX8-NEXT: v_lshl_or_b32 v1, v1, s6, v3
+; GFX8-NEXT: v_and_b32_e32 v3, s7, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
; GFX8-NEXT: v_mov_b32_e32 v4, v2
; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: buffer_atomic_cmpswap v[3:4], v5, s[16:19], 0 offen glc
@@ -4085,9 +4086,10 @@ define void @buffer_fat_ptr_agent_atomic_fadd_noret_f16__offset__amdgpu_no_fine_
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, s6, v2
-; GFX8-NEXT: v_and_b32_e32 v4, s7, v2
; GFX8-NEXT: v_add_f16_e32 v1, v1, v0
-; GFX8-NEXT: v_lshl_or_b32 v1, v1, s6, v4
+; GFX8-NEXT: v_and_b32_e32 v4, s7, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, s6, v1
+; GFX8-NEXT: v_or_b32_e32 v1, v4, v1
; GFX8-NEXT: v_mov_b32_e32 v5, v2
; GFX8-NEXT: v_mov_b32_e32 v4, v1
; GFX8-NEXT: buffer_atomic_cmpswap v[4:5], v3, s[16:19], 0 offen glc
@@ -4800,8 +4802,9 @@ define half @buffer_fat_ptr_agent_atomic_fadd_ret_f16__offset__waterfall__amdgpu
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v6, v4, v7
; GFX8-NEXT: v_add_f16_e32 v6, v6, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, v4, v6
; GFX8-NEXT: v_and_b32_e32 v8, v7, v11
-; GFX8-NEXT: v_lshl_or_b32 v6, v6, v4, v8
+; GFX8-NEXT: v_or_b32_e32 v6, v8, v6
; GFX8-NEXT: v_mov_b32_e32 v9, v7
; GFX8-NEXT: s_mov_b64 s[12:13], exec
; GFX8-NEXT: v_mov_b32_e32 v8, v6
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
index 21f719d0b2997..3d85bf7019426 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmax.ll
@@ -2758,9 +2758,10 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__amdgpu_no_fine_gr
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v0, s6, v1
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX8-NEXT: v_and_b32_e32 v2, s7, v1
; GFX8-NEXT: v_max_f16_e32 v0, v0, v5
-; GFX8-NEXT: v_lshl_or_b32 v0, v0, s6, v2
+; GFX8-NEXT: v_and_b32_e32 v2, s7, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: v_mov_b32_e32 v2, v0
; GFX8-NEXT: buffer_atomic_cmpswap v[2:3], v4, s[16:19], 0 offen glc
@@ -3204,9 +3205,10 @@ define void @buffer_fat_ptr_agent_atomic_fmax_noret_f16__offset__amdgpu_no_fine_
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v0, s6, v1
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX8-NEXT: v_and_b32_e32 v4, s7, v1
; GFX8-NEXT: v_max_f16_e32 v0, v0, v3
-; GFX8-NEXT: v_lshl_or_b32 v0, v0, s6, v4
+; GFX8-NEXT: v_and_b32_e32 v4, s7, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v4, v0
; GFX8-NEXT: v_mov_b32_e32 v5, v1
; GFX8-NEXT: v_mov_b32_e32 v4, v0
; GFX8-NEXT: buffer_atomic_cmpswap v[4:5], v2, s[16:19], 0 offen glc
@@ -3941,8 +3943,9 @@ define half @buffer_fat_ptr_agent_atomic_fmax_ret_f16__offset__waterfall__amdgpu
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v7, v6
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
; GFX8-NEXT: v_max_f16_e32 v4, v4, v10
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX8-NEXT: v_and_b32_e32 v5, v6, v9
-; GFX8-NEXT: v_lshl_or_b32 v5, v4, v7, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v4
; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: s_mov_b64 s[12:13], exec
; GFX8-NEXT: v_mov_b32_e32 v5, v6
diff --git a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
index 3dda7c7272276..3f15d35320573 100644
--- a/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/buffer-fat-pointer-atomicrmw-fmin.ll
@@ -2758,9 +2758,10 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__amdgpu_no_fine_gr
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v0, s6, v1
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX8-NEXT: v_and_b32_e32 v2, s7, v1
; GFX8-NEXT: v_min_f16_e32 v0, v0, v5
-; GFX8-NEXT: v_lshl_or_b32 v0, v0, s6, v2
+; GFX8-NEXT: v_and_b32_e32 v2, s7, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-NEXT: v_mov_b32_e32 v3, v1
; GFX8-NEXT: v_mov_b32_e32 v2, v0
; GFX8-NEXT: buffer_atomic_cmpswap v[2:3], v4, s[16:19], 0 offen glc
@@ -3204,9 +3205,10 @@ define void @buffer_fat_ptr_agent_atomic_fmin_noret_f16__offset__amdgpu_no_fine_
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v0, s6, v1
; GFX8-NEXT: v_max_f16_e32 v0, v0, v0
-; GFX8-NEXT: v_and_b32_e32 v4, s7, v1
; GFX8-NEXT: v_min_f16_e32 v0, v0, v3
-; GFX8-NEXT: v_lshl_or_b32 v0, v0, s6, v4
+; GFX8-NEXT: v_and_b32_e32 v4, s7, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, s6, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v4, v0
; GFX8-NEXT: v_mov_b32_e32 v5, v1
; GFX8-NEXT: v_mov_b32_e32 v4, v0
; GFX8-NEXT: buffer_atomic_cmpswap v[4:5], v2, s[16:19], 0 offen glc
@@ -3941,8 +3943,9 @@ define half @buffer_fat_ptr_agent_atomic_fmin_ret_f16__offset__waterfall__amdgpu
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v7, v6
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
; GFX8-NEXT: v_min_f16_e32 v4, v4, v10
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, v7, v4
; GFX8-NEXT: v_and_b32_e32 v5, v6, v9
-; GFX8-NEXT: v_lshl_or_b32 v5, v4, v7, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v5, v4
; GFX8-NEXT: v_mov_b32_e32 v4, v5
; GFX8-NEXT: s_mov_b64 s[12:13], exec
; GFX8-NEXT: v_mov_b32_e32 v5, v6
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index ccf84c5cd5a27..77ee1ada2af94 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -244,10 +244,11 @@ define amdgpu_kernel void @call_coldcc() #0 {
; VI-NEXT: s_add_u32 s4, s4, coldcc at gotpcrel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, coldcc at gotpcrel32@hi+12
; VI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b64 s[10:11], s[6:7]
; VI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; VI-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_mov_b64 s[4:5], s[0:1]
; VI-NEXT: s_mov_b64 s[6:7], s[2:3]
; VI-NEXT: s_mov_b64 s[0:1], s[88:89]
@@ -355,10 +356,11 @@ define amdgpu_kernel void @call_fastcc() #0 {
; VI-NEXT: s_add_u32 s4, s4, fastcc at gotpcrel32@lo+4
; VI-NEXT: s_addc_u32 s5, s5, fastcc at gotpcrel32@hi+12
; VI-NEXT: s_load_dwordx2 s[16:17], s[4:5], 0x0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; VI-NEXT: s_mov_b32 s14, s10
; VI-NEXT: s_mov_b64 s[10:11], s[6:7]
; VI-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; VI-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_mov_b64 s[4:5], s[0:1]
; VI-NEXT: s_mov_b64 s[6:7], s[2:3]
; VI-NEXT: s_mov_b64 s[0:1], s[88:89]
@@ -3803,18 +3805,18 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 3, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v12, v13
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 3, v14
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 4, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v11, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 3, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v7, v2
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v10
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 4, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 15, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v6, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 15, v2
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v6, 4, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 15, v8
+; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v4, 12, v5
@@ -3828,9 +3830,11 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: global_store_b32 v[0:1], v0, off
; GFX11-FAKE16-NEXT: s_endpgm
;
@@ -3969,13 +3973,13 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
; GFX1250-FAKE16-NEXT: v_or_b32_e32 v9, v13, v9
; GFX1250-FAKE16-NEXT: v_or_b32_e32 v11, v14, v11
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v12, v28, v15, 1 bitop3:0xec
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 4, v3
-; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v4
; GFX1250-FAKE16-NEXT: v_or_b32_e32 v2, v2, v6
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v6, v16, v8, 1 bitop3:0xec
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v5, v7, v5, 3 bitop3:0xec
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v7, v10, 15, v9 bitop3:0xc8
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v8, v12, v11, 3 bitop3:0xec
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v3, 4, v3
+; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v4, 8, v4
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v1, 12, v1
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v2, v6, v2, 3 bitop3:0xec
; GFX1250-FAKE16-NEXT: v_lshlrev_b16 v5, 4, v5
@@ -3990,8 +3994,9 @@ define amdgpu_cs void @amdgpu_cs_v32i1(<32 x i1> %arg0) {
; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1250-FAKE16-NEXT: v_bitop3_b16 v1, v2, v3, 0xff bitop3:0xec
; GFX1250-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX1250-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX1250-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX1250-FAKE16-NEXT: global_store_b32 v[0:1], v0, off
; GFX1250-FAKE16-NEXT: s_endpgm
store <32 x i1> %arg0, ptr addrspace(1) poison
diff --git a/llvm/test/CodeGen/AMDGPU/cc-update.ll b/llvm/test/CodeGen/AMDGPU/cc-update.ll
index cd41775e036ad..ee1feccc6334c 100644
--- a/llvm/test/CodeGen/AMDGPU/cc-update.ll
+++ b/llvm/test/CodeGen/AMDGPU/cc-update.ll
@@ -70,9 +70,10 @@ define amdgpu_kernel void @test_kern_call() local_unnamed_addr #0 {
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s17
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_mov_b32 s13, s15
; GFX803-NEXT: s_mov_b32 s12, s14
@@ -153,9 +154,10 @@ define amdgpu_kernel void @test_kern_stack_and_call() local_unnamed_addr #0 {
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s17
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_mov_b32 s13, s15
; GFX803-NEXT: s_mov_b32 s12, s14
@@ -319,9 +321,10 @@ define amdgpu_kernel void @test_force_fp_kern_call() local_unnamed_addr #2 {
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s17
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_mov_b32 s13, s15
; GFX803-NEXT: s_mov_b32 s12, s14
@@ -424,9 +427,10 @@ define amdgpu_kernel void @test_force_fp_kern_stack_and_call() local_unnamed_add
; GFX803-NEXT: s_add_i32 s12, s12, s17
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8
; GFX803-NEXT: s_add_u32 s0, s0, s17
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_mov_b32 s33, 0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s13
; GFX803-NEXT: s_mov_b32 s13, s15
diff --git a/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll b/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
index cb2e86c9c6b01..7a576b1c58c55 100644
--- a/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
+++ b/llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll
@@ -297,17 +297,18 @@ define amdgpu_kernel void @test_copy_v4i8_extra_use(ptr addrspace(1) %out0, ptr
; VI-NEXT: s_mov_b32 s9, s3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; VI-NEXT: v_add_u16_e32 v3, 9, v0
; VI-NEXT: v_and_b32_e32 v4, 0xffffff00, v1
; VI-NEXT: v_add_u16_e32 v1, 9, v1
+; VI-NEXT: v_add_u16_e32 v3, 9, v0
+; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
; VI-NEXT: v_and_b32_e32 v2, 0xffffff00, v0
; VI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_or_b32_e32 v1, v4, v1
-; VI-NEXT: v_add_u16_e32 v2, 0x900, v2
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v1, 0x900, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_add_u16_e32 v2, 0x900, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: buffer_store_dword v1, off, s[8:11], 0
; VI-NEXT: s_endpgm
@@ -382,17 +383,18 @@ define amdgpu_kernel void @test_copy_v4i8_x2_extra_use(ptr addrspace(1) %out0, p
; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; VI-NEXT: v_add_u16_e32 v3, 9, v0
; VI-NEXT: v_and_b32_e32 v4, 0xffffff00, v1
; VI-NEXT: v_add_u16_e32 v1, 9, v1
+; VI-NEXT: v_add_u16_e32 v3, 9, v0
+; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
; VI-NEXT: v_and_b32_e32 v2, 0xffffff00, v0
; VI-NEXT: v_and_b32_e32 v3, 0xff, v3
-; VI-NEXT: v_and_b32_e32 v1, 0xff, v1
-; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_or_b32_e32 v1, v4, v1
-; VI-NEXT: v_add_u16_e32 v2, 0x900, v2
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_add_u16_e32 v1, 0x900, v1
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_add_u16_e32 v2, 0x900, v2
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: buffer_store_dword v1, off, s[12:15], 0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
diff --git a/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll b/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll
index cbbda05e7f732..3ca7dea0c4b08 100644
--- a/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll
+++ b/llvm/test/CodeGen/AMDGPU/copysign-to-disjoint-or-combine.ll
@@ -105,7 +105,8 @@ define double @copysign_known_signmask_f64_known_positive_mag(double nofpclass(n
; GFX9-LABEL: copysign_known_signmask_f64_known_positive_mag:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_lshl_or_b32 v1, v2, 31, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 31, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
%signmask = shl i64 %sign, 63
%signmask.bitcast = bitcast i64 %signmask to double
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz.ll b/llvm/test/CodeGen/AMDGPU/ctlz.ll
index a23131a10909b..2318155c3c078 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz.ll
@@ -1830,8 +1830,10 @@ define amdgpu_kernel void @v_ctlz_i17_sel_ne_bitwidth(ptr addrspace(1) noalias %
; VI-NEXT: v_mov_b32_e32 v1, 0x1ffff
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: v_ffbh_u32_e32 v0, v0
; VI-NEXT: v_min_u32_e32 v0, 32, v0
; VI-NEXT: v_add_u32_e32 v0, vcc, -15, v0
diff --git a/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
index e67d314fb4727..867bd8ee26227 100644
--- a/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctlz_zero_poison.ll
@@ -840,8 +840,10 @@ define amdgpu_kernel void @v_ctlz_zero_poison_i32_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v5, v[6:7]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1000,16 +1002,20 @@ define amdgpu_kernel void @v_ctlz_zero_poison_i64_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v3, v[4:5]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_waitcnt vmcnt(7)
+; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v10
; VI-NEXT: s_waitcnt vmcnt(6)
-; VI-NEXT: v_lshl_or_b32 v4, v10, 8, v11
+; VI-NEXT: v_or_b32_e32 v4, v4, v11
; VI-NEXT: s_waitcnt vmcnt(5)
; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v12
; VI-NEXT: s_waitcnt vmcnt(4)
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v5, v4
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v7
; VI-NEXT: v_ffbh_u32_e32 v4, v4
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshl_or_b32 v5, v7, 8, v8
+; VI-NEXT: v_or_b32_e32 v5, v5, v8
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/ctpop16.ll b/llvm/test/CodeGen/AMDGPU/ctpop16.ll
index 2267294721d88..3b3f59363e252 100644
--- a/llvm/test/CodeGen/AMDGPU/ctpop16.ll
+++ b/llvm/test/CodeGen/AMDGPU/ctpop16.ll
@@ -502,8 +502,9 @@ define amdgpu_kernel void @v_ctpop_v2i16(ptr addrspace(1) noalias %out, ptr addr
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm
;
@@ -571,9 +572,10 @@ define amdgpu_kernel void @v_ctpop_v2i16(ptr addrspace(1) noalias %out, ptr addr
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; VI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
-; VI-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; VI-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -628,15 +630,17 @@ define amdgpu_kernel void @v_ctpop_v4i16(ptr addrspace(1) noalias %out, ptr addr
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v0
+; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
-; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
+; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v3
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
@@ -740,12 +744,14 @@ define amdgpu_kernel void @v_ctpop_v4i16(ptr addrspace(1) noalias %out, ptr addr
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v2, v2, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v3, v3, 0
-; VI-GISEL-NEXT: v_lshl_or_b32 v0, v2, 16, v0
-; VI-GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v1
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-GISEL-NEXT: v_or_b32_e32 v1, v1, v3
; VI-GISEL-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -812,25 +818,29 @@ define amdgpu_kernel void @v_ctpop_v8i16(ptr addrspace(1) noalias %out, ptr addr
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v3
-; VI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; VI-NEXT: v_lshrrev_b32_e32 v6, 16, v1
-; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; VI-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; VI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: v_bcnt_u32_b32 v4, v4, 0
-; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
; VI-NEXT: v_bcnt_u32_b32 v5, v5, 0
-; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
; VI-NEXT: v_bcnt_u32_b32 v6, v6, 0
-; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
; VI-NEXT: v_bcnt_u32_b32 v7, v7, 0
+; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
+; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
-; VI-NEXT: v_lshl_or_b32 v3, v4, 16, v3
-; VI-NEXT: v_lshl_or_b32 v2, v5, 16, v2
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
-; VI-NEXT: v_lshl_or_b32 v0, v7, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-NEXT: v_or_b32_e32 v3, v3, v4
+; VI-NEXT: v_or_b32_e32 v2, v2, v5
+; VI-NEXT: v_or_b32_e32 v1, v1, v6
+; VI-NEXT: v_or_b32_e32 v0, v0, v7
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
@@ -986,18 +996,22 @@ define amdgpu_kernel void @v_ctpop_v8i16(ptr addrspace(1) noalias %out, ptr addr
; VI-GISEL-NEXT: v_and_b32_e32 v1, 0xffff, v1
; VI-GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2
; VI-GISEL-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v4, v4, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v5, v5, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v2, v2, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v6, v6, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v3, v3, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v7, v7, 0
-; VI-GISEL-NEXT: v_lshl_or_b32 v0, v4, 16, v0
-; VI-GISEL-NEXT: v_lshl_or_b32 v1, v5, 16, v1
-; VI-GISEL-NEXT: v_lshl_or_b32 v2, v6, 16, v2
-; VI-GISEL-NEXT: v_lshl_or_b32 v3, v7, 16, v3
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v3, v3, 0
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v4
+; VI-GISEL-NEXT: v_or_b32_e32 v1, v1, v5
+; VI-GISEL-NEXT: v_or_b32_e32 v2, v2, v6
+; VI-GISEL-NEXT: v_or_b32_e32 v3, v3, v7
; VI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-GISEL-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x()
@@ -1094,46 +1108,54 @@ define amdgpu_kernel void @v_ctpop_v16i16(ptr addrspace(1) noalias %out, ptr add
; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v3
-; VI-NEXT: v_and_b32_e32 v3, 0xffff, v3
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v2
-; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; VI-NEXT: v_lshrrev_b32_e32 v10, 16, v1
-; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; VI-NEXT: v_lshrrev_b32_e32 v11, 16, v0
+; VI-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; VI-NEXT: v_and_b32_e32 v1, 0xffff, v1
; VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; VI-NEXT: v_and_b32_e32 v7, 0xffff, v7
; VI-NEXT: v_lshrrev_b32_e32 v13, 16, v6
-; VI-NEXT: v_and_b32_e32 v6, 0xffff, v6
; VI-NEXT: v_lshrrev_b32_e32 v14, 16, v5
-; VI-NEXT: v_and_b32_e32 v5, 0xffff, v5
; VI-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; VI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; VI-NEXT: v_bcnt_u32_b32 v8, v8, 0
-; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
; VI-NEXT: v_bcnt_u32_b32 v9, v9, 0
-; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
; VI-NEXT: v_bcnt_u32_b32 v10, v10, 0
-; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
; VI-NEXT: v_bcnt_u32_b32 v11, v11, 0
+; VI-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; VI-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; VI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; VI-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; VI-NEXT: v_bcnt_u32_b32 v3, v3, 0
+; VI-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; VI-NEXT: v_bcnt_u32_b32 v1, v1, 0
; VI-NEXT: v_bcnt_u32_b32 v0, v0, 0
; VI-NEXT: v_bcnt_u32_b32 v12, v12, 0
-; VI-NEXT: v_bcnt_u32_b32 v7, v7, 0
; VI-NEXT: v_bcnt_u32_b32 v13, v13, 0
-; VI-NEXT: v_bcnt_u32_b32 v6, v6, 0
; VI-NEXT: v_bcnt_u32_b32 v14, v14, 0
-; VI-NEXT: v_bcnt_u32_b32 v5, v5, 0
; VI-NEXT: v_bcnt_u32_b32 v15, v15, 0
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; VI-NEXT: v_bcnt_u32_b32 v7, v7, 0
+; VI-NEXT: v_bcnt_u32_b32 v6, v6, 0
+; VI-NEXT: v_bcnt_u32_b32 v5, v5, 0
; VI-NEXT: v_bcnt_u32_b32 v4, v4, 0
-; VI-NEXT: v_lshl_or_b32 v3, v8, 16, v3
-; VI-NEXT: v_lshl_or_b32 v2, v9, 16, v2
-; VI-NEXT: v_lshl_or_b32 v1, v10, 16, v1
-; VI-NEXT: v_lshl_or_b32 v0, v11, 16, v0
-; VI-NEXT: v_lshl_or_b32 v7, v12, 16, v7
-; VI-NEXT: v_lshl_or_b32 v6, v13, 16, v6
-; VI-NEXT: v_lshl_or_b32 v5, v14, 16, v5
-; VI-NEXT: v_lshl_or_b32 v4, v15, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; VI-NEXT: v_or_b32_e32 v3, v3, v8
+; VI-NEXT: v_or_b32_e32 v2, v2, v9
+; VI-NEXT: v_or_b32_e32 v1, v1, v10
+; VI-NEXT: v_or_b32_e32 v0, v0, v11
+; VI-NEXT: v_or_b32_e32 v7, v7, v12
+; VI-NEXT: v_or_b32_e32 v6, v6, v13
+; VI-NEXT: v_or_b32_e32 v5, v5, v14
+; VI-NEXT: v_or_b32_e32 v4, v4, v15
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; VI-NEXT: s_endpgm
@@ -1404,34 +1426,42 @@ define amdgpu_kernel void @v_ctpop_v16i16(ptr addrspace(1) noalias %out, ptr add
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v13, 16, v5
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v14, 16, v6
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v8, v8, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v9, v9, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v2, v2, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v10, v10, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v3, v3, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v11, v11, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v0, v0, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v1, v1, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v2, v2, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v3, v3, 0
; VI-GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4
; VI-GISEL-NEXT: v_and_b32_e32 v5, 0xffff, v5
; VI-GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6
; VI-GISEL-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v4, v4, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v12, v12, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v5, v5, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v13, v13, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v6, v6, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v14, v14, 0
-; VI-GISEL-NEXT: v_bcnt_u32_b32 v7, v7, 0
; VI-GISEL-NEXT: v_bcnt_u32_b32 v15, v15, 0
-; VI-GISEL-NEXT: v_lshl_or_b32 v0, v8, 16, v0
-; VI-GISEL-NEXT: v_lshl_or_b32 v1, v9, 16, v1
-; VI-GISEL-NEXT: v_lshl_or_b32 v2, v10, 16, v2
-; VI-GISEL-NEXT: v_lshl_or_b32 v3, v11, 16, v3
-; VI-GISEL-NEXT: v_lshl_or_b32 v4, v12, 16, v4
-; VI-GISEL-NEXT: v_lshl_or_b32 v5, v13, 16, v5
-; VI-GISEL-NEXT: v_lshl_or_b32 v6, v14, 16, v6
-; VI-GISEL-NEXT: v_lshl_or_b32 v7, v15, 16, v7
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v4, v4, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v5, v5, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v6, v6, 0
+; VI-GISEL-NEXT: v_bcnt_u32_b32 v7, v7, 0
+; VI-GISEL-NEXT: v_or_b32_e32 v0, v0, v8
+; VI-GISEL-NEXT: v_or_b32_e32 v1, v1, v9
+; VI-GISEL-NEXT: v_or_b32_e32 v2, v2, v10
+; VI-GISEL-NEXT: v_or_b32_e32 v3, v3, v11
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v8, 16, v12
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v9, 16, v13
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v10, 16, v14
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v11, 16, v15
+; VI-GISEL-NEXT: v_or_b32_e32 v4, v4, v8
+; VI-GISEL-NEXT: v_or_b32_e32 v5, v5, v9
+; VI-GISEL-NEXT: v_or_b32_e32 v6, v6, v10
+; VI-GISEL-NEXT: v_or_b32_e32 v7, v7, v11
; VI-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-GISEL-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; VI-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
index 5f2f677399ae1..60d87fe22f208 100644
--- a/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
+++ b/llvm/test/CodeGen/AMDGPU/cttz_zero_poison.ll
@@ -682,8 +682,10 @@ define amdgpu_kernel void @v_cttz_zero_poison_i16_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v3, v[0:1]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: v_ffbl_b32_e32 v3, v2
; VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
@@ -803,8 +805,10 @@ define amdgpu_kernel void @v_cttz_zero_poison_i32_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v5, v[6:7]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -963,15 +967,19 @@ define amdgpu_kernel void @v_cttz_zero_poison_i64_with_select(ptr addrspace(1) n
; VI-NEXT: flat_load_ubyte v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_waitcnt vmcnt(7)
+; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v12
; VI-NEXT: s_waitcnt vmcnt(6)
-; VI-NEXT: v_lshl_or_b32 v3, v12, 8, v13
+; VI-NEXT: v_or_b32_e32 v3, v3, v13
; VI-NEXT: s_waitcnt vmcnt(5)
; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; VI-NEXT: s_waitcnt vmcnt(4)
; VI-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v3, v4, v3
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v6
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshl_or_b32 v4, v6, 8, v7
+; VI-NEXT: v_or_b32_e32 v4, v4, v7
; VI-NEXT: v_ffbl_b32_e32 v3, v3
; VI-NEXT: v_add_u32_e32 v3, vcc, 32, v3
; VI-NEXT: s_waitcnt vmcnt(1)
@@ -1131,8 +1139,10 @@ define amdgpu_kernel void @v_cttz_i32_sel_eq_neg1(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_load_ubyte v5, v[6:7]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1259,8 +1269,10 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_neg1(ptr addrspace(1) noalias %out,
; VI-NEXT: flat_load_ubyte v5, v[6:7]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1390,8 +1402,10 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %
; VI-NEXT: flat_load_ubyte v5, v[6:7]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshl_or_b32 v2, v2, 8, v3
+; VI-NEXT: v_or_b32_e32 v2, v2, v3
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
@@ -1588,8 +1602,10 @@ define amdgpu_kernel void @v_cttz_i32_sel_ne_bitwidth(ptr addrspace(1) noalias %
; VI-NEXT: flat_load_ubyte v2, v[2:3]
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_lshlrev_b32_e32 v3, 8, v4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshl_or_b32 v2, v4, 8, v2
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_ffbl_b32_e32 v2, v2
; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index 9f2ecf285c7ac..0eed0ba50092b 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -1483,6 +1483,7 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned_multiuse(ptr addrspace(1
; VI-NEXT: s_mov_b32 s8, s2
; VI-NEXT: s_mov_b32 s9, s3
; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v6
; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v6
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_lshlrev_b32_e32 v7, 8, v2
@@ -1490,7 +1491,7 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned_multiuse(ptr addrspace(1
; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v4
-; VI-NEXT: v_lshl_or_b32 v4, v6, 8, v4
+; VI-NEXT: v_or_b32_e32 v4, v5, v4
; VI-NEXT: v_or_b32_e32 v5, v7, v3
; VI-NEXT: v_mov_b32_e32 v3, v1
; VI-NEXT: v_perm_b32 v4, v4, v5, s12
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2.ll b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
index 30f1d49362b42..9f1b55ea3b1ef 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
@@ -1497,9 +1497,11 @@ define amdgpu_kernel void @read2_v2i32_align1_odd_offset(ptr addrspace(1) %out)
; GFX9-ALIGNED-NEXT: ds_read_u8 v8, v2 offset:71
; GFX9-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v0, v3, 8, v0
-; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v1, v1, 8, v6
+; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX9-ALIGNED-NEXT: v_or_b32_e32 v1, v1, v6
; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v6, 8, v7
+; GFX9-ALIGNED-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v5
; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
diff --git a/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll b/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
index 9af0548bc43a1..217868d5b7b59 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
@@ -19,7 +19,8 @@ define void @extract_multiple_v16i8(ptr addrspace(1) %out) {
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s0
; GFX9-NEXT: v_perm_b32 v3, v4, v5, s0
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -33,8 +34,9 @@ define void @extract_multiple_v16i8(ptr addrspace(1) %out) {
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
; GFX12-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX12-NEXT: v_or_b32_e32 v2, v2, v3
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
; GFX12-NEXT: s_set_pc_i64 s[30:31]
%ptr = getelementptr inbounds i8, ptr addrspace(3) @lds, i32 0
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 818b5e4154ecc..3f6750546618f 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -3911,8 +3911,9 @@ define <2 x bfloat> @v_copysign_out_v2bf16_mag_v2bf16_sign_v2f64(<2 x bfloat> %m
; GFX8-LABEL: v_copysign_out_v2bf16_mag_v2bf16_sign_v2f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; GFX8-NEXT: v_and_b32_e32 v2, 0x8000, v2
-; GFX8-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX8-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-NEXT: s_mov_b32 s4, 0x7fff7fff
; GFX8-NEXT: v_bfi_b32 v0, s4, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
@@ -7151,12 +7152,14 @@ define <4 x bfloat> @v_copysign_out_v4bf16_mag_v4bf16_sign_v4f64(<4 x bfloat> %m
; GFX8-LABEL: v_copysign_out_v4bf16_mag_v4bf16_sign_v4f64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; GFX8-NEXT: v_and_b32_e32 v3, 0x8000, v3
-; GFX8-NEXT: v_lshl_or_b32 v2, v5, 16, v3
+; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
; GFX8-NEXT: s_mov_b32 s4, 0x7fff7fff
-; GFX8-NEXT: v_and_b32_e32 v3, 0x8000, v7
; GFX8-NEXT: v_bfi_b32 v0, s4, v0, v2
-; GFX8-NEXT: v_lshl_or_b32 v2, v9, 16, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v9
+; GFX8-NEXT: v_and_b32_e32 v3, 0x8000, v7
+; GFX8-NEXT: v_or_b32_e32 v2, v3, v2
; GFX8-NEXT: v_bfi_b32 v1, s4, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -7986,8 +7989,9 @@ define <2 x bfloat> @v_copysign_v2bf16_0_v2bf64(<2 x double> %sign) {
; GFX8-LABEL: v_copysign_v2bf16_0_v2bf64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v3
; GFX8-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; GFX8-NEXT: v_lshl_or_b32 v0, v3, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: s_mov_b32 s4, 0x7fff7fff
; GFX8-NEXT: v_bfi_b32 v0, s4, 0, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 718c55d8ad397..0ae807783a151 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -913,8 +913,9 @@ define half @v_copysign_out_f16_mag_f64_sign_f16(double %mag, half %sign) {
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v1, vcc, s4, v1
+; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v1
; VI-NEXT: v_or_b32_e32 v3, v5, v3
-; VI-NEXT: v_lshl_or_b32 v4, v1, 12, v0
+; VI-NEXT: v_or_b32_e32 v4, v0, v4
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; VI-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
; VI-NEXT: v_and_b32_e32 v4, 7, v3
@@ -3048,8 +3049,9 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; VI-NEXT: s_movk_i32 s5, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s5, v3
+; VI-NEXT: v_lshlrev_b32_e32 v6, 12, v3
; VI-NEXT: v_or_b32_e32 v5, v7, v5
-; VI-NEXT: v_lshl_or_b32 v6, v3, 12, v2
+; VI-NEXT: v_or_b32_e32 v6, v2, v6
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; VI-NEXT: v_and_b32_e32 v6, 7, v5
@@ -3085,8 +3087,9 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v3
; VI-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v1, vcc, s5, v1
+; VI-NEXT: v_lshlrev_b32_e32 v5, 12, v1
; VI-NEXT: v_or_b32_e32 v3, v8, v3
-; VI-NEXT: v_lshl_or_b32 v5, v1, 12, v0
+; VI-NEXT: v_or_b32_e32 v5, v0, v5
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; VI-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; VI-NEXT: v_and_b32_e32 v5, 7, v3
@@ -3453,8 +3456,9 @@ define <2 x half> @v_copysign_out_v2f16_mag_v2f16_sign_v2f64(<2 x half> %mag, <2
; VI-LABEL: v_copysign_out_v2f16_mag_v2f16_sign_v2f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; VI-NEXT: v_and_b32_e32 v2, 0x8000, v2
-; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: s_mov_b32 s4, 0x7fff7fff
; VI-NEXT: v_bfi_b32 v0, s4, v0, v1
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -4686,8 +4690,9 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI-NEXT: s_movk_i32 s5, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v5, vcc, s5, v5
+; VI-NEXT: v_lshlrev_b32_e32 v9, 12, v5
; VI-NEXT: v_or_b32_e32 v8, v10, v8
-; VI-NEXT: v_lshl_or_b32 v9, v5, 12, v4
+; VI-NEXT: v_or_b32_e32 v9, v4, v9
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; VI-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; VI-NEXT: v_and_b32_e32 v9, 7, v8
@@ -4723,8 +4728,9 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v8, v5
; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v1, vcc, s5, v1
+; VI-NEXT: v_lshlrev_b32_e32 v8, 12, v1
; VI-NEXT: v_or_b32_e32 v5, v11, v5
-; VI-NEXT: v_lshl_or_b32 v8, v1, 12, v0
+; VI-NEXT: v_or_b32_e32 v8, v0, v8
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; VI-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc
; VI-NEXT: v_and_b32_e32 v8, 7, v5
@@ -4757,8 +4763,9 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v5, v2
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s5, v3
+; VI-NEXT: v_lshlrev_b32_e32 v5, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v8, v2
-; VI-NEXT: v_lshl_or_b32 v5, v3, 12, v1
+; VI-NEXT: v_or_b32_e32 v5, v1, v5
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc
; VI-NEXT: v_and_b32_e32 v5, 7, v2
@@ -4775,8 +4782,9 @@ define <3 x half> @v_copysign_out_v3f16_mag_v3f64_sign_v3f16(<3 x double> %mag,
; VI-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v3
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: s_mov_b32 s4, 0x7fff7fff
; VI-NEXT: v_bfi_b32 v0, s4, v0, v6
; VI-NEXT: v_bfi_b32 v1, s4, v4, v7
@@ -5831,8 +5839,9 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: s_movk_i32 s5, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v5, vcc, s5, v5
+; VI-NEXT: v_lshlrev_b32_e32 v11, 12, v5
; VI-NEXT: v_or_b32_e32 v10, v12, v10
-; VI-NEXT: v_lshl_or_b32 v11, v5, 12, v4
+; VI-NEXT: v_or_b32_e32 v11, v4, v11
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; VI-NEXT: v_cndmask_b32_e32 v10, v11, v10, vcc
; VI-NEXT: v_and_b32_e32 v11, 7, v10
@@ -5868,8 +5877,9 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v10, v6
; VI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v7, vcc, s5, v7
+; VI-NEXT: v_lshlrev_b32_e32 v10, 12, v7
; VI-NEXT: v_or_b32_e32 v6, v13, v6
-; VI-NEXT: v_lshl_or_b32 v10, v7, 12, v5
+; VI-NEXT: v_or_b32_e32 v10, v5, v10
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v7
; VI-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; VI-NEXT: v_and_b32_e32 v10, 7, v6
@@ -5902,8 +5912,9 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v7, v6
; VI-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v1, vcc, s5, v1
+; VI-NEXT: v_lshlrev_b32_e32 v7, 12, v1
; VI-NEXT: v_or_b32_e32 v6, v10, v6
-; VI-NEXT: v_lshl_or_b32 v7, v1, 12, v0
+; VI-NEXT: v_or_b32_e32 v7, v0, v7
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v1
; VI-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc
; VI-NEXT: v_and_b32_e32 v7, 7, v6
@@ -5936,8 +5947,9 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cmp_ne_u32_e32 vcc, v6, v2
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s5, v3
+; VI-NEXT: v_lshlrev_b32_e32 v6, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v7, v2
-; VI-NEXT: v_lshl_or_b32 v6, v3, 12, v1
+; VI-NEXT: v_or_b32_e32 v6, v1, v6
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; VI-NEXT: v_and_b32_e32 v6, 7, v2
@@ -5954,11 +5966,13 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f64_sign_v4f16(<4 x double> %mag,
; VI-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc
; VI-NEXT: v_cmp_eq_u32_e32 vcc, s6, v3
; VI-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v5
; VI-NEXT: v_and_b32_e32 v2, 0x7fff, v4
-; VI-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; VI-NEXT: s_mov_b32 s4, 0x7fff7fff
-; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_bfi_b32 v0, s4, v0, v8
; VI-NEXT: v_bfi_b32 v1, s4, v1, v9
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -6562,12 +6576,14 @@ define <4 x half> @v_copysign_out_v4f16_mag_v4f16_sign_v4f64(<4 x half> %mag, <4
; VI-LABEL: v_copysign_out_v4f16_mag_v4f16_sign_v4f64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v5
; VI-NEXT: v_and_b32_e32 v3, 0x8000, v3
-; VI-NEXT: v_lshl_or_b32 v2, v5, 16, v3
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: s_mov_b32 s4, 0x7fff7fff
-; VI-NEXT: v_and_b32_e32 v3, 0x8000, v7
; VI-NEXT: v_bfi_b32 v0, s4, v0, v2
-; VI-NEXT: v_lshl_or_b32 v2, v9, 16, v3
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v9
+; VI-NEXT: v_and_b32_e32 v3, 0x8000, v7
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_bfi_b32 v1, s4, v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
@@ -7242,8 +7258,9 @@ define <2 x half> @v_copysign_v2f16_0_v2bf64(<2 x double> %sign) {
; VI-LABEL: v_copysign_v2f16_0_v2bf64:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v3
; VI-NEXT: v_and_b32_e32 v1, 0x8000, v1
-; VI-NEXT: v_lshl_or_b32 v0, v3, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: s_mov_b32 s4, 0x7fff7fff
; VI-NEXT: v_bfi_b32 v0, s4, 0, v0
; VI-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
index 90c6048e74e3e..f01879d98da41 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fadd.ll
@@ -8711,9 +8711,10 @@ define half @flat_agent_atomic_fadd_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9089,9 +9090,10 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9470,9 +9472,10 @@ define half @flat_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9829,9 +9832,10 @@ define void @flat_agent_atomic_fadd_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -10195,9 +10199,10 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -10564,9 +10569,10 @@ define void @flat_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -11501,9 +11507,10 @@ define half @flat_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -11875,9 +11882,10 @@ define void @flat_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
index 5ce36037c41b7..4e3d7947bfbbd 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmax.ll
@@ -6359,9 +6359,10 @@ define half @flat_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6762,9 +6763,10 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7168,9 +7170,10 @@ define half @flat_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7547,9 +7550,10 @@ define void @flat_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_max_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7938,9 +7942,10 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8332,9 +8337,10 @@ define void @flat_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9334,9 +9340,10 @@ define half @flat_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9733,9 +9740,10 @@ define void @flat_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
index 01c236cbd27c8..40f58f5ce5902 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fmin.ll
@@ -6359,9 +6359,10 @@ define half @flat_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr %
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6762,9 +6763,10 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grain
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7168,9 +7170,10 @@ define half @flat_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_grain
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7547,9 +7550,10 @@ define void @flat_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_min_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7938,9 +7942,10 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8332,9 +8337,10 @@ define void @flat_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9334,9 +9340,10 @@ define half @flat_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_grai
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9733,9 +9740,10 @@ define void @flat_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
index 5e2a6e56eab91..d2bc7b3f4e48e 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-atomicrmw-fsub.ll
@@ -6142,9 +6142,10 @@ define half @flat_agent_atomic_fsub_ret_f16(ptr %ptr, half %val) #0 {
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6520,9 +6521,10 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6901,9 +6903,10 @@ define half @flat_agent_atomic_fsub_ret_f16__offset12b_neg(ptr %ptr, half %val)
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7260,9 +7263,10 @@ define void @flat_agent_atomic_fsub_noret_f16(ptr %ptr, half %val) #0 {
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7626,9 +7630,10 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %val
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7995,9 +8000,10 @@ define void @flat_agent_atomic_fsub_noret_f16__offset12b_neg(ptr %ptr, half %val
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8932,9 +8938,10 @@ define half @flat_system_atomic_fsub_ret_f16__offset12b_pos(ptr %ptr, half %val)
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9306,9 +9313,10 @@ define void @flat_system_atomic_fsub_noret_f16__offset12b_pos(ptr %ptr, half %va
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
index d1467f5615c7b..13e4206ab7f57 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.f16.ll
@@ -3527,10 +3527,12 @@ define <4 x half> @v_fneg_fmad_v4f32(<4 x half> %a, <4 x half> %b, <4 x half> %c
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; VI-NEXT: v_fma_f16 v7, v9, v8, v7
-; VI-NEXT: v_fma_f16 v1, v1, v3, v5
; VI-NEXT: v_fma_f16 v0, v0, v2, v4
-; VI-NEXT: v_lshl_or_b32 v0, v7, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; VI-NEXT: v_fma_f16 v1, v1, v3, v5
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; VI-NEXT: s_setpc_b64 s[30:31]
@@ -3610,10 +3612,12 @@ define <4 x half> @v_fneg_fmad_v4f32_nsz(<4 x half> %a, <4 x half> %b, <4 x half
; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; VI-NEXT: v_fma_f16 v7, v9, -v8, -v7
-; VI-NEXT: v_fma_f16 v1, v1, -v3, -v5
; VI-NEXT: v_fma_f16 v0, v0, -v2, -v4
-; VI-NEXT: v_lshl_or_b32 v0, v7, 16, v0
-; VI-NEXT: v_lshl_or_b32 v1, v6, 16, v1
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; VI-NEXT: v_fma_f16 v1, v1, -v3, -v5
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
; VI-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_fneg_fmad_v4f32_nsz:
@@ -3984,8 +3988,9 @@ define half @v_fneg_fp_round_f64_to_f16(double %a) #0 {
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v5, v2
-; VI-NEXT: v_lshl_or_b32 v4, v3, 12, v0
+; VI-NEXT: v_or_b32_e32 v4, v0, v4
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-NEXT: v_and_b32_e32 v4, 7, v2
@@ -4132,8 +4137,9 @@ define half @v_fneg_fp_round_fneg_f64_to_f16(double %a) #0 {
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v5, v2
-; VI-NEXT: v_lshl_or_b32 v4, v3, 12, v0
+; VI-NEXT: v_or_b32_e32 v4, v0, v4
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-NEXT: v_and_b32_e32 v4, 7, v2
@@ -4286,8 +4292,9 @@ define { half, double } @v_fneg_fp_round_store_use_fneg_f64_to_f16(double %a) #0
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v5, vcc, s4, v5
+; VI-NEXT: v_lshlrev_b32_e32 v6, 12, v5
; VI-NEXT: v_or_b32_e32 v4, v7, v4
-; VI-NEXT: v_lshl_or_b32 v6, v5, 12, v0
+; VI-NEXT: v_or_b32_e32 v6, v0, v6
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v5
; VI-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc
; VI-NEXT: v_and_b32_e32 v6, 7, v4
@@ -4444,8 +4451,9 @@ define { half, double } @v_fneg_fp_round_multi_use_fneg_f64_to_f16(double %a, do
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, s4, v6
+; VI-NEXT: v_lshlrev_b32_e32 v7, 12, v6
; VI-NEXT: v_or_b32_e32 v5, v8, v5
-; VI-NEXT: v_lshl_or_b32 v7, v6, 12, v4
+; VI-NEXT: v_or_b32_e32 v7, v4, v7
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v6
; VI-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
; VI-NEXT: v_and_b32_e32 v7, 7, v5
@@ -4600,8 +4608,9 @@ define { half, half } @v_fneg_multi_use_fp_round_fneg_f64_to_f16(double %a) #0 {
; VI-NEXT: s_movk_i32 s4, 0xfc10
; VI-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; VI-NEXT: v_add_u32_e32 v3, vcc, s4, v3
+; VI-NEXT: v_lshlrev_b32_e32 v4, 12, v3
; VI-NEXT: v_or_b32_e32 v2, v5, v2
-; VI-NEXT: v_lshl_or_b32 v4, v3, 12, v0
+; VI-NEXT: v_or_b32_e32 v4, v0, v4
; VI-NEXT: v_cmp_gt_i32_e32 vcc, 1, v3
; VI-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; VI-NEXT: v_and_b32_e32 v4, 7, v2
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index 690983f0be8e1..a893711ce0942 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -2020,9 +2020,10 @@ define <2 x i8> @test_s_signed_v2f64_v2i8(<2 x double> inreg %f) {
; GFX11-NEXT: s_movk_i32 s0, 0xff80
; GFX11-NEXT: v_med3_i32 v2, v0, s0, 0x7f
; GFX11-NEXT: v_med3_i32 v0, v1, s0, 0x7f
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v2
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT: v_lshl_or_b32 v0, v2, 8, v0
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_v2f64_v2i8:
@@ -2038,9 +2039,10 @@ define <2 x i8> @test_s_signed_v2f64_v2i8(<2 x double> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT: v_med3_i32 v2, v0, s0, 0x7f
; GFX12-ISEL-NEXT: v_med3_i32 v0, v1, s0, 0x7f
-; GFX12-ISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v2
; GFX12-ISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-ISEL-NEXT: v_lshl_or_b32 v0, v2, 8, v0
+; GFX12-ISEL-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-ISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_v2f64_v2i8:
@@ -3564,23 +3566,24 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-FAKE16-LABEL: test_s_signed_v4f16_v4i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, s1
; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
-; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, s1
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s2
+; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, s1
; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-FAKE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX11-FAKE16-NEXT: s_movk_i32 s1, 0xff80
+; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX11-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-FAKE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
-; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX11-FAKE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX11-FAKE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v0, v1
; GFX11-FAKE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3594,23 +3597,24 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-TRUE16-LABEL: test_s_signed_v4f16_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
+; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-TRUE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX11-TRUE16-NEXT: s_movk_i32 s1, 0xff80
+; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
-; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v0, v1
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3628,25 +3632,27 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, s1
; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
-; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s2
+; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, s1
; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-FAKE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
; GFX12-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-FAKE16-NEXT: s_movk_i32 s1, 0xff80
+; GFX12-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX12-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
-; GFX12-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX12-FAKE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX12-FAKE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v0, v1
; GFX12-FAKE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3664,25 +3670,27 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
-; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
+; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-TRUE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-TRUE16-NEXT: s_movk_i32 s1, 0xff80
+; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
-; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX12-TRUE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX12-TRUE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v0, v1
; GFX12-TRUE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -6962,17 +6970,18 @@ define <4 x i8> @test_s_signed_v4f32_v4i8(<4 x float> inreg %f) {
; GFX11-LABEL: test_s_signed_v4f32_v4i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cvt_i32_f32_e32 v0, s3
; GFX11-NEXT: v_cvt_i32_f32_e32 v1, s2
; GFX11-NEXT: s_movk_i32 s2, 0xff80
-; GFX11-NEXT: v_cvt_i32_f32_e32 v0, s3
; GFX11-NEXT: v_cvt_i32_f32_e32 v2, s1
; GFX11-NEXT: v_cvt_i32_f32_e32 v3, s0
-; GFX11-NEXT: v_med3_i32 v1, v1, s2, 0x7f
; GFX11-NEXT: v_med3_i32 v0, v0, s2, 0x7f
+; GFX11-NEXT: v_med3_i32 v1, v1, s2, 0x7f
; GFX11-NEXT: v_med3_i32 v2, v2, s2, 0x7f
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v0, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v2, v1, v0
; GFX11-NEXT: v_med3_i32 v0, v3, s2, 0x7f
; GFX11-NEXT: v_and_b32_e32 v1, 0xff00, v4
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -6991,19 +7000,20 @@ define <4 x i8> @test_s_signed_v4f32_v4i8(<4 x float> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT: v_mov_b32_e32 v0, 0x7f
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s1, s1
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s2, s2
; GFX12-ISEL-NEXT: s_cvt_i32_f32 s3, s3
+; GFX12-ISEL-NEXT: s_cvt_i32_f32 s2, s2
+; GFX12-ISEL-NEXT: s_cvt_i32_f32 s1, s1
; GFX12-ISEL-NEXT: s_cvt_i32_f32 s0, s0
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_med3_i32 v3, 0xffffff80, s1, v0
-; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX12-ISEL-NEXT: v_med3_i32 v2, 0xffffff80, s2, v0
; GFX12-ISEL-NEXT: v_med3_i32 v1, 0xffffff80, s3, v0
+; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX12-ISEL-NEXT: v_med3_i32 v2, 0xffffff80, s2, v0
+; GFX12-ISEL-NEXT: v_med3_i32 v3, 0xffffff80, s1, v0
; GFX12-ISEL-NEXT: v_med3_i32 v0, 0xffffff80, s0, v0
; GFX12-ISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX12-ISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-ISEL-NEXT: v_lshl_or_b32 v2, v1, 8, v2
+; GFX12-ISEL-NEXT: v_or_b32_e32 v2, v2, v1
; GFX12-ISEL-NEXT: v_and_b32_e32 v1, 0xff00, v3
; GFX12-ISEL-NEXT: v_or_b32_e32 v0, v0, v3
; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v2
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index c3f7283bc00f8..14094c50e2290 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -1891,11 +1891,12 @@ define <2 x i8> @test_s_unsigned_v2f64_v2i8(<2 x double> inreg %f) {
; GFX9-LABEL: test_s_unsigned_v2f64_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_u32_f64_e32 v0, s[16:17]
; GFX9-NEXT: v_cvt_u32_f64_e32 v1, s[18:19]
-; GFX9-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX9-NEXT: v_cvt_u32_f64_e32 v0, s[16:17]
; GFX9-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 8, v0
+; GFX9-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v1
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_unsigned_v2f64_v2i8:
@@ -1905,7 +1906,8 @@ define <2 x i8> @test_s_unsigned_v2f64_v2i8(<2 x double> inreg %f) {
; GFX11-NEXT: v_cvt_u32_f64_e32 v2, s[0:1]
; GFX11-NEXT: v_min_u32_e32 v1, 0xff, v0
; GFX11-NEXT: v_min_u32_e32 v0, 0xff, v2
-; GFX11-NEXT: v_lshl_or_b32 v0, v1, 8, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_unsigned_v2f64_v2i8:
@@ -1919,7 +1921,8 @@ define <2 x i8> @test_s_unsigned_v2f64_v2i8(<2 x double> inreg %f) {
; GFX12-ISEL-NEXT: v_cvt_u32_f64_e32 v2, s[0:1]
; GFX12-ISEL-NEXT: v_min_u32_e32 v1, 0xff, v0
; GFX12-ISEL-NEXT: v_min_u32_e32 v0, 0xff, v2
-; GFX12-ISEL-NEXT: v_lshl_or_b32 v0, v1, 8, v0
+; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v1
+; GFX12-ISEL-NEXT: v_or_b32_e32 v0, v0, v2
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_unsigned_v2f64_v2i8:
@@ -3277,13 +3280,14 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
; GFX9-NEXT: s_lshr_b32 s5, s17, 16
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_cvt_u16_f16_e32 v2, s17
; GFX9-NEXT: v_cvt_u16_f16_e32 v3, s5
-; GFX9-NEXT: v_min_u32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_cvt_u16_f16_e32 v2, s17
; GFX9-NEXT: v_min_u32_sdwa v3, v3, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_min_u32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s16
; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 8, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3308,7 +3312,8 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v0, 8, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v1, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3334,7 +3339,8 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v0, 8, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v1, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3366,7 +3372,8 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v0, 8, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v1, v0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3398,7 +3405,8 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX12-TRUE16-NEXT: v_lshl_or_b32 v2, v0, 8, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v1, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -5386,27 +5394,30 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_lshr_b32 s5, s18, 16
-; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s18
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
-; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s18
; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX9-NEXT: s_lshr_b32 s5, s19, 16
-; GFX9-NEXT: v_lshl_or_b32 v8, v1, 8, v0
-; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s19
+; GFX9-NEXT: v_or_b32_e32 v8, v0, v1
; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
-; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s19
; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: s_lshr_b32 s5, s17, 16
-; GFX9-NEXT: v_lshl_or_b32 v6, v1, 8, v0
-; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s17
+; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX9-NEXT: v_cvt_u16_f16_e32 v2, s5
+; GFX9-NEXT: v_or_b32_e32 v6, v0, v1
+; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s17
+; GFX9-NEXT: v_min_u32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: s_lshr_b32 s5, s16, 16
; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_min_u32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_cvt_u16_f16_e32 v7, s5
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v6
-; GFX9-NEXT: v_lshl_or_b32 v2, v2, 8, v0
+; GFX9-NEXT: v_or_b32_e32 v2, v0, v2
; GFX9-NEXT: v_min_u32_sdwa v7, v7, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -5436,35 +5447,38 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v5, s1
; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v6, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX11-FAKE16-NEXT: v_min_u32_e32 v7, 0xff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX11-FAKE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 8, v1
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s0
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v1, v0
; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v4, 8, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 8, v5
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v1, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v8
@@ -5484,35 +5498,38 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s1
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v6.l, s1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v7, 0xff, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX11-TRUE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v0, 8, v1
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v1, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v4, 8, v7
-; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 8, v5
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v3, v7
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v1, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v8
@@ -5537,36 +5554,39 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v5, s1
; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v6, s1
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX12-FAKE16-NEXT: v_min_u32_e32 v7, 0xff, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX12-FAKE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v8, v0, 8, v1
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s0
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, v1, v0
; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v6, v4, 8, v7
-; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 8, v5
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s0
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, v1, v4
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v8
@@ -5591,36 +5611,39 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s1
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v6.l, s1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v7, 0xff, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX12-TRUE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX12-TRUE16-NEXT: v_lshl_or_b32 v8, v0, 8, v1
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, v1, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX12-TRUE16-NEXT: v_lshl_or_b32 v6, v4, 8, v7
-; GFX12-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 8, v5
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v5, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, v3, v7
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, v1, v4
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX12-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v8
@@ -6372,14 +6395,15 @@ define <4 x i8> @test_s_unsigned_v4f32_v4i8(<4 x float> inreg %f) {
; GFX9-LABEL: test_s_unsigned_v4f32_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_u32_f32_e32 v2, s18
; GFX9-NEXT: v_cvt_u32_f32_e32 v3, s19
+; GFX9-NEXT: v_cvt_u32_f32_e32 v2, s18
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, s17
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, s16
-; GFX9-NEXT: v_min_u32_e32 v2, 0xff, v2
; GFX9-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX9-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
; GFX9-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v3, 8, v2
+; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
; GFX9-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -6398,7 +6422,8 @@ define <4 x i8> @test_s_unsigned_v4f32_v4i8(<4 x float> inreg %f) {
; GFX11-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-NEXT: v_min_u32_e32 v3, 0xff, v2
-; GFX11-NEXT: v_lshl_or_b32 v2, v0, 8, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX11-NEXT: v_or_b32_e32 v2, v1, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, s0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2
diff --git a/llvm/test/CodeGen/AMDGPU/function-args.ll b/llvm/test/CodeGen/AMDGPU/function-args.ll
index 6ebfb95856361..07dcad993ffe2 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args.ll
@@ -1049,19 +1049,34 @@ define void @void_func_v4i8(<4 x i8> %arg0) #0 {
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX89-LABEL: void_func_v4i8:
-; GFX89: ; %bb.0:
-; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX89-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX89-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX89-NEXT: v_perm_b32 v1, v2, v3, s4
-; GFX89-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX89-NEXT: s_mov_b64 s[4:5], 0
-; GFX89-NEXT: s_mov_b32 s7, 0xf000
-; GFX89-NEXT: s_mov_b32 s6, -1
-; GFX89-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GFX89-NEXT: s_waitcnt vmcnt(0)
-; GFX89-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: void_func_v4i8:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s4, 0xc0c0004
+; VI-NEXT: v_perm_b32 v0, v0, v1, s4
+; VI-NEXT: v_perm_b32 v1, v2, v3, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: s_mov_b64 s[4:5], 0
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: void_func_v4i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX9-NEXT: v_perm_b32 v1, v2, v3, s4
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: s_mov_b64 s[4:5], 0
+; GFX9-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-NEXT: s_mov_b32 s6, -1
+; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: void_func_v4i8:
; GFX11: ; %bb.0:
@@ -1101,21 +1116,38 @@ define void @void_func_v5i8(<5 x i8> %arg0) #0 {
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX89-LABEL: void_func_v5i8:
-; GFX89: ; %bb.0:
-; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX89-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX89-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX89-NEXT: v_perm_b32 v1, v2, v3, s4
-; GFX89-NEXT: s_mov_b64 s[4:5], 4
-; GFX89-NEXT: s_mov_b32 s7, 0xf000
-; GFX89-NEXT: s_mov_b32 s6, -1
-; GFX89-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX89-NEXT: buffer_store_byte v4, off, s[4:7], 0
-; GFX89-NEXT: s_mov_b64 s[4:5], 0
-; GFX89-NEXT: buffer_store_dword v0, off, s[4:7], 0
-; GFX89-NEXT: s_waitcnt vmcnt(0)
-; GFX89-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: void_func_v5i8:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s4, 0xc0c0004
+; VI-NEXT: v_perm_b32 v0, v0, v1, s4
+; VI-NEXT: v_perm_b32 v1, v2, v3, s4
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: s_mov_b64 s[4:5], 4
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
+; VI-NEXT: buffer_store_byte v4, off, s[4:7], 0
+; VI-NEXT: s_mov_b64 s[4:5], 0
+; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: void_func_v5i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX9-NEXT: v_perm_b32 v1, v2, v3, s4
+; GFX9-NEXT: s_mov_b64 s[4:5], 4
+; GFX9-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-NEXT: s_mov_b32 s6, -1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: buffer_store_byte v4, off, s[4:7], 0
+; GFX9-NEXT: s_mov_b64 s[4:5], 0
+; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: void_func_v5i8:
; GFX11: ; %bb.0:
@@ -1164,22 +1196,41 @@ define void @void_func_v8i8(<8 x i8> %arg0) #0 {
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX89-LABEL: void_func_v8i8:
-; GFX89: ; %bb.0:
-; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX89-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX89-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX89-NEXT: v_perm_b32 v5, v6, v7, s4
-; GFX89-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX89-NEXT: v_perm_b32 v1, v2, v3, s4
-; GFX89-NEXT: v_lshl_or_b32 v4, v5, 16, v4
-; GFX89-NEXT: v_lshl_or_b32 v3, v1, 16, v0
-; GFX89-NEXT: s_mov_b64 s[4:5], 0
-; GFX89-NEXT: s_mov_b32 s7, 0xf000
-; GFX89-NEXT: s_mov_b32 s6, -1
-; GFX89-NEXT: buffer_store_dwordx2 v[3:4], off, s[4:7], 0
-; GFX89-NEXT: s_waitcnt vmcnt(0)
-; GFX89-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: void_func_v8i8:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s4, 0xc0c0004
+; VI-NEXT: v_perm_b32 v4, v4, v5, s4
+; VI-NEXT: v_perm_b32 v5, v6, v7, s4
+; VI-NEXT: v_perm_b32 v0, v0, v1, s4
+; VI-NEXT: v_perm_b32 v1, v2, v3, s4
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_or_b32_e32 v3, v0, v1
+; VI-NEXT: s_mov_b64 s[4:5], 0
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: buffer_store_dwordx2 v[3:4], off, s[4:7], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: void_func_v8i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
+; GFX9-NEXT: v_perm_b32 v5, v6, v7, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX9-NEXT: v_perm_b32 v1, v2, v3, s4
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v1, 16, v0
+; GFX9-NEXT: s_mov_b64 s[4:5], 0
+; GFX9-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-NEXT: s_mov_b32 s6, -1
+; GFX9-NEXT: buffer_store_dwordx2 v[3:4], off, s[4:7], 0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: void_func_v8i8:
; GFX11: ; %bb.0:
@@ -1246,28 +1297,55 @@ define void @void_func_v16i8(<16 x i8> %arg0) #0 {
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_setpc_b64 s[30:31]
;
-; GFX89-LABEL: void_func_v16i8:
-; GFX89: ; %bb.0:
-; GFX89-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX89-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX89-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX89-NEXT: v_perm_b32 v13, v14, v15, s4
-; GFX89-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX89-NEXT: v_perm_b32 v9, v10, v11, s4
-; GFX89-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX89-NEXT: v_perm_b32 v5, v6, v7, s4
-; GFX89-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX89-NEXT: v_perm_b32 v1, v2, v3, s4
-; GFX89-NEXT: v_lshl_or_b32 v12, v13, 16, v12
-; GFX89-NEXT: v_lshl_or_b32 v11, v9, 16, v8
-; GFX89-NEXT: v_lshl_or_b32 v10, v5, 16, v4
-; GFX89-NEXT: v_lshl_or_b32 v9, v1, 16, v0
-; GFX89-NEXT: s_mov_b64 s[4:5], 0
-; GFX89-NEXT: s_mov_b32 s7, 0xf000
-; GFX89-NEXT: s_mov_b32 s6, -1
-; GFX89-NEXT: buffer_store_dwordx4 v[9:12], off, s[4:7], 0
-; GFX89-NEXT: s_waitcnt vmcnt(0)
-; GFX89-NEXT: s_setpc_b64 s[30:31]
+; VI-LABEL: void_func_v16i8:
+; VI: ; %bb.0:
+; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; VI-NEXT: s_mov_b32 s4, 0xc0c0004
+; VI-NEXT: v_perm_b32 v12, v12, v13, s4
+; VI-NEXT: v_perm_b32 v13, v14, v15, s4
+; VI-NEXT: v_perm_b32 v8, v8, v9, s4
+; VI-NEXT: v_perm_b32 v9, v10, v11, s4
+; VI-NEXT: v_perm_b32 v4, v4, v5, s4
+; VI-NEXT: v_perm_b32 v5, v6, v7, s4
+; VI-NEXT: v_perm_b32 v0, v0, v1, s4
+; VI-NEXT: v_perm_b32 v1, v2, v3, s4
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; VI-NEXT: v_or_b32_e32 v12, v12, v13
+; VI-NEXT: v_or_b32_e32 v11, v8, v9
+; VI-NEXT: v_or_b32_e32 v10, v4, v5
+; VI-NEXT: v_or_b32_e32 v9, v0, v1
+; VI-NEXT: s_mov_b64 s[4:5], 0
+; VI-NEXT: s_mov_b32 s7, 0xf000
+; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: buffer_store_dwordx4 v[9:12], off, s[4:7], 0
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: void_func_v16i8:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
+; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
+; GFX9-NEXT: v_perm_b32 v13, v14, v15, s4
+; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
+; GFX9-NEXT: v_perm_b32 v9, v10, v11, s4
+; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
+; GFX9-NEXT: v_perm_b32 v5, v6, v7, s4
+; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
+; GFX9-NEXT: v_perm_b32 v1, v2, v3, s4
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v8
+; GFX9-NEXT: v_lshl_or_b32 v10, v5, 16, v4
+; GFX9-NEXT: v_lshl_or_b32 v9, v1, 16, v0
+; GFX9-NEXT: s_mov_b64 s[4:5], 0
+; GFX9-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-NEXT: s_mov_b32 s6, -1
+; GFX9-NEXT: buffer_store_dwordx4 v[9:12], off, s[4:7], 0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: void_func_v16i8:
; GFX11-TRUE16: ; %bb.0:
@@ -1409,36 +1487,40 @@ define void @void_func_v32i8(<32 x i8> %arg0) #0 {
; VI-NEXT: v_perm_b32 v8, v8, v9, s8
; VI-NEXT: v_perm_b32 v9, v10, v11, s8
; VI-NEXT: buffer_load_ubyte v10, off, s[0:3], s32
-; VI-NEXT: v_perm_b32 v12, v12, v13, s8
-; VI-NEXT: v_perm_b32 v13, v14, v15, s8
; VI-NEXT: v_perm_b32 v0, v0, v1, s8
; VI-NEXT: v_perm_b32 v1, v2, v3, s8
; VI-NEXT: v_perm_b32 v2, v26, v27, s8
-; VI-NEXT: v_perm_b32 v3, v22, v23, s8
-; VI-NEXT: v_perm_b32 v15, v18, v19, s8
+; VI-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; VI-NEXT: v_perm_b32 v12, v12, v13, s8
+; VI-NEXT: v_perm_b32 v13, v14, v15, s8
; VI-NEXT: v_perm_b32 v4, v4, v5, s8
; VI-NEXT: v_perm_b32 v5, v6, v7, s8
+; VI-NEXT: v_perm_b32 v3, v22, v23, s8
+; VI-NEXT: v_perm_b32 v14, v16, v17, s8
+; VI-NEXT: v_perm_b32 v15, v18, v19, s8
+; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; VI-NEXT: v_or_b32_e32 v2, v8, v9
; VI-NEXT: v_perm_b32 v7, v28, v29, s8
; VI-NEXT: v_perm_b32 v6, v24, v25, s8
; VI-NEXT: v_perm_b32 v11, v20, v21, s8
-; VI-NEXT: v_perm_b32 v14, v16, v17, s8
-; VI-NEXT: v_lshlrev_b32_e32 v17, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; VI-NEXT: v_lshlrev_b32_e32 v18, 16, v3
; VI-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; VI-NEXT: v_lshl_or_b32 v2, v9, 16, v8
; VI-NEXT: s_mov_b64 s[4:5], 16
; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1
+; VI-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; VI-NEXT: v_lshlrev_b32_e32 v16, 16, v1
-; VI-NEXT: v_lshl_or_b32 v1, v5, 16, v4
+; VI-NEXT: v_or_b32_e32 v1, v4, v5
; VI-NEXT: v_or_b32_e32 v6, v6, v17
; VI-NEXT: v_or_b32_e32 v5, v11, v18
; VI-NEXT: v_or_b32_e32 v4, v14, v15
-; VI-NEXT: v_lshl_or_b32 v3, v13, 16, v12
+; VI-NEXT: v_or_b32_e32 v3, v12, v13
; VI-NEXT: v_or_b32_e32 v0, v0, v16
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_perm_b32 v8, v30, v10, s8
-; VI-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; VI-NEXT: v_or_b32_e32 v7, v7, v8
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0
; VI-NEXT: s_mov_b64 s[4:5], 0
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
index 9a6825fdae9dd..dbf99aa1c8577 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd.ll
@@ -9230,9 +9230,10 @@ define half @global_agent_atomic_fadd_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9744,9 +9745,10 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -10264,9 +10266,10 @@ define half @global_agent_atomic_fadd_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -10757,9 +10760,10 @@ define void @global_agent_atomic_fadd_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -11255,9 +11259,10 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -11759,9 +11764,10 @@ define void @global_agent_atomic_fadd_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -13034,9 +13040,10 @@ define half @global_system_atomic_fadd_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_add_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -13542,9 +13549,10 @@ define void @global_system_atomic_fadd_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_add_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
index 681519b86e88b..93443914d3f97 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmax.ll
@@ -4782,9 +4782,10 @@ define half @global_agent_atomic_fmax_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -5233,9 +5234,10 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -5689,9 +5691,10 @@ define half @global_agent_atomic_fmax_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6118,9 +6121,10 @@ define void @global_agent_atomic_fmax_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_max_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6557,9 +6561,10 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7000,9 +7005,10 @@ define void @global_agent_atomic_fmax_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8126,9 +8132,10 @@ define half @global_system_atomic_fmax_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_max_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8575,9 +8582,10 @@ define void @global_system_atomic_fmax_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_max_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
index 79704b99691b2..b8217cf862b3a 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fmin.ll
@@ -4782,9 +4782,10 @@ define half @global_agent_atomic_fmin_ret_f16__amdgpu_no_fine_grained_memory(ptr
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -5233,9 +5234,10 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gra
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -5689,9 +5691,10 @@ define half @global_agent_atomic_fmin_ret_f16__offset12b_neg__amdgpu_no_fine_gra
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6118,9 +6121,10 @@ define void @global_agent_atomic_fmin_noret_f16__amdgpu_no_fine_grained_memory(p
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_min_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6557,9 +6561,10 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_g
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7000,9 +7005,10 @@ define void @global_agent_atomic_fmin_noret_f16__offset12b_neg__amdgpu_no_fine_g
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8126,9 +8132,10 @@ define half @global_system_atomic_fmin_ret_f16__offset12b_pos__amdgpu_no_fine_gr
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
; GFX8-NEXT: v_max_f16_e32 v5, v5, v5
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_min_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8575,9 +8582,10 @@ define void @global_system_atomic_fmin_noret_f16__offset12b_pos__amdgpu_no_fine_
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v2, v4, v3
; GFX8-NEXT: v_max_f16_e32 v2, v2, v2
-; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
; GFX8-NEXT: v_min_f16_e32 v2, v2, v6
-; GFX8-NEXT: v_lshl_or_b32 v2, v2, v4, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v3, v5
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, v4, v2
+; GFX8-NEXT: v_or_b32_e32 v2, v7, v2
; GFX8-NEXT: flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
index 16ded66cf0106..4ab68e8822676 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fsub.ll
@@ -5514,9 +5514,10 @@ define half @global_agent_atomic_fsub_ret_f16(ptr addrspace(1) %ptr, half %val)
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -5940,9 +5941,10 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %p
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6371,9 +6373,10 @@ define half @global_agent_atomic_fsub_ret_f16__offset12b_neg(ptr addrspace(1) %p
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -6780,9 +6783,10 @@ define void @global_agent_atomic_fsub_noret_f16(ptr addrspace(1) %ptr, half %val
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7194,9 +7198,10 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -7612,9 +7617,10 @@ define void @global_agent_atomic_fsub_noret_f16__offset12b_neg(ptr addrspace(1)
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -8673,9 +8679,10 @@ define half @global_system_atomic_fsub_ret_f16__offset12b_pos(ptr addrspace(1) %
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v6, v5
; GFX8-NEXT: v_lshrrev_b32_e32 v5, v3, v6
-; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
; GFX8-NEXT: v_sub_f16_e32 v5, v5, v2
-; GFX8-NEXT: v_lshl_or_b32 v5, v5, v3, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v6, v4
+; GFX8-NEXT: v_lshlrev_b32_e32 v5, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v5, v7, v5
; GFX8-NEXT: flat_atomic_cmpswap v5, v[0:1], v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
@@ -9097,9 +9104,10 @@ define void @global_system_atomic_fsub_noret_f16__offset12b_pos(ptr addrspace(1)
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v5, v4
-; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
; GFX8-NEXT: v_sub_f16_e32 v3, v3, v2
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v5, v7
+; GFX8-NEXT: v_and_b32_e32 v7, v4, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v5, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v7, v3
; GFX8-NEXT: flat_atomic_cmpswap v3, v[0:1], v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: buffer_wbinvl1
diff --git a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
index a3499833115ef..a6bcafd0361ff 100644
--- a/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-load-xcnt.ll
@@ -23,7 +23,9 @@ define void @test_i8load_v4i8store(ptr addrspace(1) %ptr_a, ptr addrspace(1) %pt
; GCN-SDAG-FAKE16-NEXT: v_perm_b32 v1, v10, v7, 0xc0c0004
; GCN-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GCN-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v6, v0
-; GCN-SDAG-FAKE16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GCN-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-SDAG-FAKE16-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-SDAG-FAKE16-NEXT: global_store_b32 v[8:9], v0, off
; GCN-SDAG-FAKE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -59,7 +61,9 @@ define void @test_i8load_v4i8store(ptr addrspace(1) %ptr_a, ptr addrspace(1) %pt
; GCN-SDAG-REAL16-NEXT: v_perm_b32 v1, v10, v7, 0xc0c0004
; GCN-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GCN-SDAG-REAL16-NEXT: v_or_b16 v0.l, v6.l, v0.l
-; GCN-SDAG-REAL16-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GCN-SDAG-REAL16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GCN-SDAG-REAL16-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-SDAG-REAL16-NEXT: global_store_b32 v[8:9], v0, off
; GCN-SDAG-REAL16-NEXT: s_set_pc_i64 s[30:31]
%a = load i8, ptr addrspace(1) %ptr_a
diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll
index bddcd2ff4e329..b67c40b2d8333 100644
--- a/llvm/test/CodeGen/AMDGPU/idot4u.ll
+++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll
@@ -2759,13 +2759,14 @@ define amdgpu_kernel void @udot4_acc8_vecMul(ptr addrspace(1) %src1,
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-DL-FAKE16-NEXT: v_or_b32_e32 v6, v6, v5
; GFX11-DL-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
+; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-DL-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-DL-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-DL-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 16, v8
; GFX11-DL-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 8, v6
-; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-DL-FAKE16-NEXT: v_add_nc_u16 v0, v0, v6
+; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-DL-FAKE16-NEXT: v_mad_u16 v0, v4, v7, v0
-; GFX11-DL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-DL-FAKE16-NEXT: v_add_nc_u16 v0, v0, v1
; GFX11-DL-FAKE16-NEXT: global_store_b8 v2, v0, s[4:5]
; GFX11-DL-FAKE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
index 96dd8bd52dbf3..3ef7238576a65 100644
--- a/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
+++ b/llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll
@@ -720,16 +720,17 @@ define <2 x i16> @clpeak_imad_pat_v2i16(<2 x i16> %x, <2 x i16> %y) {
; GFX8-SDAG-NEXT: v_add_u16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v0, v3
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v2, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, v0
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v2, v1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v2, v1, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v3
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v2, v1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v0, v4, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v1, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v2
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v3
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_imad_pat_v2i16:
@@ -958,21 +959,22 @@ define <3 x i16> @clpeak_imad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) {
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-SDAG-NEXT: v_add_u16_e32 v1, 1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v6, v0, v5
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v8, v4, v2
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v5, v0
-; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v2, v4
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v3
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v8, v4, v2
+; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v2, v4
; GFX8-SDAG-NEXT: v_mad_u16 v1, v1, v3, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v5
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v4, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v3
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v4, v2
; GFX8-SDAG-NEXT: v_mad_u16 v3, v0, v6, v0
; GFX8-SDAG-NEXT: v_mad_u16 v4, v2, v8, v2
-; GFX8-SDAG-NEXT: v_mad_u16 v5, v1, v7, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v3, v0, v3
+; GFX8-SDAG-NEXT: v_mad_u16 v5, v1, v7, v1
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-SDAG-NEXT: v_mad_u16 v2, v4, v2, v4
; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, v5
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_imad_pat_v3i16:
@@ -1478,34 +1480,36 @@ define <4 x i16> @clpeak_imad_pat_v4i16(<4 x i16> %x, <4 x i16> %y) {
; GFX8-SDAG: ; %bb.0: ; %entry
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_mov_b32_e32 v6, 1
-; GFX8-SDAG-NEXT: v_add_u16_e32 v4, 1, v1
; GFX8-SDAG-NEXT: v_add_u16_e32 v5, 1, v0
; GFX8-SDAG-NEXT: v_add_u16_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; GFX8-SDAG-NEXT: v_add_u16_e32 v4, 1, v1
; GFX8-SDAG-NEXT: v_add_u16_sdwa v1, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v6
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v9, v0, v8
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v10, v5, v2
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v8, v0
-; GFX8-SDAG-NEXT: v_mad_u16 v1, v1, v6, v1
-; GFX8-SDAG-NEXT: v_mad_u16 v5, v5, v2, v5
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v6
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v10, v5, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v11, v4, v3
+; GFX8-SDAG-NEXT: v_mad_u16 v1, v1, v6, v1
; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v3, v4
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v6
+; GFX8-SDAG-NEXT: v_mad_u16 v5, v5, v2, v5
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v8
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v6
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v5, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v3, v4, v3
; GFX8-SDAG-NEXT: v_mad_u16 v4, v0, v9, v0
; GFX8-SDAG-NEXT: v_mad_u16 v5, v1, v7, v1
; GFX8-SDAG-NEXT: v_mad_u16 v7, v2, v10, v2
-; GFX8-SDAG-NEXT: v_mad_u16 v6, v3, v11, v3
; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, v4
-; GFX8-SDAG-NEXT: v_mad_u16 v2, v7, v2, v7
+; GFX8-SDAG-NEXT: v_mad_u16 v6, v3, v11, v3
; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, v5
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-SDAG-NEXT: v_mad_u16 v2, v7, v2, v7
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v6, v3, v6
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX8-SDAG-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_imad_pat_v4i16:
@@ -2237,16 +2241,17 @@ define <2 x i16> @clpeak_umad_pat_v2i16(<2 x i16> %x, <2 x i16> %y) {
; GFX8-SDAG-NEXT: v_add_u16_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v0, v3
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v2, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, v0
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v2, v1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v2, v1, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v3
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v2, v1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v0, v4, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v1, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v2
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v3
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_umad_pat_v2i16:
@@ -2475,21 +2480,22 @@ define <3 x i16> @clpeak_umad_pat_v3i16(<3 x i16> %x, <3 x i16> %y) {
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX8-SDAG-NEXT: v_add_u16_e32 v1, 1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v6, v0, v5
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v8, v4, v2
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v5, v0
-; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v2, v4
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v3
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v8, v4, v2
+; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v2, v4
; GFX8-SDAG-NEXT: v_mad_u16 v1, v1, v3, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v5
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v4, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v3
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v4, v2
; GFX8-SDAG-NEXT: v_mad_u16 v3, v0, v6, v0
; GFX8-SDAG-NEXT: v_mad_u16 v4, v2, v8, v2
-; GFX8-SDAG-NEXT: v_mad_u16 v5, v1, v7, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v3, v0, v3
+; GFX8-SDAG-NEXT: v_mad_u16 v5, v1, v7, v1
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-SDAG-NEXT: v_mad_u16 v2, v4, v2, v4
; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, v5
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_umad_pat_v3i16:
@@ -2995,34 +3001,36 @@ define <4 x i16> @clpeak_umad_pat_v4i16(<4 x i16> %x, <4 x i16> %y) {
; GFX8-SDAG: ; %bb.0: ; %entry
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_mov_b32_e32 v6, 1
-; GFX8-SDAG-NEXT: v_add_u16_e32 v4, 1, v1
; GFX8-SDAG-NEXT: v_add_u16_e32 v5, 1, v0
; GFX8-SDAG-NEXT: v_add_u16_sdwa v0, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
+; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v8, 16, v2
+; GFX8-SDAG-NEXT: v_add_u16_e32 v4, 1, v1
; GFX8-SDAG-NEXT: v_add_u16_sdwa v1, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v8, 16, v2
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v6
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v9, v0, v8
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v10, v5, v2
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v8, v0
-; GFX8-SDAG-NEXT: v_mad_u16 v1, v1, v6, v1
-; GFX8-SDAG-NEXT: v_mad_u16 v5, v5, v2, v5
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v7, v1, v6
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v10, v5, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v11, v4, v3
+; GFX8-SDAG-NEXT: v_mad_u16 v1, v1, v6, v1
; GFX8-SDAG-NEXT: v_mad_u16 v4, v4, v3, v4
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v6
+; GFX8-SDAG-NEXT: v_mad_u16 v5, v5, v2, v5
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v8
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v6
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v5, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v3, v4, v3
; GFX8-SDAG-NEXT: v_mad_u16 v4, v0, v9, v0
; GFX8-SDAG-NEXT: v_mad_u16 v5, v1, v7, v1
; GFX8-SDAG-NEXT: v_mad_u16 v7, v2, v10, v2
-; GFX8-SDAG-NEXT: v_mad_u16 v6, v3, v11, v3
; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, v4
-; GFX8-SDAG-NEXT: v_mad_u16 v2, v7, v2, v7
+; GFX8-SDAG-NEXT: v_mad_u16 v6, v3, v11, v3
; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, v5
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-SDAG-NEXT: v_mad_u16 v2, v7, v2, v7
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v6, v3, v6
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX8-SDAG-NEXT: v_or_b32_e32 v1, v2, v1
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_umad_pat_v4i16:
@@ -10974,26 +10982,27 @@ define <2 x i16> @clpeak_imad_pat_v2i16_x2(<2 x i16> %x, <2 x i16> %y) {
; GFX8-SDAG-NEXT: v_mad_u16 v4, v0, v3, v0
; GFX8-SDAG-NEXT: v_mad_u16 v5, v2, v1, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v4, v3
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, 1
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v1, v2, v1, 1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v4, v0, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v5, v1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v2, v4
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v3, v3, v5
; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, 1
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v3, v3, v5
; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, 1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v2, v0
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v3, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v0
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v3, v1
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; GFX8-SDAG-NEXT: v_mad_u16 v2, v0, v4, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v1, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v2
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v3
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_imad_pat_v2i16_x2:
@@ -11322,26 +11331,27 @@ define <2 x i16> @clpeak_umad_pat_v2i16_x2(<2 x i16> %x, <2 x i16> %y) {
; GFX8-SDAG-NEXT: v_mad_u16 v4, v0, v3, v0
; GFX8-SDAG-NEXT: v_mad_u16 v5, v2, v1, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v4, v3
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v3, 1
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v1, v2, v1, 1
; GFX8-SDAG-NEXT: v_mad_u16 v2, v4, v0, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v5, v1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v2, v2, v4
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v3, v3, v5
; GFX8-SDAG-NEXT: v_mad_u16 v0, v4, v0, 1
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v3, v3, v5
; GFX8-SDAG-NEXT: v_mad_u16 v1, v5, v1, 1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v4, v2, v0
-; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v3, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v0
+; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v5, v3, v1
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v1
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v0, v0, v2
; GFX8-SDAG-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; GFX8-SDAG-NEXT: v_mad_u16 v2, v0, v4, v0
; GFX8-SDAG-NEXT: v_mad_u16 v3, v1, v5, v1
; GFX8-SDAG-NEXT: v_mad_u16 v0, v2, v0, v2
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX8-SDAG-NEXT: v_mad_u16 v1, v3, v1, v3
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: clpeak_umad_pat_v2i16_x2:
@@ -11608,7 +11618,8 @@ define <2 x i16> @multi_use_mul_mad_i16_var(i16 %x, i16 %y, i16 %z0, i16 %z1) {
; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-SDAG-NEXT: v_mad_u16 v3, v0, v1, v3
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v1, v2
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-GISEL-LABEL: multi_use_mul_mad_i16_var:
@@ -11616,7 +11627,8 @@ define <2 x i16> @multi_use_mul_mad_i16_var(i16 %x, i16 %y, i16 %z0, i16 %z1) {
; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-GISEL-NEXT: v_mad_u16 v2, v0, v1, v2
; GFX8-GISEL-NEXT: v_mad_u16 v0, v0, v1, v3
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v2, v0
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: multi_use_mul_mad_i16_var:
@@ -12089,12 +12101,14 @@ define <4 x i16> @multi_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX8-SDAG-NEXT: v_mad_u16 v6, v5, v4, v6
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX8-SDAG-NEXT: v_mad_u16 v2, v0, v1, v2
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v2, v6, 16, v2
+; GFX8-SDAG-NEXT: v_or_b32_e32 v2, v2, v6
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GFX8-SDAG-NEXT: v_mad_u16 v4, v5, v4, v6
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v1, v3
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v1, v4, 16, v0
+; GFX8-SDAG-NEXT: v_or_b32_e32 v1, v0, v4
; GFX8-SDAG-NEXT: v_mov_b32_e32 v0, v2
; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
;
@@ -12104,13 +12118,15 @@ define <4 x i16> @multi_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX8-GISEL-NEXT: v_mad_u16 v2, v0, v1, v2
; GFX8-GISEL-NEXT: v_mad_u16 v6, v4, v5, v6
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v2, v6, 16, v2
+; GFX8-GISEL-NEXT: v_mad_u16 v2, v0, v1, v2
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX8-GISEL-NEXT: v_or_b32_e32 v2, v2, v6
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v3
; GFX8-GISEL-NEXT: v_mad_u16 v0, v0, v1, v3
; GFX8-GISEL-NEXT: v_mad_u16 v1, v4, v5, v6
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v1, v1, 16, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v0, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v2
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
@@ -12228,8 +12244,9 @@ define <2 x i16> @other_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
; GFX8-SDAG-NEXT: v_or_b32_e32 v6, v7, v6
; GFX8-SDAG-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX8-SDAG-NEXT: v_mad_u16 v4, v5, v4, v7
+; GFX8-SDAG-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX8-SDAG-NEXT: v_mad_u16 v0, v0, v1, v2
-; GFX8-SDAG-NEXT: v_lshl_or_b32 v0, v4, 16, v0
+; GFX8-SDAG-NEXT: v_or_b32_e32 v0, v0, v4
; GFX8-SDAG-NEXT: s_mov_b32 m0, -1
; GFX8-SDAG-NEXT: ds_write_b32 v3, v6
; GFX8-SDAG-NEXT: s_waitcnt lgkmcnt(0)
@@ -12246,7 +12263,8 @@ define <2 x i16> @other_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX8-GISEL-NEXT: v_mad_u16 v0, v0, v1, v2
; GFX8-GISEL-NEXT: v_mad_u16 v1, v4, v5, v7
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_mov_b32 m0, -1
; GFX8-GISEL-NEXT: ds_write_b32 v3, v6
; GFX8-GISEL-NEXT: s_waitcnt lgkmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
index d7cfa46a0d6ef..c46bd6c7687c2 100644
--- a/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
+++ b/llvm/test/CodeGen/AMDGPU/itofp.i128.ll
@@ -640,9 +640,10 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: v_and_or_b32 v0, v0, 1, v4
; SDAG-NEXT: v_add_co_u32_e32 v4, vcc, 1, v0
; SDAG-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
-; SDAG-NEXT: v_lshrrev_b64 v[0:1], 2, v[4:5]
; SDAG-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
-; SDAG-NEXT: v_lshl_or_b32 v10, v6, 30, v1
+; SDAG-NEXT: v_lshrrev_b64 v[0:1], 2, v[4:5]
+; SDAG-NEXT: v_lshlrev_b32_e32 v7, 30, v6
+; SDAG-NEXT: v_or_b32_e32 v10, v1, v7
; SDAG-NEXT: v_and_b32_e32 v1, 0x800000, v5
; SDAG-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; SDAG-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -671,8 +672,9 @@ define double @sitofp_i128_to_f64(i128 %x) {
; SDAG-NEXT: s_branch .LBB2_2
; SDAG-NEXT: .LBB2_14: ; %itofp-if-then20
; SDAG-NEXT: v_lshrrev_b64 v[0:1], 3, v[4:5]
+; SDAG-NEXT: v_lshlrev_b32_e32 v4, 29, v6
+; SDAG-NEXT: v_or_b32_e32 v10, v1, v4
; SDAG-NEXT: v_mov_b32_e32 v8, v2
-; SDAG-NEXT: v_lshl_or_b32 v10, v6, 29, v1
; SDAG-NEXT: s_branch .LBB2_10
;
; GISEL-LABEL: sitofp_i128_to_f64:
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-args.ll b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
index d4f4f66fb4077..ea0a8cbe663fd 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-args.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-args.ll
@@ -5201,7 +5201,8 @@ define amdgpu_kernel void @packed_struct_argument_alignment(<{i32, i64}> %arg0,
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_store_dwordx2 v[2:3], v[4:5]
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshl_or_b32 v4, v8, 8, v9
+; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v8
+; VI-NEXT: v_or_b32_e32 v4, v4, v9
; VI-NEXT: v_lshlrev_b32_e32 v5, 8, v10
; VI-NEXT: v_or_b32_sdwa v5, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v4, v5, v4
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
index 345de7ba1b2b7..3fbba4848703f 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.bpermute.ll
@@ -147,7 +147,8 @@ define void @ds_bpermute_or_shl(ptr addrspace(1) %out, i32 %base_index, i32 %src
; CHECK-GISEL: ; %bb.0:
; CHECK-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-GISEL-NEXT: v_and_b32_e32 v2, 62, v2
-; CHECK-GISEL-NEXT: v_lshl_or_b32 v2, v2, 2, 4
+; CHECK-GISEL-NEXT: v_lshlrev_b32_e32 v2, 2, v2
+; CHECK-GISEL-NEXT: v_or_b32_e32 v2, 4, v2
; CHECK-GISEL-NEXT: ds_bpermute_b32 v2, v2, v3
; CHECK-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; CHECK-GISEL-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
index 47b6a09a70650..e8bf198f89855 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll
@@ -702,8 +702,9 @@ define amdgpu_kernel void @fma_v2f16(
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; VI-NEXT: v_fma_f16 v3, v5, v4, v3
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-NEXT: v_fma_f16 v0, v2, v1, v0
-; VI-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v3
; VI-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-NEXT: s_endpgm
;
@@ -893,8 +894,9 @@ define amdgpu_kernel void @fma_v2f16_imm_a(
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_fma_f16 v2, v3, s2, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_fma_f16 v0, v1, s2, v0
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm
;
@@ -1077,8 +1079,9 @@ define amdgpu_kernel void @fma_v2f16_imm_b(
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_fma_f16 v2, v3, s2, v2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_fma_f16 v0, v1, s2, v0
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm
;
@@ -1261,8 +1264,9 @@ define amdgpu_kernel void @fma_v2f16_imm_c(
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-NEXT: v_fma_f16 v2, v3, v2, s2
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_fma_f16 v0, v1, v0, s2
-; VI-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm
;
@@ -1571,8 +1575,10 @@ define amdgpu_kernel void @fma_v4f16(
; VI-NEXT: v_fma_f16 v0, v4, v2, v0
; VI-NEXT: v_fma_f16 v2, v8, v7, v6
; VI-NEXT: v_fma_f16 v3, v9, v5, v3
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; VI-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v1, v2
+; VI-NEXT: v_or_b32_e32 v0, v0, v3
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
index c84221b6d3afd..146956c5908ea 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll
@@ -840,8 +840,9 @@ define amdgpu_kernel void @fmuladd_v2f16(
; VI-FLUSH-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; VI-FLUSH-NEXT: s_waitcnt vmcnt(0)
; VI-FLUSH-NEXT: v_mac_f16_sdwa v3, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; VI-FLUSH-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-FLUSH-NEXT: v_mac_f16_e32 v1, v0, v2
-; VI-FLUSH-NEXT: v_lshl_or_b32 v0, v3, 16, v1
+; VI-FLUSH-NEXT: v_or_b32_e32 v0, v1, v3
; VI-FLUSH-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-FLUSH-NEXT: s_endpgm
;
@@ -875,8 +876,9 @@ define amdgpu_kernel void @fmuladd_v2f16(
; VI-DENORM-NEXT: s_waitcnt vmcnt(0)
; VI-DENORM-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; VI-DENORM-NEXT: v_fma_f16 v3, v5, v4, v3
+; VI-DENORM-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; VI-DENORM-NEXT: v_fma_f16 v0, v2, v1, v0
-; VI-DENORM-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; VI-DENORM-NEXT: v_or_b32_e32 v0, v0, v3
; VI-DENORM-NEXT: buffer_store_dword v0, off, s[8:11], 0
; VI-DENORM-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
index 840a1df32c3a9..9e0870ad62358 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
@@ -703,21 +703,36 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GCN-NOHSA-VI-NEXT: flat_load_ushort v21, v[4:5]
; GCN-NOHSA-VI-NEXT: flat_load_ushort v22, v[6:7]
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(14)
-; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v3, v16, 16, v17
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v3, v17, v1
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(13)
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(12)
-; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v2, v18, 16, v19
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v2, v19, v1
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(11)
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v8
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(10)
-; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v1, v8, 16, v9
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v1, v9, v1
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(9)
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v4, 16, v10
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(8)
-; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v7, v10, 16, v11
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v7, v11, v4
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(7)
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v4, 16, v12
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(6)
-; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v6, v12, 16, v13
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v6, v13, v4
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(5)
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v4, 16, v14
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(4)
-; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v5, v14, 16, v15
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v5, v15, v4
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(2)
-; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v4, v0, 16, v20
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v4, v20, v0
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v21
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v0, v21, 16, v22
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v0, v22, v0
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
index b0cc4db127994..33defc2ecf6a9 100644
--- a/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-global-i16.ll
@@ -729,6 +729,9 @@ define amdgpu_kernel void @global_load_v16i16_align2(ptr addrspace(1) %in, ptr a
; GCN-NOHSA-VI-NEXT: buffer_load_ushort v15, off, s[4:7], 0 offset:16
; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s2
; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s3
+; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(14)
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(13)
; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v16, 16, v2
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(12)
@@ -742,9 +745,9 @@ define amdgpu_kernel void @global_load_v16i16_align2(ptr addrspace(1) %in, ptr a
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(8)
; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v19, 16, v7
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(7)
-; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v3, v0, 16, v8
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v3, v8, v0
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(6)
-; GCN-NOHSA-VI-NEXT: v_lshl_or_b32 v2, v1, 16, v9
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v2, v9, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(5)
; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v1, v10, v16
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(4)
diff --git a/llvm/test/CodeGen/AMDGPU/load-hi16.ll b/llvm/test/CodeGen/AMDGPU/load-hi16.ll
index e856dc9fc0ba2..91ed52b564d15 100644
--- a/llvm/test/CodeGen/AMDGPU/load-hi16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-hi16.ll
@@ -109,8 +109,9 @@ define <2 x i16> @load_local_lo_hi_v2i16_multi_use_hi(ptr addrspace(3) noalias %
; GFX803-NEXT: v_mov_b32_e32 v2, 0
; GFX803-NEXT: s_waitcnt lgkmcnt(1)
; GFX803-NEXT: ds_write_b16 v2, v1
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(1)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
@@ -2255,7 +2256,8 @@ define <2 x i16> @load_local_v2i16_split_multi_chain(ptr addrspace(3) %in) #0 {
; GFX803-NEXT: ds_read_u16 v1, v0
; GFX803-NEXT: ds_read_u16 v0, v0 offset:2
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_v2i16_split_multi_chain:
@@ -2303,8 +2305,10 @@ define <2 x i16> @load_local_lo_hi_v2i16_samechain(ptr addrspace(3) %in) #0 {
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v1, v0 offset:16
; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: s_waitcnt lgkmcnt(1)
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_lo_hi_v2i16_samechain:
@@ -2351,7 +2355,8 @@ define <2 x i16> @load_local_v2i16_broadcast(ptr addrspace(3) %in) #0 {
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v0, v0
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_v2i16_broadcast:
@@ -2404,7 +2409,8 @@ define <2 x i16> @load_local_lo_hi_v2i16_side_effect(ptr addrspace(3) %in, ptr a
; GFX803-NEXT: ds_write_b16 v1, v3
; GFX803-NEXT: ds_read_u16 v0, v0 offset:16
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v2
+; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v2, v0
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_lo_hi_v2i16_side_effect:
@@ -2460,7 +2466,8 @@ define <2 x i16> @load_global_v2i16_split(ptr addrspace(1) %in) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: flat_load_ushort v1, v[2:3] glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_global_v2i16_split:
@@ -2514,7 +2521,8 @@ define <2 x i16> @load_flat_v2i16_split(ptr %in) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: flat_load_ushort v1, v[2:3] glc
; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_flat_v2i16_split:
@@ -2565,7 +2573,8 @@ define <2 x i16> @load_constant_v2i16_split(ptr addrspace(4) %in) #0 {
; GFX803-NEXT: flat_load_ushort v0, v[0:1] glc
; GFX803-NEXT: flat_load_ushort v1, v[2:3] glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_constant_v2i16_split:
@@ -2616,7 +2625,8 @@ define <2 x i16> @load_private_v2i16_split(ptr addrspace(5) byval(i16) %in) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:2 glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_private_v2i16_split:
diff --git a/llvm/test/CodeGen/AMDGPU/load-lo16.ll b/llvm/test/CodeGen/AMDGPU/load-lo16.ll
index 485adc5c5a758..311ce242926a9 100644
--- a/llvm/test/CodeGen/AMDGPU/load-lo16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-lo16.ll
@@ -56,8 +56,9 @@ define <2 x i16> @load_local_lo_v2i16_reglo(ptr addrspace(3) %in, i16 %reg) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-FLATSCR-LABEL: load_local_lo_v2i16_reglo:
@@ -104,8 +105,9 @@ define void @load_local_lo_v2i16_reglo_vreg(ptr addrspace(3) %in, i16 %reg) #0 {
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -261,8 +263,9 @@ define void @load_local_lo_v2f16_reglo_vreg(ptr addrspace(3) %in, half %reg) #0
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u16 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -354,8 +357,9 @@ define void @load_local_lo_v2i16_reglo_vreg_zexti8(ptr addrspace(3) %in, i16 %re
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u8 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -502,8 +506,9 @@ define void @load_local_lo_v2f16_reglo_vreg_zexti8(ptr addrspace(3) %in, half %r
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: s_mov_b32 m0, -1
; GFX803-NEXT: ds_read_u8 v0, v0
+; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX803-NEXT: s_waitcnt lgkmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
@@ -1338,8 +1343,9 @@ define void @load_private_lo_v2i16_reghi_vreg(ptr addrspace(5) byval(i16) %in, i
; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
+; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
index 72f1ab0b6fb82..b0da72184f050 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
@@ -1532,9 +1532,10 @@ define half @local_atomic_fadd_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
; GFX8-NEXT: v_add_f16_e32 v3, 4.0, v3
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -1923,9 +1924,10 @@ define half @local_atomic_fadd_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
; GFX8-NEXT: v_add_f16_e32 v3, 4.0, v3
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -2295,9 +2297,10 @@ define void @local_atomic_fadd_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v0, v3
-; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
; GFX8-NEXT: v_add_f16_e32 v4, 4.0, v4
-; GFX8-NEXT: v_lshl_or_b32 v4, v4, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, v0, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
@@ -2673,9 +2676,10 @@ define void @local_atomic_fadd_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v1, v3
-; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
; GFX8-NEXT: v_add_f16_e32 v4, 4.0, v4
-; GFX8-NEXT: v_lshl_or_b32 v4, v4, v1, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, v1, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
index ba446c13cd2e4..43d77d0afa8c6 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmax.ll
@@ -1073,9 +1073,10 @@ define half @local_atomic_fmax_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
; GFX8-NEXT: v_max_f16_e32 v3, 4.0, v3
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -1475,9 +1476,10 @@ define half @local_atomic_fmax_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
; GFX8-NEXT: v_max_f16_e32 v3, 4.0, v3
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -1858,9 +1860,10 @@ define void @local_atomic_fmax_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v0, v3
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
-; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
; GFX8-NEXT: v_max_f16_e32 v4, 4.0, v4
-; GFX8-NEXT: v_lshl_or_b32 v4, v4, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, v0, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
@@ -2247,9 +2250,10 @@ define void @local_atomic_fmax_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
-; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
; GFX8-NEXT: v_max_f16_e32 v4, 4.0, v4
-; GFX8-NEXT: v_lshl_or_b32 v4, v4, v1, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, v1, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
index 2e4339b30d9e6..1759a212c6ea3 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fmin.ll
@@ -1073,9 +1073,10 @@ define half @local_atomic_fmin_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
; GFX8-NEXT: v_min_f16_e32 v3, 4.0, v3
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -1475,9 +1476,10 @@ define half @local_atomic_fmin_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
; GFX8-NEXT: v_max_f16_e32 v3, v3, v3
-; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
; GFX8-NEXT: v_min_f16_e32 v3, 4.0, v3
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -1858,9 +1860,10 @@ define void @local_atomic_fmin_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v0, v3
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
-; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
; GFX8-NEXT: v_min_f16_e32 v4, 4.0, v4
-; GFX8-NEXT: v_lshl_or_b32 v4, v4, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, v0, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
@@ -2247,9 +2250,10 @@ define void @local_atomic_fmin_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v1, v3
; GFX8-NEXT: v_max_f16_e32 v4, v4, v4
-; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
; GFX8-NEXT: v_min_f16_e32 v4, 4.0, v4
-; GFX8-NEXT: v_lshl_or_b32 v4, v4, v1, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, v1, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
index 1d46b5536a2fa..5feb76edf3d17 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fsub.ll
@@ -1994,9 +1994,10 @@ define half @local_atomic_fsub_ret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
; GFX8-NEXT: v_add_f16_e32 v3, -4.0, v3
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -2385,9 +2386,10 @@ define half @local_atomic_fsub_ret_f16__offset(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v4, v3
; GFX8-NEXT: v_lshrrev_b32_e32 v3, v0, v4
-; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
; GFX8-NEXT: v_add_f16_e32 v3, -4.0, v3
-; GFX8-NEXT: v_lshl_or_b32 v3, v3, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v4, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, v0, v3
+; GFX8-NEXT: v_or_b32_e32 v3, v5, v3
; GFX8-NEXT: ds_cmpst_rtn_b32 v3, v1, v4, v3
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v3, v4
@@ -2757,9 +2759,10 @@ define void @local_atomic_fsub_noret_f16(ptr addrspace(3) %ptr) nounwind {
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v0, v3
-; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
; GFX8-NEXT: v_add_f16_e32 v4, -4.0, v4
-; GFX8-NEXT: v_lshl_or_b32 v4, v4, v0, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, v0, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
@@ -3135,9 +3138,10 @@ define void @local_atomic_fsub_noret_f16__offset(ptr addrspace(3) %ptr) nounwind
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v4, v1, v3
-; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
; GFX8-NEXT: v_add_f16_e32 v4, -4.0, v4
-; GFX8-NEXT: v_lshl_or_b32 v4, v4, v1, v5
+; GFX8-NEXT: v_and_b32_e32 v5, v3, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v4, v1, v4
+; GFX8-NEXT: v_or_b32_e32 v4, v5, v4
; GFX8-NEXT: ds_cmpst_rtn_b32 v4, v0, v3, v4
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
index c58bdd75e5cdc..4b658de512f81 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
@@ -469,27 +469,28 @@ define protected amdgpu_kernel void @kernel_round1(ptr addrspace(1) nocapture no
; CHECK-NEXT: s_xor_b32 s4, exec_lo, s4
; CHECK-NEXT: s_cbranch_execz .LBB0_31
; CHECK-NEXT: ; %bb.30: ; in Loop: Header=BB0_28 Depth=1
-; CHECK-NEXT: v_mad_u64_u32 v[7:8], null, 0x180, v73, s[66:67]
; CHECK-NEXT: v_xor_b32_e32 v5, v60, v58
-; CHECK-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; CHECK-NEXT: v_lshrrev_b64 v[3:4], 16, v[45:46]
+; CHECK-NEXT: v_mad_u64_u32 v[7:8], null, 0x180, v73, s[66:67]
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 5, v0
; CHECK-NEXT: v_lshrrev_b64 v[1:2], 16, v[56:57]
+; CHECK-NEXT: v_lshlrev_b32_e32 v10, 16, v5
; CHECK-NEXT: v_lshlrev_b32_e32 v9, 6, v72
; CHECK-NEXT: v_lshlrev_b32_e32 v11, 12, v63
; CHECK-NEXT: v_xor_b32_e32 v6, v61, v59
-; CHECK-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; CHECK-NEXT: ; implicit-def: $vgpr42
+; CHECK-NEXT: ; implicit-def: $vgpr43
+; CHECK-NEXT: ; implicit-def: $vgpr44
; CHECK-NEXT: v_add_co_u32 v7, vcc_lo, v7, v0
+; CHECK-NEXT: v_or_b32_e32 v4, v10, v4
+; CHECK-NEXT: v_lshlrev_b32_e32 v10, 16, v45
; CHECK-NEXT: v_or3_b32 v9, v9, v11, v62
; CHECK-NEXT: v_add_co_ci_u32_e64 v8, null, 0, v8, vcc_lo
; CHECK-NEXT: v_lshrrev_b64 v[5:6], 16, v[5:6]
-; CHECK-NEXT: v_or_b32_e32 v4, v10, v4
-; CHECK-NEXT: v_lshl_or_b32 v2, v45, 16, v2
+; CHECK-NEXT: v_or_b32_e32 v2, v10, v2
; CHECK-NEXT: global_store_dword v[7:8], v9, off offset:4
; CHECK-NEXT: global_store_dwordx4 v[7:8], v[1:4], off offset:8
; CHECK-NEXT: global_store_dwordx2 v[7:8], v[5:6], off offset:24
-; CHECK-NEXT: ; implicit-def: $vgpr42
-; CHECK-NEXT: ; implicit-def: $vgpr43
-; CHECK-NEXT: ; implicit-def: $vgpr44
; CHECK-NEXT: .LBB0_31: ; %Flow
; CHECK-NEXT: ; in Loop: Header=BB0_28 Depth=1
; CHECK-NEXT: s_andn2_saveexec_b32 s4, s4
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
index 60b206ba91589..30ad3be46053c 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
@@ -19,15 +19,19 @@ define amdgpu_kernel void @ctlz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
+; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v6
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 8, v7
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
@@ -53,20 +57,23 @@ define amdgpu_kernel void @ctlz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3]
; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:4
+; GFX10-NEXT: s_waitcnt vmcnt(7)
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX10-NEXT: s_waitcnt vmcnt(4)
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; GFX10-NEXT: s_waitcnt vmcnt(2)
-; GFX10-NEXT: v_lshl_or_b32 v4, v4, 8, v6
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v8
-; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v8
+; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
; GFX10-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX10-NEXT: v_ffbh_u32_e32 v0, v0
+; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
; GFX10-NEXT: v_ffbh_u32_e32 v2, v3
+; GFX10-NEXT: v_ffbh_u32_e32 v0, v0
; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, 32 clamp
; GFX10-NEXT: v_min_u32_e32 v0, v2, v0
; GFX10-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
@@ -91,15 +98,19 @@ define amdgpu_kernel void @ctlz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
+; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v6
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 8, v7
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
@@ -126,20 +137,23 @@ define amdgpu_kernel void @ctlz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3]
; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:4
+; GFX10-NEXT: s_waitcnt vmcnt(7)
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(5)
; GFX10-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX10-NEXT: s_waitcnt vmcnt(4)
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; GFX10-NEXT: s_waitcnt vmcnt(2)
-; GFX10-NEXT: v_lshl_or_b32 v4, v4, 8, v6
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v8
-; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v8
+; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
; GFX10-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX10-NEXT: v_ffbh_u32_e32 v0, v0
+; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
; GFX10-NEXT: v_ffbh_u32_e32 v2, v3
+; GFX10-NEXT: v_ffbh_u32_e32 v0, v0
; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, 32 clamp
; GFX10-NEXT: v_min_u32_e32 v0, v2, v0
; GFX10-NEXT: v_min_u32_e32 v0, 64, v0
@@ -165,15 +179,19 @@ define amdgpu_kernel void @cttz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
+; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v6
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 8, v7
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
@@ -199,15 +217,19 @@ define amdgpu_kernel void @cttz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
+; GFX10-NEXT: s_waitcnt vmcnt(7)
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(6)
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX10-NEXT: s_waitcnt vmcnt(4)
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX10-NEXT: s_waitcnt vmcnt(2)
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v6
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v6
; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_lshl_or_b32 v3, v4, 8, v7
+; GFX10-NEXT: v_or_b32_e32 v3, v4, v7
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
@@ -238,15 +260,19 @@ define amdgpu_kernel void @cttz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
+; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(5)
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v6
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
+; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 8, v7
+; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
@@ -273,15 +299,19 @@ define amdgpu_kernel void @cttz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3]
; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
+; GFX10-NEXT: s_waitcnt vmcnt(7)
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(6)
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX10-NEXT: s_waitcnt vmcnt(4)
+; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX10-NEXT: s_waitcnt vmcnt(3)
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
; GFX10-NEXT: s_waitcnt vmcnt(2)
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v6
+; GFX10-NEXT: v_or_b32_e32 v0, v0, v6
; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_lshl_or_b32 v3, v4, 8, v7
+; GFX10-NEXT: v_or_b32_e32 v3, v4, v7
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
diff --git a/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll b/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
index 0756bf624f763..e065b8e4c5f97 100644
--- a/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/pack.v2i16.ll
@@ -411,7 +411,8 @@ define amdgpu_kernel void @v_pack_v2i16_inline_imm_lo(ptr addrspace(1) %in1) #0
; GFX803-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX803-NEXT: flat_load_dword v0, v[0:1] glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
-; GFX803-NEXT: v_lshl_or_b32 v0, v0, 16, 64
+; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX803-NEXT: v_or_b32_e32 v0, 64, v0
; GFX803-NEXT: ;;#ASMSTART
; GFX803-NEXT: ; use v0
; GFX803-NEXT: ;;#ASMEND
diff --git a/llvm/test/CodeGen/AMDGPU/permute_i8.ll b/llvm/test/CodeGen/AMDGPU/permute_i8.ll
index 1c7642bb05bac..b54d80a03abd0 100644
--- a/llvm/test/CodeGen/AMDGPU/permute_i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/permute_i8.ll
@@ -615,6 +615,7 @@ define amdgpu_kernel void @shuffle8i8(ptr addrspace(1) %in0, ptr addrspace(1) %i
; GFX10-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_bfe_u32 s0, s4, 0x80008
+; GFX10-NEXT: v_perm_b32 v0, s4, s8, v0
; GFX10-NEXT: s_lshl_b32 s1, s9, 8
; GFX10-NEXT: s_bfe_u32 s2, s5, 0x80008
; GFX10-NEXT: s_lshl_b32 s3, s8, 8
@@ -623,13 +624,13 @@ define amdgpu_kernel void @shuffle8i8(ptr addrspace(1) %in0, ptr addrspace(1) %i
; GFX10-NEXT: s_or_b32 s1, s2, s1
; GFX10-NEXT: s_lshl_b32 s2, s9, 8
; GFX10-NEXT: s_or_b32 s0, s0, s3
-; GFX10-NEXT: v_perm_b32 v0, s4, s8, v0
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: s_or_b32 s2, s5, s2
; GFX10-NEXT: s_and_b32 s0, s0, 0xffff
; GFX10-NEXT: s_lshl_b32 s1, s1, 16
; GFX10-NEXT: s_and_b32 s2, s2, 0xffff
; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: v_lshl_or_b32 v1, v0, 16, s2
+; GFX10-NEXT: v_or_b32_e32 v1, s2, v0
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX10-NEXT: s_endpgm
@@ -653,14 +654,15 @@ define amdgpu_kernel void @shuffle8i8(ptr addrspace(1) %in0, ptr addrspace(1) %i
; GFX9-NEXT: s_and_b32 s5, s4, 0xff
; GFX9-NEXT: s_or_b32 s0, s0, s3
; GFX9-NEXT: s_lshl_b32 s2, s2, 8
-; GFX9-NEXT: s_or_b32 s2, s5, s2
; GFX9-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-NEXT: s_or_b32 s2, s5, s2
+; GFX9-NEXT: v_perm_b32 v0, s4, v0, v1
; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: v_perm_b32 v0, s4, v0, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: s_and_b32 s2, s2, 0xffff
; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: v_lshl_or_b32 v1, v0, 16, s2
+; GFX9-NEXT: v_or_b32_e32 v1, s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX9-NEXT: s_endpgm
@@ -3871,7 +3873,8 @@ define amdgpu_kernel void @any_extend_to_perm(i8 %arg, <4 x i8> %arg1) {
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_perm_b32 v0, s1, s0, v0
; GFX10-NEXT: s_and_b32 s0, s1, 0xffff
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, s0
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
; GFX10-NEXT: ds_write_b32 v1, v0
; GFX10-NEXT: s_endpgm
;
@@ -3881,9 +3884,10 @@ define amdgpu_kernel void @any_extend_to_perm(i8 %arg, <4 x i8> %arg1) {
; GFX9-NEXT: v_mov_b32_e32 v0, 0xc0c0006
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s0
-; GFX9-NEXT: s_and_b32 s2, s1, 0xffff
; GFX9-NEXT: v_perm_b32 v0, s1, v1, v0
-; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, s2
+; GFX9-NEXT: s_and_b32 s2, s1, 0xffff
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: v_or_b32_e32 v0, s2, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: ds_write_b32 v1, v0
; GFX9-NEXT: s_endpgm
@@ -3904,13 +3908,15 @@ define amdgpu_kernel void @more_any_extend_to_perm(i8 %arg, <4 x i8> %arg1, i8 %
; GFX10-NEXT: v_mov_b32_e32 v1, 0xc0c0104
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_perm_b32 v2, s6, s7, v0
-; GFX10-NEXT: v_perm_b32 v3, s0, s7, v1
; GFX10-NEXT: v_perm_b32 v0, s0, s7, v0
+; GFX10-NEXT: v_perm_b32 v3, s0, s7, v1
; GFX10-NEXT: v_perm_b32 v1, s6, s7, v1
; GFX10-NEXT: v_mov_b32_e32 v4, s1
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_mov_b32_e32 v5, s2
-; GFX10-NEXT: v_lshl_or_b32 v2, v2, 16, v3
-; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GFX10-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-NEXT: ds_write_b32 v4, v2
; GFX10-NEXT: ds_write_b32 v5, v0
; GFX10-NEXT: s_endpgm
@@ -3919,17 +3925,19 @@ define amdgpu_kernel void @more_any_extend_to_perm(i8 %arg, <4 x i8> %arg1, i8 %
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; GFX9-NEXT: v_mov_b32_e32 v0, 0xc0c0104
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0304
+; GFX9-NEXT: v_mov_b32_e32 v0, 0xc0c0104
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s7
-; GFX9-NEXT: v_perm_b32 v3, s0, v2, v0
; GFX9-NEXT: v_perm_b32 v4, s6, v2, v1
-; GFX9-NEXT: v_perm_b32 v0, s6, v2, v0
; GFX9-NEXT: v_perm_b32 v1, s0, v2, v1
-; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
+; GFX9-NEXT: v_perm_b32 v3, s0, v2, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_perm_b32 v0, s6, v2, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s1
-; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: ds_write_b32 v4, v3
; GFX9-NEXT: ds_write_b32 v1, v0
diff --git a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
index 2546557e99083..5c043eadf6096 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
+++ b/llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx12.mir
@@ -19,9 +19,10 @@ body: |
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3
- ; GFX1250-NEXT: $vgpr1 = V_LSHL_OR_B32_e64 $vgpr0, 8, 0, implicit $exec
+ ; GFX1250-NEXT: renamable $vgpr1 = V_LSHLREV_B32_e32 8, $vgpr0, implicit $exec
; GFX1250-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 256, $vgpr0, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr3, $sgpr_null = V_ADDC_U32_e64 0, killed $vgpr0, killed $vcc_lo, 0, implicit $exec
+ ; GFX1250-NEXT: renamable $vgpr1 = disjoint V_OR_B32_e32 0, killed $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr0 = V_ADD_U32_e32 -256, $vgpr1, implicit $exec
; GFX1250-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr1, $vgpr2_vgpr3, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
; GFX1250-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr0, killed $vgpr2_vgpr3, 256, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
@@ -58,9 +59,10 @@ body: |
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4
- ; GFX1250-NEXT: $vgpr1 = V_LSHL_OR_B32_e64 $vgpr0, 8, 0, implicit $exec
+ ; GFX1250-NEXT: renamable $vgpr1 = V_LSHLREV_B32_e32 8, $vgpr0, implicit $exec
; GFX1250-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 256, $vgpr0, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr3, $sgpr_null = V_ADDC_U32_e64 0, killed $vgpr0, killed $vcc_lo, 0, implicit $exec
+ ; GFX1250-NEXT: renamable $vgpr1 = disjoint V_OR_B32_e32 0, killed $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr0 = V_ADD_U32_e32 -256, $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr4 = V_ADD_U32_e32 -260, $vgpr1, implicit $exec
; GFX1250-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr1, $vgpr2_vgpr3, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
@@ -152,9 +154,10 @@ body: |
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr4
- ; GFX1250-NEXT: $vgpr1 = V_LSHL_OR_B32_e64 $vgpr0, 8, 0, implicit $exec
+ ; GFX1250-NEXT: renamable $vgpr1 = V_LSHLREV_B32_e32 8, $vgpr0, implicit $exec
; GFX1250-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 256, $vgpr0, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr3, $sgpr_null = V_ADDC_U32_e64 0, killed $vgpr0, killed $vcc_lo, 0, implicit $exec
+ ; GFX1250-NEXT: renamable $vgpr1 = disjoint V_OR_B32_e32 0, killed $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr0 = V_ADD_U32_e32 -256, $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr4 = V_ADD_U32_e32 -512, $vgpr1, implicit $exec
; GFX1250-NEXT: GLOBAL_LOAD_ASYNC_TO_LDS_B128 killed $vgpr1, $vgpr2_vgpr3, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
@@ -200,9 +203,10 @@ body: |
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr1
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr2
; GFX1250-NEXT: frame-setup CFI_INSTRUCTION undefined $vgpr3
- ; GFX1250-NEXT: $vgpr1 = V_LSHL_OR_B32_e64 $vgpr0, 8, 0, implicit $exec
+ ; GFX1250-NEXT: renamable $vgpr1 = V_LSHLREV_B32_e32 8, $vgpr0, implicit $exec
; GFX1250-NEXT: renamable $vgpr2, renamable $vcc_lo = V_ADD_CO_U32_e64 256, $vgpr0, 0, implicit $exec
; GFX1250-NEXT: renamable $vgpr3, $sgpr_null = V_ADDC_U32_e64 0, killed $vgpr0, killed $vcc_lo, 0, implicit $exec
+ ; GFX1250-NEXT: renamable $vgpr1 = disjoint V_OR_B32_e32 0, killed $vgpr1, implicit $exec
; GFX1250-NEXT: renamable $vgpr0 = V_ADD_U32_e32 -256, $vgpr1, implicit $exec
; GFX1250-NEXT: GLOBAL_STORE_ASYNC_FROM_LDS_B128 $vgpr2_vgpr3, killed $vgpr1, 0, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
; GFX1250-NEXT: GLOBAL_STORE_ASYNC_FROM_LDS_B128 killed $vgpr2_vgpr3, killed $vgpr0, 256, 0, implicit-def $asynccnt, implicit $exec, implicit $asynccnt :: (load store (s128), align 1, addrspace 3)
diff --git a/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll b/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
index f8b6a0109ebb3..74bd338c7c022 100644
--- a/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
+++ b/llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
@@ -2656,8 +2656,9 @@ define <2 x i16> @v_mul_add_1_v2i16(<2 x i16> %x, <2 x i16> %y) {
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX8-NEXT: v_mad_u16 v2, v3, v2, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_mad_u16 v0, v0, v1, v0
-; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_add_1_v2i16:
@@ -2723,8 +2724,9 @@ define <2 x i16> @v_mul_add_1_v2i16_commute(<2 x i16> %x, <2 x i16> %y) {
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX8-NEXT: v_mad_u16 v2, v3, v2, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_mad_u16 v0, v0, v1, v0
-; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_add_1_v2i16_commute:
@@ -2787,8 +2789,9 @@ define <2 x i16> @v_mul_add_x_v2i16(<2 x i16> %x, <2 x i16> %y) {
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX8-NEXT: v_mad_u16 v2, v3, v2, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX8-NEXT: v_mad_u16 v0, v0, v1, v0
-; GFX8-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_add_x_v2i16:
@@ -4328,9 +4331,10 @@ define <2 x i16> @v_mul_9_add_52_v2i16(<2 x i16> %arg) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX8-NEXT: v_mad_u16 v0, v0, 9, 52
; GFX8-NEXT: v_mad_u16 v1, v1, 9, 52
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_mad_u16 v0, v0, 9, 52
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_9_add_52_v2i16:
@@ -4713,9 +4717,10 @@ define <2 x i16> @v_mul_5_add_1_v2i16(<2 x i16> %arg) {
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
-; GFX8-NEXT: v_mad_u16 v0, v0, 5, 1
; GFX8-NEXT: v_mad_u16 v1, v1, 5, 1
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_mad_u16 v0, v0, 5, 1
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_5_add_1_v2i16:
@@ -4773,9 +4778,10 @@ define <2 x i16> @v_mul_284_add_82_v2i16(<2 x i16> %arg) {
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-NEXT: s_movk_i32 s4, 0x11c
; GFX8-NEXT: v_mov_b32_e32 v2, 0x52
-; GFX8-NEXT: v_mad_u16 v0, v0, s4, v2
; GFX8-NEXT: v_mad_u16 v1, v1, s4, v2
-; GFX8-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-NEXT: v_mad_u16 v0, v0, s4, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_mul_284_add_82_v2i16:
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
index 1d0fcd3a962ea..a82415e2e8303 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
@@ -322,22 +322,24 @@ define amdgpu_kernel void @scalar_to_vector_v4f16() {
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-NEXT: s_mov_b32 s2, -1
-; GFX11-NEXT: ; kill: def $vgpr1_hi16 killed $sgpr0 killed $exec
; GFX11-NEXT: buffer_load_d16_u8 v0, off, s[0:3], 0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshl_or_b32 v0, v0, 8, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX11-NEXT: ; kill: def $vgpr1_hi16 killed $sgpr0 killed $exec
; GFX11-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v1
; GFX11-NEXT: s_and_b32 s1, s0, 0xff00
; GFX11-NEXT: s_bfe_u32 s4, s0, 0x80008
; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
; GFX11-NEXT: s_or_b32 s1, s4, s1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshl_b32 s4, s1, 16
; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
; GFX11-NEXT: s_or_b32 s0, s0, s4
; GFX11-NEXT: s_or_b32 s1, s1, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX11-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll
index c0b0f9ad13107..b690879dab99b 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll
@@ -1653,8 +1653,10 @@ define amdgpu_kernel void @v_sdiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: s_mov_b32 s1, s5
; TONGA-NEXT: s_waitcnt vmcnt(3)
; TONGA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; TONGA-NEXT: s_waitcnt vmcnt(2)
+; TONGA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; TONGA-NEXT: s_waitcnt vmcnt(1)
-; TONGA-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; TONGA-NEXT: v_or_b32_e32 v1, v2, v1
; TONGA-NEXT: v_bfe_i32 v1, v1, 0, 23
; TONGA-NEXT: v_cvt_f32_i32_e32 v2, v1
; TONGA-NEXT: s_waitcnt vmcnt(0)
@@ -1694,8 +1696,10 @@ define amdgpu_kernel void @v_sdiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_mov_b32 s1, s9
; GFX9-NEXT: s_waitcnt vmcnt(3)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 23
; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -1834,14 +1838,18 @@ define amdgpu_kernel void @v_sdiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; TONGA-NEXT: buffer_load_ushort v3, off, s[8:11], 0
; TONGA-NEXT: s_mov_b32 s0, s4
; TONGA-NEXT: s_mov_b32 s1, s5
+; TONGA-NEXT: s_waitcnt vmcnt(3)
+; TONGA-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; TONGA-NEXT: s_waitcnt vmcnt(2)
-; TONGA-NEXT: v_lshl_or_b32 v1, v0, 16, v1
+; TONGA-NEXT: v_or_b32_e32 v1, v1, v4
; TONGA-NEXT: v_cvt_f32_i32_e32 v1, v1
+; TONGA-NEXT: s_waitcnt vmcnt(1)
+; TONGA-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; TONGA-NEXT: s_waitcnt vmcnt(0)
-; TONGA-NEXT: v_lshl_or_b32 v3, v2, 16, v3
+; TONGA-NEXT: v_or_b32_e32 v3, v3, v4
; TONGA-NEXT: v_cvt_f32_i32_e32 v3, v3
-; TONGA-NEXT: v_xor_b32_e32 v0, v2, v0
; TONGA-NEXT: v_rcp_f32_e32 v4, v1
+; TONGA-NEXT: v_xor_b32_e32 v0, v2, v0
; TONGA-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; TONGA-NEXT: v_or_b32_e32 v0, 1, v0
; TONGA-NEXT: v_mul_f32_e32 v2, v3, v4
@@ -1871,14 +1879,18 @@ define amdgpu_kernel void @v_sdiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: buffer_load_ushort v3, off, s[4:7], 0
; GFX9-NEXT: s_mov_b32 s0, s8
; GFX9-NEXT: s_mov_b32 s1, s9
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_lshl_or_b32 v1, v0, 16, v1
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v4
; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v1
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshl_or_b32 v3, v2, 16, v3
+; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v3
-; GFX9-NEXT: v_xor_b32_e32 v0, v2, v0
; GFX9-NEXT: v_rcp_f32_e32 v4, v1
+; GFX9-NEXT: v_xor_b32_e32 v0, v2, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
; GFX9-NEXT: v_mul_f32_e32 v2, v3, v4
diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
index 0d8788c781a1c..fa705fb455ba8 100644
--- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
@@ -312,7 +312,8 @@ define amdgpu_kernel void @mul_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in
; NOSDWA-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v4, 16, v4
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, v4, v2
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; NOSDWA-NEXT: v_or_b32_e32 v2, v3, v2
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -405,8 +406,10 @@ define amdgpu_kernel void @mul_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in
; NOSDWA-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; NOSDWA-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; NOSDWA-NEXT: v_mul_lo_u16_e32 v0, v0, v2
-; NOSDWA-NEXT: v_lshl_or_b32 v1, v1, 16, v6
-; NOSDWA-NEXT: v_lshl_or_b32 v0, v0, 16, v7
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; NOSDWA-NEXT: v_or_b32_e32 v1, v6, v1
+; NOSDWA-NEXT: v_or_b32_e32 v0, v7, v0
; NOSDWA-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; NOSDWA-NEXT: s_endpgm
;
@@ -512,10 +515,14 @@ define amdgpu_kernel void @mul_v8i16(ptr addrspace(1) %out, ptr addrspace(1) %in
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, v2, v6
; NOSDWA-NEXT: v_mul_lo_u16_e32 v1, v1, v5
; NOSDWA-NEXT: v_mul_lo_u16_e32 v0, v0, v4
-; NOSDWA-NEXT: v_lshl_or_b32 v3, v3, 16, v10
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v2, 16, v11
-; NOSDWA-NEXT: v_lshl_or_b32 v1, v1, 16, v12
-; NOSDWA-NEXT: v_lshl_or_b32 v0, v0, 16, v13
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; NOSDWA-NEXT: v_or_b32_e32 v3, v10, v3
+; NOSDWA-NEXT: v_or_b32_e32 v2, v11, v2
+; NOSDWA-NEXT: v_or_b32_e32 v1, v12, v1
+; NOSDWA-NEXT: v_or_b32_e32 v0, v13, v0
; NOSDWA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; NOSDWA-NEXT: s_endpgm
;
@@ -688,8 +695,9 @@ define amdgpu_kernel void @mul_v2half(ptr addrspace(1) %out, ptr addrspace(1) %i
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
; NOSDWA-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; NOSDWA-NEXT: v_mul_f16_e32 v4, v5, v4
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; NOSDWA-NEXT: v_mul_f16_e32 v2, v3, v2
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v4
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -772,8 +780,10 @@ define amdgpu_kernel void @mul_v4half(ptr addrspace(1) %out, ptr addrspace(1) %i
; NOSDWA-NEXT: v_mul_f16_e32 v0, v0, v2
; NOSDWA-NEXT: v_mul_f16_e32 v2, v7, v6
; NOSDWA-NEXT: v_mul_f16_e32 v3, v8, v3
-; NOSDWA-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; NOSDWA-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; NOSDWA-NEXT: v_or_b32_e32 v1, v1, v2
+; NOSDWA-NEXT: v_or_b32_e32 v0, v0, v3
; NOSDWA-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; NOSDWA-NEXT: s_endpgm
;
@@ -869,10 +879,14 @@ define amdgpu_kernel void @mul_v8half(ptr addrspace(1) %out, ptr addrspace(1) %i
; NOSDWA-NEXT: v_mul_f16_e32 v7, v12, v7
; NOSDWA-NEXT: v_mul_f16_e32 v6, v13, v6
; NOSDWA-NEXT: v_mul_f16_e32 v4, v4, v5
-; NOSDWA-NEXT: v_lshl_or_b32 v3, v10, 16, v3
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v7, 16, v2
-; NOSDWA-NEXT: v_lshl_or_b32 v1, v6, 16, v1
-; NOSDWA-NEXT: v_lshl_or_b32 v0, v4, 16, v0
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v5, 16, v10
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; NOSDWA-NEXT: v_or_b32_e32 v3, v3, v5
+; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v7
+; NOSDWA-NEXT: v_or_b32_e32 v1, v1, v6
+; NOSDWA-NEXT: v_or_b32_e32 v0, v0, v4
; NOSDWA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
; NOSDWA-NEXT: s_endpgm
;
@@ -1143,25 +1157,26 @@ define amdgpu_kernel void @mul_v4i8(ptr addrspace(1) %out, ptr addrspace(1) %ina
; NOSDWA-NEXT: v_mov_b32_e32 v0, s0
; NOSDWA-NEXT: v_mov_b32_e32 v1, s1
; NOSDWA-NEXT: s_waitcnt vmcnt(1)
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v6, 8, v4
; NOSDWA-NEXT: v_lshrrev_b32_e32 v3, 16, v4
; NOSDWA-NEXT: v_lshrrev_b32_e32 v5, 24, v4
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v6, 8, v4
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v9, 8, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v8, 24, v2
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v9, 8, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, v4, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v4, v6, v9
-; NOSDWA-NEXT: v_and_b32_e32 v2, 0xff, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v5, v5, v8
; NOSDWA-NEXT: v_mul_lo_u16_e32 v3, v3, v7
+; NOSDWA-NEXT: v_and_b32_e32 v2, 0xff, v2
; NOSDWA-NEXT: v_lshlrev_b16_e32 v4, 8, v4
; NOSDWA-NEXT: v_lshlrev_b16_e32 v5, 8, v5
; NOSDWA-NEXT: v_and_b32_e32 v3, 0xff, v3
; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v4
; NOSDWA-NEXT: v_or_b32_e32 v3, v3, v5
; NOSDWA-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v3
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -1271,43 +1286,45 @@ define amdgpu_kernel void @mul_v8i8(ptr addrspace(1) %out, ptr addrspace(1) %ina
; NOSDWA-NEXT: v_mov_b32_e32 v4, s0
; NOSDWA-NEXT: v_mov_b32_e32 v5, s1
; NOSDWA-NEXT: s_waitcnt vmcnt(1)
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v8, 8, v0
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v11, 8, v1
-; NOSDWA-NEXT: s_waitcnt vmcnt(0)
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v14, 8, v2
-; NOSDWA-NEXT: v_lshrrev_b16_e32 v17, 8, v3
; NOSDWA-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; NOSDWA-NEXT: v_lshrrev_b32_e32 v7, 24, v0
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v8, 8, v0
; NOSDWA-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; NOSDWA-NEXT: v_lshrrev_b32_e32 v10, 24, v1
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v11, 8, v1
+; NOSDWA-NEXT: s_waitcnt vmcnt(0)
; NOSDWA-NEXT: v_lshrrev_b32_e32 v12, 16, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v13, 24, v2
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v14, 8, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v15, 16, v3
; NOSDWA-NEXT: v_lshrrev_b32_e32 v16, 24, v3
+; NOSDWA-NEXT: v_lshrrev_b16_e32 v17, 8, v3
; NOSDWA-NEXT: v_mul_lo_u16_e32 v1, v1, v3
; NOSDWA-NEXT: v_mul_lo_u16_e32 v0, v0, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, v11, v17
-; NOSDWA-NEXT: v_mul_lo_u16_e32 v8, v8, v14
-; NOSDWA-NEXT: v_and_b32_e32 v1, 0xff, v1
; NOSDWA-NEXT: v_mul_lo_u16_e32 v3, v10, v16
; NOSDWA-NEXT: v_mul_lo_u16_e32 v9, v9, v15
-; NOSDWA-NEXT: v_and_b32_e32 v0, 0xff, v0
+; NOSDWA-NEXT: v_mul_lo_u16_e32 v8, v8, v14
; NOSDWA-NEXT: v_mul_lo_u16_e32 v7, v7, v13
; NOSDWA-NEXT: v_mul_lo_u16_e32 v6, v6, v12
+; NOSDWA-NEXT: v_and_b32_e32 v1, 0xff, v1
+; NOSDWA-NEXT: v_and_b32_e32 v0, 0xff, v0
; NOSDWA-NEXT: v_lshlrev_b16_e32 v2, 8, v2
-; NOSDWA-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; NOSDWA-NEXT: v_lshlrev_b16_e32 v3, 8, v3
; NOSDWA-NEXT: v_and_b32_e32 v9, 0xff, v9
+; NOSDWA-NEXT: v_lshlrev_b16_e32 v8, 8, v8
; NOSDWA-NEXT: v_lshlrev_b16_e32 v7, 8, v7
; NOSDWA-NEXT: v_and_b32_e32 v6, 0xff, v6
; NOSDWA-NEXT: v_or_b32_e32 v1, v1, v2
-; NOSDWA-NEXT: v_or_b32_e32 v0, v0, v8
; NOSDWA-NEXT: v_or_b32_e32 v2, v9, v3
+; NOSDWA-NEXT: v_or_b32_e32 v0, v0, v8
; NOSDWA-NEXT: v_or_b32_e32 v3, v6, v7
; NOSDWA-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; NOSDWA-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; NOSDWA-NEXT: v_lshl_or_b32 v1, v2, 16, v1
-; NOSDWA-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; NOSDWA-NEXT: v_or_b32_e32 v1, v1, v2
+; NOSDWA-NEXT: v_or_b32_e32 v0, v0, v3
; NOSDWA-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
; NOSDWA-NEXT: s_endpgm
;
@@ -1442,8 +1459,9 @@ define amdgpu_kernel void @sitofp_v2i16_to_v2f16(
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
; NOSDWA-NEXT: v_lshrrev_b32_e32 v3, 16, v2
; NOSDWA-NEXT: v_cvt_f16_i16_e32 v3, v3
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; NOSDWA-NEXT: v_cvt_f16_i16_e32 v2, v2
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v3
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -1517,8 +1535,9 @@ define amdgpu_kernel void @mac_v2half(ptr addrspace(1) %out, ptr addrspace(1) %i
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
; NOSDWA-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; NOSDWA-NEXT: v_mac_f16_e32 v4, v5, v4
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; NOSDWA-NEXT: v_mac_f16_e32 v2, v3, v2
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v4
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -1539,8 +1558,9 @@ define amdgpu_kernel void @mac_v2half(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX89-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX89-NEXT: s_waitcnt vmcnt(0)
; GFX89-NEXT: v_mac_f16_sdwa v4, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX89-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX89-NEXT: v_mac_f16_e32 v2, v3, v2
-; GFX89-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX89-NEXT: v_or_b32_e32 v2, v2, v4
; GFX89-NEXT: flat_store_dword v[0:1], v2
; GFX89-NEXT: s_endpgm
;
@@ -1598,7 +1618,8 @@ define amdgpu_kernel void @immediate_mul_v2i16(ptr addrspace(1) %out, ptr addrsp
; NOSDWA-NEXT: v_mul_lo_u16_e32 v3, 0x7b, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, 0x141, v2
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; NOSDWA-NEXT: v_or_b32_e32 v2, v3, v2
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -1680,7 +1701,8 @@ define amdgpu_kernel void @mulmul_v2i16(ptr addrspace(1) %out, ptr addrspace(1)
; NOSDWA-NEXT: v_mul_lo_u16_e32 v5, v5, v4
; NOSDWA-NEXT: v_mul_lo_u16_e32 v2, v3, v2
; NOSDWA-NEXT: v_mul_lo_u16_e32 v3, v5, v4
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; NOSDWA-NEXT: v_or_b32_e32 v2, v2, v3
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -1769,9 +1791,10 @@ define amdgpu_kernel void @add_bb_v2i16(ptr addrspace(1) %out, ptr addrspace(1)
; NOSDWA-NEXT: v_add_u32_e32 v3, vcc, v1, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; NOSDWA-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; NOSDWA-NEXT: v_and_b32_e32 v3, 0xffff, v3
; NOSDWA-NEXT: v_add_u32_e32 v1, vcc, v1, v2
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v1, 16, v3
+; NOSDWA-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; NOSDWA-NEXT: v_or_b32_e32 v2, v3, v1
; NOSDWA-NEXT: v_mov_b32_e32 v1, s1
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
@@ -2199,8 +2222,9 @@ define amdgpu_kernel void @mac_v2half_same_srcop(ptr addrspace(1) %out, ptr addr
; NOSDWA-NEXT: s_waitcnt vmcnt(0)
; NOSDWA-NEXT: v_lshrrev_b32_e32 v5, 16, v3
; NOSDWA-NEXT: v_mac_f16_e32 v5, v4, v4
+; NOSDWA-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; NOSDWA-NEXT: v_mac_f16_e32 v3, v2, v2
-; NOSDWA-NEXT: v_lshl_or_b32 v2, v5, 16, v3
+; NOSDWA-NEXT: v_or_b32_e32 v2, v3, v4
; NOSDWA-NEXT: flat_store_dword v[0:1], v2
; NOSDWA-NEXT: s_endpgm
;
@@ -2221,8 +2245,9 @@ define amdgpu_kernel void @mac_v2half_same_srcop(ptr addrspace(1) %out, ptr addr
; GFX89-NEXT: v_lshrrev_b32_e32 v3, 16, v4
; GFX89-NEXT: s_waitcnt vmcnt(0)
; GFX89-NEXT: v_mac_f16_sdwa v3, v2, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX89-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX89-NEXT: v_mac_f16_e32 v4, v2, v2
-; GFX89-NEXT: v_lshl_or_b32 v2, v3, 16, v4
+; GFX89-NEXT: v_or_b32_e32 v2, v4, v3
; GFX89-NEXT: flat_store_dword v[0:1], v2
; GFX89-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
index 0f10241e3bccc..c026a42993d48 100644
--- a/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/select-fabs-fneg-extract.v2f16.ll
@@ -3697,8 +3697,9 @@ define <2 x half> @select_fneg_posk_src_fma_v2f16(<2 x i32> %c, <2 x half> %x, <
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; VI-NEXT: v_fma_f16 v1, v4, 4.0, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_fma_f16 v2, v2, 4.0, v3
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; VI-NEXT: v_mov_b32_e32 v2, 0x4000
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
@@ -3796,8 +3797,9 @@ define <2 x half> @select_fneg_posk_src_fmad_v2f16(<2 x i32> %c, <2 x half> %x,
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v3
; VI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; VI-NEXT: v_fma_f16 v1, v4, 4.0, v1
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; VI-NEXT: v_fma_f16 v2, v2, 4.0, v3
-; VI-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; VI-NEXT: v_or_b32_e32 v1, v2, v1
; VI-NEXT: v_xor_b32_e32 v1, 0x80008000, v1
; VI-NEXT: v_mov_b32_e32 v2, 0x4000
; VI-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/shl.ll b/llvm/test/CodeGen/AMDGPU/shl.ll
index 0960e64ecd8f2..7278247d9b45f 100644
--- a/llvm/test/CodeGen/AMDGPU/shl.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl.ll
@@ -2135,7 +2135,8 @@ define void @shl_or_k(ptr addrspace(1) %out, i32 %in) {
; VI-LABEL: shl_or_k:
; VI: ; %bb.0:
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-NEXT: v_lshl_or_b32 v2, v2, 2, 4
+; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v2
+; VI-NEXT: v_or_b32_e32 v2, 4, v2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/shl_or.ll b/llvm/test/CodeGen/AMDGPU/shl_or.ll
index 3c147a53f1ccd..efb28c8860853 100644
--- a/llvm/test/CodeGen/AMDGPU/shl_or.ll
+++ b/llvm/test/CodeGen/AMDGPU/shl_or.ll
@@ -11,7 +11,8 @@
define amdgpu_ps float @shl_or(i32 %a, i32 %b, i32 %c) {
; VI-LABEL: shl_or:
; VI: ; %bb.0:
-; VI-NEXT: v_lshl_or_b32 v0, v0, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v2
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or:
@@ -55,7 +56,8 @@ define amdgpu_ps float @shl_or_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {
define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) {
; VI-LABEL: shl_or_vgpr_all2:
; VI: ; %bb.0:
-; VI-NEXT: v_lshl_or_b32 v0, v0, v1, v2
+; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
+; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or_vgpr_all2:
@@ -76,7 +78,8 @@ define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) {
define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
; VI-LABEL: shl_or_vgpr_ac:
; VI: ; %bb.0:
-; VI-NEXT: v_lshl_or_b32 v0, v0, s2, v1
+; VI-NEXT: v_lshlrev_b32_e32 v0, s2, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or_vgpr_ac:
@@ -97,7 +100,8 @@ define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {
define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) {
; VI-LABEL: shl_or_vgpr_const:
; VI: ; %bb.0:
-; VI-NEXT: v_lshl_or_b32 v0, v0, v1, 6
+; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v0
+; VI-NEXT: v_or_b32_e32 v0, 6, v0
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or_vgpr_const:
@@ -118,7 +122,8 @@ define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) {
define amdgpu_ps float @shl_or_vgpr_const2(i32 %a, i32 %b) {
; VI-LABEL: shl_or_vgpr_const2:
; VI: ; %bb.0:
-; VI-NEXT: v_lshl_or_b32 v0, v0, 6, v1
+; VI-NEXT: v_lshlrev_b32_e32 v0, 6, v0
+; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or_vgpr_const2:
@@ -161,7 +166,8 @@ define amdgpu_ps float @shl_or_vgpr_const_scalar1(i32 inreg %a, i32 %b) {
define amdgpu_ps float @shl_or_vgpr_const_scalar2(i32 %a, i32 inreg %b) {
; VI-LABEL: shl_or_vgpr_const_scalar2:
; VI: ; %bb.0:
-; VI-NEXT: v_lshl_or_b32 v0, v0, 6, s2
+; VI-NEXT: v_lshlrev_b32_e32 v0, 6, v0
+; VI-NEXT: v_or_b32_e32 v0, s2, v0
; VI-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: shl_or_vgpr_const_scalar2:
diff --git a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
index 3a0d3a1abba03..9304154d30ad7 100644
--- a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
+++ b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll
@@ -2320,13 +2320,14 @@ define amdgpu_kernel void @v_test_v2i16_x_sub_7_0(ptr addrspace(1) %out, ptr add
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1]
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; VI-GISEL-NEXT: v_add_u16_e32 v3, -7, v3
-; VI-GISEL-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-GISEL-NEXT: v_or_b32_e32 v2, v3, v2
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
@@ -3087,13 +3088,14 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg32_0(ptr addrspace(1) %out, ptr
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1]
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; VI-GISEL-NEXT: v_add_u16_e32 v3, 0xffe0, v3
-; VI-GISEL-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-GISEL-NEXT: v_or_b32_e32 v2, v3, v2
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
@@ -3461,13 +3463,14 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg16_0(ptr addrspace(1) %out, ptr
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: flat_load_dword v3, v[0:1]
; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2
+; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1
; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-GISEL-NEXT: s_waitcnt vmcnt(0)
; VI-GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v3
; VI-GISEL-NEXT: v_add_u16_e32 v3, -16, v3
-; VI-GISEL-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-GISEL-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-GISEL-NEXT: v_or_b32_e32 v2, v3, v2
; VI-GISEL-NEXT: flat_store_dword v[0:1], v2
; VI-GISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
index 814b0723aab1b..76f8f484fc763 100644
--- a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
@@ -861,19 +861,20 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-NEXT: v_cmp_gt_i32_sdwa vcc, sext(v1), sext(v2) src0_sel:WORD_0 src1_sel:WORD_0
+; GFX9-NEXT: v_cmp_gt_i32_sdwa s[0:1], sext(v1), sext(v2) src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX9-NEXT: v_cndmask_b32_e32 v5, v2, v1, vcc
-; GFX9-NEXT: v_cmp_gt_i32_sdwa s[0:1], sext(v1), sext(v2) src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v6, v4, v3, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2
; GFX9-NEXT: v_lshl_or_b32 v4, v6, 16, v4
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
-; GFX9-NEXT: v_lshl_or_b32 v2, v2, 1, v5
+; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
; GFX9-NEXT: global_store_dword v0, v4, s[8:9]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v0, v1, s[10:11]
@@ -915,10 +916,11 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; VI-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[0:1]
; VI-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_lshlrev_b32_e32 v5, 1, v5
; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; VI-NEXT: flat_store_dword v[0:1], v6
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshl_or_b32 v0, v5, 1, v9
+; VI-NEXT: v_or_b32_e32 v0, v9, v5
; VI-NEXT: v_or_b32_sdwa v4, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: v_and_b32_e32 v0, 3, v0
; VI-NEXT: flat_store_dword v[2:3], v4
diff --git a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
index 1b655c6a52335..f08b68f9b8c38 100644
--- a/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
+++ b/llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask-phi-extend.ll
@@ -569,8 +569,8 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:1124 ; 4-byte Folded Reload
; CHECK-NEXT: v_accvgpr_write_b32 a16, v58
; CHECK-NEXT: v_accvgpr_write_b32 a17, v59
-; CHECK-NEXT: v_accvgpr_read_b32 v58, a40
; CHECK-NEXT: v_accvgpr_read_b32 v60, a36
+; CHECK-NEXT: v_accvgpr_read_b32 v58, a40
; CHECK-NEXT: s_xor_b64 s[54:55], exec, -1
; CHECK-NEXT: s_waitcnt vmcnt(29)
; CHECK-NEXT: v_xor_b32_e32 v28, v28, v18
@@ -592,44 +592,46 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_xor_b32_e32 v34, v36, v10
; CHECK-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a46
; CHECK-NEXT: v_accvgpr_read_b32 v31, a39
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a46
+; CHECK-NEXT: v_xor_b32_e32 v33, v35, v9
+; CHECK-NEXT: s_waitcnt vmcnt(20)
+; CHECK-NEXT: v_xor_b32_e32 v35, v39, v13
; CHECK-NEXT: s_waitcnt vmcnt(15)
; CHECK-NEXT: v_xor_b32_e32 v10, v44, v30
; CHECK-NEXT: v_accvgpr_read_b32 v30, a44
-; CHECK-NEXT: v_xor_b32_e32 v33, v35, v9
-; CHECK-NEXT: v_xor_b32_e32 v35, v39, v13
; CHECK-NEXT: s_waitcnt vmcnt(11)
; CHECK-NEXT: v_xor_b32_e32 v6, v48, v30
; CHECK-NEXT: v_accvgpr_read_b32 v30, a42
-; CHECK-NEXT: v_xor_b32_e32 v8, v46, v20
-; CHECK-NEXT: s_waitcnt vmcnt(9)
-; CHECK-NEXT: v_xor_b32_e32 v20, v50, v30
-; CHECK-NEXT: v_accvgpr_read_b32 v30, a38
+; CHECK-NEXT: v_xor_b32_e32 v9, v47, v21
+; CHECK-NEXT: s_waitcnt vmcnt(8)
+; CHECK-NEXT: v_xor_b32_e32 v21, v51, v25
+; CHECK-NEXT: v_accvgpr_write_b32 a36, v0
; CHECK-NEXT: s_waitcnt vmcnt(6)
; CHECK-NEXT: v_xor_b32_e32 v13, v53, v31
; CHECK-NEXT: v_accvgpr_read_b32 v31, a29
; CHECK-NEXT: s_waitcnt vmcnt(4)
; CHECK-NEXT: v_xor_b32_e32 v1, v55, v31
+; CHECK-NEXT: s_waitcnt vmcnt(3)
+; CHECK-NEXT: v_xor_b32_e32 v25, v56, v60
+; CHECK-NEXT: v_xor_b32_e32 v8, v46, v20
+; CHECK-NEXT: v_xor_b32_e32 v20, v50, v30
+; CHECK-NEXT: v_accvgpr_read_b32 v30, a38
+; CHECK-NEXT: v_xor_b32_e32 v0, v54, v58
+; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; CHECK-NEXT: v_xor_b32_e32 v11, v45, v19
; CHECK-NEXT: v_xor_b32_e32 v19, v27, v5
-; CHECK-NEXT: v_accvgpr_write_b32 a36, v0
; CHECK-NEXT: v_xor_b32_e32 v4, v52, v30
-; CHECK-NEXT: v_xor_b32_e32 v0, v54, v58
-; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
-; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffffff, v13
-; CHECK-NEXT: v_xor_b32_e32 v18, v38, v12
; CHECK-NEXT: v_xor_b32_e32 v30, v26, v2
+; CHECK-NEXT: v_lshlrev_b32_e32 v5, 17, v25
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 14, v[0:1]
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v5
+; CHECK-NEXT: v_and_b32_e32 v5, 0x7fffffff, v13
+; CHECK-NEXT: v_xor_b32_e32 v18, v38, v12
; CHECK-NEXT: v_lshlrev_b32_e32 v12, 18, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 13, v[4:5]
-; CHECK-NEXT: v_xor_b32_e32 v9, v47, v21
-; CHECK-NEXT: v_xor_b32_e32 v7, v49, v23
-; CHECK-NEXT: v_xor_b32_e32 v21, v51, v25
-; CHECK-NEXT: s_waitcnt vmcnt(3)
-; CHECK-NEXT: v_xor_b32_e32 v25, v56, v60
; CHECK-NEXT: v_or_b32_e32 v1, v1, v12
-; CHECK-NEXT: v_lshl_or_b32 v3, v25, 17, v3
+; CHECK-NEXT: v_xor_b32_e32 v7, v49, v23
; CHECK-NEXT: v_and_b32_e32 v21, 0x7fffffff, v21
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
@@ -660,18 +662,21 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_addc_co_u32_e64 v13, s[38:39], 0, v37, s[38:39]
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:80
; CHECK-NEXT: s_movk_i32 s38, 0x7c
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 19, v4
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 12, v[20:21]
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v0
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 20, v20
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 11, v[6:7]
-; CHECK-NEXT: v_lshl_or_b32 v3, v4, 19, v3
-; CHECK-NEXT: v_lshl_or_b32 v1, v20, 20, v1
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v4
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:64
-; CHECK-NEXT: v_accvgpr_read_b32 v4, a12
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 22, v8
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 21, v6
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 10, v[8:9]
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 9, v[10:11]
-; CHECK-NEXT: v_lshl_or_b32 v3, v6, 21, v3
-; CHECK-NEXT: v_lshl_or_b32 v1, v8, 22, v1
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v4
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:48
-; CHECK-NEXT: v_accvgpr_read_b32 v6, a36
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 26, v18
; CHECK-NEXT: v_add_co_u32_e64 v0, s[38:39], s38, v36
; CHECK-NEXT: v_addc_co_u32_e64 v1, s[38:39], 0, v37, s[38:39]
; CHECK-NEXT: v_lshrrev_b32_e32 v2, 15, v23
@@ -682,42 +687,51 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_addc_co_u32_e64 v1, s[38:39], 0, v37, s[38:39]
; CHECK-NEXT: flat_store_dword v[0:1], v2
; CHECK-NEXT: v_and_b32_e32 v0, 0x7fffffff, v19
-; CHECK-NEXT: v_lshl_or_b32 v31, v28, 31, v0
+; CHECK-NEXT: v_lshlrev_b32_e32 v1, 31, v28
+; CHECK-NEXT: v_or_b32_e32 v31, v0, v1
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 23, v10
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 8, v[16:17]
-; CHECK-NEXT: v_lshl_or_b32 v1, v10, 23, v1
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:64
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 24, v16
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 7, v[14:15]
-; CHECK-NEXT: v_lshl_or_b32 v1, v16, 24, v1
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
; CHECK-NEXT: v_and_b32_e32 v19, 0x7fffffff, v35
-; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v62
; CHECK-NEXT: flat_store_dwordx2 v[12:13], v[0:1] offset:32
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 25, v14
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 6, v[18:19]
+; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v62
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 5, v[34:35]
-; CHECK-NEXT: v_lshl_or_b32 v3, v14, 25, v3
-; CHECK-NEXT: v_lshl_or_b32 v1, v18, 26, v1
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v4
; CHECK-NEXT: flat_store_dwordx4 v[12:13], v[0:3] offset:16
-; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: v_accvgpr_read_b32 v6, a36
; CHECK-NEXT: v_mov_b32_e32 v0, v33
; CHECK-NEXT: v_and_b32_e32 v33, 0x7fffffff, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 4, v[32:33]
-; CHECK-NEXT: v_lshl_or_b32 v1, v34, 27, v1
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 27, v34
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:32
; CHECK-NEXT: v_accvgpr_read_b32 v0, a27
; CHECK-NEXT: v_accvgpr_read_b32 v2, a36
; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 3, v[2:3]
-; CHECK-NEXT: v_lshl_or_b32 v1, v32, 28, v1
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 28, v32
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
; CHECK-NEXT: flat_store_dwordx2 v[12:13], v[0:1]
; CHECK-NEXT: v_mov_b32_e32 v0, v29
; CHECK-NEXT: v_accvgpr_read_b32 v2, a12
; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v0
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[2:3]
-; CHECK-NEXT: v_lshl_or_b32 v1, v6, 29, v1
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v6
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
; CHECK-NEXT: flat_store_dwordx2 v[36:37], v[0:1] offset:16
; CHECK-NEXT: v_accvgpr_read_b32 v0, a9
+; CHECK-NEXT: v_accvgpr_read_b32 v4, a12
; CHECK-NEXT: v_and_b32_e32 v29, 0x7fffffff, v0
; CHECK-NEXT: v_lshrrev_b64 v[32:33], 1, v[28:29]
-; CHECK-NEXT: v_lshl_or_b32 v33, v4, 30, v33
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v4
+; CHECK-NEXT: v_or_b32_e32 v33, v33, v0
; CHECK-NEXT: flat_store_dwordx4 v[36:37], v[30:33]
; CHECK-NEXT: .LBB0_3: ; %Flow52
; CHECK-NEXT: s_or_b64 exec, exec, s[52:53]
@@ -916,53 +930,65 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: flat_store_dword v[0:1], v2
; CHECK-NEXT: v_accvgpr_read_b32 v2, a26
; CHECK-NEXT: v_accvgpr_read_b32 v3, a27
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 31, v10
+; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v9
; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
+; CHECK-NEXT: v_or_b32_e32 v9, v1, v0
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 17, v4
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 14, v[2:3]
; CHECK-NEXT: v_and_b32_e32 v37, 0x7fffffff, v37
-; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v9
; CHECK-NEXT: v_or_b32_e32 v5, v5, v0
; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v34
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 18, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 13, v[36:37]
-; CHECK-NEXT: v_lshl_or_b32 v9, v10, 31, v1
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v35, vcc
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:80
-; CHECK-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 20, v30
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v36
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 12, v[30:31]
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 11, v[32:33]
-; CHECK-NEXT: v_lshl_or_b32 v5, v36, 19, v5
-; CHECK-NEXT: v_lshl_or_b32 v3, v30, 20, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:64
-; CHECK-NEXT: v_lshl_or_b32 v11, v12, 30, v11
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 22, v28
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 21, v32
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 10, v[28:29]
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 9, v[20:21]
-; CHECK-NEXT: v_lshl_or_b32 v5, v32, 21, v5
-; CHECK-NEXT: v_lshl_or_b32 v3, v28, 22, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:48
-; CHECK-NEXT: flat_store_dwordx4 v[34:35], v[8:11]
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 26, v24
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v20
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[26:27]
-; CHECK-NEXT: v_lshl_or_b32 v3, v20, 23, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[34:35], v[2:3] offset:64
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v26
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[18:19]
-; CHECK-NEXT: v_lshl_or_b32 v3, v26, 24, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3] offset:32
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 25, v18
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 6, v[24:25]
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 5, v[16:17]
-; CHECK-NEXT: v_lshl_or_b32 v5, v18, 25, v5
-; CHECK-NEXT: v_lshl_or_b32 v3, v24, 26, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:16
-; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v16
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[22:23]
-; CHECK-NEXT: v_lshl_or_b32 v3, v16, 27, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[34:35], v[2:3] offset:32
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v22
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 3, v[14:15]
-; CHECK-NEXT: v_lshl_or_b32 v3, v22, 28, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v14
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[12:13]
-; CHECK-NEXT: v_lshl_or_b32 v1, v14, 29, v1
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
; CHECK-NEXT: flat_store_dwordx2 v[34:35], v[0:1] offset:16
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v12
+; CHECK-NEXT: v_or_b32_e32 v11, v11, v0
+; CHECK-NEXT: flat_store_dwordx4 v[34:35], v[8:11]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: ; kill: killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: .LBB0_41: ; %Flow
@@ -1017,7 +1043,7 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_and_b32_e32 v31, 0x7fffffff, v31
; CHECK-NEXT: v_and_b32_e32 v33, 0x7fffffff, v33
; CHECK-NEXT: v_and_b32_e32 v35, 0x7fffffff, v35
-; CHECK-NEXT: v_and_b32_e32 v37, 0x7fffffff, v37
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 18, v36
; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v52
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v53, vcc
; CHECK-NEXT: v_lshrrev_b32_e32 v2, 15, v39
@@ -1026,49 +1052,63 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_alignbit_b32 v2, v39, v38, 15
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v53, vcc
; CHECK-NEXT: flat_store_dword v[0:1], v2
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 31, v10
; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v9
+; CHECK-NEXT: v_and_b32_e32 v37, 0x7fffffff, v37
+; CHECK-NEXT: v_or_b32_e32 v9, v1, v0
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 17, v38
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 14, v[36:37]
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v0
; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v52
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 13, v[34:35]
-; CHECK-NEXT: v_lshl_or_b32 v9, v10, 31, v1
-; CHECK-NEXT: v_lshl_or_b32 v5, v38, 17, v5
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v53, vcc
-; CHECK-NEXT: v_lshl_or_b32 v3, v36, 18, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:80
-; CHECK-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 20, v32
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v34
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 12, v[32:33]
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 11, v[30:31]
-; CHECK-NEXT: v_lshl_or_b32 v5, v34, 19, v5
-; CHECK-NEXT: v_lshl_or_b32 v3, v32, 20, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:64
-; CHECK-NEXT: v_lshl_or_b32 v11, v12, 30, v11
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 22, v28
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 21, v30
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 10, v[28:29]
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 9, v[26:27]
-; CHECK-NEXT: v_lshl_or_b32 v5, v30, 21, v5
-; CHECK-NEXT: v_lshl_or_b32 v3, v28, 22, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:48
-; CHECK-NEXT: flat_store_dwordx4 v[52:53], v[8:11]
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 26, v20
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v26
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[24:25]
-; CHECK-NEXT: v_lshl_or_b32 v3, v26, 23, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[52:53], v[2:3] offset:64
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v24
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[22:23]
-; CHECK-NEXT: v_lshl_or_b32 v3, v24, 24, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3] offset:32
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 25, v22
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 6, v[20:21]
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 5, v[18:19]
-; CHECK-NEXT: v_lshl_or_b32 v5, v22, 25, v5
-; CHECK-NEXT: v_lshl_or_b32 v3, v20, 26, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:16
-; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: v_lshrrev_b64 v[10:11], 1, v[10:11]
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v18
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[16:17]
-; CHECK-NEXT: v_lshl_or_b32 v3, v18, 27, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[52:53], v[2:3] offset:32
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v16
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 3, v[14:15]
-; CHECK-NEXT: v_lshl_or_b32 v3, v16, 28, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v14
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[12:13]
-; CHECK-NEXT: v_lshl_or_b32 v1, v14, 29, v1
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
; CHECK-NEXT: flat_store_dwordx2 v[52:53], v[0:1] offset:16
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v12
+; CHECK-NEXT: v_or_b32_e32 v11, v11, v0
+; CHECK-NEXT: flat_store_dwordx4 v[52:53], v[8:11]
; CHECK-NEXT: .LBB0_43: ; %Flow48
; CHECK-NEXT: s_or_b64 exec, exec, s[56:57]
; CHECK-NEXT: s_andn2_b64 s[48:49], s[48:49], exec
@@ -1117,12 +1157,12 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:1620 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:1624 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:1628 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
+; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:1488 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:1492 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:1480 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:1484 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:984 ; 4-byte Folded Reload
-; CHECK-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:988 ; 4-byte Folded Reload
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_lshlrev_b32_e32 v6, 17, v32
; CHECK-NEXT: v_and_b32_e32 v59, 0x7fffffff, v59
@@ -1131,10 +1171,15 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_and_b32_e32 v49, 0x7fffffff, v49
; CHECK-NEXT: v_and_b32_e32 v43, 0x7fffffff, v43
; CHECK-NEXT: v_and_b32_e32 v4, 0x7fffffff, v1
-; CHECK-NEXT: v_lshl_or_b32 v41, v42, 31, v4
-; CHECK-NEXT: v_lshrrev_b64 v[42:43], 1, v[42:43]
-; CHECK-NEXT: v_lshl_or_b32 v43, v48, 30, v43
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v10
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
+; CHECK-NEXT: flat_store_short v[0:1], v33
+; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x78, v10
+; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
+; CHECK-NEXT: flat_store_dword v[0:1], v36
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 31, v42
; CHECK-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
+; CHECK-NEXT: v_or_b32_e32 v41, v4, v0
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 14, v[2:3]
; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
; CHECK-NEXT: v_or_b32_e32 v5, v5, v6
@@ -1143,67 +1188,74 @@ define void @f(ptr %p, <16 x i1> %m, <16 x i63> %pt, <16 x i1> %sc,
; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:1472 ; 4-byte Folded Reload
; CHECK-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:1476 ; 4-byte Folded Reload
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x7c, v10
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
-; CHECK-NEXT: flat_store_short v[0:1], v33
-; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 0x78, v10
-; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
-; CHECK-NEXT: flat_store_dword v[0:1], v36
; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 24, v10
; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v11, vcc
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:80
-; CHECK-NEXT: flat_store_dwordx4 v[10:11], v[40:43]
-; CHECK-NEXT: s_waitcnt vmcnt(0)
-; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
-; CHECK-NEXT: v_lshrrev_b64 v[4:5], 12, v[6:7]
-; CHECK-NEXT: v_lshl_or_b32 v5, v8, 19, v5
+; CHECK-NEXT: v_lshrrev_b64 v[42:43], 1, v[42:43]
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 19, v8
; CHECK-NEXT: v_accvgpr_read_b32 v8, a32
; CHECK-NEXT: v_accvgpr_read_b32 v9, a33
; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
+; CHECK-NEXT: s_waitcnt vmcnt(0)
+; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
+; CHECK-NEXT: v_lshrrev_b64 v[4:5], 12, v[6:7]
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 20, v6
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 11, v[8:9]
-; CHECK-NEXT: v_lshl_or_b32 v3, v6, 20, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: v_accvgpr_read_b32 v6, a34
-; CHECK-NEXT: v_accvgpr_read_b32 v7, a35
-; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:64
-; CHECK-NEXT: s_nop 0
-; CHECK-NEXT: v_lshrrev_b64 v[4:5], 10, v[6:7]
-; CHECK-NEXT: v_lshl_or_b32 v5, v8, 21, v5
+; CHECK-NEXT: v_accvgpr_read_b32 v7, a35
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 21, v8
; CHECK-NEXT: v_accvgpr_read_b32 v8, a24
+; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: v_accvgpr_read_b32 v9, a25
+; CHECK-NEXT: v_lshrrev_b64 v[4:5], 10, v[6:7]
; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 22, v6
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 9, v[8:9]
-; CHECK-NEXT: v_lshl_or_b32 v3, v6, 22, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:48
; CHECK-NEXT: v_accvgpr_read_b32 v6, a22
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 23, v8
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 8, v[58:59]
-; CHECK-NEXT: v_lshl_or_b32 v3, v8, 23, v3
-; CHECK-NEXT: v_accvgpr_read_b32 v8, a20
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[2:3] offset:64
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 24, v58
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 7, v[50:51]
; CHECK-NEXT: v_accvgpr_read_b32 v7, a23
-; CHECK-NEXT: v_accvgpr_read_b32 v9, a21
-; CHECK-NEXT: v_lshl_or_b32 v3, v58, 24, v3
+; CHECK-NEXT: v_accvgpr_read_b32 v8, a20
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
-; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
+; CHECK-NEXT: v_accvgpr_read_b32 v9, a21
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3] offset:32
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 25, v50
; CHECK-NEXT: v_lshrrev_b64 v[4:5], 6, v[6:7]
+; CHECK-NEXT: v_and_b32_e32 v9, 0x7fffffff, v9
+; CHECK-NEXT: v_or_b32_e32 v5, v5, v2
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 26, v6
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 5, v[8:9]
-; CHECK-NEXT: v_lshl_or_b32 v5, v50, 25, v5
-; CHECK-NEXT: v_lshl_or_b32 v3, v6, 26, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v6
; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
; CHECK-NEXT: flat_store_dwordx4 v[0:1], v[2:5] offset:16
; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 27, v8
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 4, v[56:57]
-; CHECK-NEXT: v_lshl_or_b32 v3, v8, 27, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: v_and_b32_e32 v7, 0x7fffffff, v7
; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[2:3] offset:32
+; CHECK-NEXT: v_lshlrev_b32_e32 v4, 28, v56
; CHECK-NEXT: v_lshrrev_b64 v[2:3], 3, v[6:7]
-; CHECK-NEXT: v_lshl_or_b32 v3, v56, 28, v3
+; CHECK-NEXT: v_or_b32_e32 v3, v3, v4
; CHECK-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; CHECK-NEXT: v_lshlrev_b32_e32 v2, 29, v6
; CHECK-NEXT: v_lshrrev_b64 v[0:1], 2, v[48:49]
-; CHECK-NEXT: v_lshl_or_b32 v1, v6, 29, v1
+; CHECK-NEXT: v_or_b32_e32 v1, v1, v2
; CHECK-NEXT: flat_store_dwordx2 v[10:11], v[0:1] offset:16
+; CHECK-NEXT: v_lshlrev_b32_e32 v0, 30, v48
+; CHECK-NEXT: v_or_b32_e32 v43, v43, v0
+; CHECK-NEXT: flat_store_dwordx4 v[10:11], v[40:43]
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: ; kill: killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/stack-realign.ll b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
index 2222a3a7baff4..c975f3a9ba946 100644
--- a/llvm/test/CodeGen/AMDGPU/stack-realign.ll
+++ b/llvm/test/CodeGen/AMDGPU/stack-realign.ll
@@ -155,8 +155,9 @@ define amdgpu_kernel void @kernel_call_align16_from_8() #0 {
; GCN-NEXT: s_add_u32 s14, s14, needs_align16_default_stack_align at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s15, s15, needs_align16_default_stack_align at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[18:19], s[14:15], 0x0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: v_mov_b32_e32 v3, 2
; GCN-NEXT: v_or_b32_e32 v31, v0, v2
; GCN-NEXT: s_mov_b32 s14, s16
@@ -187,8 +188,9 @@ define amdgpu_kernel void @kernel_call_align16_from_5() #6 {
; GCN-NEXT: s_add_u32 s14, s14, needs_align16_default_stack_align at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s15, s15, needs_align16_default_stack_align at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[18:19], s[14:15], 0x0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: v_mov_b32_e32 v3, 2
; GCN-NEXT: v_or_b32_e32 v31, v0, v2
; GCN-NEXT: s_mov_b32 s14, s16
@@ -219,8 +221,9 @@ define amdgpu_kernel void @kernel_call_align4_from_5() #6 {
; GCN-NEXT: s_add_u32 s14, s14, needs_align16_stack_align4 at gotpcrel32@lo+4
; GCN-NEXT: s_addc_u32 s15, s15, needs_align16_stack_align4 at gotpcrel32@hi+12
; GCN-NEXT: s_load_dwordx2 s[18:19], s[14:15], 0x0
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 10, v1
; GCN-NEXT: v_lshlrev_b32_e32 v2, 20, v2
-; GCN-NEXT: v_lshl_or_b32 v0, v1, 10, v0
+; GCN-NEXT: v_or_b32_e32 v0, v0, v1
; GCN-NEXT: v_mov_b32_e32 v3, 2
; GCN-NEXT: v_or_b32_e32 v31, v0, v2
; GCN-NEXT: s_mov_b32 s14, s16
diff --git a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
index e56dd62834280..480eb0dd5fe9c 100644
--- a/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll
@@ -94,7 +94,8 @@ define amdgpu_kernel void @local_store_i55(ptr addrspace(3) %ptr, i55 %arg) #0 {
; FIJI-NEXT: v_mov_b32_e32 v1, s2
; FIJI-NEXT: ds_write_b16 v1, v2 offset:4
; FIJI-NEXT: s_waitcnt vmcnt(0)
-; FIJI-NEXT: v_lshl_or_b32 v0, v0, 16, s4
+; FIJI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; FIJI-NEXT: v_or_b32_e32 v0, s4, v0
; FIJI-NEXT: v_bfe_u32 v0, v0, 16, 7
; FIJI-NEXT: ds_write_b8 v1, v0 offset:6
; FIJI-NEXT: ds_write_b32 v1, v3
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
index eec02c141ca3e..f695526737311 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
@@ -47,8 +47,9 @@ define <2 x half> @v_constained_fma_v2f16_fpexcept_strict(<2 x half> %x, <2 x ha
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX8-NEXT: v_fma_f16 v3, v5, v4, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX8-NEXT: v_fma_f16 v0, v0, v1, v2
-; GFX8-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_constained_fma_v2f16_fpexcept_strict:
@@ -81,8 +82,9 @@ define <3 x half> @v_constained_fma_v3f16_fpexcept_strict(<3 x half> %x, <3 x ha
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
; GFX8-NEXT: v_fma_f16 v6, v8, v7, v6
+; GFX8-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
-; GFX8-NEXT: v_lshl_or_b32 v0, v6, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v6
; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
@@ -141,10 +143,12 @@ define <4 x half> @v_constained_fma_v4f16_fpexcept_strict(<4 x half> %x, <4 x ha
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v0
; GFX8-NEXT: v_fma_f16 v7, v9, v8, v7
-; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
; GFX8-NEXT: v_fma_f16 v0, v0, v2, v4
-; GFX8-NEXT: v_lshl_or_b32 v0, v7, 16, v0
-; GFX8-NEXT: v_lshl_or_b32 v1, v6, 16, v1
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v7
+; GFX8-NEXT: v_fma_f16 v1, v1, v3, v5
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v6
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_constained_fma_v4f16_fpexcept_strict:
@@ -297,8 +301,9 @@ define <2 x half> @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg(<2 x half> %
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX8-NEXT: v_fma_f16 v3, -v5, -v4, v3
+; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX8-NEXT: v_fma_f16 v0, -v0, -v1, v2
-; GFX8-NEXT: v_lshl_or_b32 v0, v3, 16, v0
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_constained_fma_v2f16_fpexcept_strict_fneg_fneg:
diff --git a/llvm/test/CodeGen/AMDGPU/trunc-store.ll b/llvm/test/CodeGen/AMDGPU/trunc-store.ll
index fdf10b1d52188..b22a824b1a3c7 100644
--- a/llvm/test/CodeGen/AMDGPU/trunc-store.ll
+++ b/llvm/test/CodeGen/AMDGPU/trunc-store.ll
@@ -59,26 +59,30 @@ define amdgpu_kernel void @truncstore_arg_v16i32_to_v16i8(ptr addrspace(1) %out,
; VI-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_mov_b32_e32 v2, s23
-; VI-NEXT: v_perm_b32 v1, s20, v1, v0
+; VI-NEXT: v_mov_b32_e32 v1, s21
; VI-NEXT: v_perm_b32 v2, s22, v2, v0
-; VI-NEXT: v_lshl_or_b32 v3, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v1, s17
+; VI-NEXT: v_perm_b32 v1, s20, v1, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, v1, v2
; VI-NEXT: v_mov_b32_e32 v2, s19
-; VI-NEXT: v_perm_b32 v1, s16, v1, v0
+; VI-NEXT: v_mov_b32_e32 v1, s17
; VI-NEXT: v_perm_b32 v2, s18, v2, v0
-; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v1, s13
+; VI-NEXT: v_perm_b32 v1, s16, v1, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s15
-; VI-NEXT: v_perm_b32 v1, s12, v1, v0
+; VI-NEXT: v_or_b32_e32 v2, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s13
; VI-NEXT: v_perm_b32 v4, s14, v4, v0
-; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; VI-NEXT: v_perm_b32 v1, s12, v1, v0
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v1, v1, v4
; VI-NEXT: v_mov_b32_e32 v4, s9
; VI-NEXT: v_mov_b32_e32 v5, s11
; VI-NEXT: v_perm_b32 v4, s8, v4, v0
; VI-NEXT: v_perm_b32 v0, s10, v5, v0
-; VI-NEXT: v_lshl_or_b32 v0, v0, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-NEXT: v_or_b32_e32 v0, v4, v0
; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -143,30 +147,34 @@ define amdgpu_kernel void @truncstore_arg_v16i64_to_v16i8(ptr addrspace(1) %out,
; VI-LABEL: truncstore_arg_v16i64_to_v16i8:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx16 s[16:31], s[4:5], 0xe4
+; VI-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; VI-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
; VI-NEXT: s_load_dwordx16 s[0:15], s[4:5], 0xa4
-; VI-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; VI-NEXT: s_waitcnt lgkmcnt(0)
-; VI-NEXT: v_mov_b32_e32 v1, s26
; VI-NEXT: v_mov_b32_e32 v2, s30
-; VI-NEXT: v_perm_b32 v1, s24, v1, v0
+; VI-NEXT: v_mov_b32_e32 v1, s26
; VI-NEXT: v_perm_b32 v2, s28, v2, v0
-; VI-NEXT: v_lshl_or_b32 v3, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v1, s18
+; VI-NEXT: v_perm_b32 v1, s24, v1, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; VI-NEXT: v_or_b32_e32 v3, v1, v2
; VI-NEXT: v_mov_b32_e32 v2, s22
-; VI-NEXT: v_perm_b32 v1, s16, v1, v0
+; VI-NEXT: v_mov_b32_e32 v1, s18
; VI-NEXT: v_perm_b32 v2, s20, v2, v0
-; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v1
-; VI-NEXT: v_mov_b32_e32 v1, s10
+; VI-NEXT: v_perm_b32 v1, s16, v1, v0
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_mov_b32_e32 v4, s14
-; VI-NEXT: v_perm_b32 v1, s8, v1, v0
+; VI-NEXT: v_or_b32_e32 v2, v1, v2
+; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: v_perm_b32 v4, s12, v4, v0
-; VI-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; VI-NEXT: v_perm_b32 v1, s8, v1, v0
+; VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; VI-NEXT: v_or_b32_e32 v1, v1, v4
; VI-NEXT: v_mov_b32_e32 v4, s2
; VI-NEXT: v_mov_b32_e32 v5, s6
; VI-NEXT: v_perm_b32 v4, s0, v4, v0
; VI-NEXT: v_perm_b32 v0, s4, v5, v0
-; VI-NEXT: v_lshl_or_b32 v0, v0, 16, v4
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; VI-NEXT: v_or_b32_e32 v0, v4, v0
; VI-NEXT: v_mov_b32_e32 v4, s34
; VI-NEXT: v_mov_b32_e32 v5, s35
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
@@ -253,7 +261,8 @@ define void @truncstore_v5i32_to_v5i8(ptr addrspace(1) %out, <5 x i32> %val) {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v3, v4, v5, s4
-; VI-NEXT: v_lshl_or_b32 v4, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v4, v2, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; VI-NEXT: flat_store_byte v[2:3], v6
@@ -351,7 +360,8 @@ define void @truncstore_v6i32_to_v6i8(ptr addrspace(1) %out, <6 x i32> %val) {
; VI-NEXT: s_mov_b32 s4, 0xc0c0004
; VI-NEXT: v_perm_b32 v2, v2, v3, s4
; VI-NEXT: v_perm_b32 v3, v4, v5, s4
-; VI-NEXT: v_lshl_or_b32 v4, v3, 16, v2
+; VI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; VI-NEXT: v_or_b32_e32 v4, v2, v3
; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; VI-NEXT: v_perm_b32 v5, v6, v7, s4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index 0dec2e18b9569..859a65f88800d 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -1727,11 +1727,15 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: buffer_load_ushort v3, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s4, s0
; VI-NEXT: s_mov_b32 s5, s1
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_cvt_f32_u32_e32 v0, v0
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshl_or_b32 v1, v2, 16, v3
+; VI-NEXT: v_or_b32_e32 v1, v3, v1
; VI-NEXT: v_cvt_f32_u32_e32 v1, v1
; VI-NEXT: v_rcp_f32_e32 v2, v0
; VI-NEXT: v_mul_f32_e32 v2, v1, v2
@@ -1769,11 +1773,15 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mov_b32_e32 v3, s3
; GCN-NEXT: flat_load_ubyte v0, v[0:1]
; GCN-NEXT: flat_load_ushort v1, v[2:3]
+; GCN-NEXT: s_waitcnt vmcnt(3)
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v6
; GCN-NEXT: s_waitcnt vmcnt(2)
-; GCN-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GCN-NEXT: v_or_b32_e32 v2, v4, v2
; GCN-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; GCN-NEXT: v_or_b32_e32 v0, v1, v0
; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0
; GCN-NEXT: v_rcp_f32_e32 v4, v2
; GCN-NEXT: v_mov_b32_e32 v0, s0
@@ -1798,13 +1806,17 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1030-NEXT: global_load_ushort v2, v0, s[2:3] offset:4
; GFX1030-NEXT: global_load_ubyte v3, v0, s[2:3] offset:2
; GFX1030-NEXT: global_load_ushort v4, v0, s[2:3]
+; GFX1030-NEXT: s_waitcnt vmcnt(3)
+; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX1030-NEXT: s_waitcnt vmcnt(2)
-; GFX1030-NEXT: v_lshl_or_b32 v1, v1, 16, v2
-; GFX1030-NEXT: s_waitcnt vmcnt(0)
-; GFX1030-NEXT: v_lshl_or_b32 v2, v3, 16, v4
+; GFX1030-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX1030-NEXT: s_waitcnt vmcnt(1)
+; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX1030-NEXT: s_waitcnt vmcnt(0)
+; GFX1030-NEXT: v_or_b32_e32 v2, v4, v2
; GFX1030-NEXT: v_rcp_f32_e32 v3, v1
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v2
; GFX1030-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1030-NEXT: v_trunc_f32_e32 v3, v3
; GFX1030-NEXT: v_fma_f32 v2, -v3, v1, v2
@@ -1925,13 +1937,17 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; VI-NEXT: buffer_load_ushort v3, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5
+; VI-NEXT: s_waitcnt vmcnt(3)
+; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; VI-NEXT: s_waitcnt vmcnt(2)
-; VI-NEXT: v_lshl_or_b32 v0, v0, 16, v1
+; VI-NEXT: v_or_b32_e32 v0, v1, v0
; VI-NEXT: v_cvt_f32_u32_e32 v1, v0
; VI-NEXT: v_sub_u32_e32 v4, vcc, 0, v0
-; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_lshl_or_b32 v2, v2, 16, v3
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; VI-NEXT: v_rcp_f32_e32 v1, v1
+; VI-NEXT: s_waitcnt vmcnt(0)
+; VI-NEXT: v_or_b32_e32 v2, v3, v2
; VI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; VI-NEXT: v_cvt_u32_f32_e32 v1, v1
; VI-NEXT: v_mul_lo_u32 v4, v4, v1
@@ -1977,13 +1993,17 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; GCN-NEXT: v_mov_b32_e32 v1, s3
; GCN-NEXT: flat_load_ubyte v2, v[2:3]
; GCN-NEXT: flat_load_ushort v0, v[0:1]
+; GCN-NEXT: s_waitcnt vmcnt(3)
+; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v4
; GCN-NEXT: s_waitcnt vmcnt(2)
-; GCN-NEXT: v_lshl_or_b32 v3, v4, 16, v5
+; GCN-NEXT: v_or_b32_e32 v3, v5, v1
; GCN-NEXT: v_cvt_f32_u32_e32 v1, v3
; GCN-NEXT: v_sub_u32_e32 v4, vcc, 0, v3
+; GCN-NEXT: s_waitcnt vmcnt(1)
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GCN-NEXT: v_rcp_f32_e32 v1, v1
; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: v_lshl_or_b32 v2, v2, 16, v0
+; GCN-NEXT: v_or_b32_e32 v2, v0, v2
; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
; GCN-NEXT: v_mul_lo_u32 v4, v4, v1
diff --git a/llvm/test/CodeGen/AMDGPU/v_lshl_or_b32.mir b/llvm/test/CodeGen/AMDGPU/v_lshl_or_b32.mir
deleted file mode 100644
index 3d2a15b689dcf..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/v_lshl_or_b32.mir
+++ /dev/null
@@ -1,131 +0,0 @@
-# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX9 %s
-# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX10P %s
-# RUN: llc -simplify-mir -mtriple=amdgcn -mcpu=gfx1201 -run-pass=si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GCN,GFX10P %s
-
-# Post-RA fusion of v_lshlrev_b32 + v_or_b32 into v_lshl_or_b32 in
-# SIShrinkInstructions::matchLshlOr.
-
----
-# Simple adjacent pair, shift amount is an inline immediate.
-# GCN-LABEL: name: lshl_or_adjacent
-# GCN: $vgpr0 = V_LSHL_OR_B32_e64 $vgpr1, 16, $vgpr2, implicit $exec
-# GCN-NOT: V_LSHLREV_B32
-# GCN-NOT: V_OR_B32
-name: lshl_or_adjacent
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr1, $vgpr2, $sgpr30_sgpr31
- $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
- $vgpr0 = V_OR_B32_e32 killed $vgpr0, $vgpr2, implicit $exec
- S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
-...
-
----
-# Same as above but with the killed source on the other side of the or
-# (v_or_b32 is commutative).
-# GCN-LABEL: name: lshl_or_commuted
-# GCN: $vgpr0 = V_LSHL_OR_B32_e64 $vgpr1, 16, $vgpr2, implicit $exec
-# GCN-NOT: V_LSHLREV_B32
-# GCN-NOT: V_OR_B32
-name: lshl_or_commuted
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr1, $vgpr2, $sgpr30_sgpr31
- $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
- $vgpr0 = V_OR_B32_e32 $vgpr2, killed $vgpr0, implicit $exec
- S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
-...
-
----
-# A few intervening instructions that don't touch the shift result. Still fuses
-# because the search window is 16 instructions.
-# GCN-LABEL: name: lshl_or_sparse
-# GCN: $vgpr0 = V_LSHL_OR_B32_e64 $vgpr1, 16, $vgpr2, implicit $exec
-# GCN-NOT: V_LSHLREV_B32
-name: lshl_or_sparse
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $sgpr30_sgpr31
- $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
- $vgpr3 = V_ADD_U32_e32 $vgpr4, $vgpr5, implicit $exec
- $vgpr4 = V_MUL_U32_U24_e32 $vgpr5, $vgpr3, implicit $exec
- $vgpr0 = V_OR_B32_e32 killed $vgpr0, $vgpr2, implicit $exec
- S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr3, implicit $vgpr4
-...
-
----
-# Negative: another instruction reads the shift result before the or, so the
-# shift cannot be removed. Pair must remain unfused.
-# GCN-LABEL: name: lshl_or_multiuse_blocks
-# GCN: $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
-# GCN: V_MOV_B32_e32 $vgpr0, implicit $exec
-# GCN: V_OR_B32_e32 killed $vgpr0, $vgpr2, implicit $exec
-# GCN-NOT: V_LSHL_OR_B32_e64
-name: lshl_or_multiuse_blocks
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr1, $vgpr2, $sgpr30_sgpr31
- $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
- $vgpr3 = V_MOV_B32_e32 $vgpr0, implicit $exec
- $vgpr0 = V_OR_B32_e32 killed $vgpr0, $vgpr2, implicit $exec
- S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr3
-...
-
----
-# Negative: shift destination is not killed at the or, so the value escapes.
-# Conservatively keep the original sequence.
-# GCN-LABEL: name: lshl_or_not_killed
-# GCN: $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
-# GCN: V_OR_B32_e32 $vgpr0, $vgpr2, implicit $exec
-# GCN-NOT: V_LSHL_OR_B32_e64
-name: lshl_or_not_killed
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr1, $vgpr2, $sgpr30_sgpr31
- $vgpr0 = V_LSHLREV_B32_e32 16, $vgpr1, implicit $exec
- $vgpr3 = V_OR_B32_e32 $vgpr0, $vgpr2, implicit $exec
- S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0, implicit $vgpr3
-...
-
----
-# Constant-bus check: two distinct SGPR sources (plus an inline-immediate shift
-# amount) is over the limit on GFX9 (constant-bus limit 1) but within the
-# limit on GFX10+ (limit 2). The peephole must therefore bail on GFX9 and
-# fuse on GFX10+.
-# GCN-LABEL: name: lshl_or_two_sgprs
-# GFX9: V_LSHLREV_B32
-# GFX9: V_OR_B32
-# GFX9-NOT: V_LSHL_OR_B32_e64
-# GFX10P: V_LSHL_OR_B32_e64 $sgpr4, 16, $sgpr5, implicit $exec
-# GFX10P-NOT: V_LSHLREV_B32
-name: lshl_or_two_sgprs
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $sgpr4, $sgpr5, $sgpr30_sgpr31
- $vgpr0 = V_LSHLREV_B32_e64 16, $sgpr4, implicit $exec
- $vgpr0 = V_OR_B32_e64 killed $vgpr0, $sgpr5, implicit $exec
- S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
-...
-
----
-# Variable (VGPR) shift amount: should still fuse, since the shift amount is a
-# VGPR (does not consume a constant-bus slot) and both shifted value and or
-# operand are VGPRs.
-# GCN-LABEL: name: lshl_or_var_shift
-# GCN: $vgpr0 = V_LSHL_OR_B32_e64 $vgpr1, $vgpr3, $vgpr2, implicit $exec
-# GCN-NOT: V_LSHLREV_B32
-name: lshl_or_var_shift
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
- $vgpr0 = V_LSHLREV_B32_e32 $vgpr3, $vgpr1, implicit $exec
- $vgpr0 = V_OR_B32_e32 killed $vgpr0, $vgpr2, implicit $exec
- S_SETPC_B64_return $sgpr30_sgpr31, implicit $vgpr0
-...
diff --git a/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll b/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
index 53e01648588e8..f32db0dd5f473 100644
--- a/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_mac_f16-fpdp-rounding-mode.ll
@@ -9,10 +9,11 @@ define <2 x half> @v_mac_f16_fpdp_rounding(<2 x half> %a, <2 x half> %c, <2 x ha
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; CHECK-NEXT: v_mac_f16_sdwa v6, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; CHECK-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; CHECK-NEXT: v_mac_f16_e32 v1, v0, v2
; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1
; CHECK-NEXT: v_cvt_f16_f32_e32 v3, v3
-; CHECK-NEXT: v_lshl_or_b32 v0, v6, 16, v1
+; CHECK-NEXT: v_or_b32_e32 v0, v1, v6
; CHECK-NEXT: flat_store_short v[4:5], v3
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll b/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
index ea95cc3436840..8e1a4bf2a2d9f 100644
--- a/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
@@ -365,8 +365,9 @@ entry:
; VI-DAG: v_lshrrev_b32_e32 v[[C_F16_1:[0-9]+]], 16, v[[C_V2_F16]]
; VI-DAG: v_mac_f16_sdwa v[[C_F16_1]], v[[A_V2_F16]], v[[B_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-DAG: v_mac_f16_e32 v[[C_V2_F16]], v[[A_V2_F16]], v[[B_V2_F16]]
+; VI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[C_F16_1]]
; VI-NOT: and
-; VI-DAG: v_lshl_or_b32 v[[R_V2_F16:[0-9]+]], v[[C_F16_1]], 16, v[[C_V2_F16]]
+; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[C_V2_F16]], v[[R_F16_HI]]
; VI: {{buffer|flat}}_store_dword v[[R_V2_F16]]
; VI: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
index ae2dc9beb2f6a..99b6ab7a6401b 100644
--- a/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
@@ -166,7 +166,8 @@ define amdgpu_kernel void @basic_smax_smin_sgpr(ptr addrspace(1) %out, i32 inreg
; SDAG-VI-NEXT: s_sext_i32_i16 s3, s3
; SDAG-VI-NEXT: v_med3_i32 v1, s2, 0, v0
; SDAG-VI-NEXT: v_med3_i32 v0, s3, 0, v0
-; SDAG-VI-NEXT: v_lshl_or_b32 v2, v0, 16, v1
+; SDAG-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; SDAG-VI-NEXT: v_or_b32_e32 v2, v1, v0
; SDAG-VI-NEXT: v_mov_b32_e32 v0, s0
; SDAG-VI-NEXT: v_mov_b32_e32 v1, s1
; SDAG-VI-NEXT: flat_store_dword v[0:1], v2
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
index b19432807ea40..efad5770a0261 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll
@@ -355,12 +355,14 @@ define i8 @test_vector_reduce_smax_v4i8(<4 x i8> %v) {
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX8-GISEL-NEXT: v_max_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smax_v4i8:
@@ -656,15 +658,17 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) {
; GFX8-GISEL-NEXT: v_max_i16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_i16_e32 v1, s4, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
-; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_max_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smax_v8i8:
@@ -1097,15 +1101,17 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) {
; GFX8-GISEL-NEXT: v_max_i16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_i16_e32 v1, s4, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
-; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_max_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-GISEL-NEXT: v_max_i16_e32 v3, s4, v3
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smax_v16i8:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
index dce58bf30547b..2be894755078a 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll
@@ -355,12 +355,14 @@ define i8 @test_vector_reduce_smin_v4i8(<4 x i8> %v) {
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX8-GISEL-NEXT: v_min_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smin_v4i8:
@@ -656,15 +658,17 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) {
; GFX8-GISEL-NEXT: v_min_i16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_min_i16_e32 v1, s4, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
-; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_min_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smin_v8i8:
@@ -1097,15 +1101,17 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) {
; GFX8-GISEL-NEXT: v_min_i16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_min_i16_e32 v1, s4, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
-; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_min_i16_e32 v2, s4, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-GISEL-NEXT: v_min_i16_e32 v3, s4, v3
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_smin_v16i8:
diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
index 489ef64a86369..2b4a226274b41 100644
--- a/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-umax.ll
@@ -331,12 +331,14 @@ define i8 @test_vector_reduce_umax_v4i8(<4 x i8> %v) {
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
; GFX8-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umax_v4i8:
@@ -615,15 +617,17 @@ define i8 @test_vector_reduce_umax_v8i8(<8 x i8> %v) {
; GFX8-GISEL-NEXT: v_max_u16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_u16_e32 v1, 0, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
-; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
; GFX8-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umax_v8i8:
@@ -1019,15 +1023,17 @@ define i8 @test_vector_reduce_umax_v16i8(<16 x i8> %v) {
; GFX8-GISEL-NEXT: v_max_u16_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_max_u16_e32 v1, 0, v1
; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 8
-; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
; GFX8-GISEL-NEXT: v_max_u16_e32 v2, 0, v2
; GFX8-GISEL-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
; GFX8-GISEL-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX8-GISEL-NEXT: v_max_u16_e32 v3, 0, v3
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: v_and_b32_e32 v1, 0xff, v3
-; GFX8-GISEL-NEXT: v_lshl_or_b32 v0, v1, 24, v0
+; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 24, v1
+; GFX8-GISEL-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-SDAG-LABEL: test_vector_reduce_umax_v16i8:
diff --git a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
index fa7447933d5b3..20789232b1f25 100644
--- a/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
+++ b/llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
@@ -760,19 +760,20 @@ define amdgpu_kernel void @v8i8_multiuse_multiblock(ptr addrspace(1) %src1, ptr
; GFX942-NEXT: ; %bb.3: ; %bb.2
; GFX942-NEXT: v_lshlrev_b16_e32 v3, 8, v1
; GFX942-NEXT: v_and_b32_e32 v4, 0xffffff00, v1
-; GFX942-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT: v_and_b32_e32 v5, 0xffffff00, v0
; GFX942-NEXT: s_mov_b32 s2, 0xc0c0001
+; GFX942-NEXT: v_or_b32_sdwa v3, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX942-NEXT: v_or_b32_sdwa v5, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX942-NEXT: v_perm_b32 v1, 0, v1, s2
; GFX942-NEXT: v_mov_b32_e32 v2, 0
; GFX942-NEXT: v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: v_or_b32_sdwa v5, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT: v_perm_b32 v6, 0, v0, s2
; GFX942-NEXT: s_mov_b32 s3, 0xffff0000
-; GFX942-NEXT: v_perm_b32 v1, 0, v1, s2
+; GFX942-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX942-NEXT: v_and_or_b32 v7, v0, s3, v6
; GFX942-NEXT: v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX942-NEXT: v_lshl_or_b32 v1, v1, 16, v6
+; GFX942-NEXT: v_or_b32_e32 v1, v6, v1
; GFX942-NEXT: global_store_dword v2, v3, s[14:15]
; GFX942-NEXT: global_store_dword v2, v4, s[14:15] offset:8
; GFX942-NEXT: global_store_dword v2, v7, s[14:15] offset:16
>From 01b6f922408abbf0a3e74e506e4d0570b9bbe34b Mon Sep 17 00:00:00 2001
From: Barbara Mitic <Barbara.Mitic at amd.com>
Date: Thu, 11 Jun 2026 08:45:00 +0200
Subject: [PATCH 3/3] [AMDGPU] Select uniform (shl, or) to a scalar
S_LSHL_OR_B32 pseudo
The uniform (or (shl x, y), z) pattern is not matched by the existing
three-op selection, which is gated on divergence and selects the VALU
v_lshl_or_b32; uniform values are instead lowered to separate
s_lshl_b32 + s_or_b32.
Add a scalar pseudo S_LSHL_OR_B32 and select the uniform pattern to it
via a new UniformThreeOpFrag (the non-divergent counterpart of
ThreeOpFrag, reusing HasOneUseBinOp). After register allocation:
- SIFixSGPRCopies promotes the pseudo to v_lshl_or_b32 (moveToVALUImpl)
when an operand turns out to be VGPR-resident, the same as any other
scalar op moved to the VALU; or
- expandPostRAPseudo lowers it to s_lshl_b32 + s_or_b32 when it stays
scalar.
---
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 7 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 44 +
llvm/lib/Target/AMDGPU/SIInstructions.td | 15 +
llvm/lib/Target/AMDGPU/VOP3Instructions.td | 10 +
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 20060 ++++++++--------
.../CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll | 343 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll | 939 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll | 1911 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll | 78 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 5856 ++---
.../CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll | 189 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll | 195 +-
.../AMDGPU/amdgpu-codegenprepare-idiv.ll | 26 +-
.../CodeGen/AMDGPU/calling-conventions.ll | 1557 +-
llvm/test/CodeGen/AMDGPU/ds_read2.ll | 28 +-
.../test/CodeGen/AMDGPU/extract-i8-codegen.ll | 16 +-
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 63 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 503 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 281 +-
llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll | 132 +-
llvm/test/CodeGen/AMDGPU/fptrunc.ll | 13 +-
llvm/test/CodeGen/AMDGPU/fshl.ll | 18 +-
.../AMDGPU/kernel-argument-dag-lowering.ll | 18 +-
llvm/test/CodeGen/AMDGPU/lshl_or-expand.mir | 34 +
llvm/test/CodeGen/AMDGPU/lshl_or-promote.mir | 24 +
llvm/test/CodeGen/AMDGPU/lshl_or.ll | 171 +
llvm/test/CodeGen/AMDGPU/min.ll | 72 +-
.../CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll | 276 +-
llvm/test/CodeGen/AMDGPU/permute_i8.ll | 90 +-
llvm/test/CodeGen/AMDGPU/preload-kernargs.ll | 78 +-
...-alloca-vector-dynamic-idx-bitcasts-llc.ll | 36 +-
llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll | 38 +-
llvm/test/CodeGen/AMDGPU/sdiv.ll | 96 +-
llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll | 48 +-
llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll | 13 +-
.../AMDGPU/triton_regression_no_waterfall.ll | 4 +-
llvm/test/CodeGen/AMDGPU/udiv.ll | 61 +-
37 files changed, 15811 insertions(+), 17532 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/lshl_or-expand.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/lshl_or-promote.mir
create mode 100644 llvm/test/CodeGen/AMDGPU/lshl_or.ll
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index ffe34102b0a4e..b7fd12caf8f15 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -1056,7 +1056,12 @@ bool SIFixSGPRCopies::needToBeConvertedToVALU(V2SCopyInfo *Info) {
unsigned Penalty =
Info->NumSVCopies + Info->SiblingPenalty + Info->NumReadfirstlanes;
- unsigned Profit = Info->SChain.size();
+ // Weight each instruction by how many it expands to, so a fused pseudo
+ // (e.g. S_LSHL_OR_B32 -> S_LSHL_B32 + S_OR_B32) is not mistaken for a
+ // shorter, cheaper chain.
+ unsigned Profit = 0;
+ for (MachineInstr *MI : Info->SChain)
+ Profit += MI->getOpcode() == AMDGPU::S_LSHL_OR_B32 ? 2 : 1;
Info->Score = Penalty > Profit ? 0 : Profit - Penalty;
Info->NeedToBeConvertedToVALU = Info->Score < 3;
return Info->NeedToBeConvertedToVALU;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index ef9d184555bd6..8cbe9f80583e2 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -2092,6 +2092,28 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
const AMDGPU::LaneMaskConstants &LMC = AMDGPU::LaneMaskConstants::get(ST);
switch (MI.getOpcode()) {
default: return TargetInstrInfo::expandPostRAPseudo(MI);
+ case AMDGPU::S_LSHL_OR_B32: {
+ // Expand into s_lshl_b32 + s_or_b32. The earlyclobber on $sdst lets the
+ // shift write Dst directly without aliasing a source.
+ Register Dst = MI.getOperand(0).getReg();
+ MachineOperand Src0 = MI.getOperand(1);
+ MachineOperand Src1 = MI.getOperand(2);
+ const MachineOperand &Src2 = MI.getOperand(3);
+ // The s_or_b32 reads Src2 after the s_lshl_b32, so if a shift operand
+ // aliases Src2 (e.g. (x << c) | x) it must not kill it.
+ if (Src2.isReg()) {
+ if (Src0.isReg() && Src0.isKill() &&
+ RI.regsOverlap(Src0.getReg(), Src2.getReg()))
+ Src0.setIsKill(false);
+ if (Src1.isReg() && Src1.isKill() &&
+ RI.regsOverlap(Src1.getReg(), Src2.getReg()))
+ Src1.setIsKill(false);
+ }
+ BuildMI(MBB, MI, DL, get(AMDGPU::S_LSHL_B32), Dst).add(Src0).add(Src1);
+ BuildMI(MBB, MI, DL, get(AMDGPU::S_OR_B32), Dst).addReg(Dst).add(Src2);
+ MI.eraseFromParent();
+ break;
+ }
case AMDGPU::S_MOV_B64_term:
// This is only a terminator to get the correct spill code placement during
// register allocation.
@@ -8301,6 +8323,28 @@ void SIInstrInfo::moveToVALUImpl(
Inst.eraseFromParent();
}
return;
+ case AMDGPU::S_LSHL_OR_B32: {
+ // A VGPR operand turned up; move to the equivalent VALU instruction.
+ MachineOperand &Dest = Inst.getOperand(0);
+ MachineOperand &Src0 = Inst.getOperand(1);
+ MachineOperand &Src1 = Inst.getOperand(2);
+ MachineOperand &Src2 = Inst.getOperand(3);
+
+ const TargetRegisterClass *NewRC =
+ RI.getEquivalentVGPRClass(MRI.getRegClass(Dest.getReg()));
+ Register DestReg = MRI.createVirtualRegister(NewRC);
+ MachineInstr *NewInstr =
+ BuildMI(*MBB, &Inst, DL, get(AMDGPU::V_LSHL_OR_B32_e64), DestReg)
+ .add(Src0)
+ .add(Src1)
+ .add(Src2);
+
+ legalizeOperands(*NewInstr, MDT);
+ MRI.replaceRegWith(Dest.getReg(), DestReg);
+ addUsersToMoveToVALUWorklist(DestReg, MRI, Worklist);
+ Inst.eraseFromParent();
+ }
+ return;
case AMDGPU::S_LSHL1_ADD_U32:
case AMDGPU::S_LSHL2_ADD_U32:
case AMDGPU::S_LSHL3_ADD_U32:
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 2186f9303a192..bacb1130eadf8 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -464,6 +464,21 @@ def GET_GROUPSTATICSIZE : SPseudoInstSI <(outs SReg_32:$sdst), (ins),
[(set SReg_32:$sdst, (int_amdgcn_groupstaticsize))]>;
} // End let usesCustomInserter = 1, SALU = 1
+// Scalar (x << y) | z for uniform values. SIFixSGPRCopies promotes this to the
+// VALU V_LSHL_OR_B32 if an operand is VGPR-resident, otherwise
+// expandPostRAPseudo lowers it to S_LSHL_B32 + S_OR_B32. The earlyclobber on
+// $sdst keeps the destination from aliasing a source so the expansion can write
+// the shift result into it. Gated on GFX9+, where V_LSHL_OR_B32 exists.
+let Defs = [SCC], Constraints = "@earlyclobber $sdst",
+ SubtargetPredicate = isGFX9Plus in
+def S_LSHL_OR_B32 : SPseudoInstSI <
+ (outs SReg_32:$sdst),
+ (ins SSrc_b32:$src0, SSrc_b32:$src1, SSrc_b32:$src2),
+ [(set i32:$sdst,
+ (UniformThreeOpFrag<cshl_32, or> i32:$src0, i32:$src1, i32:$src2))]> {
+ let Size = 8;
+}
+
// Wrap an instruction by duplicating it, except for setting isTerminator.
class WrapTerminatorInst<SOP_Pseudo base_inst> : SPseudoInstSI<
base_inst.OutOperandList,
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index f2a2f2b3a2499..fd3a3dfd456ec 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -635,6 +635,16 @@ class ThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : ThreeOpFragSDA
}];
}
+// Uniform counterpart of ThreeOpFragSDAG: matches the non-divergent case so it
+// can be selected to a scalar pseudo (e.g. S_LSHL_OR_B32).
+class UniformThreeOpFrag<SDPatternOperator op1, SDPatternOperator op2> : PatFrag<
+ (ops node:$x, node:$y, node:$z),
+ (op2 (HasOneUseBinOp<op1> node:$x, node:$y), node:$z),
+ [{ return !N->isDivergent(); }]> {
+ // GlobalISel chooses scalar vs vector via register banks; disable there.
+ let GISelPredicateCode = [{ return false; }];
+}
+
def shl_0_to_4 : PatFrag<
(ops node:$src0, node:$src1), (shl node:$src0, node:$src1), [{
KnownBits KB = CurDAG->computeKnownBits(N->getOperand(1));
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 8fb907a94fb4a..f2709cb38e1e7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -10145,33 +10145,33 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s83, s28, 8
; GFX9-NEXT: s_lshr_b32 s81, s27, 24
; GFX9-NEXT: v_writelane_b32 v30, s46, 49
-; GFX9-NEXT: s_lshr_b32 s53, s27, 8
+; GFX9-NEXT: s_lshr_b32 s52, s27, 8
; GFX9-NEXT: s_lshr_b32 s82, s26, 16
-; GFX9-NEXT: s_lshr_b32 s67, s26, 8
+; GFX9-NEXT: s_lshr_b32 s51, s26, 8
; GFX9-NEXT: s_lshr_b32 s84, s25, 24
; GFX9-NEXT: s_lshr_b32 s96, s25, 16
; GFX9-NEXT: s_lshr_b32 s65, s25, 8
; GFX9-NEXT: s_lshr_b32 s86, s24, 16
-; GFX9-NEXT: s_lshr_b32 s55, s24, 8
+; GFX9-NEXT: s_lshr_b32 s66, s24, 8
; GFX9-NEXT: s_lshr_b32 s98, s23, 24
; GFX9-NEXT: s_lshr_b32 s87, s23, 16
-; GFX9-NEXT: s_lshr_b32 s66, s23, 8
+; GFX9-NEXT: s_lshr_b32 s55, s23, 8
; GFX9-NEXT: s_lshr_b32 s97, s22, 16
; GFX9-NEXT: s_lshr_b32 s64, s22, 8
; GFX9-NEXT: s_lshr_b32 s49, s21, 24
; GFX9-NEXT: s_lshr_b32 s99, s21, 16
; GFX9-NEXT: s_lshr_b32 s80, s21, 8
-; GFX9-NEXT: s_lshr_b32 s39, s20, 16
+; GFX9-NEXT: s_lshr_b32 s48, s20, 16
; GFX9-NEXT: s_lshr_b32 s70, s20, 8
-; GFX9-NEXT: s_lshr_b32 s48, s19, 24
+; GFX9-NEXT: s_lshr_b32 s39, s19, 24
; GFX9-NEXT: s_lshr_b32 s38, s19, 16
; GFX9-NEXT: s_lshr_b32 s68, s19, 8
; GFX9-NEXT: s_lshr_b32 s54, s18, 16
; GFX9-NEXT: s_lshr_b32 s69, s18, 8
-; GFX9-NEXT: s_lshr_b32 s52, s17, 24
+; GFX9-NEXT: s_lshr_b32 s53, s17, 24
; GFX9-NEXT: s_lshr_b32 s50, s17, 16
; GFX9-NEXT: s_lshr_b32 s71, s17, 8
-; GFX9-NEXT: s_lshr_b32 s51, s16, 16
+; GFX9-NEXT: s_lshr_b32 s67, s16, 16
; GFX9-NEXT: s_lshr_b32 s85, s16, 8
; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
; GFX9-NEXT: s_lshr_b64 s[56:57], s[6:7], 24
@@ -10325,33 +10325,33 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s83, s28, 8
; GFX9-NEXT: s_lshr_b32 s81, s27, 24
; GFX9-NEXT: v_writelane_b32 v30, s46, 49
-; GFX9-NEXT: s_lshr_b32 s53, s27, 8
+; GFX9-NEXT: s_lshr_b32 s52, s27, 8
; GFX9-NEXT: s_lshr_b32 s82, s26, 16
-; GFX9-NEXT: s_lshr_b32 s67, s26, 8
+; GFX9-NEXT: s_lshr_b32 s51, s26, 8
; GFX9-NEXT: s_lshr_b32 s84, s25, 24
; GFX9-NEXT: s_lshr_b32 s96, s25, 16
; GFX9-NEXT: s_lshr_b32 s65, s25, 8
; GFX9-NEXT: s_lshr_b32 s86, s24, 16
-; GFX9-NEXT: s_lshr_b32 s55, s24, 8
+; GFX9-NEXT: s_lshr_b32 s66, s24, 8
; GFX9-NEXT: s_lshr_b32 s98, s23, 24
; GFX9-NEXT: s_lshr_b32 s87, s23, 16
-; GFX9-NEXT: s_lshr_b32 s66, s23, 8
+; GFX9-NEXT: s_lshr_b32 s55, s23, 8
; GFX9-NEXT: s_lshr_b32 s97, s22, 16
; GFX9-NEXT: s_lshr_b32 s64, s22, 8
; GFX9-NEXT: s_lshr_b32 s49, s21, 24
; GFX9-NEXT: s_lshr_b32 s99, s21, 16
; GFX9-NEXT: s_lshr_b32 s80, s21, 8
-; GFX9-NEXT: s_lshr_b32 s39, s20, 16
+; GFX9-NEXT: s_lshr_b32 s48, s20, 16
; GFX9-NEXT: s_lshr_b32 s70, s20, 8
-; GFX9-NEXT: s_lshr_b32 s48, s19, 24
+; GFX9-NEXT: s_lshr_b32 s39, s19, 24
; GFX9-NEXT: s_lshr_b32 s38, s19, 16
; GFX9-NEXT: s_lshr_b32 s68, s19, 8
; GFX9-NEXT: s_lshr_b32 s54, s18, 16
; GFX9-NEXT: s_lshr_b32 s69, s18, 8
-; GFX9-NEXT: s_lshr_b32 s52, s17, 24
+; GFX9-NEXT: s_lshr_b32 s53, s17, 24
; GFX9-NEXT: s_lshr_b32 s50, s17, 16
; GFX9-NEXT: s_lshr_b32 s71, s17, 8
-; GFX9-NEXT: s_lshr_b32 s51, s16, 16
+; GFX9-NEXT: s_lshr_b32 s67, s16, 16
; GFX9-NEXT: s_lshr_b32 s85, s16, 8
; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
; GFX9-NEXT: s_lshr_b64 s[56:57], s[6:7], 24
@@ -10370,166 +10370,146 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24
; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24
; GFX9-NEXT: .LBB13_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v8, s36
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s85
-; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
-; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
-; GFX9-NEXT: v_mov_b32_e32 v21, s52
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v4, s71
-; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
+; GFX9-NEXT: v_mov_b32_e32 v21, s53
+; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
; GFX9-NEXT: v_perm_b32 v2, s17, v4, v1
-; GFX9-NEXT: v_mov_b32_e32 v11, s34
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v21
+; GFX9-NEXT: v_mov_b32_e32 v8, s34
; GFX9-NEXT: v_mov_b32_e32 v4, s69
-; GFX9-NEXT: v_perm_b32 v11, s54, v11, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
-; GFX9-NEXT: v_mov_b32_e32 v22, s48
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
; GFX9-NEXT: v_mov_b32_e32 v6, s68
-; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
+; GFX9-NEXT: v_perm_b32 v8, s54, v8, v1
+; GFX9-NEXT: v_mov_b32_e32 v22, s39
+; GFX9-NEXT: v_lshl_or_b32 v2, v21, 16, v2
; GFX9-NEXT: v_perm_b32 v4, s19, v6, v1
-; GFX9-NEXT: v_mov_b32_e32 v14, s30
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v22
+; GFX9-NEXT: v_mov_b32_e32 v9, s30
; GFX9-NEXT: v_mov_b32_e32 v6, s70
-; GFX9-NEXT: v_perm_b32 v14, s39, v14, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX9-NEXT: v_perm_b32 v7, s20, v6, v1
+; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshl_or_b32 v2, v8, 16, v5
+; GFX9-NEXT: v_mov_b32_e32 v10, s80
+; GFX9-NEXT: v_perm_b32 v11, s20, v6, v1
+; GFX9-NEXT: v_perm_b32 v9, s48, v9, v1
; GFX9-NEXT: v_mov_b32_e32 v23, s49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v14
-; GFX9-NEXT: v_mov_b32_e32 v9, s80
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: v_lshl_or_b32 v2, v22, 16, v4
+; GFX9-NEXT: v_perm_b32 v6, s21, v10, v1
+; GFX9-NEXT: v_mov_b32_e32 v10, s94
+; GFX9-NEXT: v_mov_b32_e32 v12, s64
; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX9-NEXT: v_perm_b32 v6, s21, v9, v1
-; GFX9-NEXT: v_mov_b32_e32 v15, s94
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v23
-; GFX9-NEXT: v_mov_b32_e32 v9, s64
-; GFX9-NEXT: v_perm_b32 v15, s97, v15, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v6, v2
-; GFX9-NEXT: v_perm_b32 v10, s22, v9, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: v_lshl_or_b32 v2, v9, 16, v11
+; GFX9-NEXT: v_mov_b32_e32 v13, s55
+; GFX9-NEXT: v_perm_b32 v12, s22, v12, v1
+; GFX9-NEXT: v_perm_b32 v10, s97, v10, v1
; GFX9-NEXT: v_mov_b32_e32 v24, s98
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v15
-; GFX9-NEXT: v_mov_b32_e32 v12, s66
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: v_lshl_or_b32 v2, v23, 16, v6
+; GFX9-NEXT: v_perm_b32 v13, s23, v13, v1
+; GFX9-NEXT: v_mov_b32_e32 v14, s92
+; GFX9-NEXT: v_mov_b32_e32 v15, s66
; GFX9-NEXT: v_perm_b32 v24, s87, v24, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v10, v2
-; GFX9-NEXT: v_perm_b32 v9, s23, v12, v1
-; GFX9-NEXT: v_mov_b32_e32 v16, s92
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v24
-; GFX9-NEXT: v_mov_b32_e32 v12, s55
-; GFX9-NEXT: v_perm_b32 v16, s86, v16, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v9, v2
-; GFX9-NEXT: v_perm_b32 v13, s24, v12, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: v_lshl_or_b32 v2, v10, 16, v12
+; GFX9-NEXT: v_mov_b32_e32 v16, s65
+; GFX9-NEXT: v_perm_b32 v15, s24, v15, v1
+; GFX9-NEXT: v_perm_b32 v14, s86, v14, v1
; GFX9-NEXT: v_mov_b32_e32 v25, s84
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v16
-; GFX9-NEXT: v_mov_b32_e32 v17, s65
-; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v13, v2
-; GFX9-NEXT: v_perm_b32 v12, s25, v17, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: v_lshl_or_b32 v2, v24, 16, v13
+; GFX9-NEXT: v_perm_b32 v16, s25, v16, v1
; GFX9-NEXT: v_mov_b32_e32 v17, s90
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v25
-; GFX9-NEXT: v_mov_b32_e32 v18, s67
-; GFX9-NEXT: v_perm_b32 v17, s82, v17, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v12, v2
+; GFX9-NEXT: v_mov_b32_e32 v18, s51
+; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: v_lshl_or_b32 v2, v14, 16, v15
+; GFX9-NEXT: v_mov_b32_e32 v7, s36
+; GFX9-NEXT: v_mov_b32_e32 v19, s52
; GFX9-NEXT: v_perm_b32 v18, s26, v18, v1
+; GFX9-NEXT: v_perm_b32 v17, s82, v17, v1
; GFX9-NEXT: v_mov_b32_e32 v26, s81
; GFX9-NEXT: v_readlane_b32 s16, v30, 49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; GFX9-NEXT: v_mov_b32_e32 v19, s53
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: v_lshl_or_b32 v2, v25, 16, v16
+; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
+; GFX9-NEXT: v_perm_b32 v7, s67, v7, v1
; GFX9-NEXT: v_perm_b32 v26, s16, v26, v1
; GFX9-NEXT: v_readlane_b32 s16, v30, 47
-; GFX9-NEXT: v_or_b32_e32 v2, v18, v2
-; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: v_lshl_or_b32 v2, v17, 16, v18
; GFX9-NEXT: v_mov_b32_e32 v20, s88
+; GFX9-NEXT: v_mov_b32_e32 v27, s83
; GFX9-NEXT: v_mov_b32_e32 v28, s16
+; GFX9-NEXT: v_lshl_or_b32 v3, v7, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 48
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v26
-; GFX9-NEXT: v_mov_b32_e32 v27, s83
+; GFX9-NEXT: v_lshl_or_b32 v2, v26, 16, v19
+; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v3, s16, v20, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v19, v2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_perm_b32 v2, s28, v27, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 45
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 46
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v2, s29, v28, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 44
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s78
; GFX9-NEXT: v_readlane_b32 s16, v30, 43
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s44, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 42
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 40
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 41
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s45, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 39
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s76
; GFX9-NEXT: v_readlane_b32 s16, v30, 38
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s42, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 37
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 35
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 36
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s43, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 34
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: v_readlane_b32 s16, v30, 33
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s40, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 32
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 30
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 31
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s41, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 29
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: v_mov_b32_e32 v2, s16
@@ -10537,18 +10517,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: v_readlane_b32 s14, v30, 28
; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s14, v30, 27
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: v_mov_b32_e32 v2, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 25
; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 26
-; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s15, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s14, v30, 24
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: v_mov_b32_e32 v2, s14
@@ -10556,18 +10534,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s62
; GFX9-NEXT: v_readlane_b32 s12, v30, 23
; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s12, v30, 22
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: v_mov_b32_e32 v2, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 20
; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 21
-; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s13, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s12, v30, 19
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: v_mov_b32_e32 v2, s12
@@ -10575,18 +10551,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s60
; GFX9-NEXT: v_readlane_b32 s10, v30, 18
; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s10, v30, 17
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: v_mov_b32_e32 v2, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 15
; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 16
-; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s11, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s10, v30, 14
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: v_mov_b32_e32 v2, s10
@@ -10594,18 +10568,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s58
; GFX9-NEXT: v_readlane_b32 s8, v30, 13
; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s8, v30, 12
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: v_mov_b32_e32 v2, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 10
; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 11
-; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s9, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s8, v30, 9
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: v_mov_b32_e32 v2, s8
@@ -10613,18 +10585,16 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_readlane_b32 s6, v30, 8
; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s6, v30, 7
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 5
; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 6
-; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s7, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s6, v30, 4
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: v_mov_b32_e32 v2, s6
@@ -10632,8 +10602,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: v_readlane_b32 s4, v30, 3
; GFX9-NEXT: v_perm_b32 v3, s4, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s4, v30, 2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_mov_b32_e32 v2, s4
@@ -10642,8 +10611,7 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: v_readlane_b32 s4, v30, 1
; GFX9-NEXT: v_perm_b32 v2, s5, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s4, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: v_readlane_b32 s30, v29, 34
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: v_readlane_b32 s31, v29, 35
@@ -10693,33 +10661,33 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: ; kill: killed $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr85
-; GFX9-NEXT: ; implicit-def: $sgpr51
+; GFX9-NEXT: ; implicit-def: $sgpr67
; GFX9-NEXT: ; implicit-def: $sgpr71
; GFX9-NEXT: ; implicit-def: $sgpr50
-; GFX9-NEXT: ; implicit-def: $sgpr52
+; GFX9-NEXT: ; implicit-def: $sgpr53
; GFX9-NEXT: ; implicit-def: $sgpr69
; GFX9-NEXT: ; implicit-def: $sgpr54
; GFX9-NEXT: ; implicit-def: $sgpr68
; GFX9-NEXT: ; implicit-def: $sgpr38
-; GFX9-NEXT: ; implicit-def: $sgpr48
-; GFX9-NEXT: ; implicit-def: $sgpr70
; GFX9-NEXT: ; implicit-def: $sgpr39
+; GFX9-NEXT: ; implicit-def: $sgpr70
+; GFX9-NEXT: ; implicit-def: $sgpr48
; GFX9-NEXT: ; implicit-def: $sgpr80
; GFX9-NEXT: ; implicit-def: $sgpr99
; GFX9-NEXT: ; implicit-def: $sgpr49
; GFX9-NEXT: ; implicit-def: $sgpr64
; GFX9-NEXT: ; implicit-def: $sgpr97
-; GFX9-NEXT: ; implicit-def: $sgpr66
+; GFX9-NEXT: ; implicit-def: $sgpr55
; GFX9-NEXT: ; implicit-def: $sgpr87
; GFX9-NEXT: ; implicit-def: $sgpr98
-; GFX9-NEXT: ; implicit-def: $sgpr55
+; GFX9-NEXT: ; implicit-def: $sgpr66
; GFX9-NEXT: ; implicit-def: $sgpr86
; GFX9-NEXT: ; implicit-def: $sgpr65
; GFX9-NEXT: ; implicit-def: $sgpr96
; GFX9-NEXT: ; implicit-def: $sgpr84
-; GFX9-NEXT: ; implicit-def: $sgpr67
+; GFX9-NEXT: ; implicit-def: $sgpr51
; GFX9-NEXT: ; implicit-def: $sgpr82
-; GFX9-NEXT: ; implicit-def: $sgpr53
+; GFX9-NEXT: ; implicit-def: $sgpr52
; GFX9-NEXT: ; implicit-def: $sgpr81
; GFX9-NEXT: ; implicit-def: $sgpr83
; GFX9-NEXT: ; implicit-def: $sgpr36
@@ -10914,62 +10882,62 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: s_lshr_b32 s42, s5, 16
; GFX11-NEXT: s_lshr_b32 s34, s27, 16
; GFX11-NEXT: s_lshr_b32 s35, s27, 8
-; GFX11-NEXT: s_lshr_b32 s37, s26, 16
+; GFX11-NEXT: s_lshr_b32 s36, s26, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 1
; GFX11-NEXT: s_lshr_b32 s42, s5, 8
-; GFX11-NEXT: s_lshr_b32 s36, s26, 8
-; GFX11-NEXT: s_lshr_b32 s39, s25, 24
-; GFX11-NEXT: s_lshr_b32 s48, s25, 16
+; GFX11-NEXT: s_lshr_b32 s37, s26, 8
+; GFX11-NEXT: s_lshr_b32 s38, s25, 24
+; GFX11-NEXT: s_lshr_b32 s39, s25, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 2
; GFX11-NEXT: s_lshr_b32 s42, s4, 16
-; GFX11-NEXT: s_lshr_b32 s38, s25, 8
-; GFX11-NEXT: s_lshr_b32 s50, s24, 16
-; GFX11-NEXT: s_lshr_b32 s49, s24, 8
+; GFX11-NEXT: s_lshr_b32 s48, s25, 8
+; GFX11-NEXT: s_lshr_b32 s49, s24, 16
+; GFX11-NEXT: s_lshr_b32 s50, s24, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 3
; GFX11-NEXT: s_lshr_b32 s42, s4, 8
-; GFX11-NEXT: s_lshr_b32 s52, s23, 24
-; GFX11-NEXT: s_lshr_b32 s53, s23, 16
-; GFX11-NEXT: s_lshr_b32 s51, s23, 8
+; GFX11-NEXT: s_lshr_b32 s51, s23, 24
+; GFX11-NEXT: s_lshr_b32 s52, s23, 16
+; GFX11-NEXT: s_lshr_b32 s55, s23, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 4
; GFX11-NEXT: s_lshr_b32 s42, s7, 24
-; GFX11-NEXT: s_lshr_b32 s69, s22, 16
-; GFX11-NEXT: s_lshr_b32 s54, s22, 8
-; GFX11-NEXT: s_lshr_b32 s55, s21, 24
+; GFX11-NEXT: s_lshr_b32 s64, s22, 16
+; GFX11-NEXT: s_lshr_b32 s66, s22, 8
+; GFX11-NEXT: s_lshr_b32 s53, s21, 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 5
; GFX11-NEXT: s_lshr_b32 s42, s7, 16
-; GFX11-NEXT: s_lshr_b32 s64, s21, 16
-; GFX11-NEXT: s_lshr_b32 s65, s21, 8
-; GFX11-NEXT: s_lshr_b32 s82, s20, 16
+; GFX11-NEXT: s_lshr_b32 s54, s21, 16
+; GFX11-NEXT: s_lshr_b32 s70, s21, 8
+; GFX11-NEXT: s_lshr_b32 s71, s20, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 6
; GFX11-NEXT: s_lshr_b32 s42, s7, 8
-; GFX11-NEXT: s_lshr_b32 s68, s20, 8
-; GFX11-NEXT: s_lshr_b32 s66, s19, 24
+; GFX11-NEXT: s_lshr_b32 s80, s20, 8
+; GFX11-NEXT: s_lshr_b32 s65, s19, 24
; GFX11-NEXT: s_lshr_b32 s67, s19, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 7
; GFX11-NEXT: s_lshr_b32 s42, s6, 16
-; GFX11-NEXT: s_lshr_b32 s85, s19, 8
+; GFX11-NEXT: s_lshr_b32 s84, s19, 8
; GFX11-NEXT: s_lshr_b32 s86, s18, 16
; GFX11-NEXT: s_lshr_b32 s87, s18, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 8
; GFX11-NEXT: s_lshr_b32 s42, s6, 8
-; GFX11-NEXT: s_lshr_b32 s70, s17, 24
-; GFX11-NEXT: s_lshr_b32 s71, s17, 16
+; GFX11-NEXT: s_lshr_b32 s68, s17, 24
+; GFX11-NEXT: s_lshr_b32 s69, s17, 16
; GFX11-NEXT: s_lshr_b32 s96, s17, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 9
; GFX11-NEXT: s_lshr_b32 s42, s9, 24
; GFX11-NEXT: s_lshr_b32 s97, s16, 16
; GFX11-NEXT: s_lshr_b32 s98, s16, 8
-; GFX11-NEXT: s_lshr_b32 s80, s3, 24
+; GFX11-NEXT: s_lshr_b32 s81, s3, 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 10
; GFX11-NEXT: s_lshr_b32 s42, s9, 16
-; GFX11-NEXT: s_lshr_b32 s81, s3, 16
+; GFX11-NEXT: s_lshr_b32 s82, s3, 16
; GFX11-NEXT: s_lshr_b32 s99, s3, 8
; GFX11-NEXT: s_lshr_b32 s100, s2, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 11
; GFX11-NEXT: s_lshr_b32 s42, s9, 8
; GFX11-NEXT: s_lshr_b32 s101, s2, 8
; GFX11-NEXT: s_lshr_b32 s83, s1, 24
-; GFX11-NEXT: s_lshr_b32 s84, s1, 16
+; GFX11-NEXT: s_lshr_b32 s85, s1, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 12
; GFX11-NEXT: s_lshr_b32 s42, s8, 16
; GFX11-NEXT: s_lshr_b32 s102, s1, 8
@@ -10987,13 +10955,13 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: s_lshr_b64 s[62:63], s[40:41], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 15
; GFX11-NEXT: s_lshr_b32 s42, s11, 16
-; GFX11-NEXT: s_lshr_b64 s[74:75], s[28:29], 24
-; GFX11-NEXT: s_lshr_b64 s[76:77], s[26:27], 24
+; GFX11-NEXT: s_lshr_b64 s[76:77], s[28:29], 24
+; GFX11-NEXT: s_lshr_b64 s[88:89], s[26:27], 24
; GFX11-NEXT: s_lshr_b64 s[72:73], s[24:25], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 16
; GFX11-NEXT: s_lshr_b32 s42, s11, 8
-; GFX11-NEXT: s_lshr_b64 s[78:79], s[22:23], 24
-; GFX11-NEXT: s_lshr_b64 s[88:89], s[20:21], 24
+; GFX11-NEXT: s_lshr_b64 s[74:75], s[22:23], 24
+; GFX11-NEXT: s_lshr_b64 s[78:79], s[20:21], 24
; GFX11-NEXT: s_lshr_b64 s[90:91], s[18:19], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 17
; GFX11-NEXT: s_lshr_b32 s42, s10, 16
@@ -11116,62 +11084,62 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: s_lshr_b32 s42, s9, 16
; GFX11-NEXT: s_lshr_b32 s34, s27, 16
; GFX11-NEXT: s_lshr_b32 s35, s27, 8
-; GFX11-NEXT: s_lshr_b32 s37, s26, 16
+; GFX11-NEXT: s_lshr_b32 s36, s26, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 11
; GFX11-NEXT: s_lshr_b32 s42, s9, 8
-; GFX11-NEXT: s_lshr_b32 s36, s26, 8
-; GFX11-NEXT: s_lshr_b32 s39, s25, 24
-; GFX11-NEXT: s_lshr_b32 s48, s25, 16
+; GFX11-NEXT: s_lshr_b32 s37, s26, 8
+; GFX11-NEXT: s_lshr_b32 s38, s25, 24
+; GFX11-NEXT: s_lshr_b32 s39, s25, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 12
; GFX11-NEXT: s_lshr_b32 s42, s8, 16
-; GFX11-NEXT: s_lshr_b32 s38, s25, 8
-; GFX11-NEXT: s_lshr_b32 s50, s24, 16
-; GFX11-NEXT: s_lshr_b32 s49, s24, 8
+; GFX11-NEXT: s_lshr_b32 s48, s25, 8
+; GFX11-NEXT: s_lshr_b32 s49, s24, 16
+; GFX11-NEXT: s_lshr_b32 s50, s24, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 13
; GFX11-NEXT: s_lshr_b32 s42, s8, 8
-; GFX11-NEXT: s_lshr_b32 s52, s23, 24
-; GFX11-NEXT: s_lshr_b32 s53, s23, 16
-; GFX11-NEXT: s_lshr_b32 s51, s23, 8
+; GFX11-NEXT: s_lshr_b32 s51, s23, 24
+; GFX11-NEXT: s_lshr_b32 s52, s23, 16
+; GFX11-NEXT: s_lshr_b32 s55, s23, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 14
; GFX11-NEXT: s_lshr_b32 s42, s11, 24
-; GFX11-NEXT: s_lshr_b32 s69, s22, 16
-; GFX11-NEXT: s_lshr_b32 s54, s22, 8
-; GFX11-NEXT: s_lshr_b32 s55, s21, 24
+; GFX11-NEXT: s_lshr_b32 s64, s22, 16
+; GFX11-NEXT: s_lshr_b32 s66, s22, 8
+; GFX11-NEXT: s_lshr_b32 s53, s21, 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 15
; GFX11-NEXT: s_lshr_b32 s42, s11, 16
-; GFX11-NEXT: s_lshr_b32 s64, s21, 16
-; GFX11-NEXT: s_lshr_b32 s65, s21, 8
-; GFX11-NEXT: s_lshr_b32 s82, s20, 16
+; GFX11-NEXT: s_lshr_b32 s54, s21, 16
+; GFX11-NEXT: s_lshr_b32 s70, s21, 8
+; GFX11-NEXT: s_lshr_b32 s71, s20, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 16
; GFX11-NEXT: s_lshr_b32 s42, s11, 8
-; GFX11-NEXT: s_lshr_b32 s68, s20, 8
-; GFX11-NEXT: s_lshr_b32 s66, s19, 24
+; GFX11-NEXT: s_lshr_b32 s80, s20, 8
+; GFX11-NEXT: s_lshr_b32 s65, s19, 24
; GFX11-NEXT: s_lshr_b32 s67, s19, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 17
; GFX11-NEXT: s_lshr_b32 s42, s10, 16
-; GFX11-NEXT: s_lshr_b32 s85, s19, 8
+; GFX11-NEXT: s_lshr_b32 s84, s19, 8
; GFX11-NEXT: s_lshr_b32 s86, s18, 16
; GFX11-NEXT: s_lshr_b32 s87, s18, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 18
; GFX11-NEXT: s_lshr_b32 s42, s10, 8
-; GFX11-NEXT: s_lshr_b32 s70, s17, 24
-; GFX11-NEXT: s_lshr_b32 s71, s17, 16
+; GFX11-NEXT: s_lshr_b32 s68, s17, 24
+; GFX11-NEXT: s_lshr_b32 s69, s17, 16
; GFX11-NEXT: s_lshr_b32 s96, s17, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 19
; GFX11-NEXT: s_lshr_b32 s42, s13, 24
; GFX11-NEXT: s_lshr_b32 s97, s16, 16
; GFX11-NEXT: s_lshr_b32 s98, s16, 8
-; GFX11-NEXT: s_lshr_b32 s80, s3, 24
+; GFX11-NEXT: s_lshr_b32 s81, s3, 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 20
; GFX11-NEXT: s_lshr_b32 s42, s13, 16
-; GFX11-NEXT: s_lshr_b32 s81, s3, 16
+; GFX11-NEXT: s_lshr_b32 s82, s3, 16
; GFX11-NEXT: s_lshr_b32 s99, s3, 8
; GFX11-NEXT: s_lshr_b32 s100, s2, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 21
; GFX11-NEXT: s_lshr_b32 s42, s13, 8
; GFX11-NEXT: s_lshr_b32 s101, s2, 8
; GFX11-NEXT: s_lshr_b32 s83, s1, 24
-; GFX11-NEXT: s_lshr_b32 s84, s1, 16
+; GFX11-NEXT: s_lshr_b32 s85, s1, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 22
; GFX11-NEXT: s_lshr_b32 s42, s12, 16
; GFX11-NEXT: s_lshr_b32 s102, s1, 8
@@ -11189,13 +11157,13 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: s_lshr_b64 s[62:63], s[40:41], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 25
; GFX11-NEXT: s_lshr_b32 s42, s15, 16
-; GFX11-NEXT: s_lshr_b64 s[74:75], s[28:29], 24
-; GFX11-NEXT: s_lshr_b64 s[76:77], s[26:27], 24
+; GFX11-NEXT: s_lshr_b64 s[76:77], s[28:29], 24
+; GFX11-NEXT: s_lshr_b64 s[88:89], s[26:27], 24
; GFX11-NEXT: s_lshr_b64 s[72:73], s[24:25], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 26
; GFX11-NEXT: s_lshr_b32 s42, s15, 8
-; GFX11-NEXT: s_lshr_b64 s[78:79], s[22:23], 24
-; GFX11-NEXT: s_lshr_b64 s[88:89], s[20:21], 24
+; GFX11-NEXT: s_lshr_b64 s[74:75], s[22:23], 24
+; GFX11-NEXT: s_lshr_b64 s[78:79], s[20:21], 24
; GFX11-NEXT: s_lshr_b64 s[90:91], s[18:19], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 27
; GFX11-NEXT: s_lshr_b32 s42, s14, 16
@@ -11233,240 +11201,208 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: v_writelane_b32 v25, s42, 7
; GFX11-NEXT: s_lshr_b64 s[42:43], s[4:5], 24
; GFX11-NEXT: .LBB13_3: ; %end
-; GFX11-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v2, s103, s30, v1
+; GFX11-NEXT: v_mov_b32_e32 v12, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, s103, s30, v12
+; GFX11-NEXT: v_perm_b32 v2, s0, s104, v12
+; GFX11-NEXT: v_perm_b32 v3, s1, s102, v12
+; GFX11-NEXT: v_perm_b32 v4, s100, s94, v12
+; GFX11-NEXT: v_perm_b32 v5, s2, s101, v12
+; GFX11-NEXT: v_perm_b32 v6, s3, s99, v12
+; GFX11-NEXT: v_perm_b32 v20, s85, s83, v12
+; GFX11-NEXT: v_perm_b32 v21, s82, s81, v12
+; GFX11-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX11-NEXT: v_perm_b32 v7, s97, s92, v12
+; GFX11-NEXT: v_perm_b32 v8, s16, s98, v12
+; GFX11-NEXT: v_lshl_or_b32 v2, v20, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v4, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v4, v21, 16, v6
+; GFX11-NEXT: v_perm_b32 v9, s17, s96, v12
+; GFX11-NEXT: v_perm_b32 v10, s86, s90, v12
+; GFX11-NEXT: v_perm_b32 v11, s18, s87, v12
+; GFX11-NEXT: v_perm_b32 v13, s19, s84, v12
+; GFX11-NEXT: v_perm_b32 v22, s69, s68, v12
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
+; GFX11-NEXT: v_perm_b32 v4, s67, s65, v12
+; GFX11-NEXT: v_perm_b32 v16, s21, s70, v12
+; GFX11-NEXT: v_lshl_or_b32 v1, v7, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v2, v22, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v3, v10, 16, v11
+; GFX11-NEXT: v_lshl_or_b32 v4, v4, 16, v13
+; GFX11-NEXT: v_perm_b32 v5, s54, s53, v12
+; GFX11-NEXT: v_perm_b32 v6, s49, s72, v12
+; GFX11-NEXT: v_perm_b32 v7, s25, s48, v12
+; GFX11-NEXT: v_perm_b32 v8, s39, s38, v12
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:16
+; GFX11-NEXT: v_lshl_or_b32 v2, v5, 16, v16
+; GFX11-NEXT: v_perm_b32 v5, s24, s50, v12
+; GFX11-NEXT: v_perm_b32 v9, s26, s37, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 7
+; GFX11-NEXT: v_perm_b32 v14, s71, s78, v12
+; GFX11-NEXT: v_perm_b32 v15, s20, s80, v12
+; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v6, v8, 16, v7
+; GFX11-NEXT: v_perm_b32 v7, s36, s88, v12
+; GFX11-NEXT: v_perm_b32 v17, s64, s74, v12
+; GFX11-NEXT: v_perm_b32 v18, s22, s66, v12
+; GFX11-NEXT: v_perm_b32 v19, s23, s55, v12
+; GFX11-NEXT: v_perm_b32 v4, s52, s51, v12
+; GFX11-NEXT: v_perm_b32 v8, s27, s35, v12
+; GFX11-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-NEXT: v_perm_b32 v9, s34, vcc_hi, v12
+; GFX11-NEXT: v_perm_b32 v10, s28, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 6
+; GFX11-NEXT: v_lshl_or_b32 v1, v14, 16, v15
+; GFX11-NEXT: v_lshl_or_b32 v3, v17, 16, v18
+; GFX11-NEXT: v_lshl_or_b32 v4, v4, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-NEXT: v_perm_b32 v9, s0, s76, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 5
+; GFX11-NEXT: v_readlane_b32 s1, v25, 4
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-NEXT: v_lshl_or_b32 v1, v9, 16, v10
+; GFX11-NEXT: v_perm_b32 v2, s29, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 3
; GFX11-NEXT: v_readlane_b32 s30, v24, 7
; GFX11-NEXT: v_readlane_b32 s31, v24, 8
+; GFX11-NEXT: v_readlane_b32 s104, v24, 6
; GFX11-NEXT: v_readlane_b32 s103, v24, 5
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_perm_b32 v18, s84, s83, v1
-; GFX11-NEXT: v_perm_b32 v3, s0, s104, v1
-; GFX11-NEXT: v_perm_b32 v4, s1, s102, v1
-; GFX11-NEXT: v_perm_b32 v5, s100, s94, v1
-; GFX11-NEXT: v_perm_b32 v19, s81, s80, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v6, s2, s101, v1
-; GFX11-NEXT: v_perm_b32 v7, s3, s99, v1
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-NEXT: v_perm_b32 v8, s97, s92, v1
-; GFX11-NEXT: v_or_b32_e32 v3, v4, v18
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v19
-; GFX11-NEXT: v_perm_b32 v11, s86, s90, v1
-; GFX11-NEXT: v_perm_b32 v20, s71, s70, v1
-; GFX11-NEXT: v_perm_b32 v21, s67, s66, v1
-; GFX11-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX11-NEXT: v_or_b32_e32 v5, v7, v5
-; GFX11-NEXT: v_perm_b32 v9, s16, s98, v1
-; GFX11-NEXT: v_perm_b32 v10, s17, s96, v1
-; GFX11-NEXT: v_perm_b32 v12, s18, s87, v1
-; GFX11-NEXT: v_perm_b32 v13, s19, s85, v1
-; GFX11-NEXT: v_perm_b32 v22, s64, s55, v1
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v20
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v21
-; GFX11-NEXT: v_perm_b32 v14, s82, s88, v1
-; GFX11-NEXT: v_perm_b32 v17, s21, s65, v1
-; GFX11-NEXT: v_or_b32_e32 v2, v9, v2
-; GFX11-NEXT: v_or_b32_e32 v3, v10, v3
-; GFX11-NEXT: v_or_b32_e32 v4, v12, v4
-; GFX11-NEXT: v_or_b32_e32 v5, v13, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v22
-; GFX11-NEXT: v_perm_b32 v15, s69, s78, v1
-; GFX11-NEXT: v_perm_b32 v16, s20, s68, v1
-; GFX11-NEXT: v_perm_b32 v6, s53, s52, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v14
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:16
-; GFX11-NEXT: v_or_b32_e32 v3, v17, v8
-; GFX11-NEXT: v_perm_b32 v8, s48, s39, v1
-; GFX11-NEXT: v_perm_b32 v9, s22, s54, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v15
-; GFX11-NEXT: v_or_b32_e32 v2, v16, v7
-; GFX11-NEXT: v_perm_b32 v5, s50, s72, v1
-; GFX11-NEXT: v_perm_b32 v7, s23, s51, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v11, s25, s38, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_readlane_b32 s0, v25, 6
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-NEXT: v_or_b32_e32 v5, v7, v6
-; GFX11-NEXT: v_or_b32_e32 v7, v11, v8
-; GFX11-NEXT: v_perm_b32 v11, s0, s74, v1
-; GFX11-NEXT: v_readlane_b32 s0, v25, 3
-; GFX11-NEXT: v_readlane_b32 s1, v25, 4
-; GFX11-NEXT: v_perm_b32 v9, s24, s49, v1
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:32
-; GFX11-NEXT: v_perm_b32 v12, s37, s76, v1
-; GFX11-NEXT: v_perm_b32 v8, s26, s36, v1
-; GFX11-NEXT: v_perm_b32 v2, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v25, 7
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
-; GFX11-NEXT: v_perm_b32 v10, s34, vcc_hi, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
-; GFX11-NEXT: v_perm_b32 v4, s28, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v25, 5
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT: v_perm_b32 v9, s27, s35, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX11-NEXT: v_perm_b32 v10, s29, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v25, 1
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT: v_readlane_b32 s1, v26, 31
-; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
-; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
-; GFX11-NEXT: v_perm_b32 v12, s0, s62, v1
+; GFX11-NEXT: v_perm_b32 v3, s1, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v25, 2
-; GFX11-NEXT: v_readlane_b32 s104, v24, 6
-; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:48
+; GFX11-NEXT: v_readlane_b32 s1, v26, 31
; GFX11-NEXT: v_readlane_b32 s102, v24, 4
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
-; GFX11-NEXT: v_perm_b32 v4, s40, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 30
; GFX11-NEXT: v_readlane_b32 s101, v24, 3
+; GFX11-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-NEXT: v_perm_b32 v4, s40, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 1
; GFX11-NEXT: v_readlane_b32 s100, v24, 2
; GFX11-NEXT: v_readlane_b32 s99, v24, 1
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v25, 0
-; GFX11-NEXT: v_readlane_b32 s1, v26, 26
; GFX11-NEXT: v_readlane_b32 s98, v24, 0
; GFX11-NEXT: v_readlane_b32 s97, v23, 31
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v10
-; GFX11-NEXT: v_perm_b32 v5, s41, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 28
+; GFX11-NEXT: v_perm_b32 v5, s0, s62, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 0
; GFX11-NEXT: v_readlane_b32 s96, v23, 30
; GFX11-NEXT: v_readlane_b32 s87, v23, 29
; GFX11-NEXT: v_readlane_b32 s86, v23, 28
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX11-NEXT: v_perm_b32 v11, s0, s60, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 25
+; GFX11-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-NEXT: v_perm_b32 v6, s41, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 30
; GFX11-NEXT: v_readlane_b32 s85, v23, 27
; GFX11-NEXT: v_readlane_b32 s84, v23, 26
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:64
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v11
-; GFX11-NEXT: v_perm_b32 v6, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 29
-; GFX11-NEXT: v_readlane_b32 s1, v26, 21
; GFX11-NEXT: v_readlane_b32 s83, v23, 25
; GFX11-NEXT: v_readlane_b32 s82, v23, 24
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v6
-; GFX11-NEXT: v_perm_b32 v8, s14, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 27
+; GFX11-NEXT: v_perm_b32 v7, s1, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 29
+; GFX11-NEXT: v_readlane_b32 s1, v26, 26
; GFX11-NEXT: v_readlane_b32 s81, v23, 23
; GFX11-NEXT: v_readlane_b32 s80, v23, 22
+; GFX11-NEXT: v_lshl_or_b32 v4, v7, 16, v6
+; GFX11-NEXT: v_perm_b32 v8, s14, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 28
; GFX11-NEXT: v_readlane_b32 s71, v23, 21
-; GFX11-NEXT: v_or_b32_e32 v6, v8, v9
-; GFX11-NEXT: v_perm_b32 v10, s15, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 23
; GFX11-NEXT: v_readlane_b32 s70, v23, 20
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:64
; GFX11-NEXT: v_readlane_b32 s69, v23, 19
+; GFX11-NEXT: v_perm_b32 v9, s0, s60, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 27
; GFX11-NEXT: v_readlane_b32 s68, v23, 18
-; GFX11-NEXT: v_or_b32_e32 v7, v10, v11
-; GFX11-NEXT: v_perm_b32 v12, s0, s58, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 24
; GFX11-NEXT: v_readlane_b32 s67, v23, 17
; GFX11-NEXT: v_readlane_b32 s66, v23, 16
+; GFX11-NEXT: v_lshl_or_b32 v5, v9, 16, v8
+; GFX11-NEXT: v_perm_b32 v10, s15, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 25
; GFX11-NEXT: v_readlane_b32 s65, v23, 15
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
-; GFX11-NEXT: v_perm_b32 v8, s12, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 20
; GFX11-NEXT: v_readlane_b32 s64, v23, 14
; GFX11-NEXT: v_readlane_b32 s55, v23, 13
; GFX11-NEXT: v_readlane_b32 s54, v23, 12
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 22
-; GFX11-NEXT: v_readlane_b32 s1, v26, 16
+; GFX11-NEXT: v_perm_b32 v11, s1, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 24
+; GFX11-NEXT: v_readlane_b32 s1, v26, 21
; GFX11-NEXT: v_readlane_b32 s53, v23, 11
; GFX11-NEXT: v_readlane_b32 s52, v23, 10
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
-; GFX11-NEXT: v_perm_b32 v9, s13, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 18
+; GFX11-NEXT: v_lshl_or_b32 v6, v11, 16, v10
+; GFX11-NEXT: v_perm_b32 v7, s12, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 23
; GFX11-NEXT: v_readlane_b32 s51, v23, 9
; GFX11-NEXT: v_readlane_b32 s50, v23, 8
; GFX11-NEXT: v_readlane_b32 s49, v23, 7
-; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
-; GFX11-NEXT: v_perm_b32 v11, s0, s56, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 15
; GFX11-NEXT: v_readlane_b32 s48, v23, 6
+; GFX11-NEXT: v_perm_b32 v8, s0, s58, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 22
; GFX11-NEXT: v_readlane_b32 s39, v23, 5
; GFX11-NEXT: v_readlane_b32 s38, v23, 4
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
-; GFX11-NEXT: v_perm_b32 v2, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 19
-; GFX11-NEXT: v_readlane_b32 s1, v26, 11
; GFX11-NEXT: v_readlane_b32 s37, v23, 3
+; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-NEXT: v_perm_b32 v9, s13, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 20
; GFX11-NEXT: v_readlane_b32 s36, v23, 2
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX11-NEXT: v_perm_b32 v4, s10, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 17
; GFX11-NEXT: v_readlane_b32 s35, v23, 1
; GFX11-NEXT: v_readlane_b32 s34, v23, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT: v_perm_b32 v10, s11, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, s1, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 19
+; GFX11-NEXT: v_readlane_b32 s1, v26, 16
+; GFX11-NEXT: v_lshl_or_b32 v8, v1, 16, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v2, s10, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 18
+; GFX11-NEXT: v_perm_b32 v3, s0, s56, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 17
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
-; GFX11-NEXT: v_perm_b32 v12, s0, s46, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-NEXT: v_perm_b32 v4, s11, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v10, s1, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 14
+; GFX11-NEXT: v_readlane_b32 s1, v26, 11
+; GFX11-NEXT: v_lshl_or_b32 v2, v10, 16, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v11, s8, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 13
+; GFX11-NEXT: v_perm_b32 v3, s0, s46, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
-; GFX11-NEXT: v_perm_b32 v4, s8, s0, v1
+; GFX11-NEXT: v_lshl_or_b32 v3, v3, 16, v11
+; GFX11-NEXT: v_perm_b32 v4, s9, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v9, s1, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 9
; GFX11-NEXT: v_readlane_b32 s1, v26, 6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v5, s9, s0, v1
+; GFX11-NEXT: v_lshl_or_b32 v4, v9, 16, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v10, s6, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 8
+; GFX11-NEXT: v_perm_b32 v9, s0, s44, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v10
-; GFX11-NEXT: v_perm_b32 v11, s0, s44, v1
+; GFX11-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; GFX11-NEXT: v_perm_b32 v11, s7, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v13, s1, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 4
; GFX11-NEXT: v_readlane_b32 s1, v26, 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX11-NEXT: v_perm_b32 v12, s6, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v10, v12, v11
-; GFX11-NEXT: v_perm_b32 v14, s7, s0, v1
+; GFX11-NEXT: v_lshl_or_b32 v10, v13, 16, v11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v11, s4, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v11, v14, v13
-; GFX11-NEXT: v_perm_b32 v12, s0, s42, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT: v_perm_b32 v13, s4, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX11-NEXT: v_perm_b32 v13, s1, s0, v1
+; GFX11-NEXT: v_perm_b32 v13, s0, s42, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_perm_b32 v1, s5, s0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v13, v1, v13
+; GFX11-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX11-NEXT: v_perm_b32 v13, s5, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v12, s1, s0, v12
+; GFX11-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX11-NEXT: s_clause 0x2
-; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:80
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:96
-; GFX11-NEXT: scratch_store_b128 v0, v[10:13], off offset:112
+; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:80
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:96
+; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:112
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Reload
; GFX11-NEXT: scratch_load_b32 v23, off, s32
@@ -11485,51 +11421,51 @@ define inreg <128 x i8> @bitcast_v32i32_to_v128i8_scalar(<32 x i32> inreg %a, i3
; GFX11-NEXT: ; implicit-def: $sgpr103
; GFX11-NEXT: ; implicit-def: $sgpr30
; GFX11-NEXT: ; implicit-def: $sgpr102
-; GFX11-NEXT: ; implicit-def: $sgpr84
+; GFX11-NEXT: ; implicit-def: $sgpr85
; GFX11-NEXT: ; implicit-def: $sgpr83
; GFX11-NEXT: ; implicit-def: $sgpr101
; GFX11-NEXT: ; implicit-def: $sgpr100
; GFX11-NEXT: ; implicit-def: $sgpr94
; GFX11-NEXT: ; implicit-def: $sgpr99
+; GFX11-NEXT: ; implicit-def: $sgpr82
; GFX11-NEXT: ; implicit-def: $sgpr81
-; GFX11-NEXT: ; implicit-def: $sgpr80
; GFX11-NEXT: ; implicit-def: $sgpr98
; GFX11-NEXT: ; implicit-def: $sgpr97
; GFX11-NEXT: ; implicit-def: $sgpr92
; GFX11-NEXT: ; implicit-def: $sgpr96
-; GFX11-NEXT: ; implicit-def: $sgpr71
-; GFX11-NEXT: ; implicit-def: $sgpr70
+; GFX11-NEXT: ; implicit-def: $sgpr69
+; GFX11-NEXT: ; implicit-def: $sgpr68
; GFX11-NEXT: ; implicit-def: $sgpr87
; GFX11-NEXT: ; implicit-def: $sgpr86
; GFX11-NEXT: ; implicit-def: $sgpr90
-; GFX11-NEXT: ; implicit-def: $sgpr85
+; GFX11-NEXT: ; implicit-def: $sgpr84
; GFX11-NEXT: ; implicit-def: $sgpr67
-; GFX11-NEXT: ; implicit-def: $sgpr66
-; GFX11-NEXT: ; implicit-def: $sgpr68
-; GFX11-NEXT: ; implicit-def: $sgpr82
-; GFX11-NEXT: ; implicit-def: $sgpr88
; GFX11-NEXT: ; implicit-def: $sgpr65
-; GFX11-NEXT: ; implicit-def: $sgpr64
-; GFX11-NEXT: ; implicit-def: $sgpr55
-; GFX11-NEXT: ; implicit-def: $sgpr54
-; GFX11-NEXT: ; implicit-def: $sgpr69
+; GFX11-NEXT: ; implicit-def: $sgpr80
+; GFX11-NEXT: ; implicit-def: $sgpr71
; GFX11-NEXT: ; implicit-def: $sgpr78
-; GFX11-NEXT: ; implicit-def: $sgpr51
+; GFX11-NEXT: ; implicit-def: $sgpr70
+; GFX11-NEXT: ; implicit-def: $sgpr54
; GFX11-NEXT: ; implicit-def: $sgpr53
+; GFX11-NEXT: ; implicit-def: $sgpr66
+; GFX11-NEXT: ; implicit-def: $sgpr64
+; GFX11-NEXT: ; implicit-def: $sgpr74
+; GFX11-NEXT: ; implicit-def: $sgpr55
; GFX11-NEXT: ; implicit-def: $sgpr52
-; GFX11-NEXT: ; implicit-def: $sgpr49
+; GFX11-NEXT: ; implicit-def: $sgpr51
; GFX11-NEXT: ; implicit-def: $sgpr50
+; GFX11-NEXT: ; implicit-def: $sgpr49
; GFX11-NEXT: ; implicit-def: $sgpr72
-; GFX11-NEXT: ; implicit-def: $sgpr38
; GFX11-NEXT: ; implicit-def: $sgpr48
; GFX11-NEXT: ; implicit-def: $sgpr39
-; GFX11-NEXT: ; implicit-def: $sgpr36
+; GFX11-NEXT: ; implicit-def: $sgpr38
; GFX11-NEXT: ; implicit-def: $sgpr37
+; GFX11-NEXT: ; implicit-def: $sgpr36
; GFX11-NEXT: ; implicit-def: $sgpr35
; GFX11-NEXT: ; implicit-def: $sgpr34
; GFX11-NEXT: ; implicit-def: $vcc_hi
+; GFX11-NEXT: ; implicit-def: $sgpr88
; GFX11-NEXT: ; implicit-def: $sgpr76
-; GFX11-NEXT: ; implicit-def: $sgpr74
; GFX11-NEXT: ; implicit-def: $sgpr62
; GFX11-NEXT: ; implicit-def: $sgpr60
; GFX11-NEXT: ; implicit-def: $sgpr58
@@ -19586,99 +19522,99 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:324
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:320
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:316
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:312
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:308
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:304
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:296
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:288
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:276
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:272
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:268
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:264
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:260
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:256
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:252
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:236
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:228
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:216
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:212
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:200
+; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:200
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:196
-; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:192
+; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:192
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:188
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:184
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:180
@@ -19687,371 +19623,315 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:168
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:164
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:160
-; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:156
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:156
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:152
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:148
-; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:144
-; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:140
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:144
+; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:140
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:136
-; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:132
-; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:128
-; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:124
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:132
+; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:128
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:124
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:120
-; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:116
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:108
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:108
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:100
-; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:92
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:76
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:64
-; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:48
-; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:12
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(41)
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(41)
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(39)
+; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(39)
+; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(37)
+; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(37)
+; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(35)
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(35)
+; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(33)
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(33)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(32)
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB15_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
-; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
-; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
-; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
-; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
-; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v45, v26
+; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_perm_b32 v12, v42, v41, s4
+; GFX9-NEXT: v_perm_b32 v13, v40, v54, s4
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX9-NEXT: v_perm_b32 v13, v55, v53, s4
+; GFX9-NEXT: v_perm_b32 v14, v52, v50, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_perm_b32 v14, v51, v49, s4
+; GFX9-NEXT: v_perm_b32 v15, v48, v38, s4
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX9-NEXT: v_perm_b32 v15, v39, v37, s4
+; GFX9-NEXT: v_perm_b32 v16, v35, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; GFX9-NEXT: v_perm_b32 v16, v36, v34, s4
+; GFX9-NEXT: v_perm_b32 v17, v32, v17, s4
+; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX9-NEXT: v_perm_b32 v17, v33, v63, s4
+; GFX9-NEXT: v_perm_b32 v18, v61, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: v_perm_b32 v18, v62, v60, s4
+; GFX9-NEXT: v_perm_b32 v19, v58, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX9-NEXT: v_perm_b32 v19, v59, v57, s4
+; GFX9-NEXT: v_perm_b32 v20, v47, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; GFX9-NEXT: v_perm_b32 v20, v56, v46, s4
+; GFX9-NEXT: v_perm_b32 v21, v44, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX9-NEXT: v_perm_b32 v21, v45, v43, s4
+; GFX9-NEXT: v_perm_b32 v22, v31, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; GFX9-NEXT: v_perm_b32 v22, v30, v29, s4
+; GFX9-NEXT: v_perm_b32 v23, v28, v23, s4
+; GFX9-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX9-NEXT: v_perm_b32 v23, v27, v26, s4
+; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
+; GFX9-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: v_mov_b32_e32 v44, v45
+; GFX9-NEXT: v_mov_b32_e32 v54, v53
+; GFX9-NEXT: v_mov_b32_e32 v40, v55
+; GFX9-NEXT: v_mov_b32_e32 v50, v49
+; GFX9-NEXT: v_mov_b32_e32 v52, v51
+; GFX9-NEXT: v_mov_b32_e32 v38, v37
+; GFX9-NEXT: v_mov_b32_e32 v48, v39
+; GFX9-NEXT: v_mov_b32_e32 v35, v34
+; GFX9-NEXT: v_mov_b32_e32 v32, v63
+; GFX9-NEXT: v_mov_b32_e32 v61, v60
+; GFX9-NEXT: v_mov_b32_e32 v58, v57
; GFX9-NEXT: v_mov_b32_e32 v47, v46
-; GFX9-NEXT: v_mov_b32_e32 v57, v56
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
+; GFX9-NEXT: v_perm_b32 v43, v45, v43, s4
+; GFX9-NEXT: v_lshl_or_b32 v31, v43, 16, v31
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB15_3
; GFX9-NEXT: .LBB15_2:
-; GFX9-NEXT: v_mov_b32_e32 v57, v56
+; GFX9-NEXT: v_mov_b32_e32 v40, v55
+; GFX9-NEXT: v_mov_b32_e32 v54, v53
+; GFX9-NEXT: v_mov_b32_e32 v52, v51
+; GFX9-NEXT: v_mov_b32_e32 v50, v49
+; GFX9-NEXT: v_mov_b32_e32 v48, v39
+; GFX9-NEXT: v_mov_b32_e32 v38, v37
+; GFX9-NEXT: v_mov_b32_e32 v35, v34
+; GFX9-NEXT: v_mov_b32_e32 v32, v63
+; GFX9-NEXT: v_mov_b32_e32 v61, v60
+; GFX9-NEXT: v_mov_b32_e32 v58, v57
; GFX9-NEXT: v_mov_b32_e32 v47, v46
-; GFX9-NEXT: v_mov_b32_e32 v45, v26
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
+; GFX9-NEXT: v_mov_b32_e32 v44, v45
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: .LBB15_3: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v43, v44
-; GFX9-NEXT: v_mov_b32_e32 v44, v45
-; GFX9-NEXT: v_mov_b32_e32 v45, v47
-; GFX9-NEXT: v_mov_b32_e32 v46, v57
-; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v43, v44
+; GFX9-NEXT: v_mov_b32_e32 v44, v47
+; GFX9-NEXT: v_mov_b32_e32 v47, v32
; GFX9-NEXT: s_cbranch_vccnz .LBB15_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -20152,250 +20032,258 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v10
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v10, v10, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_add_u32_e32 v16, 3, v32
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; GFX9-NEXT: s_add_i32 s6, s6, 3
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_add_u32_e32 v14, 3, v48
-; GFX9-NEXT: v_perm_b32 v14, v14, v39, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v15, 3, v36
-; GFX9-NEXT: v_perm_b32 v15, v15, v35, s5
-; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s5
-; GFX9-NEXT: v_add_u32_e32 v17, 3, v60
-; GFX9-NEXT: s_waitcnt vmcnt(16)
-; GFX9-NEXT: v_perm_b32 v17, v17, v18, s5
-; GFX9-NEXT: v_add_u32_e32 v18, 3, v57
-; GFX9-NEXT: s_waitcnt vmcnt(15)
-; GFX9-NEXT: v_perm_b32 v18, v18, v19, s5
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(15)
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(20)
; GFX9-NEXT: v_perm_b32 v11, s6, v12, v11
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_sdwa v17, v17, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_sdwa v18, v18, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s5
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v12, 3, v54
-; GFX9-NEXT: v_add_u32_e32 v13, 3, v52
-; GFX9-NEXT: v_perm_b32 v12, v12, v53, s5
-; GFX9-NEXT: v_perm_b32 v13, v13, v51, s5
+; GFX9-NEXT: v_add_u32_e32 v12, 3, v34
+; GFX9-NEXT: v_perm_b32 v12, v12, v41, s5
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v12
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
+; GFX9-NEXT: v_perm_b32 v13, v13, v14, s5
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v13, v13, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v12, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v13, 3, v50
-; GFX9-NEXT: v_perm_b32 v13, v13, v49, s5
+; GFX9-NEXT: v_add_u32_e32 v13, 3, v40
+; GFX9-NEXT: v_perm_b32 v13, v13, v54, s5
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
+; GFX9-NEXT: v_perm_b32 v14, v14, v15, s5
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v14, 3, v38
-; GFX9-NEXT: v_perm_b32 v14, v14, v37, s5
+; GFX9-NEXT: v_add_u32_e32 v14, 3, v52
+; GFX9-NEXT: v_perm_b32 v14, v14, v50, s5
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v14
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s5
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v15, 3, v34
-; GFX9-NEXT: v_perm_b32 v15, v15, v33, s5
+; GFX9-NEXT: v_add_u32_e32 v15, 3, v48
+; GFX9-NEXT: v_perm_b32 v15, v15, v38, s5
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v15
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v16, 3, v16
+; GFX9-NEXT: v_perm_b32 v16, v16, v17, s5
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v16, 3, v62
-; GFX9-NEXT: v_perm_b32 v16, v16, v61, s5
+; GFX9-NEXT: v_add_u32_e32 v16, 3, v36
+; GFX9-NEXT: v_perm_b32 v16, v16, v35, s5
; GFX9-NEXT: v_add_u32_e32 v16, 0x300, v16
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s5
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v17, v17, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v16, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v17, 3, v41
-; GFX9-NEXT: v_perm_b32 v17, v17, v40, s5
+; GFX9-NEXT: v_add_u32_e32 v17, 3, v33
+; GFX9-NEXT: v_perm_b32 v17, v17, v47, s5
; GFX9-NEXT: v_add_u32_e32 v17, 0x300, v17
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_add_u32_e32 v18, 3, v18
+; GFX9-NEXT: v_perm_b32 v18, v18, v19, s5
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v18, v18, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v18, 3, v42
-; GFX9-NEXT: v_perm_b32 v18, v18, v47, s5
+; GFX9-NEXT: v_add_u32_e32 v18, 3, v62
+; GFX9-NEXT: v_perm_b32 v18, v18, v61, s5
; GFX9-NEXT: v_add_u32_e32 v18, 0x300, v18
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
+; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v19, v19, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v18, v18, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v19, 3, v46
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_e32 v19, 3, v59
+; GFX9-NEXT: v_perm_b32 v19, v19, v58, s5
; GFX9-NEXT: v_add_u32_e32 v19, 0x300, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v20, 3, v20
; GFX9-NEXT: v_perm_b32 v20, v20, v21, s5
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v20, v20, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v19, v19, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v20, 3, v45
+; GFX9-NEXT: v_add_u32_e32 v20, 3, v56
; GFX9-NEXT: v_perm_b32 v20, v20, v44, s5
; GFX9-NEXT: v_add_u32_e32 v20, 0x300, v20
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v21, 3, v21
; GFX9-NEXT: v_perm_b32 v21, v21, v22, s5
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v21, v21, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v20, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_add_u32_e32 v21, 3, v43
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v21, v21, v22, s5
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v21, 0x300, v21
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: v_perm_b32 v22, v22, v23, s5
; GFX9-NEXT: v_add_u32_sdwa v22, v22, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v21, v21, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v22, v22, v23, s5
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v22, 0x300, v22
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: v_perm_b32 v23, v23, v24, s5
; GFX9-NEXT: v_add_u32_sdwa v23, v23, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v22, v22, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v23, v24, s5
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v23, 0x300, v23
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v24, 3, v24
; GFX9-NEXT: v_perm_b32 v24, v24, v25, s5
; GFX9-NEXT: v_add_u32_sdwa v24, v24, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v24, 3, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v24, v25, s5
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v24, 0x300, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v25, 3, v25
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s5
; GFX9-NEXT: v_add_u32_sdwa v25, v25, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v24, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v25, 3, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s5
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v25, 0x300, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v26, 3, v26
; GFX9-NEXT: v_perm_b32 v26, v26, v27, s5
; GFX9-NEXT: v_add_u32_sdwa v26, v26, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v26, 3, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v26, v27, s5
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v26, 0x300, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v27, 3, v27
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s5
; GFX9-NEXT: v_add_u32_sdwa v27, v27, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v26, v26, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s5
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v27, 0x300, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v28, 3, v28
; GFX9-NEXT: v_perm_b32 v28, v28, v29, s5
; GFX9-NEXT: v_add_u32_sdwa v28, v28, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v28, 3, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v28, v29, s5
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v28, 0x300, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v29, 3, v29
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s5
; GFX9-NEXT: v_add_u32_sdwa v29, v29, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v28, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v29, 3, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s5
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v29, 0x300, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v30, 3, v30
; GFX9-NEXT: v_perm_b32 v30, v30, v31, s5
; GFX9-NEXT: v_add_u32_sdwa v30, v30, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v30, 3, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v30, v31, s5
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v30, 0x300, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v31, 3, v31
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s5
; GFX9-NEXT: v_add_u32_sdwa v31, v31, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v30, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v31, 3, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s5
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v31, 0x300, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v32, 3, v32
@@ -20425,10 +20313,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v32i32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
@@ -20550,149 +20435,109 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB15_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v163, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v147, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v6, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v132, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v129, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v114, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v101, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v99, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v83, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v14, 16, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v99, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, v23, v24
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v103, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v101, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, v23, v24
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v83, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, v29, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v65, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v40, v41
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v181, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v67, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v66, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v52, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v167, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v165, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v49, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v183, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v34, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v150, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v145, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v21, 16, v20
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v119, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v102, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v96, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v85, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v25, v27, 16, v26
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v70, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v65, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v31, 16, v30
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v39, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v40, 16, v183
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB15_3
; GFX11-TRUE16-NEXT: .LBB15_2: ; %cmp.true
@@ -20987,9 +20832,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v36, v35
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v33, v32
; GFX11-TRUE16-NEXT: .LBB15_3: ; %end
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB15_4:
@@ -20999,10 +20842,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v32i32_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
-; GFX11-FAKE16-NEXT: ; meta instruction
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:308
@@ -21124,149 +20964,109 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB15_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v180, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v164, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v163, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v147, v135, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v6, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v146, v134, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v132, v130, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v129, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v117, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v114, v112, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v101, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v100, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v84, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v83, v71, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v14, 16, v13
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v147, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v100, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v23, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v103, v99, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v101, v97, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v25, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v67, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v49, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v29, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v65, v53, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v31
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v183, 16, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v29, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-FAKE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v31, v183
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v40, v41
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v182, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v181, v177, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v67, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v66, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v167, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v165, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v49, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v183, v37, v33, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v40, v34, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v161, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v150, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v145, v133, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v144, v131, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v21, 16, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v128, v116, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v119, v115, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v103, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v102, v98, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v96, v86, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v85, v82, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v27, 16, v26
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v81, v69, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v70, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v65, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v31, 16, v30
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v48, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v39, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v40, 16, v183
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB15_3
; GFX11-FAKE16-NEXT: .LBB15_2: ; %cmp.true
@@ -21561,9 +21361,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v36, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v33, v32
; GFX11-FAKE16-NEXT: .LBB15_3: ; %end
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB15_4:
@@ -45685,27 +45483,27 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[13:14]
-; GFX9-NEXT: v_add_f32_e64 v22, s43, 1.0
-; GFX9-NEXT: v_add_f32_e64 v21, s42, 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: v_add_f32_e64 v20, s43, 1.0
+; GFX9-NEXT: v_add_f32_e64 v19, s42, 1.0
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[21:22]
-; GFX9-NEXT: v_add_f32_e64 v24, s45, 1.0
-; GFX9-NEXT: v_add_f32_e64 v23, s44, 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[19:20]
+; GFX9-NEXT: v_add_f32_e64 v22, s45, 1.0
+; GFX9-NEXT: v_add_f32_e64 v21, s44, 1.0
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[23:24]
+; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[21:22]
; GFX9-NEXT: v_add_f32_e64 v26, s29, 1.0
; GFX9-NEXT: v_add_f32_e64 v25, s28, 1.0
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[25:26]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v2
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v2
@@ -45773,94 +45571,94 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v14
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v13
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v13
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v20
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v20
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v20
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v19
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v19
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v22
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v22
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v22
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v21
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v21
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v24
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v24
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v24
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v26
; GFX9-NEXT: v_add_f32_e64 v28, s27, 1.0
+; GFX9-NEXT: v_add_f32_e64 v27, s26, 1.0
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v26
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; GFX9-NEXT: v_add_f32_e64 v30, s25, 1.0
+; GFX9-NEXT: v_add_f32_e64 v29, s24, 1.0
+; GFX9-NEXT: v_lshrrev_b64 v[39:40], 24, v[27:28]
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v28
; GFX9-NEXT: v_add_f32_e64 v32, s23, 1.0
; GFX9-NEXT: v_add_f32_e64 v31, s22, 1.0
-; GFX9-NEXT: v_add_f32_e64 v30, s25, 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[40:41], 24, v[29:30]
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v28
-; GFX9-NEXT: v_add_f32_e64 v34, s21, 1.0
-; GFX9-NEXT: v_add_f32_e64 v33, s20, 1.0
-; GFX9-NEXT: v_lshrrev_b64 v[39:40], 24, v[31:32]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; GFX9-NEXT: v_add_f32_e64 v36, s21, 1.0
+; GFX9-NEXT: v_add_f32_e64 v35, s20, 1.0
+; GFX9-NEXT: v_lshrrev_b64 v[41:42], 24, v[31:32]
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v30
; GFX9-NEXT: v_add_f32_e64 v49, s17, 1.0
-; GFX9-NEXT: v_add_f32_e64 v36, s19, 1.0
-; GFX9-NEXT: v_add_f32_e64 v35, s18, 1.0
-; GFX9-NEXT: v_add_f32_e64 v27, s26, 1.0
-; GFX9-NEXT: v_lshrrev_b64 v[40:41], 24, v[33:34]
+; GFX9-NEXT: v_add_f32_e64 v38, s19, 1.0
+; GFX9-NEXT: v_add_f32_e64 v37, s18, 1.0
+; GFX9-NEXT: v_lshrrev_b64 v[42:43], 24, v[35:36]
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v30
; GFX9-NEXT: v_add_f32_e64 v48, s16, 1.0
-; GFX9-NEXT: v_add_f32_e64 v29, s24, 1.0
-; GFX9-NEXT: v_lshrrev_b64 v[53:54], 24, v[27:28]
-; GFX9-NEXT: v_lshrrev_b64 v[41:42], 24, v[35:36]
+; GFX9-NEXT: v_lshrrev_b64 v[43:44], 24, v[37:38]
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v32
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 24, v34
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v36
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 24, v49
-; GFX9-NEXT: v_lshrrev_b64 v[54:55], 24, v[29:30]
-; GFX9-NEXT: v_lshrrev_b64 v[42:43], 24, v[48:49]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v16, 24, v36
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v38
+; GFX9-NEXT: v_lshrrev_b32_e32 v23, 24, v49
+; GFX9-NEXT: v_lshrrev_b64 v[44:45], 24, v[48:49]
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v32
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v34
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v36
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v49
-; GFX9-NEXT: v_lshrrev_b32_e32 v44, 16, v23
-; GFX9-NEXT: v_lshrrev_b32_e32 v43, 8, v23
+; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v36
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v38
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v23, 16, v49
+; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v21
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 8, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 8, v26
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v25
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 8, v25
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 8, v28
-; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v27
-; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v27
-; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v30
+; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v27
+; GFX9-NEXT: v_lshrrev_b32_e32 v51, 8, v27
+; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v30
; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v29
-; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v29
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v29
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v32
-; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v31
-; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v31
+; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v31
+; GFX9-NEXT: v_lshrrev_b32_e32 v52, 8, v31
; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 8, v34
-; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v33
-; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v33
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v36
-; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v35
-; GFX9-NEXT: v_lshrrev_b32_e32 v18, 8, v35
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v49
-; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v48
-; GFX9-NEXT: v_lshrrev_b32_e32 v20, 8, v48
+; GFX9-NEXT: v_lshrrev_b32_e32 v16, 8, v36
+; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v35
+; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v35
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v54, 8, v38
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v37
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v37
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v23, 8, v49
+; GFX9-NEXT: v_lshrrev_b32_e32 v24, 16, v48
+; GFX9-NEXT: v_lshrrev_b32_e32 v33, 8, v48
; GFX9-NEXT: s_branch .LBB37_5
; GFX9-NEXT: .LBB37_3:
; GFX9-NEXT: ; implicit-def: $sgpr46
@@ -46011,46 +45809,45 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: s_branch .LBB37_2
; GFX9-NEXT: .LBB37_4:
-; GFX9-NEXT: v_mov_b32_e32 v53, s46
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v53, s56
+; GFX9-NEXT: v_mov_b32_e32 v34, s39
+; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v34, s38
; GFX9-NEXT: v_mov_b32_e32 v1, s4
-; GFX9-NEXT: v_mov_b32_e32 v39, s96
+; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v34, s96
; GFX9-NEXT: v_readlane_b32 s4, v62, 0
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v39, s87
+; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v34, s87
; GFX9-NEXT: v_mov_b32_e32 v46, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 1
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v39, s83
+; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v34, s83
; GFX9-NEXT: v_mov_b32_e32 v47, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 2
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v39, s82
+; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v34, s82
; GFX9-NEXT: v_mov_b32_e32 v45, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 3
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v39, s4
+; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v34, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 4
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v39, s4
+; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v34, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 5
-; GFX9-NEXT: v_mov_b32_e32 v43, s4
+; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v34, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 6
-; GFX9-NEXT: v_mov_b32_e32 v44, s4
+; GFX9-NEXT: v_mov_b32_e32 v55, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 7
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 8
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 9
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 10
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 11
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
@@ -46059,19 +45856,19 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 13
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 14
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 15
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 16
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 17
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 18
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
@@ -46093,10 +45890,6 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 24
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v53, s58
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 25
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
@@ -46156,47 +45949,81 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 44
-; GFX9-NEXT: v_mov_b32_e32 v15, s70
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 45
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s69
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 46
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s65
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 47
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s64
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v53, s60
; GFX9-NEXT: v_readlane_b32 s4, v62, 48
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s52
-; GFX9-NEXT: v_mov_b32_e32 v37, s39
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 49
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s51
-; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v37, s38
; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v39, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s46
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s56
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s58
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s60
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s62
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s72
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s74
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s76
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s78
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v15, s70
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v15, s69
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v15, s65
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v15, s64
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v15, s52
+; GFX9-NEXT: v_mov_b32_e32 v39, s88
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v15, s51
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v48, s16
; GFX9-NEXT: v_mov_b32_e32 v49, s17
-; GFX9-NEXT: v_mov_b32_e32 v35, s18
-; GFX9-NEXT: v_mov_b32_e32 v36, s19
-; GFX9-NEXT: v_mov_b32_e32 v33, s20
-; GFX9-NEXT: v_mov_b32_e32 v34, s21
+; GFX9-NEXT: v_mov_b32_e32 v37, s18
+; GFX9-NEXT: v_mov_b32_e32 v38, s19
+; GFX9-NEXT: v_mov_b32_e32 v35, s20
+; GFX9-NEXT: v_mov_b32_e32 v36, s21
; GFX9-NEXT: v_mov_b32_e32 v31, s22
; GFX9-NEXT: v_mov_b32_e32 v32, s23
; GFX9-NEXT: v_mov_b32_e32 v29, s24
@@ -46205,10 +46032,10 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v28, s27
; GFX9-NEXT: v_mov_b32_e32 v25, s28
; GFX9-NEXT: v_mov_b32_e32 v26, s29
-; GFX9-NEXT: v_mov_b32_e32 v23, s44
-; GFX9-NEXT: v_mov_b32_e32 v24, s45
-; GFX9-NEXT: v_mov_b32_e32 v21, s42
-; GFX9-NEXT: v_mov_b32_e32 v22, s43
+; GFX9-NEXT: v_mov_b32_e32 v21, s44
+; GFX9-NEXT: v_mov_b32_e32 v22, s45
+; GFX9-NEXT: v_mov_b32_e32 v19, s42
+; GFX9-NEXT: v_mov_b32_e32 v20, s43
; GFX9-NEXT: v_mov_b32_e32 v13, s40
; GFX9-NEXT: v_mov_b32_e32 v14, s41
; GFX9-NEXT: v_mov_b32_e32 v11, s14
@@ -46222,88 +46049,61 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_mov_b32_e32 v4, s7
; GFX9-NEXT: v_mov_b32_e32 v2, s5
-; GFX9-NEXT: v_mov_b32_e32 v20, s81
-; GFX9-NEXT: v_mov_b32_e32 v55, s71
-; GFX9-NEXT: v_mov_b32_e32 v19, s80
-; GFX9-NEXT: v_mov_b32_e32 v18, s68
-; GFX9-NEXT: v_mov_b32_e32 v52, s66
-; GFX9-NEXT: v_mov_b32_e32 v17, s67
+; GFX9-NEXT: v_mov_b32_e32 v33, s81
+; GFX9-NEXT: v_mov_b32_e32 v24, s71
+; GFX9-NEXT: v_mov_b32_e32 v23, s80
+; GFX9-NEXT: v_mov_b32_e32 v17, s68
+; GFX9-NEXT: v_mov_b32_e32 v18, s66
+; GFX9-NEXT: v_mov_b32_e32 v54, s67
; GFX9-NEXT: v_mov_b32_e32 v61, s55
-; GFX9-NEXT: v_mov_b32_e32 v51, s53
+; GFX9-NEXT: v_mov_b32_e32 v53, s53
; GFX9-NEXT: v_mov_b32_e32 v16, s54
; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v60, s50
-; GFX9-NEXT: v_mov_b32_e32 v50, s48
+; GFX9-NEXT: v_mov_b32_e32 v52, s50
+; GFX9-NEXT: v_mov_b32_e32 v60, s48
; GFX9-NEXT: v_mov_b32_e32 v15, s49
-; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v37, s99
+; GFX9-NEXT: v_mov_b32_e32 v50, s99
; GFX9-NEXT: v_mov_b32_e32 v59, s97
-; GFX9-NEXT: v_mov_b32_e32 v38, s98
-; GFX9-NEXT: v_mov_b32_e32 v57, s86
-; GFX9-NEXT: v_mov_b32_e32 v58, s84
+; GFX9-NEXT: v_mov_b32_e32 v58, s98
+; GFX9-NEXT: v_mov_b32_e32 v51, s86
+; GFX9-NEXT: v_mov_b32_e32 v57, s84
; GFX9-NEXT: v_mov_b32_e32 v56, s85
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v39, s94
-; GFX9-NEXT: v_mov_b32_e32 v40, s30
-; GFX9-NEXT: v_mov_b32_e32 v41, s34
-; GFX9-NEXT: v_mov_b32_e32 v42, s36
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v53, s62
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v53, s72
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v53, s74
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v53, s76
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v53, s78
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v53, s88
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v53, s90
-; GFX9-NEXT: v_mov_b32_e32 v54, s92
+; GFX9-NEXT: v_mov_b32_e32 v39, s90
+; GFX9-NEXT: v_mov_b32_e32 v40, s92
+; GFX9-NEXT: v_mov_b32_e32 v41, s94
+; GFX9-NEXT: v_mov_b32_e32 v42, s30
+; GFX9-NEXT: v_mov_b32_e32 v43, s34
+; GFX9-NEXT: v_mov_b32_e32 v44, s36
; GFX9-NEXT: .LBB37_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v32, v32, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v19, v49, v19, s4
-; GFX9-NEXT: v_perm_b32 v16, v34, v16, s4
-; GFX9-NEXT: v_perm_b32 v34, v50, v39, s4
+; GFX9-NEXT: v_perm_b32 v21, v21, v34, s4
+; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v33, v48, v33, s4
+; GFX9-NEXT: v_perm_b32 v23, v49, v23, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v29, v29, v50, s4
; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v30, v30, v38, s4
-; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v18, v35, v18, s4
-; GFX9-NEXT: v_perm_b32 v35, v51, v40, s4
-; GFX9-NEXT: v_perm_b32 v55, v55, v42, s4
-; GFX9-NEXT: v_perm_b32 v20, v48, v20, s4
-; GFX9-NEXT: v_perm_b32 v48, v52, v41, s4
-; GFX9-NEXT: v_perm_b32 v17, v36, v17, s4
-; GFX9-NEXT: v_perm_b32 v33, v33, v61, s4
-; GFX9-NEXT: v_perm_b32 v31, v31, v60, s4
-; GFX9-NEXT: v_perm_b32 v36, v59, v54, s4
-; GFX9-NEXT: v_perm_b32 v29, v29, v37, s4
-; GFX9-NEXT: v_perm_b32 v37, v58, v53, s4
-; GFX9-NEXT: v_perm_b32 v27, v27, v57, s4
+; GFX9-NEXT: v_perm_b32 v27, v27, v51, s4
+; GFX9-NEXT: v_perm_b32 v24, v24, v44, s4
+; GFX9-NEXT: v_lshl_or_b32 v24, v24, 16, v33
+; GFX9-NEXT: v_perm_b32 v18, v18, v43, s4
+; GFX9-NEXT: v_perm_b32 v17, v37, v17, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: v_perm_b32 v37, v38, v54, s4
+; GFX9-NEXT: v_perm_b32 v38, v53, v42, s4
+; GFX9-NEXT: v_perm_b32 v35, v35, v61, s4
+; GFX9-NEXT: v_perm_b32 v16, v36, v16, s4
+; GFX9-NEXT: v_perm_b32 v36, v60, v41, s4
+; GFX9-NEXT: v_perm_b32 v31, v31, v52, s4
+; GFX9-NEXT: v_perm_b32 v15, v32, v15, s4
+; GFX9-NEXT: v_perm_b32 v32, v59, v40, s4
+; GFX9-NEXT: v_perm_b32 v30, v30, v58, s4
+; GFX9-NEXT: v_perm_b32 v39, v57, v39, s4
; GFX9-NEXT: v_perm_b32 v28, v28, v56, s4
; GFX9-NEXT: v_perm_b32 v25, v25, v46, s4
; GFX9-NEXT: v_perm_b32 v26, v26, v45, s4
-; GFX9-NEXT: v_perm_b32 v23, v23, v43, s4
; GFX9-NEXT: v_readlane_b32 s30, v63, 34
; GFX9-NEXT: v_readlane_b32 s31, v63, 35
; GFX9-NEXT: v_readlane_b32 s99, v63, 33
@@ -46341,130 +46141,110 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_perm_b32 v24, v24, v15, s4
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v39, v44, v49, s4
-; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v38, v47, v38, s4
+; GFX9-NEXT: v_perm_b32 v22, v22, v34, s4
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: v_perm_b32 v48, v47, v48, s4
+; GFX9-NEXT: s_waitcnt vmcnt(4)
+; GFX9-NEXT: v_perm_b32 v49, v55, v49, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v49, v15, v49, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v34, v34, v50, s4
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v21, v21, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v19, v19, v50, s4
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v22, v22, v15, s4
-; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v20, v20, v50, s4
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v15, v15, v50, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v50, 16, v55
-; GFX9-NEXT: v_or_b32_e32 v20, v20, v50
-; GFX9-NEXT: buffer_store_dword v20, v0, s[0:3], 0 offen
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v50, v51, v50, s4
+; GFX9-NEXT: buffer_store_dword v24, v0, s[0:3], 0 offen
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v20, v20, v50, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX9-NEXT: v_or_b32_e32 v19, v19, v20
-; GFX9-NEXT: buffer_store_dword v19, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v48
-; GFX9-NEXT: v_or_b32_e32 v18, v18, v19
-; GFX9-NEXT: buffer_store_dword v18, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v24, v24, v33, s4
+; GFX9-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; GFX9-NEXT: buffer_store_dword v23, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v18, v18, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v17, v17, v18
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v37
; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v35
-; GFX9-NEXT: v_or_b32_e32 v17, v33, v17
+; GFX9-NEXT: v_lshl_or_b32 v17, v38, 16, v35
; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v17
+; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v34
-; GFX9-NEXT: v_or_b32_e32 v16, v31, v16
+; GFX9-NEXT: v_lshl_or_b32 v16, v36, 16, v31
; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v32, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v36
-; GFX9-NEXT: v_or_b32_e32 v16, v29, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: v_lshl_or_b32 v15, v32, 16, v29
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v30, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v37
-; GFX9-NEXT: v_or_b32_e32 v16, v27, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v30
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: v_lshl_or_b32 v15, v39, 16, v27
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:40
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v28, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v38
-; GFX9-NEXT: v_or_b32_e32 v16, v25, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v28
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:44
+; GFX9-NEXT: v_lshl_or_b32 v15, v48, 16, v25
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:48
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v26, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v39
-; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v26
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:52
+; GFX9-NEXT: v_lshl_or_b32 v15, v49, 16, v21
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:56
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v24, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v49
-; GFX9-NEXT: v_or_b32_e32 v16, v21, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v22
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:60
+; GFX9-NEXT: v_lshl_or_b32 v15, v34, 16, v19
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:64
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v20
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:68
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_perm_b32 v13, v13, v15, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v50, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46473,8 +46253,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v14, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46484,8 +46263,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46494,8 +46272,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46505,8 +46282,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46515,8 +46291,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v10, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46526,8 +46301,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46536,8 +46310,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46547,8 +46320,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46557,8 +46329,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v6, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46568,8 +46339,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46578,8 +46348,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46589,8 +46358,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -46599,8 +46367,7 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -46880,134 +46647,134 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
; GFX11-NEXT: s_cbranch_vccnz .LBB37_4
; GFX11-NEXT: .LBB37_2: ; %cmp.true
-; GFX11-NEXT: v_add_f32_e64 v12, s15, 1.0
-; GFX11-NEXT: v_add_f32_e64 v11, s14, 1.0
; GFX11-NEXT: v_add_f32_e64 v14, s41, 1.0
; GFX11-NEXT: v_add_f32_e64 v13, s40, 1.0
; GFX11-NEXT: v_add_f32_e64 v16, s29, 1.0
; GFX11-NEXT: v_add_f32_e64 v15, s28, 1.0
-; GFX11-NEXT: v_add_f32_e64 v26, s19, 1.0
-; GFX11-NEXT: v_add_f32_e64 v25, s18, 1.0
+; GFX11-NEXT: v_add_f32_e64 v2, s5, 1.0
+; GFX11-NEXT: v_add_f32_e64 v1, s4, 1.0
; GFX11-NEXT: v_add_f32_e64 v18, s27, 1.0
; GFX11-NEXT: v_add_f32_e64 v17, s26, 1.0
; GFX11-NEXT: v_add_f32_e64 v4, s7, 1.0
; GFX11-NEXT: v_add_f32_e64 v3, s6, 1.0
-; GFX11-NEXT: v_add_f32_e64 v28, s17, 1.0
-; GFX11-NEXT: v_add_f32_e64 v27, s16, 1.0
; GFX11-NEXT: v_add_f32_e64 v20, s25, 1.0
; GFX11-NEXT: v_add_f32_e64 v19, s24, 1.0
; GFX11-NEXT: v_add_f32_e64 v6, s9, 1.0
; GFX11-NEXT: v_add_f32_e64 v5, s8, 1.0
-; GFX11-NEXT: v_add_f32_e64 v32, s3, 1.0
-; GFX11-NEXT: v_add_f32_e64 v31, s2, 1.0
+; GFX11-NEXT: v_add_f32_e64 v28, s17, 1.0
+; GFX11-NEXT: v_add_f32_e64 v27, s16, 1.0
; GFX11-NEXT: v_add_f32_e64 v22, s23, 1.0
; GFX11-NEXT: v_add_f32_e64 v21, s22, 1.0
; GFX11-NEXT: v_add_f32_e64 v8, s11, 1.0
; GFX11-NEXT: v_add_f32_e64 v7, s10, 1.0
-; GFX11-NEXT: v_lshrrev_b64 v[48:49], 24, v[11:12]
-; GFX11-NEXT: v_add_f32_e64 v34, s1, 1.0
-; GFX11-NEXT: v_add_f32_e64 v33, s0, 1.0
+; GFX11-NEXT: v_add_f32_e64 v30, s3, 1.0
+; GFX11-NEXT: v_add_f32_e64 v29, s2, 1.0
; GFX11-NEXT: v_add_f32_e64 v24, s21, 1.0
; GFX11-NEXT: v_add_f32_e64 v23, s20, 1.0
; GFX11-NEXT: v_add_f32_e64 v10, s13, 1.0
-; GFX11-NEXT: v_add_f32_e64 v2, s5, 1.0
-; GFX11-NEXT: v_add_f32_e64 v1, s4, 1.0
; GFX11-NEXT: v_add_f32_e64 v9, s12, 1.0
-; GFX11-NEXT: v_lshrrev_b64 v[49:50], 24, v[13:14]
-; GFX11-NEXT: v_lshrrev_b64 v[50:51], 24, v[15:16]
-; GFX11-NEXT: v_lshrrev_b64 v[35:36], 24, v[3:4]
-; GFX11-NEXT: v_lshrrev_b64 v[51:52], 24, v[17:18]
-; GFX11-NEXT: v_lshrrev_b64 v[64:65], 24, v[25:26]
-; GFX11-NEXT: v_lshrrev_b64 v[36:37], 24, v[5:6]
-; GFX11-NEXT: v_lshrrev_b64 v[52:53], 24, v[19:20]
-; GFX11-NEXT: v_lshrrev_b64 v[65:66], 24, v[27:28]
-; GFX11-NEXT: v_lshrrev_b64 v[37:38], 24, v[7:8]
-; GFX11-NEXT: v_lshrrev_b64 v[53:54], 24, v[21:22]
+; GFX11-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
+; GFX11-NEXT: v_add_f32_e64 v32, s1, 1.0
+; GFX11-NEXT: v_add_f32_e64 v31, s0, 1.0
+; GFX11-NEXT: v_add_f32_e64 v26, s19, 1.0
+; GFX11-NEXT: v_add_f32_e64 v25, s18, 1.0
+; GFX11-NEXT: v_add_f32_e64 v12, s15, 1.0
+; GFX11-NEXT: v_add_f32_e64 v11, s14, 1.0
+; GFX11-NEXT: v_lshrrev_b64 v[33:34], 24, v[1:2]
+; GFX11-NEXT: v_lshrrev_b64 v[49:50], 24, v[15:16]
+; GFX11-NEXT: v_lshrrev_b64 v[34:35], 24, v[3:4]
+; GFX11-NEXT: v_lshrrev_b64 v[50:51], 24, v[17:18]
+; GFX11-NEXT: v_lshrrev_b64 v[35:36], 24, v[5:6]
+; GFX11-NEXT: v_lshrrev_b64 v[51:52], 24, v[19:20]
+; GFX11-NEXT: v_lshrrev_b64 v[36:37], 24, v[7:8]
+; GFX11-NEXT: v_lshrrev_b64 v[52:53], 24, v[21:22]
+; GFX11-NEXT: v_lshrrev_b64 v[64:65], 24, v[27:28]
+; GFX11-NEXT: v_lshrrev_b64 v[37:38], 24, v[9:10]
+; GFX11-NEXT: v_lshrrev_b64 v[53:54], 24, v[23:24]
+; GFX11-NEXT: v_lshrrev_b64 v[65:66], 24, v[29:30]
+; GFX11-NEXT: v_lshrrev_b64 v[38:39], 24, v[11:12]
+; GFX11-NEXT: v_lshrrev_b64 v[54:55], 24, v[25:26]
; GFX11-NEXT: v_lshrrev_b64 v[66:67], 24, v[31:32]
-; GFX11-NEXT: v_lshrrev_b64 v[29:30], 24, v[1:2]
-; GFX11-NEXT: v_lshrrev_b64 v[38:39], 24, v[9:10]
-; GFX11-NEXT: v_lshrrev_b64 v[54:55], 24, v[23:24]
-; GFX11-NEXT: v_lshrrev_b64 v[67:68], 24, v[33:34]
-; GFX11-NEXT: v_lshrrev_b32_e32 v70, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v68, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v71, 8, v1
; GFX11-NEXT: v_lshrrev_b32_e32 v83, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v81, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v82, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v69, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v81, 8, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v86, 24, v6
; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v80, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v84, 8, v6
; GFX11-NEXT: v_lshrrev_b32_e32 v98, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v96, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v100, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v99, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v97, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v101, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v8
; GFX11-NEXT: v_lshrrev_b32_e32 v87, 8, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v101, 16, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v97, 8, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v112, 24, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v100, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v99, 8, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v114, 24, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v103, 16, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v102, 8, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v116, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v114, 8, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v118, 24, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v117, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v113, 8, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v119, 16, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v115, 8, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v130, 24, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v113, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v112, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v119, 24, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v116, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v115, 8, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v118, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v117, 8, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v134, 24, v14
; GFX11-NEXT: v_lshrrev_b32_e32 v129, 16, v14
; GFX11-NEXT: v_lshrrev_b32_e32 v128, 8, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v134, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v133, 16, v13
; GFX11-NEXT: v_lshrrev_b32_e32 v132, 8, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v144, 24, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v135, 16, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v131, 8, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v135, 24, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v131, 16, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v130, 8, v16
; GFX11-NEXT: v_lshrrev_b32_e32 v145, 16, v15
-; GFX11-NEXT: v_lshrrev_b32_e32 v133, 8, v15
-; GFX11-NEXT: v_lshrrev_b32_e32 v148, 24, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v147, 16, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v146, 8, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v151, 16, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v149, 8, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v162, 24, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v161, 16, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v150, 8, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v163, 16, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v160, 8, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v166, 24, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v165, 16, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v164, 8, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v177, 16, v21
-; GFX11-NEXT: v_lshrrev_b32_e32 v167, 8, v21
-; GFX11-NEXT: v_lshrrev_b32_e32 v180, 24, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v179, 16, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v176, 8, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v181, 16, v23
-; GFX11-NEXT: v_lshrrev_b32_e32 v178, 8, v23
-; GFX11-NEXT: v_lshrrev_b32_e32 v41, 24, v26
-; GFX11-NEXT: v_lshrrev_b32_e32 v40, 16, v26
-; GFX11-NEXT: v_lshrrev_b32_e32 v182, 8, v26
-; GFX11-NEXT: v_lshrrev_b32_e32 v43, 16, v25
-; GFX11-NEXT: v_lshrrev_b32_e32 v183, 8, v25
-; GFX11-NEXT: v_lshrrev_b32_e32 v45, 24, v28
-; GFX11-NEXT: v_lshrrev_b32_e32 v44, 16, v28
-; GFX11-NEXT: v_lshrrev_b32_e32 v42, 8, v28
-; GFX11-NEXT: v_lshrrev_b32_e32 v47, 16, v27
-; GFX11-NEXT: v_lshrrev_b32_e32 v46, 8, v27
-; GFX11-NEXT: v_lshrrev_b32_e32 v59, 24, v32
-; GFX11-NEXT: v_lshrrev_b32_e32 v58, 16, v32
-; GFX11-NEXT: v_lshrrev_b32_e32 v56, 8, v32
-; GFX11-NEXT: v_lshrrev_b32_e32 v60, 16, v31
-; GFX11-NEXT: v_lshrrev_b32_e32 v57, 8, v31
-; GFX11-NEXT: v_lshrrev_b32_e32 v62, 24, v34
-; GFX11-NEXT: v_lshrrev_b32_e32 v61, 16, v34
-; GFX11-NEXT: v_lshrrev_b32_e32 v63, 8, v34
-; GFX11-NEXT: v_lshrrev_b32_e32 v73, 16, v33
-; GFX11-NEXT: v_lshrrev_b32_e32 v72, 8, v33
+; GFX11-NEXT: v_lshrrev_b32_e32 v144, 8, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v147, 24, v18
+; GFX11-NEXT: v_lshrrev_b32_e32 v146, 16, v18
+; GFX11-NEXT: v_lshrrev_b32_e32 v148, 8, v18
+; GFX11-NEXT: v_lshrrev_b32_e32 v149, 16, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v150, 8, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v160, 24, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v151, 16, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v161, 8, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v162, 16, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v163, 8, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v165, 24, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v164, 16, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v166, 8, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v167, 16, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v176, 8, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v178, 24, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v177, 16, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v179, 8, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v180, 16, v23
+; GFX11-NEXT: v_lshrrev_b32_e32 v181, 8, v23
+; GFX11-NEXT: v_lshrrev_b32_e32 v183, 24, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v182, 16, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v40, 8, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v41, 16, v25
+; GFX11-NEXT: v_lshrrev_b32_e32 v42, 8, v25
+; GFX11-NEXT: v_lshrrev_b32_e32 v44, 24, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v43, 16, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v45, 8, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v46, 16, v27
+; GFX11-NEXT: v_lshrrev_b32_e32 v47, 8, v27
+; GFX11-NEXT: v_lshrrev_b32_e32 v57, 24, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v56, 16, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v58, 8, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v59, 16, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v60, 8, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v62, 24, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v61, 16, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v63, 8, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v73, 16, v31
+; GFX11-NEXT: v_lshrrev_b32_e32 v72, 8, v31
; GFX11-NEXT: s_branch .LBB37_5
; GFX11-NEXT: .LBB37_3:
; GFX11-NEXT: ; implicit-def: $sgpr43
@@ -47148,12 +46915,12 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: ; kill: killed $sgpr43
; GFX11-NEXT: s_branch .LBB37_2
; GFX11-NEXT: .LBB37_4:
-; GFX11-NEXT: v_dual_mov_b32 v33, s0 :: v_dual_mov_b32 v34, s1
+; GFX11-NEXT: v_dual_mov_b32 v31, s0 :: v_dual_mov_b32 v32, s1
; GFX11-NEXT: v_readlane_b32 s0, v76, 0
-; GFX11-NEXT: v_dual_mov_b32 v31, s2 :: v_dual_mov_b32 v32, s3
+; GFX11-NEXT: v_dual_mov_b32 v29, s2 :: v_dual_mov_b32 v30, s3
; GFX11-NEXT: v_dual_mov_b32 v27, s16 :: v_dual_mov_b32 v28, s17
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v133, s0
+; GFX11-NEXT: v_mov_b32_e32 v144, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 1
; GFX11-NEXT: v_dual_mov_b32 v25, s18 :: v_dual_mov_b32 v26, s19
; GFX11-NEXT: v_dual_mov_b32 v23, s20 :: v_dual_mov_b32 v24, s21
@@ -47162,16 +46929,16 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: v_dual_mov_b32 v21, s22 :: v_dual_mov_b32 v22, s23
; GFX11-NEXT: v_dual_mov_b32 v19, s24 :: v_dual_mov_b32 v20, s25
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v131, s0
+; GFX11-NEXT: v_mov_b32_e32 v130, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 3
; GFX11-NEXT: v_dual_mov_b32 v17, s26 :: v_dual_mov_b32 v18, s27
; GFX11-NEXT: v_dual_mov_b32 v15, s28 :: v_dual_mov_b32 v16, s29
-; GFX11-NEXT: v_mov_b32_e32 v135, s0
+; GFX11-NEXT: v_mov_b32_e32 v131, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 4
; GFX11-NEXT: v_dual_mov_b32 v13, s40 :: v_dual_mov_b32 v14, s41
; GFX11-NEXT: v_dual_mov_b32 v11, s14 :: v_dual_mov_b32 v12, s15
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v144, s0
+; GFX11-NEXT: v_mov_b32_e32 v135, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 5
; GFX11-NEXT: v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, s13
; GFX11-NEXT: v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
@@ -47180,89 +46947,89 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9
; GFX11-NEXT: v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v134, s0
+; GFX11-NEXT: v_mov_b32_e32 v133, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 7
; GFX11-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5
; GFX11-NEXT: v_dual_mov_b32 v72, s104 :: v_dual_mov_b32 v73, s102
; GFX11-NEXT: v_mov_b32_e32 v128, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 8
; GFX11-NEXT: v_dual_mov_b32 v63, s103 :: v_dual_mov_b32 v62, s100
-; GFX11-NEXT: v_dual_mov_b32 v61, s101 :: v_dual_mov_b32 v60, s97
+; GFX11-NEXT: v_dual_mov_b32 v61, s101 :: v_dual_mov_b32 v60, s99
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v129, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 9
-; GFX11-NEXT: v_dual_mov_b32 v57, s99 :: v_dual_mov_b32 v56, s98
-; GFX11-NEXT: v_dual_mov_b32 v58, s96 :: v_dual_mov_b32 v59, s87
-; GFX11-NEXT: v_mov_b32_e32 v130, s0
+; GFX11-NEXT: v_dual_mov_b32 v59, s97 :: v_dual_mov_b32 v58, s98
+; GFX11-NEXT: v_dual_mov_b32 v56, s96 :: v_dual_mov_b32 v57, s87
+; GFX11-NEXT: v_mov_b32_e32 v134, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 10
-; GFX11-NEXT: v_dual_mov_b32 v46, s86 :: v_dual_mov_b32 v47, s84
-; GFX11-NEXT: v_dual_mov_b32 v42, s85 :: v_dual_mov_b32 v45, s82
+; GFX11-NEXT: v_dual_mov_b32 v47, s86 :: v_dual_mov_b32 v46, s84
+; GFX11-NEXT: v_dual_mov_b32 v45, s85 :: v_dual_mov_b32 v44, s82
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v115, s0
+; GFX11-NEXT: v_mov_b32_e32 v117, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 11
-; GFX11-NEXT: v_dual_mov_b32 v44, s83 :: v_dual_mov_b32 v183, s81
-; GFX11-NEXT: v_dual_mov_b32 v43, s71 :: v_dual_mov_b32 v182, s80
-; GFX11-NEXT: v_mov_b32_e32 v119, s0
+; GFX11-NEXT: v_dual_mov_b32 v43, s83 :: v_dual_mov_b32 v42, s81
+; GFX11-NEXT: v_dual_mov_b32 v41, s71 :: v_dual_mov_b32 v40, s80
+; GFX11-NEXT: v_mov_b32_e32 v118, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 12
-; GFX11-NEXT: v_dual_mov_b32 v40, s70 :: v_dual_mov_b32 v41, s69
-; GFX11-NEXT: v_dual_mov_b32 v178, s68 :: v_dual_mov_b32 v181, s66
+; GFX11-NEXT: v_dual_mov_b32 v182, s70 :: v_dual_mov_b32 v183, s69
+; GFX11-NEXT: v_dual_mov_b32 v181, s68 :: v_dual_mov_b32 v180, s66
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v113, s0
+; GFX11-NEXT: v_mov_b32_e32 v115, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 13
-; GFX11-NEXT: v_dual_mov_b32 v176, s67 :: v_dual_mov_b32 v179, s65
-; GFX11-NEXT: v_dual_mov_b32 v180, s64 :: v_dual_mov_b32 v167, s55
-; GFX11-NEXT: v_mov_b32_e32 v117, s0
+; GFX11-NEXT: v_dual_mov_b32 v179, s67 :: v_dual_mov_b32 v178, s64
+; GFX11-NEXT: v_dual_mov_b32 v177, s65 :: v_dual_mov_b32 v176, s55
+; GFX11-NEXT: v_mov_b32_e32 v116, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 14
-; GFX11-NEXT: v_dual_mov_b32 v177, s53 :: v_dual_mov_b32 v164, s54
-; GFX11-NEXT: v_dual_mov_b32 v165, s52 :: v_dual_mov_b32 v166, s51
+; GFX11-NEXT: v_dual_mov_b32 v167, s53 :: v_dual_mov_b32 v166, s54
+; GFX11-NEXT: v_dual_mov_b32 v164, s52 :: v_dual_mov_b32 v165, s51
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v118, s0
+; GFX11-NEXT: v_mov_b32_e32 v119, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 15
-; GFX11-NEXT: v_dual_mov_b32 v160, s50 :: v_dual_mov_b32 v163, s48
-; GFX11-NEXT: v_dual_mov_b32 v150, s49 :: v_dual_mov_b32 v161, s39
-; GFX11-NEXT: v_mov_b32_e32 v114, s0
+; GFX11-NEXT: v_dual_mov_b32 v163, s50 :: v_dual_mov_b32 v162, s48
+; GFX11-NEXT: v_dual_mov_b32 v161, s49 :: v_dual_mov_b32 v160, s38
+; GFX11-NEXT: v_mov_b32_e32 v112, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 16
-; GFX11-NEXT: v_dual_mov_b32 v162, s38 :: v_dual_mov_b32 v149, s37
-; GFX11-NEXT: v_dual_mov_b32 v151, s35 :: v_dual_mov_b32 v146, s36
+; GFX11-NEXT: v_dual_mov_b32 v151, s39 :: v_dual_mov_b32 v150, s37
+; GFX11-NEXT: v_dual_mov_b32 v149, s35 :: v_dual_mov_b32 v148, s36
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v116, s0
+; GFX11-NEXT: v_mov_b32_e32 v113, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 17
-; GFX11-NEXT: v_dual_mov_b32 v147, s34 :: v_dual_mov_b32 v148, vcc_hi
-; GFX11-NEXT: v_dual_mov_b32 v29, s72 :: v_dual_mov_b32 v48, s90
+; GFX11-NEXT: v_dual_mov_b32 v146, s34 :: v_dual_mov_b32 v147, vcc_hi
+; GFX11-NEXT: v_dual_mov_b32 v33, s72 :: v_dual_mov_b32 v38, s90
; GFX11-NEXT: v_mov_b32_e32 v102, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 18
-; GFX11-NEXT: v_dual_mov_b32 v35, s74 :: v_dual_mov_b32 v50, s94
-; GFX11-NEXT: v_dual_mov_b32 v37, s78 :: v_dual_mov_b32 v52, s62
+; GFX11-NEXT: v_dual_mov_b32 v35, s76 :: v_dual_mov_b32 v48, s92
+; GFX11-NEXT: v_dual_mov_b32 v37, s88 :: v_dual_mov_b32 v50, s30
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v103, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 19
-; GFX11-NEXT: v_dual_mov_b32 v49, s92 :: v_dual_mov_b32 v54, s58
-; GFX11-NEXT: v_dual_mov_b32 v51, s30 :: v_dual_mov_b32 v64, s56
-; GFX11-NEXT: v_mov_b32_e32 v112, s0
+; GFX11-NEXT: v_dual_mov_b32 v49, s94 :: v_dual_mov_b32 v52, s60
+; GFX11-NEXT: v_dual_mov_b32 v51, s62 :: v_dual_mov_b32 v54, s56
+; GFX11-NEXT: v_mov_b32_e32 v114, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 20
-; GFX11-NEXT: v_dual_mov_b32 v53, s60 :: v_dual_mov_b32 v66, s44
-; GFX11-NEXT: v_mov_b32_e32 v65, s46
-; GFX11-NEXT: v_mov_b32_e32 v67, s42
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_mov_b32_e32 v97, s0
+; GFX11-NEXT: v_dual_mov_b32 v53, s58 :: v_dual_mov_b32 v64, s46
+; GFX11-NEXT: v_dual_mov_b32 v65, s44 :: v_dual_mov_b32 v66, s42
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mov_b32_e32 v99, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 21
-; GFX11-NEXT: v_mov_b32_e32 v36, s76
-; GFX11-NEXT: v_dual_mov_b32 v38, s88 :: v_dual_mov_b32 v101, s0
+; GFX11-NEXT: v_mov_b32_e32 v34, s74
+; GFX11-NEXT: v_mov_b32_e32 v36, s78
+; GFX11-NEXT: v_mov_b32_e32 v100, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 22
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v87, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 23
-; GFX11-NEXT: v_mov_b32_e32 v99, s0
+; GFX11-NEXT: v_mov_b32_e32 v96, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v100, s0
+; GFX11-NEXT: v_mov_b32_e32 v101, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 25
-; GFX11-NEXT: v_mov_b32_e32 v96, s0
+; GFX11-NEXT: v_mov_b32_e32 v97, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v98, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 27
-; GFX11-NEXT: v_mov_b32_e32 v80, s0
+; GFX11-NEXT: v_mov_b32_e32 v84, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 28
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v85, s0
@@ -47270,166 +47037,133 @@ define inreg <128 x i8> @bitcast_v32f32_to_v128i8_scalar(<32 x float> inreg %a,
; GFX11-NEXT: v_mov_b32_e32 v86, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 30
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v82, s0
+; GFX11-NEXT: v_mov_b32_e32 v81, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 31
-; GFX11-NEXT: v_mov_b32_e32 v84, s0
+; GFX11-NEXT: v_mov_b32_e32 v82, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v55, s0
+; GFX11-NEXT: v_mov_b32_e32 v69, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 1
-; GFX11-NEXT: v_mov_b32_e32 v81, s0
+; GFX11-NEXT: v_mov_b32_e32 v70, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v83, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 3
-; GFX11-NEXT: v_mov_b32_e32 v30, s0
+; GFX11-NEXT: v_mov_b32_e32 v71, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v71, s0
+; GFX11-NEXT: v_mov_b32_e32 v80, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 5
-; GFX11-NEXT: v_mov_b32_e32 v39, s0
+; GFX11-NEXT: v_mov_b32_e32 v55, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v69, s0
+; GFX11-NEXT: v_mov_b32_e32 v39, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 7
-; GFX11-NEXT: v_mov_b32_e32 v70, s0
+; GFX11-NEXT: v_mov_b32_e32 v68, s0
; GFX11-NEXT: .LBB37_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v67, v73, v67, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v66, v60, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v33, v33, v72, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v68, v61, v62, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v57, v31, v57, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v67
-; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v66
-; GFX11-NEXT: v_perm_b32 v58, v58, v59, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v34, v34, v63, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
-; GFX11-NEXT: v_or_b32_e32 v31, v33, v67
-; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v33, v57, v66
-; GFX11-NEXT: v_perm_b32 v66, v44, v45, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v67, v40, v41, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v56, v32, v56, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v58, 16, v58
-; GFX11-NEXT: v_perm_b32 v53, v177, v53, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v32, v34, v68
-; GFX11-NEXT: v_perm_b32 v27, v27, v46, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v65
-; GFX11-NEXT: v_perm_b32 v28, v28, v42, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v66, 16, v66
-; GFX11-NEXT: v_perm_b32 v68, v25, v183, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
-; GFX11-NEXT: v_perm_b32 v182, v26, v182, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v67, 16, v67
-; GFX11-NEXT: v_or_b32_e32 v34, v56, v58
-; GFX11-NEXT: v_perm_b32 v21, v21, v167, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-NEXT: v_or_b32_e32 v25, v27, v65
-; GFX11-NEXT: v_or_b32_e32 v26, v28, v66
-; GFX11-NEXT: v_or_b32_e32 v27, v68, v64
-; GFX11-NEXT: v_or_b32_e32 v28, v182, v67
+; GFX11-NEXT: v_perm_b32 v29, v29, v60, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v65, v59, v65, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v66, v73, v66, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v31, v72, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v32, v63, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v67, v61, v62, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v61, v65, 16, v29
+; GFX11-NEXT: v_perm_b32 v29, v30, v58, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v56, v57, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v59, v66, 16, v31
+; GFX11-NEXT: v_lshl_or_b32 v60, v67, 16, v32
+; GFX11-NEXT: v_perm_b32 v27, v27, v47, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v46, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v28, v45, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v43, v44, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v25, v42, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v54, v41, v54, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v65, v26, v40, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v66, v182, v183, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v62, v30, 16, v29
+; GFX11-NEXT: v_perm_b32 v23, v23, v181, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v180, v53, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v24, v179, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v177, v178, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v25, v31, 16, v27
+; GFX11-NEXT: v_lshl_or_b32 v26, v32, 16, v28
+; GFX11-NEXT: v_lshl_or_b32 v27, v54, 16, v64
+; GFX11-NEXT: v_lshl_or_b32 v28, v66, 16, v65
+; GFX11-NEXT: v_perm_b32 v31, v21, v176, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v167, v52, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v52, v22, v166, 0xc0c0004
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: scratch_store_b128 v0, v[31:34], off
+; GFX11-NEXT: scratch_store_b128 v0, v[59:62], off
; GFX11-NEXT: scratch_store_b128 v0, v[25:28], off offset:16
-; GFX11-NEXT: v_perm_b32 v26, v165, v166, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v25, v21, v53
-; GFX11-NEXT: v_perm_b32 v21, v22, v164, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v22, v163, v52, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v28, v151, v51, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v27, v161, v162, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT: v_perm_b32 v19, v19, v160, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_perm_b32 v17, v17, v149, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT: v_perm_b32 v20, v20, v150, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_or_b32_e32 v26, v21, v26
-; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
-; GFX11-NEXT: v_perm_b32 v22, v147, v148, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v21, v17, v28
-; GFX11-NEXT: v_perm_b32 v17, v18, v146, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v145, v50, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v28, v134, v49, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v20, v20, v27
-; GFX11-NEXT: v_perm_b32 v27, v135, v144, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_perm_b32 v15, v15, v133, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
+; GFX11-NEXT: v_lshl_or_b32 v21, v29, 16, v23
+; GFX11-NEXT: v_lshl_or_b32 v22, v30, 16, v24
+; GFX11-NEXT: v_perm_b32 v19, v19, v163, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v162, v51, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v20, v161, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v26, v151, v160, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v17, v150, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v149, v50, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v18, v148, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v146, v147, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v23, v32, 16, v31
+; GFX11-NEXT: v_perm_b32 v15, v15, v144, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v145, v49, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v17, v25, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v18, v26, 16, v20
+; GFX11-NEXT: v_lshl_or_b32 v19, v28, 16, v27
+; GFX11-NEXT: v_lshl_or_b32 v20, v30, 16, v29
; GFX11-NEXT: v_perm_b32 v13, v13, v132, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT: v_perm_b32 v16, v16, v131, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
-; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
-; GFX11-NEXT: v_perm_b32 v18, v129, v130, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v17, v13, v28
-; GFX11-NEXT: v_perm_b32 v28, v116, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v27
-; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v14, v119, v48, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v27, v117, v118, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v9, v9, v114, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT: v_perm_b32 v11, v11, v115, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v12, v12, v113, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v28
-; GFX11-NEXT: v_perm_b32 v9, v10, v102, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v101, v37, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
-; GFX11-NEXT: v_perm_b32 v14, v103, v112, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v27
-; GFX11-NEXT: v_perm_b32 v27, v99, v100, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v28, v98, v36, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v97, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v54, v181, v54, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v179, v180, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-NEXT: v_perm_b32 v27, v133, v48, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v11, v117, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v118, v38, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v25, v31, 16, v15
+; GFX11-NEXT: v_perm_b32 v15, v16, v130, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v131, v135, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v14, v14, v128, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v129, v134, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v27, v27, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v11, v29, 16, v11
+; GFX11-NEXT: v_perm_b32 v9, v9, v112, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v113, v37, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v97, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v98, v35, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v53, v164, v165, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v12, v115, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v116, v119, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v26, v16, 16, v15
+; GFX11-NEXT: v_perm_b32 v7, v7, v99, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v100, v36, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v8, v8, v87, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_perm_b32 v5, v5, v96, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
-; GFX11-NEXT: v_perm_b32 v10, v85, v86, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v23, v178, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT: v_perm_b32 v24, v24, v176, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v27
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v28
-; GFX11-NEXT: v_perm_b32 v5, v84, v35, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v27, v81, v83, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v28, v71, v29, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v29, v69, v70, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v80, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_or_b32_e32 v23, v23, v54
-; GFX11-NEXT: v_or_b32_e32 v24, v24, v64
-; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_perm_b32 v30, v1, v30, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT: v_perm_b32 v31, v2, v39, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v29, 16, v29
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v27
-; GFX11-NEXT: v_or_b32_e32 v3, v30, v28
-; GFX11-NEXT: v_or_b32_e32 v4, v31, v29
+; GFX11-NEXT: v_perm_b32 v16, v96, v101, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v28, v28, 16, v14
+; GFX11-NEXT: v_perm_b32 v10, v10, v102, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v14, v103, v114, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v9, v29, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v84, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v85, v86, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v24, v53, 16, v52
+; GFX11-NEXT: v_lshl_or_b32 v12, v30, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v7, v15, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v8, v16, 16, v8
+; GFX11-NEXT: v_perm_b32 v3, v3, v81, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v82, v34, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v69, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v70, v83, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v1, v71, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v80, v33, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v2, v55, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v39, v68, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v10, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v1, v15, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v16, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v30, 16, v29
+; GFX11-NEXT: v_lshl_or_b32 v4, v32, 16, v31
; GFX11-NEXT: s_clause 0x5
-; GFX11-NEXT: scratch_store_b128 v0, v[23:26], off offset:32
-; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
-; GFX11-NEXT: scratch_store_b128 v0, v[15:18], off offset:64
+; GFX11-NEXT: scratch_store_b128 v0, v[21:24], off offset:32
+; GFX11-NEXT: scratch_store_b128 v0, v[17:20], off offset:48
+; GFX11-NEXT: scratch_store_b128 v0, v[25:28], off offset:64
; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:80
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:96
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:112
@@ -55474,99 +55208,99 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:324
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:320
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:316
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:312
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:308
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:304
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:296
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:288
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:276
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:272
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:268
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:264
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:260
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:256
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:252
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:236
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:228
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:216
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:212
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:200
+; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:200
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:196
-; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:192
+; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:192
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:188
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:184
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:180
@@ -55575,371 +55309,315 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:168
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:164
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:160
-; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:156
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:156
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:152
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:148
-; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:144
-; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:140
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:144
+; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:140
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:136
-; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:132
-; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:128
-; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:124
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:132
+; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:128
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:124
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:120
-; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:116
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:108
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:108
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:100
-; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:92
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:76
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:64
-; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:48
-; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:12
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(41)
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(41)
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(39)
+; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(39)
+; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(37)
+; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(37)
+; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(35)
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(35)
+; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(33)
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(33)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(32)
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB39_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
-; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
-; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
-; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
-; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
-; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v45, v26
+; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_perm_b32 v12, v42, v41, s4
+; GFX9-NEXT: v_perm_b32 v13, v40, v54, s4
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX9-NEXT: v_perm_b32 v13, v55, v53, s4
+; GFX9-NEXT: v_perm_b32 v14, v52, v50, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_perm_b32 v14, v51, v49, s4
+; GFX9-NEXT: v_perm_b32 v15, v48, v38, s4
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX9-NEXT: v_perm_b32 v15, v39, v37, s4
+; GFX9-NEXT: v_perm_b32 v16, v35, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; GFX9-NEXT: v_perm_b32 v16, v36, v34, s4
+; GFX9-NEXT: v_perm_b32 v17, v32, v17, s4
+; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX9-NEXT: v_perm_b32 v17, v33, v63, s4
+; GFX9-NEXT: v_perm_b32 v18, v61, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: v_perm_b32 v18, v62, v60, s4
+; GFX9-NEXT: v_perm_b32 v19, v58, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX9-NEXT: v_perm_b32 v19, v59, v57, s4
+; GFX9-NEXT: v_perm_b32 v20, v47, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; GFX9-NEXT: v_perm_b32 v20, v56, v46, s4
+; GFX9-NEXT: v_perm_b32 v21, v44, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX9-NEXT: v_perm_b32 v21, v45, v43, s4
+; GFX9-NEXT: v_perm_b32 v22, v31, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; GFX9-NEXT: v_perm_b32 v22, v30, v29, s4
+; GFX9-NEXT: v_perm_b32 v23, v28, v23, s4
+; GFX9-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX9-NEXT: v_perm_b32 v23, v27, v26, s4
+; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
+; GFX9-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: v_mov_b32_e32 v44, v45
+; GFX9-NEXT: v_mov_b32_e32 v54, v53
+; GFX9-NEXT: v_mov_b32_e32 v40, v55
+; GFX9-NEXT: v_mov_b32_e32 v50, v49
+; GFX9-NEXT: v_mov_b32_e32 v52, v51
+; GFX9-NEXT: v_mov_b32_e32 v38, v37
+; GFX9-NEXT: v_mov_b32_e32 v48, v39
+; GFX9-NEXT: v_mov_b32_e32 v35, v34
+; GFX9-NEXT: v_mov_b32_e32 v32, v63
+; GFX9-NEXT: v_mov_b32_e32 v61, v60
+; GFX9-NEXT: v_mov_b32_e32 v58, v57
; GFX9-NEXT: v_mov_b32_e32 v47, v46
-; GFX9-NEXT: v_mov_b32_e32 v57, v56
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
+; GFX9-NEXT: v_perm_b32 v43, v45, v43, s4
+; GFX9-NEXT: v_lshl_or_b32 v31, v43, 16, v31
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB39_3
; GFX9-NEXT: .LBB39_2:
-; GFX9-NEXT: v_mov_b32_e32 v57, v56
+; GFX9-NEXT: v_mov_b32_e32 v40, v55
+; GFX9-NEXT: v_mov_b32_e32 v54, v53
+; GFX9-NEXT: v_mov_b32_e32 v52, v51
+; GFX9-NEXT: v_mov_b32_e32 v50, v49
+; GFX9-NEXT: v_mov_b32_e32 v48, v39
+; GFX9-NEXT: v_mov_b32_e32 v38, v37
+; GFX9-NEXT: v_mov_b32_e32 v35, v34
+; GFX9-NEXT: v_mov_b32_e32 v32, v63
+; GFX9-NEXT: v_mov_b32_e32 v61, v60
+; GFX9-NEXT: v_mov_b32_e32 v58, v57
; GFX9-NEXT: v_mov_b32_e32 v47, v46
-; GFX9-NEXT: v_mov_b32_e32 v45, v26
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
+; GFX9-NEXT: v_mov_b32_e32 v44, v45
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: .LBB39_3: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v43, v44
-; GFX9-NEXT: v_mov_b32_e32 v44, v45
-; GFX9-NEXT: v_mov_b32_e32 v45, v47
-; GFX9-NEXT: v_mov_b32_e32 v46, v57
-; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v43, v44
+; GFX9-NEXT: v_mov_b32_e32 v44, v47
+; GFX9-NEXT: v_mov_b32_e32 v47, v32
; GFX9-NEXT: s_cbranch_vccnz .LBB39_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -56040,250 +55718,258 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v10
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v10, v10, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_add_u32_e32 v16, 3, v32
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; GFX9-NEXT: s_add_i32 s6, s6, 3
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_add_u32_e32 v14, 3, v48
-; GFX9-NEXT: v_perm_b32 v14, v14, v39, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v15, 3, v36
-; GFX9-NEXT: v_perm_b32 v15, v15, v35, s5
-; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s5
-; GFX9-NEXT: v_add_u32_e32 v17, 3, v60
-; GFX9-NEXT: s_waitcnt vmcnt(16)
-; GFX9-NEXT: v_perm_b32 v17, v17, v18, s5
-; GFX9-NEXT: v_add_u32_e32 v18, 3, v57
-; GFX9-NEXT: s_waitcnt vmcnt(15)
-; GFX9-NEXT: v_perm_b32 v18, v18, v19, s5
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(15)
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(20)
; GFX9-NEXT: v_perm_b32 v11, s6, v12, v11
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_sdwa v17, v17, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_sdwa v18, v18, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s5
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v12, 3, v54
-; GFX9-NEXT: v_add_u32_e32 v13, 3, v52
-; GFX9-NEXT: v_perm_b32 v12, v12, v53, s5
-; GFX9-NEXT: v_perm_b32 v13, v13, v51, s5
+; GFX9-NEXT: v_add_u32_e32 v12, 3, v34
+; GFX9-NEXT: v_perm_b32 v12, v12, v41, s5
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v12
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
+; GFX9-NEXT: v_perm_b32 v13, v13, v14, s5
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v13, v13, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v12, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v13, 3, v50
-; GFX9-NEXT: v_perm_b32 v13, v13, v49, s5
+; GFX9-NEXT: v_add_u32_e32 v13, 3, v40
+; GFX9-NEXT: v_perm_b32 v13, v13, v54, s5
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
+; GFX9-NEXT: v_perm_b32 v14, v14, v15, s5
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v14, 3, v38
-; GFX9-NEXT: v_perm_b32 v14, v14, v37, s5
+; GFX9-NEXT: v_add_u32_e32 v14, 3, v52
+; GFX9-NEXT: v_perm_b32 v14, v14, v50, s5
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v14
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s5
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v15, 3, v34
-; GFX9-NEXT: v_perm_b32 v15, v15, v33, s5
+; GFX9-NEXT: v_add_u32_e32 v15, 3, v48
+; GFX9-NEXT: v_perm_b32 v15, v15, v38, s5
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v15
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v16, 3, v16
+; GFX9-NEXT: v_perm_b32 v16, v16, v17, s5
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v16, 3, v62
-; GFX9-NEXT: v_perm_b32 v16, v16, v61, s5
+; GFX9-NEXT: v_add_u32_e32 v16, 3, v36
+; GFX9-NEXT: v_perm_b32 v16, v16, v35, s5
; GFX9-NEXT: v_add_u32_e32 v16, 0x300, v16
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s5
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v17, v17, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v16, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v17, 3, v41
-; GFX9-NEXT: v_perm_b32 v17, v17, v40, s5
+; GFX9-NEXT: v_add_u32_e32 v17, 3, v33
+; GFX9-NEXT: v_perm_b32 v17, v17, v47, s5
; GFX9-NEXT: v_add_u32_e32 v17, 0x300, v17
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_add_u32_e32 v18, 3, v18
+; GFX9-NEXT: v_perm_b32 v18, v18, v19, s5
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v18, v18, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v18, 3, v42
-; GFX9-NEXT: v_perm_b32 v18, v18, v47, s5
+; GFX9-NEXT: v_add_u32_e32 v18, 3, v62
+; GFX9-NEXT: v_perm_b32 v18, v18, v61, s5
; GFX9-NEXT: v_add_u32_e32 v18, 0x300, v18
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
+; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v19, v19, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v18, v18, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v19, 3, v46
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_e32 v19, 3, v59
+; GFX9-NEXT: v_perm_b32 v19, v19, v58, s5
; GFX9-NEXT: v_add_u32_e32 v19, 0x300, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v20, 3, v20
; GFX9-NEXT: v_perm_b32 v20, v20, v21, s5
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v20, v20, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v19, v19, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v20, 3, v45
+; GFX9-NEXT: v_add_u32_e32 v20, 3, v56
; GFX9-NEXT: v_perm_b32 v20, v20, v44, s5
; GFX9-NEXT: v_add_u32_e32 v20, 0x300, v20
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v21, 3, v21
; GFX9-NEXT: v_perm_b32 v21, v21, v22, s5
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v21, v21, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v20, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_add_u32_e32 v21, 3, v43
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v21, v21, v22, s5
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v21, 0x300, v21
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: v_perm_b32 v22, v22, v23, s5
; GFX9-NEXT: v_add_u32_sdwa v22, v22, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v21, v21, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v22, v22, v23, s5
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v22, 0x300, v22
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: v_perm_b32 v23, v23, v24, s5
; GFX9-NEXT: v_add_u32_sdwa v23, v23, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v22, v22, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v23, v24, s5
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v23, 0x300, v23
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v24, 3, v24
; GFX9-NEXT: v_perm_b32 v24, v24, v25, s5
; GFX9-NEXT: v_add_u32_sdwa v24, v24, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v24, 3, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v24, v25, s5
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v24, 0x300, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v25, 3, v25
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s5
; GFX9-NEXT: v_add_u32_sdwa v25, v25, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v24, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v25, 3, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s5
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v25, 0x300, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v26, 3, v26
; GFX9-NEXT: v_perm_b32 v26, v26, v27, s5
; GFX9-NEXT: v_add_u32_sdwa v26, v26, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v26, 3, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v26, v27, s5
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v26, 0x300, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v27, 3, v27
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s5
; GFX9-NEXT: v_add_u32_sdwa v27, v27, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v26, v26, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s5
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v27, 0x300, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v28, 3, v28
; GFX9-NEXT: v_perm_b32 v28, v28, v29, s5
; GFX9-NEXT: v_add_u32_sdwa v28, v28, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v28, 3, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v28, v29, s5
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v28, 0x300, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v29, 3, v29
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s5
; GFX9-NEXT: v_add_u32_sdwa v29, v29, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v28, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v29, 3, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s5
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v29, 0x300, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v30, 3, v30
; GFX9-NEXT: v_perm_b32 v30, v30, v31, s5
; GFX9-NEXT: v_add_u32_sdwa v30, v30, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v30, 3, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v30, v31, s5
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v30, 0x300, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v31, 3, v31
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s5
; GFX9-NEXT: v_add_u32_sdwa v31, v31, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v30, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v31, 3, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s5
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v31, 0x300, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v32, 3, v32
@@ -56313,10 +55999,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v32f32_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
@@ -56438,149 +56121,109 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB39_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v163, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v147, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v6, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v132, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v129, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v114, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v101, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v99, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v83, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v14, 16, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v99, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, v23, v24
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v103, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v101, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, v23, v24
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v83, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, v29, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v65, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v40, v41
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v181, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v67, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v66, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v52, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v167, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v165, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v49, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v183, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v34, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v150, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v145, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v21, 16, v20
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v119, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v102, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v96, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v85, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v25, v27, 16, v26
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v70, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v65, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v31, 16, v30
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v39, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v40, 16, v183
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB39_3
; GFX11-TRUE16-NEXT: .LBB39_2: ; %cmp.true
@@ -56875,9 +56518,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v36, v35
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v33, v32
; GFX11-TRUE16-NEXT: .LBB39_3: ; %end
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB39_4:
@@ -56887,10 +56528,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v32f32_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
-; GFX11-FAKE16-NEXT: ; meta instruction
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:308
@@ -57012,149 +56650,109 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB39_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v180, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v164, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v163, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v147, v135, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v6, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v146, v134, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v132, v130, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v129, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v117, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v114, v112, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v101, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v100, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v84, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v83, v71, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v14, 16, v13
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v147, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v100, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v23, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v103, v99, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v101, v97, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v25, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v67, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v49, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v29, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v65, v53, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v31
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v183, 16, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v29, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-FAKE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v31, v183
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v40, v41
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v182, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v181, v177, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v67, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v66, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v167, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v165, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v49, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v183, v37, v33, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v40, v34, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v161, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v150, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v145, v133, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v144, v131, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v21, 16, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v128, v116, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v119, v115, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v103, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v102, v98, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v96, v86, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v85, v82, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v27, 16, v26
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v81, v69, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v70, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v65, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v31, 16, v30
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v48, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v39, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v40, 16, v183
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB39_3
; GFX11-FAKE16-NEXT: .LBB39_2: ; %cmp.true
@@ -57449,9 +57047,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v36, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v33, v32
; GFX11-FAKE16-NEXT: .LBB39_3: ; %end
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB39_4:
@@ -79903,33 +79499,33 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s83, s28, 8
; GFX9-NEXT: s_lshr_b32 s81, s27, 24
; GFX9-NEXT: v_writelane_b32 v30, s46, 49
-; GFX9-NEXT: s_lshr_b32 s53, s27, 8
+; GFX9-NEXT: s_lshr_b32 s52, s27, 8
; GFX9-NEXT: s_lshr_b32 s82, s26, 16
-; GFX9-NEXT: s_lshr_b32 s67, s26, 8
+; GFX9-NEXT: s_lshr_b32 s51, s26, 8
; GFX9-NEXT: s_lshr_b32 s84, s25, 24
; GFX9-NEXT: s_lshr_b32 s96, s25, 16
; GFX9-NEXT: s_lshr_b32 s65, s25, 8
; GFX9-NEXT: s_lshr_b32 s86, s24, 16
-; GFX9-NEXT: s_lshr_b32 s55, s24, 8
+; GFX9-NEXT: s_lshr_b32 s66, s24, 8
; GFX9-NEXT: s_lshr_b32 s98, s23, 24
; GFX9-NEXT: s_lshr_b32 s87, s23, 16
-; GFX9-NEXT: s_lshr_b32 s66, s23, 8
+; GFX9-NEXT: s_lshr_b32 s55, s23, 8
; GFX9-NEXT: s_lshr_b32 s97, s22, 16
; GFX9-NEXT: s_lshr_b32 s64, s22, 8
; GFX9-NEXT: s_lshr_b32 s49, s21, 24
; GFX9-NEXT: s_lshr_b32 s99, s21, 16
; GFX9-NEXT: s_lshr_b32 s80, s21, 8
-; GFX9-NEXT: s_lshr_b32 s39, s20, 16
+; GFX9-NEXT: s_lshr_b32 s48, s20, 16
; GFX9-NEXT: s_lshr_b32 s70, s20, 8
-; GFX9-NEXT: s_lshr_b32 s48, s19, 24
+; GFX9-NEXT: s_lshr_b32 s39, s19, 24
; GFX9-NEXT: s_lshr_b32 s38, s19, 16
; GFX9-NEXT: s_lshr_b32 s68, s19, 8
; GFX9-NEXT: s_lshr_b32 s54, s18, 16
; GFX9-NEXT: s_lshr_b32 s69, s18, 8
-; GFX9-NEXT: s_lshr_b32 s52, s17, 24
+; GFX9-NEXT: s_lshr_b32 s53, s17, 24
; GFX9-NEXT: s_lshr_b32 s50, s17, 16
; GFX9-NEXT: s_lshr_b32 s71, s17, 8
-; GFX9-NEXT: s_lshr_b32 s51, s16, 16
+; GFX9-NEXT: s_lshr_b32 s67, s16, 16
; GFX9-NEXT: s_lshr_b32 s85, s16, 8
; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
; GFX9-NEXT: s_lshr_b64 s[56:57], s[6:7], 24
@@ -80083,33 +79679,33 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: s_lshr_b32 s83, s28, 8
; GFX9-NEXT: s_lshr_b32 s81, s27, 24
; GFX9-NEXT: v_writelane_b32 v30, s46, 49
-; GFX9-NEXT: s_lshr_b32 s53, s27, 8
+; GFX9-NEXT: s_lshr_b32 s52, s27, 8
; GFX9-NEXT: s_lshr_b32 s82, s26, 16
-; GFX9-NEXT: s_lshr_b32 s67, s26, 8
+; GFX9-NEXT: s_lshr_b32 s51, s26, 8
; GFX9-NEXT: s_lshr_b32 s84, s25, 24
; GFX9-NEXT: s_lshr_b32 s96, s25, 16
; GFX9-NEXT: s_lshr_b32 s65, s25, 8
; GFX9-NEXT: s_lshr_b32 s86, s24, 16
-; GFX9-NEXT: s_lshr_b32 s55, s24, 8
+; GFX9-NEXT: s_lshr_b32 s66, s24, 8
; GFX9-NEXT: s_lshr_b32 s98, s23, 24
; GFX9-NEXT: s_lshr_b32 s87, s23, 16
-; GFX9-NEXT: s_lshr_b32 s66, s23, 8
+; GFX9-NEXT: s_lshr_b32 s55, s23, 8
; GFX9-NEXT: s_lshr_b32 s97, s22, 16
; GFX9-NEXT: s_lshr_b32 s64, s22, 8
; GFX9-NEXT: s_lshr_b32 s49, s21, 24
; GFX9-NEXT: s_lshr_b32 s99, s21, 16
; GFX9-NEXT: s_lshr_b32 s80, s21, 8
-; GFX9-NEXT: s_lshr_b32 s39, s20, 16
+; GFX9-NEXT: s_lshr_b32 s48, s20, 16
; GFX9-NEXT: s_lshr_b32 s70, s20, 8
-; GFX9-NEXT: s_lshr_b32 s48, s19, 24
+; GFX9-NEXT: s_lshr_b32 s39, s19, 24
; GFX9-NEXT: s_lshr_b32 s38, s19, 16
; GFX9-NEXT: s_lshr_b32 s68, s19, 8
; GFX9-NEXT: s_lshr_b32 s54, s18, 16
; GFX9-NEXT: s_lshr_b32 s69, s18, 8
-; GFX9-NEXT: s_lshr_b32 s52, s17, 24
+; GFX9-NEXT: s_lshr_b32 s53, s17, 24
; GFX9-NEXT: s_lshr_b32 s50, s17, 16
; GFX9-NEXT: s_lshr_b32 s71, s17, 8
-; GFX9-NEXT: s_lshr_b32 s51, s16, 16
+; GFX9-NEXT: s_lshr_b32 s67, s16, 16
; GFX9-NEXT: s_lshr_b32 s85, s16, 8
; GFX9-NEXT: s_lshr_b64 s[46:47], s[4:5], 24
; GFX9-NEXT: s_lshr_b64 s[56:57], s[6:7], 24
@@ -80128,166 +79724,146 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: s_lshr_b64 s[34:35], s[18:19], 24
; GFX9-NEXT: s_lshr_b64 s[36:37], s[16:17], 24
; GFX9-NEXT: .LBB57_3: ; %end
-; GFX9-NEXT: v_mov_b32_e32 v8, s36
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s85
-; GFX9-NEXT: v_perm_b32 v8, s51, v8, v1
-; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
-; GFX9-NEXT: v_mov_b32_e32 v21, s52
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v4, s71
-; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v8
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
+; GFX9-NEXT: v_mov_b32_e32 v21, s53
+; GFX9-NEXT: v_perm_b32 v3, s16, v2, v1
; GFX9-NEXT: v_perm_b32 v2, s17, v4, v1
-; GFX9-NEXT: v_mov_b32_e32 v11, s34
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v21
+; GFX9-NEXT: v_mov_b32_e32 v8, s34
; GFX9-NEXT: v_mov_b32_e32 v4, s69
-; GFX9-NEXT: v_perm_b32 v11, s54, v11, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
-; GFX9-NEXT: v_mov_b32_e32 v22, s48
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v11
+; GFX9-NEXT: v_perm_b32 v21, s50, v21, v1
; GFX9-NEXT: v_mov_b32_e32 v6, s68
-; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
+; GFX9-NEXT: v_perm_b32 v5, s18, v4, v1
+; GFX9-NEXT: v_perm_b32 v8, s54, v8, v1
+; GFX9-NEXT: v_mov_b32_e32 v22, s39
+; GFX9-NEXT: v_lshl_or_b32 v2, v21, 16, v2
; GFX9-NEXT: v_perm_b32 v4, s19, v6, v1
-; GFX9-NEXT: v_mov_b32_e32 v14, s30
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v22
+; GFX9-NEXT: v_mov_b32_e32 v9, s30
; GFX9-NEXT: v_mov_b32_e32 v6, s70
-; GFX9-NEXT: v_perm_b32 v14, s39, v14, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX9-NEXT: v_perm_b32 v7, s20, v6, v1
+; GFX9-NEXT: v_perm_b32 v22, s38, v22, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_lshl_or_b32 v2, v8, 16, v5
+; GFX9-NEXT: v_mov_b32_e32 v10, s80
+; GFX9-NEXT: v_perm_b32 v11, s20, v6, v1
+; GFX9-NEXT: v_perm_b32 v9, s48, v9, v1
; GFX9-NEXT: v_mov_b32_e32 v23, s49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v14
-; GFX9-NEXT: v_mov_b32_e32 v9, s80
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: v_lshl_or_b32 v2, v22, 16, v4
+; GFX9-NEXT: v_perm_b32 v6, s21, v10, v1
+; GFX9-NEXT: v_mov_b32_e32 v10, s94
+; GFX9-NEXT: v_mov_b32_e32 v12, s64
; GFX9-NEXT: v_perm_b32 v23, s99, v23, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v7, v2
-; GFX9-NEXT: v_perm_b32 v6, s21, v9, v1
-; GFX9-NEXT: v_mov_b32_e32 v15, s94
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v23
-; GFX9-NEXT: v_mov_b32_e32 v9, s64
-; GFX9-NEXT: v_perm_b32 v15, s97, v15, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v6, v2
-; GFX9-NEXT: v_perm_b32 v10, s22, v9, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: v_lshl_or_b32 v2, v9, 16, v11
+; GFX9-NEXT: v_mov_b32_e32 v13, s55
+; GFX9-NEXT: v_perm_b32 v12, s22, v12, v1
+; GFX9-NEXT: v_perm_b32 v10, s97, v10, v1
; GFX9-NEXT: v_mov_b32_e32 v24, s98
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v15
-; GFX9-NEXT: v_mov_b32_e32 v12, s66
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: v_lshl_or_b32 v2, v23, 16, v6
+; GFX9-NEXT: v_perm_b32 v13, s23, v13, v1
+; GFX9-NEXT: v_mov_b32_e32 v14, s92
+; GFX9-NEXT: v_mov_b32_e32 v15, s66
; GFX9-NEXT: v_perm_b32 v24, s87, v24, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v10, v2
-; GFX9-NEXT: v_perm_b32 v9, s23, v12, v1
-; GFX9-NEXT: v_mov_b32_e32 v16, s92
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v24
-; GFX9-NEXT: v_mov_b32_e32 v12, s55
-; GFX9-NEXT: v_perm_b32 v16, s86, v16, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v9, v2
-; GFX9-NEXT: v_perm_b32 v13, s24, v12, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: v_lshl_or_b32 v2, v10, 16, v12
+; GFX9-NEXT: v_mov_b32_e32 v16, s65
+; GFX9-NEXT: v_perm_b32 v15, s24, v15, v1
+; GFX9-NEXT: v_perm_b32 v14, s86, v14, v1
; GFX9-NEXT: v_mov_b32_e32 v25, s84
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v16
-; GFX9-NEXT: v_mov_b32_e32 v17, s65
-; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v13, v2
-; GFX9-NEXT: v_perm_b32 v12, s25, v17, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: v_lshl_or_b32 v2, v24, 16, v13
+; GFX9-NEXT: v_perm_b32 v16, s25, v16, v1
; GFX9-NEXT: v_mov_b32_e32 v17, s90
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v25
-; GFX9-NEXT: v_mov_b32_e32 v18, s67
-; GFX9-NEXT: v_perm_b32 v17, s82, v17, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v12, v2
+; GFX9-NEXT: v_mov_b32_e32 v18, s51
+; GFX9-NEXT: v_perm_b32 v25, s96, v25, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: v_lshl_or_b32 v2, v14, 16, v15
+; GFX9-NEXT: v_mov_b32_e32 v7, s36
+; GFX9-NEXT: v_mov_b32_e32 v19, s52
; GFX9-NEXT: v_perm_b32 v18, s26, v18, v1
+; GFX9-NEXT: v_perm_b32 v17, s82, v17, v1
; GFX9-NEXT: v_mov_b32_e32 v26, s81
; GFX9-NEXT: v_readlane_b32 s16, v30, 49
-; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v17
-; GFX9-NEXT: v_mov_b32_e32 v19, s53
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: v_lshl_or_b32 v2, v25, 16, v16
+; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
+; GFX9-NEXT: v_perm_b32 v7, s67, v7, v1
; GFX9-NEXT: v_perm_b32 v26, s16, v26, v1
; GFX9-NEXT: v_readlane_b32 s16, v30, 47
-; GFX9-NEXT: v_or_b32_e32 v2, v18, v2
-; GFX9-NEXT: v_perm_b32 v19, s27, v19, v1
+; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: v_lshl_or_b32 v2, v17, 16, v18
; GFX9-NEXT: v_mov_b32_e32 v20, s88
+; GFX9-NEXT: v_mov_b32_e32 v27, s83
; GFX9-NEXT: v_mov_b32_e32 v28, s16
+; GFX9-NEXT: v_lshl_or_b32 v3, v7, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 48
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v26
-; GFX9-NEXT: v_mov_b32_e32 v27, s83
+; GFX9-NEXT: v_lshl_or_b32 v2, v26, 16, v19
+; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v3, s16, v20, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v19, v2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_perm_b32 v2, s28, v27, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_readlane_b32 s16, v30, 45
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 46
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v2, s29, v28, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 44
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s78
; GFX9-NEXT: v_readlane_b32 s16, v30, 43
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s44, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 42
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 40
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 41
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s45, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 39
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s76
; GFX9-NEXT: v_readlane_b32 s16, v30, 38
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s42, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 37
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:64
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 35
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 36
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s43, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 34
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:68
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: v_readlane_b32 s16, v30, 33
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s40, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 32
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:72
; GFX9-NEXT: v_mov_b32_e32 v2, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 30
; GFX9-NEXT: v_mov_b32_e32 v3, s16
; GFX9-NEXT: v_readlane_b32 s16, v30, 31
-; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s41, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s16, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s16, v30, 29
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:76
; GFX9-NEXT: v_mov_b32_e32 v2, s16
@@ -80295,18 +79871,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: v_readlane_b32 s14, v30, 28
; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s14, v30, 27
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:80
; GFX9-NEXT: v_mov_b32_e32 v2, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 25
; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: v_readlane_b32 s14, v30, 26
-; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s15, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s14, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s14, v30, 24
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: v_mov_b32_e32 v2, s14
@@ -80314,18 +79888,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s62
; GFX9-NEXT: v_readlane_b32 s12, v30, 23
; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s12, v30, 22
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: v_mov_b32_e32 v2, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 20
; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: v_readlane_b32 s12, v30, 21
-; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s13, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s12, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s12, v30, 19
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: v_mov_b32_e32 v2, s12
@@ -80333,18 +79905,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s60
; GFX9-NEXT: v_readlane_b32 s10, v30, 18
; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s10, v30, 17
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: v_mov_b32_e32 v2, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 15
; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_readlane_b32 s10, v30, 16
-; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s11, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s10, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s10, v30, 14
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: v_mov_b32_e32 v2, s10
@@ -80352,18 +79922,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s58
; GFX9-NEXT: v_readlane_b32 s8, v30, 13
; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s8, v30, 12
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:104
; GFX9-NEXT: v_mov_b32_e32 v2, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 10
; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_readlane_b32 s8, v30, 11
-; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s9, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s8, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s8, v30, 9
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:108
; GFX9-NEXT: v_mov_b32_e32 v2, s8
@@ -80371,18 +79939,16 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_readlane_b32 s6, v30, 8
; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s6, v30, 7
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 5
; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_readlane_b32 s6, v30, 6
-; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
; GFX9-NEXT: v_perm_b32 v2, s7, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s6, v3, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s6, v30, 4
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: v_mov_b32_e32 v2, s6
@@ -80390,8 +79956,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: v_readlane_b32 s4, v30, 3
; GFX9-NEXT: v_perm_b32 v3, s4, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_readlane_b32 s4, v30, 2
; GFX9-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: v_mov_b32_e32 v2, s4
@@ -80400,8 +79965,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: v_readlane_b32 s4, v30, 1
; GFX9-NEXT: v_perm_b32 v2, s5, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s4, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: v_readlane_b32 s30, v29, 34
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: v_readlane_b32 s31, v29, 35
@@ -80451,33 +80015,33 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: ; kill: killed $sgpr46
; GFX9-NEXT: ; implicit-def: $sgpr85
-; GFX9-NEXT: ; implicit-def: $sgpr51
+; GFX9-NEXT: ; implicit-def: $sgpr67
; GFX9-NEXT: ; implicit-def: $sgpr71
; GFX9-NEXT: ; implicit-def: $sgpr50
-; GFX9-NEXT: ; implicit-def: $sgpr52
+; GFX9-NEXT: ; implicit-def: $sgpr53
; GFX9-NEXT: ; implicit-def: $sgpr69
; GFX9-NEXT: ; implicit-def: $sgpr54
; GFX9-NEXT: ; implicit-def: $sgpr68
; GFX9-NEXT: ; implicit-def: $sgpr38
-; GFX9-NEXT: ; implicit-def: $sgpr48
-; GFX9-NEXT: ; implicit-def: $sgpr70
; GFX9-NEXT: ; implicit-def: $sgpr39
+; GFX9-NEXT: ; implicit-def: $sgpr70
+; GFX9-NEXT: ; implicit-def: $sgpr48
; GFX9-NEXT: ; implicit-def: $sgpr80
; GFX9-NEXT: ; implicit-def: $sgpr99
; GFX9-NEXT: ; implicit-def: $sgpr49
; GFX9-NEXT: ; implicit-def: $sgpr64
; GFX9-NEXT: ; implicit-def: $sgpr97
-; GFX9-NEXT: ; implicit-def: $sgpr66
+; GFX9-NEXT: ; implicit-def: $sgpr55
; GFX9-NEXT: ; implicit-def: $sgpr87
; GFX9-NEXT: ; implicit-def: $sgpr98
-; GFX9-NEXT: ; implicit-def: $sgpr55
+; GFX9-NEXT: ; implicit-def: $sgpr66
; GFX9-NEXT: ; implicit-def: $sgpr86
; GFX9-NEXT: ; implicit-def: $sgpr65
; GFX9-NEXT: ; implicit-def: $sgpr96
; GFX9-NEXT: ; implicit-def: $sgpr84
-; GFX9-NEXT: ; implicit-def: $sgpr67
+; GFX9-NEXT: ; implicit-def: $sgpr51
; GFX9-NEXT: ; implicit-def: $sgpr82
-; GFX9-NEXT: ; implicit-def: $sgpr53
+; GFX9-NEXT: ; implicit-def: $sgpr52
; GFX9-NEXT: ; implicit-def: $sgpr81
; GFX9-NEXT: ; implicit-def: $sgpr83
; GFX9-NEXT: ; implicit-def: $sgpr36
@@ -80672,62 +80236,62 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: s_lshr_b32 s42, s5, 16
; GFX11-NEXT: s_lshr_b32 s34, s27, 16
; GFX11-NEXT: s_lshr_b32 s35, s27, 8
-; GFX11-NEXT: s_lshr_b32 s37, s26, 16
+; GFX11-NEXT: s_lshr_b32 s36, s26, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 1
; GFX11-NEXT: s_lshr_b32 s42, s5, 8
-; GFX11-NEXT: s_lshr_b32 s36, s26, 8
-; GFX11-NEXT: s_lshr_b32 s39, s25, 24
-; GFX11-NEXT: s_lshr_b32 s48, s25, 16
+; GFX11-NEXT: s_lshr_b32 s37, s26, 8
+; GFX11-NEXT: s_lshr_b32 s38, s25, 24
+; GFX11-NEXT: s_lshr_b32 s39, s25, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 2
; GFX11-NEXT: s_lshr_b32 s42, s4, 16
-; GFX11-NEXT: s_lshr_b32 s38, s25, 8
-; GFX11-NEXT: s_lshr_b32 s50, s24, 16
-; GFX11-NEXT: s_lshr_b32 s49, s24, 8
+; GFX11-NEXT: s_lshr_b32 s48, s25, 8
+; GFX11-NEXT: s_lshr_b32 s49, s24, 16
+; GFX11-NEXT: s_lshr_b32 s50, s24, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 3
; GFX11-NEXT: s_lshr_b32 s42, s4, 8
-; GFX11-NEXT: s_lshr_b32 s52, s23, 24
-; GFX11-NEXT: s_lshr_b32 s53, s23, 16
-; GFX11-NEXT: s_lshr_b32 s51, s23, 8
+; GFX11-NEXT: s_lshr_b32 s51, s23, 24
+; GFX11-NEXT: s_lshr_b32 s52, s23, 16
+; GFX11-NEXT: s_lshr_b32 s55, s23, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 4
; GFX11-NEXT: s_lshr_b32 s42, s7, 24
-; GFX11-NEXT: s_lshr_b32 s69, s22, 16
-; GFX11-NEXT: s_lshr_b32 s54, s22, 8
-; GFX11-NEXT: s_lshr_b32 s55, s21, 24
+; GFX11-NEXT: s_lshr_b32 s64, s22, 16
+; GFX11-NEXT: s_lshr_b32 s66, s22, 8
+; GFX11-NEXT: s_lshr_b32 s53, s21, 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 5
; GFX11-NEXT: s_lshr_b32 s42, s7, 16
-; GFX11-NEXT: s_lshr_b32 s64, s21, 16
-; GFX11-NEXT: s_lshr_b32 s65, s21, 8
-; GFX11-NEXT: s_lshr_b32 s82, s20, 16
+; GFX11-NEXT: s_lshr_b32 s54, s21, 16
+; GFX11-NEXT: s_lshr_b32 s70, s21, 8
+; GFX11-NEXT: s_lshr_b32 s71, s20, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 6
; GFX11-NEXT: s_lshr_b32 s42, s7, 8
-; GFX11-NEXT: s_lshr_b32 s68, s20, 8
-; GFX11-NEXT: s_lshr_b32 s66, s19, 24
+; GFX11-NEXT: s_lshr_b32 s80, s20, 8
+; GFX11-NEXT: s_lshr_b32 s65, s19, 24
; GFX11-NEXT: s_lshr_b32 s67, s19, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 7
; GFX11-NEXT: s_lshr_b32 s42, s6, 16
-; GFX11-NEXT: s_lshr_b32 s85, s19, 8
+; GFX11-NEXT: s_lshr_b32 s84, s19, 8
; GFX11-NEXT: s_lshr_b32 s86, s18, 16
; GFX11-NEXT: s_lshr_b32 s87, s18, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 8
; GFX11-NEXT: s_lshr_b32 s42, s6, 8
-; GFX11-NEXT: s_lshr_b32 s70, s17, 24
-; GFX11-NEXT: s_lshr_b32 s71, s17, 16
+; GFX11-NEXT: s_lshr_b32 s68, s17, 24
+; GFX11-NEXT: s_lshr_b32 s69, s17, 16
; GFX11-NEXT: s_lshr_b32 s96, s17, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 9
; GFX11-NEXT: s_lshr_b32 s42, s9, 24
; GFX11-NEXT: s_lshr_b32 s97, s16, 16
; GFX11-NEXT: s_lshr_b32 s98, s16, 8
-; GFX11-NEXT: s_lshr_b32 s80, s3, 24
+; GFX11-NEXT: s_lshr_b32 s81, s3, 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 10
; GFX11-NEXT: s_lshr_b32 s42, s9, 16
-; GFX11-NEXT: s_lshr_b32 s81, s3, 16
+; GFX11-NEXT: s_lshr_b32 s82, s3, 16
; GFX11-NEXT: s_lshr_b32 s99, s3, 8
; GFX11-NEXT: s_lshr_b32 s100, s2, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 11
; GFX11-NEXT: s_lshr_b32 s42, s9, 8
; GFX11-NEXT: s_lshr_b32 s101, s2, 8
; GFX11-NEXT: s_lshr_b32 s83, s1, 24
-; GFX11-NEXT: s_lshr_b32 s84, s1, 16
+; GFX11-NEXT: s_lshr_b32 s85, s1, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 12
; GFX11-NEXT: s_lshr_b32 s42, s8, 16
; GFX11-NEXT: s_lshr_b32 s102, s1, 8
@@ -80745,13 +80309,13 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: s_lshr_b64 s[62:63], s[40:41], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 15
; GFX11-NEXT: s_lshr_b32 s42, s11, 16
-; GFX11-NEXT: s_lshr_b64 s[74:75], s[28:29], 24
-; GFX11-NEXT: s_lshr_b64 s[76:77], s[26:27], 24
+; GFX11-NEXT: s_lshr_b64 s[76:77], s[28:29], 24
+; GFX11-NEXT: s_lshr_b64 s[88:89], s[26:27], 24
; GFX11-NEXT: s_lshr_b64 s[72:73], s[24:25], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 16
; GFX11-NEXT: s_lshr_b32 s42, s11, 8
-; GFX11-NEXT: s_lshr_b64 s[78:79], s[22:23], 24
-; GFX11-NEXT: s_lshr_b64 s[88:89], s[20:21], 24
+; GFX11-NEXT: s_lshr_b64 s[74:75], s[22:23], 24
+; GFX11-NEXT: s_lshr_b64 s[78:79], s[20:21], 24
; GFX11-NEXT: s_lshr_b64 s[90:91], s[18:19], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 17
; GFX11-NEXT: s_lshr_b32 s42, s10, 16
@@ -80854,53 +80418,53 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: v_writelane_b32 v26, s42, 0
; GFX11-NEXT: s_lshr_b32 s42, s5, 16
; GFX11-NEXT: s_lshr_b32 s35, s27, 8
-; GFX11-NEXT: s_lshr_b32 s37, s26, 16
-; GFX11-NEXT: s_lshr_b32 s36, s26, 8
+; GFX11-NEXT: s_lshr_b32 s36, s26, 16
+; GFX11-NEXT: s_lshr_b32 s37, s26, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 1
; GFX11-NEXT: s_lshr_b32 s42, s5, 8
-; GFX11-NEXT: s_lshr_b32 s39, s25, 24
-; GFX11-NEXT: s_lshr_b32 s48, s25, 16
-; GFX11-NEXT: s_lshr_b32 s38, s25, 8
+; GFX11-NEXT: s_lshr_b32 s38, s25, 24
+; GFX11-NEXT: s_lshr_b32 s39, s25, 16
+; GFX11-NEXT: s_lshr_b32 s48, s25, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 2
; GFX11-NEXT: s_lshr_b32 s42, s4, 16
-; GFX11-NEXT: s_lshr_b32 s50, s24, 16
-; GFX11-NEXT: s_lshr_b32 s49, s24, 8
-; GFX11-NEXT: s_lshr_b32 s52, s23, 24
+; GFX11-NEXT: s_lshr_b32 s49, s24, 16
+; GFX11-NEXT: s_lshr_b32 s50, s24, 8
+; GFX11-NEXT: s_lshr_b32 s51, s23, 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 3
; GFX11-NEXT: s_lshr_b32 s42, s4, 8
-; GFX11-NEXT: s_lshr_b32 s53, s23, 16
-; GFX11-NEXT: s_lshr_b32 s51, s23, 8
-; GFX11-NEXT: s_lshr_b32 s69, s22, 16
+; GFX11-NEXT: s_lshr_b32 s52, s23, 16
+; GFX11-NEXT: s_lshr_b32 s55, s23, 8
+; GFX11-NEXT: s_lshr_b32 s64, s22, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 4
; GFX11-NEXT: s_lshr_b32 s42, s7, 24
-; GFX11-NEXT: s_lshr_b32 s54, s22, 8
-; GFX11-NEXT: s_lshr_b32 s55, s21, 24
-; GFX11-NEXT: s_lshr_b32 s64, s21, 16
+; GFX11-NEXT: s_lshr_b32 s66, s22, 8
+; GFX11-NEXT: s_lshr_b32 s53, s21, 24
+; GFX11-NEXT: s_lshr_b32 s54, s21, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 5
; GFX11-NEXT: s_lshr_b32 s42, s7, 16
-; GFX11-NEXT: s_lshr_b32 s65, s21, 8
-; GFX11-NEXT: s_lshr_b32 s82, s20, 16
-; GFX11-NEXT: s_lshr_b32 s68, s20, 8
+; GFX11-NEXT: s_lshr_b32 s70, s21, 8
+; GFX11-NEXT: s_lshr_b32 s71, s20, 16
+; GFX11-NEXT: s_lshr_b32 s80, s20, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 6
; GFX11-NEXT: s_lshr_b32 s42, s7, 8
-; GFX11-NEXT: s_lshr_b32 s66, s19, 24
+; GFX11-NEXT: s_lshr_b32 s65, s19, 24
; GFX11-NEXT: s_lshr_b32 s67, s19, 16
-; GFX11-NEXT: s_lshr_b32 s85, s19, 8
+; GFX11-NEXT: s_lshr_b32 s84, s19, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 7
; GFX11-NEXT: s_lshr_b32 s42, s6, 16
; GFX11-NEXT: s_lshr_b32 s86, s18, 16
; GFX11-NEXT: s_lshr_b32 s87, s18, 8
-; GFX11-NEXT: s_lshr_b32 s70, s17, 24
+; GFX11-NEXT: s_lshr_b32 s68, s17, 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 8
; GFX11-NEXT: s_lshr_b32 s42, s6, 8
-; GFX11-NEXT: s_lshr_b32 s71, s17, 16
+; GFX11-NEXT: s_lshr_b32 s69, s17, 16
; GFX11-NEXT: s_lshr_b32 s96, s17, 8
; GFX11-NEXT: s_lshr_b32 s97, s16, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 9
; GFX11-NEXT: s_lshr_b32 s42, s9, 24
; GFX11-NEXT: s_lshr_b32 s98, s16, 8
-; GFX11-NEXT: s_lshr_b32 s80, s3, 24
-; GFX11-NEXT: s_lshr_b32 s81, s3, 16
+; GFX11-NEXT: s_lshr_b32 s81, s3, 24
+; GFX11-NEXT: s_lshr_b32 s82, s3, 16
; GFX11-NEXT: v_writelane_b32 v26, s42, 10
; GFX11-NEXT: s_lshr_b32 s42, s9, 16
; GFX11-NEXT: s_lshr_b32 s99, s3, 8
@@ -80909,7 +80473,7 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: v_writelane_b32 v26, s42, 11
; GFX11-NEXT: s_lshr_b32 s42, s9, 8
; GFX11-NEXT: s_lshr_b32 s83, s1, 24
-; GFX11-NEXT: s_lshr_b32 s84, s1, 16
+; GFX11-NEXT: s_lshr_b32 s85, s1, 16
; GFX11-NEXT: s_lshr_b32 s102, s1, 8
; GFX11-NEXT: v_writelane_b32 v26, s42, 12
; GFX11-NEXT: s_lshr_b32 s42, s8, 16
@@ -80925,15 +80489,15 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: s_lshr_b32 s42, s11, 24
; GFX11-NEXT: s_lshr_b64 s[60:61], s[14:15], 24
; GFX11-NEXT: s_lshr_b64 s[62:63], s[40:41], 24
-; GFX11-NEXT: s_lshr_b64 s[74:75], s[28:29], 24
+; GFX11-NEXT: s_lshr_b64 s[76:77], s[28:29], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 15
; GFX11-NEXT: s_lshr_b32 s42, s11, 16
-; GFX11-NEXT: s_lshr_b64 s[76:77], s[26:27], 24
+; GFX11-NEXT: s_lshr_b64 s[88:89], s[26:27], 24
; GFX11-NEXT: s_lshr_b64 s[72:73], s[24:25], 24
-; GFX11-NEXT: s_lshr_b64 s[78:79], s[22:23], 24
+; GFX11-NEXT: s_lshr_b64 s[74:75], s[22:23], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 16
; GFX11-NEXT: s_lshr_b32 s42, s11, 8
-; GFX11-NEXT: s_lshr_b64 s[88:89], s[20:21], 24
+; GFX11-NEXT: s_lshr_b64 s[78:79], s[20:21], 24
; GFX11-NEXT: s_lshr_b64 s[90:91], s[18:19], 24
; GFX11-NEXT: s_lshr_b64 s[92:93], s[16:17], 24
; GFX11-NEXT: v_writelane_b32 v26, s42, 17
@@ -80996,240 +80560,208 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: v_writelane_b32 v25, s42, 7
; GFX11-NEXT: s_lshr_b64 s[42:43], s[4:5], 24
; GFX11-NEXT: .LBB57_3: ; %end
-; GFX11-NEXT: v_mov_b32_e32 v1, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v2, s103, s30, v1
+; GFX11-NEXT: v_mov_b32_e32 v12, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, s103, s30, v12
+; GFX11-NEXT: v_perm_b32 v2, s0, s104, v12
+; GFX11-NEXT: v_perm_b32 v3, s1, s102, v12
+; GFX11-NEXT: v_perm_b32 v4, s100, s94, v12
+; GFX11-NEXT: v_perm_b32 v5, s2, s101, v12
+; GFX11-NEXT: v_perm_b32 v6, s3, s99, v12
+; GFX11-NEXT: v_perm_b32 v20, s85, s83, v12
+; GFX11-NEXT: v_perm_b32 v21, s82, s81, v12
+; GFX11-NEXT: v_lshl_or_b32 v1, v1, 16, v2
+; GFX11-NEXT: v_perm_b32 v7, s97, s92, v12
+; GFX11-NEXT: v_perm_b32 v8, s16, s98, v12
+; GFX11-NEXT: v_lshl_or_b32 v2, v20, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v4, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v4, v21, 16, v6
+; GFX11-NEXT: v_perm_b32 v9, s17, s96, v12
+; GFX11-NEXT: v_perm_b32 v10, s86, s90, v12
+; GFX11-NEXT: v_perm_b32 v11, s18, s87, v12
+; GFX11-NEXT: v_perm_b32 v13, s19, s84, v12
+; GFX11-NEXT: v_perm_b32 v22, s69, s68, v12
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
+; GFX11-NEXT: v_perm_b32 v4, s67, s65, v12
+; GFX11-NEXT: v_perm_b32 v16, s21, s70, v12
+; GFX11-NEXT: v_lshl_or_b32 v1, v7, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v2, v22, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v3, v10, 16, v11
+; GFX11-NEXT: v_lshl_or_b32 v4, v4, 16, v13
+; GFX11-NEXT: v_perm_b32 v5, s54, s53, v12
+; GFX11-NEXT: v_perm_b32 v6, s49, s72, v12
+; GFX11-NEXT: v_perm_b32 v7, s25, s48, v12
+; GFX11-NEXT: v_perm_b32 v8, s39, s38, v12
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:16
+; GFX11-NEXT: v_lshl_or_b32 v2, v5, 16, v16
+; GFX11-NEXT: v_perm_b32 v5, s24, s50, v12
+; GFX11-NEXT: v_perm_b32 v9, s26, s37, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 7
+; GFX11-NEXT: v_perm_b32 v14, s71, s78, v12
+; GFX11-NEXT: v_perm_b32 v15, s20, s80, v12
+; GFX11-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v6, v8, 16, v7
+; GFX11-NEXT: v_perm_b32 v7, s36, s88, v12
+; GFX11-NEXT: v_perm_b32 v17, s64, s74, v12
+; GFX11-NEXT: v_perm_b32 v18, s22, s66, v12
+; GFX11-NEXT: v_perm_b32 v19, s23, s55, v12
+; GFX11-NEXT: v_perm_b32 v4, s52, s51, v12
+; GFX11-NEXT: v_perm_b32 v8, s27, s35, v12
+; GFX11-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-NEXT: v_perm_b32 v9, s34, vcc_hi, v12
+; GFX11-NEXT: v_perm_b32 v10, s28, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 6
+; GFX11-NEXT: v_lshl_or_b32 v1, v14, 16, v15
+; GFX11-NEXT: v_lshl_or_b32 v3, v17, 16, v18
+; GFX11-NEXT: v_lshl_or_b32 v4, v4, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-NEXT: v_perm_b32 v9, s0, s76, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 5
+; GFX11-NEXT: v_readlane_b32 s1, v25, 4
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:32
+; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-NEXT: v_lshl_or_b32 v1, v9, 16, v10
+; GFX11-NEXT: v_perm_b32 v2, s29, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 3
; GFX11-NEXT: v_readlane_b32 s30, v24, 7
; GFX11-NEXT: v_readlane_b32 s31, v24, 8
+; GFX11-NEXT: v_readlane_b32 s104, v24, 6
; GFX11-NEXT: v_readlane_b32 s103, v24, 5
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_perm_b32 v18, s84, s83, v1
-; GFX11-NEXT: v_perm_b32 v3, s0, s104, v1
-; GFX11-NEXT: v_perm_b32 v4, s1, s102, v1
-; GFX11-NEXT: v_perm_b32 v5, s100, s94, v1
-; GFX11-NEXT: v_perm_b32 v19, s81, s80, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v6, s2, s101, v1
-; GFX11-NEXT: v_perm_b32 v7, s3, s99, v1
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX11-NEXT: v_perm_b32 v8, s97, s92, v1
-; GFX11-NEXT: v_or_b32_e32 v3, v4, v18
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v19
-; GFX11-NEXT: v_perm_b32 v11, s86, s90, v1
-; GFX11-NEXT: v_perm_b32 v20, s71, s70, v1
-; GFX11-NEXT: v_perm_b32 v21, s67, s66, v1
-; GFX11-NEXT: v_or_b32_e32 v4, v6, v4
-; GFX11-NEXT: v_or_b32_e32 v5, v7, v5
-; GFX11-NEXT: v_perm_b32 v9, s16, s98, v1
-; GFX11-NEXT: v_perm_b32 v10, s17, s96, v1
-; GFX11-NEXT: v_perm_b32 v12, s18, s87, v1
-; GFX11-NEXT: v_perm_b32 v13, s19, s85, v1
-; GFX11-NEXT: v_perm_b32 v22, s64, s55, v1
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v20
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v11
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v21
-; GFX11-NEXT: v_perm_b32 v14, s82, s88, v1
-; GFX11-NEXT: v_perm_b32 v17, s21, s65, v1
-; GFX11-NEXT: v_or_b32_e32 v2, v9, v2
-; GFX11-NEXT: v_or_b32_e32 v3, v10, v3
-; GFX11-NEXT: v_or_b32_e32 v4, v12, v4
-; GFX11-NEXT: v_or_b32_e32 v5, v13, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v22
-; GFX11-NEXT: v_perm_b32 v15, s69, s78, v1
-; GFX11-NEXT: v_perm_b32 v16, s20, s68, v1
-; GFX11-NEXT: v_perm_b32 v6, s53, s52, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v14
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:16
-; GFX11-NEXT: v_or_b32_e32 v3, v17, v8
-; GFX11-NEXT: v_perm_b32 v8, s48, s39, v1
-; GFX11-NEXT: v_perm_b32 v9, s22, s54, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v15
-; GFX11-NEXT: v_or_b32_e32 v2, v16, v7
-; GFX11-NEXT: v_perm_b32 v5, s50, s72, v1
-; GFX11-NEXT: v_perm_b32 v7, s23, s51, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v11, s25, s38, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_readlane_b32 s0, v25, 6
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-NEXT: v_or_b32_e32 v5, v7, v6
-; GFX11-NEXT: v_or_b32_e32 v7, v11, v8
-; GFX11-NEXT: v_perm_b32 v11, s0, s74, v1
-; GFX11-NEXT: v_readlane_b32 s0, v25, 3
-; GFX11-NEXT: v_readlane_b32 s1, v25, 4
-; GFX11-NEXT: v_perm_b32 v9, s24, s49, v1
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:32
-; GFX11-NEXT: v_perm_b32 v12, s37, s76, v1
-; GFX11-NEXT: v_perm_b32 v8, s26, s36, v1
-; GFX11-NEXT: v_perm_b32 v2, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v25, 7
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v10
-; GFX11-NEXT: v_perm_b32 v10, s34, vcc_hi, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
-; GFX11-NEXT: v_perm_b32 v4, s28, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v25, 5
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT: v_perm_b32 v9, s27, s35, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX11-NEXT: v_perm_b32 v10, s29, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v25, 1
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT: v_readlane_b32 s1, v26, 31
-; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
-; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
-; GFX11-NEXT: v_perm_b32 v12, s0, s62, v1
+; GFX11-NEXT: v_perm_b32 v3, s1, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v25, 2
-; GFX11-NEXT: v_readlane_b32 s104, v24, 6
-; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:48
+; GFX11-NEXT: v_readlane_b32 s1, v26, 31
; GFX11-NEXT: v_readlane_b32 s102, v24, 4
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
-; GFX11-NEXT: v_perm_b32 v4, s40, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 30
; GFX11-NEXT: v_readlane_b32 s101, v24, 3
+; GFX11-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX11-NEXT: v_perm_b32 v4, s40, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 1
; GFX11-NEXT: v_readlane_b32 s100, v24, 2
; GFX11-NEXT: v_readlane_b32 s99, v24, 1
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v25, 0
-; GFX11-NEXT: v_readlane_b32 s1, v26, 26
; GFX11-NEXT: v_readlane_b32 s98, v24, 0
; GFX11-NEXT: v_readlane_b32 s97, v23, 31
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v10
-; GFX11-NEXT: v_perm_b32 v5, s41, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 28
+; GFX11-NEXT: v_perm_b32 v5, s0, s62, v12
+; GFX11-NEXT: v_readlane_b32 s0, v25, 0
; GFX11-NEXT: v_readlane_b32 s96, v23, 30
; GFX11-NEXT: v_readlane_b32 s87, v23, 29
; GFX11-NEXT: v_readlane_b32 s86, v23, 28
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v7
-; GFX11-NEXT: v_perm_b32 v11, s0, s60, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 25
+; GFX11-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX11-NEXT: v_perm_b32 v6, s41, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 30
; GFX11-NEXT: v_readlane_b32 s85, v23, 27
; GFX11-NEXT: v_readlane_b32 s84, v23, 26
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:64
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v11
-; GFX11-NEXT: v_perm_b32 v6, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 29
-; GFX11-NEXT: v_readlane_b32 s1, v26, 21
; GFX11-NEXT: v_readlane_b32 s83, v23, 25
; GFX11-NEXT: v_readlane_b32 s82, v23, 24
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v6
-; GFX11-NEXT: v_perm_b32 v8, s14, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 27
+; GFX11-NEXT: v_perm_b32 v7, s1, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 29
+; GFX11-NEXT: v_readlane_b32 s1, v26, 26
; GFX11-NEXT: v_readlane_b32 s81, v23, 23
; GFX11-NEXT: v_readlane_b32 s80, v23, 22
+; GFX11-NEXT: v_lshl_or_b32 v4, v7, 16, v6
+; GFX11-NEXT: v_perm_b32 v8, s14, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 28
; GFX11-NEXT: v_readlane_b32 s71, v23, 21
-; GFX11-NEXT: v_or_b32_e32 v6, v8, v9
-; GFX11-NEXT: v_perm_b32 v10, s15, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 23
; GFX11-NEXT: v_readlane_b32 s70, v23, 20
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:64
; GFX11-NEXT: v_readlane_b32 s69, v23, 19
+; GFX11-NEXT: v_perm_b32 v9, s0, s60, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 27
; GFX11-NEXT: v_readlane_b32 s68, v23, 18
-; GFX11-NEXT: v_or_b32_e32 v7, v10, v11
-; GFX11-NEXT: v_perm_b32 v12, s0, s58, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 24
; GFX11-NEXT: v_readlane_b32 s67, v23, 17
; GFX11-NEXT: v_readlane_b32 s66, v23, 16
+; GFX11-NEXT: v_lshl_or_b32 v5, v9, 16, v8
+; GFX11-NEXT: v_perm_b32 v10, s15, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 25
; GFX11-NEXT: v_readlane_b32 s65, v23, 15
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v12
-; GFX11-NEXT: v_perm_b32 v8, s12, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 20
; GFX11-NEXT: v_readlane_b32 s64, v23, 14
; GFX11-NEXT: v_readlane_b32 s55, v23, 13
; GFX11-NEXT: v_readlane_b32 s54, v23, 12
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 22
-; GFX11-NEXT: v_readlane_b32 s1, v26, 16
+; GFX11-NEXT: v_perm_b32 v11, s1, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 24
+; GFX11-NEXT: v_readlane_b32 s1, v26, 21
; GFX11-NEXT: v_readlane_b32 s53, v23, 11
; GFX11-NEXT: v_readlane_b32 s52, v23, 10
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v10
-; GFX11-NEXT: v_perm_b32 v9, s13, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 18
+; GFX11-NEXT: v_lshl_or_b32 v6, v11, 16, v10
+; GFX11-NEXT: v_perm_b32 v7, s12, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 23
; GFX11-NEXT: v_readlane_b32 s51, v23, 9
; GFX11-NEXT: v_readlane_b32 s50, v23, 8
; GFX11-NEXT: v_readlane_b32 s49, v23, 7
-; GFX11-NEXT: v_or_b32_e32 v9, v9, v3
-; GFX11-NEXT: v_perm_b32 v11, s0, s56, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 15
; GFX11-NEXT: v_readlane_b32 s48, v23, 6
+; GFX11-NEXT: v_perm_b32 v8, s0, s58, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 22
; GFX11-NEXT: v_readlane_b32 s39, v23, 5
; GFX11-NEXT: v_readlane_b32 s38, v23, 4
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v11
-; GFX11-NEXT: v_perm_b32 v2, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 19
-; GFX11-NEXT: v_readlane_b32 s1, v26, 11
; GFX11-NEXT: v_readlane_b32 s37, v23, 3
+; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-NEXT: v_perm_b32 v9, s13, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 20
; GFX11-NEXT: v_readlane_b32 s36, v23, 2
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX11-NEXT: v_perm_b32 v4, s10, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 17
; GFX11-NEXT: v_readlane_b32 s35, v23, 1
; GFX11-NEXT: v_readlane_b32 s34, v23, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v5
-; GFX11-NEXT: v_perm_b32 v10, s11, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 13
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, s1, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 19
+; GFX11-NEXT: v_readlane_b32 s1, v26, 16
+; GFX11-NEXT: v_lshl_or_b32 v8, v1, 16, v9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v2, s10, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 18
+; GFX11-NEXT: v_perm_b32 v3, s0, s56, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 17
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v3, v10, v11
-; GFX11-NEXT: v_perm_b32 v12, s0, s46, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-NEXT: v_perm_b32 v4, s11, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 15
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v10, s1, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 14
+; GFX11-NEXT: v_readlane_b32 s1, v26, 11
+; GFX11-NEXT: v_lshl_or_b32 v2, v10, 16, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v11, s8, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 13
+; GFX11-NEXT: v_perm_b32 v3, s0, s46, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 12
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v12
-; GFX11-NEXT: v_perm_b32 v4, s8, s0, v1
+; GFX11-NEXT: v_lshl_or_b32 v3, v3, 16, v11
+; GFX11-NEXT: v_perm_b32 v4, s9, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 10
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v4, v4, v5
-; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v9, s1, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 9
; GFX11-NEXT: v_readlane_b32 s1, v26, 6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v5, s9, s0, v1
+; GFX11-NEXT: v_lshl_or_b32 v4, v9, 16, v4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v10, s6, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 8
+; GFX11-NEXT: v_perm_b32 v9, s0, s44, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 7
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v10
-; GFX11-NEXT: v_perm_b32 v11, s0, s44, v1
+; GFX11-NEXT: v_lshl_or_b32 v9, v9, 16, v10
+; GFX11-NEXT: v_perm_b32 v11, s7, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v10, s1, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 9
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v13, s1, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 4
; GFX11-NEXT: v_readlane_b32 s1, v26, 1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v10
-; GFX11-NEXT: v_perm_b32 v12, s6, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v10, v12, v11
-; GFX11-NEXT: v_perm_b32 v14, s7, s0, v1
+; GFX11-NEXT: v_lshl_or_b32 v10, v13, 16, v11
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v11, s4, s0, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 3
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v11, v14, v13
-; GFX11-NEXT: v_perm_b32 v12, s0, s42, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT: v_perm_b32 v13, s4, s0, v1
-; GFX11-NEXT: v_readlane_b32 s0, v26, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX11-NEXT: v_perm_b32 v13, s1, s0, v1
+; GFX11-NEXT: v_perm_b32 v13, s0, s42, v12
; GFX11-NEXT: v_readlane_b32 s0, v26, 2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_perm_b32 v1, s5, s0, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v13, v1, v13
+; GFX11-NEXT: v_lshl_or_b32 v11, v13, 16, v11
+; GFX11-NEXT: v_perm_b32 v13, s5, s0, v12
+; GFX11-NEXT: v_readlane_b32 s0, v26, 0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v12, s1, s0, v12
+; GFX11-NEXT: v_lshl_or_b32 v12, v12, 16, v13
; GFX11-NEXT: s_clause 0x2
-; GFX11-NEXT: scratch_store_b128 v0, v[6:9], off offset:80
-; GFX11-NEXT: scratch_store_b128 v0, v[2:5], off offset:96
-; GFX11-NEXT: scratch_store_b128 v0, v[10:13], off offset:112
+; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:80
+; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:96
+; GFX11-NEXT: scratch_store_b128 v0, v[9:12], off offset:112
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Reload
; GFX11-NEXT: scratch_load_b32 v23, off, s32
@@ -81248,51 +80780,51 @@ define inreg <128 x i8> @bitcast_v16i64_to_v128i8_scalar(<16 x i64> inreg %a, i3
; GFX11-NEXT: ; implicit-def: $sgpr103
; GFX11-NEXT: ; implicit-def: $sgpr30
; GFX11-NEXT: ; implicit-def: $sgpr102
-; GFX11-NEXT: ; implicit-def: $sgpr84
+; GFX11-NEXT: ; implicit-def: $sgpr85
; GFX11-NEXT: ; implicit-def: $sgpr83
; GFX11-NEXT: ; implicit-def: $sgpr101
; GFX11-NEXT: ; implicit-def: $sgpr100
; GFX11-NEXT: ; implicit-def: $sgpr94
; GFX11-NEXT: ; implicit-def: $sgpr99
+; GFX11-NEXT: ; implicit-def: $sgpr82
; GFX11-NEXT: ; implicit-def: $sgpr81
-; GFX11-NEXT: ; implicit-def: $sgpr80
; GFX11-NEXT: ; implicit-def: $sgpr98
; GFX11-NEXT: ; implicit-def: $sgpr97
; GFX11-NEXT: ; implicit-def: $sgpr92
; GFX11-NEXT: ; implicit-def: $sgpr96
-; GFX11-NEXT: ; implicit-def: $sgpr71
-; GFX11-NEXT: ; implicit-def: $sgpr70
+; GFX11-NEXT: ; implicit-def: $sgpr69
+; GFX11-NEXT: ; implicit-def: $sgpr68
; GFX11-NEXT: ; implicit-def: $sgpr87
; GFX11-NEXT: ; implicit-def: $sgpr86
; GFX11-NEXT: ; implicit-def: $sgpr90
-; GFX11-NEXT: ; implicit-def: $sgpr85
+; GFX11-NEXT: ; implicit-def: $sgpr84
; GFX11-NEXT: ; implicit-def: $sgpr67
-; GFX11-NEXT: ; implicit-def: $sgpr66
-; GFX11-NEXT: ; implicit-def: $sgpr68
-; GFX11-NEXT: ; implicit-def: $sgpr82
-; GFX11-NEXT: ; implicit-def: $sgpr88
; GFX11-NEXT: ; implicit-def: $sgpr65
-; GFX11-NEXT: ; implicit-def: $sgpr64
-; GFX11-NEXT: ; implicit-def: $sgpr55
-; GFX11-NEXT: ; implicit-def: $sgpr54
-; GFX11-NEXT: ; implicit-def: $sgpr69
+; GFX11-NEXT: ; implicit-def: $sgpr80
+; GFX11-NEXT: ; implicit-def: $sgpr71
; GFX11-NEXT: ; implicit-def: $sgpr78
-; GFX11-NEXT: ; implicit-def: $sgpr51
+; GFX11-NEXT: ; implicit-def: $sgpr70
+; GFX11-NEXT: ; implicit-def: $sgpr54
; GFX11-NEXT: ; implicit-def: $sgpr53
+; GFX11-NEXT: ; implicit-def: $sgpr66
+; GFX11-NEXT: ; implicit-def: $sgpr64
+; GFX11-NEXT: ; implicit-def: $sgpr74
+; GFX11-NEXT: ; implicit-def: $sgpr55
; GFX11-NEXT: ; implicit-def: $sgpr52
-; GFX11-NEXT: ; implicit-def: $sgpr49
+; GFX11-NEXT: ; implicit-def: $sgpr51
; GFX11-NEXT: ; implicit-def: $sgpr50
+; GFX11-NEXT: ; implicit-def: $sgpr49
; GFX11-NEXT: ; implicit-def: $sgpr72
-; GFX11-NEXT: ; implicit-def: $sgpr38
; GFX11-NEXT: ; implicit-def: $sgpr48
; GFX11-NEXT: ; implicit-def: $sgpr39
-; GFX11-NEXT: ; implicit-def: $sgpr36
+; GFX11-NEXT: ; implicit-def: $sgpr38
; GFX11-NEXT: ; implicit-def: $sgpr37
+; GFX11-NEXT: ; implicit-def: $sgpr36
; GFX11-NEXT: ; implicit-def: $sgpr35
; GFX11-NEXT: ; implicit-def: $sgpr34
; GFX11-NEXT: ; implicit-def: $vcc_hi
+; GFX11-NEXT: ; implicit-def: $sgpr88
; GFX11-NEXT: ; implicit-def: $sgpr76
-; GFX11-NEXT: ; implicit-def: $sgpr74
; GFX11-NEXT: ; implicit-def: $sgpr62
; GFX11-NEXT: ; implicit-def: $sgpr60
; GFX11-NEXT: ; implicit-def: $sgpr58
@@ -89349,99 +88881,99 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:324
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:320
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:316
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:312
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:308
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:304
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:296
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:288
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:276
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:272
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:268
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:264
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:260
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:256
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:252
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:236
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:228
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:216
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:212
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:200
+; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:200
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:196
-; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:192
+; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:192
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:188
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:184
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:180
@@ -89450,371 +88982,315 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:168
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:164
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:160
-; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:156
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:156
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:152
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:148
-; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:144
-; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:140
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:144
+; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:140
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:136
-; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:132
-; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:128
-; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:124
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:132
+; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:128
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:124
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:120
-; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:116
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:108
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:108
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:100
-; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:92
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:76
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:64
-; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:48
-; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:12
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(41)
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(41)
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(39)
+; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(39)
+; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(37)
+; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(37)
+; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(35)
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(35)
+; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(33)
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(33)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(32)
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB59_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
-; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
-; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
-; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
-; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
-; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v45, v26
+; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_perm_b32 v12, v42, v41, s4
+; GFX9-NEXT: v_perm_b32 v13, v40, v54, s4
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX9-NEXT: v_perm_b32 v13, v55, v53, s4
+; GFX9-NEXT: v_perm_b32 v14, v52, v50, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_perm_b32 v14, v51, v49, s4
+; GFX9-NEXT: v_perm_b32 v15, v48, v38, s4
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX9-NEXT: v_perm_b32 v15, v39, v37, s4
+; GFX9-NEXT: v_perm_b32 v16, v35, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; GFX9-NEXT: v_perm_b32 v16, v36, v34, s4
+; GFX9-NEXT: v_perm_b32 v17, v32, v17, s4
+; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX9-NEXT: v_perm_b32 v17, v33, v63, s4
+; GFX9-NEXT: v_perm_b32 v18, v61, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: v_perm_b32 v18, v62, v60, s4
+; GFX9-NEXT: v_perm_b32 v19, v58, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX9-NEXT: v_perm_b32 v19, v59, v57, s4
+; GFX9-NEXT: v_perm_b32 v20, v47, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; GFX9-NEXT: v_perm_b32 v20, v56, v46, s4
+; GFX9-NEXT: v_perm_b32 v21, v44, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX9-NEXT: v_perm_b32 v21, v45, v43, s4
+; GFX9-NEXT: v_perm_b32 v22, v31, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; GFX9-NEXT: v_perm_b32 v22, v30, v29, s4
+; GFX9-NEXT: v_perm_b32 v23, v28, v23, s4
+; GFX9-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX9-NEXT: v_perm_b32 v23, v27, v26, s4
+; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
+; GFX9-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: v_mov_b32_e32 v44, v45
+; GFX9-NEXT: v_mov_b32_e32 v54, v53
+; GFX9-NEXT: v_mov_b32_e32 v40, v55
+; GFX9-NEXT: v_mov_b32_e32 v50, v49
+; GFX9-NEXT: v_mov_b32_e32 v52, v51
+; GFX9-NEXT: v_mov_b32_e32 v38, v37
+; GFX9-NEXT: v_mov_b32_e32 v48, v39
+; GFX9-NEXT: v_mov_b32_e32 v35, v34
+; GFX9-NEXT: v_mov_b32_e32 v32, v63
+; GFX9-NEXT: v_mov_b32_e32 v61, v60
+; GFX9-NEXT: v_mov_b32_e32 v58, v57
; GFX9-NEXT: v_mov_b32_e32 v47, v46
-; GFX9-NEXT: v_mov_b32_e32 v57, v56
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
+; GFX9-NEXT: v_perm_b32 v43, v45, v43, s4
+; GFX9-NEXT: v_lshl_or_b32 v31, v43, 16, v31
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB59_3
; GFX9-NEXT: .LBB59_2:
-; GFX9-NEXT: v_mov_b32_e32 v57, v56
+; GFX9-NEXT: v_mov_b32_e32 v40, v55
+; GFX9-NEXT: v_mov_b32_e32 v54, v53
+; GFX9-NEXT: v_mov_b32_e32 v52, v51
+; GFX9-NEXT: v_mov_b32_e32 v50, v49
+; GFX9-NEXT: v_mov_b32_e32 v48, v39
+; GFX9-NEXT: v_mov_b32_e32 v38, v37
+; GFX9-NEXT: v_mov_b32_e32 v35, v34
+; GFX9-NEXT: v_mov_b32_e32 v32, v63
+; GFX9-NEXT: v_mov_b32_e32 v61, v60
+; GFX9-NEXT: v_mov_b32_e32 v58, v57
; GFX9-NEXT: v_mov_b32_e32 v47, v46
-; GFX9-NEXT: v_mov_b32_e32 v45, v26
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
+; GFX9-NEXT: v_mov_b32_e32 v44, v45
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: .LBB59_3: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v43, v44
-; GFX9-NEXT: v_mov_b32_e32 v44, v45
-; GFX9-NEXT: v_mov_b32_e32 v45, v47
-; GFX9-NEXT: v_mov_b32_e32 v46, v57
-; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v43, v44
+; GFX9-NEXT: v_mov_b32_e32 v44, v47
+; GFX9-NEXT: v_mov_b32_e32 v47, v32
; GFX9-NEXT: s_cbranch_vccnz .LBB59_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -89915,250 +89391,258 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v10
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v10, v10, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_add_u32_e32 v16, 3, v32
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; GFX9-NEXT: s_add_i32 s6, s6, 3
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_add_u32_e32 v14, 3, v48
-; GFX9-NEXT: v_perm_b32 v14, v14, v39, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v15, 3, v36
-; GFX9-NEXT: v_perm_b32 v15, v15, v35, s5
-; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s5
-; GFX9-NEXT: v_add_u32_e32 v17, 3, v60
-; GFX9-NEXT: s_waitcnt vmcnt(16)
-; GFX9-NEXT: v_perm_b32 v17, v17, v18, s5
-; GFX9-NEXT: v_add_u32_e32 v18, 3, v57
-; GFX9-NEXT: s_waitcnt vmcnt(15)
-; GFX9-NEXT: v_perm_b32 v18, v18, v19, s5
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(15)
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(20)
; GFX9-NEXT: v_perm_b32 v11, s6, v12, v11
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_sdwa v17, v17, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_sdwa v18, v18, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s5
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v12, 3, v54
-; GFX9-NEXT: v_add_u32_e32 v13, 3, v52
-; GFX9-NEXT: v_perm_b32 v12, v12, v53, s5
-; GFX9-NEXT: v_perm_b32 v13, v13, v51, s5
+; GFX9-NEXT: v_add_u32_e32 v12, 3, v34
+; GFX9-NEXT: v_perm_b32 v12, v12, v41, s5
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v12
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
+; GFX9-NEXT: v_perm_b32 v13, v13, v14, s5
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v13, v13, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v12, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v13, 3, v50
-; GFX9-NEXT: v_perm_b32 v13, v13, v49, s5
+; GFX9-NEXT: v_add_u32_e32 v13, 3, v40
+; GFX9-NEXT: v_perm_b32 v13, v13, v54, s5
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
+; GFX9-NEXT: v_perm_b32 v14, v14, v15, s5
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v14, 3, v38
-; GFX9-NEXT: v_perm_b32 v14, v14, v37, s5
+; GFX9-NEXT: v_add_u32_e32 v14, 3, v52
+; GFX9-NEXT: v_perm_b32 v14, v14, v50, s5
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v14
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s5
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v15, 3, v34
-; GFX9-NEXT: v_perm_b32 v15, v15, v33, s5
+; GFX9-NEXT: v_add_u32_e32 v15, 3, v48
+; GFX9-NEXT: v_perm_b32 v15, v15, v38, s5
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v15
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v16, 3, v16
+; GFX9-NEXT: v_perm_b32 v16, v16, v17, s5
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v16, 3, v62
-; GFX9-NEXT: v_perm_b32 v16, v16, v61, s5
+; GFX9-NEXT: v_add_u32_e32 v16, 3, v36
+; GFX9-NEXT: v_perm_b32 v16, v16, v35, s5
; GFX9-NEXT: v_add_u32_e32 v16, 0x300, v16
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s5
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v17, v17, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v16, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v17, 3, v41
-; GFX9-NEXT: v_perm_b32 v17, v17, v40, s5
+; GFX9-NEXT: v_add_u32_e32 v17, 3, v33
+; GFX9-NEXT: v_perm_b32 v17, v17, v47, s5
; GFX9-NEXT: v_add_u32_e32 v17, 0x300, v17
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_add_u32_e32 v18, 3, v18
+; GFX9-NEXT: v_perm_b32 v18, v18, v19, s5
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v18, v18, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v18, 3, v42
-; GFX9-NEXT: v_perm_b32 v18, v18, v47, s5
+; GFX9-NEXT: v_add_u32_e32 v18, 3, v62
+; GFX9-NEXT: v_perm_b32 v18, v18, v61, s5
; GFX9-NEXT: v_add_u32_e32 v18, 0x300, v18
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
+; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v19, v19, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v18, v18, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v19, 3, v46
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_e32 v19, 3, v59
+; GFX9-NEXT: v_perm_b32 v19, v19, v58, s5
; GFX9-NEXT: v_add_u32_e32 v19, 0x300, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v20, 3, v20
; GFX9-NEXT: v_perm_b32 v20, v20, v21, s5
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v20, v20, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v19, v19, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v20, 3, v45
+; GFX9-NEXT: v_add_u32_e32 v20, 3, v56
; GFX9-NEXT: v_perm_b32 v20, v20, v44, s5
; GFX9-NEXT: v_add_u32_e32 v20, 0x300, v20
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v21, 3, v21
; GFX9-NEXT: v_perm_b32 v21, v21, v22, s5
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v21, v21, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v20, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_add_u32_e32 v21, 3, v43
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v21, v21, v22, s5
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v21, 0x300, v21
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: v_perm_b32 v22, v22, v23, s5
; GFX9-NEXT: v_add_u32_sdwa v22, v22, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v21, v21, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v22, v22, v23, s5
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v22, 0x300, v22
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: v_perm_b32 v23, v23, v24, s5
; GFX9-NEXT: v_add_u32_sdwa v23, v23, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v22, v22, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v23, v24, s5
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v23, 0x300, v23
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v24, 3, v24
; GFX9-NEXT: v_perm_b32 v24, v24, v25, s5
; GFX9-NEXT: v_add_u32_sdwa v24, v24, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v24, 3, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v24, v25, s5
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v24, 0x300, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v25, 3, v25
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s5
; GFX9-NEXT: v_add_u32_sdwa v25, v25, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v24, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v25, 3, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s5
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v25, 0x300, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v26, 3, v26
; GFX9-NEXT: v_perm_b32 v26, v26, v27, s5
; GFX9-NEXT: v_add_u32_sdwa v26, v26, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v26, 3, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v26, v27, s5
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v26, 0x300, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v27, 3, v27
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s5
; GFX9-NEXT: v_add_u32_sdwa v27, v27, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v26, v26, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s5
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v27, 0x300, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v28, 3, v28
; GFX9-NEXT: v_perm_b32 v28, v28, v29, s5
; GFX9-NEXT: v_add_u32_sdwa v28, v28, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v28, 3, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v28, v29, s5
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v28, 0x300, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v29, 3, v29
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s5
; GFX9-NEXT: v_add_u32_sdwa v29, v29, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v28, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v29, 3, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s5
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v29, 0x300, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v30, 3, v30
; GFX9-NEXT: v_perm_b32 v30, v30, v31, s5
; GFX9-NEXT: v_add_u32_sdwa v30, v30, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v30, 3, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v30, v31, s5
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v30, 0x300, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v31, 3, v31
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s5
; GFX9-NEXT: v_add_u32_sdwa v31, v31, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v30, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v31, 3, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s5
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v31, 0x300, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v32, 3, v32
@@ -90188,10 +89672,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v16i64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
@@ -90313,149 +89794,109 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB59_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v163, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v147, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v6, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v132, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v129, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v114, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v101, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v99, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v83, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v14, 16, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v99, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, v23, v24
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v103, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v101, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, v23, v24
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v83, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, v29, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v65, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v40, v41
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v181, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v67, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v66, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v52, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v167, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v165, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v49, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v183, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v34, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v150, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v145, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v21, 16, v20
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v119, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v102, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v96, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v85, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v25, v27, 16, v26
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v70, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v65, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v31, 16, v30
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v39, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v40, 16, v183
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB59_3
; GFX11-TRUE16-NEXT: .LBB59_2: ; %cmp.true
@@ -90750,9 +90191,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v36, v35
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v33, v32
; GFX11-TRUE16-NEXT: .LBB59_3: ; %end
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB59_4:
@@ -90762,10 +90201,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v16i64_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
-; GFX11-FAKE16-NEXT: ; meta instruction
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:308
@@ -90887,149 +90323,109 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB59_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v180, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v164, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v163, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v147, v135, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v6, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v146, v134, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v132, v130, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v129, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v117, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v114, v112, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v101, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v100, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v84, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v83, v71, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v14, 16, v13
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v147, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v100, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v23, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v103, v99, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v101, v97, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v25, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v67, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v49, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v29, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v65, v53, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v31
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v183, 16, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v29, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-FAKE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v31, v183
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v40, v41
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v182, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v181, v177, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v67, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v66, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v167, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v165, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v49, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v183, v37, v33, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v40, v34, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v161, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v150, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v145, v133, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v144, v131, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v21, 16, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v128, v116, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v119, v115, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v103, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v102, v98, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v96, v86, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v85, v82, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v27, 16, v26
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v81, v69, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v70, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v65, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v31, 16, v30
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v48, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v39, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v40, 16, v183
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB59_3
; GFX11-FAKE16-NEXT: .LBB59_2: ; %cmp.true
@@ -91324,9 +90720,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v36, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v33, v32
; GFX11-FAKE16-NEXT: .LBB59_3: ; %end
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB59_4:
@@ -112247,8 +111641,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
@@ -112478,213 +111872,211 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_add_f64 v[7:8], s[12:13], 1.0
; GFX9-NEXT: v_add_f64 v[9:10], s[14:15], 1.0
; GFX9-NEXT: v_add_f64 v[13:14], s[40:41], 1.0
-; GFX9-NEXT: v_add_f64 v[17:18], s[42:43], 1.0
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[11:12]
-; GFX9-NEXT: v_add_f64 v[21:22], s[44:45], 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX9-NEXT: v_add_f64 v[23:24], s[28:29], 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4]
-; GFX9-NEXT: v_add_f64 v[28:29], s[26:27], 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[5:6]
-; GFX9-NEXT: v_add_f64 v[32:33], s[24:25], 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[7:8]
-; GFX9-NEXT: v_add_f64 v[34:35], s[22:23], 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[9:10]
-; GFX9-NEXT: v_add_f64 v[36:37], s[20:21], 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[13:14]
-; GFX9-NEXT: v_add_f64 v[38:39], s[18:19], 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[17:18]
-; GFX9-NEXT: v_add_f64 v[48:49], s[16:17], 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[21:22]
-; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v11
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[23:24]
-; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v22
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[28:29]
-; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v24
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[32:33]
-; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v29
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[34:35]
-; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v28
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[36:37]
-; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v33
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[38:39]
-; GFX9-NEXT: v_lshrrev_b32_e32 v54, 24, v35
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; GFX9-NEXT: v_add_f64 v[15:16], s[42:43], 1.0
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[11:12]
+; GFX9-NEXT: v_add_f64 v[17:18], s[44:45], 1.0
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[48:49]
-; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v35
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[1:2]
+; GFX9-NEXT: v_add_f64 v[19:20], s[28:29], 1.0
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v12
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v12
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v12
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v11
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v2
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v2
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v2
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v1
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v1
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v4
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v4
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v3
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v3
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v6
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v6
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v6
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v5
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v5
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v8
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v8
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v8
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v7
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v7
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v10
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v10
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v10
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v9
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v9
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v13
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v13
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v18
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v18
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v18
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v17
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v17
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v22
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v22
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v21
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v21
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v24
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v24
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v23
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v23
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v29
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v29
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v28
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v33
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v32
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v32
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v34
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 8, v33
-; GFX9-NEXT: v_lshrrev_b32_e32 v30, 8, v35
-; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v34
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v37
-; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v37
-; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v37
-; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v36
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v36
-; GFX9-NEXT: v_lshrrev_b32_e32 v42, 24, v39
-; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v39
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v39
-; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v38
-; GFX9-NEXT: v_lshrrev_b32_e32 v40, 8, v38
-; GFX9-NEXT: v_lshrrev_b32_e32 v61, 24, v49
-; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v49
-; GFX9-NEXT: v_lshrrev_b32_e32 v20, 8, v49
-; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v48
-; GFX9-NEXT: v_lshrrev_b32_e32 v60, 8, v48
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[3:4]
+; GFX9-NEXT: v_add_f64 v[21:22], s[26:27], 1.0
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[5:6]
+; GFX9-NEXT: v_add_f64 v[23:24], s[24:25], 1.0
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[7:8]
+; GFX9-NEXT: v_add_f64 v[25:26], s[22:23], 1.0
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[9:10]
+; GFX9-NEXT: v_add_f64 v[27:28], s[20:21], 1.0
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[13:14]
+; GFX9-NEXT: v_add_f64 v[33:34], s[16:17], 1.0
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[15:16]
+; GFX9-NEXT: v_add_f64 v[29:30], s[18:19], 1.0
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[17:18]
+; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v15
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[19:20]
+; GFX9-NEXT: v_lshrrev_b32_e32 v52, 8, v18
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[21:22]
+; GFX9-NEXT: v_lshrrev_b64 v[43:44], 24, v[29:30]
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[23:24]
+; GFX9-NEXT: v_lshrrev_b32_e32 v36, 8, v20
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[25:26]
+; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v22
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[27:28]
+; GFX9-NEXT: v_lshrrev_b32_e32 v45, 24, v24
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[33:34]
+; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v24
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v12
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v12
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v12
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v11
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v11
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v2
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v2
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v2
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v1
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v3
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v3
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v6
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v6
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v6
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v5
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v5
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v8
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v8
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v8
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v7
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v7
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v10
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v10
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v10
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v9
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v9
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v14
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v14
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v14
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v13
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v13
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v16
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v16
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v16
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v15
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v18
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v18
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v17
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v17
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v20
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v20
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v19
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v19
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 24, v22
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v22
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v21
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v21
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v23
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v23
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v25
+; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v24
+; GFX9-NEXT: v_lshrrev_b32_e32 v47, 24, v26
+; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v26
+; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v26
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v25
+; GFX9-NEXT: v_lshrrev_b32_e32 v39, 24, v28
+; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v28
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v28
+; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v27
+; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v27
+; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v30
+; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v30
+; GFX9-NEXT: v_lshrrev_b32_e32 v38, 8, v30
+; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v29
+; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v29
+; GFX9-NEXT: v_lshrrev_b32_e32 v41, 24, v34
+; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v34
+; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v34
+; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v33
+; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v33
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
; GFX9-NEXT: s_branch .LBB73_5
; GFX9-NEXT: .LBB73_3:
; GFX9-NEXT: ; implicit-def: $sgpr46
@@ -112835,247 +112227,196 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: s_branch .LBB73_2
; GFX9-NEXT: .LBB73_4:
-; GFX9-NEXT: v_mov_b32_e32 v15, s66
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s65
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s64
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s54
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s53
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s52
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s51
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s50
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s49
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s48
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s39
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s38
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s99
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s98
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s97
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s96
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s87
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s86
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s85
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s84
+; GFX9-NEXT: v_mov_b32_e32 v49, s36
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s30
+; GFX9-NEXT: v_mov_b32_e32 v32, s48
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s39
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s38
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s99
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s98
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s97
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s96
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s87
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s86
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s85
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s84
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s83
; GFX9-NEXT: v_mov_b32_e32 v11, s4
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s83
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s82
; GFX9-NEXT: v_readlane_b32 s4, v62, 0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s82
-; GFX9-NEXT: v_mov_b32_e32 v51, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 1
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 2
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 3
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 4
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 5
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 6
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 7
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 8
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 9
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 10
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 11
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 12
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 13
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 15
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 16
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s94
; GFX9-NEXT: v_readlane_b32 s4, v62, 17
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 18
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 19
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 20
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 21
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 22
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 23
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 24
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 25
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 26
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 27
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 28
-; GFX9-NEXT: v_mov_b32_e32 v55, s4
+; GFX9-NEXT: v_mov_b32_e32 v52, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 29
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 30
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 31
-; GFX9-NEXT: v_mov_b32_e32 v58, s4
-; GFX9-NEXT: v_mov_b32_e32 v57, s34
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v57, s30
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v57, s94
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v57, s92
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v52, s36
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v57, s90
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v57, v51
-; GFX9-NEXT: v_mov_b32_e32 v51, s88
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s78
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s76
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s74
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s72
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s62
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s60
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s58
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s56
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v36, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 32
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 33
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 34
-; GFX9-NEXT: v_mov_b32_e32 v50, s4
+; GFX9-NEXT: v_mov_b32_e32 v58, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 35
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v45, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 36
-; GFX9-NEXT: v_mov_b32_e32 v31, s4
+; GFX9-NEXT: v_mov_b32_e32 v46, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 37
-; GFX9-NEXT: v_mov_b32_e32 v16, s4
+; GFX9-NEXT: v_mov_b32_e32 v37, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 38
-; GFX9-NEXT: v_mov_b32_e32 v54, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 39
; GFX9-NEXT: v_mov_b32_e32 v47, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 39
+; GFX9-NEXT: v_mov_b32_e32 v31, s67
+; GFX9-NEXT: v_mov_b32_e32 v56, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 40
-; GFX9-NEXT: v_mov_b32_e32 v30, s4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v31, s66
+; GFX9-NEXT: v_mov_b32_e32 v61, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 41
-; GFX9-NEXT: v_mov_b32_e32 v25, s4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v31, s65
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 42
-; GFX9-NEXT: v_mov_b32_e32 v41, s4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v31, s64
+; GFX9-NEXT: v_mov_b32_e32 v48, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 43
-; GFX9-NEXT: v_mov_b32_e32 v44, s4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v31, s55
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s92
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v32, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 44
-; GFX9-NEXT: v_mov_b32_e32 v42, s4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v31, s54
+; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 45
-; GFX9-NEXT: v_mov_b32_e32 v26, s4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v31, s53
+; GFX9-NEXT: v_mov_b32_e32 v59, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 46
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v31, s52
+; GFX9-NEXT: v_mov_b32_e32 v38, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 47
-; GFX9-NEXT: v_mov_b32_e32 v61, s4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v31, s51
+; GFX9-NEXT: v_mov_b32_e32 v41, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 48
-; GFX9-NEXT: v_mov_b32_e32 v51, s46
-; GFX9-NEXT: v_mov_b32_e32 v43, s4
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v31, s50
+; GFX9-NEXT: v_mov_b32_e32 v60, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 49
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v12, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s7
@@ -113089,56 +112430,103 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v10, s15
; GFX9-NEXT: v_mov_b32_e32 v13, s40
; GFX9-NEXT: v_mov_b32_e32 v14, s41
-; GFX9-NEXT: v_mov_b32_e32 v17, s42
-; GFX9-NEXT: v_mov_b32_e32 v18, s43
-; GFX9-NEXT: v_mov_b32_e32 v21, s44
-; GFX9-NEXT: v_mov_b32_e32 v22, s45
-; GFX9-NEXT: v_mov_b32_e32 v23, s28
-; GFX9-NEXT: v_mov_b32_e32 v24, s29
-; GFX9-NEXT: v_mov_b32_e32 v28, s26
-; GFX9-NEXT: v_mov_b32_e32 v29, s27
-; GFX9-NEXT: v_mov_b32_e32 v32, s24
-; GFX9-NEXT: v_mov_b32_e32 v33, s25
-; GFX9-NEXT: v_mov_b32_e32 v34, s22
-; GFX9-NEXT: v_mov_b32_e32 v35, s23
-; GFX9-NEXT: v_mov_b32_e32 v36, s20
-; GFX9-NEXT: v_mov_b32_e32 v37, s21
-; GFX9-NEXT: v_mov_b32_e32 v38, s18
-; GFX9-NEXT: v_mov_b32_e32 v39, s19
-; GFX9-NEXT: v_mov_b32_e32 v48, s16
-; GFX9-NEXT: v_mov_b32_e32 v49, s17
-; GFX9-NEXT: v_mov_b32_e32 v59, s81
-; GFX9-NEXT: v_mov_b32_e32 v60, s80
-; GFX9-NEXT: v_mov_b32_e32 v56, s71
-; GFX9-NEXT: v_mov_b32_e32 v40, s70
-; GFX9-NEXT: v_mov_b32_e32 v46, s69
-; GFX9-NEXT: v_mov_b32_e32 v19, s68
-; GFX9-NEXT: v_mov_b32_e32 v27, s67
-; GFX9-NEXT: v_mov_b32_e32 v20, s4
-; GFX9-NEXT: v_mov_b32_e32 v51, s55
+; GFX9-NEXT: v_mov_b32_e32 v15, s42
+; GFX9-NEXT: v_mov_b32_e32 v16, s43
+; GFX9-NEXT: v_mov_b32_e32 v17, s44
+; GFX9-NEXT: v_mov_b32_e32 v18, s45
+; GFX9-NEXT: v_mov_b32_e32 v19, s28
+; GFX9-NEXT: v_mov_b32_e32 v20, s29
+; GFX9-NEXT: v_mov_b32_e32 v21, s26
+; GFX9-NEXT: v_mov_b32_e32 v22, s27
+; GFX9-NEXT: v_mov_b32_e32 v23, s24
+; GFX9-NEXT: v_mov_b32_e32 v24, s25
+; GFX9-NEXT: v_mov_b32_e32 v25, s22
+; GFX9-NEXT: v_mov_b32_e32 v26, s23
+; GFX9-NEXT: v_mov_b32_e32 v27, s20
+; GFX9-NEXT: v_mov_b32_e32 v28, s21
+; GFX9-NEXT: v_mov_b32_e32 v29, s18
+; GFX9-NEXT: v_mov_b32_e32 v30, s19
+; GFX9-NEXT: v_mov_b32_e32 v33, s16
+; GFX9-NEXT: v_mov_b32_e32 v34, s17
+; GFX9-NEXT: v_mov_b32_e32 v54, s81
+; GFX9-NEXT: v_mov_b32_e32 v57, s80
+; GFX9-NEXT: v_mov_b32_e32 v35, s71
+; GFX9-NEXT: v_mov_b32_e32 v53, s70
+; GFX9-NEXT: v_mov_b32_e32 v55, s69
+; GFX9-NEXT: v_mov_b32_e32 v44, s68
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v42, s4
+; GFX9-NEXT: v_mov_b32_e32 v43, s34
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s90
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s88
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s78
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s76
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s74
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s72
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s62
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s60
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s58
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s56
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s46
+; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v49, s49
; GFX9-NEXT: .LBB73_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v39, v39, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v49, v49, v20, s4
-; GFX9-NEXT: v_perm_b32 v36, v36, v19, s4
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v30, v35, v30, s4
-; GFX9-NEXT: v_perm_b32 v16, v33, v16, s4
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v48, v48, v60, s4
-; GFX9-NEXT: v_perm_b32 v25, v41, v25, s4
-; GFX9-NEXT: v_perm_b32 v37, v37, v44, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX9-NEXT: v_or_b32_e32 v25, v37, v25
-; GFX9-NEXT: v_perm_b32 v26, v26, v42, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX9-NEXT: v_perm_b32 v38, v38, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v26, v39, v26
-; GFX9-NEXT: v_perm_b32 v24, v24, v58, s4
-; GFX9-NEXT: v_perm_b32 v22, v22, v55, s4
+; GFX9-NEXT: v_perm_b32 v28, v28, v32, s4
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v24, v24, v37, s4
+; GFX9-NEXT: v_perm_b32 v29, v29, v53, s4
+; GFX9-NEXT: v_perm_b32 v33, v33, v57, s4
+; GFX9-NEXT: v_perm_b32 v22, v22, v58, s4
+; GFX9-NEXT: v_perm_b32 v18, v18, v52, s4
+; GFX9-NEXT: v_perm_b32 v34, v34, v42, s4
+; GFX9-NEXT: v_perm_b32 v35, v35, v43, s4
+; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v30, v30, v38, s4
+; GFX9-NEXT: v_perm_b32 v27, v27, v44, s4
+; GFX9-NEXT: v_lshl_or_b32 v29, v35, 16, v29
+; GFX9-NEXT: v_perm_b32 v26, v26, v61, s4
+; GFX9-NEXT: v_perm_b32 v20, v20, v36, s4
; GFX9-NEXT: v_readlane_b32 s30, v63, 34
; GFX9-NEXT: v_readlane_b32 s31, v63, 35
; GFX9-NEXT: v_readlane_b32 s99, v63, 33
@@ -113175,282 +112563,250 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: v_readlane_b32 s36, v63, 2
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_perm_b32 v34, v34, v15, s4
+; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(5)
+; GFX9-NEXT: v_perm_b32 v32, v32, v31, s4
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(5)
+; GFX9-NEXT: v_perm_b32 v54, v54, v50, s4
+; GFX9-NEXT: v_lshl_or_b32 v33, v54, 16, v33
; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_perm_b32 v27, v27, v19, s4
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_perm_b32 v45, v59, v52, s4
-; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v38, v55, v42, s4
+; GFX9-NEXT: v_lshl_or_b32 v27, v38, 16, v27
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_perm_b32 v17, v17, v53, s4
+; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v35, v15, v19, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v25, v25, v31, s4
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v25, v32, 16, v25
; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_perm_b32 v56, v56, v59, s4
-; GFX9-NEXT: buffer_load_dword v59, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_perm_b32 v19, v51, v19, s4
-; GFX9-NEXT: v_perm_b32 v32, v32, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v52, v49, v52, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v40, v46, v59, s4
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v20, v28, v15, s4
-; GFX9-NEXT: v_perm_b32 v28, v29, v50, s4
+; GFX9-NEXT: v_perm_b32 v31, v31, v50, s4
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_perm_b32 v15, v15, v49, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v15, v52, 16, v15
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_perm_b32 v23, v23, v50, s4
; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v29, v15, v50, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v23, v23, v15, s4
-; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v23, v31, 16, v23
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_perm_b32 v16, v16, v49, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v33, v15, v50, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v37, v37, v50, s4
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v21, v21, v15, s4
-; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v21, v21, v50, s4
+; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v21, v37, 16, v21
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v51, v50, v57, s4
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_perm_b32 v19, v19, v50, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v19, v51, 16, v19
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_perm_b32 v36, v36, v57, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v36, 16, v17
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v50, v15, v50, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v49, v50, v49, s4
+; GFX9-NEXT: buffer_store_dword v33, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v33, v60, v41, s4
+; GFX9-NEXT: buffer_store_dword v29, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: v_perm_b32 v29, v59, v40, s4
+; GFX9-NEXT: buffer_store_dword v27, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: v_perm_b32 v27, v48, v39, s4
+; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: v_perm_b32 v25, v56, v47, s4
+; GFX9-NEXT: buffer_store_dword v23, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: v_perm_b32 v23, v46, v45, s4
+; GFX9-NEXT: v_lshl_or_b32 v33, v33, 16, v34
+; GFX9-NEXT: v_lshl_or_b32 v29, v29, 16, v30
+; GFX9-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; GFX9-NEXT: v_lshl_or_b32 v25, v25, 16, v26
+; GFX9-NEXT: v_lshl_or_b32 v23, v23, 16, v24
+; GFX9-NEXT: buffer_store_dword v33, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: buffer_store_dword v29, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: buffer_store_dword v27, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: buffer_store_dword v23, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: buffer_store_dword v21, v0, s[0:3], 0 offen offset:40
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v17, v17, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v21, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v21, v21, 16, v22
+; GFX9-NEXT: buffer_store_dword v21, v0, s[0:3], 0 offen offset:44
+; GFX9-NEXT: buffer_store_dword v19, v0, s[0:3], 0 offen offset:48
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v18, v18, v15, s4
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v19, v21, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v19, v19, 16, v20
+; GFX9-NEXT: buffer_store_dword v19, v0, s[0:3], 0 offen offset:52
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:56
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v15, v15, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v51, 16, v45
-; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX9-NEXT: v_or_b32_e32 v48, v48, v51
-; GFX9-NEXT: v_or_b32_e32 v25, v34, v25
-; GFX9-NEXT: buffer_store_dword v48, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v48, v43, v61, s4
-; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: v_perm_b32 v25, v47, v54, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v48
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX9-NEXT: v_or_b32_e32 v48, v49, v48
-; GFX9-NEXT: v_or_b32_e32 v25, v30, v25
-; GFX9-NEXT: buffer_store_dword v48, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v48, 16, v56
-; GFX9-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v40
-; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v35
-; GFX9-NEXT: v_or_b32_e32 v38, v38, v48
-; GFX9-NEXT: v_or_b32_e32 v26, v36, v26
-; GFX9-NEXT: v_or_b32_e32 v25, v32, v25
-; GFX9-NEXT: buffer_store_dword v38, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: buffer_store_dword v25, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v25, v31, v25, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v25
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v19
-; GFX9-NEXT: v_or_b32_e32 v16, v20, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v19, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v28, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v29
-; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v19, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v24, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v33
-; GFX9-NEXT: v_or_b32_e32 v16, v21, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v19, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v50
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v19, v17, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v18
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:60
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:64
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v17, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v18, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v15, v17, v15, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:68
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_perm_b32 v13, v13, v15, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v49, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v15, v14, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v9, v13, s4
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v13
+; GFX9-NEXT: v_lshl_or_b32 v9, v13, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:80
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v13, v10, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:84
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v9, s4
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:88
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v9, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:92
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v5, v7, s4
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v7, v7, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:96
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v7, v6, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:100
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v3, v5, s4
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v5, v6, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:104
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v4, v5, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:108
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v1, v3, s4
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v3, v4, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v2, v57, v2, s4
+; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
; GFX9-NEXT: v_perm_b32 v1, v11, v1, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_perm_b32 v1, v12, v1, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v3, v2, s4
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v1, v12, v1, s4
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -113467,8 +112823,8 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
-; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -113478,88 +112834,92 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: s_or_saveexec_b32 s4, -1
; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Spill
-; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:72
-; GFX11-NEXT: scratch_store_b32 off, v75, s32 offset:76
; GFX11-NEXT: scratch_store_b32 off, v76, s32 offset:80
; GFX11-NEXT: scratch_store_b32 off, v77, s32 offset:84
+; GFX11-NEXT: scratch_store_b32 off, v78, s32 offset:88
+; GFX11-NEXT: scratch_store_b32 off, v79, s32 offset:92
; GFX11-NEXT: s_mov_b32 exec_lo, s4
-; GFX11-NEXT: s_clause 0x11 ; 72-byte Folded Spill
-; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:68
+; GFX11-NEXT: s_clause 0x13 ; 80-byte Folded Spill
+; GFX11-NEXT: scratch_store_b32 off, v40, s32 offset:76
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:64
+; GFX11-NEXT: scratch_store_b32 off, v41, s32 offset:72
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:60
+; GFX11-NEXT: scratch_store_b32 off, v42, s32 offset:68
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:56
+; GFX11-NEXT: scratch_store_b32 off, v43, s32 offset:64
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:52
+; GFX11-NEXT: scratch_store_b32 off, v44, s32 offset:60
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:48
+; GFX11-NEXT: scratch_store_b32 off, v45, s32 offset:56
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:44
+; GFX11-NEXT: scratch_store_b32 off, v46, s32 offset:52
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:40
+; GFX11-NEXT: scratch_store_b32 off, v47, s32 offset:48
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:36
+; GFX11-NEXT: scratch_store_b32 off, v56, s32 offset:44
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:32
+; GFX11-NEXT: scratch_store_b32 off, v57, s32 offset:40
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:28
+; GFX11-NEXT: scratch_store_b32 off, v58, s32 offset:36
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:24
+; GFX11-NEXT: scratch_store_b32 off, v59, s32 offset:32
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:20
+; GFX11-NEXT: scratch_store_b32 off, v60, s32 offset:28
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:16
+; GFX11-NEXT: scratch_store_b32 off, v61, s32 offset:24
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:12
+; GFX11-NEXT: scratch_store_b32 off, v62, s32 offset:20
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:8
+; GFX11-NEXT: scratch_store_b32 off, v63, s32 offset:16
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:4
+; GFX11-NEXT: scratch_store_b32 off, v72, s32 offset:12
; GFX11-NEXT: ; meta instruction
-; GFX11-NEXT: scratch_store_b32 off, v73, s32
-; GFX11-NEXT: v_writelane_b32 v74, s34, 0
-; GFX11-NEXT: v_writelane_b32 v74, s35, 1
-; GFX11-NEXT: v_writelane_b32 v74, s36, 2
-; GFX11-NEXT: v_writelane_b32 v74, s37, 3
-; GFX11-NEXT: v_writelane_b32 v74, s38, 4
-; GFX11-NEXT: v_writelane_b32 v74, s39, 5
-; GFX11-NEXT: v_writelane_b32 v74, s48, 6
-; GFX11-NEXT: v_writelane_b32 v74, s49, 7
-; GFX11-NEXT: v_writelane_b32 v74, s50, 8
-; GFX11-NEXT: v_writelane_b32 v74, s51, 9
-; GFX11-NEXT: v_writelane_b32 v74, s52, 10
-; GFX11-NEXT: v_writelane_b32 v74, s53, 11
-; GFX11-NEXT: v_writelane_b32 v74, s54, 12
-; GFX11-NEXT: v_writelane_b32 v74, s55, 13
-; GFX11-NEXT: v_writelane_b32 v74, s64, 14
-; GFX11-NEXT: v_writelane_b32 v74, s65, 15
-; GFX11-NEXT: v_writelane_b32 v74, s66, 16
-; GFX11-NEXT: v_writelane_b32 v74, s67, 17
-; GFX11-NEXT: v_writelane_b32 v74, s68, 18
-; GFX11-NEXT: v_writelane_b32 v74, s69, 19
-; GFX11-NEXT: v_writelane_b32 v74, s70, 20
-; GFX11-NEXT: v_writelane_b32 v74, s71, 21
-; GFX11-NEXT: v_writelane_b32 v74, s80, 22
-; GFX11-NEXT: v_writelane_b32 v74, s81, 23
-; GFX11-NEXT: v_writelane_b32 v74, s82, 24
-; GFX11-NEXT: v_writelane_b32 v74, s83, 25
-; GFX11-NEXT: v_writelane_b32 v74, s84, 26
-; GFX11-NEXT: v_writelane_b32 v74, s85, 27
-; GFX11-NEXT: v_writelane_b32 v74, s86, 28
-; GFX11-NEXT: v_writelane_b32 v74, s87, 29
-; GFX11-NEXT: v_writelane_b32 v74, s96, 30
-; GFX11-NEXT: v_writelane_b32 v74, s97, 31
-; GFX11-NEXT: v_writelane_b32 v75, s98, 0
-; GFX11-NEXT: v_writelane_b32 v75, s99, 1
-; GFX11-NEXT: v_writelane_b32 v75, s100, 2
-; GFX11-NEXT: v_writelane_b32 v75, s101, 3
-; GFX11-NEXT: v_writelane_b32 v75, s102, 4
-; GFX11-NEXT: v_writelane_b32 v75, s103, 5
-; GFX11-NEXT: v_writelane_b32 v75, s104, 6
-; GFX11-NEXT: v_writelane_b32 v75, s30, 7
-; GFX11-NEXT: v_writelane_b32 v75, s31, 8
+; GFX11-NEXT: scratch_store_b32 off, v73, s32 offset:8
+; GFX11-NEXT: ; meta instruction
+; GFX11-NEXT: scratch_store_b32 off, v74, s32 offset:4
+; GFX11-NEXT: ; meta instruction
+; GFX11-NEXT: scratch_store_b32 off, v75, s32
+; GFX11-NEXT: v_writelane_b32 v76, s34, 0
+; GFX11-NEXT: v_writelane_b32 v76, s35, 1
+; GFX11-NEXT: v_writelane_b32 v76, s36, 2
+; GFX11-NEXT: v_writelane_b32 v76, s37, 3
+; GFX11-NEXT: v_writelane_b32 v76, s38, 4
+; GFX11-NEXT: v_writelane_b32 v76, s39, 5
+; GFX11-NEXT: v_writelane_b32 v76, s48, 6
+; GFX11-NEXT: v_writelane_b32 v76, s49, 7
+; GFX11-NEXT: v_writelane_b32 v76, s50, 8
+; GFX11-NEXT: v_writelane_b32 v76, s51, 9
+; GFX11-NEXT: v_writelane_b32 v76, s52, 10
+; GFX11-NEXT: v_writelane_b32 v76, s53, 11
+; GFX11-NEXT: v_writelane_b32 v76, s54, 12
+; GFX11-NEXT: v_writelane_b32 v76, s55, 13
+; GFX11-NEXT: v_writelane_b32 v76, s64, 14
+; GFX11-NEXT: v_writelane_b32 v76, s65, 15
+; GFX11-NEXT: v_writelane_b32 v76, s66, 16
+; GFX11-NEXT: v_writelane_b32 v76, s67, 17
+; GFX11-NEXT: v_writelane_b32 v76, s68, 18
+; GFX11-NEXT: v_writelane_b32 v76, s69, 19
+; GFX11-NEXT: v_writelane_b32 v76, s70, 20
+; GFX11-NEXT: v_writelane_b32 v76, s71, 21
+; GFX11-NEXT: v_writelane_b32 v76, s80, 22
+; GFX11-NEXT: v_writelane_b32 v76, s81, 23
+; GFX11-NEXT: v_writelane_b32 v76, s82, 24
+; GFX11-NEXT: v_writelane_b32 v76, s83, 25
+; GFX11-NEXT: v_writelane_b32 v76, s84, 26
+; GFX11-NEXT: v_writelane_b32 v76, s85, 27
+; GFX11-NEXT: v_writelane_b32 v76, s86, 28
+; GFX11-NEXT: v_writelane_b32 v76, s87, 29
+; GFX11-NEXT: v_writelane_b32 v76, s96, 30
+; GFX11-NEXT: v_writelane_b32 v76, s97, 31
+; GFX11-NEXT: v_writelane_b32 v77, s98, 0
+; GFX11-NEXT: v_writelane_b32 v77, s99, 1
+; GFX11-NEXT: v_writelane_b32 v77, s100, 2
+; GFX11-NEXT: v_writelane_b32 v77, s101, 3
+; GFX11-NEXT: v_writelane_b32 v77, s102, 4
+; GFX11-NEXT: v_writelane_b32 v77, s103, 5
+; GFX11-NEXT: v_writelane_b32 v77, s104, 6
+; GFX11-NEXT: v_writelane_b32 v77, s30, 7
+; GFX11-NEXT: v_writelane_b32 v77, s31, 8
; GFX11-NEXT: v_readfirstlane_b32 s42, v15
; GFX11-NEXT: v_readfirstlane_b32 s41, v14
; GFX11-NEXT: v_readfirstlane_b32 s40, v13
@@ -113577,272 +112937,272 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX11-NEXT: v_readfirstlane_b32 s12, v1
; GFX11-NEXT: s_cmp_lg_u32 s42, 0
; GFX11-NEXT: s_mov_b32 vcc_lo, 0
-; GFX11-NEXT: ; implicit-def: $vgpr76 : SGPR spill to VGPR lane
-; GFX11-NEXT: ; implicit-def: $vgpr77 : SGPR spill to VGPR lane
+; GFX11-NEXT: ; implicit-def: $vgpr78 : SGPR spill to VGPR lane
+; GFX11-NEXT: ; implicit-def: $vgpr79 : SGPR spill to VGPR lane
; GFX11-NEXT: s_cbranch_scc0 .LBB73_3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s11, 16
; GFX11-NEXT: s_lshr_b32 s48, s41, 24
-; GFX11-NEXT: v_writelane_b32 v76, s42, 0
+; GFX11-NEXT: v_writelane_b32 v78, s42, 0
; GFX11-NEXT: s_lshr_b32 s42, s9, 24
; GFX11-NEXT: s_lshr_b32 s39, s41, 16
; GFX11-NEXT: s_lshr_b32 s38, s41, 8
; GFX11-NEXT: s_lshr_b32 s50, s40, 16
-; GFX11-NEXT: v_writelane_b32 v76, s42, 1
+; GFX11-NEXT: v_writelane_b32 v78, s42, 1
; GFX11-NEXT: s_lshr_b32 s42, s9, 16
; GFX11-NEXT: s_lshr_b32 s49, s40, 8
; GFX11-NEXT: s_lshr_b32 s37, s15, 24
; GFX11-NEXT: s_lshr_b32 s36, s15, 16
-; GFX11-NEXT: v_writelane_b32 v76, s42, 2
+; GFX11-NEXT: v_writelane_b32 v78, s42, 2
; GFX11-NEXT: s_lshr_b32 s42, s9, 8
; GFX11-NEXT: s_lshr_b32 s35, s15, 8
; GFX11-NEXT: s_lshr_b32 s52, s14, 16
; GFX11-NEXT: s_lshr_b32 s51, s14, 8
-; GFX11-NEXT: v_writelane_b32 v76, s42, 3
+; GFX11-NEXT: v_writelane_b32 v78, s42, 3
; GFX11-NEXT: s_lshr_b32 s42, s7, 24
; GFX11-NEXT: s_lshr_b32 s34, s11, 24
; GFX11-NEXT: s_lshr_b32 s104, s11, 8
; GFX11-NEXT: s_lshr_b32 s54, s10, 16
-; GFX11-NEXT: v_writelane_b32 v76, s42, 4
+; GFX11-NEXT: v_writelane_b32 v78, s42, 4
; GFX11-NEXT: s_lshr_b32 s42, s7, 16
; GFX11-NEXT: s_lshr_b32 s53, s10, 8
; GFX11-NEXT: s_lshr_b32 s64, s8, 16
; GFX11-NEXT: s_lshr_b32 s55, s8, 8
-; GFX11-NEXT: v_writelane_b32 v76, s42, 5
+; GFX11-NEXT: v_writelane_b32 v78, s42, 5
; GFX11-NEXT: s_lshr_b32 s42, s7, 8
; GFX11-NEXT: s_lshr_b32 s66, s6, 16
; GFX11-NEXT: s_lshr_b32 s65, s6, 8
; GFX11-NEXT: s_lshr_b32 s68, s4, 16
-; GFX11-NEXT: v_writelane_b32 v76, s42, 6
+; GFX11-NEXT: v_writelane_b32 v78, s42, 6
; GFX11-NEXT: s_lshr_b32 s42, s5, 24
; GFX11-NEXT: s_lshr_b32 s67, s4, 8
; GFX11-NEXT: s_lshr_b32 s70, s12, 16
; GFX11-NEXT: s_lshr_b32 s69, s12, 8
-; GFX11-NEXT: v_writelane_b32 v76, s42, 7
+; GFX11-NEXT: v_writelane_b32 v78, s42, 7
; GFX11-NEXT: s_lshr_b32 s42, s5, 16
; GFX11-NEXT: s_lshr_b32 s80, s28, 16
; GFX11-NEXT: s_lshr_b32 s71, s28, 8
; GFX11-NEXT: s_lshr_b32 s82, s26, 16
-; GFX11-NEXT: v_writelane_b32 v76, s42, 8
+; GFX11-NEXT: v_writelane_b32 v78, s42, 8
; GFX11-NEXT: s_lshr_b32 s42, s5, 8
; GFX11-NEXT: s_lshr_b32 s81, s26, 8
; GFX11-NEXT: s_lshr_b32 s84, s24, 16
; GFX11-NEXT: s_lshr_b32 s83, s24, 8
-; GFX11-NEXT: v_writelane_b32 v76, s42, 9
+; GFX11-NEXT: v_writelane_b32 v78, s42, 9
; GFX11-NEXT: s_lshr_b32 s42, s13, 24
; GFX11-NEXT: s_lshr_b32 s86, s22, 16
; GFX11-NEXT: s_lshr_b32 s85, s22, 8
; GFX11-NEXT: s_lshr_b32 s96, s20, 16
-; GFX11-NEXT: v_writelane_b32 v76, s42, 10
+; GFX11-NEXT: v_writelane_b32 v78, s42, 10
; GFX11-NEXT: s_lshr_b32 s42, s13, 16
; GFX11-NEXT: s_lshr_b32 s87, s20, 8
; GFX11-NEXT: s_lshr_b32 s98, s18, 16
; GFX11-NEXT: s_lshr_b32 s97, s18, 8
-; GFX11-NEXT: v_writelane_b32 v76, s42, 11
+; GFX11-NEXT: v_writelane_b32 v78, s42, 11
; GFX11-NEXT: s_lshr_b32 s42, s13, 8
; GFX11-NEXT: s_lshr_b32 s100, s16, 16
; GFX11-NEXT: s_lshr_b32 s99, s16, 8
; GFX11-NEXT: s_lshr_b32 s102, s2, 16
-; GFX11-NEXT: v_writelane_b32 v76, s42, 12
+; GFX11-NEXT: v_writelane_b32 v78, s42, 12
; GFX11-NEXT: s_lshr_b32 s42, s29, 24
; GFX11-NEXT: s_lshr_b32 s101, s2, 8
; GFX11-NEXT: s_lshr_b32 vcc_hi, s0, 16
; GFX11-NEXT: s_lshr_b32 s103, s0, 8
-; GFX11-NEXT: v_writelane_b32 v76, s42, 13
+; GFX11-NEXT: v_writelane_b32 v78, s42, 13
; GFX11-NEXT: s_lshr_b32 s42, s29, 16
; GFX11-NEXT: s_lshr_b64 s[72:73], s[40:41], 24
; GFX11-NEXT: s_lshr_b64 s[74:75], s[14:15], 24
; GFX11-NEXT: s_lshr_b64 s[76:77], s[10:11], 24
-; GFX11-NEXT: v_writelane_b32 v76, s42, 14
+; GFX11-NEXT: v_writelane_b32 v78, s42, 14
; GFX11-NEXT: s_lshr_b32 s42, s29, 8
; GFX11-NEXT: s_lshr_b64 s[78:79], s[8:9], 24
; GFX11-NEXT: s_lshr_b64 s[88:89], s[6:7], 24
; GFX11-NEXT: s_lshr_b64 s[90:91], s[4:5], 24
-; GFX11-NEXT: v_writelane_b32 v76, s42, 15
+; GFX11-NEXT: v_writelane_b32 v78, s42, 15
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
; GFX11-NEXT: s_lshr_b64 s[92:93], s[12:13], 24
; GFX11-NEXT: s_lshr_b64 s[94:95], s[28:29], 24
; GFX11-NEXT: s_lshr_b64 s[30:31], s[26:27], 24
-; GFX11-NEXT: v_writelane_b32 v76, s42, 16
+; GFX11-NEXT: v_writelane_b32 v78, s42, 16
; GFX11-NEXT: s_lshr_b32 s42, s27, 16
; GFX11-NEXT: s_lshr_b64 s[62:63], s[24:25], 24
; GFX11-NEXT: s_lshr_b64 s[60:61], s[22:23], 24
; GFX11-NEXT: s_lshr_b64 s[58:59], s[20:21], 24
-; GFX11-NEXT: v_writelane_b32 v76, s42, 17
+; GFX11-NEXT: v_writelane_b32 v78, s42, 17
; GFX11-NEXT: s_lshr_b32 s42, s27, 8
; GFX11-NEXT: s_lshr_b64 s[56:57], s[18:19], 24
; GFX11-NEXT: s_lshr_b64 s[46:47], s[16:17], 24
; GFX11-NEXT: s_lshr_b64 s[44:45], s[2:3], 24
-; GFX11-NEXT: v_writelane_b32 v76, s42, 18
+; GFX11-NEXT: v_writelane_b32 v78, s42, 18
; GFX11-NEXT: s_lshr_b32 s42, s25, 24
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v76, s42, 19
+; GFX11-NEXT: v_writelane_b32 v78, s42, 19
; GFX11-NEXT: s_lshr_b32 s42, s25, 16
-; GFX11-NEXT: v_writelane_b32 v76, s42, 20
+; GFX11-NEXT: v_writelane_b32 v78, s42, 20
; GFX11-NEXT: s_lshr_b32 s42, s25, 8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v76, s42, 21
+; GFX11-NEXT: v_writelane_b32 v78, s42, 21
; GFX11-NEXT: s_lshr_b32 s42, s23, 24
-; GFX11-NEXT: v_writelane_b32 v76, s42, 22
+; GFX11-NEXT: v_writelane_b32 v78, s42, 22
; GFX11-NEXT: s_lshr_b32 s42, s23, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v76, s42, 23
+; GFX11-NEXT: v_writelane_b32 v78, s42, 23
; GFX11-NEXT: s_lshr_b32 s42, s23, 8
-; GFX11-NEXT: v_writelane_b32 v76, s42, 24
+; GFX11-NEXT: v_writelane_b32 v78, s42, 24
; GFX11-NEXT: s_lshr_b32 s42, s21, 24
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v76, s42, 25
+; GFX11-NEXT: v_writelane_b32 v78, s42, 25
; GFX11-NEXT: s_lshr_b32 s42, s21, 16
-; GFX11-NEXT: v_writelane_b32 v76, s42, 26
+; GFX11-NEXT: v_writelane_b32 v78, s42, 26
; GFX11-NEXT: s_lshr_b32 s42, s21, 8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v76, s42, 27
+; GFX11-NEXT: v_writelane_b32 v78, s42, 27
; GFX11-NEXT: s_lshr_b32 s42, s19, 24
-; GFX11-NEXT: v_writelane_b32 v76, s42, 28
+; GFX11-NEXT: v_writelane_b32 v78, s42, 28
; GFX11-NEXT: s_lshr_b32 s42, s19, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v76, s42, 29
+; GFX11-NEXT: v_writelane_b32 v78, s42, 29
; GFX11-NEXT: s_lshr_b32 s42, s19, 8
-; GFX11-NEXT: v_writelane_b32 v76, s42, 30
+; GFX11-NEXT: v_writelane_b32 v78, s42, 30
; GFX11-NEXT: s_lshr_b32 s42, s17, 24
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v76, s42, 31
+; GFX11-NEXT: v_writelane_b32 v78, s42, 31
; GFX11-NEXT: s_lshr_b32 s42, s17, 16
-; GFX11-NEXT: v_writelane_b32 v77, s42, 0
+; GFX11-NEXT: v_writelane_b32 v79, s42, 0
; GFX11-NEXT: s_lshr_b32 s42, s17, 8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v77, s42, 1
+; GFX11-NEXT: v_writelane_b32 v79, s42, 1
; GFX11-NEXT: s_lshr_b32 s42, s3, 24
-; GFX11-NEXT: v_writelane_b32 v77, s42, 2
+; GFX11-NEXT: v_writelane_b32 v79, s42, 2
; GFX11-NEXT: s_lshr_b32 s42, s3, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v77, s42, 3
+; GFX11-NEXT: v_writelane_b32 v79, s42, 3
; GFX11-NEXT: s_lshr_b32 s42, s3, 8
-; GFX11-NEXT: v_writelane_b32 v77, s42, 4
+; GFX11-NEXT: v_writelane_b32 v79, s42, 4
; GFX11-NEXT: s_lshr_b32 s42, s1, 24
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v77, s42, 5
+; GFX11-NEXT: v_writelane_b32 v79, s42, 5
; GFX11-NEXT: s_lshr_b32 s42, s1, 16
-; GFX11-NEXT: v_writelane_b32 v77, s42, 6
+; GFX11-NEXT: v_writelane_b32 v79, s42, 6
; GFX11-NEXT: s_lshr_b32 s42, s1, 8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_writelane_b32 v77, s42, 7
+; GFX11-NEXT: v_writelane_b32 v79, s42, 7
; GFX11-NEXT: s_lshr_b64 s[42:43], s[0:1], 24
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
; GFX11-NEXT: s_cbranch_vccnz .LBB73_4
; GFX11-NEXT: .LBB73_2: ; %cmp.true
-; GFX11-NEXT: v_add_f64 v[21:22], s[22:23], 1.0
-; GFX11-NEXT: v_add_f64 v[11:12], s[4:5], 1.0
-; GFX11-NEXT: v_add_f64 v[23:24], s[20:21], 1.0
; GFX11-NEXT: v_add_f64 v[13:14], s[12:13], 1.0
-; GFX11-NEXT: v_add_f64 v[27:28], s[18:19], 1.0
-; GFX11-NEXT: v_add_f64 v[15:16], s[28:29], 1.0
-; GFX11-NEXT: v_add_f64 v[31:32], s[16:17], 1.0
-; GFX11-NEXT: v_add_f64 v[7:8], s[8:9], 1.0
-; GFX11-NEXT: v_add_f64 v[17:18], s[26:27], 1.0
-; GFX11-NEXT: v_add_f64 v[35:36], s[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[1:2], s[40:41], 1.0
+; GFX11-NEXT: v_add_f64 v[15:16], s[28:29], 1.0
; GFX11-NEXT: v_add_f64 v[3:4], s[14:15], 1.0
+; GFX11-NEXT: v_add_f64 v[17:18], s[26:27], 1.0
; GFX11-NEXT: v_add_f64 v[5:6], s[10:11], 1.0
-; GFX11-NEXT: v_add_f64 v[9:10], s[6:7], 1.0
; GFX11-NEXT: v_add_f64 v[19:20], s[24:25], 1.0
-; GFX11-NEXT: v_add_f64 v[48:49], s[0:1], 1.0
-; GFX11-NEXT: v_lshrrev_b64 v[64:65], 24, v[21:22]
-; GFX11-NEXT: v_lshrrev_b64 v[50:51], 24, v[11:12]
-; GFX11-NEXT: v_lshrrev_b64 v[65:66], 24, v[23:24]
-; GFX11-NEXT: v_lshrrev_b64 v[51:52], 24, v[13:14]
-; GFX11-NEXT: v_lshrrev_b64 v[66:67], 24, v[27:28]
-; GFX11-NEXT: v_lshrrev_b64 v[52:53], 24, v[15:16]
-; GFX11-NEXT: v_lshrrev_b64 v[67:68], 24, v[31:32]
-; GFX11-NEXT: v_lshrrev_b64 v[37:38], 24, v[7:8]
-; GFX11-NEXT: v_lshrrev_b64 v[53:54], 24, v[17:18]
-; GFX11-NEXT: v_lshrrev_b64 v[68:69], 24, v[35:36]
-; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[1:2]
-; GFX11-NEXT: v_lshrrev_b64 v[29:30], 24, v[3:4]
-; GFX11-NEXT: v_lshrrev_b64 v[33:34], 24, v[5:6]
-; GFX11-NEXT: v_lshrrev_b64 v[38:39], 24, v[9:10]
-; GFX11-NEXT: v_lshrrev_b64 v[54:55], 24, v[19:20]
-; GFX11-NEXT: v_lshrrev_b64 v[69:70], 24, v[48:49]
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v55, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v82, 24, v4
+; GFX11-NEXT: v_add_f64 v[7:8], s[8:9], 1.0
+; GFX11-NEXT: v_add_f64 v[21:22], s[22:23], 1.0
+; GFX11-NEXT: v_add_f64 v[27:28], s[16:17], 1.0
+; GFX11-NEXT: v_add_f64 v[9:10], s[6:7], 1.0
+; GFX11-NEXT: v_add_f64 v[23:24], s[20:21], 1.0
+; GFX11-NEXT: v_add_f64 v[29:30], s[2:3], 1.0
+; GFX11-NEXT: v_add_f64 v[11:12], s[4:5], 1.0
+; GFX11-NEXT: v_add_f64 v[25:26], s[18:19], 1.0
+; GFX11-NEXT: v_add_f64 v[31:32], s[0:1], 1.0
+; GFX11-NEXT: v_lshrrev_b64 v[48:49], 24, v[13:14]
+; GFX11-NEXT: v_lshrrev_b64 v[33:34], 24, v[1:2]
+; GFX11-NEXT: v_lshrrev_b64 v[49:50], 24, v[15:16]
+; GFX11-NEXT: v_lshrrev_b64 v[34:35], 24, v[3:4]
+; GFX11-NEXT: v_lshrrev_b64 v[50:51], 24, v[17:18]
+; GFX11-NEXT: v_lshrrev_b64 v[35:36], 24, v[5:6]
+; GFX11-NEXT: v_lshrrev_b64 v[51:52], 24, v[19:20]
+; GFX11-NEXT: v_lshrrev_b64 v[36:37], 24, v[7:8]
+; GFX11-NEXT: v_lshrrev_b64 v[52:53], 24, v[21:22]
+; GFX11-NEXT: v_lshrrev_b64 v[64:65], 24, v[27:28]
+; GFX11-NEXT: v_lshrrev_b64 v[37:38], 24, v[9:10]
+; GFX11-NEXT: v_lshrrev_b64 v[53:54], 24, v[23:24]
+; GFX11-NEXT: v_lshrrev_b64 v[65:66], 24, v[29:30]
+; GFX11-NEXT: v_lshrrev_b64 v[38:39], 24, v[11:12]
+; GFX11-NEXT: v_lshrrev_b64 v[54:55], 24, v[25:26]
+; GFX11-NEXT: v_lshrrev_b64 v[66:67], 24, v[31:32]
+; GFX11-NEXT: v_lshrrev_b32_e32 v69, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v80, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v81, 24, v4
; GFX11-NEXT: v_lshrrev_b32_e32 v83, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v81, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v71, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v97, 24, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v98, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v86, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v85, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v70, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v96, 24, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v97, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v99, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v5
; GFX11-NEXT: v_lshrrev_b32_e32 v84, 8, v5
; GFX11-NEXT: v_lshrrev_b32_e32 v102, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v103, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v101, 8, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v112, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v113, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v87, 8, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v114, 24, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v116, 16, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v115, 8, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v100, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v99, 8, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v130, 24, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v131, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v129, 8, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v113, 16, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v112, 8, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v134, 24, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v145, 16, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v144, 8, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v118, 16, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v117, 8, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v148, 24, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v150, 16, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v147, 8, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v128, 16, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v116, 24, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v118, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v128, 8, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v98, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v100, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v131, 24, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v132, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v134, 8, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v101, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v103, 8, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v144, 24, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v146, 16, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v148, 8, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v114, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v115, 8, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v151, 24, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v160, 16, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v161, 8, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v117, 16, v15
; GFX11-NEXT: v_lshrrev_b32_e32 v119, 8, v15
-; GFX11-NEXT: v_lshrrev_b32_e32 v162, 24, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v164, 16, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v163, 8, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v133, 16, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v132, 8, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v176, 24, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v179, 16, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v167, 8, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v146, 16, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v166, 24, v18
+; GFX11-NEXT: v_lshrrev_b32_e32 v167, 16, v18
+; GFX11-NEXT: v_lshrrev_b32_e32 v176, 8, v18
+; GFX11-NEXT: v_lshrrev_b32_e32 v129, 16, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v130, 8, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v179, 24, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v180, 16, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v183, 8, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v133, 16, v19
; GFX11-NEXT: v_lshrrev_b32_e32 v135, 8, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v182, 24, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v40, 16, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v183, 8, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v151, 16, v21
-; GFX11-NEXT: v_lshrrev_b32_e32 v149, 8, v21
-; GFX11-NEXT: v_lshrrev_b32_e32 v44, 24, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v45, 16, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v43, 8, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v161, 16, v23
-; GFX11-NEXT: v_lshrrev_b32_e32 v160, 8, v23
-; GFX11-NEXT: v_lshrrev_b32_e32 v46, 24, v28
-; GFX11-NEXT: v_lshrrev_b32_e32 v56, 16, v28
-; GFX11-NEXT: v_lshrrev_b32_e32 v47, 8, v28
-; GFX11-NEXT: v_lshrrev_b32_e32 v166, 16, v27
+; GFX11-NEXT: v_lshrrev_b32_e32 v40, 24, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v41, 16, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v42, 8, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v145, 16, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v147, 8, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v43, 24, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v44, 16, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v45, 8, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v149, 16, v23
+; GFX11-NEXT: v_lshrrev_b32_e32 v150, 8, v23
+; GFX11-NEXT: v_lshrrev_b32_e32 v46, 24, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v47, 16, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v56, 8, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v162, 16, v25
+; GFX11-NEXT: v_lshrrev_b32_e32 v163, 8, v25
+; GFX11-NEXT: v_lshrrev_b32_e32 v57, 24, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v58, 16, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v59, 8, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v164, 16, v27
; GFX11-NEXT: v_lshrrev_b32_e32 v165, 8, v27
-; GFX11-NEXT: v_lshrrev_b32_e32 v58, 24, v32
-; GFX11-NEXT: v_lshrrev_b32_e32 v59, 16, v32
-; GFX11-NEXT: v_lshrrev_b32_e32 v57, 8, v32
-; GFX11-NEXT: v_lshrrev_b32_e32 v178, 16, v31
-; GFX11-NEXT: v_lshrrev_b32_e32 v177, 8, v31
-; GFX11-NEXT: v_lshrrev_b32_e32 v60, 24, v36
-; GFX11-NEXT: v_lshrrev_b32_e32 v62, 16, v36
-; GFX11-NEXT: v_lshrrev_b32_e32 v61, 8, v36
-; GFX11-NEXT: v_lshrrev_b32_e32 v181, 16, v35
-; GFX11-NEXT: v_lshrrev_b32_e32 v180, 8, v35
-; GFX11-NEXT: v_lshrrev_b32_e32 v63, 24, v49
-; GFX11-NEXT: v_lshrrev_b32_e32 v72, 16, v49
-; GFX11-NEXT: v_lshrrev_b32_e32 v73, 8, v49
-; GFX11-NEXT: v_lshrrev_b32_e32 v41, 16, v48
-; GFX11-NEXT: v_lshrrev_b32_e32 v42, 8, v48
+; GFX11-NEXT: v_lshrrev_b32_e32 v60, 24, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v61, 16, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v62, 8, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v177, 16, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v178, 8, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v63, 24, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v72, 16, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v73, 8, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v181, 16, v31
+; GFX11-NEXT: v_lshrrev_b32_e32 v182, 8, v31
; GFX11-NEXT: s_branch .LBB73_5
; GFX11-NEXT: .LBB73_3:
; GFX11-NEXT: ; implicit-def: $sgpr43
@@ -113983,358 +113343,329 @@ define inreg <128 x i8> @bitcast_v16f64_to_v128i8_scalar(<16 x double> inreg %a,
; GFX11-NEXT: ; kill: killed $sgpr43
; GFX11-NEXT: s_branch .LBB73_2
; GFX11-NEXT: .LBB73_4:
-; GFX11-NEXT: v_dual_mov_b32 v48, s0 :: v_dual_mov_b32 v49, s1
-; GFX11-NEXT: v_readlane_b32 s0, v76, 0
-; GFX11-NEXT: v_mov_b32_e32 v83, s36
+; GFX11-NEXT: v_dual_mov_b32 v31, s0 :: v_dual_mov_b32 v32, s1
+; GFX11-NEXT: v_readlane_b32 s0, v78, 0
; GFX11-NEXT: v_dual_mov_b32 v1, s40 :: v_dual_mov_b32 v2, s41
; GFX11-NEXT: v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, s15
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_mov_b32_e32 v98, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 1
-; GFX11-NEXT: v_mov_b32_e32 v97, s34
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mov_b32_e32 v97, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 1
+; GFX11-NEXT: v_mov_b32_e32 v39, s50
; GFX11-NEXT: v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v6, s11
; GFX11-NEXT: v_dual_mov_b32 v7, s8 :: v_dual_mov_b32 v8, s9
; GFX11-NEXT: v_mov_b32_e32 v102, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 2
+; GFX11-NEXT: v_readlane_b32 s0, v78, 2
+; GFX11-NEXT: v_mov_b32_e32 v55, s49
; GFX11-NEXT: v_dual_mov_b32 v9, s6 :: v_dual_mov_b32 v10, s7
; GFX11-NEXT: v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v12, s5
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v103, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mov_b32_e32 v112, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 3
; GFX11-NEXT: v_dual_mov_b32 v13, s12 :: v_dual_mov_b32 v14, s13
; GFX11-NEXT: v_dual_mov_b32 v15, s28 :: v_dual_mov_b32 v16, s29
-; GFX11-NEXT: v_mov_b32_e32 v101, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 4
+; GFX11-NEXT: v_mov_b32_e32 v113, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 4
+; GFX11-NEXT: v_mov_b32_e32 v69, s48
; GFX11-NEXT: v_dual_mov_b32 v17, s26 :: v_dual_mov_b32 v18, s27
; GFX11-NEXT: v_dual_mov_b32 v19, s24 :: v_dual_mov_b32 v20, s25
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v114, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mov_b32_e32 v116, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 5
+; GFX11-NEXT: v_mov_b32_e32 v71, s39
; GFX11-NEXT: v_dual_mov_b32 v21, s22 :: v_dual_mov_b32 v22, s23
; GFX11-NEXT: v_dual_mov_b32 v23, s20 :: v_dual_mov_b32 v24, s21
-; GFX11-NEXT: v_mov_b32_e32 v116, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 6
-; GFX11-NEXT: v_dual_mov_b32 v27, s18 :: v_dual_mov_b32 v28, s19
-; GFX11-NEXT: v_dual_mov_b32 v31, s16 :: v_dual_mov_b32 v32, s17
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v115, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 7
-; GFX11-NEXT: v_dual_mov_b32 v35, s2 :: v_dual_mov_b32 v36, s3
-; GFX11-NEXT: v_dual_mov_b32 v41, vcc_hi :: v_dual_mov_b32 v42, s103
-; GFX11-NEXT: v_mov_b32_e32 v130, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 8
-; GFX11-NEXT: v_dual_mov_b32 v181, s102 :: v_dual_mov_b32 v180, s101
-; GFX11-NEXT: v_dual_mov_b32 v178, s100 :: v_dual_mov_b32 v177, s99
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mov_b32_e32 v118, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 6
+; GFX11-NEXT: v_mov_b32_e32 v81, s37
+; GFX11-NEXT: v_dual_mov_b32 v25, s18 :: v_dual_mov_b32 v26, s19
+; GFX11-NEXT: v_dual_mov_b32 v27, s16 :: v_dual_mov_b32 v28, s17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mov_b32_e32 v128, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 7
+; GFX11-NEXT: v_dual_mov_b32 v29, s2 :: v_dual_mov_b32 v30, s3
+; GFX11-NEXT: v_dual_mov_b32 v181, vcc_hi :: v_dual_mov_b32 v182, s103
; GFX11-NEXT: v_mov_b32_e32 v131, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 9
-; GFX11-NEXT: v_dual_mov_b32 v166, s98 :: v_dual_mov_b32 v165, s97
-; GFX11-NEXT: v_dual_mov_b32 v161, s96 :: v_dual_mov_b32 v160, s87
-; GFX11-NEXT: v_mov_b32_e32 v129, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 10
-; GFX11-NEXT: v_dual_mov_b32 v151, s86 :: v_dual_mov_b32 v146, s84
-; GFX11-NEXT: v_dual_mov_b32 v149, s85 :: v_dual_mov_b32 v132, s81
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_readlane_b32 s0, v78, 8
+; GFX11-NEXT: v_mov_b32_e32 v83, s36
+; GFX11-NEXT: v_dual_mov_b32 v177, s102 :: v_dual_mov_b32 v178, s101
+; GFX11-NEXT: v_dual_mov_b32 v164, s100 :: v_dual_mov_b32 v165, s99
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_mov_b32_e32 v132, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 9
+; GFX11-NEXT: v_dual_mov_b32 v85, s35 :: v_dual_mov_b32 v162, s98
+; GFX11-NEXT: v_mov_b32_e32 v163, s97
+; GFX11-NEXT: v_dual_mov_b32 v149, s96 :: v_dual_mov_b32 v150, s87
; GFX11-NEXT: v_mov_b32_e32 v134, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 11
-; GFX11-NEXT: v_dual_mov_b32 v135, s83 :: v_dual_mov_b32 v128, s80
-; GFX11-NEXT: v_dual_mov_b32 v133, s82 :: v_dual_mov_b32 v118, s70
-; GFX11-NEXT: v_mov_b32_e32 v145, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 12
-; GFX11-NEXT: v_dual_mov_b32 v119, s71 :: v_dual_mov_b32 v112, s67
-; GFX11-NEXT: v_dual_mov_b32 v117, s69 :: v_dual_mov_b32 v100, s66
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_readlane_b32 s0, v78, 10
+; GFX11-NEXT: v_dual_mov_b32 v145, s86 :: v_dual_mov_b32 v130, s81
+; GFX11-NEXT: v_dual_mov_b32 v147, s85 :: v_dual_mov_b32 v114, s70
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-NEXT: v_mov_b32_e32 v144, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 13
-; GFX11-NEXT: v_dual_mov_b32 v113, s68 :: v_dual_mov_b32 v96, s64
-; GFX11-NEXT: v_dual_mov_b32 v99, s65 :: v_dual_mov_b32 v84, s53
-; GFX11-NEXT: v_mov_b32_e32 v148, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 14
-; GFX11-NEXT: v_dual_mov_b32 v87, s55 :: v_dual_mov_b32 v80, s52
-; GFX11-NEXT: v_dual_mov_b32 v85, s54 :: v_dual_mov_b32 v30, s50
+; GFX11-NEXT: v_readlane_b32 s0, v78, 11
+; GFX11-NEXT: v_mov_b32_e32 v99, s104
+; GFX11-NEXT: v_dual_mov_b32 v133, s84 :: v_dual_mov_b32 v98, s66
+; GFX11-NEXT: v_dual_mov_b32 v135, s83 :: v_dual_mov_b32 v100, s65
+; GFX11-NEXT: v_mov_b32_e32 v146, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 12
+; GFX11-NEXT: v_dual_mov_b32 v129, s82 :: v_dual_mov_b32 v86, s64
+; GFX11-NEXT: v_dual_mov_b32 v117, s80 :: v_dual_mov_b32 v82, s54
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v150, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 15
-; GFX11-NEXT: v_dual_mov_b32 v71, s51 :: v_dual_mov_b32 v26, s49
-; GFX11-NEXT: v_dual_mov_b32 v39, s48 :: v_dual_mov_b32 v34, s38
-; GFX11-NEXT: v_mov_b32_e32 v147, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 16
-; GFX11-NEXT: v_dual_mov_b32 v55, s39 :: v_dual_mov_b32 v82, s37
-; GFX11-NEXT: v_dual_mov_b32 v81, s35 :: v_dual_mov_b32 v86, s104
+; GFX11-NEXT: v_mov_b32_e32 v148, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 13
+; GFX11-NEXT: v_dual_mov_b32 v119, s71 :: v_dual_mov_b32 v84, s53
+; GFX11-NEXT: v_dual_mov_b32 v115, s69 :: v_dual_mov_b32 v68, s52
+; GFX11-NEXT: v_mov_b32_e32 v151, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 14
+; GFX11-NEXT: v_dual_mov_b32 v101, s68 :: v_dual_mov_b32 v70, s51
+; GFX11-NEXT: v_dual_mov_b32 v103, s67 :: v_dual_mov_b32 v80, s38
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v162, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 17
-; GFX11-NEXT: v_dual_mov_b32 v69, s42 :: v_dual_mov_b32 v68, s44
-; GFX11-NEXT: v_dual_mov_b32 v67, s46 :: v_dual_mov_b32 v66, s56
-; GFX11-NEXT: v_mov_b32_e32 v164, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 18
-; GFX11-NEXT: v_dual_mov_b32 v65, s58 :: v_dual_mov_b32 v64, s60
-; GFX11-NEXT: v_dual_mov_b32 v54, s62 :: v_dual_mov_b32 v53, s30
+; GFX11-NEXT: v_mov_b32_e32 v160, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 15
+; GFX11-NEXT: v_dual_mov_b32 v87, s55 :: v_dual_mov_b32 v96, s34
+; GFX11-NEXT: v_dual_mov_b32 v65, s44 :: v_dual_mov_b32 v54, s56
+; GFX11-NEXT: v_mov_b32_e32 v161, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 16
+; GFX11-NEXT: v_dual_mov_b32 v53, s58 :: v_dual_mov_b32 v52, s60
+; GFX11-NEXT: v_dual_mov_b32 v51, s62 :: v_dual_mov_b32 v50, s30
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v163, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 19
-; GFX11-NEXT: v_dual_mov_b32 v52, s94 :: v_dual_mov_b32 v51, s92
-; GFX11-NEXT: v_dual_mov_b32 v50, s90 :: v_dual_mov_b32 v37, s78
-; GFX11-NEXT: v_mov_b32_e32 v176, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 20
-; GFX11-NEXT: v_dual_mov_b32 v38, s88 :: v_dual_mov_b32 v33, s76
-; GFX11-NEXT: v_mov_b32_e32 v29, s74
-; GFX11-NEXT: v_mov_b32_e32 v25, s72
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v179, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 21
+; GFX11-NEXT: v_mov_b32_e32 v166, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 17
+; GFX11-NEXT: v_dual_mov_b32 v49, s94 :: v_dual_mov_b32 v48, s92
+; GFX11-NEXT: v_dual_mov_b32 v38, s90 :: v_dual_mov_b32 v37, s88
; GFX11-NEXT: v_mov_b32_e32 v167, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 22
+; GFX11-NEXT: v_readlane_b32 s0, v78, 18
+; GFX11-NEXT: v_dual_mov_b32 v36, s78 :: v_dual_mov_b32 v35, s76
+; GFX11-NEXT: v_dual_mov_b32 v34, s74 :: v_dual_mov_b32 v33, s72
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-NEXT: v_mov_b32_e32 v176, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 19
+; GFX11-NEXT: v_mov_b32_e32 v66, s42
+; GFX11-NEXT: v_dual_mov_b32 v64, s46 :: v_dual_mov_b32 v179, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 20
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mov_b32_e32 v180, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 21
+; GFX11-NEXT: v_mov_b32_e32 v183, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 22
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v182, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 23
; GFX11-NEXT: v_mov_b32_e32 v40, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 24
+; GFX11-NEXT: v_readlane_b32 s0, v78, 23
+; GFX11-NEXT: v_mov_b32_e32 v41, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v183, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 25
-; GFX11-NEXT: v_mov_b32_e32 v44, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 26
+; GFX11-NEXT: v_mov_b32_e32 v42, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 25
+; GFX11-NEXT: v_mov_b32_e32 v43, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mov_b32_e32 v44, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 27
; GFX11-NEXT: v_mov_b32_e32 v45, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 27
-; GFX11-NEXT: v_mov_b32_e32 v43, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 28
+; GFX11-NEXT: v_readlane_b32 s0, v78, 28
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v46, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 29
+; GFX11-NEXT: v_readlane_b32 s0, v78, 29
+; GFX11-NEXT: v_mov_b32_e32 v47, s0
+; GFX11-NEXT: v_readlane_b32 s0, v78, 30
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v56, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 30
+; GFX11-NEXT: v_readlane_b32 s0, v78, 31
+; GFX11-NEXT: v_mov_b32_e32 v57, s0
+; GFX11-NEXT: v_readlane_b32 s0, v79, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v47, s0
-; GFX11-NEXT: v_readlane_b32 s0, v76, 31
; GFX11-NEXT: v_mov_b32_e32 v58, s0
-; GFX11-NEXT: v_readlane_b32 s0, v77, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s0, v79, 1
; GFX11-NEXT: v_mov_b32_e32 v59, s0
-; GFX11-NEXT: v_readlane_b32 s0, v77, 1
-; GFX11-NEXT: v_mov_b32_e32 v57, s0
-; GFX11-NEXT: v_readlane_b32 s0, v77, 2
+; GFX11-NEXT: v_readlane_b32 s0, v79, 2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v60, s0
-; GFX11-NEXT: v_readlane_b32 s0, v77, 3
-; GFX11-NEXT: v_mov_b32_e32 v62, s0
-; GFX11-NEXT: v_readlane_b32 s0, v77, 4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_readlane_b32 s0, v79, 3
; GFX11-NEXT: v_mov_b32_e32 v61, s0
-; GFX11-NEXT: v_readlane_b32 s0, v77, 5
+; GFX11-NEXT: v_readlane_b32 s0, v79, 4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mov_b32_e32 v62, s0
+; GFX11-NEXT: v_readlane_b32 s0, v79, 5
; GFX11-NEXT: v_mov_b32_e32 v63, s0
-; GFX11-NEXT: v_readlane_b32 s0, v77, 6
+; GFX11-NEXT: v_readlane_b32 s0, v79, 6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v72, s0
-; GFX11-NEXT: v_readlane_b32 s0, v77, 7
+; GFX11-NEXT: v_readlane_b32 s0, v79, 7
; GFX11-NEXT: v_mov_b32_e32 v73, s0
; GFX11-NEXT: .LBB73_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v69, v41, v69, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v48, v48, v42, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v70, v72, v63, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v68, v181, v68, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v181, v62, v60, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
-; GFX11-NEXT: v_perm_b32 v49, v49, v73, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v70
-; GFX11-NEXT: v_perm_b32 v35, v35, v180, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v180, 16, v181
-; GFX11-NEXT: v_or_b32_e32 v60, v48, v69
-; GFX11-NEXT: v_perm_b32 v48, v178, v67, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v61, v49, v70
-; GFX11-NEXT: v_perm_b32 v49, v56, v46, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v63, v36, v180
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
-; GFX11-NEXT: v_lshlrev_b32_e32 v36, 16, v48
-; GFX11-NEXT: v_perm_b32 v48, v166, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v31, v31, v177, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v29, v178, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v65, v177, v65, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v66, v181, v66, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v31, v182, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v32, v73, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v67, v72, v63, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v74, v65, 16, v29
+; GFX11-NEXT: v_perm_b32 v29, v30, v62, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v61, v60, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v72, v66, 16, v31
+; GFX11-NEXT: v_lshl_or_b32 v73, v67, 16, v32
; GFX11-NEXT: v_perm_b32 v27, v27, v165, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v28, v28, v47, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v49, 16, v49
-; GFX11-NEXT: v_lshlrev_b32_e32 v48, 16, v48
-; GFX11-NEXT: v_or_b32_e32 v62, v35, v68
-; GFX11-NEXT: v_perm_b32 v35, v59, v58, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v66, v31, v36
-; GFX11-NEXT: v_or_b32_e32 v69, v28, v49
-; GFX11-NEXT: v_or_b32_e32 v68, v27, v48
-; GFX11-NEXT: v_perm_b32 v27, v161, v65, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v28, v45, v44, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v31, v151, v64, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v32, v32, v57, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v35, 16, v35
-; GFX11-NEXT: v_perm_b32 v23, v23, v160, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_perm_b32 v24, v24, v43, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-NEXT: v_perm_b32 v21, v21, v149, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-NEXT: v_or_b32_e32 v67, v32, v35
+; GFX11-NEXT: v_perm_b32 v31, v164, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v28, v59, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v58, v57, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v25, v163, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v54, v162, v54, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v65, v26, v56, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v66, v47, v46, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v75, v30, 16, v29
+; GFX11-NEXT: v_perm_b32 v23, v23, v150, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v149, v53, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v24, v45, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v44, v43, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v25, v31, 16, v27
+; GFX11-NEXT: v_lshl_or_b32 v26, v32, 16, v28
+; GFX11-NEXT: v_lshl_or_b32 v27, v54, 16, v64
+; GFX11-NEXT: v_lshl_or_b32 v28, v66, 16, v65
+; GFX11-NEXT: v_perm_b32 v31, v21, v147, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v145, v52, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v52, v22, v42, 0xc0c0004
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: scratch_store_b128 v0, v[60:63], off
-; GFX11-NEXT: scratch_store_b128 v0, v[66:69], off offset:16
-; GFX11-NEXT: v_or_b32_e32 v64, v23, v27
-; GFX11-NEXT: v_perm_b32 v23, v40, v182, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v65, v24, v28
-; GFX11-NEXT: v_or_b32_e32 v66, v21, v31
-; GFX11-NEXT: v_perm_b32 v21, v22, v183, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v22, v146, v54, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v179, v176, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v27, v133, v53, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: scratch_store_b128 v0, v[72:75], off
+; GFX11-NEXT: scratch_store_b128 v0, v[25:28], off offset:16
+; GFX11-NEXT: v_lshl_or_b32 v21, v29, 16, v23
+; GFX11-NEXT: v_lshl_or_b32 v22, v30, 16, v24
; GFX11-NEXT: v_perm_b32 v19, v19, v135, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_perm_b32 v20, v20, v167, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v17, v17, v132, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_or_b32_e32 v67, v21, v23
-; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
-; GFX11-NEXT: v_perm_b32 v22, v164, v162, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v20, v20, v24
-; GFX11-NEXT: v_or_b32_e32 v21, v17, v27
-; GFX11-NEXT: v_perm_b32 v17, v18, v163, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v128, v52, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v118, v51, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v150, v148, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
+; GFX11-NEXT: v_perm_b32 v25, v133, v51, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v20, v183, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v26, v180, v179, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v17, v130, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v129, v50, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v18, v176, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v167, v166, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v23, v32, 16, v31
; GFX11-NEXT: v_perm_b32 v15, v15, v119, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v13, v13, v117, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v16, v16, v147, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
-; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
-; GFX11-NEXT: v_perm_b32 v18, v145, v134, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v17, v13, v24
-; GFX11-NEXT: v_perm_b32 v24, v100, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v23
-; GFX11-NEXT: v_perm_b32 v13, v14, v144, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v14, v113, v50, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v131, v130, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v9, v9, v99, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v11, v11, v112, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v12, v12, v129, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v24
-; GFX11-NEXT: v_perm_b32 v9, v10, v115, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v96, v37, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
-; GFX11-NEXT: v_perm_b32 v14, v116, v114, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v23
-; GFX11-NEXT: v_perm_b32 v23, v103, v102, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v85, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v87, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v8, v8, v101, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX11-NEXT: v_perm_b32 v31, v117, v49, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v17, v25, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v18, v26, 16, v20
+; GFX11-NEXT: v_lshl_or_b32 v19, v28, 16, v27
+; GFX11-NEXT: v_lshl_or_b32 v20, v30, 16, v29
+; GFX11-NEXT: v_perm_b32 v13, v13, v115, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v114, v48, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v11, v103, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v101, v38, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v25, v31, 16, v15
+; GFX11-NEXT: v_perm_b32 v15, v16, v161, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v160, v151, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v14, v14, v148, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v146, v144, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v27, v27, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v11, v29, 16, v11
+; GFX11-NEXT: v_perm_b32 v9, v9, v100, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v98, v37, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v5, v5, v84, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
-; GFX11-NEXT: v_perm_b32 v10, v98, v97, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v23
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v24
-; GFX11-NEXT: v_perm_b32 v5, v80, v29, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v83, v82, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v30, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v55, v39, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v86, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v71, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v81, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_perm_b32 v26, v1, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v27, v2, v34, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v23
-; GFX11-NEXT: v_or_b32_e32 v3, v26, v24
-; GFX11-NEXT: v_or_b32_e32 v4, v27, v25
+; GFX11-NEXT: v_perm_b32 v29, v82, v35, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v53, v41, v40, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v12, v134, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v132, v131, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v26, v16, 16, v15
+; GFX11-NEXT: v_perm_b32 v7, v7, v87, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v86, v36, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v8, v8, v113, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v112, v102, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v28, v28, 16, v14
+; GFX11-NEXT: v_perm_b32 v10, v10, v128, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v14, v118, v116, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v9, v29, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v99, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v97, v96, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v24, v53, 16, v52
+; GFX11-NEXT: v_lshl_or_b32 v12, v30, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v7, v15, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v8, v16, 16, v8
+; GFX11-NEXT: v_perm_b32 v3, v3, v70, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v68, v34, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v85, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v83, v81, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v1, v55, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v39, v33, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v2, v80, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v71, v69, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v10, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v1, v15, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v16, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v30, 16, v29
+; GFX11-NEXT: v_lshl_or_b32 v4, v32, 16, v31
; GFX11-NEXT: s_clause 0x5
-; GFX11-NEXT: scratch_store_b128 v0, v[64:67], off offset:32
-; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
-; GFX11-NEXT: scratch_store_b128 v0, v[15:18], off offset:64
+; GFX11-NEXT: scratch_store_b128 v0, v[21:24], off offset:32
+; GFX11-NEXT: scratch_store_b128 v0, v[17:20], off offset:48
+; GFX11-NEXT: scratch_store_b128 v0, v[25:28], off offset:64
; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:80
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:96
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:112
-; GFX11-NEXT: s_clause 0x11 ; 72-byte Folded Reload
-; GFX11-NEXT: scratch_load_b32 v73, off, s32
-; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:4
-; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:8
-; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:12
-; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:16
-; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:20
-; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:24
-; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:28
-; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:32
-; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:36
-; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:40
-; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:44
-; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:48
-; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:52
-; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:56
-; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:60
-; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:64
-; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:68
-; GFX11-NEXT: v_readlane_b32 s30, v75, 7
-; GFX11-NEXT: v_readlane_b32 s31, v75, 8
-; GFX11-NEXT: v_readlane_b32 s104, v75, 6
-; GFX11-NEXT: v_readlane_b32 s103, v75, 5
-; GFX11-NEXT: v_readlane_b32 s102, v75, 4
-; GFX11-NEXT: v_readlane_b32 s101, v75, 3
-; GFX11-NEXT: v_readlane_b32 s100, v75, 2
-; GFX11-NEXT: v_readlane_b32 s99, v75, 1
-; GFX11-NEXT: v_readlane_b32 s98, v75, 0
-; GFX11-NEXT: v_readlane_b32 s97, v74, 31
-; GFX11-NEXT: v_readlane_b32 s96, v74, 30
-; GFX11-NEXT: v_readlane_b32 s87, v74, 29
-; GFX11-NEXT: v_readlane_b32 s86, v74, 28
-; GFX11-NEXT: v_readlane_b32 s85, v74, 27
-; GFX11-NEXT: v_readlane_b32 s84, v74, 26
-; GFX11-NEXT: v_readlane_b32 s83, v74, 25
-; GFX11-NEXT: v_readlane_b32 s82, v74, 24
-; GFX11-NEXT: v_readlane_b32 s81, v74, 23
-; GFX11-NEXT: v_readlane_b32 s80, v74, 22
-; GFX11-NEXT: v_readlane_b32 s71, v74, 21
-; GFX11-NEXT: v_readlane_b32 s70, v74, 20
-; GFX11-NEXT: v_readlane_b32 s69, v74, 19
-; GFX11-NEXT: v_readlane_b32 s68, v74, 18
-; GFX11-NEXT: v_readlane_b32 s67, v74, 17
-; GFX11-NEXT: v_readlane_b32 s66, v74, 16
-; GFX11-NEXT: v_readlane_b32 s65, v74, 15
-; GFX11-NEXT: v_readlane_b32 s64, v74, 14
-; GFX11-NEXT: v_readlane_b32 s55, v74, 13
-; GFX11-NEXT: v_readlane_b32 s54, v74, 12
-; GFX11-NEXT: v_readlane_b32 s53, v74, 11
-; GFX11-NEXT: v_readlane_b32 s52, v74, 10
-; GFX11-NEXT: v_readlane_b32 s51, v74, 9
-; GFX11-NEXT: v_readlane_b32 s50, v74, 8
-; GFX11-NEXT: v_readlane_b32 s49, v74, 7
-; GFX11-NEXT: v_readlane_b32 s48, v74, 6
-; GFX11-NEXT: v_readlane_b32 s39, v74, 5
-; GFX11-NEXT: v_readlane_b32 s38, v74, 4
-; GFX11-NEXT: v_readlane_b32 s37, v74, 3
-; GFX11-NEXT: v_readlane_b32 s36, v74, 2
-; GFX11-NEXT: v_readlane_b32 s35, v74, 1
-; GFX11-NEXT: v_readlane_b32 s34, v74, 0
+; GFX11-NEXT: s_clause 0x13 ; 80-byte Folded Reload
+; GFX11-NEXT: scratch_load_b32 v75, off, s32
+; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:4
+; GFX11-NEXT: scratch_load_b32 v73, off, s32 offset:8
+; GFX11-NEXT: scratch_load_b32 v72, off, s32 offset:12
+; GFX11-NEXT: scratch_load_b32 v63, off, s32 offset:16
+; GFX11-NEXT: scratch_load_b32 v62, off, s32 offset:20
+; GFX11-NEXT: scratch_load_b32 v61, off, s32 offset:24
+; GFX11-NEXT: scratch_load_b32 v60, off, s32 offset:28
+; GFX11-NEXT: scratch_load_b32 v59, off, s32 offset:32
+; GFX11-NEXT: scratch_load_b32 v58, off, s32 offset:36
+; GFX11-NEXT: scratch_load_b32 v57, off, s32 offset:40
+; GFX11-NEXT: scratch_load_b32 v56, off, s32 offset:44
+; GFX11-NEXT: scratch_load_b32 v47, off, s32 offset:48
+; GFX11-NEXT: scratch_load_b32 v46, off, s32 offset:52
+; GFX11-NEXT: scratch_load_b32 v45, off, s32 offset:56
+; GFX11-NEXT: scratch_load_b32 v44, off, s32 offset:60
+; GFX11-NEXT: scratch_load_b32 v43, off, s32 offset:64
+; GFX11-NEXT: scratch_load_b32 v42, off, s32 offset:68
+; GFX11-NEXT: scratch_load_b32 v41, off, s32 offset:72
+; GFX11-NEXT: scratch_load_b32 v40, off, s32 offset:76
+; GFX11-NEXT: v_readlane_b32 s30, v77, 7
+; GFX11-NEXT: v_readlane_b32 s31, v77, 8
+; GFX11-NEXT: v_readlane_b32 s104, v77, 6
+; GFX11-NEXT: v_readlane_b32 s103, v77, 5
+; GFX11-NEXT: v_readlane_b32 s102, v77, 4
+; GFX11-NEXT: v_readlane_b32 s101, v77, 3
+; GFX11-NEXT: v_readlane_b32 s100, v77, 2
+; GFX11-NEXT: v_readlane_b32 s99, v77, 1
+; GFX11-NEXT: v_readlane_b32 s98, v77, 0
+; GFX11-NEXT: v_readlane_b32 s97, v76, 31
+; GFX11-NEXT: v_readlane_b32 s96, v76, 30
+; GFX11-NEXT: v_readlane_b32 s87, v76, 29
+; GFX11-NEXT: v_readlane_b32 s86, v76, 28
+; GFX11-NEXT: v_readlane_b32 s85, v76, 27
+; GFX11-NEXT: v_readlane_b32 s84, v76, 26
+; GFX11-NEXT: v_readlane_b32 s83, v76, 25
+; GFX11-NEXT: v_readlane_b32 s82, v76, 24
+; GFX11-NEXT: v_readlane_b32 s81, v76, 23
+; GFX11-NEXT: v_readlane_b32 s80, v76, 22
+; GFX11-NEXT: v_readlane_b32 s71, v76, 21
+; GFX11-NEXT: v_readlane_b32 s70, v76, 20
+; GFX11-NEXT: v_readlane_b32 s69, v76, 19
+; GFX11-NEXT: v_readlane_b32 s68, v76, 18
+; GFX11-NEXT: v_readlane_b32 s67, v76, 17
+; GFX11-NEXT: v_readlane_b32 s66, v76, 16
+; GFX11-NEXT: v_readlane_b32 s65, v76, 15
+; GFX11-NEXT: v_readlane_b32 s64, v76, 14
+; GFX11-NEXT: v_readlane_b32 s55, v76, 13
+; GFX11-NEXT: v_readlane_b32 s54, v76, 12
+; GFX11-NEXT: v_readlane_b32 s53, v76, 11
+; GFX11-NEXT: v_readlane_b32 s52, v76, 10
+; GFX11-NEXT: v_readlane_b32 s51, v76, 9
+; GFX11-NEXT: v_readlane_b32 s50, v76, 8
+; GFX11-NEXT: v_readlane_b32 s49, v76, 7
+; GFX11-NEXT: v_readlane_b32 s48, v76, 6
+; GFX11-NEXT: v_readlane_b32 s39, v76, 5
+; GFX11-NEXT: v_readlane_b32 s38, v76, 4
+; GFX11-NEXT: v_readlane_b32 s37, v76, 3
+; GFX11-NEXT: v_readlane_b32 s36, v76, 2
+; GFX11-NEXT: v_readlane_b32 s35, v76, 1
+; GFX11-NEXT: v_readlane_b32 s34, v76, 0
; GFX11-NEXT: s_or_saveexec_b32 s0, -1
; GFX11-NEXT: s_clause 0x3 ; 16-byte Folded Reload
-; GFX11-NEXT: scratch_load_b32 v74, off, s32 offset:72
-; GFX11-NEXT: scratch_load_b32 v75, off, s32 offset:76
; GFX11-NEXT: scratch_load_b32 v76, off, s32 offset:80
; GFX11-NEXT: scratch_load_b32 v77, off, s32 offset:84
+; GFX11-NEXT: scratch_load_b32 v78, off, s32 offset:88
+; GFX11-NEXT: scratch_load_b32 v79, off, s32 offset:92
; GFX11-NEXT: s_mov_b32 exec_lo, s0
; GFX11-NEXT: s_waitcnt vmcnt(0)
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -122310,99 +121641,99 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:324
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:320
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:316
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:312
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:308
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:304
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:296
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:292
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:288
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:280
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:276
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:272
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:268
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:264
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:260
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:256
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:252
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:476 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:484 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:236
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:496 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:228
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:500 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:504 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:216
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:512 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:212
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:516 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:520 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v31
-; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:200
+; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:200
; GFX9-NEXT: buffer_load_ushort v25, off, s[0:3], s32 offset:196
-; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:192
+; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:192
; GFX9-NEXT: buffer_load_ushort v27, off, s[0:3], s32 offset:188
; GFX9-NEXT: buffer_load_ushort v23, off, s[0:3], s32 offset:184
; GFX9-NEXT: buffer_load_ushort v28, off, s[0:3], s32 offset:180
@@ -122411,371 +121742,315 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: buffer_load_ushort v22, off, s[0:3], s32 offset:168
; GFX9-NEXT: buffer_load_ushort v31, off, s[0:3], s32 offset:164
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:160
-; GFX9-NEXT: buffer_load_ushort v24, off, s[0:3], s32 offset:156
+; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:156
; GFX9-NEXT: buffer_load_ushort v21, off, s[0:3], s32 offset:152
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:148
-; GFX9-NEXT: buffer_load_ushort v26, off, s[0:3], s32 offset:144
-; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:140
+; GFX9-NEXT: buffer_load_ushort v46, off, s[0:3], s32 offset:144
+; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:140
; GFX9-NEXT: buffer_load_ushort v20, off, s[0:3], s32 offset:136
-; GFX9-NEXT: buffer_load_ushort v45, off, s[0:3], s32 offset:132
-; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:128
-; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:124
+; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:132
+; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:128
+; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:124
; GFX9-NEXT: buffer_load_ushort v19, off, s[0:3], s32 offset:120
-; GFX9-NEXT: buffer_load_ushort v57, off, s[0:3], s32 offset:116
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:112
-; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:108
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:116
+; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:112
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:108
; GFX9-NEXT: buffer_load_ushort v18, off, s[0:3], s32 offset:104
-; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:100
-; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:96
-; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:92
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:100
+; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:96
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:92
; GFX9-NEXT: buffer_load_ushort v17, off, s[0:3], s32 offset:88
-; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:84
-; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:80
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:76
+; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:84
+; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:80
+; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:76
; GFX9-NEXT: buffer_load_ushort v16, off, s[0:3], s32 offset:72
-; GFX9-NEXT: buffer_load_ushort v32, off, s[0:3], s32 offset:68
-; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:64
-; GFX9-NEXT: buffer_load_ushort v34, off, s[0:3], s32 offset:60
-; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:56
-; GFX9-NEXT: buffer_load_ushort v36, off, s[0:3], s32 offset:52
-; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:48
-; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:44
-; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:40
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:36
-; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:32
-; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:28
-; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:24
-; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:20
-; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:16
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:12
+; GFX9-NEXT: buffer_load_ushort v35, off, s[0:3], s32 offset:68
+; GFX9-NEXT: buffer_load_ushort v37, off, s[0:3], s32 offset:64
+; GFX9-NEXT: buffer_load_ushort v39, off, s[0:3], s32 offset:60
+; GFX9-NEXT: buffer_load_ushort v38, off, s[0:3], s32 offset:56
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:52
+; GFX9-NEXT: buffer_load_ushort v49, off, s[0:3], s32 offset:48
+; GFX9-NEXT: buffer_load_ushort v51, off, s[0:3], s32 offset:44
+; GFX9-NEXT: buffer_load_ushort v50, off, s[0:3], s32 offset:40
+; GFX9-NEXT: buffer_load_ushort v52, off, s[0:3], s32 offset:36
+; GFX9-NEXT: buffer_load_ushort v53, off, s[0:3], s32 offset:32
+; GFX9-NEXT: buffer_load_ushort v55, off, s[0:3], s32 offset:28
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:24
+; GFX9-NEXT: buffer_load_ushort v40, off, s[0:3], s32 offset:20
+; GFX9-NEXT: buffer_load_ushort v41, off, s[0:3], s32 offset:16
+; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:12
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v55, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v29, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v30, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v31, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(47)
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v44, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v45, off, s[0:3], s32 offset:664 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(44)
-; GFX9-NEXT: buffer_store_dword v47, off, s[0:3], s32 offset:668 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:672 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:676 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:680 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:684 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v57, off, s[0:3], s32 offset:688 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(46)
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:692 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:608 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(45)
-; GFX9-NEXT: buffer_store_dword v59, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:696 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v60, off, s[0:3], s32 offset:536 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:540 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:544 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:700 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:552 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:556 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:560 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:564 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:568 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:572 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:576 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:580 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v49, off, s[0:3], s32 offset:584 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:588 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:592 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:596 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v53, off, s[0:3], s32 offset:600 ; 4-byte Folded Spill
-; GFX9-NEXT: s_waitcnt vmcnt(43)
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:604 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:524 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(41)
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(41)
+; GFX9-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(39)
+; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(39)
+; GFX9-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(37)
+; GFX9-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(37)
+; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(35)
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(35)
+; GFX9-NEXT: buffer_store_dword v52, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(33)
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:656 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(33)
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:660 ; 4-byte Folded Spill
+; GFX9-NEXT: s_waitcnt vmcnt(32)
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:528 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:532 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB75_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: v_perm_b32 v11, s6, v15, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: v_perm_b32 v12, v52, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_perm_b32 v13, v54, v53, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX9-NEXT: v_perm_b32 v13, v48, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_perm_b32 v14, v50, v49, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX9-NEXT: v_perm_b32 v14, v36, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_perm_b32 v15, v38, v37, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX9-NEXT: v_perm_b32 v15, v32, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v16, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
-; GFX9-NEXT: v_perm_b32 v16, v60, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_perm_b32 v17, v62, v61, s4
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX9-NEXT: v_perm_b32 v17, v59, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_perm_b32 v18, v41, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v17, v18, v17
-; GFX9-NEXT: v_perm_b32 v18, v57, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_perm_b32 v19, v42, v58, s4
-; GFX9-NEXT: v_or_b32_e32 v18, v19, v18
-; GFX9-NEXT: v_perm_b32 v19, v45, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX9-NEXT: v_perm_b32 v20, v56, v47, s4
-; GFX9-NEXT: v_or_b32_e32 v19, v20, v19
-; GFX9-NEXT: v_perm_b32 v20, v44, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX9-NEXT: v_perm_b32 v21, v46, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v20, v21, v20
-; GFX9-NEXT: v_perm_b32 v21, v31, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX9-NEXT: v_perm_b32 v22, v24, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v21, v22, v21
-; GFX9-NEXT: v_perm_b32 v22, v28, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX9-NEXT: v_perm_b32 v23, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v22, v23, v22
-; GFX9-NEXT: v_perm_b32 v23, v25, v63, s4
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
-; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX9-NEXT: v_perm_b32 v24, v27, v55, s4
-; GFX9-NEXT: v_or_b32_e32 v23, v24, v23
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v45, v26
+; GFX9-NEXT: v_perm_b32 v12, v14, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: v_perm_b32 v12, v42, v41, s4
+; GFX9-NEXT: v_perm_b32 v13, v40, v54, s4
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX9-NEXT: v_perm_b32 v13, v55, v53, s4
+; GFX9-NEXT: v_perm_b32 v14, v52, v50, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_perm_b32 v14, v51, v49, s4
+; GFX9-NEXT: v_perm_b32 v15, v48, v38, s4
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX9-NEXT: v_perm_b32 v15, v39, v37, s4
+; GFX9-NEXT: v_perm_b32 v16, v35, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v16, 16, v15
+; GFX9-NEXT: v_perm_b32 v16, v36, v34, s4
+; GFX9-NEXT: v_perm_b32 v17, v32, v17, s4
+; GFX9-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX9-NEXT: v_perm_b32 v17, v33, v63, s4
+; GFX9-NEXT: v_perm_b32 v18, v61, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: v_perm_b32 v18, v62, v60, s4
+; GFX9-NEXT: v_perm_b32 v19, v58, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX9-NEXT: v_perm_b32 v19, v59, v57, s4
+; GFX9-NEXT: v_perm_b32 v20, v47, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; GFX9-NEXT: v_perm_b32 v20, v56, v46, s4
+; GFX9-NEXT: v_perm_b32 v21, v44, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX9-NEXT: v_perm_b32 v21, v45, v43, s4
+; GFX9-NEXT: v_perm_b32 v22, v31, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v21, v22, 16, v21
+; GFX9-NEXT: v_perm_b32 v22, v30, v29, s4
+; GFX9-NEXT: v_perm_b32 v23, v28, v23, s4
+; GFX9-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX9-NEXT: v_perm_b32 v23, v27, v26, s4
+; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
+; GFX9-NEXT: v_lshl_or_b32 v23, v24, 16, v23
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: v_mov_b32_e32 v44, v45
+; GFX9-NEXT: v_mov_b32_e32 v54, v53
+; GFX9-NEXT: v_mov_b32_e32 v40, v55
+; GFX9-NEXT: v_mov_b32_e32 v50, v49
+; GFX9-NEXT: v_mov_b32_e32 v52, v51
+; GFX9-NEXT: v_mov_b32_e32 v38, v37
+; GFX9-NEXT: v_mov_b32_e32 v48, v39
+; GFX9-NEXT: v_mov_b32_e32 v35, v34
+; GFX9-NEXT: v_mov_b32_e32 v32, v63
+; GFX9-NEXT: v_mov_b32_e32 v61, v60
+; GFX9-NEXT: v_mov_b32_e32 v58, v57
; GFX9-NEXT: v_mov_b32_e32 v47, v46
-; GFX9-NEXT: v_mov_b32_e32 v57, v56
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v25, v24, s4
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v24, 16, v24
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: v_or_b32_e32 v24, v25, v24
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v26, v25, s4
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: v_or_b32_e32 v25, v26, v25
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v25, v26, 16, v25
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v27, v26, s4
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v26, 16, v26
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: v_or_b32_e32 v26, v27, v26
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v28, v27, s4
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: v_or_b32_e32 v27, v28, v27
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v29, v28, s4
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v28, 16, v28
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v28, v29, v28
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v30, v29, s4
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v29, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: v_or_b32_e32 v29, v30, v29
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v31, v30, s4
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v30, 16, v30
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: v_or_b32_e32 v30, v31, v30
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v43, v31, s4
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v31, 16, v31
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v45, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v43, v46, v43, s4
-; GFX9-NEXT: v_or_b32_e32 v31, v43, v31
+; GFX9-NEXT: v_perm_b32 v43, v45, v43, s4
+; GFX9-NEXT: v_lshl_or_b32 v31, v43, 16, v31
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: s_branch .LBB75_3
; GFX9-NEXT: .LBB75_2:
-; GFX9-NEXT: v_mov_b32_e32 v57, v56
+; GFX9-NEXT: v_mov_b32_e32 v40, v55
+; GFX9-NEXT: v_mov_b32_e32 v54, v53
+; GFX9-NEXT: v_mov_b32_e32 v52, v51
+; GFX9-NEXT: v_mov_b32_e32 v50, v49
+; GFX9-NEXT: v_mov_b32_e32 v48, v39
+; GFX9-NEXT: v_mov_b32_e32 v38, v37
+; GFX9-NEXT: v_mov_b32_e32 v35, v34
+; GFX9-NEXT: v_mov_b32_e32 v32, v63
+; GFX9-NEXT: v_mov_b32_e32 v61, v60
+; GFX9-NEXT: v_mov_b32_e32 v58, v57
; GFX9-NEXT: v_mov_b32_e32 v47, v46
-; GFX9-NEXT: v_mov_b32_e32 v45, v26
-; GFX9-NEXT: v_mov_b32_e32 v44, v24
+; GFX9-NEXT: v_mov_b32_e32 v44, v45
; GFX9-NEXT: s_mov_b64 s[4:5], -1
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; GFX9-NEXT: .LBB75_3: ; %Flow
-; GFX9-NEXT: v_mov_b32_e32 v43, v44
-; GFX9-NEXT: v_mov_b32_e32 v44, v45
-; GFX9-NEXT: v_mov_b32_e32 v45, v47
-; GFX9-NEXT: v_mov_b32_e32 v46, v57
-; GFX9-NEXT: buffer_load_dword v47, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v57, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:532 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:528 ; 4-byte Folded Reload
; GFX9-NEXT: s_andn2_b64 vcc, exec, s[4:5]
+; GFX9-NEXT: v_mov_b32_e32 v43, v44
+; GFX9-NEXT: v_mov_b32_e32 v44, v47
+; GFX9-NEXT: v_mov_b32_e32 v47, v32
; GFX9-NEXT: s_cbranch_vccnz .LBB75_5
; GFX9-NEXT: ; %bb.4: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -122876,250 +122151,258 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:700 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:696 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:692 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v10, 0x300, v10
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v10, v10, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:684 ; 4-byte Folded Reload
-; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_add_u32_e32 v16, 3, v32
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; GFX9-NEXT: s_add_i32 s6, s6, 3
-; GFX9-NEXT: s_waitcnt vmcnt(10)
-; GFX9-NEXT: v_add_u32_e32 v14, 3, v48
-; GFX9-NEXT: v_perm_b32 v14, v14, v39, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:680 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:672 ; 4-byte Folded Reload
-; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v15, 3, v36
-; GFX9-NEXT: v_perm_b32 v15, v15, v35, s5
-; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s5
-; GFX9-NEXT: v_add_u32_e32 v17, 3, v60
-; GFX9-NEXT: s_waitcnt vmcnt(16)
-; GFX9-NEXT: v_perm_b32 v17, v17, v18, s5
-; GFX9-NEXT: v_add_u32_e32 v18, 3, v57
-; GFX9-NEXT: s_waitcnt vmcnt(15)
-; GFX9-NEXT: v_perm_b32 v18, v18, v19, s5
-; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:688 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(15)
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:604 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:596 ; 4-byte Folded Reload
+; GFX9-NEXT: s_mov_b32 s5, 0xc0c0004
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:588 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:580 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:568 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:552 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:536 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(20)
; GFX9-NEXT: v_perm_b32 v11, s6, v12, v11
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:676 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v11, 0x300, v11
-; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_sdwa v17, v17, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_sdwa v18, v18, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:668 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v12, 3, v12
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s5
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:660 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v12, v12, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v11, v11, v12 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v12, 3, v54
-; GFX9-NEXT: v_add_u32_e32 v13, 3, v52
-; GFX9-NEXT: v_perm_b32 v12, v12, v53, s5
-; GFX9-NEXT: v_perm_b32 v13, v13, v51, s5
+; GFX9-NEXT: v_add_u32_e32 v12, 3, v34
+; GFX9-NEXT: v_perm_b32 v12, v12, v41, s5
; GFX9-NEXT: v_add_u32_e32 v12, 0x300, v12
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v13, 3, v13
+; GFX9-NEXT: v_perm_b32 v13, v13, v14, s5
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:652 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v13, v13, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v12, v12, v13 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v13, 3, v50
-; GFX9-NEXT: v_perm_b32 v13, v13, v49, s5
+; GFX9-NEXT: v_add_u32_e32 v13, 3, v40
+; GFX9-NEXT: v_perm_b32 v13, v13, v54, s5
; GFX9-NEXT: v_add_u32_e32 v13, 0x300, v13
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v14, 3, v14
+; GFX9-NEXT: v_perm_b32 v14, v14, v15, s5
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v14, v14, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v13, v13, v14 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v14, 3, v38
-; GFX9-NEXT: v_perm_b32 v14, v14, v37, s5
+; GFX9-NEXT: v_add_u32_e32 v14, 3, v52
+; GFX9-NEXT: v_perm_b32 v14, v14, v50, s5
; GFX9-NEXT: v_add_u32_e32 v14, 0x300, v14
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v15, 3, v15
+; GFX9-NEXT: v_perm_b32 v15, v15, v16, s5
+; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v15, v15, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v14, v14, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v15, 3, v34
-; GFX9-NEXT: v_perm_b32 v15, v15, v33, s5
+; GFX9-NEXT: v_add_u32_e32 v15, 3, v48
+; GFX9-NEXT: v_perm_b32 v15, v15, v38, s5
; GFX9-NEXT: v_add_u32_e32 v15, 0x300, v15
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v16, 3, v16
+; GFX9-NEXT: v_perm_b32 v16, v16, v17, s5
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v16, v16, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v15, v15, v16 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v16, 3, v62
-; GFX9-NEXT: v_perm_b32 v16, v16, v61, s5
+; GFX9-NEXT: v_add_u32_e32 v16, 3, v36
+; GFX9-NEXT: v_perm_b32 v16, v16, v35, s5
; GFX9-NEXT: v_add_u32_e32 v16, 0x300, v16
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v17, 3, v17
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s5
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v17, v17, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v16, v16, v17 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v17, 3, v41
-; GFX9-NEXT: v_perm_b32 v17, v17, v40, s5
+; GFX9-NEXT: v_add_u32_e32 v17, 3, v33
+; GFX9-NEXT: v_perm_b32 v17, v17, v47, s5
; GFX9-NEXT: v_add_u32_e32 v17, 0x300, v17
+; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_add_u32_e32 v18, 3, v18
+; GFX9-NEXT: v_perm_b32 v18, v18, v19, s5
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_sdwa v18, v18, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v17, v17, v18 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v18, 3, v42
-; GFX9-NEXT: v_perm_b32 v18, v18, v47, s5
+; GFX9-NEXT: v_add_u32_e32 v18, 3, v62
+; GFX9-NEXT: v_perm_b32 v18, v18, v61, s5
; GFX9-NEXT: v_add_u32_e32 v18, 0x300, v18
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_add_u32_e32 v19, 3, v19
+; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:592 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v19, v19, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v18, v18, v19 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v19, 3, v46
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v19, v19, v20, s5
-; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:664 ; 4-byte Folded Reload
+; GFX9-NEXT: v_add_u32_e32 v19, 3, v59
+; GFX9-NEXT: v_perm_b32 v19, v19, v58, s5
; GFX9-NEXT: v_add_u32_e32 v19, 0x300, v19
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v20, 3, v20
; GFX9-NEXT: v_perm_b32 v20, v20, v21, s5
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:656 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:584 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v20, v20, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v19, v19, v20 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_add_u32_e32 v20, 3, v45
+; GFX9-NEXT: v_add_u32_e32 v20, 3, v56
; GFX9-NEXT: v_perm_b32 v20, v20, v44, s5
; GFX9-NEXT: v_add_u32_e32 v20, 0x300, v20
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v21, 3, v21
; GFX9-NEXT: v_perm_b32 v21, v21, v22, s5
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:576 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_sdwa v21, v21, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v20, v20, v21 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_add_u32_e32 v21, 3, v43
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v21, v21, v22, s5
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:572 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v21, 0x300, v21
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: v_perm_b32 v22, v22, v23, s5
; GFX9-NEXT: v_add_u32_sdwa v22, v22, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v21, v21, v22 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:564 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:560 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v22, 3, v22
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v22, v22, v23, s5
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:556 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v22, 0x300, v22
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: v_perm_b32 v23, v23, v24, s5
; GFX9-NEXT: v_add_u32_sdwa v23, v23, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v22, v22, v23 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:548 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:544 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v23, 3, v23
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v23, v23, v24, s5
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:612 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:540 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v23, 0x300, v23
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v24, 3, v24
; GFX9-NEXT: v_perm_b32 v24, v24, v25, s5
; GFX9-NEXT: v_add_u32_sdwa v24, v24, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v23, v23, v24 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:524 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v24, 3, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v24, v24, v25, s5
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:516 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:520 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v24, 0x300, v24
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v25, 3, v25
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s5
; GFX9-NEXT: v_add_u32_sdwa v25, v25, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v24, v24, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v25, 3, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v25, v25, v26, s5
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v25, 0x300, v25
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v26, 3, v26
; GFX9-NEXT: v_perm_b32 v26, v26, v27, s5
; GFX9-NEXT: v_add_u32_sdwa v26, v26, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v25, v25, v26 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v26, 3, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v26, v26, v27, s5
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v26, 0x300, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v27, 3, v27
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s5
; GFX9-NEXT: v_add_u32_sdwa v27, v27, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v26, v26, v27 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v27, 3, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v27, v27, v28, s5
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v27, 0x300, v27
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v28, 3, v28
; GFX9-NEXT: v_perm_b32 v28, v28, v29, s5
; GFX9-NEXT: v_add_u32_sdwa v28, v28, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v27, v27, v28 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v28, 3, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v28, v28, v29, s5
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v28, 0x300, v28
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v29, 3, v29
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s5
; GFX9-NEXT: v_add_u32_sdwa v29, v29, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v28, v28, v29 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v29, 3, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v29, v29, v30, s5
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v29, 0x300, v29
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v30, 3, v30
; GFX9-NEXT: v_perm_b32 v30, v30, v31, s5
; GFX9-NEXT: v_add_u32_sdwa v30, v30, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v29, v29, v30 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v30, 3, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v30, v30, v31, s5
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v30, 0x300, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v31, 3, v31
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s5
; GFX9-NEXT: v_add_u32_sdwa v31, v31, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v30, v30, v31 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v31, 3, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v31, v31, v32, s5
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v31, 0x300, v31
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v32, 3, v32
@@ -123149,10 +122432,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v16f64_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
-; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
@@ -123274,149 +122554,109 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB75_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s2, s3, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s40, s15, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v163, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v147, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v6, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s14, s13, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s45, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v55, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v132, v130, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v129, v118, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v114, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s12, s11, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v101, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v99, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v83, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v14, 16, v13
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v99, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, v23, v24
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v103, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v101, v97, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, v23, v24
-; GFX11-TRUE16-NEXT: v_perm_b32 v24, v83, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, v29, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v65, v53, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v28
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v40, v41
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v181, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v67, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v66, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v52, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v167, v166, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v165, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v49, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v183, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v34, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v150, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v145, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v135, v131, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v21, 16, v20
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v119, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v103, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v102, v98, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
+; GFX11-TRUE16-NEXT: v_perm_b32 v24, v96, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v85, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v25, v27, 16, v26
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v70, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v65, v53, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v55, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v31, 16, v30
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v39, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v40, 16, v183
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB75_3
; GFX11-TRUE16-NEXT: .LBB75_2: ; %cmp.true
@@ -123711,9 +122951,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v36, v35
; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v33, v32
; GFX11-TRUE16-NEXT: .LBB75_3: ; %end
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB75_4:
@@ -123723,10 +122961,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v16f64_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
-; GFX11-FAKE16-NEXT: ; meta instruction
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v32, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v34, off, s32 offset:308
@@ -123848,149 +123083,109 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB75_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v144, v131, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s18, s19, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v102, v98, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v85, v82, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v70, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s2, s3, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s0, s1, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s16, s17, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s26, s27, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s74, s73, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v3, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s24, s25, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s20, s21, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s72, s63, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s56, s47, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v4, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s13, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s40, s15, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s58, s57, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(5)
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v180, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v164, v160, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v163, v151, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v147, v135, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s26, s27, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s24, s25, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s28, s29, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s74, s73, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s62, s61, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v6, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s72, s63, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s40, s15, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s14, s13, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v14, s6, s5, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v7, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s46, s45, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s60, s59, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v64, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v40, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v8, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s42, s41, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s44, s43, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v9, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v12, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v146, v134, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s44, s43, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v132, v130, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v129, v118, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v117, v113, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v114, v112, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v12, 16, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, s12, s11, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s8, s7, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s9, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v101, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v100, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v84, v80, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v83, v71, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v14, 16, v13
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v147, v135, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, v19, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, v21, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v100, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, v23, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v103, v99, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v24, 16, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v101, v97, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, v23, v24
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, v25, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, v25, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v67, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v27, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v49, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v29, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v29, v65, v53, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v30, 16, v31
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v52, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v183, 16, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v29, v30
-; GFX11-FAKE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-FAKE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-FAKE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v31, v183
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v40, v41
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s4, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v182, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v181, v177, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v67, v55, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v66, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v52, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v167, v166, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v165, v162, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v49, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v183, v37, v33, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v40, v34, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v161, v149, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v150, v148, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v19, 16, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v145, v133, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v144, v131, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v19, 16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v21, 16, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v128, v116, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v119, v115, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v21, 16, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v23, 16, v22
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v103, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v102, v98, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v23, 16, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v25, 16, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v96, v86, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v85, v82, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v25, 16, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v27, 16, v26
+; GFX11-FAKE16-NEXT: v_perm_b32 v26, v81, v69, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v70, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v27, 16, v26
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v65, v53, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v64, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v29, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v31, 16, v30
+; GFX11-FAKE16-NEXT: v_perm_b32 v30, v48, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v39, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v31, 16, v30
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v40, 16, v183
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB75_3
; GFX11-FAKE16-NEXT: .LBB75_2: ; %cmp.true
@@ -124285,9 +123480,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v36, v35
; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v33, v32
; GFX11-FAKE16-NEXT: .LBB75_3: ; %end
-; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB75_4:
@@ -147679,7 +146872,6 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_readfirstlane_b32 s47, v7
; GFX9-NEXT: v_readfirstlane_b32 s59, v6
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332
-; GFX9-NEXT: v_readfirstlane_b32 s42, v13
; GFX9-NEXT: v_readfirstlane_b32 s74, v30
; GFX9-NEXT: v_readfirstlane_b32 s44, v29
; GFX9-NEXT: v_readfirstlane_b32 s56, v28
@@ -147697,6 +146889,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_readfirstlane_b32 s58, v16
; GFX9-NEXT: v_readfirstlane_b32 s73, v15
; GFX9-NEXT: v_readfirstlane_b32 s75, v14
+; GFX9-NEXT: v_readfirstlane_b32 s42, v13
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:324
@@ -147717,26 +146910,28 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:296
+; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:296
; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:292
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:288
+; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:288
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:280
-; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:276
+; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:280
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:276
; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:272
; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:268
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:264
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:260
-; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:256
-; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:252
-; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:248
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:244
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240
+; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:264
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:260
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:256
+; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:252
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:240
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:236
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232
@@ -147747,7 +146942,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
@@ -147759,7 +146954,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
@@ -147773,13 +146968,11 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:192
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v13, off, s[0:3], s32 offset:188
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:188
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:184
; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:180
; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:176
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:172
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:172
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:168
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:164
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:160
@@ -147852,23 +147045,23 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB89_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -147917,38 +147110,37 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s73
; GFX9-NEXT: v_perm_b32 v7, s75, v7, v8
-; GFX9-NEXT: v_mov_b32_e32 v63, v33
; GFX9-NEXT: v_mov_b32_e32 v33, v9
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_perm_b32 v9, s58, v9, v8
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v10
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
; GFX9-NEXT: v_perm_b32 v10, s74, v12, v8
-; GFX9-NEXT: v_or_b32_sdwa v9, v11, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v18
-; GFX9-NEXT: v_or_b32_sdwa v9, v22, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v13
-; GFX9-NEXT: v_or_b32_sdwa v10, v15, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v22
+; GFX9-NEXT: v_lshl_or_b32 v9, v18, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v15
+; GFX9-NEXT: v_lshl_or_b32 v10, v13, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_lshl_or_b32 v12, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v14
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v17
; GFX9-NEXT: v_perm_b32 v10, v26, v21, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v17, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v14, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v13, v9, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v25
-; GFX9-NEXT: v_or_b32_sdwa v9, v30, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v16
-; GFX9-NEXT: v_or_b32_sdwa v10, v20, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v30
+; GFX9-NEXT: v_lshl_or_b32 v9, v25, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v20
+; GFX9-NEXT: v_lshl_or_b32 v10, v16, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_lshl_or_b32 v14, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v19
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v24
; GFX9-NEXT: v_perm_b32 v10, v35, v29, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v24, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v19, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v15, v9, 16, v10
; GFX9-NEXT: v_perm_b32 v9, v39, v34, s4
@@ -147975,140 +147167,141 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_perm_b32 v10, v56, v44, s4
; GFX9-NEXT: v_lshl_or_b32 v21, v10, 16, v9
-; GFX9-NEXT: v_perm_b32 v9, v58, v42, s4
+; GFX9-NEXT: v_perm_b32 v9, v62, v42, s4
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_perm_b32 v10, v59, v47, s4
; GFX9-NEXT: v_lshl_or_b32 v22, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; GFX9-NEXT: v_mov_b32_e32 v41, v46
; GFX9-NEXT: v_mov_b32_e32 v50, v32
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v51, v49
-; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v41, v46
; GFX9-NEXT: v_mov_b32_e32 v39, v52
; GFX9-NEXT: v_mov_b32_e32 v52, v38
; GFX9-NEXT: v_mov_b32_e32 v34, v37
; GFX9-NEXT: v_mov_b32_e32 v37, v31
-; GFX9-NEXT: s_lshl_b32 s5, s13, 8
-; GFX9-NEXT: s_lshl_b32 s77, s9, 8
-; GFX9-NEXT: s_lshl_b32 s78, s44, 8
-; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(9)
-; GFX9-NEXT: v_perm_b32 v9, v9, v10, s4
+; GFX9-NEXT: s_waitcnt vmcnt(8)
+; GFX9-NEXT: v_perm_b32 v9, v58, v9, s4
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v32, v58, s4
; GFX9-NEXT: v_lshl_or_b32 v23, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v49
-; GFX9-NEXT: v_or_b32_sdwa v10, v24, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX9-NEXT: v_lshl_or_b32 v24, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v35
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v49, 8, v10
+; GFX9-NEXT: v_lshl_or_b32 v24, v10, 16, v9
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v25, v10, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v35, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v25, v9, 16, v10
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v33
-; GFX9-NEXT: v_or_b32_sdwa v10, v62, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v33, v46
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; GFX9-NEXT: v_or_b32_sdwa v9, v43, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v43
+; GFX9-NEXT: v_lshl_or_b32 v9, v54, 8, v9
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; GFX9-NEXT: v_mov_b32_e32 v54, v48
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v26, 8, v10
; GFX9-NEXT: v_lshl_or_b32 v26, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v48
-; GFX9-NEXT: v_perm_b32 v10, v63, v61, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v61
+; GFX9-NEXT: v_lshl_or_b32 v9, v33, 8, v9
+; GFX9-NEXT: v_mov_b32_e32 v33, v46
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v10, v10, v48, s4
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v27, v9, 16, v10
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v54, v61
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v63
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_mov_b32_e32 v48, v63
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GFX9-NEXT: v_or_b32_sdwa v10, v28, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v28, 8, v10
; GFX9-NEXT: v_lshl_or_b32 v28, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v36, v10, s4
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v29, v9, 16, v10
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v43
-; GFX9-NEXT: v_or_b32_sdwa v9, v62, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v62
+; GFX9-NEXT: v_lshl_or_b32 v9, v43, 8, v9
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GFX9-NEXT: v_or_b32_sdwa v10, v30, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v30, 8, v10
; GFX9-NEXT: v_lshl_or_b32 v30, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v38
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v46
; GFX9-NEXT: v_perm_b32 v10, v63, v61, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v46, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v38, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX9-NEXT: s_and_b32 s4, s40, 0xff
; GFX9-NEXT: v_lshl_or_b32 v31, v9, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v9, s57
+; GFX9-NEXT: s_lshl_b32 s5, s13, 8
; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
-; GFX9-NEXT: s_and_b32 s4, s40, 0xff
-; GFX9-NEXT: s_or_b32 s4, s4, s5
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX9-NEXT: v_lshl_or_b32 v9, s4, 16, v8
; GFX9-NEXT: s_and_b32 s4, s76, 0xff
+; GFX9-NEXT: v_lshl_or_b32 v9, s5, 16, v8
; GFX9-NEXT: s_lshl_b32 s5, s41, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s11, 0xff
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
+; GFX9-NEXT: s_or_b32 s5, s5, s4
+; GFX9-NEXT: s_and_b32 s4, s11, 0xff
+; GFX9-NEXT: s_lshl_b32 s77, s9, 8
+; GFX9-NEXT: s_or_b32 s77, s77, s4
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s77
; GFX9-NEXT: s_and_b32 s5, s72, 0xff
; GFX9-NEXT: s_lshl_b32 s77, s62, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_and_b32 s77, s56, 0xff
-; GFX9-NEXT: s_or_b32 s77, s77, s78
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s77
+; GFX9-NEXT: s_or_b32 s77, s77, s5
+; GFX9-NEXT: s_and_b32 s5, s56, 0xff
+; GFX9-NEXT: s_lshl_b32 s78, s44, 8
+; GFX9-NEXT: s_or_b32 s78, s78, s5
+; GFX9-NEXT: s_pack_ll_b32_b16 s5, s77, s78
; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: v_mov_b32_e32 v10, s5
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: v_mov_b32_e32 v63, v36
; GFX9-NEXT: s_branch .LBB89_3
; GFX9-NEXT: .LBB89_2:
-; GFX9-NEXT: v_mov_b32_e32 v54, v61
+; GFX9-NEXT: v_mov_b32_e32 v54, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v32
; GFX9-NEXT: v_mov_b32_e32 v51, v49
; GFX9-NEXT: v_mov_b32_e32 v39, v52
@@ -148152,7 +147345,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: s_add_i32 s74, s74, 3
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_add_i32 s72, s72, 3
; GFX9-NEXT: s_add_i32 s56, s56, 3
; GFX9-NEXT: s_add_i32 s60, s60, 3
@@ -148181,76 +147374,75 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; GFX9-NEXT: v_add_u32_e32 v0, 3, v63
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v38, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v62, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v54, s4
; GFX9-NEXT: v_add_u32_e32 v63, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v31, 0x300, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v30, 0x300, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v35, s4
@@ -148260,12 +147452,12 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v28, 0x300, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v49, s4
; GFX9-NEXT: v_add_u32_e32 v27, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
@@ -148273,9 +147465,9 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_add_u32_e32 v0, 3, v32
; GFX9-NEXT: v_perm_b32 v0, v0, v58, s4
; GFX9-NEXT: v_add_u32_e32 v25, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v32, s23
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v42, s4
@@ -148309,18 +147501,18 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_and_b32_e32 v23, 0xffff, v26
; GFX9-NEXT: v_lshl_or_b32 v23, v25, 16, v23
; GFX9-NEXT: v_and_b32_e32 v25, 0xffff, v30
-; GFX9-NEXT: v_lshl_or_b32 v25, v29, 16, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v24, 0xffff, v28
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v25, v29, 16, v25
; GFX9-NEXT: v_lshl_or_b32 v24, v27, 16, v24
; GFX9-NEXT: v_and_b32_e32 v27, 0xffff, v63
; GFX9-NEXT: v_and_b32_e32 v19, 0xffff, v19
; GFX9-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX9-NEXT: v_lshl_or_b32 v19, v52, 16, v19
; GFX9-NEXT: v_lshl_or_b32 v20, v49, 16, v20
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
@@ -148332,6 +147524,10 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX9-NEXT: v_lshl_or_b32 v18, v37, 16, v18
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; GFX9-NEXT: v_and_b32_e32 v28, 0xffff, v38
+; GFX9-NEXT: v_lshl_or_b32 v28, v62, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -148350,7 +147546,7 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v16, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -148501,12 +147697,12 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_and_b32_e32 v32, 0xffff, v54
; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v32
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_and_b32_e32 v29, 0xffff, v29
; GFX9-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: v_lshl_or_b32 v26, v31, 16, v26
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v29, 0xffff, v29
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v0, s18, v34, v0
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
@@ -148518,8 +147714,6 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
-; GFX9-NEXT: v_and_b32_e32 v28, 0xffff, v38
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v33
; GFX9-NEXT: v_lshl_or_b32 v2, v61, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v3, v60, 16, v3
@@ -148531,10 +147725,8 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX9-NEXT: v_lshl_or_b32 v9, v46, 16, v9
; GFX9-NEXT: v_lshl_or_b32 v10, v45, 16, v10
; GFX9-NEXT: v_lshl_or_b32 v11, v44, 16, v11
-; GFX9-NEXT: v_lshl_or_b32 v28, v62, 16, v28
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_and_b32_e32 v30, 0xffff, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v30, 0xffff, v30
; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -148563,10 +147755,12 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v64bf16_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
+; GFX11-TRUE16-NEXT: s_clause 0x2 ; 12-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:328
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:324
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:320
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:308
@@ -148687,156 +147881,136 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB89_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s63, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s57, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xff, v117
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s76
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s56, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s8, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s11, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s78
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v13, 0xff, v68
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s41, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s79
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s10, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v164
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s46, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v114
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v64, 8, v24
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v131
+; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s47, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s78
+; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s13, 8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v37, 8, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xff, v38
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v119, 8, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v144
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v70, 8, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v82, 8, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v167
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s76
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v53, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v66, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s88, s78
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v71, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v32, 8, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v69, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v87, 8, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v10.l
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v29, 0xff, v149
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v84, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v128, 8, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v162
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v98, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v113, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v19.l
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v118, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v179
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v21.l
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v101, 8, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v132, 8, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v23.l
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v86, 8, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v150, 8, v30
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v50
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v160
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v165
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xff, v166
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v33, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v183, v102, 8, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v41, v129, 8, v30
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v42, v133, 8, v31
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v39, 8, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v178, 8, v40
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, s79
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s77
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v29.h, v183.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v41.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v42.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB89_3
; GFX11-TRUE16-NEXT: .LBB89_2: ; %cmp.true
@@ -149069,9 +148243,10 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v129.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.h, v133.l
; GFX11-TRUE16-NEXT: .LBB89_3: ; %end
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-TRUE16-NEXT: s_clause 0x2 ; 12-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:328
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB89_4:
@@ -149082,7 +148257,10 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v64bf16_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
+; GFX11-FAKE16-NEXT: ; meta instruction
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:308
@@ -149205,193 +148383,174 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s74, 0xff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v33
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v48
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v49
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v96, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v68, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s11, s8, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s7, s5, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s42, s15, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s44, s41, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v9, 16, v10
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s76, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v35, 8, s76
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s14, s10, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s76
; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s43, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-FAKE16-NEXT: s_lshl_b32 s76, s13, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v38
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s78
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v37
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s77, s76
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v33, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v36, 8, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v70, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v53
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v48
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v67, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v113, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v37, 8, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v32, 8, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v9, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v36
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v11, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v50
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v14, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v82, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v13
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v82, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v34, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v14, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v9, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v96, v85, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v71, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v83, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v117
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v146, v128, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v160
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v144
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v10, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v9, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v71, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v16, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v83, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v148
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v9, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v19, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v87, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v135
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v86, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v147, 8, v26
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v162, v145, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v150
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v179, v163, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v116, v103, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v100, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s76, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v132, v129, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s13, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v11, 16, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v113, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v20, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v101, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v11, 16, v22
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v134
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v119
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-FAKE16-NEXT: s_and_b32 s77, s62, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s59, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s45, 8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v24, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v114
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v24, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s63, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s61, 8
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v147
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v182, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v132, v129, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v115, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v22, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v134
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v26, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v133
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v119, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v117, 8, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v26, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v177
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v164
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v131
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s79, 16, v10
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s59, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v114, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v25
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s77
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s45, 8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v144, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v149
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s63, 0xff
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s79, s77
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s61, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v177
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v133, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v151
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v28, v29
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s78
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v164, 8, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v10, 16, v27
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v135, 8, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v176
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v161
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v28, v29
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v179, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v165
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v29, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v178
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v166
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v11, v31
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v161, 8, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v178
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v180
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v165, 8, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v183, v150, 8, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s79, 16, v8
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v40
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v41, v166, 8, v30
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v41, 16, v31
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v183, 16, v40
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB89_3
; GFX11-FAKE16-NEXT: .LBB89_2: ; %cmp.true
@@ -149656,7 +148815,9 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v34
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v35
; GFX11-FAKE16-NEXT: .LBB89_3: ; %end
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
+; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB89_4:
@@ -161065,8 +160226,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: s_cbranch_execnz .LBB91_4
; GFX9-NEXT: .LBB91_2: ; %cmp.true
; GFX9-NEXT: s_and_b32 s46, s45, 0xffff0000
-; GFX9-NEXT: v_mov_b32_e32 v13, 0x40c00000
-; GFX9-NEXT: v_add_f32_e32 v1, s46, v13
+; GFX9-NEXT: v_mov_b32_e32 v12, 0x40c00000
+; GFX9-NEXT: v_add_f32_e32 v1, s46, v12
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
@@ -161075,7 +160236,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX9-NEXT: s_lshl_b32 s45, s45, 16
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v1
-; GFX9-NEXT: v_add_f32_e32 v1, s45, v13
+; GFX9-NEXT: v_add_f32_e32 v1, s45, v12
; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
@@ -161083,21 +160244,21 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: s_and_b32 s45, s44, 0xffff0000
; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v1
-; GFX9-NEXT: v_add_f32_e32 v1, s45, v13
+; GFX9-NEXT: v_add_f32_e32 v1, s45, v12
; GFX9-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX9-NEXT: v_add_u32_e32 v3, v3, v1
-; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
; GFX9-NEXT: s_lshl_b32 s44, s44, 16
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v1
-; GFX9-NEXT: v_add_f32_e32 v1, s44, v13
+; GFX9-NEXT: v_add_f32_e32 v1, s44, v12
; GFX9-NEXT: v_bfe_u32 v3, v1, 16, 1
; GFX9-NEXT: v_add_u32_e32 v3, v3, v1
; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
@@ -161105,10 +160266,10 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: s_and_b32 s44, s43, 0xffff0000
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc
-; GFX9-NEXT: v_add_f32_e32 v3, s44, v13
+; GFX9-NEXT: v_add_f32_e32 v3, s44, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: v_add_u32_e32 v4, v4, v3
; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
@@ -161119,7 +160280,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX9-NEXT: s_lshl_b32 s43, s43, 16
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v3
-; GFX9-NEXT: v_add_f32_e32 v3, s43, v13
+; GFX9-NEXT: v_add_f32_e32 v3, s43, v12
; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1
; GFX9-NEXT: v_add_u32_e32 v4, v4, v3
; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4
@@ -161127,21 +160288,21 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX9-NEXT: s_and_b32 s43, s42, 0xffff0000
; GFX9-NEXT: v_lshl_or_b32 v4, v6, 16, v3
-; GFX9-NEXT: v_add_f32_e32 v3, s43, v13
+; GFX9-NEXT: v_add_f32_e32 v3, s43, v12
; GFX9-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX9-NEXT: v_add_u32_e32 v5, v5, v3
-; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v3
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s42, s42, 16
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v3
-; GFX9-NEXT: v_add_f32_e32 v3, s42, v13
+; GFX9-NEXT: v_add_f32_e32 v3, s42, v12
; GFX9-NEXT: v_bfe_u32 v5, v3, 16, 1
; GFX9-NEXT: v_add_u32_e32 v5, v5, v3
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
@@ -161149,10 +160310,10 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
; GFX9-NEXT: s_and_b32 s42, s41, 0xffff0000
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
-; GFX9-NEXT: v_add_f32_e32 v5, s42, v13
+; GFX9-NEXT: v_add_f32_e32 v5, s42, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v3
; GFX9-NEXT: v_bfe_u32 v6, v5, 16, 1
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX9-NEXT: v_add_u32_e32 v6, v6, v5
; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
@@ -161163,7 +160324,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
; GFX9-NEXT: s_lshl_b32 s41, s41, 16
; GFX9-NEXT: v_lshrrev_b32_e32 v8, 16, v5
-; GFX9-NEXT: v_add_f32_e32 v5, s41, v13
+; GFX9-NEXT: v_add_f32_e32 v5, s41, v12
; GFX9-NEXT: v_bfe_u32 v6, v5, 16, 1
; GFX9-NEXT: v_add_u32_e32 v6, v6, v5
; GFX9-NEXT: v_add_u32_e32 v6, 0x7fff, v6
@@ -161171,21 +160332,21 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX9-NEXT: s_and_b32 s41, s40, 0xffff0000
; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v5
-; GFX9-NEXT: v_add_f32_e32 v5, s41, v13
+; GFX9-NEXT: v_add_f32_e32 v5, s41, v12
; GFX9-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX9-NEXT: v_add_u32_e32 v7, v7, v5
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_add_u32_e32 v7, 0x7fff, v7
; GFX9-NEXT: v_or_b32_e32 v8, 0x400000, v5
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc
; GFX9-NEXT: s_lshl_b32 s40, s40, 16
; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v5
-; GFX9-NEXT: v_add_f32_e32 v5, s40, v13
+; GFX9-NEXT: v_add_f32_e32 v5, s40, v12
; GFX9-NEXT: v_bfe_u32 v7, v5, 16, 1
; GFX9-NEXT: v_add_u32_e32 v7, v7, v5
; GFX9-NEXT: v_add_u32_e32 v7, 0x7fff, v7
@@ -161193,13 +160354,13 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v5, v5
; GFX9-NEXT: s_and_b32 s40, s15, 0xffff0000
; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v8, vcc
-; GFX9-NEXT: v_add_f32_e32 v7, s40, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s40, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v5
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshl_or_b32 v5, v9, 16, v5
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
@@ -161207,7 +160368,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
; GFX9-NEXT: s_lshl_b32 s15, s15, 16
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s15, v13
+; GFX9-NEXT: v_add_f32_e32 v7, s15, v12
; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
@@ -161218,592 +160379,591 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX9-NEXT: s_and_b32 s15, s14, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v11, v10, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s15, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
+; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v7
+; GFX9-NEXT: v_add_f32_e32 v7, s15, v12
+; GFX9-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v9, v9, v7
+; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: v_add_u32_e32 v9, 0x7fff, v9
+; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
; GFX9-NEXT: s_lshl_b32 s14, s14, 16
-; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s14, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v7
+; GFX9-NEXT: v_add_f32_e32 v7, s14, v12
+; GFX9-NEXT: v_bfe_u32 v9, v7, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v9, v9, v7
+; GFX9-NEXT: v_add_u32_e32 v9, 0x7fff, v9
+; GFX9-NEXT: v_or_b32_e32 v10, 0x400000, v7
; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: s_and_b32 s14, s11, 0xffff0000
+; GFX9-NEXT: v_cndmask_b32_e32 v7, v9, v10, vcc
+; GFX9-NEXT: v_add_f32_e32 v9, s14, v12
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
+; GFX9-NEXT: v_bfe_u32 v10, v9, 16, 1
; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX9-NEXT: s_and_b32 s14, s11, 0xffff0000
-; GFX9-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshl_or_b32 v10, v10, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s14, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_add_u32_e32 v10, v10, v9
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshl_or_b32 v7, v11, 16, v7
+; GFX9-NEXT: v_add_u32_e32 v10, 0x7fff, v10
+; GFX9-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
; GFX9-NEXT: s_lshl_b32 s11, s11, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s11, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v9
+; GFX9-NEXT: v_add_f32_e32 v9, s11, v12
+; GFX9-NEXT: v_bfe_u32 v10, v9, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v10, v10, v9
+; GFX9-NEXT: v_add_u32_e32 v10, 0x7fff, v10
+; GFX9-NEXT: v_or_b32_e32 v11, 0x400000, v9
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v10, v11, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_and_b32 s11, s10, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v17, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s11, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v10, v13, 16, v9
+; GFX9-NEXT: v_add_f32_e32 v9, s11, v12
+; GFX9-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v11, v11, v9
+; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; GFX9-NEXT: v_add_u32_e32 v11, 0x7fff, v11
+; GFX9-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
; GFX9-NEXT: s_lshl_b32 s10, s10, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v9
+; GFX9-NEXT: v_add_f32_e32 v9, s10, v12
+; GFX9-NEXT: v_bfe_u32 v11, v9, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v11, v11, v9
+; GFX9-NEXT: v_add_u32_e32 v11, 0x7fff, v11
+; GFX9-NEXT: v_or_b32_e32 v13, 0x400000, v9
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v9, v9
; GFX9-NEXT: s_and_b32 s10, s13, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v16, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_cndmask_b32_e32 v9, v11, v13, vcc
+; GFX9-NEXT: v_add_f32_e32 v11, s10, v12
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 16, v9
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshl_or_b32 v9, v14, 16, v9
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s10, s13, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s10, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s10, s12, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v19, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v16, v15, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s10, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s10, s12, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s10, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s10, s9, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v18, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s10, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s10, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s9, s9, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s9, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s9, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s9, s8, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v23, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s9, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v21, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s9, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s8, s8, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s8, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s8, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s8, s7, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v22, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s8, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v20, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s8, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s7, s7, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s7, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s7, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s7, s6, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v25, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s7, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v25, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s7, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s6, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s17, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v24, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v24, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s17, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s16, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v27, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v27, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s16, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s19, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v26, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v26, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s19, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s18, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v29, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v29, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s18, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s21, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v28, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v28, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s21, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s20, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v53, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v53, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s20, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s23, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v52, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v52, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s23, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s22, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v55, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v55, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s22, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s25, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v54, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v54, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s25, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s24, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v41, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v41, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s24, 16
-; GFX9-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s27, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v40, v12, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v40, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s27, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s26, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v43, v14, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v43, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s26, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s29, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v42, v57, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v42, v60, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s29, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s28, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v45, v56, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v45, v17, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v14, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v14, vcc
; GFX9-NEXT: s_lshl_b32 s6, s28, 16
-; GFX9-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v14, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v17, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s6, s5, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v44, v14, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s6, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v44, v14, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s6, v12
+; GFX9-NEXT: v_bfe_u32 v13, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v13, v13, v11
+; GFX9-NEXT: v_add_u32_e32 v13, 0x7fff, v13
+; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v13, v17, vcc
; GFX9-NEXT: s_lshl_b32 s5, s5, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s5, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v7
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v61
+; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s5, v12
+; GFX9-NEXT: v_bfe_u32 v17, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v17, v17, v11
+; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
+; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX9-NEXT: s_and_b32 s5, s4, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v47, v58, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s5, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
+; GFX9-NEXT: v_lshl_or_b32 v47, v13, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s5, v12
+; GFX9-NEXT: v_bfe_u32 v17, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v17, v17, v11
+; GFX9-NEXT: v_add_u32_e32 v17, 0x7fff, v17
+; GFX9-NEXT: v_or_b32_e32 v18, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v17, v18, vcc
; GFX9-NEXT: s_lshl_b32 s4, s4, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v7
-; GFX9-NEXT: v_add_f32_e32 v7, s4, v13
-; GFX9-NEXT: v_bfe_u32 v8, v7, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v8, v8, v7
-; GFX9-NEXT: v_add_u32_e32 v8, 0x7fff, v8
-; GFX9-NEXT: v_or_b32_e32 v9, 0x400000, v7
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v7, v7
-; GFX9-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v13, 16, v7
-; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v13
-; GFX9-NEXT: v_lshl_or_b32 v46, v59, 16, v7
-; GFX9-NEXT: v_lshrrev_b64 v[7:8], 24, v[24:25]
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[7:8], 24, v[22:23]
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[7:8], 24, v[18:19]
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[7:8], 24, v[16:17]
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[7:8], 24, v[10:11]
-; GFX9-NEXT: v_lshrrev_b64 v[36:37], 24, v[42:43]
-; GFX9-NEXT: v_lshrrev_b64 v[48:49], 24, v[52:53]
+; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v11
+; GFX9-NEXT: v_add_f32_e32 v11, s4, v12
+; GFX9-NEXT: v_bfe_u32 v12, v11, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v12, v12, v11
+; GFX9-NEXT: v_add_u32_e32 v12, 0x7fff, v12
+; GFX9-NEXT: v_or_b32_e32 v17, 0x400000, v11
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v11, v11
+; GFX9-NEXT: v_cndmask_b32_e32 v11, v12, v17, vcc
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[24:25]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[20:21]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 16, v11
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[9:10]
+; GFX9-NEXT: v_and_b32_e32 v11, 0xffff, v12
+; GFX9-NEXT: v_lshl_or_b32 v46, v61, 16, v11
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; GFX9-NEXT: v_lshrrev_b64 v[30:31], 24, v[46:47]
-; GFX9-NEXT: v_lshrrev_b64 v[33:34], 24, v[44:45]
+; GFX9-NEXT: v_lshrrev_b64 v[48:49], 24, v[52:53]
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[7:8]
+; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[44:45]
+; GFX9-NEXT: v_lshrrev_b64 v[34:35], 24, v[42:43]
; GFX9-NEXT: v_lshrrev_b64 v[37:38], 24, v[40:41]
; GFX9-NEXT: v_lshrrev_b64 v[49:50], 24, v[28:29]
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[5:6]
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 8, v24
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v22
; GFX9-NEXT: v_lshrrev_b64 v[38:39], 24, v[54:55]
; GFX9-NEXT: v_lshrrev_b64 v[50:51], 24, v[26:27]
-; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
-; GFX9-NEXT: v_lshrrev_b64 v[31:32], 24, v[3:4]
-; GFX9-NEXT: v_lshrrev_b64 v[34:35], 24, v[1:2]
-; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v28
-; GFX9-NEXT: v_lshrrev_b32_e32 v28, 24, v25
-; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v25
-; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v24, 24, v23
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v32, 24, v47
-; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v47
-; GFX9-NEXT: v_lshrrev_b32_e32 v39, 8, v46
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[32:33], 24, v[3:4]
+; GFX9-NEXT: v_lshrrev_b64 v[35:36], 24, v[1:2]
+; GFX9-NEXT: v_lshrrev_b32_e32 v23, 8, v26
+; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v25
+; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v24, 24, v21
+; GFX9-NEXT: v_lshrrev_b32_e32 v33, 24, v47
+; GFX9-NEXT: v_lshrrev_b32_e32 v39, 8, v47
+; GFX9-NEXT: v_lshrrev_b32_e32 v36, 8, v46
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 24, v45
; GFX9-NEXT: v_lshrrev_b32_e32 v45, 8, v45
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 8, v44
@@ -161813,40 +160973,41 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_lshrrev_b32_e32 v47, 24, v41
; GFX9-NEXT: v_lshrrev_b32_e32 v41, 8, v41
; GFX9-NEXT: v_lshrrev_b32_e32 v40, 8, v40
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v55
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v55
; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v55
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 8, v54
-; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v53
+; GFX9-NEXT: v_lshrrev_b32_e32 v56, 24, v53
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v53
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 8, v52
-; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v29
-; GFX9-NEXT: v_lshrrev_b32_e32 v7, 8, v29
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 24, v27
-; GFX9-NEXT: v_lshrrev_b32_e32 v27, 8, v27
-; GFX9-NEXT: v_lshrrev_b32_e32 v26, 8, v26
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v23, 8, v23
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v18, 8, v18
-; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v17
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v17
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 24, v29
+; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v29
+; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v28
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 24, v27
+; GFX9-NEXT: v_lshrrev_b32_e32 v11, 8, v27
+; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v25, 8, v25
+; GFX9-NEXT: buffer_store_dword v24, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v21
+; GFX9-NEXT: v_lshrrev_b32_e32 v20, 8, v20
+; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v16, 8, v16
-; GFX9-NEXT: v_lshrrev_b32_e32 v28, 24, v11
-; GFX9-NEXT: v_lshrrev_b32_e32 v11, 8, v11
+; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v15
+; GFX9-NEXT: v_lshrrev_b32_e32 v27, 24, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v10, 8, v10
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v28, 24, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 24, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v24, 24, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v3
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v59, 24, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v25, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; GFX9-NEXT: s_branch .LBB91_5
; GFX9-NEXT: .LBB91_3:
; GFX9-NEXT: ; implicit-def: $sgpr46
@@ -161997,22 +161158,24 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: s_branch .LBB91_2
; GFX9-NEXT: .LBB91_4:
+; GFX9-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s28
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s29
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s26
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s27
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s24
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s25
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s22
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s23
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s20
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s21
@@ -162026,73 +161189,75 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s6
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s8
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s9
-; GFX9-NEXT: v_mov_b32_e32 v13, s4
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s12
-; GFX9-NEXT: v_readlane_b32 s4, v62, 0
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s13
-; GFX9-NEXT: v_mov_b32_e32 v59, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 1
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v12, s4
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s10
-; GFX9-NEXT: v_mov_b32_e32 v58, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 2
+; GFX9-NEXT: v_readlane_b32 s4, v62, 0
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s11
-; GFX9-NEXT: v_mov_b32_e32 v14, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 3
+; GFX9-NEXT: v_mov_b32_e32 v61, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 1
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s14
-; GFX9-NEXT: v_mov_b32_e32 v56, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 4
+; GFX9-NEXT: v_mov_b32_e32 v13, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 2
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s15
-; GFX9-NEXT: v_mov_b32_e32 v57, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 5
+; GFX9-NEXT: v_mov_b32_e32 v14, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 3
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 4
+; GFX9-NEXT: v_mov_b32_e32 v60, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 5
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 6
-; GFX9-NEXT: v_mov_b32_e32 v12, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 7
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 7
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 8
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 9
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 10
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 11
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 12
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 13
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 14
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 15
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 16
-; GFX9-NEXT: v_mov_b32_e32 v39, s4
+; GFX9-NEXT: v_mov_b32_e32 v36, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 17
-; GFX9-NEXT: v_mov_b32_e32 v32, s4
+; GFX9-NEXT: v_mov_b32_e32 v33, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 18
-; GFX9-NEXT: v_mov_b32_e32 v35, s4
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 19
; GFX9-NEXT: v_mov_b32_e32 v44, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 20
@@ -162114,153 +161279,148 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_readlane_b32 s4, v62, 28
; GFX9-NEXT: v_mov_b32_e32 v54, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 29
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 30
; GFX9-NEXT: v_mov_b32_e32 v55, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 31
; GFX9-NEXT: v_mov_b32_e32 v52, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 32
-; GFX9-NEXT: v_mov_b32_e32 v21, s4
-; GFX9-NEXT: v_mov_b32_e32 v20, s78
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v56, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 33
+; GFX9-NEXT: v_mov_b32_e32 v53, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 34
+; GFX9-NEXT: v_mov_b32_e32 v57, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 35
+; GFX9-NEXT: v_mov_b32_e32 v18, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 36
+; GFX9-NEXT: v_mov_b32_e32 v58, s4
+; GFX9-NEXT: v_readlane_b32 s4, v62, 37
+; GFX9-NEXT: v_mov_b32_e32 v23, s4
+; GFX9-NEXT: v_mov_b32_e32 v22, s78
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v20, s88
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v22, s88
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v22, s90
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v22, s92
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s81
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s68
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v20, s90
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s80
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s67
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v20, s92
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s71
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s66
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s70
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s65
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s69
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s64
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s40
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s55
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s41
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s54
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s42
-; GFX9-NEXT: v_readlane_b32 s4, v62, 33
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s53
-; GFX9-NEXT: v_mov_b32_e32 v53, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 34
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s43
-; GFX9-NEXT: v_mov_b32_e32 v8, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 35
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s52
-; GFX9-NEXT: v_mov_b32_e32 v60, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 36
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s44
-; GFX9-NEXT: v_mov_b32_e32 v7, s4
-; GFX9-NEXT: v_readlane_b32 s4, v62, 37
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s51
-; GFX9-NEXT: v_mov_b32_e32 v26, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 38
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s45
-; GFX9-NEXT: v_mov_b32_e32 v9, s4
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s52
+; GFX9-NEXT: v_mov_b32_e32 v19, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 39
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s50
-; GFX9-NEXT: v_mov_b32_e32 v27, s4
+; GFX9-NEXT: v_mov_b32_e32 v1, s44
+; GFX9-NEXT: v_mov_b32_e32 v11, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 40
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s49
+; GFX9-NEXT: v_mov_b32_e32 v1, s51
; GFX9-NEXT: v_mov_b32_e32 v28, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 41
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s97
-; GFX9-NEXT: v_mov_b32_e32 v11, s4
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s45
+; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 42
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s99
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s50
; GFX9-NEXT: v_mov_b32_e32 v29, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 43
-; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s48
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v1, s49
; GFX9-NEXT: v_mov_b32_e32 v6, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 44
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s86
+; GFX9-NEXT: v_mov_b32_e32 v1, s97
; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 45
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s96
+; GFX9-NEXT: v_mov_b32_e32 v1, s99
; GFX9-NEXT: v_mov_b32_e32 v24, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 46
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v1, s85
+; GFX9-NEXT: v_mov_b32_e32 v1, s86
; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 47
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 48
-; GFX9-NEXT: v_mov_b32_e32 v20, s94
-; GFX9-NEXT: v_mov_b32_e32 v22, s4
+; GFX9-NEXT: v_mov_b32_e32 v22, s94
+; GFX9-NEXT: v_mov_b32_e32 v59, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 49
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v61, s5
-; GFX9-NEXT: v_mov_b32_e32 v18, s98
-; GFX9-NEXT: v_mov_b32_e32 v19, s39
-; GFX9-NEXT: v_mov_b32_e32 v16, s87
-; GFX9-NEXT: v_mov_b32_e32 v25, s82
-; GFX9-NEXT: v_mov_b32_e32 v17, s84
-; GFX9-NEXT: v_mov_b32_e32 v10, s38
+; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v20, s48
+; GFX9-NEXT: v_mov_b32_e32 v21, s96
+; GFX9-NEXT: v_mov_b32_e32 v15, s98
+; GFX9-NEXT: v_mov_b32_e32 v26, s85
+; GFX9-NEXT: v_mov_b32_e32 v16, s39
+; GFX9-NEXT: v_mov_b32_e32 v9, s87
+; GFX9-NEXT: v_mov_b32_e32 v27, s82
+; GFX9-NEXT: v_mov_b32_e32 v10, s84
+; GFX9-NEXT: v_mov_b32_e32 v7, s38
; GFX9-NEXT: v_mov_b32_e32 v5, s83
; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v30, s46
-; GFX9-NEXT: v_mov_b32_e32 v33, s56
-; GFX9-NEXT: v_mov_b32_e32 v36, s58
+; GFX9-NEXT: v_mov_b32_e32 v31, s56
+; GFX9-NEXT: v_mov_b32_e32 v34, s58
; GFX9-NEXT: v_mov_b32_e32 v37, s60
; GFX9-NEXT: v_mov_b32_e32 v38, s62
; GFX9-NEXT: v_mov_b32_e32 v48, s72
; GFX9-NEXT: v_mov_b32_e32 v49, s74
; GFX9-NEXT: v_mov_b32_e32 v50, s76
-; GFX9-NEXT: v_mov_b32_e32 v20, s30
-; GFX9-NEXT: v_mov_b32_e32 v31, s34
-; GFX9-NEXT: v_mov_b32_e32 v34, s36
+; GFX9-NEXT: v_mov_b32_e32 v22, s30
+; GFX9-NEXT: v_mov_b32_e32 v32, s34
+; GFX9-NEXT: v_mov_b32_e32 v35, s36
; GFX9-NEXT: .LBB91_5: ; %end
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v14, v14, v33, s4
-; GFX9-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v12, v12, v37, s4
-; GFX9-NEXT: v_perm_b32 v36, v57, v36, s4
-; GFX9-NEXT: v_perm_b32 v30, v59, v30, s4
+; GFX9-NEXT: v_perm_b32 v14, v14, v31, s4
+; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v34, v60, v34, s4
+; GFX9-NEXT: v_perm_b32 v30, v61, v30, s4
; GFX9-NEXT: v_readlane_b32 s30, v63, 34
; GFX9-NEXT: v_readlane_b32 s31, v63, 35
; GFX9-NEXT: v_readlane_b32 s99, v63, 33
@@ -162298,300 +161458,278 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v50, v23, v50, s4
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v50, v25, v50, s4
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v33, v33, v34, s4
-; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v31, v31, v35, s4
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v49, v23, v49, s4
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v49, v25, v49, s4
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v31, v34, v31, s4
-; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v32, v35, v32, s4
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v48, v23, v48, s4
-; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v48, v25, v48, s4
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v26, v34, v26, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v34, 16, v50
-; GFX9-NEXT: v_or_b32_e32 v26, v26, v34
-; GFX9-NEXT: buffer_store_dword v26, v0, s[0:3], 0 offen
-; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v38, v23, v38, s4
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v26, v26, v27, s4
-; GFX9-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v23, v35, v23, s4
+; GFX9-NEXT: v_lshl_or_b32 v23, v50, 16, v23
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v9, v27, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v9, v26, v9
-; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v38, v25, v38, s4
+; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v8, v9, v8, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v49
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX9-NEXT: buffer_store_dword v8, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v37, v25, v37, s4
+; GFX9-NEXT: buffer_store_dword v23, v0, s[0:3], 0 offen
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v11, v23, v11, s4
+; GFX9-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v8, v8, v60, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v48
+; GFX9-NEXT: v_perm_b32 v19, v23, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v19, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v11, v11, v57, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v49, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v7, v7, v53, s4
+; GFX9-NEXT: v_perm_b32 v11, v11, v58, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v8, v8, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v38
+; GFX9-NEXT: v_perm_b32 v18, v19, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v18, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v7, v7, v54, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v11, v11, v52, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v48, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v7, v7, v55, s4
+; GFX9-NEXT: v_perm_b32 v11, v11, v53, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v8, v8, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v12
+; GFX9-NEXT: v_perm_b32 v18, v18, v56, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v18, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v7, v7, v40, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v11, v11, v54, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v38, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v7, v7, v41, s4
+; GFX9-NEXT: v_perm_b32 v11, v11, v55, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v8, v8, v47, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v36
+; GFX9-NEXT: v_perm_b32 v17, v18, v17, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v17, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v7, v7, v42, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v11, v11, v40, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v37, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v7, v7, v43, s4
+; GFX9-NEXT: v_perm_b32 v11, v11, v41, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v8, v8, v46, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v14
+; GFX9-NEXT: v_perm_b32 v17, v17, v47, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v17, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v7, v7, v44, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:48
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v8, v56, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX9-NEXT: v_perm_b32 v11, v11, v42, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v34, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:40
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_perm_b32 v11, v11, v43, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v7, v7, v45, s4
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_perm_b32 v7, v13, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v30
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: v_perm_b32 v8, v58, v32, s4
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:56
-; GFX9-NEXT: v_perm_b32 v7, v61, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v46, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v17, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:44
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v11, v11, v44, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v14, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:48
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_perm_b32 v11, v11, v45, s4
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v14, v14, v51, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v14, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:52
+; GFX9-NEXT: v_perm_b32 v11, v12, v36, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v30, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:56
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v12, v13, v33, s4
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v11, v11, v39, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
+; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:60
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v1, v7, v1, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v33
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v7
+; GFX9-NEXT: v_perm_b32 v1, v11, v1, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v31, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:64
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v2, v2, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, v2, v59, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:68
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v31
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v1, v3, s4
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v32, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:72
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v1, v1, v4, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v24, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:76
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v1, v1, v5, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v2, v2, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, v2, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:80
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v1, v1, v6, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v29, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:84
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_perm_b32 v1, v1, v7, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v10, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:88
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v1, v1, v11, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v8, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v28, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:92
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_perm_b32 v1, v1, v9, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:96
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v1, v1, v17, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v10, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v2, v2, v25, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, v2, v27, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:100
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_perm_b32 v1, v1, v15, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:104
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_perm_b32 v1, v1, v16, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v1, v1, v19, s4
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, v2, v26, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:108
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:112
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_perm_b32 v1, v1, v21, s4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:116
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
-; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -162902,27 +162040,27 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v2, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v2, v5, v8 :: v_dual_add_nc_u32 v5, 0x7fff, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s41
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v2
; GFX11-TRUE16-NEXT: v_bfe_u32 v6, v8, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v7, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v39.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v50.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v9 :: v_dual_add_nc_u32 v4, v5, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v6, v8
; GFX11-TRUE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s28
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s29
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v8
@@ -162935,27 +162073,27 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v8, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v4
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v6
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s15
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: s_and_b32 s15, s14, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s14, s14, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v53.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v54.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v9, v10
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v7, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v3, v3, v11 :: v_dual_add_nc_u32 v6, 0x7fff, v6
@@ -162978,20 +162116,20 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: s_and_b32 s13, s12, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s12, s12, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v12, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v10, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v52.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v65.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v8, v10
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_add_nc_u32 v8, v11, v12
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s13
@@ -163015,20 +162153,20 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: s_and_b32 s11, s10, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s10, s10, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v13
; GFX11-TRUE16-NEXT: v_bfe_u32 v13, v14, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 16, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v10, v12, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v64.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v10, v12
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v15 :: v_dual_add_nc_u32 v10, v13, v14
; GFX11-TRUE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s11
@@ -163045,27 +162183,27 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v14, v15
; GFX11-TRUE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v13
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-TRUE16-NEXT: s_and_b32 s9, s8, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s8, s8, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 16, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v9
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v15
; GFX11-TRUE16-NEXT: v_bfe_u32 v15, v16, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v12, v14, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v66.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v67.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v12, v14
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v17 :: v_dual_add_nc_u32 v12, v15, v16
; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s9
@@ -163089,20 +162227,20 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: s_and_b32 s7, s6, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s6, s6, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v11
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v14
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v17
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 16, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v9
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 16, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v9
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v13, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v14, v16, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v70.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 16, v13
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v68.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 16, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, v14, v16
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v11, v11, v19 :: v_dual_add_nc_u32 v14, v17, v18
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s7
@@ -163126,446 +162264,446 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
; GFX11-TRUE16-NEXT: s_and_b32 s5, s4, 0xffff0000
; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 16, v13
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v19
; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s4
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s1, 0xffff0000
-; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 16, v11
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v16, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v20
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v98, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v87.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v97, 16, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v16, v18
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v13, v13, v21 :: v_dual_add_nc_u32 v16, v19, v20
; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s5
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v22, 16, 1
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, 0xffff0000
-; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s1, 0xffff0000
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v21, 16, 1
+; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 16
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v14
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v20, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v17, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v22, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, 0xffff0000
+; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v21 :: v_dual_add_nc_u32 v16, v17, v19
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v20, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v99.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v101, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v18, v20
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v23 :: v_dual_add_nc_u32 v18, v21, v22
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, 0xffff0000
; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v99.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s1
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s3, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v102, 16, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v22, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v20, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v18
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v24 :: v_dual_add_nc_u32 v18, v19, v21
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v22, v23
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, 0xffff0000
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v112.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v113, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v102.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v113.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v87.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, 0xffff0000
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v24 :: v_dual_add_nc_u32 v16, v17, v19
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v23, v22
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v23, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v23
+; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v22, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s2, 16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v101.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v98.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s17, 0xffff0000
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v103.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v24, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v22, v23
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v114, 16, v18
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v25 :: v_dual_add_nc_u32 v18, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v23, v22
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s17, 16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v83.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v25, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v103.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v101.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v112.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s16, 0xffff0000
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v24 :: v_dual_add_nc_u32 v16, v17, v19
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v23, v22
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v23, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v18
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v26 :: v_dual_add_nc_u32 v18, v19, v21
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v22, v25
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v22, 16, 1
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s16, 16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v36.l, v116.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v36.h, v129.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v100.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v97.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v118, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v24 :: v_dual_add_nc_u32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v22, v23
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_bfe_u32 v23, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v117, 16, v18
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v102.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v26, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v19, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v25, v22
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 16, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v25, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s1, s19, 0xffff0000
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v118.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v35.h, v132.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v115.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v35.h, v128.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s18, 0xffff0000
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v24 :: v_dual_add_nc_u32 v16, v17, v19
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v23, v22
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v18
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v26 :: v_dual_add_nc_u32 v18, v19, v21
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v22, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v25
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s26, 16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v84.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v81.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v24, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v97.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v130, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v23 :: v_dual_add_nc_u32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v86.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v117.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v34.h, v130.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v82.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v26, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v96.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v129, 16, v18
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v22 :: v_dual_add_nc_u32 v18, v19, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v26
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v19, v24
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v21, v26
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v21, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s21, 16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v22 :: v_dual_add_nc_u32 v16, v17, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v22 :: v_dual_add_nc_u32 v18, v19, v21
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX11-TRUE16-NEXT: s_and_b32 s0, s21, 0xffff0000
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v19, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v22, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v17 :: v_dual_add_nc_u32 v16, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v25, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 16, v15
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v19 :: v_dual_add_nc_u32 v18, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v25, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v27, v22
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v17
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v16, v24 :: v_dual_add_nc_u32 v15, v17, v23
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v18, v26 :: v_dual_add_nc_u32 v17, v19, v25
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v45.l, v131.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v44.l, v131.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v133, 16, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s20, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s23, 16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 16, v16
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v19 :: v_dual_add_nc_u32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v134, 16, v18
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v21 :: v_dual_add_nc_u32 v18, v19, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
; GFX11-TRUE16-NEXT: s_and_b32 s0, s23, 0xffff0000
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v19, v22
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v21, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s22, 0xffff0000
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v17 :: v_dual_add_nc_u32 v16, 0x7fff, v16
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v19 :: v_dual_add_nc_u32 v18, 0x7fff, v18
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v25, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 16, v15
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v25, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v27, v21
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v22, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 16, v17
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v16, v16, v24 :: v_dual_add_nc_u32 v15, v17, v23
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v18, v18, v26 :: v_dual_add_nc_u32 v17, v19, v25
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v145, 16, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v20
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s22, 16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v18, 16, 1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_bfe_u32 v25, v24, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v20, 16, 1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_bfe_u32 v27, v26, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v17, v18
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v22, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v19, 16, 1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v146, 16, v18
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v22 :: v_dual_add_nc_u32 v18, v19, v20
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v21, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, v25, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, 0x400000, v18
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v17, v19
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x7fff, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, v27, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v160, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v20
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v19, v21
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x7fff, v27
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s25, 16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v15, v15, v16 :: v_dual_add_nc_u32 v16, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, 0x400000, v19
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 16, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v18, v22
+; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v17, v17, v18 :: v_dual_add_nc_u32 v18, 0x7fff, v19
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v161, 16, v17
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v20, v22
; GFX11-TRUE16-NEXT: s_and_b32 s0, s24, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v17, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v22
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v19, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v25, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v150, 16, v16
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, v17, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v149, 16, v18
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v19, v25
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s24, 16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v16, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v15
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v19, v16
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v15, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v18, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v17
; GFX11-TRUE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, v21, v18
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s27, 0xffff0000
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v19, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
+; GFX11-TRUE16-NEXT: v_bfe_u32 v22, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v21
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v151, 16, v19
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s27, 16
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v41.l, v147.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v18, v19, vcc_lo
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v22, v15
-; GFX11-TRUE16-NEXT: v_bfe_u32 v19, v17, 16, 1
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v162.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v20, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v22, v17
+; GFX11-TRUE16-NEXT: v_bfe_u32 v21, v19, 16, 1
; GFX11-TRUE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, 0x400000, v15
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, v19, v17
-; GFX11-TRUE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v15, v16, v18, vcc_lo
-; GFX11-TRUE16-NEXT: v_bfe_u32 v16, v22, 16, 1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x7fff, v19
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v23, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v27, 0x400000, v23
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, v16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v41.h, v161.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v19, v26, vcc_lo
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, 0x400000, v22
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 16, v18
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v20
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, 0x400000, v17
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s26, 0xffff0000
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, v21, v19
+; GFX11-TRUE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v17, v18, v20, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v18, v22, 16, 1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
+; GFX11-TRUE16-NEXT: v_bfe_u32 v20, v25, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, 0x400000, v25
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v22
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.l, v151.l
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v21, v28, vcc_lo
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v21, 0x400000, v22
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, v18, v23
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, 0x400000, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v166, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v16, v16, v19, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v40.l, v150.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v40.h, v163.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v162, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v19, v25, v26, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v47.l, v134.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v47.h, v149.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v46.l, v146.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v27, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v46.h, v160.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v45.h, v145.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v44.l, v135.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v44.h, v148.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 16, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v100.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v114.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v117.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v115.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v28.h, v128.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v119.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v49.h, v133.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.l, v130.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.h, v144.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.l, v162.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v179.h, v176.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, v20, v25
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, 0x400000, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v165, 16, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v167, 16, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v18, v18, v21, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.l, v165.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v177.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v69.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v178.h, v166.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v163, 16, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v21, v27, v28, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.l, v146.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v160.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.l, v149.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v164, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v20, v20, v29, vcc_lo
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v181.h, v161.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v41.l, v134.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v41.h, v148.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v40.l, v145.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v176, 16, v20
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v40.h, v150.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v44.h, v144.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v43.l, v133.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v46.l, v163.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v46.h, v167.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v45.l, v164.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v45.h, v176.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v43.h, v147.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v85.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v98.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v113.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v116.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v114.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v118.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v49.l, v119.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v49.h, v132.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.l, v129.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v48.h, v135.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v64.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v71.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v85.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v96.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.l, v151.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v183.h, v164.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.l, v166.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v182.h, v167.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v84.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v83.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v86.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[28:29], 24, v[178:179]
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v52.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v69.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v70.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v80.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v81.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[29:30], 24, v[181:182]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[30:31], 24, v[40:41]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[31:32], 24, v[46:47]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[20:21]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[44:45]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[35:36]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[16:17], 24, v[13:14]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[25:26], 24, v[178:179]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[48:49]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[38:39], 24, v[28:29]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[11:12]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 24, v49
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[25:26], 24, v[45:46]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[31:32], 24, v[43:44]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[34:35]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[13:14]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[48:49]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[37:38], 24, v[23:24]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[11:12]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[26:27], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[9:10]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v46
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 8, v46
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 8, v45
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 24, v49
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v57, 8, v49
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v48
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 24, v36
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v36
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 8, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 24, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 8, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[26:27], 24, v[182:183]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[9:10]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[23:24], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 24, v179
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 8, v179
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 24, v183
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 8, v183
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 8, v182
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 24, v41
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 8, v41
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 24, v47
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 8, v47
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 8, v46
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 24, v45
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v47, 8, v45
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v46, 8, v44
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v45, 24, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 24, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v58, 8, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v59, 8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[1:2], 24, v[1:2]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v177, 24, v179
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v179, 8, v179
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v178, 8, v178
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v180, 24, v182
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v182, 8, v182
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v181, 8, v181
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v183, 24, v41
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v41, 8, v41
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v40, 8, v40
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 8, v35
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 24, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 8, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 8, v20
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 24, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v42, 24, v44
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v44, 8, v44
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v43, 8, v43
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v56, 8, v48
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v60, 24, v35
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v61, 8, v35
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v62, 8, v34
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v63, 24, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v73, 8, v24
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v72, 8, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 24, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 8, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 8, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 24, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 8, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 8, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v27, 24, v12
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 24, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 8, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 8, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 24, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 24, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 8, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 8, v9
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v29, 24, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v8
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 8, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 24, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 24, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX11-TRUE16-NEXT: s_branch .LBB91_5
@@ -163708,288 +162846,261 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-TRUE16-NEXT: ; kill: killed $sgpr43
; GFX11-TRUE16-NEXT: s_branch .LBB91_2
; GFX11-TRUE16-NEXT: .LBB91_4:
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v118, s2 :: v_dual_mov_b32 v115, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v149, s22 :: v_dual_mov_b32 v114, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 0
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v86, s8 :: v_dual_mov_b32 v165, s26
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v162, s27
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v166, s24 :: v_dual_mov_b32 v151, s25
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v133, s18 :: v_dual_mov_b32 v164, s26
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v163, s27
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v165, s24 :: v_dual_mov_b32 v146, s23
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v177, s0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 1
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v150, s22 :: v_dual_mov_b32 v147, s23
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v146, s20 :: v_dual_mov_b32 v135, s18
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v176, s0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v151, s25 :: v_dual_mov_b32 v134, s21
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v145, s20 :: v_dual_mov_b32 v82, s9
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v167, s0 :: v_dual_mov_b32 v100, s99
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v82, s10
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v134, s21 :: v_dual_mov_b32 v131, s19
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v130, s16 :: v_dual_mov_b32 v119, s17
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v167, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v131, s19
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v83, s10 :: v_dual_mov_b32 v112, s104
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v71, s11 :: v_dual_mov_b32 v102, s103
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v166, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 3
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v116, s3 :: v_dual_mov_b32 v99, s5
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v114, s1 :: v_dual_mov_b32 v87, s7
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v164, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v129, s16
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v103, s100 :: v_dual_mov_b32 v84, s97
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v98, s102
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v162, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 4
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v102, s4 :: v_dual_mov_b32 v81, s9
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v98, s6 :: v_dual_mov_b32 v71, s11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v163, s0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 5
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v113, s104 :: v_dual_mov_b32 v112, s100
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v103, s103 :: v_dual_mov_b32 v100, s102
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v81, s96 :: v_dual_mov_b32 v80, s12
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v69, s13 :: v_dual_mov_b32 v70, s87
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v161, s0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 6
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v101, s99 :: v_dual_mov_b32 v96, s101
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v97, s98 :: v_dual_mov_b32 v84, s96
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 5
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v119, s17
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v67, s14 :: v_dual_mov_b32 v68, s86
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v65, s15 :: v_dual_mov_b32 v66, s85
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v160, s0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 6
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v117, s2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, s40 :: v_dual_mov_b32 v64, s84
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v96, s98
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v150, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 7
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v85, s97 :: v_dual_mov_b32 v70, s13
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v83, s12 :: v_dual_mov_b32 v80, s87
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v149, s0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v68, s14 :: v_dual_mov_b32 v69, s86
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v65, s15 :: v_dual_mov_b32 v64, s40
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v115, s3
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, s41 :: v_dual_mov_b32 v54, s83
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, s28 :: v_dual_mov_b32 v52, s82
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v148, s0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v86, s101 :: v_dual_mov_b32 v39, s29
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v50, s81 :: v_dual_mov_b32 v15, s80
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v14, s67 :: v_dual_mov_b32 v147, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 9
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v67, s85 :: v_dual_mov_b32 v66, s84
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s41 :: v_dual_mov_b32 v55, s83
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v145, s0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 10
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, s28 :: v_dual_mov_b32 v53, s82
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v50, s29 :: v_dual_mov_b32 v51, s81
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v113, s1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v13, s71 :: v_dual_mov_b32 v24, s54
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, s65 :: v_dual_mov_b32 v12, s64
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v144, s0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 10
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, s69 :: v_dual_mov_b32 v34, s51
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, s66 :: v_dual_mov_b32 v10, s53
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v135, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 11
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s80 :: v_dual_mov_b32 v19, s70
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, s68 :: v_dual_mov_b32 v13, s71
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v133, s0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 12
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, s65 :: v_dual_mov_b32 v14, s67
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, s69 :: v_dual_mov_b32 v12, s64
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v101, s4
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, s55 :: v_dual_mov_b32 v8, s50
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, s48 :: v_dual_mov_b32 v48, s37
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v132, s0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 12
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v99, s5
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, s52 :: v_dual_mov_b32 v6, s39
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v46, s49 :: v_dual_mov_b32 v49, s35
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v130, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 13
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v27, s54 :: v_dual_mov_b32 v28, s51
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, s66 :: v_dual_mov_b32 v10, s53
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v129, s0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 14
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, s55 :: v_dual_mov_b32 v8, s50
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, s48 :: v_dual_mov_b32 v6, s39
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v97, s6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v45, s36 :: v_dual_mov_b32 v4, vcc_hi
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v59, s38 :: v_dual_mov_b32 v58, s34
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v128, s0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 14
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v87, s7
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, s72 :: v_dual_mov_b32 v28, s62
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v29, s60 :: v_dual_mov_b32 v30, s58
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v118, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 15
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, s52 :: v_dual_mov_b32 v48, s35
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, s37 :: v_dual_mov_b32 v36, s36
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v117, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v85, s8
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, s56 :: v_dual_mov_b32 v32, s46
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v36, s44 :: v_dual_mov_b32 v37, s42
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v116, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 16
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, s49 :: v_dual_mov_b32 v44, s38
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v45, vcc_hi :: v_dual_mov_b32 v4, s34
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v178, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, s74 :: v_dual_mov_b32 v18, s76
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v19, s78 :: v_dual_mov_b32 v20, s88
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v33, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 17
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, s72 :: v_dual_mov_b32 v26, s62
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, s60 :: v_dual_mov_b32 v31, s58
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v39, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v21, s90 :: v_dual_mov_b32 v26, s92
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, s94
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s30
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v27, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 18
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, s56 :: v_dual_mov_b32 v33, s46
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v37, s44 :: v_dual_mov_b32 v38, s42
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v34, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v22, s68
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v16, s70
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v38, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 19
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, s74 :: v_dual_mov_b32 v16, s76
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v17, s78 :: v_dual_mov_b32 v18, s88
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v180, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v178, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 20
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, s90 :: v_dual_mov_b32 v23, s92
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, s94
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s30
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v181, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v177, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 21
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v179, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 22
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v181, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 23
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v183, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v180, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v182, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 25
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v42, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v40, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 26
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v43, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v183, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 27
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v41, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 28
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v46, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v43, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 29
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v56, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v42, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 30
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v47, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v44, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v76, 31
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v59, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v56, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v77, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v58, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v47, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v77, 1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v57, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v77, 2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v60, s0
-; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v77, 3
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v62, s0
+; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v77, 3
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v60, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v77, 4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v61, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v77, 5
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v73, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v72, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v77, 6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v63, s0
; GFX11-TRUE16-NEXT: v_readlane_b32 s0, v77, 7
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v72, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v73, s0
; GFX11-TRUE16-NEXT: .LBB91_5: ; %end
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v128, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v38, v115, v73, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v115, v117, v63, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_perm_b32 v117, v114, v72, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v114, v129, v62, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v37, v132, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX11-TRUE16-NEXT: v_perm_b32 v118, v118, v60, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v114
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v114, v38, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v144, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; GFX11-TRUE16-NEXT: v_perm_b32 v128, v116, v61, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v130, v59, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v148, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v115, v117, v115
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v116, v118, v37
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v117, v128, v129
-; GFX11-TRUE16-NEXT: v_perm_b32 v37, v133, v58, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v38, v119, v57, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v119, v135, v46, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v32, 16, v32
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v128, v33, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v160, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v149, v43, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v130, v119, v32
-; GFX11-TRUE16-NEXT: v_perm_b32 v32, v146, v42, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v30, v163, v30, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v118, v145, v56, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v129, v38, v37
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v134, v41, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 16, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v32, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v161, v183, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v131, v131, v47, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v118
-; GFX11-TRUE16-NEXT: v_perm_b32 v37, v150, v40, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v167, v26, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v31, v33, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v147, v182, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v177, v25, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v131, v131, v118
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v32, v37, v38
-; GFX11-TRUE16-NEXT: v_perm_b32 v38, v166, v180, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v69, v23, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v96, v18, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v118, v37, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v114, v72, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v118, v117, v62, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v36, v130, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v113, v113, v73, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v114, v116, v63, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v116, v2, 16, v37
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v115, v61, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v118, v36, 16, v118
+; GFX11-TRUE16-NEXT: v_perm_b32 v36, v128, v60, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v129, v56, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v32, v135, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v115, v133, v43, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v147, v31, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v117, v114, 16, v113
+; GFX11-TRUE16-NEXT: v_perm_b32 v113, v119, v57, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v114, v132, v47, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v119, v36, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v145, v40, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v30, v150, v30, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v131, v131, v44, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v132, v144, v42, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v164, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v25, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v128, v32, 16, v37
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v130, v31, 16, v115
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v134, v41, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v32, v148, v183, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v36, v149, v181, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v161, v29, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v129, v114, 16, v113
+; GFX11-TRUE16-NEXT: v_perm_b32 v113, v146, v182, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v114, v160, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v30, 16, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v165, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v166, v28, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v38, v163, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v167, v27, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v131, v132, 16, v131
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v115, v25, 16, v33
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v55, v46, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v64, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v67, v5, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v68, v26, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v85, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v98, v19, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, v80, v7, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v81, v21, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, v83, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v86, v20, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v32, 16, v31
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v37, 16, v36
+; GFX11-TRUE16-NEXT: v_perm_b32 v36, v151, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v162, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[114:117], off
+; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[116:119], off
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[128:131], off offset:16
-; GFX11-TRUE16-NEXT: v_perm_b32 v116, v165, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v33, v33, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v176, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v114, v38, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v51, v45, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v68, v5, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v84, v22, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v82, v9, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v100, v17, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v37, v164, v181, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v116, v116, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v162, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v32, v114, 16, v113
+; GFX11-TRUE16-NEXT: v_perm_b32 v51, v51, v59, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v52, v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v113, v28, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v116, v27, 16, v38
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v39, v58, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v50, v4, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, v83, v7, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v5, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v80, v29, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v86, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v9, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v97, v27, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v115, v151, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v53, v1, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v66, v3, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v117, v25, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v55, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v4, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v26, v67, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v85, v28, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v103, v16, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v101, v21, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v113, v15, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v112, v24, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v115, v115, v37
-; GFX11-TRUE16-NEXT: v_perm_b32 v34, v52, v44, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v37, v64, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, v54, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v53, v45, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v54, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v6, v65, v6, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v70, v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v66, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v3, 16, v25
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v70, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v26, 16, v5
; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v81, v12, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v98, v13, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v26, v84, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v19, 16, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v82, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v96, v24, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v21, 16, v7
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v20, 16, v9
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v97, v13, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v102, v18, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v87, v14, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v102, v20, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v99, v19, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v34, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v37, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v25
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v6, v26
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v22
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v23
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v12, v17
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v13, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v19, v21
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v100, v23, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v101, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v112, v17, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v99, v16, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v103, v22, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v114, v37, 16, v36
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v1, 16, v51
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v28, 16, v27
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v33, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v25, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v26, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v19, 16, v12
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v18, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v20, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v17, 16, v15
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v21, 16, v16
; GFX11-TRUE16-NEXT: s_clause 0x5
-; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[30:33], off offset:32
-; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[114:117], off offset:48
+; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[29:32], off offset:32
+; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[113:116], off offset:48
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:64
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:80
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:96
@@ -164352,7 +163463,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v11, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, v10, v4
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v2, v5, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s41
; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, 0x400000, v6
@@ -164361,13 +163472,13 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v3, 0x7fff, v3
; GFX11-FAKE16-NEXT: v_bfe_u32 v6, v8, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v2
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v7, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v6, v8
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v1, v5, v7
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v3, v3, v9 :: v_dual_add_nc_u32 v4, 0x7fff, v4
@@ -164382,15 +163493,15 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v4
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, v5, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v1, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v8, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s28
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v4, 0x7fff, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v7
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v9
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
@@ -164401,9 +163512,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v39
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v48
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v5
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v4, v11 :: v_dual_add_nc_u32 v5, v7, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v9, v10
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s15
@@ -164422,8 +163533,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v9, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v48, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v49, 16, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v7, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v10, v11
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc_lo
@@ -164438,9 +163549,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v10, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 16, v5
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v7
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v58, 8, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v8, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v11, v12
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s13
@@ -164455,7 +163566,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-FAKE16-NEXT: s_and_b32 s12, s11, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s11, s11, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 16, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v9
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, 0x400000, v12
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v13, 16, 1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
@@ -164463,7 +163574,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v9, v11, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 16, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v14 :: v_dual_add_nc_u32 v8, v9, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v12, v13
@@ -164480,7 +163591,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v12, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v9, v10, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v13, v14
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s11
@@ -164495,7 +163606,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: s_and_b32 s10, s9, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s9, s9, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 16, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v14
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v15, 16, 1
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
@@ -164503,7 +163614,7 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v13, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v10
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v11, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v14, v15
@@ -164519,9 +163630,9 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v12, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v14, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v68
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 16, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v12, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v15, v16
; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s9
@@ -164539,14 +163650,14 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 16, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v17, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v82, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v83, 16, v9
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v13 :: v_dual_and_b32 v9, 0xffff, v71
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v12, v12, v13 :: v_dual_and_b32 v9, 0xffff, v82
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v15, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v17
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v85, 16, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 16, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 16, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, v13, v15
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v16, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v11, v18, vcc_lo
@@ -164562,8 +163673,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v14, v16, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 16, v13
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v13
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v14, v16
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v12, v19 :: v_dual_add_nc_u32 v14, v17, v18
; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s7
@@ -164582,8 +163693,8 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v17, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v70
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 16, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 16, v14
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v15, v17
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v19
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v20, vcc_lo
@@ -164599,443 +163710,442 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v18, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 16, v15
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v21 :: v_dual_add_nc_u32 v15, v16, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v19, v20
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v13
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v16, v18
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v17, v14, v21 :: v_dual_add_nc_u32 v16, v19, v20
; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s5
; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s4
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v20
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v20
; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v21, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
; GFX11-FAKE16-NEXT: s_and_b32 s4, s1, 0xffff0000
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v16, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v16, v19, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v19, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v49
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v20, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 16, v15
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v22 :: v_dual_add_nc_u32 v15, v16, v19
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v19
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v98, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v17, v19
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v20, v21
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v22, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s4
; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
; GFX11-FAKE16-NEXT: s_and_b32 s1, s0, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v101, 16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v21
; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v22, 16, 1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v84
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v50, 16, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v20, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s3, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v99, 16, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v20
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v23, vcc_lo
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v50
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v20
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v100, 16, v17
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v23 :: v_dual_add_nc_u32 v17, v18, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v21, v22
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v18
; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v22
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v21, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v23, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s3, 0xffff0000
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v19
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v98, 16, v13
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v19, 16, 1
+; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s3, 16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v21
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v18, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v21, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v87
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v103, 16, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v19
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v23, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v22, v21
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v22, v23
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v17
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v24 :: v_dual_add_nc_u32 v17, v18, v21
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v51, 16, v3
; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v21
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v22, 16, 1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v23
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v24, 16, 1
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s2, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v100, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v96
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v20, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v51
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v112, 16, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v20
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v25, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v21, v22
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v101, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v22
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v99
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v20
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v21, 16, 1
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s17, 0xffff0000
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v19, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v102, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v103
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v18, v19
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v25, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v22, v21
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v114, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v112
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v21
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v102, 16, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v98
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v22, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v52
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v113, 16, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v20, v22
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v25, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v23, v24
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v102, 16, v15
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v117, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v100
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v22
+; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v23, 16, 1
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s17, 0xffff0000
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v21, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v103, 16, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v112
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v114, 16, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v20, v21
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v25, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v24, v23
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v115, 16, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v113
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v23
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s17, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v117, 16, v13
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v113
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v22, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v19
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v38, v118, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v115, 16, v15
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v21, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v117, 16, v15
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v114
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v24, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v21
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v39, v119, 16, v15
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v17
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v20, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v23, v24
; GFX11-FAKE16-NEXT: s_and_b32 s0, s16, 0xffff0000
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v22
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s16, 16
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v17, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v19, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v24
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s16, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
+; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v21, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v20, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v115
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v25, v19
-; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v26, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v116
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v25, v21
+; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v26, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v23, vcc_lo
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v37, v129, 16, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v130, 16, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v116, 16, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v20, v26
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, 0x400000, v19
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v38, v130, 16, v16
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v20
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v118, 16, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v22, v26
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, 0x400000, v21
; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v26
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v26
+; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v20, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v17, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v20, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v52, 16, v3
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v19, v22, v18
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v13
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v22, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v53, 16, v3
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v24, v20
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v15
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v14, v14, v21 :: v_dual_add_nc_u32 v15, v15, v20
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v19, 0x400000, v20
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v16, v16, v23 :: v_dual_add_nc_u32 v17, v17, v22
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v22
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v128, 16, v16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, 0x400000, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v116
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v118
; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s21, 16
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v14, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v53
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v128
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v44, v130, 16, v21
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v133, 16, v13
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v15, v19, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v15, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v16, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v54
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xffff, v128
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v45, v131, 16, v23
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v15
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v17, v21, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v17, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s18, 16
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v19, 0x40c00000, s1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v43, v134, 16, v22
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v119, 16, v14
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v44, v133, 16, v24
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v129, 16, v16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
-; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v19, 16, 1
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v119
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v14, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v18, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v46, v133, 16, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v21, v14
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v15, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v22, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, v25, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, 0x7fff, v21
+; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v21, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v129
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v16, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v16
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v20, 16, 1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v43, v135, 16, v22
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, v23, v16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v17, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v21
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v24, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v25, v21
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x7fff, v22
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v20, v26, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v19, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v15
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v17
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, 0x7fff, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, 0x7fff, v24
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v22, v26, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v17
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v14
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v19, v22, v27, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v134, 16, v16
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v24, v27, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s20, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v86, 16, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v131, 16, v19
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v21, v28, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v132
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v83
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v131
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v18
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v25, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s23, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v41, v145, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v13
-; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v14, 16, 1
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v86
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v132, 16, v21
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v23, v28, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v134
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v87, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v132
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v145, 16, v20
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s23, 16
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v47, v145, 16, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v147, 16, v15
+; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v16, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v20, 16, 1
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s23, 0xffff0000
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, v13, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v18
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v22, v20, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v13, 0x7fff, v13
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v17, v20
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v24, v22, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, 0x400000, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
-; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v21, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, v22, v20
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
+; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v23, 16, 1
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v24, v22
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v13, v25, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, v26, v21
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v21
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v27, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v25, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v14
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, v26, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v24
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v22
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v23
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v27, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s22, 16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v15
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v18, v22, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v54
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v20, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v150, 16, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v135, 16, v18
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v25, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, v15, v20
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v64, 16, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v135
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v149, 16, v14
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v17
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v20, v24, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v64
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v22, 16, 1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v151, 16, v15
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v144, 16, v20
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v25, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v17, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v65, 16, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v144
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v150, 16, v16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: s_and_b32 s0, s25, 0xffff0000
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v144
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v183, v149, 16, v18
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v14, 16, 1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v18, 0x400000, v20
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v22, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v146
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v181, v150, 16, v20
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v16, 16, 1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v22
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v24, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s25, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v45, v147, 16, v19
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v21, v14
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v18, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v18, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v22, 16, 1
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v14
-; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v18, 16, 1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v84
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v23, v16
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v20, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v20, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_bfe_u32 v25, v24, 16, 1
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x7fff, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v16
+; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v20, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v162, 16, v15
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v161, 16, v17
; GFX11-FAKE16-NEXT: v_add_f32_e64 v27, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v20, v21, vcc_lo
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v25, v22
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v21, v26, v18
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-FAKE16-NEXT: v_bfe_u32 v15, v27, 16, 1
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v148, 16, v14
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v14, 0x7fff, v20
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v21, 0x400000, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v67
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v22, v23, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, v25, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v23, v26, v20
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-FAKE16-NEXT: v_bfe_u32 v17, v27, 16, 1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v149, 16, v16
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v16, 0x7fff, v22
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x7fff, v23
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v23, 0x400000, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v66
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s24, 16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v22
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v18, v20, v21 :: v_dual_add_nc_u32 v15, v15, v27
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, 0x400000, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, v17, v27
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v22, v23, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-FAKE16-NEXT: v_add_f32_e64 v26, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v20, 0x400000, v27
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v15
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v27
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v17
; GFX11-FAKE16-NEXT: s_and_b32 s0, s27, 0xffff0000
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v14, v25, vcc_lo
-; GFX11-FAKE16-NEXT: v_bfe_u32 v21, v26, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v16, v25, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v23, v26, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v146, 16, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v22, 0x400000, v26
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v163, 16, v14
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v14, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v148, 16, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v24, 0x400000, v26
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v164, 16, v16
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v16, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v15, v15, v20 :: v_dual_add_nc_u32 v18, v21, v26
-; GFX11-FAKE16-NEXT: v_add_f32_e64 v21, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v23, v26
+; GFX11-FAKE16-NEXT: v_add_f32_e64 v23, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s26, 16
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v164, 16, v15
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v15, 0x7fff, v18
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v165, 16, v17
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v17, 0x7fff, v20
; GFX11-FAKE16-NEXT: v_add_f32_e64 v25, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v21, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v27, v23, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
-; GFX11-FAKE16-NEXT: v_bfe_u32 v18, v14, 16, 1
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v15, v15, v22, vcc_lo
+; GFX11-FAKE16-NEXT: v_bfe_u32 v20, v16, 16, 1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v17, v17, v24, vcc_lo
; GFX11-FAKE16-NEXT: v_bfe_u32 v29, v25, 16, 1
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, v27, v21
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, v27, v23
; GFX11-FAKE16-NEXT: v_add_f32_e64 v28, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v21
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, 0x400000, v23
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, v29, v25
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x7fff, v22
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, v18, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, 0x7fff, v24
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, v20, v16
; GFX11-FAKE16-NEXT: v_bfe_u32 v26, v28, 16, 1
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v25
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v27, 0x7fff, v27
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v21, v22, v32, vcc_lo
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v23, v24, v32, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v18, 0x7fff, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v14
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v20, 0x7fff, v20
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v16
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v26, v26, v28
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v69, 16, v7
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v163, 16, v17
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v25, v27, v33, vcc_lo
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v80
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v22, 0x7fff, v26
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v160, 16, v23
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v24, 0x7fff, v26
; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, 0x400000, v28
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v151, 16, v21
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v14, v18, v29, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v162, 16, v25
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v16, v20, v29, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v28, v28
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v65
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v160, 16, v25
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v161, 16, v15
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v165, 16, v14
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v18, v22, v26, vcc_lo
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v151
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xffff, v160
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v146
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v148
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v166, 16, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v161
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v177, v165, 16, v14
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v68
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v148
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v23, 0xffff, v149
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v166, 16, v16
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v20, v24, v26, vcc_lo
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v69, 16, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v71
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v160
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v162
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v167, 16, v20
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v163
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v46, v151, 16, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v99, 16, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v96
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v42, v147, 16, v21
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v97, 16, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v181, v163, 16, v20
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v176, v166, 16, v15
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v180, v164, 16, v18
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v182, v162, 16, v21
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v178, v164, 16, v22
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v177, v165, 16, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v80, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v180, v161, 16, v23
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v55, 16, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v81, 16, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v40, v150, 16, v13
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v66, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[45:46]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[25:26], 24, v[176:177]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[43:44]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[26:27], 24, v[180:181]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[37:38]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[18:19], 24, v[11:12]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[27:28], 24, v[182:183]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[30:31]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[19:20], 24, v[9:10]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[28:29], 24, v[40:41]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[23:24]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[7:8]
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v167, 24, v177
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 8, v177
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v179, 24, v181
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v177, 8, v181
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v178, 8, v180
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v181, 24, v183
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v180, 8, v183
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v42, 24, v41
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v183, 8, v41
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v59, 8, v43
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v62, 24, v38
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v61, 8, v38
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v41, 24, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 8, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v43, 8, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v183, v166, 16, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v182, v167, 16, v17
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[32:33], 24, v[46:47]
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v67, 16, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v101, 16, v13
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[33:34], 24, v[42:43]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[34:35], 24, v[44:45]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[20:21], 24, v[11:12]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[27:28], 24, v[177:178]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[35:36], 24, v[38:39]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[9:10]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[28:29], 24, v[180:181]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[36:37], 24, v[30:31]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[22:23], 24, v[7:8]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[24:25], 24, v[182:183]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[15:16], 24, v[18:19]
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 24, v183
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 8, v183
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 8, v182
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v182, 24, v47
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v40, 8, v47
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v183, 8, v46
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v47, 24, v45
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v57, 8, v45
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v56, 8, v44
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v44, 24, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v45, 8, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v46, 8, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[3:4]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[16:17]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[21:22], 24, v[5:6]
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v56, 24, v46
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v47, 8, v46
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v46, 8, v45
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v58, 24, v44
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v57, 8, v44
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v45, 24, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 8, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v44, 8, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[16:17], 24, v[13:14]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[25:26], 24, v[5:6]
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 24, v2
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v59, 8, v1
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[1:2], 24, v[1:2]
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v176, 8, v176
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v182, 8, v182
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v40, 8, v40
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v60, 8, v37
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v176, 24, v178
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v178, 8, v178
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v177, 8, v177
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v179, 24, v181
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v181, 8, v181
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v180, 8, v180
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v41, 24, v43
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v43, 8, v43
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v42, 8, v42
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v60, 24, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v61, 8, v39
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v62, 8, v38
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v63, 24, v31
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v72, 8, v31
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v73, 8, v30
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v29, 24, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v15, 8, v24
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 8, v23
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 24, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 8, v17
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v16, 8, v16
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 24, v12
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v73, 8, v31
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v72, 8, v30
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v17, 24, v19
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v19, 8, v19
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v18, 8, v18
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 24, v14
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v14, 8, v14
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v13
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 24, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v12, 8, v12
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v11, 8, v11
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v30, 24, v10
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v10, 8, v10
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v9, 8, v9
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 24, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 24, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v8, 8, v8
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 8, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 24, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 24, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 8, v6
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
; GFX11-FAKE16-NEXT: s_branch .LBB91_5
@@ -165178,287 +164288,251 @@ define inreg <128 x i8> @bitcast_v64bf16_to_v128i8_scalar(<64 x bfloat> inreg %a
; GFX11-FAKE16-NEXT: ; kill: killed $sgpr43
; GFX11-FAKE16-NEXT: s_branch .LBB91_2
; GFX11-FAKE16-NEXT: .LBB91_4:
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v112, s0 :: v_dual_mov_b32 v103, s1
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v144, s23 :: v_dual_mov_b32 v113, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 0
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v160, s26 :: v_dual_mov_b32 v151, s27
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v161, s24 :: v_dual_mov_b32 v146, s25
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v166, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v132, s21
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v162, s26 :: v_dual_mov_b32 v163, s24
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v160, s27 :: v_dual_mov_b32 v149, s22
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v167, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 1
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v148, s22 :: v_dual_mov_b32 v135, s23
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v144, s20 :: v_dual_mov_b32 v131, s21
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v165, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v148, s25 :: v_dual_mov_b32 v129, s19
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v146, s20 :: v_dual_mov_b32 v81, s9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v166, s0 :: v_dual_mov_b32 v99, s99
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v132, s18 :: v_dual_mov_b32 v119, s19
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v128, s16 :: v_dual_mov_b32 v115, s2
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v164, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v134, s18
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, s10 :: v_dual_mov_b32 v103, s104
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, s11 :: v_dual_mov_b32 v101, s103
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v165, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v116, s17 :: v_dual_mov_b32 v113, s3
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v99, s4 :: v_dual_mov_b32 v96, s5
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v163, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v102, s100 :: v_dual_mov_b32 v83, s97
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v97, s102 :: v_dual_mov_b32 v80, s96
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v71, s12 :: v_dual_mov_b32 v164, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 4
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v87, s6 :: v_dual_mov_b32 v84, s7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, s8 :: v_dual_mov_b32 v70, s9
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v128, s16 :: v_dual_mov_b32 v87, s98
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v68, s13 :: v_dual_mov_b32 v69, s87
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v162, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v161, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 5
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v71, s10 :: v_dual_mov_b32 v68, s11
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v102, s104 :: v_dual_mov_b32 v101, s100
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v149, s0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 6
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v100, s103 :: v_dual_mov_b32 v97, s102
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v98, s99 :: v_dual_mov_b32 v85, s101
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v66, s14 :: v_dual_mov_b32 v67, s86
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, s15 :: v_dual_mov_b32 v65, s85
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v150, s0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 6
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v118, s17
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, s40 :: v_dual_mov_b32 v55, s84
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, s41 :: v_dual_mov_b32 v53, s83
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v151, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 7
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v86, s98 :: v_dual_mov_b32 v81, s96
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v82, s97 :: v_dual_mov_b32 v67, s13
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v116, s2
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, s28 :: v_dual_mov_b32 v51, s82
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v48, s29 :: v_dual_mov_b32 v49, s81
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v145, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 8
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v80, s12 :: v_dual_mov_b32 v69, s87
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, s14 :: v_dual_mov_b32 v66, s86
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v114, s3 :: v_dual_mov_b32 v17, s68
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s64 :: v_dual_mov_b32 v19, s70
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v147, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s53 :: v_dual_mov_b32 v147, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 9
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, s15 :: v_dual_mov_b32 v53, s40
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, s85 :: v_dual_mov_b32 v55, s84
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v133, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v112, s1 :: v_dual_mov_b32 v85, s101
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v13, s71 :: v_dual_mov_b32 v38, s48
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v135, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 10
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v51, s41 :: v_dual_mov_b32 v52, s83
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v49, s28 :: v_dual_mov_b32 v50, s82
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v100, s4 :: v_dual_mov_b32 v11, s69
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s50 :: v_dual_mov_b32 v9, s66
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v134, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s39 :: v_dual_mov_b32 v133, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 11
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, s29 :: v_dual_mov_b32 v48, s81
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v22, s80 :: v_dual_mov_b32 v23, s65
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v130, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v98, s5 :: v_dual_mov_b32 v31, s51
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v46, s49 :: v_dual_mov_b32 v7, s55
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v44, s35 :: v_dual_mov_b32 v131, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 12
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s71 :: v_dual_mov_b32 v17, s67
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v11, s69 :: v_dual_mov_b32 v24, s54
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, s52 :: v_dual_mov_b32 v4, vcc_hi
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v39, s37 :: v_dual_mov_b32 v58, s34
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v129, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v130, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 13
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v12, s64 :: v_dual_mov_b32 v9, s66
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, s51 :: v_dual_mov_b32 v7, s55
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v118, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v96, s6 :: v_dual_mov_b32 v45, s36
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, s72 :: v_dual_mov_b32 v59, s38
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v28, s60 :: v_dual_mov_b32 v119, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 14
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s53 :: v_dual_mov_b32 v31, s48
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v8, s50 :: v_dual_mov_b32 v5, s52
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v86, s7 :: v_dual_mov_b32 v27, s62
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s58 :: v_dual_mov_b32 v33, s56
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v117, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s46 :: v_dual_mov_b32 v117, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 15
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, s37 :: v_dual_mov_b32 v6, s39
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v43, s49 :: v_dual_mov_b32 v38, s36
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v114, s0
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, s8 :: v_dual_mov_b32 v35, s44
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, s42 :: v_dual_mov_b32 v15, s74
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s76 :: v_dual_mov_b32 v115, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 16
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v41, s35 :: v_dual_mov_b32 v44, s38
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v45, vcc_hi :: v_dual_mov_b32 v4, s34
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, s78 :: v_dual_mov_b32 v21, s88
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v22, s90 :: v_dual_mov_b32 v25, s92
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v176, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v29, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 17
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v25, s72 :: v_dual_mov_b32 v26, s62
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v27, s60 :: v_dual_mov_b32 v28, s58
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v167, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, s94
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s30 :: v_dual_mov_b32 v18, s80
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v26, s65 :: v_dual_mov_b32 v23, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 18
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s56 :: v_dual_mov_b32 v33, s46
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s44 :: v_dual_mov_b32 v35, s42
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v36, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v14, s67
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, s54 :: v_dual_mov_b32 v37, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 19
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v13, s74 :: v_dual_mov_b32 v14, s76
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, s78 :: v_dual_mov_b32 v19, s88
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v178, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v177, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 20
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, s90 :: v_dual_mov_b32 v21, s92
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, s94
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, s30
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v179, s0
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v176, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 21
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v29, s68
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v15, s70
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v177, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v178, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 22
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v182, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v180, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 23
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v181, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v179, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 24
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v180, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v181, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 25
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v183, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 26
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v42, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v182, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 27
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v183, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v40, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 28
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v46, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v42, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 29
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v56, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v41, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 30
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v47, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v43, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v76, 31
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v59, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v56, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v77, 0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v58, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v47, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v77, 1
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v57, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v77, 2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v60, s0
-; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v77, 3
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v62, s0
+; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v77, 3
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v60, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v77, 4
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v61, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v77, 5
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v73, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v72, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v77, 6
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v63, s0
; GFX11-FAKE16-NEXT: v_readlane_b32 s0, v77, 7
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v72, s0
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v73, s0
; GFX11-FAKE16-NEXT: .LBB91_5: ; %end
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v35, v112, v73, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v112, v114, v63, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v34, v129, v34, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v103, v103, v72, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v114, v118, v62, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v112
-; GFX11-FAKE16-NEXT: v_perm_b32 v115, v115, v60, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v112, v35, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v134, v33, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v118, v113, v61, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v129, 16, v114
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v113, v103, v117
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v114, v115, v34
-; GFX11-FAKE16-NEXT: v_perm_b32 v33, v128, v59, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v34, v130, v58, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v32, v147, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v103, v133, v56, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v115, v118, v129
-; GFX11-FAKE16-NEXT: v_perm_b32 v35, v116, v57, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v34, 16, v34
-; GFX11-FAKE16-NEXT: v_perm_b32 v116, v132, v46, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v117, 16, v32
-; GFX11-FAKE16-NEXT: v_perm_b32 v118, v119, v47, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v33, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v150, v28, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v145, v42, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v35, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v116, v117
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v118, v103
-; GFX11-FAKE16-NEXT: v_perm_b32 v103, v144, v40, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v162, v27, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v116, v131, v183, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v66, v21, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v117, v148, v182, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v117, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v36, v113, v72, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v117, v116, v62, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v35, v130, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v112, v112, v73, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v113, v115, v63, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v115, v2, 16, v36
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v114, v61, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v117, v35, 16, v117
+; GFX11-FAKE16-NEXT: v_perm_b32 v35, v119, v60, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v114, v134, v42, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v119, v147, v33, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v116, v113, 16, v112
+; GFX11-FAKE16-NEXT: v_perm_b32 v36, v128, v56, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v34, v133, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v112, v118, v57, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v113, v131, v47, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v128, v129, v43, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v129, v135, v41, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v118, v35, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v146, v183, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v32, v151, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v35, v119, 16, v114
+; GFX11-FAKE16-NEXT: v_perm_b32 v114, v149, v180, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v161, v28, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v37, v160, v37, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v166, v23, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v33, v34, 16, v36
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v34, v113, 16, v112
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v36, v129, 16, v128
+; GFX11-FAKE16-NEXT: v_perm_b32 v112, v132, v40, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v113, v145, v182, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v32, v32, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v163, v177, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v165, v27, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v162, v29, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v167, v24, 0xc0c0004
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[112:115], off
-; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[32:35], off offset:16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v32, v103, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v149, v181, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, v116, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v164, v26, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v163, v179, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, v65, v5, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v81, v20, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v85, v19, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v34, v117, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v27, v135, v180, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-FAKE16-NEXT: v_perm_b32 v103, v161, v178, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v25, v166, v25, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v112, v146, v177, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, v50, v1, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v80, v7, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v5, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v69, v31, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v71, v9, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v97, v18, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v114, 16, v25
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v35, v27, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v103, v26
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, v165, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v26, v112, v28
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v151, v36, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v36, v48, v45, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v48, v49, v44, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v20
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v67, v8, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v82, v30, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v83, v11, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v24, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[115:118], off
+; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[33:36], off offset:16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v34, v28, 16, v114
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v148, v178, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v36, v164, v176, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v115, v23, 16, v37
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v54, v46, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v55, v3, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v39, v4, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v48, v1
-; GFX11-FAKE16-NEXT: v_perm_b32 v48, v52, v41, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v37, v64, v37, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v68, v10, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v8, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v18
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v100, v14, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v98, v23, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v102, v13, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v101, v29, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v113, v160, v176, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v39, v53, v43, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, v28, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v4, v36
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, v51, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v36, 16, v48
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, v54, v6, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v70, v12, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v87, v16, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v84, v17, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v99, v22, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v22, 16, v13
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v96, v15, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v113, v114
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v39, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v36
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v6, v37
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v18
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v16, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v17, v19
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v21, v22
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v23, v20
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v33, v113, 16, v112
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v112, v27, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v114, v24, 16, v29
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, v48, v58, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, v49, v4, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v52, v45, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v27, v53, v44, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v84, v11, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v97, v20, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v119, v144, v181, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v128, v150, v179, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v82, v9, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v85, v21, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v50, v50, v59, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, v51, v1, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v113, v36, 16, v28
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, v66, v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v67, v25, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, v64, v6, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v65, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v23
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, v71, v7, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v80, v22, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, v68, v8, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v23, v69, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v27, 16, v24
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v70, v10, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v24, v83, v31, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v20, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v81, v12, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v30, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v35, v128, 16, v119
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v21, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v96, v13, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v101, v16, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v86, v14, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v99, v26, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v100, v18, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v103, v15, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v98, v19, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v102, v17, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v1, 16, v50
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v25, 16, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v28, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v22, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v23, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v24, 16, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v20, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v21, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v19
; GFX11-FAKE16-NEXT: s_clause 0x5
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[32:35], off offset:32
-; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[25:28], off offset:48
+; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[112:115], off offset:48
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off offset:64
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:80
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:96
@@ -174415,7 +173489,6 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_readfirstlane_b32 s47, v7
; GFX9-NEXT: v_readfirstlane_b32 s59, v6
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332
-; GFX9-NEXT: v_readfirstlane_b32 s42, v13
; GFX9-NEXT: v_readfirstlane_b32 s74, v30
; GFX9-NEXT: v_readfirstlane_b32 s44, v29
; GFX9-NEXT: v_readfirstlane_b32 s56, v28
@@ -174433,6 +173506,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_readfirstlane_b32 s58, v16
; GFX9-NEXT: v_readfirstlane_b32 s73, v15
; GFX9-NEXT: v_readfirstlane_b32 s75, v14
+; GFX9-NEXT: v_readfirstlane_b32 s42, v13
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:324
@@ -174453,26 +173527,28 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:296
+; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:296
; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:292
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:288
+; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:288
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:280
-; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:276
+; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:280
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:276
; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:272
; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:268
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:264
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:260
-; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:256
-; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:252
-; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:248
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:244
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240
+; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:264
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:260
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:256
+; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:252
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:240
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:236
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232
@@ -174483,7 +173559,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
@@ -174495,7 +173571,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
@@ -174509,13 +173585,11 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:192
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v13, off, s[0:3], s32 offset:188
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:188
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:184
; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:180
; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:176
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:172
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:172
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:168
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:164
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:160
@@ -174588,23 +173662,23 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB93_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -174653,38 +173727,37 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s73
; GFX9-NEXT: v_perm_b32 v7, s75, v7, v8
-; GFX9-NEXT: v_mov_b32_e32 v63, v33
; GFX9-NEXT: v_mov_b32_e32 v33, v9
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_perm_b32 v9, s58, v9, v8
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v10
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
; GFX9-NEXT: v_perm_b32 v10, s74, v12, v8
-; GFX9-NEXT: v_or_b32_sdwa v9, v11, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v18
-; GFX9-NEXT: v_or_b32_sdwa v9, v22, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v13
-; GFX9-NEXT: v_or_b32_sdwa v10, v15, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v22
+; GFX9-NEXT: v_lshl_or_b32 v9, v18, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v15
+; GFX9-NEXT: v_lshl_or_b32 v10, v13, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_lshl_or_b32 v12, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v14
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v17
; GFX9-NEXT: v_perm_b32 v10, v26, v21, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v17, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v14, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v13, v9, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v25
-; GFX9-NEXT: v_or_b32_sdwa v9, v30, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v16
-; GFX9-NEXT: v_or_b32_sdwa v10, v20, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v30
+; GFX9-NEXT: v_lshl_or_b32 v9, v25, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v20
+; GFX9-NEXT: v_lshl_or_b32 v10, v16, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_lshl_or_b32 v14, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v19
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v24
; GFX9-NEXT: v_perm_b32 v10, v35, v29, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v24, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v19, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v15, v9, 16, v10
; GFX9-NEXT: v_perm_b32 v9, v39, v34, s4
@@ -174711,140 +173784,141 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_perm_b32 v10, v56, v44, s4
; GFX9-NEXT: v_lshl_or_b32 v21, v10, 16, v9
-; GFX9-NEXT: v_perm_b32 v9, v58, v42, s4
+; GFX9-NEXT: v_perm_b32 v9, v62, v42, s4
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_perm_b32 v10, v59, v47, s4
; GFX9-NEXT: v_lshl_or_b32 v22, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; GFX9-NEXT: v_mov_b32_e32 v41, v46
; GFX9-NEXT: v_mov_b32_e32 v50, v32
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v51, v49
-; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v41, v46
; GFX9-NEXT: v_mov_b32_e32 v39, v52
; GFX9-NEXT: v_mov_b32_e32 v52, v38
; GFX9-NEXT: v_mov_b32_e32 v34, v37
; GFX9-NEXT: v_mov_b32_e32 v37, v31
-; GFX9-NEXT: s_lshl_b32 s5, s13, 8
-; GFX9-NEXT: s_lshl_b32 s77, s9, 8
-; GFX9-NEXT: s_lshl_b32 s78, s44, 8
-; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(9)
-; GFX9-NEXT: v_perm_b32 v9, v9, v10, s4
+; GFX9-NEXT: s_waitcnt vmcnt(8)
+; GFX9-NEXT: v_perm_b32 v9, v58, v9, s4
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v32, v58, s4
; GFX9-NEXT: v_lshl_or_b32 v23, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v49
-; GFX9-NEXT: v_or_b32_sdwa v10, v24, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX9-NEXT: v_lshl_or_b32 v24, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v35
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v49, 8, v10
+; GFX9-NEXT: v_lshl_or_b32 v24, v10, 16, v9
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v25, v10, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v35, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v25, v9, 16, v10
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v33
-; GFX9-NEXT: v_or_b32_sdwa v10, v62, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v33, v46
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; GFX9-NEXT: v_or_b32_sdwa v9, v43, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v43
+; GFX9-NEXT: v_lshl_or_b32 v9, v54, 8, v9
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; GFX9-NEXT: v_mov_b32_e32 v54, v48
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v26, 8, v10
; GFX9-NEXT: v_lshl_or_b32 v26, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v48
-; GFX9-NEXT: v_perm_b32 v10, v63, v61, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v61
+; GFX9-NEXT: v_lshl_or_b32 v9, v33, 8, v9
+; GFX9-NEXT: v_mov_b32_e32 v33, v46
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v10, v10, v48, s4
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v27, v9, 16, v10
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v54, v61
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v63
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_mov_b32_e32 v48, v63
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GFX9-NEXT: v_or_b32_sdwa v10, v28, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v28, 8, v10
; GFX9-NEXT: v_lshl_or_b32 v28, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v36, v10, s4
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v29, v9, 16, v10
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v43
-; GFX9-NEXT: v_or_b32_sdwa v9, v62, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v62
+; GFX9-NEXT: v_lshl_or_b32 v9, v43, 8, v9
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GFX9-NEXT: v_or_b32_sdwa v10, v30, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v30, 8, v10
; GFX9-NEXT: v_lshl_or_b32 v30, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v38
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v46
; GFX9-NEXT: v_perm_b32 v10, v63, v61, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v46, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v38, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX9-NEXT: s_and_b32 s4, s40, 0xff
; GFX9-NEXT: v_lshl_or_b32 v31, v9, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v9, s57
+; GFX9-NEXT: s_lshl_b32 s5, s13, 8
; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
-; GFX9-NEXT: s_and_b32 s4, s40, 0xff
-; GFX9-NEXT: s_or_b32 s4, s4, s5
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX9-NEXT: v_lshl_or_b32 v9, s4, 16, v8
; GFX9-NEXT: s_and_b32 s4, s76, 0xff
+; GFX9-NEXT: v_lshl_or_b32 v9, s5, 16, v8
; GFX9-NEXT: s_lshl_b32 s5, s41, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s11, 0xff
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
+; GFX9-NEXT: s_or_b32 s5, s5, s4
+; GFX9-NEXT: s_and_b32 s4, s11, 0xff
+; GFX9-NEXT: s_lshl_b32 s77, s9, 8
+; GFX9-NEXT: s_or_b32 s77, s77, s4
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s77
; GFX9-NEXT: s_and_b32 s5, s72, 0xff
; GFX9-NEXT: s_lshl_b32 s77, s62, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_and_b32 s77, s56, 0xff
-; GFX9-NEXT: s_or_b32 s77, s77, s78
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s77
+; GFX9-NEXT: s_or_b32 s77, s77, s5
+; GFX9-NEXT: s_and_b32 s5, s56, 0xff
+; GFX9-NEXT: s_lshl_b32 s78, s44, 8
+; GFX9-NEXT: s_or_b32 s78, s78, s5
+; GFX9-NEXT: s_pack_ll_b32_b16 s5, s77, s78
; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: v_mov_b32_e32 v10, s5
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: v_mov_b32_e32 v63, v36
; GFX9-NEXT: s_branch .LBB93_3
; GFX9-NEXT: .LBB93_2:
-; GFX9-NEXT: v_mov_b32_e32 v54, v61
+; GFX9-NEXT: v_mov_b32_e32 v54, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v32
; GFX9-NEXT: v_mov_b32_e32 v51, v49
; GFX9-NEXT: v_mov_b32_e32 v39, v52
@@ -174888,7 +173962,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: s_add_i32 s74, s74, 3
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_add_i32 s72, s72, 3
; GFX9-NEXT: s_add_i32 s56, s56, 3
; GFX9-NEXT: s_add_i32 s60, s60, 3
@@ -174917,76 +173991,75 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; GFX9-NEXT: v_add_u32_e32 v0, 3, v63
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v38, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v62, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v54, s4
; GFX9-NEXT: v_add_u32_e32 v63, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v31, 0x300, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v30, 0x300, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v35, s4
@@ -174996,12 +174069,12 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v28, 0x300, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v49, s4
; GFX9-NEXT: v_add_u32_e32 v27, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
@@ -175009,9 +174082,9 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_add_u32_e32 v0, 3, v32
; GFX9-NEXT: v_perm_b32 v0, v0, v58, s4
; GFX9-NEXT: v_add_u32_e32 v25, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v32, s23
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v42, s4
@@ -175045,18 +174118,18 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_and_b32_e32 v23, 0xffff, v26
; GFX9-NEXT: v_lshl_or_b32 v23, v25, 16, v23
; GFX9-NEXT: v_and_b32_e32 v25, 0xffff, v30
-; GFX9-NEXT: v_lshl_or_b32 v25, v29, 16, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v24, 0xffff, v28
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v25, v29, 16, v25
; GFX9-NEXT: v_lshl_or_b32 v24, v27, 16, v24
; GFX9-NEXT: v_and_b32_e32 v27, 0xffff, v63
; GFX9-NEXT: v_and_b32_e32 v19, 0xffff, v19
; GFX9-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX9-NEXT: v_lshl_or_b32 v19, v52, 16, v19
; GFX9-NEXT: v_lshl_or_b32 v20, v49, 16, v20
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
@@ -175068,6 +174141,10 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX9-NEXT: v_lshl_or_b32 v18, v37, 16, v18
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; GFX9-NEXT: v_and_b32_e32 v28, 0xffff, v38
+; GFX9-NEXT: v_lshl_or_b32 v28, v62, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -175086,7 +174163,7 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v16, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -175237,12 +174314,12 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_and_b32_e32 v32, 0xffff, v54
; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v32
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_and_b32_e32 v29, 0xffff, v29
; GFX9-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: v_lshl_or_b32 v26, v31, 16, v26
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v29, 0xffff, v29
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v0, s18, v34, v0
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
@@ -175254,8 +174331,6 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
-; GFX9-NEXT: v_and_b32_e32 v28, 0xffff, v38
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v33
; GFX9-NEXT: v_lshl_or_b32 v2, v61, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v3, v60, 16, v3
@@ -175267,10 +174342,8 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX9-NEXT: v_lshl_or_b32 v9, v46, 16, v9
; GFX9-NEXT: v_lshl_or_b32 v10, v45, 16, v10
; GFX9-NEXT: v_lshl_or_b32 v11, v44, 16, v11
-; GFX9-NEXT: v_lshl_or_b32 v28, v62, 16, v28
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_and_b32_e32 v30, 0xffff, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v30, 0xffff, v30
; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -175299,10 +174372,12 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v64f16_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
+; GFX11-TRUE16-NEXT: s_clause 0x2 ; 12-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:328
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:324
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:320
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:308
@@ -175423,156 +174498,136 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB93_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s63, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s57, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xff, v117
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s76
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s56, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s8, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s11, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s78
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v13, 0xff, v68
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s41, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s79
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s10, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v164
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s46, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v114
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v64, 8, v24
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v131
+; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s47, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s78
+; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s13, 8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v37, 8, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xff, v38
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v119, 8, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v144
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v70, 8, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v82, 8, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v167
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s76
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v53, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v66, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s88, s78
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v71, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v32, 8, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v69, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v87, 8, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v10.l
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v29, 0xff, v149
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v84, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v128, 8, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v162
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v98, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v113, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v19.l
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v118, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v179
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v21.l
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v101, 8, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v132, 8, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v23.l
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v86, 8, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v150, 8, v30
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v50
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v160
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v165
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xff, v166
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v33, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v183, v102, 8, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v41, v129, 8, v30
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v42, v133, 8, v31
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v39, 8, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v178, 8, v40
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, s79
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s77
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v29.h, v183.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v41.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v42.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB93_3
; GFX11-TRUE16-NEXT: .LBB93_2: ; %cmp.true
@@ -175805,9 +174860,10 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v129.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.h, v133.l
; GFX11-TRUE16-NEXT: .LBB93_3: ; %end
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-TRUE16-NEXT: s_clause 0x2 ; 12-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:328
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB93_4:
@@ -175818,7 +174874,10 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v64f16_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
+; GFX11-FAKE16-NEXT: ; meta instruction
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:308
@@ -175941,193 +175000,174 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s74, 0xff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v33
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v48
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v49
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v96, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v68, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s11, s8, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s7, s5, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s42, s15, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s44, s41, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v9, 16, v10
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s76, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v35, 8, s76
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s14, s10, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s76
; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s43, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-FAKE16-NEXT: s_lshl_b32 s76, s13, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v38
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s78
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v37
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s77, s76
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v33, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v36, 8, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v70, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v53
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v48
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v67, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v113, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v37, 8, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v32, 8, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v9, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v36
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v11, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v50
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v14, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v82, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v13
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v82, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v34, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v14, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v9, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v96, v85, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v71, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v83, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v117
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v146, v128, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v160
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v144
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v10, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v9, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v71, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v16, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v83, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v148
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v9, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v19, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v87, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v135
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v86, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v147, 8, v26
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v162, v145, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v150
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v179, v163, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v116, v103, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v100, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s76, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v132, v129, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s13, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v11, 16, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v113, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v20, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v101, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v11, 16, v22
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v134
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v119
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-FAKE16-NEXT: s_and_b32 s77, s62, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s59, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s45, 8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v24, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v114
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v24, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s63, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s61, 8
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v147
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v182, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v132, v129, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v115, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v22, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v134
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v26, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v133
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v119, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v117, 8, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v26, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v177
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v164
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v131
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s79, 16, v10
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s59, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v114, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v25
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s77
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s45, 8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v144, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v149
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s63, 0xff
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s79, s77
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s61, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v177
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v133, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v151
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v28, v29
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s78
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v164, 8, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v10, 16, v27
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v135, 8, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v176
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v161
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v28, v29
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v179, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v165
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v29, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v178
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v166
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v11, v31
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v161, 8, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v178
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v180
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v165, 8, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v183, v150, 8, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s79, 16, v8
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v40
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v41, v166, 8, v30
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v41, 16, v31
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v183, 16, v40
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB93_3
; GFX11-FAKE16-NEXT: .LBB93_2: ; %cmp.true
@@ -176392,7 +175432,9 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v34
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v35
; GFX11-FAKE16-NEXT: .LBB93_3: ; %end
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
+; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB93_4:
@@ -184207,8 +183249,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
@@ -184431,231 +183473,237 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: s_lshr_b64 s[36:37], s[44:45], 24
; GFX9-NEXT: s_cbranch_execnz .LBB95_4
; GFX9-NEXT: .LBB95_2: ; %cmp.true
-; GFX9-NEXT: v_mov_b32_e32 v15, 0x200
-; GFX9-NEXT: v_pk_add_f16 v26, s5, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v25, s4, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v20, s45, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v19, s44, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v14, s43, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v13, s42, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v12, s41, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v11, s40, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v10, s15, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v9, s14, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v8, s13, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v7, s12, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v6, s11, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v5, s10, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v4, s9, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v3, s8, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v2, s7, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v1, s6, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v49, s17, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v48, s16, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v38, s19, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v37, s18, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v36, s21, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v35, s20, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v34, s23, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v33, s22, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v32, s25, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v31, s24, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v30, s27, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v29, s26, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v28, s29, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v27, s28, v15 op_sel_hi:[1,0]
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[25:26]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[27:28]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[29:30]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[31:32]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[33:34]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[35:36]
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v38
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v38
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v49
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v49
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v1
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, 0x200
+; GFX9-NEXT: v_pk_add_f16 v24, s5, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v23, s4, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v16, s45, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v15, s44, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v14, s43, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v13, s42, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v12, s41, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v11, s40, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v10, s15, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v9, s14, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v8, s13, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v7, s12, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v6, s11, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v5, s10, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v4, s9, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v3, s8, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v2, s7, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v1, s6, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v38, s17, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v37, s16, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v36, s19, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v35, s18, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v34, s21, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v33, s20, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v32, s23, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v31, s22, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v30, s25, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v29, s24, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v28, s27, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v27, s26, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v26, s29, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v25, s28, v17 op_sel_hi:[1,0]
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[23:24]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[25:26]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[27:28]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v4
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v4
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[29:30]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v3
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[5:6]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v3
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v6
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[31:32]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v6
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[7:8]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v6
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v5
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[33:34]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v5
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[9:10]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v8
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[35:36]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v8
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[11:12]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v7
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v7
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[37:38]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v10
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[13:14]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v10
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v10
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v9
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[19:20]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v9
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v12
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v12
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v26
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v12
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v26
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v11
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v26
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v11
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v25
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v28
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v28
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v30
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v30
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v13
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v32
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v20
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v32
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX9-NEXT: v_lshrrev_b64 v[43:44], 24, v[37:38]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v34
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 24, v36
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v20
-; GFX9-NEXT: v_lshrrev_b64 v[44:45], 24, v[48:49]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v36
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v25
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v28
-; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v27
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[3:4]
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v38
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v38
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v2
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[5:6]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v2
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v3
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[7:8]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v3
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v6
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v6
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[9:10]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v6
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v5
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v5
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[11:12]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v8
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v8
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[13:14]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v7
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v10
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v10
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v10
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v24
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v9
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v24
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v12
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v24
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v12
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v23
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v12
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v23
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v11
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v26
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v11
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v26
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v14
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v28
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v14
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v28
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v14
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v30
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v13
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v30
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v13
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v32
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v16
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v16
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v34
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 24, v36
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v16
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v34
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v36
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v15
+; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v26
+; GFX9-NEXT: v_lshrrev_b32_e32 v45, 16, v25
+; GFX9-NEXT: v_lshrrev_b32_e32 v54, 8, v25
+; GFX9-NEXT: v_lshrrev_b32_e32 v39, 8, v28
+; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v27
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 8, v27
-; GFX9-NEXT: v_lshrrev_b32_e32 v56, 8, v30
-; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v29
-; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v29
-; GFX9-NEXT: v_lshrrev_b32_e32 v59, 8, v32
+; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v30
+; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v29
+; GFX9-NEXT: v_lshrrev_b32_e32 v56, 8, v29
+; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v31
-; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v31
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v23, 8, v34
-; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v33
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v33
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 8, v36
-; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v35
-; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v35
-; GFX9-NEXT: v_lshrrev_b32_e32 v24, 8, v38
-; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v37
-; GFX9-NEXT: v_lshrrev_b32_e32 v52, 8, v37
-; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v49
-; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v48
-; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v48
+; GFX9-NEXT: v_lshrrev_b32_e32 v59, 8, v31
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v34
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v33
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v36
+; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v35
+; GFX9-NEXT: v_lshrrev_b32_e32 v20, 8, v35
+; GFX9-NEXT: v_lshrrev_b32_e32 v49, 8, v38
+; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v37
+; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v37
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 24, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v41, 8, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v45, 8, v1
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v19
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v43, 8, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v44, 16, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v15
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; GFX9-NEXT: s_branch .LBB95_5
; GFX9-NEXT: .LBB95_3:
; GFX9-NEXT: ; implicit-def: $sgpr46
@@ -184806,225 +183854,253 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: s_branch .LBB95_2
; GFX9-NEXT: .LBB95_4:
-; GFX9-NEXT: v_mov_b32_e32 v15, s81
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s71
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s80
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s70
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s69
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s68
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s66
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s67
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s65
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s64
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s55
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s53
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s54
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s52
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s51
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s50
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s48
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s49
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s39
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s38
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s99
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s97
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s98
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s96
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s87
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s86
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s84
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s85
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s83
-; GFX9-NEXT: v_mov_b32_e32 v25, s4
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s82
+; GFX9-NEXT: v_mov_b32_e32 v17, s81
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s71
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s80
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s70
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s69
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s68
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s66
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s67
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s65
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s64
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s55
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s53
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s54
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s52
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s51
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s50
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s48
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s49
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s39
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s38
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s99
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s97
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s98
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s96
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s87
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s86
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s84
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s85
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s83
+; GFX9-NEXT: v_mov_b32_e32 v23, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s82
; GFX9-NEXT: v_readlane_b32 s4, v62, 0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 1
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 2
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v21, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 3
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v44, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 4
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 5
-; GFX9-NEXT: v_mov_b32_e32 v22, s4
+; GFX9-NEXT: v_mov_b32_e32 v53, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 6
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v51, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 7
-; GFX9-NEXT: v_mov_b32_e32 v45, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 8
-; GFX9-NEXT: v_mov_b32_e32 v41, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 9
; GFX9-NEXT: v_mov_b32_e32 v42, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 10
-; GFX9-NEXT: v_mov_b32_e32 v55, s4
+; GFX9-NEXT: v_mov_b32_e32 v50, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 11
-; GFX9-NEXT: v_mov_b32_e32 v39, s4
+; GFX9-NEXT: v_mov_b32_e32 v52, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 12
-; GFX9-NEXT: v_mov_b32_e32 v50, s4
+; GFX9-NEXT: v_mov_b32_e32 v49, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 13
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 15
-; GFX9-NEXT: v_mov_b32_e32 v52, s4
+; GFX9-NEXT: v_mov_b32_e32 v20, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 16
-; GFX9-NEXT: v_mov_b32_e32 v54, s4
+; GFX9-NEXT: v_mov_b32_e32 v22, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 17
-; GFX9-NEXT: v_mov_b32_e32 v24, s4
+; GFX9-NEXT: v_mov_b32_e32 v19, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 18
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 19
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 20
-; GFX9-NEXT: v_mov_b32_e32 v21, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 21
; GFX9-NEXT: v_mov_b32_e32 v18, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 22
-; GFX9-NEXT: v_mov_b32_e32 v16, s4
+; GFX9-NEXT: v_mov_b32_e32 v61, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 23
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 24
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 25
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v59, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 26
-; GFX9-NEXT: v_mov_b32_e32 v61, s4
+; GFX9-NEXT: v_mov_b32_e32 v60, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 27
-; GFX9-NEXT: v_mov_b32_e32 v23, s4
+; GFX9-NEXT: v_mov_b32_e32 v58, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 28
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 29
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 30
-; GFX9-NEXT: v_mov_b32_e32 v53, s4
+; GFX9-NEXT: v_mov_b32_e32 v56, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 31
-; GFX9-NEXT: v_mov_b32_e32 v60, s4
+; GFX9-NEXT: v_mov_b32_e32 v57, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 32
-; GFX9-NEXT: v_mov_b32_e32 v59, s4
+; GFX9-NEXT: v_mov_b32_e32 v47, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 33
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 34
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 35
-; GFX9-NEXT: v_mov_b32_e32 v57, s4
+; GFX9-NEXT: v_mov_b32_e32 v46, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 36
-; GFX9-NEXT: v_mov_b32_e32 v58, s4
+; GFX9-NEXT: v_mov_b32_e32 v48, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 37
-; GFX9-NEXT: v_mov_b32_e32 v56, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 38
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: v_mov_b32_e32 v54, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 39
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v54, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 40
-; GFX9-NEXT: v_mov_b32_e32 v46, s4
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v54, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 41
-; GFX9-NEXT: v_mov_b32_e32 v47, s4
+; GFX9-NEXT: v_mov_b32_e32 v45, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 42
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: v_mov_b32_e32 v55, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 43
-; GFX9-NEXT: v_mov_b32_e32 v51, s4
+; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 44
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s4
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 45
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s4
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 46
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s4
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 47
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 48
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 49
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s4
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s46
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s56
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s58
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s60
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s62
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s72
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v43, v53
+; GFX9-NEXT: v_mov_b32_e32 v53, v21
+; GFX9-NEXT: v_mov_b32_e32 v21, s92
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v40, s74
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v21, s94
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v40, s76
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v21, s30
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s78
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v21, s34
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s88
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v19, s44
-; GFX9-NEXT: v_mov_b32_e32 v20, s45
+; GFX9-NEXT: v_mov_b32_e32 v41, s90
+; GFX9-NEXT: v_mov_b32_e32 v21, s36
+; GFX9-NEXT: v_mov_b32_e32 v15, s44
+; GFX9-NEXT: v_mov_b32_e32 v16, s45
; GFX9-NEXT: v_mov_b32_e32 v13, s42
; GFX9-NEXT: v_mov_b32_e32 v14, s43
; GFX9-NEXT: v_mov_b32_e32 v11, s40
@@ -185039,78 +184115,50 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: v_mov_b32_e32 v4, s9
; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s7
-; GFX9-NEXT: v_mov_b32_e32 v48, s16
-; GFX9-NEXT: v_mov_b32_e32 v49, s17
-; GFX9-NEXT: v_mov_b32_e32 v37, s18
-; GFX9-NEXT: v_mov_b32_e32 v38, s19
-; GFX9-NEXT: v_mov_b32_e32 v35, s20
-; GFX9-NEXT: v_mov_b32_e32 v36, s21
-; GFX9-NEXT: v_mov_b32_e32 v33, s22
-; GFX9-NEXT: v_mov_b32_e32 v34, s23
-; GFX9-NEXT: v_mov_b32_e32 v31, s24
-; GFX9-NEXT: v_mov_b32_e32 v32, s25
-; GFX9-NEXT: v_mov_b32_e32 v29, s26
-; GFX9-NEXT: v_mov_b32_e32 v30, s27
-; GFX9-NEXT: v_mov_b32_e32 v27, s28
-; GFX9-NEXT: v_mov_b32_e32 v28, s29
-; GFX9-NEXT: v_mov_b32_e32 v26, s5
-; GFX9-NEXT: v_mov_b32_e32 v43, s74
-; GFX9-NEXT: v_mov_b32_e32 v44, s76
-; GFX9-NEXT: v_mov_b32_e32 v40, v41
-; GFX9-NEXT: v_mov_b32_e32 v41, v45
-; GFX9-NEXT: v_mov_b32_e32 v45, v22
-; GFX9-NEXT: v_mov_b32_e32 v22, s90
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v22, s92
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v22, s94
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v22, s30
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v22, s34
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v37, s16
+; GFX9-NEXT: v_mov_b32_e32 v38, s17
+; GFX9-NEXT: v_mov_b32_e32 v35, s18
+; GFX9-NEXT: v_mov_b32_e32 v36, s19
+; GFX9-NEXT: v_mov_b32_e32 v33, s20
+; GFX9-NEXT: v_mov_b32_e32 v34, s21
+; GFX9-NEXT: v_mov_b32_e32 v31, s22
+; GFX9-NEXT: v_mov_b32_e32 v32, s23
+; GFX9-NEXT: v_mov_b32_e32 v29, s24
+; GFX9-NEXT: v_mov_b32_e32 v30, s25
+; GFX9-NEXT: v_mov_b32_e32 v27, s26
+; GFX9-NEXT: v_mov_b32_e32 v28, s27
+; GFX9-NEXT: v_mov_b32_e32 v25, s28
+; GFX9-NEXT: v_mov_b32_e32 v26, s29
+; GFX9-NEXT: v_mov_b32_e32 v24, s5
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v22, s36
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; GFX9-NEXT: .LBB95_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v37, v37, v52, s4
-; GFX9-NEXT: v_perm_b32 v31, v31, v53, s4
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v33, v33, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v21, v35, v21, s4
-; GFX9-NEXT: v_perm_b32 v16, v36, v16, s4
-; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v24, v38, v24, s4
-; GFX9-NEXT: v_perm_b32 v17, v28, v17, s4
-; GFX9-NEXT: v_perm_b32 v48, v48, v55, s4
-; GFX9-NEXT: v_perm_b32 v49, v49, v50, s4
-; GFX9-NEXT: v_perm_b32 v50, v54, v43, s4
-; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v39, v39, v44, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; GFX9-NEXT: v_or_b32_e32 v39, v48, v39
-; GFX9-NEXT: v_perm_b32 v23, v34, v23, s4
-; GFX9-NEXT: v_perm_b32 v32, v32, v59, s4
-; GFX9-NEXT: v_perm_b32 v29, v29, v57, s4
-; GFX9-NEXT: v_perm_b32 v30, v30, v56, s4
+; GFX9-NEXT: v_perm_b32 v37, v37, v50, s4
+; GFX9-NEXT: v_perm_b32 v38, v38, v49, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v20, v35, v20, s4
+; GFX9-NEXT: v_perm_b32 v19, v36, v19, s4
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v33, v17, s4
+; GFX9-NEXT: v_perm_b32 v33, v34, v61, s4
+; GFX9-NEXT: v_perm_b32 v28, v28, v39, s4
+; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v31, v31, v59, s4
+; GFX9-NEXT: v_perm_b32 v32, v32, v58, s4
+; GFX9-NEXT: v_perm_b32 v29, v29, v56, s4
+; GFX9-NEXT: v_perm_b32 v30, v30, v47, s4
; GFX9-NEXT: v_perm_b32 v27, v27, v46, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v45, s4
+; GFX9-NEXT: v_perm_b32 v25, v25, v54, s4
+; GFX9-NEXT: v_perm_b32 v26, v26, v55, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v43, s4
; GFX9-NEXT: v_readlane_b32 s30, v63, 34
; GFX9-NEXT: v_readlane_b32 s31, v63, 35
; GFX9-NEXT: v_readlane_b32 s99, v63, 33
@@ -185147,274 +184195,254 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: v_readlane_b32 s36, v63, 2
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v36, v58, v52, s4
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v22, v25, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v35, v61, v35, s4
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_perm_b32 v18, v18, v54, s4
-; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v18, v21, v18
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_perm_b32 v38, v47, v52, s4
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_perm_b32 v25, v26, v15, s4
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_perm_b32 v34, v60, v54, s4
+; GFX9-NEXT: s_waitcnt vmcnt(5)
+; GFX9-NEXT: v_perm_b32 v22, v22, v49, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v20, v22, 16, v20
+; GFX9-NEXT: s_waitcnt vmcnt(5)
+; GFX9-NEXT: v_perm_b32 v18, v18, v35, s4
+; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: v_perm_b32 v52, v52, v40, s4
+; GFX9-NEXT: v_lshl_or_b32 v37, v52, 16, v37
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v36, v48, v49, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v34, v60, v34, s4
+; GFX9-NEXT: v_perm_b32 v35, v57, v35, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v28, v51, v52, s4
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v39, v45, v48, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v21, v21, v48, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v23, v23, v48, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v26, v15, v51, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v24, v24, v48, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v19, v19, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v48, v49, v48, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v20, v20, v15, s4
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v15, v15, v49, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v15, v48, 16, v15
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v15, v15, v51, s4
-; GFX9-NEXT: buffer_store_dword v39, v0, s[0:3], 0 offen
-; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v16, v16, v49, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v49, v50, v49, s4
+; GFX9-NEXT: buffer_store_dword v37, v0, s[0:3], 0 offen
+; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v39, v39, v48, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; GFX9-NEXT: v_or_b32_e32 v39, v49, v39
-; GFX9-NEXT: buffer_store_dword v39, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v50
-; GFX9-NEXT: v_or_b32_e32 v37, v37, v39
-; GFX9-NEXT: buffer_store_dword v37, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v37, v37, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; GFX9-NEXT: v_or_b32_e32 v24, v24, v37
-; GFX9-NEXT: buffer_store_dword v24, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: buffer_store_dword v18, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v37, v37, v50, s4
+; GFX9-NEXT: v_lshl_or_b32 v37, v37, 16, v38
+; GFX9-NEXT: buffer_store_dword v37, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: buffer_store_dword v20, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v18, v18, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v18
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v35
-; GFX9-NEXT: v_or_b32_e32 v16, v33, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v20, v20, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; GFX9-NEXT: buffer_store_dword v19, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v34
-; GFX9-NEXT: v_or_b32_e32 v16, v31, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v33
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: v_lshl_or_b32 v17, v34, 16, v31
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v32, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v36
-; GFX9-NEXT: v_or_b32_e32 v16, v29, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v32
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: v_lshl_or_b32 v17, v35, 16, v29
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v30, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v38
-; GFX9-NEXT: v_or_b32_e32 v16, v27, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v30
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: v_lshl_or_b32 v17, v36, 16, v27
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:40
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v28
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:44
+; GFX9-NEXT: v_lshl_or_b32 v17, v39, 16, v25
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:48
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v25, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX9-NEXT: v_or_b32_e32 v16, v19, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v26
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:52
+; GFX9-NEXT: v_lshl_or_b32 v17, v21, 16, v23
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:56
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v20, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v24
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:60
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:64
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v15, v15, v17, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:68
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_perm_b32 v13, v13, v15, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v49, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v14, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v11, v13, s4
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:80
-; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:84
-; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v9, v11, s4
-; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:88
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v10, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:92
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v9, s4
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:96
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:100
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v5, v7, s4
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:104
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v6, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:108
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v3, v5, s4
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:112
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v3, v4, v53, s4
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v44, v4, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_perm_b32 v3, v51, v3, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
-; GFX9-NEXT: v_perm_b32 v1, v2, v41, s4
-; GFX9-NEXT: v_perm_b32 v2, v40, v42, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v2, v2, v42, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -185431,8 +184459,8 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
-; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -185694,134 +184722,134 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
; GFX11-NEXT: s_cbranch_vccnz .LBB95_4
; GFX11-NEXT: .LBB95_2: ; %cmp.true
-; GFX11-NEXT: v_pk_add_f16 v28, 0x200, s19 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s27 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s26 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v27, 0x200, s18 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v30, 0x200, s17 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v29, 0x200, s16 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s5 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s4 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v20, 0x200, s25 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v19, 0x200, s24 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s7 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s6 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v22, 0x200, s23 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s22 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s9 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s8 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v24, 0x200, s21 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s20 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s11 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s10 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v32, 0x200, s1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v31, 0x200, s0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v26, 0x200, s19 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v25, 0x200, s18 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s41 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s40 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v10, 0x200, s13 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s12 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s9 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s8 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v34, 0x200, s3 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v33, 0x200, s2 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v22, 0x200, s23 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v21, 0x200, s22 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v28, 0x200, s17 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v27, 0x200, s16 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b64 v[48:49], 24, v[17:18]
; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s29 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s28 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s15 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s14 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s11 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s10 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s7 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s6 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s5 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s4 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v36, 0x200, s1 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v35, 0x200, s0 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v24, 0x200, s21 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v23, 0x200, s20 op_sel_hi:[0,1]
-; GFX11-NEXT: v_lshrrev_b64 v[51:52], 24, v[17:18]
-; GFX11-NEXT: v_lshrrev_b64 v[64:65], 24, v[27:28]
-; GFX11-NEXT: v_lshrrev_b64 v[52:53], 24, v[19:20]
-; GFX11-NEXT: v_lshrrev_b64 v[65:66], 24, v[29:30]
-; GFX11-NEXT: v_lshrrev_b64 v[53:54], 24, v[21:22]
-; GFX11-NEXT: v_lshrrev_b64 v[69:70], 24, v[33:34]
-; GFX11-NEXT: v_lshrrev_b64 v[37:38], 24, v[5:6]
-; GFX11-NEXT: v_lshrrev_b64 v[48:49], 24, v[9:10]
-; GFX11-NEXT: v_lshrrev_b64 v[66:67], 24, v[13:14]
-; GFX11-NEXT: v_lshrrev_b64 v[54:55], 24, v[23:24]
-; GFX11-NEXT: v_lshrrev_b64 v[70:71], 24, v[35:36]
-; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[1:2]
-; GFX11-NEXT: v_lshrrev_b64 v[31:32], 24, v[3:4]
-; GFX11-NEXT: v_lshrrev_b64 v[38:39], 24, v[7:8]
-; GFX11-NEXT: v_lshrrev_b64 v[49:50], 24, v[11:12]
-; GFX11-NEXT: v_lshrrev_b64 v[67:68], 24, v[15:16]
-; GFX11-NEXT: v_lshrrev_b32_e32 v148, 24, v18
+; GFX11-NEXT: v_pk_add_f16 v30, 0x200, s3 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v29, 0x200, s2 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b64 v[49:50], 24, v[19:20]
+; GFX11-NEXT: v_lshrrev_b64 v[33:34], 24, v[1:2]
+; GFX11-NEXT: v_lshrrev_b64 v[50:51], 24, v[21:22]
+; GFX11-NEXT: v_lshrrev_b64 v[34:35], 24, v[3:4]
+; GFX11-NEXT: v_lshrrev_b64 v[51:52], 24, v[23:24]
+; GFX11-NEXT: v_lshrrev_b64 v[35:36], 24, v[5:6]
+; GFX11-NEXT: v_lshrrev_b64 v[52:53], 24, v[25:26]
+; GFX11-NEXT: v_lshrrev_b64 v[64:65], 24, v[31:32]
+; GFX11-NEXT: v_lshrrev_b64 v[36:37], 24, v[7:8]
+; GFX11-NEXT: v_lshrrev_b64 v[53:54], 24, v[27:28]
+; GFX11-NEXT: v_lshrrev_b64 v[37:38], 24, v[9:10]
+; GFX11-NEXT: v_lshrrev_b64 v[65:66], 24, v[13:14]
+; GFX11-NEXT: v_lshrrev_b64 v[54:55], 24, v[29:30]
+; GFX11-NEXT: v_lshrrev_b64 v[38:39], 24, v[11:12]
+; GFX11-NEXT: v_lshrrev_b64 v[66:67], 24, v[15:16]
+; GFX11-NEXT: v_lshrrev_b32_e32 v160, 24, v18
; GFX11-NEXT: v_lshrrev_b32_e32 v147, 16, v18
; GFX11-NEXT: v_lshrrev_b32_e32 v146, 8, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v160, 16, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v151, 16, v17
; GFX11-NEXT: v_lshrrev_b32_e32 v150, 8, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v162, 24, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v161, 16, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v149, 8, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v163, 16, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v151, 8, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v166, 24, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v163, 24, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v149, 16, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v148, 8, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v162, 16, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v161, 8, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v178, 24, v22
; GFX11-NEXT: v_lshrrev_b32_e32 v165, 16, v22
; GFX11-NEXT: v_lshrrev_b32_e32 v164, 8, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v178, 16, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v177, 16, v21
; GFX11-NEXT: v_lshrrev_b32_e32 v176, 8, v21
-; GFX11-NEXT: v_lshrrev_b32_e32 v180, 24, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v179, 16, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v167, 8, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v181, 16, v23
-; GFX11-NEXT: v_lshrrev_b32_e32 v177, 8, v23
-; GFX11-NEXT: v_lshrrev_b32_e32 v42, 24, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v181, 24, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v167, 16, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v166, 8, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v180, 16, v23
+; GFX11-NEXT: v_lshrrev_b32_e32 v179, 8, v23
+; GFX11-NEXT: v_lshrrev_b32_e32 v44, 24, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v183, 16, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v182, 8, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v43, 16, v25
+; GFX11-NEXT: v_lshrrev_b32_e32 v42, 8, v25
+; GFX11-NEXT: v_lshrrev_b32_e32 v47, 24, v28
; GFX11-NEXT: v_lshrrev_b32_e32 v41, 16, v28
-; GFX11-NEXT: v_lshrrev_b32_e32 v183, 8, v28
-; GFX11-NEXT: v_lshrrev_b32_e32 v43, 16, v27
-; GFX11-NEXT: v_lshrrev_b32_e32 v182, 8, v27
-; GFX11-NEXT: v_lshrrev_b32_e32 v46, 24, v30
-; GFX11-NEXT: v_lshrrev_b32_e32 v44, 16, v30
-; GFX11-NEXT: v_lshrrev_b32_e32 v40, 8, v30
-; GFX11-NEXT: v_lshrrev_b32_e32 v47, 16, v29
-; GFX11-NEXT: v_lshrrev_b32_e32 v45, 8, v29
-; GFX11-NEXT: v_lshrrev_b32_e32 v59, 24, v34
-; GFX11-NEXT: v_lshrrev_b32_e32 v58, 16, v34
-; GFX11-NEXT: v_lshrrev_b32_e32 v57, 8, v34
-; GFX11-NEXT: v_lshrrev_b32_e32 v60, 16, v33
-; GFX11-NEXT: v_lshrrev_b32_e32 v56, 8, v33
-; GFX11-NEXT: v_lshrrev_b32_e32 v72, 24, v36
-; GFX11-NEXT: v_lshrrev_b32_e32 v62, 16, v36
-; GFX11-NEXT: v_lshrrev_b32_e32 v61, 8, v36
-; GFX11-NEXT: v_lshrrev_b32_e32 v73, 16, v35
-; GFX11-NEXT: v_lshrrev_b32_e32 v63, 8, v35
-; GFX11-NEXT: v_lshrrev_b32_e32 v50, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v40, 8, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v46, 16, v27
+; GFX11-NEXT: v_lshrrev_b32_e32 v45, 8, v27
+; GFX11-NEXT: v_lshrrev_b32_e32 v58, 24, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v57, 16, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v56, 8, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v63, 16, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v62, 8, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v72, 24, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v61, 16, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v60, 8, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v73, 16, v31
+; GFX11-NEXT: v_lshrrev_b32_e32 v59, 8, v31
+; GFX11-NEXT: v_lshrrev_b32_e32 v55, 24, v2
; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v81, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v82, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v86, 24, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v97, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v87, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v100, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v99, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v96, 8, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v101, 16, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v98, 8, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v112, 24, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v103, 16, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v102, 8, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v115, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v113, 8, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v118, 24, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v117, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v114, 8, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v119, 16, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v116, 8, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v130, 24, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v129, 16, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v128, 8, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v133, 16, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v131, 8, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v144, 24, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v135, 16, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v132, 8, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v145, 16, v15
-; GFX11-NEXT: v_lshrrev_b32_e32 v134, 8, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v68, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v70, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v81, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v85, 24, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v86, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v96, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v98, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v97, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v99, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v100, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v101, 8, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v103, 24, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v102, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v112, 8, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v113, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v114, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v116, 24, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v115, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v117, 8, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v118, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v119, 8, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v129, 24, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v128, 16, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v130, 8, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v131, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v132, 8, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v134, 24, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v133, 16, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v135, 8, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v144, 16, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v145, 8, v15
; GFX11-NEXT: s_branch .LBB95_5
; GFX11-NEXT: .LBB95_3:
; GFX11-NEXT: ; implicit-def: $sgpr43
@@ -185962,287 +184990,255 @@ define inreg <128 x i8> @bitcast_v64f16_to_v128i8_scalar(<64 x half> inreg %a, i
; GFX11-NEXT: ; kill: killed $sgpr43
; GFX11-NEXT: s_branch .LBB95_2
; GFX11-NEXT: .LBB95_4:
-; GFX11-NEXT: v_dual_mov_b32 v35, s0 :: v_dual_mov_b32 v36, s1
+; GFX11-NEXT: v_dual_mov_b32 v31, s0 :: v_dual_mov_b32 v32, s1
; GFX11-NEXT: v_readlane_b32 s0, v76, 0
; GFX11-NEXT: v_dual_mov_b32 v15, s28 :: v_dual_mov_b32 v16, s29
; GFX11-NEXT: v_dual_mov_b32 v13, s40 :: v_dual_mov_b32 v14, s41
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v63, s0
+; GFX11-NEXT: v_mov_b32_e32 v59, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 1
; GFX11-NEXT: v_dual_mov_b32 v11, s14 :: v_dual_mov_b32 v12, s15
; GFX11-NEXT: v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, s13
; GFX11-NEXT: v_mov_b32_e32 v73, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 2
+; GFX11-NEXT: v_mov_b32_e32 v39, s34
; GFX11-NEXT: v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
; GFX11-NEXT: v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v61, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mov_b32_e32 v60, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 3
; GFX11-NEXT: v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
; GFX11-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5
-; GFX11-NEXT: v_mov_b32_e32 v62, s0
+; GFX11-NEXT: v_mov_b32_e32 v61, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 4
-; GFX11-NEXT: v_dual_mov_b32 v33, s2 :: v_dual_mov_b32 v34, s3
-; GFX11-NEXT: v_dual_mov_b32 v29, s16 :: v_dual_mov_b32 v30, s17
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mov_b32_e32 v55, vcc_hi
+; GFX11-NEXT: v_dual_mov_b32 v29, s2 :: v_dual_mov_b32 v30, s3
+; GFX11-NEXT: v_dual_mov_b32 v27, s16 :: v_dual_mov_b32 v28, s17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v72, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 5
-; GFX11-NEXT: v_dual_mov_b32 v27, s18 :: v_dual_mov_b32 v28, s19
+; GFX11-NEXT: v_dual_mov_b32 v25, s18 :: v_dual_mov_b32 v26, s19
; GFX11-NEXT: v_dual_mov_b32 v23, s20 :: v_dual_mov_b32 v24, s21
-; GFX11-NEXT: v_mov_b32_e32 v56, s0
+; GFX11-NEXT: v_mov_b32_e32 v62, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 6
; GFX11-NEXT: v_dual_mov_b32 v21, s22 :: v_dual_mov_b32 v22, s23
; GFX11-NEXT: v_dual_mov_b32 v19, s24 :: v_dual_mov_b32 v20, s25
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v60, s0
+; GFX11-NEXT: v_mov_b32_e32 v63, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 7
; GFX11-NEXT: v_dual_mov_b32 v17, s26 :: v_dual_mov_b32 v18, s27
-; GFX11-NEXT: v_dual_mov_b32 v134, s104 :: v_dual_mov_b32 v145, s102
-; GFX11-NEXT: v_mov_b32_e32 v57, s0
+; GFX11-NEXT: v_dual_mov_b32 v145, s104 :: v_dual_mov_b32 v144, s102
+; GFX11-NEXT: v_mov_b32_e32 v56, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 8
-; GFX11-NEXT: v_dual_mov_b32 v132, s103 :: v_dual_mov_b32 v135, s101
-; GFX11-NEXT: v_dual_mov_b32 v144, s100 :: v_dual_mov_b32 v131, s99
+; GFX11-NEXT: v_dual_mov_b32 v135, s103 :: v_dual_mov_b32 v134, s100
+; GFX11-NEXT: v_dual_mov_b32 v133, s101 :: v_dual_mov_b32 v132, s99
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v58, s0
+; GFX11-NEXT: v_mov_b32_e32 v57, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 9
-; GFX11-NEXT: v_dual_mov_b32 v133, s97 :: v_dual_mov_b32 v128, s98
-; GFX11-NEXT: v_dual_mov_b32 v129, s96 :: v_dual_mov_b32 v130, s87
-; GFX11-NEXT: v_mov_b32_e32 v59, s0
+; GFX11-NEXT: v_dual_mov_b32 v131, s97 :: v_dual_mov_b32 v130, s98
+; GFX11-NEXT: v_dual_mov_b32 v128, s96 :: v_dual_mov_b32 v129, s87
+; GFX11-NEXT: v_mov_b32_e32 v58, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 10
-; GFX11-NEXT: v_dual_mov_b32 v116, s86 :: v_dual_mov_b32 v119, s84
-; GFX11-NEXT: v_dual_mov_b32 v114, s85 :: v_dual_mov_b32 v117, s83
+; GFX11-NEXT: v_dual_mov_b32 v119, s86 :: v_dual_mov_b32 v118, s84
+; GFX11-NEXT: v_dual_mov_b32 v117, s85 :: v_dual_mov_b32 v116, s82
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v45, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 11
-; GFX11-NEXT: v_dual_mov_b32 v118, s82 :: v_dual_mov_b32 v113, s81
-; GFX11-NEXT: v_dual_mov_b32 v115, s71 :: v_dual_mov_b32 v102, s80
-; GFX11-NEXT: v_mov_b32_e32 v47, s0
+; GFX11-NEXT: v_dual_mov_b32 v115, s83 :: v_dual_mov_b32 v114, s81
+; GFX11-NEXT: v_dual_mov_b32 v113, s71 :: v_dual_mov_b32 v112, s80
+; GFX11-NEXT: v_mov_b32_e32 v46, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 12
-; GFX11-NEXT: v_dual_mov_b32 v103, s70 :: v_dual_mov_b32 v112, s69
-; GFX11-NEXT: v_dual_mov_b32 v98, s68 :: v_dual_mov_b32 v101, s66
+; GFX11-NEXT: v_dual_mov_b32 v102, s70 :: v_dual_mov_b32 v103, s69
+; GFX11-NEXT: v_dual_mov_b32 v101, s68 :: v_dual_mov_b32 v100, s66
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v40, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 13
-; GFX11-NEXT: v_dual_mov_b32 v96, s67 :: v_dual_mov_b32 v99, s65
-; GFX11-NEXT: v_dual_mov_b32 v100, s64 :: v_dual_mov_b32 v87, s55
-; GFX11-NEXT: v_mov_b32_e32 v44, s0
+; GFX11-NEXT: v_dual_mov_b32 v99, s67 :: v_dual_mov_b32 v98, s64
+; GFX11-NEXT: v_dual_mov_b32 v97, s65 :: v_dual_mov_b32 v96, s55
+; GFX11-NEXT: v_mov_b32_e32 v41, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 14
-; GFX11-NEXT: v_dual_mov_b32 v97, s53 :: v_dual_mov_b32 v86, s51
-; GFX11-NEXT: v_dual_mov_b32 v83, s54 :: v_dual_mov_b32 v82, s50
+; GFX11-NEXT: v_dual_mov_b32 v87, s53 :: v_dual_mov_b32 v86, s54
+; GFX11-NEXT: v_dual_mov_b32 v84, s52 :: v_dual_mov_b32 v85, s51
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v46, s0
+; GFX11-NEXT: v_mov_b32_e32 v47, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 15
-; GFX11-NEXT: v_dual_mov_b32 v85, s52 :: v_dual_mov_b32 v84, s48
-; GFX11-NEXT: v_dual_mov_b32 v55, s49 :: v_dual_mov_b32 v80, s39
-; GFX11-NEXT: v_mov_b32_e32 v182, s0
+; GFX11-NEXT: v_dual_mov_b32 v83, s50 :: v_dual_mov_b32 v82, s48
+; GFX11-NEXT: v_dual_mov_b32 v81, s49 :: v_dual_mov_b32 v80, s38
+; GFX11-NEXT: v_mov_b32_e32 v42, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 16
-; GFX11-NEXT: v_dual_mov_b32 v81, s38 :: v_dual_mov_b32 v32, s37
-; GFX11-NEXT: v_dual_mov_b32 v71, s35 :: v_dual_mov_b32 v26, s36
+; GFX11-NEXT: v_dual_mov_b32 v71, s39 :: v_dual_mov_b32 v70, s37
+; GFX11-NEXT: v_dual_mov_b32 v69, s35 :: v_dual_mov_b32 v68, s36
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v43, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 17
-; GFX11-NEXT: v_dual_mov_b32 v39, s34 :: v_dual_mov_b32 v50, vcc_hi
-; GFX11-NEXT: v_dual_mov_b32 v51, s72 :: v_dual_mov_b32 v52, s62
-; GFX11-NEXT: v_mov_b32_e32 v183, s0
+; GFX11-NEXT: v_dual_mov_b32 v49, s62 :: v_dual_mov_b32 v52, s56
+; GFX11-NEXT: v_dual_mov_b32 v51, s58 :: v_dual_mov_b32 v54, s44
+; GFX11-NEXT: v_mov_b32_e32 v182, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 18
-; GFX11-NEXT: v_dual_mov_b32 v53, s60 :: v_dual_mov_b32 v54, s58
-; GFX11-NEXT: v_dual_mov_b32 v64, s56 :: v_dual_mov_b32 v65, s46
+; GFX11-NEXT: v_dual_mov_b32 v53, s46 :: v_dual_mov_b32 v64, s42
+; GFX11-NEXT: v_dual_mov_b32 v33, s74 :: v_dual_mov_b32 v34, s76
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v41, s0
+; GFX11-NEXT: v_mov_b32_e32 v183, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 19
-; GFX11-NEXT: v_dual_mov_b32 v69, s44 :: v_dual_mov_b32 v70, s42
-; GFX11-NEXT: v_dual_mov_b32 v25, s74 :: v_dual_mov_b32 v38, s88
-; GFX11-NEXT: v_mov_b32_e32 v42, s0
+; GFX11-NEXT: v_dual_mov_b32 v35, s78 :: v_dual_mov_b32 v36, s88
+; GFX11-NEXT: v_dual_mov_b32 v37, s90 :: v_dual_mov_b32 v38, s92
+; GFX11-NEXT: v_mov_b32_e32 v44, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 20
-; GFX11-NEXT: v_dual_mov_b32 v31, s76 :: v_dual_mov_b32 v48, s90
-; GFX11-NEXT: v_dual_mov_b32 v37, s78 :: v_dual_mov_b32 v66, s94
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v177, s0
+; GFX11-NEXT: v_dual_mov_b32 v65, s94 :: v_dual_mov_b32 v66, s30
+; GFX11-NEXT: v_mov_b32_e32 v48, s72
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v50, s60 :: v_dual_mov_b32 v179, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 21
-; GFX11-NEXT: v_mov_b32_e32 v49, s92
-; GFX11-NEXT: v_mov_b32_e32 v67, s30
-; GFX11-NEXT: v_mov_b32_e32 v181, s0
+; GFX11-NEXT: v_mov_b32_e32 v180, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 22
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v167, s0
+; GFX11-NEXT: v_mov_b32_e32 v166, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 23
-; GFX11-NEXT: v_mov_b32_e32 v179, s0
+; GFX11-NEXT: v_mov_b32_e32 v167, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v180, s0
+; GFX11-NEXT: v_mov_b32_e32 v181, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 25
; GFX11-NEXT: v_mov_b32_e32 v176, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v178, s0
+; GFX11-NEXT: v_mov_b32_e32 v177, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 27
; GFX11-NEXT: v_mov_b32_e32 v164, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 28
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v165, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 29
-; GFX11-NEXT: v_mov_b32_e32 v166, s0
+; GFX11-NEXT: v_mov_b32_e32 v178, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 30
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v151, s0
+; GFX11-NEXT: v_mov_b32_e32 v161, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 31
-; GFX11-NEXT: v_mov_b32_e32 v163, s0
+; GFX11-NEXT: v_mov_b32_e32 v162, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v149, s0
+; GFX11-NEXT: v_mov_b32_e32 v148, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 1
-; GFX11-NEXT: v_mov_b32_e32 v161, s0
+; GFX11-NEXT: v_mov_b32_e32 v149, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v162, s0
+; GFX11-NEXT: v_mov_b32_e32 v163, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 3
; GFX11-NEXT: v_mov_b32_e32 v150, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v160, s0
+; GFX11-NEXT: v_mov_b32_e32 v151, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 5
; GFX11-NEXT: v_mov_b32_e32 v146, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v147, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 7
-; GFX11-NEXT: v_mov_b32_e32 v148, s0
+; GFX11-NEXT: v_mov_b32_e32 v160, s0
; GFX11-NEXT: .LBB95_5: ; %end
-; GFX11-NEXT: v_perm_b32 v68, v73, v70, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v70, v62, v72, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v69, v60, v69, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v70
-; GFX11-NEXT: v_perm_b32 v35, v35, v63, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
-; GFX11-NEXT: v_perm_b32 v56, v33, v56, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
-; GFX11-NEXT: v_perm_b32 v58, v58, v59, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v57, v34, v57, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v34, v36, v70
-; GFX11-NEXT: v_perm_b32 v29, v29, v45, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v65
-; GFX11-NEXT: v_perm_b32 v70, v27, v182, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
-; GFX11-NEXT: v_or_b32_e32 v33, v35, v68
-; GFX11-NEXT: v_or_b32_e32 v35, v56, v69
-; GFX11-NEXT: v_perm_b32 v68, v44, v46, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v69, v41, v42, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v58, 16, v58
-; GFX11-NEXT: v_or_b32_e32 v27, v29, v65
-; GFX11-NEXT: v_or_b32_e32 v29, v70, v64
-; GFX11-NEXT: v_perm_b32 v54, v181, v54, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v179, v180, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v53, v178, v53, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v30, v30, v40, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
-; GFX11-NEXT: v_perm_b32 v182, v28, v183, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
-; GFX11-NEXT: v_or_b32_e32 v36, v57, v58
-; GFX11-NEXT: v_perm_b32 v23, v23, v177, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT: v_perm_b32 v24, v24, v167, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
-; GFX11-NEXT: v_perm_b32 v21, v21, v176, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-NEXT: v_or_b32_e32 v28, v30, v68
-; GFX11-NEXT: v_or_b32_e32 v30, v182, v69
+; GFX11-NEXT: v_perm_b32 v29, v29, v62, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v54, v63, v54, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v73, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v31, v59, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v32, v60, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v67, v61, v72, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v61, v54, 16, v29
+; GFX11-NEXT: v_perm_b32 v29, v30, v56, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v57, v58, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v59, v64, 16, v31
+; GFX11-NEXT: v_lshl_or_b32 v60, v67, 16, v32
+; GFX11-NEXT: v_perm_b32 v27, v27, v45, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v46, v53, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v28, v40, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v41, v47, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v53, v25, v42, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v52, v43, v52, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v54, v26, v182, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v183, v44, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v62, v30, 16, v29
+; GFX11-NEXT: v_perm_b32 v23, v23, v179, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v180, v51, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v24, v166, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v167, v181, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v25, v31, 16, v27
+; GFX11-NEXT: v_lshl_or_b32 v26, v32, 16, v28
+; GFX11-NEXT: v_lshl_or_b32 v27, v52, 16, v53
+; GFX11-NEXT: v_lshl_or_b32 v28, v64, 16, v54
+; GFX11-NEXT: v_perm_b32 v31, v21, v176, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v177, v50, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v50, v22, v164, 0xc0c0004
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: scratch_store_b128 v0, v[33:36], off
-; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:16
-; GFX11-NEXT: v_or_b32_e32 v27, v23, v54
-; GFX11-NEXT: v_perm_b32 v23, v165, v166, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v28, v24, v64
-; GFX11-NEXT: v_or_b32_e32 v29, v21, v53
-; GFX11-NEXT: v_perm_b32 v21, v22, v164, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v22, v163, v52, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v161, v162, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v30, v160, v51, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v17, v17, v150, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v30
-; GFX11-NEXT: v_or_b32_e32 v30, v21, v23
-; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
-; GFX11-NEXT: v_perm_b32 v22, v147, v148, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v20, v20, v24
-; GFX11-NEXT: v_or_b32_e32 v21, v17, v33
-; GFX11-NEXT: v_perm_b32 v17, v18, v146, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v145, v67, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v133, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v135, v144, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_perm_b32 v15, v15, v134, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v13, v13, v131, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v16, v16, v132, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
-; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
-; GFX11-NEXT: v_perm_b32 v18, v129, v130, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v17, v13, v24
-; GFX11-NEXT: v_perm_b32 v24, v115, v48, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v23
-; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v14, v119, v49, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v117, v118, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v9, v9, v113, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v11, v11, v116, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v12, v12, v114, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v24
-; GFX11-NEXT: v_perm_b32 v9, v10, v102, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v101, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
-; GFX11-NEXT: v_perm_b32 v14, v103, v112, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v23
-; GFX11-NEXT: v_perm_b32 v23, v99, v100, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v97, v37, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v98, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v8, v8, v96, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_perm_b32 v5, v5, v87, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
-; GFX11-NEXT: v_perm_b32 v10, v85, v86, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v23
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v24
-; GFX11-NEXT: v_perm_b32 v5, v84, v31, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v80, v81, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v71, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v39, v50, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v83, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_perm_b32 v31, v1, v32, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v26, v2, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v23
-; GFX11-NEXT: v_or_b32_e32 v3, v31, v24
-; GFX11-NEXT: v_or_b32_e32 v4, v26, v25
+; GFX11-NEXT: scratch_store_b128 v0, v[59:62], off
+; GFX11-NEXT: scratch_store_b128 v0, v[25:28], off offset:16
+; GFX11-NEXT: v_lshl_or_b32 v21, v29, 16, v23
+; GFX11-NEXT: v_lshl_or_b32 v22, v30, 16, v24
+; GFX11-NEXT: v_perm_b32 v19, v19, v161, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v162, v49, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v20, v148, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v26, v149, v163, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v17, v150, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v151, v48, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v18, v146, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v147, v160, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v23, v32, 16, v31
+; GFX11-NEXT: v_perm_b32 v15, v15, v145, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v144, v66, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v17, v25, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v18, v26, 16, v20
+; GFX11-NEXT: v_lshl_or_b32 v19, v28, 16, v27
+; GFX11-NEXT: v_lshl_or_b32 v20, v30, 16, v29
+; GFX11-NEXT: v_perm_b32 v13, v13, v132, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v131, v65, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v11, v119, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v118, v38, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v25, v31, 16, v15
+; GFX11-NEXT: v_perm_b32 v15, v16, v135, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v133, v134, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v14, v14, v130, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v128, v129, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v27, v27, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v11, v29, 16, v11
+; GFX11-NEXT: v_perm_b32 v9, v9, v114, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v113, v37, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v96, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v87, v35, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v51, v165, v178, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v12, v117, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v115, v116, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v26, v16, 16, v15
+; GFX11-NEXT: v_perm_b32 v7, v7, v101, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v100, v36, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v8, v8, v99, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v97, v98, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v28, v28, 16, v14
+; GFX11-NEXT: v_perm_b32 v10, v10, v112, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v14, v102, v103, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v9, v29, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v86, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v84, v85, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v24, v51, 16, v50
+; GFX11-NEXT: v_lshl_or_b32 v12, v30, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v7, v15, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v8, v16, 16, v8
+; GFX11-NEXT: v_perm_b32 v3, v3, v83, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v82, v34, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v81, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v71, v80, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v1, v70, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v69, v33, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v2, v68, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v39, v55, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v10, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v1, v15, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v16, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v30, 16, v29
+; GFX11-NEXT: v_lshl_or_b32 v4, v32, 16, v31
; GFX11-NEXT: s_clause 0x5
-; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:32
-; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
-; GFX11-NEXT: scratch_store_b128 v0, v[15:18], off offset:64
+; GFX11-NEXT: scratch_store_b128 v0, v[21:24], off offset:32
+; GFX11-NEXT: scratch_store_b128 v0, v[17:20], off offset:48
+; GFX11-NEXT: scratch_store_b128 v0, v[25:28], off offset:64
; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:80
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:96
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:112
@@ -195198,7 +194194,6 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s47, v7
; GFX9-NEXT: v_readfirstlane_b32 s59, v6
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:332
-; GFX9-NEXT: v_readfirstlane_b32 s42, v13
; GFX9-NEXT: v_readfirstlane_b32 s74, v30
; GFX9-NEXT: v_readfirstlane_b32 s44, v29
; GFX9-NEXT: v_readfirstlane_b32 s56, v28
@@ -195216,6 +194211,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s58, v16
; GFX9-NEXT: v_readfirstlane_b32 s73, v15
; GFX9-NEXT: v_readfirstlane_b32 s75, v14
+; GFX9-NEXT: v_readfirstlane_b32 s42, v13
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:472 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:324
@@ -195236,26 +194232,28 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:300
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:492 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:296
+; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:296
; GFX9-NEXT: buffer_load_ushort v5, off, s[0:3], s32 offset:292
-; GFX9-NEXT: buffer_load_ushort v3, off, s[0:3], s32 offset:288
+; GFX9-NEXT: buffer_load_ushort v4, off, s[0:3], s32 offset:288
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:284
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:488 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:280
-; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:276
+; GFX9-NEXT: buffer_load_ushort v7, off, s[0:3], s32 offset:280
+; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:276
; GFX9-NEXT: buffer_load_ushort v6, off, s[0:3], s32 offset:272
; GFX9-NEXT: buffer_load_ushort v63, off, s[0:3], s32 offset:268
-; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:264
-; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:260
-; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:256
-; GFX9-NEXT: buffer_load_ushort v33, off, s[0:3], s32 offset:252
-; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:248
-; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:244
-; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:240
+; GFX9-NEXT: buffer_load_ushort v9, off, s[0:3], s32 offset:264
+; GFX9-NEXT: buffer_load_ushort v61, off, s[0:3], s32 offset:260
+; GFX9-NEXT: buffer_load_ushort v48, off, s[0:3], s32 offset:256
+; GFX9-NEXT: buffer_load_ushort v8, off, s[0:3], s32 offset:252
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:248
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:244
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v54, off, s[0:3], s32 offset:240
; GFX9-NEXT: buffer_load_ushort v43, off, s[0:3], s32 offset:236
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:232
@@ -195266,7 +194264,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:224
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:220
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Spill
@@ -195278,7 +194276,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:208
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:204
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
@@ -195292,13 +194290,11 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:508 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_ushort v0, off, s[0:3], s32 offset:192
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_ushort v13, off, s[0:3], s32 offset:188
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:444 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:188
; GFX9-NEXT: buffer_load_ushort v47, off, s[0:3], s32 offset:184
; GFX9-NEXT: buffer_load_ushort v59, off, s[0:3], s32 offset:180
; GFX9-NEXT: buffer_load_ushort v42, off, s[0:3], s32 offset:176
-; GFX9-NEXT: buffer_load_ushort v58, off, s[0:3], s32 offset:172
+; GFX9-NEXT: buffer_load_ushort v62, off, s[0:3], s32 offset:172
; GFX9-NEXT: buffer_load_ushort v44, off, s[0:3], s32 offset:168
; GFX9-NEXT: buffer_load_ushort v56, off, s[0:3], s32 offset:164
; GFX9-NEXT: buffer_load_ushort v60, off, s[0:3], s32 offset:160
@@ -195371,23 +194367,23 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:612 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:616 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:432 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:620 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:440 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v58, off, s[0:3], s32 offset:624 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:448 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v48, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:452 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:460 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:628 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:456 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v28, off, s[0:3], s32 offset:632 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v50, off, s[0:3], s32 offset:636 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:464 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v61, off, s[0:3], s32 offset:640 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v43, off, s[0:3], s32 offset:644 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:648 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v27, off, s[0:3], s32 offset:652 ; 4-byte Folded Spill
; GFX9-NEXT: s_cbranch_scc0 .LBB97_2
; GFX9-NEXT: ; %bb.1: ; %cmp.false
@@ -195436,38 +194432,37 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s73
; GFX9-NEXT: v_perm_b32 v7, s75, v7, v8
-; GFX9-NEXT: v_mov_b32_e32 v63, v33
; GFX9-NEXT: v_mov_b32_e32 v33, v9
; GFX9-NEXT: v_mov_b32_e32 v9, s45
; GFX9-NEXT: v_perm_b32 v9, s58, v9, v8
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v10
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
; GFX9-NEXT: v_perm_b32 v10, s74, v12, v8
-; GFX9-NEXT: v_or_b32_sdwa v9, v11, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v18
-; GFX9-NEXT: v_or_b32_sdwa v9, v22, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v13
-; GFX9-NEXT: v_or_b32_sdwa v10, v15, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v22
+; GFX9-NEXT: v_lshl_or_b32 v9, v18, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v15
+; GFX9-NEXT: v_lshl_or_b32 v10, v13, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_lshl_or_b32 v12, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v14
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v17
; GFX9-NEXT: v_perm_b32 v10, v26, v21, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v17, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v14, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v13, v9, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v25
-; GFX9-NEXT: v_or_b32_sdwa v9, v30, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v16
-; GFX9-NEXT: v_or_b32_sdwa v10, v20, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v30
+; GFX9-NEXT: v_lshl_or_b32 v9, v25, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v20
+; GFX9-NEXT: v_lshl_or_b32 v10, v16, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_lshl_or_b32 v14, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v19
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v24
; GFX9-NEXT: v_perm_b32 v10, v35, v29, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v24, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v19, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v15, v9, 16, v10
; GFX9-NEXT: v_perm_b32 v9, v39, v34, s4
@@ -195494,140 +194489,141 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_perm_b32 v10, v56, v44, s4
; GFX9-NEXT: v_lshl_or_b32 v21, v10, 16, v9
-; GFX9-NEXT: v_perm_b32 v9, v58, v42, s4
+; GFX9-NEXT: v_perm_b32 v9, v62, v42, s4
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_perm_b32 v10, v59, v47, s4
; GFX9-NEXT: v_lshl_or_b32 v22, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
+; GFX9-NEXT: v_mov_b32_e32 v41, v46
; GFX9-NEXT: v_mov_b32_e32 v50, v32
-; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v51, v49
-; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v41, v46
; GFX9-NEXT: v_mov_b32_e32 v39, v52
; GFX9-NEXT: v_mov_b32_e32 v52, v38
; GFX9-NEXT: v_mov_b32_e32 v34, v37
; GFX9-NEXT: v_mov_b32_e32 v37, v31
-; GFX9-NEXT: s_lshl_b32 s5, s13, 8
-; GFX9-NEXT: s_lshl_b32 s77, s9, 8
-; GFX9-NEXT: s_lshl_b32 s78, s44, 8
-; GFX9-NEXT: buffer_load_dword v46, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:504 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:500 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v38, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(9)
-; GFX9-NEXT: v_perm_b32 v9, v9, v10, s4
+; GFX9-NEXT: s_waitcnt vmcnt(8)
+; GFX9-NEXT: v_perm_b32 v9, v58, v9, s4
+; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:508 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v58, off, s[0:3], s32 offset:512 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v32, v58, s4
; GFX9-NEXT: v_lshl_or_b32 v23, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v49
-; GFX9-NEXT: v_or_b32_sdwa v10, v24, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX9-NEXT: v_lshl_or_b32 v24, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v35
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v49, 8, v10
+; GFX9-NEXT: v_lshl_or_b32 v24, v10, 16, v9
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v25, v10, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v35, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v25, v9, 16, v10
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v33
-; GFX9-NEXT: v_or_b32_sdwa v10, v62, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:492 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v33, v46
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; GFX9-NEXT: v_or_b32_sdwa v9, v43, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v43
+; GFX9-NEXT: v_lshl_or_b32 v9, v54, 8, v9
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
+; GFX9-NEXT: v_mov_b32_e32 v54, v48
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v26, 8, v10
; GFX9-NEXT: v_lshl_or_b32 v26, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v48
-; GFX9-NEXT: v_perm_b32 v10, v63, v61, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v54, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v61
+; GFX9-NEXT: v_lshl_or_b32 v9, v33, 8, v9
+; GFX9-NEXT: v_mov_b32_e32 v33, v46
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v10, v10, v48, s4
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v27, v9, 16, v10
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v43, off, s[0:3], s32 offset:496 ; 4-byte Folded Reload
-; GFX9-NEXT: v_mov_b32_e32 v54, v61
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v63
; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:484 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(2)
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_mov_b32_e32 v48, v63
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GFX9-NEXT: v_or_b32_sdwa v10, v28, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v28, 8, v10
; GFX9-NEXT: v_lshl_or_b32 v28, v10, 16, v9
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v10, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 8, v9
; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:488 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v36, v10, s4
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v29, v9, 16, v10
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v43
-; GFX9-NEXT: v_or_b32_sdwa v9, v62, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v62
+; GFX9-NEXT: v_lshl_or_b32 v9, v43, 8, v9
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v10
-; GFX9-NEXT: v_or_b32_sdwa v10, v30, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v10
+; GFX9-NEXT: v_lshl_or_b32 v10, v30, 8, v10
; GFX9-NEXT: v_lshl_or_b32 v30, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v38
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v46
; GFX9-NEXT: v_perm_b32 v10, v63, v61, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v46, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v38, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX9-NEXT: s_and_b32 s4, s40, 0xff
; GFX9-NEXT: v_lshl_or_b32 v31, v9, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v9, s57
+; GFX9-NEXT: s_lshl_b32 s5, s13, 8
; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
-; GFX9-NEXT: s_and_b32 s4, s40, 0xff
-; GFX9-NEXT: s_or_b32 s4, s4, s5
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX9-NEXT: v_lshl_or_b32 v9, s4, 16, v8
; GFX9-NEXT: s_and_b32 s4, s76, 0xff
+; GFX9-NEXT: v_lshl_or_b32 v9, s5, 16, v8
; GFX9-NEXT: s_lshl_b32 s5, s41, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s11, 0xff
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
+; GFX9-NEXT: s_or_b32 s5, s5, s4
+; GFX9-NEXT: s_and_b32 s4, s11, 0xff
+; GFX9-NEXT: s_lshl_b32 s77, s9, 8
+; GFX9-NEXT: s_or_b32 s77, s77, s4
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s77
; GFX9-NEXT: s_and_b32 s5, s72, 0xff
; GFX9-NEXT: s_lshl_b32 s77, s62, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_and_b32 s77, s56, 0xff
-; GFX9-NEXT: s_or_b32 s77, s77, s78
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s77
+; GFX9-NEXT: s_or_b32 s77, s77, s5
+; GFX9-NEXT: s_and_b32 s5, s56, 0xff
+; GFX9-NEXT: s_lshl_b32 s78, s44, 8
+; GFX9-NEXT: s_or_b32 s78, s78, s5
+; GFX9-NEXT: s_pack_ll_b32_b16 s5, s77, s78
; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: v_mov_b32_e32 v10, s5
; GFX9-NEXT: s_mov_b64 s[4:5], 0
; GFX9-NEXT: v_mov_b32_e32 v63, v36
; GFX9-NEXT: s_branch .LBB97_3
; GFX9-NEXT: .LBB97_2:
-; GFX9-NEXT: v_mov_b32_e32 v54, v61
+; GFX9-NEXT: v_mov_b32_e32 v54, v48
; GFX9-NEXT: v_mov_b32_e32 v50, v32
; GFX9-NEXT: v_mov_b32_e32 v51, v49
; GFX9-NEXT: v_mov_b32_e32 v39, v52
@@ -195671,7 +194667,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:480 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
; GFX9-NEXT: s_add_i32 s74, s74, 3
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_add_i32 s72, s72, 3
; GFX9-NEXT: s_add_i32 s56, s56, 3
; GFX9-NEXT: s_add_i32 s60, s60, 3
@@ -195700,76 +194696,75 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:408 ; 4-byte Folded Spill
; GFX9-NEXT: v_add_u32_e32 v0, 3, v63
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:420 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:448 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:424 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v38, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v62, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:628 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v54, s4
; GFX9-NEXT: v_add_u32_e32 v63, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:416 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:428 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:644 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:464 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:648 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:412 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:452 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:432 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v31, 0x300, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:468 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:456 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:460 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v30, 0x300, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:436 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:440 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v35, s4
@@ -195779,12 +194774,12 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v28, 0x300, v0
; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v49, s4
; GFX9-NEXT: v_add_u32_e32 v27, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:444 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:624 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
@@ -195792,9 +194787,9 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_add_u32_e32 v0, 3, v32
; GFX9-NEXT: v_perm_b32 v0, v0, v58, s4
; GFX9-NEXT: v_add_u32_e32 v25, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:616 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:620 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
; GFX9-NEXT: v_mov_b32_e32 v32, s23
-; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:640 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v42, s4
@@ -195828,18 +194823,18 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_and_b32_e32 v23, 0xffff, v26
; GFX9-NEXT: v_lshl_or_b32 v23, v25, 16, v23
; GFX9-NEXT: v_and_b32_e32 v25, 0xffff, v30
-; GFX9-NEXT: v_lshl_or_b32 v25, v29, 16, v25
; GFX9-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:412 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:424 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v24, 0xffff, v28
-; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:416 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v25, v29, 16, v25
; GFX9-NEXT: v_lshl_or_b32 v24, v27, 16, v24
; GFX9-NEXT: v_and_b32_e32 v27, 0xffff, v63
; GFX9-NEXT: v_and_b32_e32 v19, 0xffff, v19
; GFX9-NEXT: v_and_b32_e32 v20, 0xffff, v20
; GFX9-NEXT: v_lshl_or_b32 v19, v52, 16, v19
; GFX9-NEXT: v_lshl_or_b32 v20, v49, 16, v20
+; GFX9-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:428 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:420 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(4)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
@@ -195851,6 +194846,10 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:600 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v18, 0xffff, v18
; GFX9-NEXT: v_lshl_or_b32 v18, v37, 16, v18
+; GFX9-NEXT: s_waitcnt vmcnt(3)
+; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
+; GFX9-NEXT: v_and_b32_e32 v28, 0xffff, v38
+; GFX9-NEXT: v_lshl_or_b32 v28, v62, 16, v28
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_u32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -195869,7 +194868,7 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX9-NEXT: v_add_u32_e32 v16, 0x300, v0
-; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:636 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:632 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:608 ; 4-byte Folded Reload
; GFX9-NEXT: v_and_b32_e32 v16, 0xffff, v16
; GFX9-NEXT: s_waitcnt vmcnt(1)
@@ -196020,12 +195019,12 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_and_b32_e32 v32, 0xffff, v54
; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v32
; GFX9-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:476 ; 4-byte Folded Reload
-; GFX9-NEXT: v_and_b32_e32 v29, 0xffff, v29
; GFX9-NEXT: v_and_b32_e32 v26, 0xffff, v26
-; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
-; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: v_lshl_or_b32 v26, v31, 16, v26
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:408 ; 4-byte Folded Reload
+; GFX9-NEXT: v_and_b32_e32 v29, 0xffff, v29
+; GFX9-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; GFX9-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:480 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v0, s18, v34, v0
; GFX9-NEXT: v_add_u32_e32 v0, 0x300, v0
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
@@ -196037,8 +195036,6 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX9-NEXT: v_lshl_or_b32 v27, v28, 16, v27
-; GFX9-NEXT: v_and_b32_e32 v28, 0xffff, v38
; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, v33
; GFX9-NEXT: v_lshl_or_b32 v2, v61, 16, v2
; GFX9-NEXT: v_lshl_or_b32 v3, v60, 16, v3
@@ -196050,10 +195047,8 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX9-NEXT: v_lshl_or_b32 v9, v46, 16, v9
; GFX9-NEXT: v_lshl_or_b32 v10, v45, 16, v10
; GFX9-NEXT: v_lshl_or_b32 v11, v44, 16, v11
-; GFX9-NEXT: v_lshl_or_b32 v28, v62, 16, v28
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_and_b32_e32 v30, 0xffff, v30
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v30, 0xffff, v30
; GFX9-NEXT: v_lshl_or_b32 v30, v31, 16, v30
; GFX9-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:472 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
@@ -196082,10 +195077,12 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-LABEL: bitcast_v128i8_to_v64i16_scalar:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
+; GFX11-TRUE16-NEXT: s_clause 0x2 ; 12-byte Folded Spill
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v40, s32 offset:328
; GFX11-TRUE16-NEXT: ; meta instruction
-; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:324
+; GFX11-TRUE16-NEXT: ; meta instruction
+; GFX11-TRUE16-NEXT: scratch_store_b32 off, v42, s32 offset:320
; GFX11-TRUE16-NEXT: s_clause 0x1f
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:308
@@ -196206,156 +195203,136 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB97_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s63, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s57, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xff, v117
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s76
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s56, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s8, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s11, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s78
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v13, 0xff, v68
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s41, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s79
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s10, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v164
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s46, 0xff
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v114
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v64, 8, v24
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v131
+; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s47, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s78
+; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s13, 8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v37, 8, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xff, v38
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v24, v119, 8, v26
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v144
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v70, 8, v10
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v27.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v27, v82, 8, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v167
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s76
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v53, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v66, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s88, s78
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v71, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v32, 8, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v69, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v87, 8, v26
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v10.l
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v29, 0xff, v149
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v84, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v26, v128, 8, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v162
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v17.l
; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v98, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v18.l
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v113, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v19.l
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v118, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v20.l
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v30.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v179
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v21.l
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v29, v101, 8, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v31, v132, 8, v28
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v22.l
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v23.l
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v25.l
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v86, 8, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v27.l
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v28, v150, 8, v30
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v50
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v29.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v160
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v165
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v31.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v31, 0xff, v166
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v33, 8, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v183, v102, 8, v29
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v41, v129, 8, v30
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v42, v133, 8, v31
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v39, 8, v14
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v30, v178, 8, v40
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, s79
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s77
+; GFX11-TRUE16-NEXT: v_mov_b16_e64 v29.h, v183.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v41.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v42.l
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB97_3
; GFX11-TRUE16-NEXT: .LBB97_2: ; %cmp.true
@@ -196588,9 +195565,10 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v129.l
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.h, v133.l
; GFX11-TRUE16-NEXT: .LBB97_3: ; %end
-; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
-; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
-; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
+; GFX11-TRUE16-NEXT: s_clause 0x2 ; 12-byte Folded Reload
+; GFX11-TRUE16-NEXT: scratch_load_b32 v42, off, s32 offset:320
+; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:324
+; GFX11-TRUE16-NEXT: scratch_load_b32 v40, off, s32 offset:328
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-TRUE16-NEXT: .LBB97_4:
@@ -196601,7 +195579,10 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-LABEL: bitcast_v128i8_to_v64i16_scalar:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:320 ; 4-byte Folded Spill
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Spill
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v40, s32 offset:324
+; GFX11-FAKE16-NEXT: ; meta instruction
+; GFX11-FAKE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
; GFX11-FAKE16-NEXT: s_clause 0x1f
; GFX11-FAKE16-NEXT: scratch_load_u16 v166, off, s32 offset:312
; GFX11-FAKE16-NEXT: scratch_load_u16 v180, off, s32 offset:308
@@ -196724,193 +195705,174 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s74, 0xff
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(2)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v33
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v48
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v32
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v49
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v96, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v68, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
; GFX11-FAKE16-NEXT: v_perm_b32 v4, s11, s8, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s6, s4, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v67, v51, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v80, v66, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s7, s5, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s42, s15, v8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s44, s41, v8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v5, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v68, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v9, 16, v10
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v35
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s15, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s41, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xffff, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v17, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v21, v116, v103, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s43, 8
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v118, v101, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s14, s10, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s76, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v38
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v35, 8, s76
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s14, s10, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s76
; GFX11-FAKE16-NEXT: s_and_b32 s76, s46, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v21, 0xffff, v21
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v7, 16, v9
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s43, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-FAKE16-NEXT: s_lshl_b32 s76, s13, 8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v38
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s78
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v13, v14
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v53
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v37
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s77, s76
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v33, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v36, 8, v14
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v69, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v87, v70, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v53
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v48
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v67, v51, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v113, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v37, 8, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v32, 8, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v9, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v36
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v11, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v14, v15
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 8, v34
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v50
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v14, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v82, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v65, v39, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v13
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v82, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v34, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v14, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v80, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v22, 0xffff, v22
-; GFX11-FAKE16-NEXT: v_perm_b32 v23, v115, v99, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v130
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v9, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v96, v85, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v15, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v71, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v83, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v86, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v117
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v19, 0xffff, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v25, v146, v128, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v160
; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v144
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v10, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v9, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v71, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v18, 16, v19
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v16, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v98, v83, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v148
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v9, 16, v10
; GFX11-FAKE16-NEXT: v_perm_b32 v9, v102, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v19, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v87, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v135
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v86, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v147, 8, v26
+; GFX11-FAKE16-NEXT: v_perm_b32 v28, v162, v145, 0xc0c0004
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v150
-; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s78, s40, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v29, v179, v163, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v116, v103, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v112, v100, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s76, 16, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v132, v129, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s13, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v11, 16, v21
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v113, v97, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v20, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v118, v101, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v29, 0xffff, v29
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v11, 16, v22
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v23, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v134
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v119
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
; GFX11-FAKE16-NEXT: s_and_b32 s77, s62, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s59, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s45, 8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v24, v25
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v24, 0xff, v131
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v25, 8, v114
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v25, v24, v25
-; GFX11-FAKE16-NEXT: v_perm_b32 v24, v146, v128, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s63, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s61, 8
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xffff, v24
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v160
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v147
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v25, 16, v26
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v148
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v31, v182, v167, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v132, v129, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v115, v99, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v22, v22, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xff, v134
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v31, 0xffff, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v26, v27
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v26, 0xff, v149
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v27, 8, v133
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v119, 8, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v23, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s60, s57, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v117, 8, v24
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s72, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v27, v26, v27
-; GFX11-FAKE16-NEXT: v_perm_b32 v26, v162, v145, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xffff, v26
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v177
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v164
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v24, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v131
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v27, 16, v28
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s79, 16, v10
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s59, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v114, 8, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v25
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s77
+; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s45, 8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v25, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v144, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v26
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xff, v149
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s63, 0xff
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s79, s77
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s61, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v26, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v177
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v133, 8, v27
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v27, 0xffff, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v151
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v28, v29
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s78
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v164, 8, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v27, v10, 16, v27
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v135, 8, v28
; GFX11-FAKE16-NEXT: v_and_b32_e32 v28, 0xff, v176
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v29, 8, v161
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, v28, v29
-; GFX11-FAKE16-NEXT: v_perm_b32 v28, v179, v163, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xffff, v28
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v11, 16, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 8, v165
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v29, 16, v30
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v178
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v10, v11
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v180
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v31, 8, v166
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_and_b32 v183, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v31, v11, v31
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v182, v167, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v183
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v161, 8, v28
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v28, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v181
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v178
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v29, v30, 16, v29
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v30, 0xff, v180
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v165, 8, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v183, v150, 8, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s79, 16, v8
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v40
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v41, v166, 8, v30
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v40, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v41, 16, v31
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v183, 16, v40
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB97_3
; GFX11-FAKE16-NEXT: .LBB97_2: ; %cmp.true
@@ -197175,7 +196137,9 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v30, v30, 16, v34
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v31, v31, 16, v35
; GFX11-FAKE16-NEXT: .LBB97_3: ; %end
-; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:320 ; 4-byte Folded Reload
+; GFX11-FAKE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
+; GFX11-FAKE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
+; GFX11-FAKE16-NEXT: scratch_load_b32 v40, off, s32 offset:324
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
; GFX11-FAKE16-NEXT: .LBB97_4:
@@ -204709,8 +203673,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
-; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
@@ -204933,230 +203897,236 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: s_lshr_b64 s[36:37], s[44:45], 24
; GFX9-NEXT: s_cbranch_execnz .LBB99_4
; GFX9-NEXT: .LBB99_2: ; %cmp.true
-; GFX9-NEXT: v_pk_add_u16 v26, s5, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_u16 v25, s4, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[25:26]
-; GFX9-NEXT: v_pk_add_u16 v28, s29, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_u16 v27, s28, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[27:28]
-; GFX9-NEXT: v_pk_add_u16 v30, s27, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_u16 v29, s26, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[29:30]
-; GFX9-NEXT: v_pk_add_u16 v32, s25, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_u16 v31, s24, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[31:32]
-; GFX9-NEXT: v_pk_add_u16 v34, s23, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_u16 v33, s22, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[33:34]
-; GFX9-NEXT: v_pk_add_u16 v38, s19, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_u16 v36, s21, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_u16 v35, s20, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; GFX9-NEXT: v_pk_add_u16 v24, s5, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_u16 v23, s4, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[23:24]
+; GFX9-NEXT: v_pk_add_u16 v26, s29, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_u16 v25, s28, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[25:26]
+; GFX9-NEXT: v_pk_add_u16 v28, s27, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_u16 v27, s26, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[27:28]
+; GFX9-NEXT: v_pk_add_u16 v30, s25, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_u16 v29, s24, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[35:36]
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v38
-; GFX9-NEXT: v_pk_add_u16 v49, s17, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v38
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[29:30]
+; GFX9-NEXT: v_pk_add_u16 v32, s23, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_u16 v31, s22, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[31:32]
+; GFX9-NEXT: v_pk_add_u16 v34, s21, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_u16 v33, s20, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[33:34]
+; GFX9-NEXT: v_pk_add_u16 v36, s19, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_u16 v35, s18, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[35:36]
+; GFX9-NEXT: v_pk_add_u16 v38, s17, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_u16 v37, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[37:38]
; GFX9-NEXT: v_pk_add_u16 v2, s7, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v1, s6, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v49
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v49
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
; GFX9-NEXT: v_pk_add_u16 v4, s9, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v1
; GFX9-NEXT: v_pk_add_u16 v3, s8, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v4
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v4
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[3:4]
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v38
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v38
; GFX9-NEXT: v_pk_add_u16 v6, s11, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v5, s10, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v3
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[5:6]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v3
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v6
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v2
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[5:6]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v2
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v4
; GFX9-NEXT: v_pk_add_u16 v8, s13, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, s12, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v6
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[7:8]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v6
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v5
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v3
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[7:8]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v3
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v6
; GFX9-NEXT: v_pk_add_u16 v10, s15, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, s14, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v5
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[9:10]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v8
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v8
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v6
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[9:10]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v6
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v5
; GFX9-NEXT: v_pk_add_u16 v12, s41, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, s40, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v8
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[11:12]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v7
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v7
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v5
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[11:12]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v8
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v8
; GFX9-NEXT: v_pk_add_u16 v14, s43, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, s42, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v10
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[13:14]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v10
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v10
-; GFX9-NEXT: v_pk_add_u16 v20, s45, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_u16 v19, s44, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v9
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[19:20]
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v9
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v12
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v12
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v26
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v12
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v26
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v11
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v26
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v11
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v25
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v28
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v28
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v30
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v30
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v13
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v32
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 24, v20
-; GFX9-NEXT: v_pk_add_u16 v37, s18, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v32
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v20
-; GFX9-NEXT: v_pk_add_u16 v48, s16, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_lshrrev_b64 v[43:44], 24, v[37:38]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 24, v34
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 24, v36
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v20
-; GFX9-NEXT: v_lshrrev_b64 v[44:45], 24, v[48:49]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 16, v34
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v36
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v25
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v28
-; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v27
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v8
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[13:14]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v7
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v7
+; GFX9-NEXT: v_pk_add_u16 v16, s45, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_u16 v15, s44, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v10
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[15:16]
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v10
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v10
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v24
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v9
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v24
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v12
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v24
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v12
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v23
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v12
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v23
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v11
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v26
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v11
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v26
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v14
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v28
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v14
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v28
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v14
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v30
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v13
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v30
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v13
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v32
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 24, v16
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v32
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v16
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 24, v34
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 24, v36
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v16
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v34
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 16, v36
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v15
+; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v26
+; GFX9-NEXT: v_lshrrev_b32_e32 v45, 16, v25
+; GFX9-NEXT: v_lshrrev_b32_e32 v54, 8, v25
+; GFX9-NEXT: v_lshrrev_b32_e32 v39, 8, v28
+; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v27
; GFX9-NEXT: v_lshrrev_b32_e32 v46, 8, v27
-; GFX9-NEXT: v_lshrrev_b32_e32 v56, 8, v30
-; GFX9-NEXT: v_lshrrev_b32_e32 v58, 16, v29
-; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v29
-; GFX9-NEXT: v_lshrrev_b32_e32 v59, 8, v32
+; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v30
+; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v29
+; GFX9-NEXT: v_lshrrev_b32_e32 v56, 8, v29
+; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v32
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v31
-; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v31
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v23, 8, v34
-; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v33
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v33
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 8, v36
-; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v35
-; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v35
-; GFX9-NEXT: v_lshrrev_b32_e32 v24, 8, v38
-; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v37
-; GFX9-NEXT: v_lshrrev_b32_e32 v52, 8, v37
-; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v49
-; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v48
-; GFX9-NEXT: v_lshrrev_b32_e32 v55, 8, v48
+; GFX9-NEXT: v_lshrrev_b32_e32 v59, 8, v31
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v34
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v33
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v33
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v36
+; GFX9-NEXT: v_lshrrev_b32_e32 v22, 16, v35
+; GFX9-NEXT: v_lshrrev_b32_e32 v20, 8, v35
+; GFX9-NEXT: v_lshrrev_b32_e32 v49, 8, v38
+; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v37
+; GFX9-NEXT: v_lshrrev_b32_e32 v50, 8, v37
; GFX9-NEXT: v_lshrrev_b32_e32 v42, 24, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v41, 8, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v45, 8, v1
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v19
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v43, 8, v1
+; GFX9-NEXT: v_lshrrev_b32_e32 v44, 16, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v53, 8, v4
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v15
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
; GFX9-NEXT: s_branch .LBB99_5
; GFX9-NEXT: .LBB99_3:
; GFX9-NEXT: ; implicit-def: $sgpr46
@@ -205307,225 +204277,253 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: ; implicit-def: $sgpr46
; GFX9-NEXT: s_branch .LBB99_2
; GFX9-NEXT: .LBB99_4:
-; GFX9-NEXT: v_mov_b32_e32 v15, s81
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s71
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s80
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s70
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s69
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s68
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s66
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s67
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s65
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s64
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s55
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s53
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s54
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s52
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s51
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s50
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s48
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s49
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s39
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s38
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s99
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s97
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s98
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s96
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s87
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s86
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s84
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s85
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s83
-; GFX9-NEXT: v_mov_b32_e32 v25, s4
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s82
+; GFX9-NEXT: v_mov_b32_e32 v17, s81
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s71
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s80
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s70
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s69
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s68
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s66
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s67
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s65
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s64
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s55
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s53
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s54
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s52
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s51
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s50
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s48
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s49
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s39
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s38
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s99
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s97
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s98
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s96
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s87
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s86
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s84
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s85
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s83
+; GFX9-NEXT: v_mov_b32_e32 v23, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s82
; GFX9-NEXT: v_readlane_b32 s4, v62, 0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 1
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 2
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v21, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 3
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v44, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 4
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 5
-; GFX9-NEXT: v_mov_b32_e32 v22, s4
+; GFX9-NEXT: v_mov_b32_e32 v53, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 6
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v51, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 7
-; GFX9-NEXT: v_mov_b32_e32 v45, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 8
-; GFX9-NEXT: v_mov_b32_e32 v41, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:392 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 9
; GFX9-NEXT: v_mov_b32_e32 v42, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 10
-; GFX9-NEXT: v_mov_b32_e32 v55, s4
+; GFX9-NEXT: v_mov_b32_e32 v50, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 11
-; GFX9-NEXT: v_mov_b32_e32 v39, s4
+; GFX9-NEXT: v_mov_b32_e32 v52, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 12
-; GFX9-NEXT: v_mov_b32_e32 v50, s4
+; GFX9-NEXT: v_mov_b32_e32 v49, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 13
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:388 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 14
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 15
-; GFX9-NEXT: v_mov_b32_e32 v52, s4
+; GFX9-NEXT: v_mov_b32_e32 v20, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 16
-; GFX9-NEXT: v_mov_b32_e32 v54, s4
+; GFX9-NEXT: v_mov_b32_e32 v22, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 17
-; GFX9-NEXT: v_mov_b32_e32 v24, s4
+; GFX9-NEXT: v_mov_b32_e32 v19, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 18
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 19
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 20
-; GFX9-NEXT: v_mov_b32_e32 v21, s4
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v17, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 21
; GFX9-NEXT: v_mov_b32_e32 v18, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 22
-; GFX9-NEXT: v_mov_b32_e32 v16, s4
+; GFX9-NEXT: v_mov_b32_e32 v61, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 23
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 24
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 25
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v15, s4
+; GFX9-NEXT: v_mov_b32_e32 v59, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 26
-; GFX9-NEXT: v_mov_b32_e32 v61, s4
+; GFX9-NEXT: v_mov_b32_e32 v60, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 27
-; GFX9-NEXT: v_mov_b32_e32 v23, s4
+; GFX9-NEXT: v_mov_b32_e32 v58, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 28
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 29
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 30
-; GFX9-NEXT: v_mov_b32_e32 v53, s4
+; GFX9-NEXT: v_mov_b32_e32 v56, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 31
-; GFX9-NEXT: v_mov_b32_e32 v60, s4
+; GFX9-NEXT: v_mov_b32_e32 v57, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 32
-; GFX9-NEXT: v_mov_b32_e32 v59, s4
+; GFX9-NEXT: v_mov_b32_e32 v47, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 33
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 34
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 35
-; GFX9-NEXT: v_mov_b32_e32 v57, s4
+; GFX9-NEXT: v_mov_b32_e32 v46, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 36
-; GFX9-NEXT: v_mov_b32_e32 v58, s4
+; GFX9-NEXT: v_mov_b32_e32 v48, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 37
-; GFX9-NEXT: v_mov_b32_e32 v56, s4
+; GFX9-NEXT: buffer_store_dword v39, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v39, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 38
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: v_mov_b32_e32 v54, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 39
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v54, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 40
-; GFX9-NEXT: v_mov_b32_e32 v46, s4
+; GFX9-NEXT: buffer_store_dword v54, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v54, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 41
-; GFX9-NEXT: v_mov_b32_e32 v47, s4
+; GFX9-NEXT: v_mov_b32_e32 v45, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 42
-; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v17, s4
+; GFX9-NEXT: v_mov_b32_e32 v55, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 43
-; GFX9-NEXT: v_mov_b32_e32 v51, s4
+; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 44
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s4
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 45
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s4
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 46
-; GFX9-NEXT: buffer_store_dword v51, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v51, s4
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 47
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:396 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 48
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:376 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s4
; GFX9-NEXT: v_readlane_b32 s4, v62, 49
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s4
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s46
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s56
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s58
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s60
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s62
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s72
-; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v43, v53
+; GFX9-NEXT: v_mov_b32_e32 v53, v21
+; GFX9-NEXT: v_mov_b32_e32 v21, s92
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v40, s74
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:364 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:368 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v21, s94
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:372 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v40, s76
+; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:380 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:384 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v21, s30
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s78
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v21, s34
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v40, s88
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v19, s44
-; GFX9-NEXT: v_mov_b32_e32 v20, s45
+; GFX9-NEXT: v_mov_b32_e32 v41, s90
+; GFX9-NEXT: v_mov_b32_e32 v21, s36
+; GFX9-NEXT: v_mov_b32_e32 v15, s44
+; GFX9-NEXT: v_mov_b32_e32 v16, s45
; GFX9-NEXT: v_mov_b32_e32 v13, s42
; GFX9-NEXT: v_mov_b32_e32 v14, s43
; GFX9-NEXT: v_mov_b32_e32 v11, s40
@@ -205540,78 +204538,50 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v4, s9
; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s7
-; GFX9-NEXT: v_mov_b32_e32 v48, s16
-; GFX9-NEXT: v_mov_b32_e32 v49, s17
-; GFX9-NEXT: v_mov_b32_e32 v37, s18
-; GFX9-NEXT: v_mov_b32_e32 v38, s19
-; GFX9-NEXT: v_mov_b32_e32 v35, s20
-; GFX9-NEXT: v_mov_b32_e32 v36, s21
-; GFX9-NEXT: v_mov_b32_e32 v33, s22
-; GFX9-NEXT: v_mov_b32_e32 v34, s23
-; GFX9-NEXT: v_mov_b32_e32 v31, s24
-; GFX9-NEXT: v_mov_b32_e32 v32, s25
-; GFX9-NEXT: v_mov_b32_e32 v29, s26
-; GFX9-NEXT: v_mov_b32_e32 v30, s27
-; GFX9-NEXT: v_mov_b32_e32 v27, s28
-; GFX9-NEXT: v_mov_b32_e32 v28, s29
-; GFX9-NEXT: v_mov_b32_e32 v26, s5
-; GFX9-NEXT: v_mov_b32_e32 v43, s74
-; GFX9-NEXT: v_mov_b32_e32 v44, s76
-; GFX9-NEXT: v_mov_b32_e32 v40, v41
-; GFX9-NEXT: v_mov_b32_e32 v41, v45
-; GFX9-NEXT: v_mov_b32_e32 v45, v22
-; GFX9-NEXT: v_mov_b32_e32 v22, s90
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v22, s92
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v22, s94
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v22, s30
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v22, s34
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v37, s16
+; GFX9-NEXT: v_mov_b32_e32 v38, s17
+; GFX9-NEXT: v_mov_b32_e32 v35, s18
+; GFX9-NEXT: v_mov_b32_e32 v36, s19
+; GFX9-NEXT: v_mov_b32_e32 v33, s20
+; GFX9-NEXT: v_mov_b32_e32 v34, s21
+; GFX9-NEXT: v_mov_b32_e32 v31, s22
+; GFX9-NEXT: v_mov_b32_e32 v32, s23
+; GFX9-NEXT: v_mov_b32_e32 v29, s24
+; GFX9-NEXT: v_mov_b32_e32 v30, s25
+; GFX9-NEXT: v_mov_b32_e32 v27, s26
+; GFX9-NEXT: v_mov_b32_e32 v28, s27
+; GFX9-NEXT: v_mov_b32_e32 v25, s28
+; GFX9-NEXT: v_mov_b32_e32 v26, s29
+; GFX9-NEXT: v_mov_b32_e32 v24, s5
+; GFX9-NEXT: buffer_store_dword v41, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v22, s36
-; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v42, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v23, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v22, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill
; GFX9-NEXT: .LBB99_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v37, v37, v52, s4
-; GFX9-NEXT: v_perm_b32 v31, v31, v53, s4
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v33, v33, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v21, v35, v21, s4
-; GFX9-NEXT: v_perm_b32 v16, v36, v16, s4
-; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v24, v38, v24, s4
-; GFX9-NEXT: v_perm_b32 v17, v28, v17, s4
-; GFX9-NEXT: v_perm_b32 v48, v48, v55, s4
-; GFX9-NEXT: v_perm_b32 v49, v49, v50, s4
-; GFX9-NEXT: v_perm_b32 v50, v54, v43, s4
-; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v39, v39, v44, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; GFX9-NEXT: v_or_b32_e32 v39, v48, v39
-; GFX9-NEXT: v_perm_b32 v23, v34, v23, s4
-; GFX9-NEXT: v_perm_b32 v32, v32, v59, s4
-; GFX9-NEXT: v_perm_b32 v29, v29, v57, s4
-; GFX9-NEXT: v_perm_b32 v30, v30, v56, s4
+; GFX9-NEXT: v_perm_b32 v37, v37, v50, s4
+; GFX9-NEXT: v_perm_b32 v38, v38, v49, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:364 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:368 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v20, v35, v20, s4
+; GFX9-NEXT: v_perm_b32 v19, v36, v19, s4
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v33, v17, s4
+; GFX9-NEXT: v_perm_b32 v33, v34, v61, s4
+; GFX9-NEXT: v_perm_b32 v28, v28, v39, s4
+; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:380 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v31, v31, v59, s4
+; GFX9-NEXT: v_perm_b32 v32, v32, v58, s4
+; GFX9-NEXT: v_perm_b32 v29, v29, v56, s4
+; GFX9-NEXT: v_perm_b32 v30, v30, v47, s4
; GFX9-NEXT: v_perm_b32 v27, v27, v46, s4
-; GFX9-NEXT: v_perm_b32 v1, v1, v45, s4
+; GFX9-NEXT: v_perm_b32 v25, v25, v54, s4
+; GFX9-NEXT: v_perm_b32 v26, v26, v55, s4
+; GFX9-NEXT: v_perm_b32 v1, v1, v43, s4
; GFX9-NEXT: v_readlane_b32 s30, v63, 34
; GFX9-NEXT: v_readlane_b32 s31, v63, 35
; GFX9-NEXT: v_readlane_b32 s99, v63, 33
@@ -205648,274 +204618,254 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: v_readlane_b32 s36, v63, 2
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v36, v58, v52, s4
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v22, v25, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v35, v61, v35, s4
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_perm_b32 v18, v18, v54, s4
-; GFX9-NEXT: buffer_load_dword v54, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v55, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v18, v21, v18
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_perm_b32 v38, v47, v52, s4
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v53, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_perm_b32 v25, v26, v15, s4
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_perm_b32 v34, v60, v54, s4
+; GFX9-NEXT: s_waitcnt vmcnt(5)
+; GFX9-NEXT: v_perm_b32 v22, v22, v49, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v20, v22, 16, v20
+; GFX9-NEXT: s_waitcnt vmcnt(5)
+; GFX9-NEXT: v_perm_b32 v18, v18, v35, s4
+; GFX9-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v17, v18, 16, v17
+; GFX9-NEXT: s_waitcnt vmcnt(7)
+; GFX9-NEXT: v_perm_b32 v52, v52, v40, s4
+; GFX9-NEXT: v_lshl_or_b32 v37, v52, 16, v37
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v36, v48, v49, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v34, v60, v34, s4
+; GFX9-NEXT: v_perm_b32 v35, v57, v35, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v28, v51, v52, s4
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v39, v45, v48, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:396 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v21, v21, v48, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:376 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v23, v23, v48, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:372 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v24, v24, v48, s4
+; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v26, v15, v51, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v48, v49, v48, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v19, v19, v15, s4
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v15, v15, v49, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
+; GFX9-NEXT: v_lshl_or_b32 v15, v48, 16, v15
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v20, v20, v15, s4
-; GFX9-NEXT: buffer_load_dword v51, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v52, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v16, v16, v49, s4
+; GFX9-NEXT: buffer_load_dword v49, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v15, v15, v51, s4
-; GFX9-NEXT: buffer_store_dword v39, v0, s[0:3], 0 offen
-; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v49, v50, v49, s4
+; GFX9-NEXT: buffer_store_dword v37, v0, s[0:3], 0 offen
+; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v48, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v39, v39, v48, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v39
-; GFX9-NEXT: v_or_b32_e32 v39, v49, v39
-; GFX9-NEXT: buffer_store_dword v39, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_lshlrev_b32_e32 v39, 16, v50
-; GFX9-NEXT: v_or_b32_e32 v37, v37, v39
-; GFX9-NEXT: buffer_store_dword v37, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
-; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v39, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v37, v37, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v37, 16, v37
-; GFX9-NEXT: v_or_b32_e32 v24, v24, v37
-; GFX9-NEXT: buffer_store_dword v24, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: buffer_store_dword v18, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v50, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v37, v37, v50, s4
+; GFX9-NEXT: v_lshl_or_b32 v37, v37, 16, v38
+; GFX9-NEXT: buffer_store_dword v37, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: buffer_store_dword v20, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v18, v18, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v16, v16, v18
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v35
-; GFX9-NEXT: v_or_b32_e32 v16, v33, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v20, v20, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; GFX9-NEXT: buffer_store_dword v19, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v23, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v34
-; GFX9-NEXT: v_or_b32_e32 v16, v31, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v33
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: v_lshl_or_b32 v17, v34, 16, v31
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v32, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v36
-; GFX9-NEXT: v_or_b32_e32 v16, v29, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v32
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: v_lshl_or_b32 v17, v35, 16, v29
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v30, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v38
-; GFX9-NEXT: v_or_b32_e32 v16, v27, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:48
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v30
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: v_lshl_or_b32 v17, v36, 16, v27
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:40
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v17, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v28
-; GFX9-NEXT: v_or_b32_e32 v16, v22, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:56
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v28
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:44
+; GFX9-NEXT: v_lshl_or_b32 v17, v39, 16, v25
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:48
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v25, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:60
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v26
-; GFX9-NEXT: v_or_b32_e32 v16, v19, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:64
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v26
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:52
+; GFX9-NEXT: v_lshl_or_b32 v17, v21, 16, v23
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:56
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v16, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v16, v20, v16
-; GFX9-NEXT: buffer_store_dword v16, v0, s[0:3], 0 offen offset:68
-; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v17, v17, v18, s4
+; GFX9-NEXT: v_lshl_or_b32 v17, v17, 16, v24
+; GFX9-NEXT: buffer_store_dword v17, v0, s[0:3], 0 offen offset:60
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:64
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; GFX9-NEXT: s_nop 0
+; GFX9-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v15, v15, v17, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:68
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v13, v13, v16, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_perm_b32 v13, v13, v15, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v49, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:72
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v14, v14, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:76
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v11, v13, s4
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v13, v14, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:80
-; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v12, v12, v13, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:84
-; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v9, v11, s4
-; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v11, v12, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:88
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v10, v10, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:92
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v7, v9, s4
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v9, v10, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:96
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v8, v8, v9, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:100
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v5, v7, s4
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v7, v8, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:104
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:108 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v6, v6, v7, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:108
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v3, v3, v5, s4
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_perm_b32 v5, v6, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:112
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v3, v4, v53, s4
+; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v4, v4, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v44, v4, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:116
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v3, v4, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: s_waitcnt vmcnt(1)
+; GFX9-NEXT: v_perm_b32 v3, v51, v3, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:120
-; GFX9-NEXT: v_perm_b32 v1, v2, v41, s4
-; GFX9-NEXT: v_perm_b32 v2, v40, v42, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:392 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v1, v2, v1, s4
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_perm_b32 v2, v2, v42, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:124
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v60, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -205932,8 +204882,8 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
-; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:384 ; 4-byte Folded Reload
-; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:388 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v63, off, s[0:3], s32 offset:400 ; 4-byte Folded Reload
+; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 offset:404 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -206195,134 +205145,134 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, vcc_lo
; GFX11-NEXT: s_cbranch_vccnz .LBB99_4
; GFX11-NEXT: .LBB99_2: ; %cmp.true
-; GFX11-NEXT: v_pk_add_u16 v28, s19, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v18, s27, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v17, s26, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v27, s18, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v30, s17, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v29, s16, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v2, s5, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v1, s4, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v20, s25, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v19, s24, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v4, s7, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v3, s6, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v22, s23, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v21, s22, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v6, s9, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v5, s8, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v24, s21, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v23, s20, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v8, s11, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v7, s10, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v32, s1, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v31, s0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v26, s19, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v25, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v14, s41, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v13, s40, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v10, s13, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v9, s12, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v6, s9, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v5, s8, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v34, s3, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v33, s2, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v22, s23, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v21, s22, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v28, s17, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v27, s16, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_lshrrev_b64 v[48:49], 24, v[17:18]
; GFX11-NEXT: v_pk_add_u16 v16, s29, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v15, s28, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v12, s15, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v11, s14, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v8, s11, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v7, s10, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v4, s7, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v3, s6, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v2, s5, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v1, s4, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v36, s1, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v35, s0, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v24, s21, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v23, s20, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_lshrrev_b64 v[51:52], 24, v[17:18]
-; GFX11-NEXT: v_lshrrev_b64 v[64:65], 24, v[27:28]
-; GFX11-NEXT: v_lshrrev_b64 v[52:53], 24, v[19:20]
-; GFX11-NEXT: v_lshrrev_b64 v[65:66], 24, v[29:30]
-; GFX11-NEXT: v_lshrrev_b64 v[53:54], 24, v[21:22]
-; GFX11-NEXT: v_lshrrev_b64 v[69:70], 24, v[33:34]
-; GFX11-NEXT: v_lshrrev_b64 v[37:38], 24, v[5:6]
-; GFX11-NEXT: v_lshrrev_b64 v[48:49], 24, v[9:10]
-; GFX11-NEXT: v_lshrrev_b64 v[66:67], 24, v[13:14]
-; GFX11-NEXT: v_lshrrev_b64 v[54:55], 24, v[23:24]
-; GFX11-NEXT: v_lshrrev_b64 v[70:71], 24, v[35:36]
-; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[1:2]
-; GFX11-NEXT: v_lshrrev_b64 v[31:32], 24, v[3:4]
-; GFX11-NEXT: v_lshrrev_b64 v[38:39], 24, v[7:8]
-; GFX11-NEXT: v_lshrrev_b64 v[49:50], 24, v[11:12]
-; GFX11-NEXT: v_lshrrev_b64 v[67:68], 24, v[15:16]
-; GFX11-NEXT: v_lshrrev_b32_e32 v148, 24, v18
+; GFX11-NEXT: v_pk_add_u16 v30, s3, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v29, s2, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_lshrrev_b64 v[49:50], 24, v[19:20]
+; GFX11-NEXT: v_lshrrev_b64 v[33:34], 24, v[1:2]
+; GFX11-NEXT: v_lshrrev_b64 v[50:51], 24, v[21:22]
+; GFX11-NEXT: v_lshrrev_b64 v[34:35], 24, v[3:4]
+; GFX11-NEXT: v_lshrrev_b64 v[51:52], 24, v[23:24]
+; GFX11-NEXT: v_lshrrev_b64 v[35:36], 24, v[5:6]
+; GFX11-NEXT: v_lshrrev_b64 v[52:53], 24, v[25:26]
+; GFX11-NEXT: v_lshrrev_b64 v[64:65], 24, v[31:32]
+; GFX11-NEXT: v_lshrrev_b64 v[36:37], 24, v[7:8]
+; GFX11-NEXT: v_lshrrev_b64 v[53:54], 24, v[27:28]
+; GFX11-NEXT: v_lshrrev_b64 v[37:38], 24, v[9:10]
+; GFX11-NEXT: v_lshrrev_b64 v[65:66], 24, v[13:14]
+; GFX11-NEXT: v_lshrrev_b64 v[54:55], 24, v[29:30]
+; GFX11-NEXT: v_lshrrev_b64 v[38:39], 24, v[11:12]
+; GFX11-NEXT: v_lshrrev_b64 v[66:67], 24, v[15:16]
+; GFX11-NEXT: v_lshrrev_b32_e32 v160, 24, v18
; GFX11-NEXT: v_lshrrev_b32_e32 v147, 16, v18
; GFX11-NEXT: v_lshrrev_b32_e32 v146, 8, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v160, 16, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v151, 16, v17
; GFX11-NEXT: v_lshrrev_b32_e32 v150, 8, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v162, 24, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v161, 16, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v149, 8, v20
-; GFX11-NEXT: v_lshrrev_b32_e32 v163, 16, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v151, 8, v19
-; GFX11-NEXT: v_lshrrev_b32_e32 v166, 24, v22
+; GFX11-NEXT: v_lshrrev_b32_e32 v163, 24, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v149, 16, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v148, 8, v20
+; GFX11-NEXT: v_lshrrev_b32_e32 v162, 16, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v161, 8, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v178, 24, v22
; GFX11-NEXT: v_lshrrev_b32_e32 v165, 16, v22
; GFX11-NEXT: v_lshrrev_b32_e32 v164, 8, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v178, 16, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v177, 16, v21
; GFX11-NEXT: v_lshrrev_b32_e32 v176, 8, v21
-; GFX11-NEXT: v_lshrrev_b32_e32 v180, 24, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v179, 16, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v167, 8, v24
-; GFX11-NEXT: v_lshrrev_b32_e32 v181, 16, v23
-; GFX11-NEXT: v_lshrrev_b32_e32 v177, 8, v23
-; GFX11-NEXT: v_lshrrev_b32_e32 v42, 24, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v181, 24, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v167, 16, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v166, 8, v24
+; GFX11-NEXT: v_lshrrev_b32_e32 v180, 16, v23
+; GFX11-NEXT: v_lshrrev_b32_e32 v179, 8, v23
+; GFX11-NEXT: v_lshrrev_b32_e32 v44, 24, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v183, 16, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v182, 8, v26
+; GFX11-NEXT: v_lshrrev_b32_e32 v43, 16, v25
+; GFX11-NEXT: v_lshrrev_b32_e32 v42, 8, v25
+; GFX11-NEXT: v_lshrrev_b32_e32 v47, 24, v28
; GFX11-NEXT: v_lshrrev_b32_e32 v41, 16, v28
-; GFX11-NEXT: v_lshrrev_b32_e32 v183, 8, v28
-; GFX11-NEXT: v_lshrrev_b32_e32 v43, 16, v27
-; GFX11-NEXT: v_lshrrev_b32_e32 v182, 8, v27
-; GFX11-NEXT: v_lshrrev_b32_e32 v46, 24, v30
-; GFX11-NEXT: v_lshrrev_b32_e32 v44, 16, v30
-; GFX11-NEXT: v_lshrrev_b32_e32 v40, 8, v30
-; GFX11-NEXT: v_lshrrev_b32_e32 v47, 16, v29
-; GFX11-NEXT: v_lshrrev_b32_e32 v45, 8, v29
-; GFX11-NEXT: v_lshrrev_b32_e32 v59, 24, v34
-; GFX11-NEXT: v_lshrrev_b32_e32 v58, 16, v34
-; GFX11-NEXT: v_lshrrev_b32_e32 v57, 8, v34
-; GFX11-NEXT: v_lshrrev_b32_e32 v60, 16, v33
-; GFX11-NEXT: v_lshrrev_b32_e32 v56, 8, v33
-; GFX11-NEXT: v_lshrrev_b32_e32 v72, 24, v36
-; GFX11-NEXT: v_lshrrev_b32_e32 v62, 16, v36
-; GFX11-NEXT: v_lshrrev_b32_e32 v61, 8, v36
-; GFX11-NEXT: v_lshrrev_b32_e32 v73, 16, v35
-; GFX11-NEXT: v_lshrrev_b32_e32 v63, 8, v35
-; GFX11-NEXT: v_lshrrev_b32_e32 v50, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v40, 8, v28
+; GFX11-NEXT: v_lshrrev_b32_e32 v46, 16, v27
+; GFX11-NEXT: v_lshrrev_b32_e32 v45, 8, v27
+; GFX11-NEXT: v_lshrrev_b32_e32 v58, 24, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v57, 16, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v56, 8, v30
+; GFX11-NEXT: v_lshrrev_b32_e32 v63, 16, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v62, 8, v29
+; GFX11-NEXT: v_lshrrev_b32_e32 v72, 24, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v61, 16, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v60, 8, v32
+; GFX11-NEXT: v_lshrrev_b32_e32 v73, 16, v31
+; GFX11-NEXT: v_lshrrev_b32_e32 v59, 8, v31
+; GFX11-NEXT: v_lshrrev_b32_e32 v55, 24, v2
; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v81, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v82, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v86, 24, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v97, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v87, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v100, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v99, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v96, 8, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v101, 16, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v98, 8, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v112, 24, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v103, 16, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v102, 8, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v115, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v113, 8, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v118, 24, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v117, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v114, 8, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v119, 16, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v116, 8, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v130, 24, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v129, 16, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v128, 8, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v133, 16, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v131, 8, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v144, 24, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v135, 16, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v132, 8, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v145, 16, v15
-; GFX11-NEXT: v_lshrrev_b32_e32 v134, 8, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v68, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v70, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v80, 24, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v81, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v85, 24, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v86, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v96, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v98, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v97, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v99, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v100, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v101, 8, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v103, 24, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v102, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v112, 8, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v113, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v114, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v116, 24, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v115, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v117, 8, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v118, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v119, 8, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v129, 24, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v128, 16, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v130, 8, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v131, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v132, 8, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v134, 24, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v133, 16, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v135, 8, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v144, 16, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v145, 8, v15
; GFX11-NEXT: s_branch .LBB99_5
; GFX11-NEXT: .LBB99_3:
; GFX11-NEXT: ; implicit-def: $sgpr43
@@ -206463,287 +205413,255 @@ define inreg <128 x i8> @bitcast_v64i16_to_v128i8_scalar(<64 x i16> inreg %a, i3
; GFX11-NEXT: ; kill: killed $sgpr43
; GFX11-NEXT: s_branch .LBB99_2
; GFX11-NEXT: .LBB99_4:
-; GFX11-NEXT: v_dual_mov_b32 v35, s0 :: v_dual_mov_b32 v36, s1
+; GFX11-NEXT: v_dual_mov_b32 v31, s0 :: v_dual_mov_b32 v32, s1
; GFX11-NEXT: v_readlane_b32 s0, v76, 0
; GFX11-NEXT: v_dual_mov_b32 v15, s28 :: v_dual_mov_b32 v16, s29
; GFX11-NEXT: v_dual_mov_b32 v13, s40 :: v_dual_mov_b32 v14, s41
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v63, s0
+; GFX11-NEXT: v_mov_b32_e32 v59, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 1
; GFX11-NEXT: v_dual_mov_b32 v11, s14 :: v_dual_mov_b32 v12, s15
; GFX11-NEXT: v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v10, s13
; GFX11-NEXT: v_mov_b32_e32 v73, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 2
+; GFX11-NEXT: v_mov_b32_e32 v39, s34
; GFX11-NEXT: v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11
; GFX11-NEXT: v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v61, s0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mov_b32_e32 v60, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 3
; GFX11-NEXT: v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7
; GFX11-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5
-; GFX11-NEXT: v_mov_b32_e32 v62, s0
+; GFX11-NEXT: v_mov_b32_e32 v61, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 4
-; GFX11-NEXT: v_dual_mov_b32 v33, s2 :: v_dual_mov_b32 v34, s3
-; GFX11-NEXT: v_dual_mov_b32 v29, s16 :: v_dual_mov_b32 v30, s17
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_mov_b32_e32 v55, vcc_hi
+; GFX11-NEXT: v_dual_mov_b32 v29, s2 :: v_dual_mov_b32 v30, s3
+; GFX11-NEXT: v_dual_mov_b32 v27, s16 :: v_dual_mov_b32 v28, s17
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v72, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 5
-; GFX11-NEXT: v_dual_mov_b32 v27, s18 :: v_dual_mov_b32 v28, s19
+; GFX11-NEXT: v_dual_mov_b32 v25, s18 :: v_dual_mov_b32 v26, s19
; GFX11-NEXT: v_dual_mov_b32 v23, s20 :: v_dual_mov_b32 v24, s21
-; GFX11-NEXT: v_mov_b32_e32 v56, s0
+; GFX11-NEXT: v_mov_b32_e32 v62, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 6
; GFX11-NEXT: v_dual_mov_b32 v21, s22 :: v_dual_mov_b32 v22, s23
; GFX11-NEXT: v_dual_mov_b32 v19, s24 :: v_dual_mov_b32 v20, s25
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v60, s0
+; GFX11-NEXT: v_mov_b32_e32 v63, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 7
; GFX11-NEXT: v_dual_mov_b32 v17, s26 :: v_dual_mov_b32 v18, s27
-; GFX11-NEXT: v_dual_mov_b32 v134, s104 :: v_dual_mov_b32 v145, s102
-; GFX11-NEXT: v_mov_b32_e32 v57, s0
+; GFX11-NEXT: v_dual_mov_b32 v145, s104 :: v_dual_mov_b32 v144, s102
+; GFX11-NEXT: v_mov_b32_e32 v56, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 8
-; GFX11-NEXT: v_dual_mov_b32 v132, s103 :: v_dual_mov_b32 v135, s101
-; GFX11-NEXT: v_dual_mov_b32 v144, s100 :: v_dual_mov_b32 v131, s99
+; GFX11-NEXT: v_dual_mov_b32 v135, s103 :: v_dual_mov_b32 v134, s100
+; GFX11-NEXT: v_dual_mov_b32 v133, s101 :: v_dual_mov_b32 v132, s99
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v58, s0
+; GFX11-NEXT: v_mov_b32_e32 v57, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 9
-; GFX11-NEXT: v_dual_mov_b32 v133, s97 :: v_dual_mov_b32 v128, s98
-; GFX11-NEXT: v_dual_mov_b32 v129, s96 :: v_dual_mov_b32 v130, s87
-; GFX11-NEXT: v_mov_b32_e32 v59, s0
+; GFX11-NEXT: v_dual_mov_b32 v131, s97 :: v_dual_mov_b32 v130, s98
+; GFX11-NEXT: v_dual_mov_b32 v128, s96 :: v_dual_mov_b32 v129, s87
+; GFX11-NEXT: v_mov_b32_e32 v58, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 10
-; GFX11-NEXT: v_dual_mov_b32 v116, s86 :: v_dual_mov_b32 v119, s84
-; GFX11-NEXT: v_dual_mov_b32 v114, s85 :: v_dual_mov_b32 v117, s83
+; GFX11-NEXT: v_dual_mov_b32 v119, s86 :: v_dual_mov_b32 v118, s84
+; GFX11-NEXT: v_dual_mov_b32 v117, s85 :: v_dual_mov_b32 v116, s82
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v45, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 11
-; GFX11-NEXT: v_dual_mov_b32 v118, s82 :: v_dual_mov_b32 v113, s81
-; GFX11-NEXT: v_dual_mov_b32 v115, s71 :: v_dual_mov_b32 v102, s80
-; GFX11-NEXT: v_mov_b32_e32 v47, s0
+; GFX11-NEXT: v_dual_mov_b32 v115, s83 :: v_dual_mov_b32 v114, s81
+; GFX11-NEXT: v_dual_mov_b32 v113, s71 :: v_dual_mov_b32 v112, s80
+; GFX11-NEXT: v_mov_b32_e32 v46, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 12
-; GFX11-NEXT: v_dual_mov_b32 v103, s70 :: v_dual_mov_b32 v112, s69
-; GFX11-NEXT: v_dual_mov_b32 v98, s68 :: v_dual_mov_b32 v101, s66
+; GFX11-NEXT: v_dual_mov_b32 v102, s70 :: v_dual_mov_b32 v103, s69
+; GFX11-NEXT: v_dual_mov_b32 v101, s68 :: v_dual_mov_b32 v100, s66
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v40, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 13
-; GFX11-NEXT: v_dual_mov_b32 v96, s67 :: v_dual_mov_b32 v99, s65
-; GFX11-NEXT: v_dual_mov_b32 v100, s64 :: v_dual_mov_b32 v87, s55
-; GFX11-NEXT: v_mov_b32_e32 v44, s0
+; GFX11-NEXT: v_dual_mov_b32 v99, s67 :: v_dual_mov_b32 v98, s64
+; GFX11-NEXT: v_dual_mov_b32 v97, s65 :: v_dual_mov_b32 v96, s55
+; GFX11-NEXT: v_mov_b32_e32 v41, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 14
-; GFX11-NEXT: v_dual_mov_b32 v97, s53 :: v_dual_mov_b32 v86, s51
-; GFX11-NEXT: v_dual_mov_b32 v83, s54 :: v_dual_mov_b32 v82, s50
+; GFX11-NEXT: v_dual_mov_b32 v87, s53 :: v_dual_mov_b32 v86, s54
+; GFX11-NEXT: v_dual_mov_b32 v84, s52 :: v_dual_mov_b32 v85, s51
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v46, s0
+; GFX11-NEXT: v_mov_b32_e32 v47, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 15
-; GFX11-NEXT: v_dual_mov_b32 v85, s52 :: v_dual_mov_b32 v84, s48
-; GFX11-NEXT: v_dual_mov_b32 v55, s49 :: v_dual_mov_b32 v80, s39
-; GFX11-NEXT: v_mov_b32_e32 v182, s0
+; GFX11-NEXT: v_dual_mov_b32 v83, s50 :: v_dual_mov_b32 v82, s48
+; GFX11-NEXT: v_dual_mov_b32 v81, s49 :: v_dual_mov_b32 v80, s38
+; GFX11-NEXT: v_mov_b32_e32 v42, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 16
-; GFX11-NEXT: v_dual_mov_b32 v81, s38 :: v_dual_mov_b32 v32, s37
-; GFX11-NEXT: v_dual_mov_b32 v71, s35 :: v_dual_mov_b32 v26, s36
+; GFX11-NEXT: v_dual_mov_b32 v71, s39 :: v_dual_mov_b32 v70, s37
+; GFX11-NEXT: v_dual_mov_b32 v69, s35 :: v_dual_mov_b32 v68, s36
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-NEXT: v_mov_b32_e32 v43, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 17
-; GFX11-NEXT: v_dual_mov_b32 v39, s34 :: v_dual_mov_b32 v50, vcc_hi
-; GFX11-NEXT: v_dual_mov_b32 v51, s72 :: v_dual_mov_b32 v52, s62
-; GFX11-NEXT: v_mov_b32_e32 v183, s0
+; GFX11-NEXT: v_dual_mov_b32 v49, s62 :: v_dual_mov_b32 v52, s56
+; GFX11-NEXT: v_dual_mov_b32 v51, s58 :: v_dual_mov_b32 v54, s44
+; GFX11-NEXT: v_mov_b32_e32 v182, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 18
-; GFX11-NEXT: v_dual_mov_b32 v53, s60 :: v_dual_mov_b32 v54, s58
-; GFX11-NEXT: v_dual_mov_b32 v64, s56 :: v_dual_mov_b32 v65, s46
+; GFX11-NEXT: v_dual_mov_b32 v53, s46 :: v_dual_mov_b32 v64, s42
+; GFX11-NEXT: v_dual_mov_b32 v33, s74 :: v_dual_mov_b32 v34, s76
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v41, s0
+; GFX11-NEXT: v_mov_b32_e32 v183, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 19
-; GFX11-NEXT: v_dual_mov_b32 v69, s44 :: v_dual_mov_b32 v70, s42
-; GFX11-NEXT: v_dual_mov_b32 v25, s74 :: v_dual_mov_b32 v38, s88
-; GFX11-NEXT: v_mov_b32_e32 v42, s0
+; GFX11-NEXT: v_dual_mov_b32 v35, s78 :: v_dual_mov_b32 v36, s88
+; GFX11-NEXT: v_dual_mov_b32 v37, s90 :: v_dual_mov_b32 v38, s92
+; GFX11-NEXT: v_mov_b32_e32 v44, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 20
-; GFX11-NEXT: v_dual_mov_b32 v31, s76 :: v_dual_mov_b32 v48, s90
-; GFX11-NEXT: v_dual_mov_b32 v37, s78 :: v_dual_mov_b32 v66, s94
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_mov_b32_e32 v177, s0
+; GFX11-NEXT: v_dual_mov_b32 v65, s94 :: v_dual_mov_b32 v66, s30
+; GFX11-NEXT: v_mov_b32_e32 v48, s72
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v50, s60 :: v_dual_mov_b32 v179, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 21
-; GFX11-NEXT: v_mov_b32_e32 v49, s92
-; GFX11-NEXT: v_mov_b32_e32 v67, s30
-; GFX11-NEXT: v_mov_b32_e32 v181, s0
+; GFX11-NEXT: v_mov_b32_e32 v180, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 22
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v167, s0
+; GFX11-NEXT: v_mov_b32_e32 v166, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 23
-; GFX11-NEXT: v_mov_b32_e32 v179, s0
+; GFX11-NEXT: v_mov_b32_e32 v167, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v180, s0
+; GFX11-NEXT: v_mov_b32_e32 v181, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 25
; GFX11-NEXT: v_mov_b32_e32 v176, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 26
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v178, s0
+; GFX11-NEXT: v_mov_b32_e32 v177, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 27
; GFX11-NEXT: v_mov_b32_e32 v164, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 28
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v165, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 29
-; GFX11-NEXT: v_mov_b32_e32 v166, s0
+; GFX11-NEXT: v_mov_b32_e32 v178, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 30
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v151, s0
+; GFX11-NEXT: v_mov_b32_e32 v161, s0
; GFX11-NEXT: v_readlane_b32 s0, v76, 31
-; GFX11-NEXT: v_mov_b32_e32 v163, s0
+; GFX11-NEXT: v_mov_b32_e32 v162, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v149, s0
+; GFX11-NEXT: v_mov_b32_e32 v148, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 1
-; GFX11-NEXT: v_mov_b32_e32 v161, s0
+; GFX11-NEXT: v_mov_b32_e32 v149, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v162, s0
+; GFX11-NEXT: v_mov_b32_e32 v163, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 3
; GFX11-NEXT: v_mov_b32_e32 v150, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 4
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_mov_b32_e32 v160, s0
+; GFX11-NEXT: v_mov_b32_e32 v151, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 5
; GFX11-NEXT: v_mov_b32_e32 v146, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_mov_b32_e32 v147, s0
; GFX11-NEXT: v_readlane_b32 s0, v77, 7
-; GFX11-NEXT: v_mov_b32_e32 v148, s0
+; GFX11-NEXT: v_mov_b32_e32 v160, s0
; GFX11-NEXT: .LBB99_5: ; %end
-; GFX11-NEXT: v_perm_b32 v68, v73, v70, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v70, v62, v72, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v69, v60, v69, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v36, v36, v61, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v65, v47, v65, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v43, v64, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v70, 16, v70
-; GFX11-NEXT: v_perm_b32 v35, v35, v63, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
-; GFX11-NEXT: v_perm_b32 v56, v33, v56, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
-; GFX11-NEXT: v_perm_b32 v58, v58, v59, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v57, v34, v57, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v34, v36, v70
-; GFX11-NEXT: v_perm_b32 v29, v29, v45, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v65, 16, v65
-; GFX11-NEXT: v_perm_b32 v70, v27, v182, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
-; GFX11-NEXT: v_or_b32_e32 v33, v35, v68
-; GFX11-NEXT: v_or_b32_e32 v35, v56, v69
-; GFX11-NEXT: v_perm_b32 v68, v44, v46, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v69, v41, v42, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v58, 16, v58
-; GFX11-NEXT: v_or_b32_e32 v27, v29, v65
-; GFX11-NEXT: v_or_b32_e32 v29, v70, v64
-; GFX11-NEXT: v_perm_b32 v54, v181, v54, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v64, v179, v180, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v53, v178, v53, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v30, v30, v40, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v68, 16, v68
-; GFX11-NEXT: v_perm_b32 v182, v28, v183, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v69
-; GFX11-NEXT: v_or_b32_e32 v36, v57, v58
-; GFX11-NEXT: v_perm_b32 v23, v23, v177, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v54, 16, v54
-; GFX11-NEXT: v_perm_b32 v24, v24, v167, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v64, 16, v64
-; GFX11-NEXT: v_perm_b32 v21, v21, v176, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-NEXT: v_or_b32_e32 v28, v30, v68
-; GFX11-NEXT: v_or_b32_e32 v30, v182, v69
+; GFX11-NEXT: v_perm_b32 v29, v29, v62, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v54, v63, v54, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v73, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v31, v59, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v32, v60, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v67, v61, v72, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v61, v54, 16, v29
+; GFX11-NEXT: v_perm_b32 v29, v30, v56, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v57, v58, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v59, v64, 16, v31
+; GFX11-NEXT: v_lshl_or_b32 v60, v67, 16, v32
+; GFX11-NEXT: v_perm_b32 v27, v27, v45, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v46, v53, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v28, v40, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v41, v47, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v53, v25, v42, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v52, v43, v52, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v54, v26, v182, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v64, v183, v44, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v62, v30, 16, v29
+; GFX11-NEXT: v_perm_b32 v23, v23, v179, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v180, v51, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v24, v166, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v167, v181, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v25, v31, 16, v27
+; GFX11-NEXT: v_lshl_or_b32 v26, v32, 16, v28
+; GFX11-NEXT: v_lshl_or_b32 v27, v52, 16, v53
+; GFX11-NEXT: v_lshl_or_b32 v28, v64, 16, v54
+; GFX11-NEXT: v_perm_b32 v31, v21, v176, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v177, v50, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v50, v22, v164, 0xc0c0004
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: scratch_store_b128 v0, v[33:36], off
-; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:16
-; GFX11-NEXT: v_or_b32_e32 v27, v23, v54
-; GFX11-NEXT: v_perm_b32 v23, v165, v166, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v28, v24, v64
-; GFX11-NEXT: v_or_b32_e32 v29, v21, v53
-; GFX11-NEXT: v_perm_b32 v21, v22, v164, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v22, v163, v52, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v161, v162, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v30, v160, v51, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v17, v17, v150, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v33, 16, v30
-; GFX11-NEXT: v_or_b32_e32 v30, v21, v23
-; GFX11-NEXT: v_or_b32_e32 v19, v19, v22
-; GFX11-NEXT: v_perm_b32 v22, v147, v148, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v20, v20, v24
-; GFX11-NEXT: v_or_b32_e32 v21, v17, v33
-; GFX11-NEXT: v_perm_b32 v17, v18, v146, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v145, v67, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v133, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v135, v144, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_perm_b32 v15, v15, v134, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v13, v13, v131, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v16, v16, v132, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v22, v17, v22
-; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
-; GFX11-NEXT: v_perm_b32 v18, v129, v130, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v17, v13, v24
-; GFX11-NEXT: v_perm_b32 v24, v115, v48, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v23
-; GFX11-NEXT: v_perm_b32 v13, v14, v128, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v14, v119, v49, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v117, v118, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v9, v9, v113, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v11, v11, v116, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v12, v12, v114, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_or_b32_e32 v18, v13, v18
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v24
-; GFX11-NEXT: v_perm_b32 v9, v10, v102, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v101, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
-; GFX11-NEXT: v_perm_b32 v14, v103, v112, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v23
-; GFX11-NEXT: v_perm_b32 v23, v99, v100, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v97, v37, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v98, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v8, v8, v96, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_perm_b32 v5, v5, v87, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
-; GFX11-NEXT: v_perm_b32 v10, v85, v86, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v23
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v24
-; GFX11-NEXT: v_perm_b32 v5, v84, v31, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v23, v80, v81, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v71, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v39, v50, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v83, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v55, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-NEXT: v_perm_b32 v31, v1, v32, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v26, v2, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v23
-; GFX11-NEXT: v_or_b32_e32 v3, v31, v24
-; GFX11-NEXT: v_or_b32_e32 v4, v26, v25
+; GFX11-NEXT: scratch_store_b128 v0, v[59:62], off
+; GFX11-NEXT: scratch_store_b128 v0, v[25:28], off offset:16
+; GFX11-NEXT: v_lshl_or_b32 v21, v29, 16, v23
+; GFX11-NEXT: v_lshl_or_b32 v22, v30, 16, v24
+; GFX11-NEXT: v_perm_b32 v19, v19, v161, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v162, v49, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v20, v148, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v26, v149, v163, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v17, v150, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v151, v48, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v18, v146, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v147, v160, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v23, v32, 16, v31
+; GFX11-NEXT: v_perm_b32 v15, v15, v145, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v144, v66, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v17, v25, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v18, v26, 16, v20
+; GFX11-NEXT: v_lshl_or_b32 v19, v28, 16, v27
+; GFX11-NEXT: v_lshl_or_b32 v20, v30, 16, v29
+; GFX11-NEXT: v_perm_b32 v13, v13, v132, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v27, v131, v65, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v11, v119, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v118, v38, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v25, v31, 16, v15
+; GFX11-NEXT: v_perm_b32 v15, v16, v135, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v133, v134, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v14, v14, v130, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v28, v128, v129, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v27, v27, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v11, v29, 16, v11
+; GFX11-NEXT: v_perm_b32 v9, v9, v114, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v113, v37, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v96, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v87, v35, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v51, v165, v178, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v12, v117, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v115, v116, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v26, v16, 16, v15
+; GFX11-NEXT: v_perm_b32 v7, v7, v101, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v100, v36, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v8, v8, v99, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v97, v98, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v28, v28, 16, v14
+; GFX11-NEXT: v_perm_b32 v10, v10, v112, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v14, v102, v103, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v9, v29, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v86, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v84, v85, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v24, v51, 16, v50
+; GFX11-NEXT: v_lshl_or_b32 v12, v30, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v7, v15, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v8, v16, 16, v8
+; GFX11-NEXT: v_perm_b32 v3, v3, v83, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v82, v34, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v81, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v71, v80, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v29, v1, v70, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v30, v69, v33, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v2, v68, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v32, v39, v55, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v14, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v10, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v1, v15, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v16, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v30, 16, v29
+; GFX11-NEXT: v_lshl_or_b32 v4, v32, 16, v31
; GFX11-NEXT: s_clause 0x5
-; GFX11-NEXT: scratch_store_b128 v0, v[27:30], off offset:32
-; GFX11-NEXT: scratch_store_b128 v0, v[19:22], off offset:48
-; GFX11-NEXT: scratch_store_b128 v0, v[15:18], off offset:64
+; GFX11-NEXT: scratch_store_b128 v0, v[21:24], off offset:32
+; GFX11-NEXT: scratch_store_b128 v0, v[17:20], off offset:48
+; GFX11-NEXT: scratch_store_b128 v0, v[25:28], off offset:64
; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:80
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:96
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:112
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
index 7e231f48de12a..b35cd046669a7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.128bit.ll
@@ -4692,31 +4692,27 @@ define inreg <4 x i32> @bitcast_v16i8_to_v4i32_scalar(<16 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -4772,24 +4768,19 @@ define inreg <4 x i32> @bitcast_v16i8_to_v4i32_scalar(<16 x i8> inreg %a, i32 in
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
-; GFX11-NEXT: v_perm_b32 v7, s26, s27, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
-; GFX11-NEXT: v_perm_b32 v8, s24, s25, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v8, v6
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v0
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-NEXT: .LBB27_2: ; %cmp.true
@@ -9219,31 +9210,27 @@ define inreg <4 x float> @bitcast_v16i8_to_v4f32_scalar(<16 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9299,24 +9286,19 @@ define inreg <4 x float> @bitcast_v16i8_to_v4f32_scalar(<16 x i8> inreg %a, i32
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
-; GFX11-NEXT: v_perm_b32 v7, s26, s27, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
-; GFX11-NEXT: v_perm_b32 v8, s24, s25, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v8, v6
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v0
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-NEXT: .LBB51_2: ; %cmp.true
@@ -13331,31 +13313,27 @@ define inreg <2 x i64> @bitcast_v16i8_to_v2i64_scalar(<16 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -13411,24 +13389,19 @@ define inreg <2 x i64> @bitcast_v16i8_to_v2i64_scalar(<16 x i8> inreg %a, i32 in
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
-; GFX11-NEXT: v_perm_b32 v7, s26, s27, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
-; GFX11-NEXT: v_perm_b32 v8, s24, s25, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v8, v6
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v0
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-NEXT: .LBB71_2: ; %cmp.true
@@ -17081,31 +17054,27 @@ define inreg <2 x double> @bitcast_v16i8_to_v2f64_scalar(<16 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -17161,24 +17130,19 @@ define inreg <2 x double> @bitcast_v16i8_to_v2f64_scalar(<16 x i8> inreg %a, i32
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
-; GFX11-NEXT: v_perm_b32 v7, s26, s27, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
-; GFX11-NEXT: v_perm_b32 v8, s24, s25, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v8, v6
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v0
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-NEXT: .LBB87_2: ; %cmp.true
@@ -20627,31 +20591,27 @@ define inreg <8 x i16> @bitcast_v16i8_to_v8i16_scalar(<16 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB99_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB99_3
; GFX9-NEXT: .LBB99_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -20707,24 +20667,19 @@ define inreg <8 x i16> @bitcast_v16i8_to_v8i16_scalar(<16 x i8> inreg %a, i32 in
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
-; GFX11-NEXT: v_perm_b32 v7, s26, s27, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
-; GFX11-NEXT: v_perm_b32 v8, s24, s25, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v8, v6
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v0
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB99_3
; GFX11-NEXT: .LBB99_2: ; %cmp.true
@@ -23623,31 +23578,27 @@ define inreg <8 x half> @bitcast_v16i8_to_v8f16_scalar(<16 x i8> inreg %a, i32 i
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB107_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB107_3
; GFX9-NEXT: .LBB107_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -23703,24 +23654,19 @@ define inreg <8 x half> @bitcast_v16i8_to_v8f16_scalar(<16 x i8> inreg %a, i32 i
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
-; GFX11-NEXT: v_perm_b32 v7, s26, s27, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
-; GFX11-NEXT: v_perm_b32 v8, s24, s25, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v8, v6
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v0
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB107_3
; GFX11-NEXT: .LBB107_2: ; %cmp.true
@@ -25924,31 +25870,27 @@ define inreg <8 x bfloat> @bitcast_v16i8_to_v8bf16_scalar(<16 x i8> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s7, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB111_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v3, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v4, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_perm_b32 v4, s26, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v5, s6
; GFX9-NEXT: v_perm_b32 v4, s28, v4, v3
; GFX9-NEXT: v_perm_b32 v3, s7, v5, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v3, 16, v4
; GFX9-NEXT: s_cbranch_execnz .LBB111_3
; GFX9-NEXT: .LBB111_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -26004,24 +25946,19 @@ define inreg <8 x bfloat> @bitcast_v16i8_to_v8bf16_scalar(<16 x i8> inreg %a, i3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
-; GFX11-NEXT: v_perm_b32 v7, s26, s27, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
-; GFX11-NEXT: v_perm_b32 v8, s24, s25, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v7
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v8, v6
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v0
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB111_3
; GFX11-NEXT: .LBB111_2: ; %cmp.true
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
index 224b73353c3bc..281799445136b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.256bit.ll
@@ -7365,55 +7365,47 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_mov_b32_e32 v4, s46
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s44
-; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_mov_b32_e32 v5, s42
; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v6, s14
; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s12
-; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_mov_b32_e32 v8, s10
; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -7519,39 +7511,31 @@ define inreg <8 x i32> @bitcast_v32i8_to_v8i32_scalar(<32 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB27_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_perm_b32 v4, s26, s27, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v12, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-NEXT: v_perm_b32 v6, s41, s40, v3
+; GFX11-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v4, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v5, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v6, v11, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v13, 16, v12
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-NEXT: .LBB27_2: ; %cmp.true
@@ -14633,55 +14617,47 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_mov_b32_e32 v4, s46
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s44
-; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_mov_b32_e32 v5, s42
; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v6, s14
; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s12
-; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_mov_b32_e32 v8, s10
; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -14787,39 +14763,31 @@ define inreg <8 x float> @bitcast_v32i8_to_v8f32_scalar(<32 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB51_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_perm_b32 v4, s26, s27, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v12, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-NEXT: v_perm_b32 v6, s41, s40, v3
+; GFX11-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v4, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v5, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v6, v11, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v13, 16, v12
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-NEXT: .LBB51_2: ; %cmp.true
@@ -21362,55 +21330,47 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_mov_b32_e32 v4, s46
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s44
-; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_mov_b32_e32 v5, s42
; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v6, s14
; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s12
-; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_mov_b32_e32 v8, s10
; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -21516,39 +21476,31 @@ define inreg <4 x i64> @bitcast_v32i8_to_v4i64_scalar(<32 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB71_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_perm_b32 v4, s26, s27, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v12, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-NEXT: v_perm_b32 v6, s41, s40, v3
+; GFX11-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v4, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v5, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v6, v11, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v13, 16, v12
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-NEXT: .LBB71_2: ; %cmp.true
@@ -27624,55 +27576,47 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s47, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v7, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v7
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v7
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s46
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_mov_b32_e32 v4, s46
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s47, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s44
-; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_mov_b32_e32 v5, s42
; GFX9-NEXT: v_perm_b32 v4, s45, v4, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s14
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s43, v5, v7
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_mov_b32_e32 v6, s14
; GFX9-NEXT: v_perm_b32 v5, s41, v5, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v8, s10
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s15, v6, v7
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s12
-; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_mov_b32_e32 v8, s10
; GFX9-NEXT: v_perm_b32 v6, s13, v6, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v8
+; GFX9-NEXT: v_perm_b32 v8, s11, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v6, v8, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v8, s8
; GFX9-NEXT: v_mov_b32_e32 v9, s6
; GFX9-NEXT: v_perm_b32 v8, s9, v8, v7
; GFX9-NEXT: v_perm_b32 v7, s7, v9, v7
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v7, v8, v7
+; GFX9-NEXT: v_lshl_or_b32 v7, v7, 16, v8
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -27778,39 +27722,31 @@ define inreg <4 x double> @bitcast_v32i8_to_v4f64_scalar(<32 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB87_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v3, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
-; GFX11-NEXT: v_perm_b32 v5, s22, s23, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v3
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v3
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v3
-; GFX11-NEXT: v_perm_b32 v9, s41, s40, v3
-; GFX11-NEXT: v_perm_b32 v11, s5, s4, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v4
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s13, s12, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v9
-; GFX11-NEXT: v_perm_b32 v9, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v3
+; GFX11-NEXT: v_perm_b32 v5, s20, s21, v3
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v3
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v3
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v2
+; GFX11-NEXT: v_perm_b32 v4, s26, s27, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: v_perm_b32 v5, s28, s29, v3
-; GFX11-NEXT: v_perm_b32 v10, s15, s14, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v12, s11, s10, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v13, s7, s6, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v4
-; GFX11-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v12, v9
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v11
+; GFX11-NEXT: v_perm_b32 v6, s41, s40, v3
+; GFX11-NEXT: v_perm_b32 v8, s15, s14, v3
+; GFX11-NEXT: v_perm_b32 v9, s13, s12, v3
+; GFX11-NEXT: v_perm_b32 v10, s11, s10, v3
+; GFX11-NEXT: v_perm_b32 v11, s9, s8, v3
+; GFX11-NEXT: v_perm_b32 v12, s7, s6, v3
+; GFX11-NEXT: v_perm_b32 v13, s5, s4, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v4, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v5, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v6, v11, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v13, 16, v12
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-NEXT: .LBB87_2: ; %cmp.true
@@ -33789,47 +33725,47 @@ define inreg <16 x i16> @bitcast_v32i8_to_v16i16_scalar(<32 x i8> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v4
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: s_and_b32 s4, s14, 0xff
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: s_lshl_b32 s5, s12, 8
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v4
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: s_and_b32 s4, s9, 0xff
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: s_lshl_b32 s56, s7, 8
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s6
-; GFX9-NEXT: s_and_b32 s4, s14, 0xff
-; GFX9-NEXT: s_lshl_b32 s5, s12, 8
+; GFX9-NEXT: s_or_b32 s56, s56, s4
; GFX9-NEXT: v_perm_b32 v5, s8, v5, v4
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s9, 0xff
-; GFX9-NEXT: s_lshl_b32 s56, s7, 8
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s56
+; GFX9-NEXT: s_and_b32 s5, s11, 0xff
; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
-; GFX9-NEXT: s_or_b32 s5, s5, s56
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: v_perm_b32 v5, s42, v5, v4
-; GFX9-NEXT: s_and_b32 s5, s11, 0xff
; GFX9-NEXT: s_lshl_b32 s56, s10, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s56
+; GFX9-NEXT: v_perm_b32 v5, s42, v5, v4
+; GFX9-NEXT: s_or_b32 s56, s56, s5
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX9-NEXT: v_lshl_or_b32 v5, s5, 16, v5
; GFX9-NEXT: s_and_b32 s5, s45, 0xff
+; GFX9-NEXT: v_lshl_or_b32 v5, s56, 16, v5
; GFX9-NEXT: s_lshl_b32 s56, s44, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s56
-; GFX9-NEXT: s_and_b32 s56, s15, 0xff
+; GFX9-NEXT: s_or_b32 s56, s56, s5
+; GFX9-NEXT: s_and_b32 s5, s15, 0xff
; GFX9-NEXT: s_lshl_b32 s57, s13, 8
-; GFX9-NEXT: s_or_b32 s56, s56, s57
+; GFX9-NEXT: s_or_b32 s57, s57, s5
+; GFX9-NEXT: s_pack_ll_b32_b16 s5, s56, s57
; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s56
-; GFX9-NEXT: v_perm_b32 v4, s47, v6, v4
; GFX9-NEXT: s_and_b32 s56, s43, 0xff
+; GFX9-NEXT: v_perm_b32 v4, s47, v6, v4
; GFX9-NEXT: s_lshl_b32 s57, s41, 8
-; GFX9-NEXT: s_or_b32 s56, s56, s57
+; GFX9-NEXT: s_or_b32 s57, s57, s56
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX9-NEXT: v_lshl_or_b32 v7, s56, 16, v4
+; GFX9-NEXT: v_lshl_or_b32 v7, s57, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v6, s5
; GFX9-NEXT: s_cbranch_execnz .LBB99_3
@@ -33943,45 +33879,45 @@ define inreg <16 x i16> @bitcast_v32i8_to_v16i16_scalar(<32 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB99_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: s_and_b32 s43, s11, 0xff
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_lshl_b32 s44, s7, 8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_or_b32 s44, s44, s43
; GFX11-TRUE16-NEXT: s_and_b32 s43, s28, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s44, s29, 8
; GFX11-TRUE16-NEXT: s_and_b32 s45, s12, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s9, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s43, s43, s44
-; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s18, s19, v4
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s43, s43, s44
-; GFX11-TRUE16-NEXT: s_and_b32 s44, s11, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s7, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s2, s3, v4
-; GFX11-TRUE16-NEXT: s_or_b32 s44, s44, s45
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s40, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s10, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
+; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s29, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s46, s46, s43
+; GFX11-TRUE16-NEXT: s_lshl_b32 s43, s9, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s43, s43, s45
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s44
-; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s8, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s4, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s44, s8, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s40, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s47, s4, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s47, s47, s44
+; GFX11-TRUE16-NEXT: s_and_b32 s44, s14, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s56, s10, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s18, s19, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s56, s56, s45
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v4
+; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s5, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v4
-; GFX11-TRUE16-NEXT: s_or_b32 s45, s45, s46
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s22, s23, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s47, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s5, 8
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s45
-; GFX11-TRUE16-NEXT: s_or_b32 s45, s47, s46
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s45, s45, s44
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v4
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s44, s44, s45
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s43, s46, s43
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s44, s56, s45
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s41, s15, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s13, s6, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, s47
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, s43
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s44
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
@@ -34072,52 +34008,53 @@ define inreg <16 x i16> @bitcast_v32i8_to_v16i16_scalar(<32 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: s_mov_b32 s42, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB99_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s43, s28, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s44, s29, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s45, s5, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s43, s43, s44
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s44, s9, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v4
-; GFX11-FAKE16-NEXT: s_or_b32 s44, s44, s45
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_or_b32 s44, s44, s43
+; GFX11-FAKE16-NEXT: s_and_b32 s43, s9, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s45, s7, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s46, s5, 8
+; GFX11-FAKE16-NEXT: s_or_b32 s46, s46, s43
+; GFX11-FAKE16-NEXT: s_lshl_b32 s43, s4, 8
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s44, s44, s46
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_or_b32 s43, s43, s45
+; GFX11-FAKE16-NEXT: s_and_b32 s45, s40, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s47, s13, 8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s18, s19, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s43, s43, s44
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: s_and_b32 s46, s7, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s47, s4, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s15, s8, v4
-; GFX11-FAKE16-NEXT: s_or_b32 s45, s46, s47
-; GFX11-FAKE16-NEXT: s_and_b32 s44, s40, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s41, s12, v4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s46, s6, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s47, s14, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s56, s10, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, s45, 16, v5
-; GFX11-FAKE16-NEXT: s_lshl_b32 s45, s13, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_or_b32 s44, s44, s45
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v5, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s15, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s41, s12, v3
+; GFX11-FAKE16-NEXT: s_or_b32 s47, s47, s45
; GFX11-FAKE16-NEXT: s_and_b32 s45, s11, 0xff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_or_b32 s45, s45, s46
-; GFX11-FAKE16-NEXT: s_or_b32 s46, s47, s56
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s44, s44, s45
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s44 :: v_dual_and_b32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v8, 16, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, s46, 16, v4
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, s43
+; GFX11-FAKE16-NEXT: s_and_b32 s56, s14, 0xff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: s_lshl_b32 s57, s6, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v7
+; GFX11-FAKE16-NEXT: s_or_b32 s57, s57, s45
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_lshl_b32 s45, s10, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, s43, 16, v5
+; GFX11-FAKE16-NEXT: s_or_b32 s45, s45, s56
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s43, s47, s57
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v8, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, s45, 16, v6
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, s44
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, s43
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB99_3
; GFX11-FAKE16-NEXT: .LBB99_2: ; %cmp.true
@@ -39248,47 +39185,47 @@ define inreg <16 x half> @bitcast_v32i8_to_v16f16_scalar(<32 x i8> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v4
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: s_and_b32 s4, s14, 0xff
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: s_lshl_b32 s5, s12, 8
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v4
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: s_and_b32 s4, s9, 0xff
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: s_lshl_b32 s56, s7, 8
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s6
-; GFX9-NEXT: s_and_b32 s4, s14, 0xff
-; GFX9-NEXT: s_lshl_b32 s5, s12, 8
+; GFX9-NEXT: s_or_b32 s56, s56, s4
; GFX9-NEXT: v_perm_b32 v5, s8, v5, v4
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s9, 0xff
-; GFX9-NEXT: s_lshl_b32 s56, s7, 8
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s56
+; GFX9-NEXT: s_and_b32 s5, s11, 0xff
; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
-; GFX9-NEXT: s_or_b32 s5, s5, s56
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: v_perm_b32 v5, s42, v5, v4
-; GFX9-NEXT: s_and_b32 s5, s11, 0xff
; GFX9-NEXT: s_lshl_b32 s56, s10, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s56
+; GFX9-NEXT: v_perm_b32 v5, s42, v5, v4
+; GFX9-NEXT: s_or_b32 s56, s56, s5
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX9-NEXT: v_lshl_or_b32 v5, s5, 16, v5
; GFX9-NEXT: s_and_b32 s5, s45, 0xff
+; GFX9-NEXT: v_lshl_or_b32 v5, s56, 16, v5
; GFX9-NEXT: s_lshl_b32 s56, s44, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s56
-; GFX9-NEXT: s_and_b32 s56, s15, 0xff
+; GFX9-NEXT: s_or_b32 s56, s56, s5
+; GFX9-NEXT: s_and_b32 s5, s15, 0xff
; GFX9-NEXT: s_lshl_b32 s57, s13, 8
-; GFX9-NEXT: s_or_b32 s56, s56, s57
+; GFX9-NEXT: s_or_b32 s57, s57, s5
+; GFX9-NEXT: s_pack_ll_b32_b16 s5, s56, s57
; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s56
-; GFX9-NEXT: v_perm_b32 v4, s47, v6, v4
; GFX9-NEXT: s_and_b32 s56, s43, 0xff
+; GFX9-NEXT: v_perm_b32 v4, s47, v6, v4
; GFX9-NEXT: s_lshl_b32 s57, s41, 8
-; GFX9-NEXT: s_or_b32 s56, s56, s57
+; GFX9-NEXT: s_or_b32 s57, s57, s56
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX9-NEXT: v_lshl_or_b32 v7, s56, 16, v4
+; GFX9-NEXT: v_lshl_or_b32 v7, s57, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v6, s5
; GFX9-NEXT: s_cbranch_execnz .LBB107_3
@@ -39402,45 +39339,45 @@ define inreg <16 x half> @bitcast_v32i8_to_v16f16_scalar(<32 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB107_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: s_and_b32 s43, s11, 0xff
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_lshl_b32 s44, s7, 8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_or_b32 s44, s44, s43
; GFX11-TRUE16-NEXT: s_and_b32 s43, s28, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s44, s29, 8
; GFX11-TRUE16-NEXT: s_and_b32 s45, s12, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s9, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s43, s43, s44
-; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s18, s19, v4
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s43, s43, s44
-; GFX11-TRUE16-NEXT: s_and_b32 s44, s11, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s7, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s2, s3, v4
-; GFX11-TRUE16-NEXT: s_or_b32 s44, s44, s45
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s40, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s10, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
+; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s29, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s46, s46, s43
+; GFX11-TRUE16-NEXT: s_lshl_b32 s43, s9, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s43, s43, s45
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s44
-; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s8, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s4, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s44, s8, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s40, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s47, s4, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s47, s47, s44
+; GFX11-TRUE16-NEXT: s_and_b32 s44, s14, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s56, s10, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s18, s19, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s56, s56, s45
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v4
+; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s5, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v4
-; GFX11-TRUE16-NEXT: s_or_b32 s45, s45, s46
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s22, s23, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s47, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s5, 8
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s45
-; GFX11-TRUE16-NEXT: s_or_b32 s45, s47, s46
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s45, s45, s44
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v4
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s44, s44, s45
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s43, s46, s43
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s44, s56, s45
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s41, s15, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s13, s6, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, s47
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, s43
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s44
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
@@ -39531,52 +39468,53 @@ define inreg <16 x half> @bitcast_v32i8_to_v16f16_scalar(<32 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: s_mov_b32 s42, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB107_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s43, s28, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s44, s29, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s45, s5, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s43, s43, s44
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s44, s9, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v4
-; GFX11-FAKE16-NEXT: s_or_b32 s44, s44, s45
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_or_b32 s44, s44, s43
+; GFX11-FAKE16-NEXT: s_and_b32 s43, s9, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s45, s7, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s46, s5, 8
+; GFX11-FAKE16-NEXT: s_or_b32 s46, s46, s43
+; GFX11-FAKE16-NEXT: s_lshl_b32 s43, s4, 8
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s44, s44, s46
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_or_b32 s43, s43, s45
+; GFX11-FAKE16-NEXT: s_and_b32 s45, s40, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s47, s13, 8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s18, s19, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s43, s43, s44
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: s_and_b32 s46, s7, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s47, s4, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s15, s8, v4
-; GFX11-FAKE16-NEXT: s_or_b32 s45, s46, s47
-; GFX11-FAKE16-NEXT: s_and_b32 s44, s40, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s41, s12, v4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s46, s6, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s47, s14, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s56, s10, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, s45, 16, v5
-; GFX11-FAKE16-NEXT: s_lshl_b32 s45, s13, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_or_b32 s44, s44, s45
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v5, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s15, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s41, s12, v3
+; GFX11-FAKE16-NEXT: s_or_b32 s47, s47, s45
; GFX11-FAKE16-NEXT: s_and_b32 s45, s11, 0xff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_or_b32 s45, s45, s46
-; GFX11-FAKE16-NEXT: s_or_b32 s46, s47, s56
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s44, s44, s45
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s44 :: v_dual_and_b32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v8, 16, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, s46, 16, v4
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, s43
+; GFX11-FAKE16-NEXT: s_and_b32 s56, s14, 0xff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: s_lshl_b32 s57, s6, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v7
+; GFX11-FAKE16-NEXT: s_or_b32 s57, s57, s45
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_lshl_b32 s45, s10, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, s43, 16, v5
+; GFX11-FAKE16-NEXT: s_or_b32 s45, s45, s56
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s43, s47, s57
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v8, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, s45, 16, v6
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, s44
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, s43
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB107_3
; GFX11-FAKE16-NEXT: .LBB107_2: ; %cmp.true
@@ -43628,47 +43566,47 @@ define inreg <16 x bfloat> @bitcast_v32i8_to_v16bf16_scalar(<32 x i8> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v2, s22, v2, v4
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX9-NEXT: s_and_b32 s4, s14, 0xff
; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-NEXT: s_lshl_b32 s5, s12, 8
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v4
; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_perm_b32 v3, s26, v3, v4
; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: s_and_b32 s4, s9, 0xff
; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-NEXT: s_lshl_b32 s56, s7, 8
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s6
-; GFX9-NEXT: s_and_b32 s4, s14, 0xff
-; GFX9-NEXT: s_lshl_b32 s5, s12, 8
+; GFX9-NEXT: s_or_b32 s56, s56, s4
; GFX9-NEXT: v_perm_b32 v5, s8, v5, v4
; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v3
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s9, 0xff
-; GFX9-NEXT: s_lshl_b32 s56, s7, 8
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s56
+; GFX9-NEXT: s_and_b32 s5, s11, 0xff
; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
-; GFX9-NEXT: s_or_b32 s5, s5, s56
; GFX9-NEXT: v_mov_b32_e32 v5, s40
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: v_perm_b32 v5, s42, v5, v4
-; GFX9-NEXT: s_and_b32 s5, s11, 0xff
; GFX9-NEXT: s_lshl_b32 s56, s10, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s56
+; GFX9-NEXT: v_perm_b32 v5, s42, v5, v4
+; GFX9-NEXT: s_or_b32 s56, s56, s5
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX9-NEXT: v_lshl_or_b32 v5, s5, 16, v5
; GFX9-NEXT: s_and_b32 s5, s45, 0xff
+; GFX9-NEXT: v_lshl_or_b32 v5, s56, 16, v5
; GFX9-NEXT: s_lshl_b32 s56, s44, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s56
-; GFX9-NEXT: s_and_b32 s56, s15, 0xff
+; GFX9-NEXT: s_or_b32 s56, s56, s5
+; GFX9-NEXT: s_and_b32 s5, s15, 0xff
; GFX9-NEXT: s_lshl_b32 s57, s13, 8
-; GFX9-NEXT: s_or_b32 s56, s56, s57
+; GFX9-NEXT: s_or_b32 s57, s57, s5
+; GFX9-NEXT: s_pack_ll_b32_b16 s5, s56, s57
; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s56
-; GFX9-NEXT: v_perm_b32 v4, s47, v6, v4
; GFX9-NEXT: s_and_b32 s56, s43, 0xff
+; GFX9-NEXT: v_perm_b32 v4, s47, v6, v4
; GFX9-NEXT: s_lshl_b32 s57, s41, 8
-; GFX9-NEXT: s_or_b32 s56, s56, s57
+; GFX9-NEXT: s_or_b32 s57, s57, s56
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX9-NEXT: v_lshl_or_b32 v7, s56, 16, v4
+; GFX9-NEXT: v_lshl_or_b32 v7, s57, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v4, s4
; GFX9-NEXT: v_mov_b32_e32 v6, s5
; GFX9-NEXT: s_cbranch_execnz .LBB111_3
@@ -43782,45 +43720,45 @@ define inreg <16 x bfloat> @bitcast_v32i8_to_v16bf16_scalar(<32 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_mov_b32 s42, 0
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB111_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
+; GFX11-TRUE16-NEXT: s_and_b32 s43, s11, 0xff
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_lshl_b32 s44, s7, 8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_or_b32 s44, s44, s43
; GFX11-TRUE16-NEXT: s_and_b32 s43, s28, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s44, s29, 8
; GFX11-TRUE16-NEXT: s_and_b32 s45, s12, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s9, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s43, s43, s44
-; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s18, s19, v4
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s43, s43, s44
-; GFX11-TRUE16-NEXT: s_and_b32 s44, s11, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s7, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s2, s3, v4
-; GFX11-TRUE16-NEXT: s_or_b32 s44, s44, s45
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s40, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s10, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v6.l
+; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s29, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s22, s23, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s46, s46, s43
+; GFX11-TRUE16-NEXT: s_lshl_b32 s43, s9, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s43, s43, s45
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v6.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s44
-; GFX11-TRUE16-NEXT: s_or_b32 s44, s45, s46
-; GFX11-TRUE16-NEXT: s_and_b32 s45, s8, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s4, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s44, s8, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s45, s40, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s47, s4, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s47, s47, s44
+; GFX11-TRUE16-NEXT: s_and_b32 s44, s14, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s56, s10, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s18, s19, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s56, s56, s45
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v4
+; GFX11-TRUE16-NEXT: s_lshl_b32 s45, s5, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v4
-; GFX11-TRUE16-NEXT: s_or_b32 s45, s45, s46
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s22, s23, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s26, s27, v4
-; GFX11-TRUE16-NEXT: s_and_b32 s47, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s46, s5, 8
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s45
-; GFX11-TRUE16-NEXT: s_or_b32 s45, s47, s46
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v4
+; GFX11-TRUE16-NEXT: s_or_b32 s45, s45, s44
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v4
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s44, s44, s45
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s43, s46, s43
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s44, s56, s45
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v5.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s41, s15, v4
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s13, s6, v4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, s47
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, s43
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s44
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
@@ -43911,52 +43849,53 @@ define inreg <16 x bfloat> @bitcast_v32i8_to_v16bf16_scalar(<32 x i8> inreg %a,
; GFX11-FAKE16-NEXT: s_mov_b32 s42, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB111_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s43, s28, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s44, s29, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s45, s5, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s43, s43, s44
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v4
-; GFX11-FAKE16-NEXT: s_and_b32 s44, s9, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v4
-; GFX11-FAKE16-NEXT: s_or_b32 s44, s44, s45
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_or_b32 s44, s44, s43
+; GFX11-FAKE16-NEXT: s_and_b32 s43, s9, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s45, s7, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s46, s5, 8
+; GFX11-FAKE16-NEXT: s_or_b32 s46, s46, s43
+; GFX11-FAKE16-NEXT: s_lshl_b32 s43, s4, 8
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s44, s44, s46
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v3, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_or_b32 s43, s43, s45
+; GFX11-FAKE16-NEXT: s_and_b32 s45, s40, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s47, s13, 8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s18, s19, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s43, s43, s44
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: s_and_b32 s46, s7, 0xff
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: s_lshl_b32 s47, s4, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s15, s8, v4
-; GFX11-FAKE16-NEXT: s_or_b32 s45, s46, s47
-; GFX11-FAKE16-NEXT: s_and_b32 s44, s40, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s41, s12, v4
-; GFX11-FAKE16-NEXT: s_lshl_b32 s46, s6, 8
-; GFX11-FAKE16-NEXT: s_and_b32 s47, s14, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s56, s10, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, s45, 16, v5
-; GFX11-FAKE16-NEXT: s_lshl_b32 s45, s13, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: s_or_b32 s44, s44, s45
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v5, 16, v2
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s15, s8, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s41, s12, v3
+; GFX11-FAKE16-NEXT: s_or_b32 s47, s47, s45
; GFX11-FAKE16-NEXT: s_and_b32 s45, s11, 0xff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: s_or_b32 s45, s45, s46
-; GFX11-FAKE16-NEXT: s_or_b32 s46, s47, s56
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s44, s44, s45
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v6, s44 :: v_dual_and_b32 v7, 0xffff, v7
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v8, 16, v7
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, s46, 16, v4
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, s43
+; GFX11-FAKE16-NEXT: s_and_b32 s56, s14, 0xff
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX11-FAKE16-NEXT: s_lshl_b32 s57, s6, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v7
+; GFX11-FAKE16-NEXT: s_or_b32 s57, s57, s45
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v3
+; GFX11-FAKE16-NEXT: s_lshl_b32 s45, s10, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, s43, 16, v5
+; GFX11-FAKE16-NEXT: s_or_b32 s45, s45, s56
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s43, s47, s57
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v8, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, s45, 16, v6
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, s44
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, s43
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB111_3
; GFX11-FAKE16-NEXT: .LBB111_2: ; %cmp.true
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
index aba9755a4f357..67097ce8e4956 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.320bit.ll
@@ -3766,76 +3766,66 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; GFX9-NEXT: s_lshr_b32 s75, s16, 16
; GFX9-NEXT: s_lshr_b32 s76, s16, 8
; GFX9-NEXT: .LBB13_3: ; %end
+; GFX9-NEXT: v_mov_b32_e32 v1, s76
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s12
-; GFX9-NEXT: v_mov_b32_e32 v1, s76
-; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s72
+; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s74
-; GFX9-NEXT: v_perm_b32 v3, s73, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
+; GFX9-NEXT: v_perm_b32 v3, s73, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s59
+; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s61
-; GFX9-NEXT: v_perm_b32 v3, s60, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s59
; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_perm_b32 v3, s60, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s58
-; GFX9-NEXT: v_perm_b32 v3, s57, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s46
+; GFX9-NEXT: v_perm_b32 v3, s57, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s56
-; GFX9-NEXT: v_perm_b32 v3, s47, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
+; GFX9-NEXT: v_perm_b32 v3, s47, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s45
-; GFX9-NEXT: v_perm_b32 v3, s44, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s41
+; GFX9-NEXT: v_perm_b32 v3, s44, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s43
-; GFX9-NEXT: v_perm_b32 v3, s42, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s41
; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s4
+; GFX9-NEXT: v_perm_b32 v3, s42, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s40
-; GFX9-NEXT: v_perm_b32 v3, s29, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s29, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s28
; GFX9-NEXT: v_mov_b32_e32 v3, s26
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s27, v3, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -3880,18 +3870,18 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB13_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s14, s21, 24
-; GFX11-NEXT: s_lshr_b32 s22, s21, 16
-; GFX11-NEXT: s_lshr_b32 s15, s21, 8
-; GFX11-NEXT: s_lshr_b32 s24, s20, 16
-; GFX11-NEXT: s_lshr_b32 s23, s20, 8
-; GFX11-NEXT: s_lshr_b32 s26, s19, 24
-; GFX11-NEXT: s_lshr_b32 s27, s19, 16
-; GFX11-NEXT: s_lshr_b32 s25, s19, 8
-; GFX11-NEXT: s_lshr_b32 s29, s18, 16
-; GFX11-NEXT: s_lshr_b32 s28, s18, 8
-; GFX11-NEXT: s_lshr_b32 s41, s17, 24
-; GFX11-NEXT: s_lshr_b32 s42, s17, 16
-; GFX11-NEXT: s_lshr_b32 s40, s17, 8
+; GFX11-NEXT: s_lshr_b32 s15, s21, 16
+; GFX11-NEXT: s_lshr_b32 s22, s21, 8
+; GFX11-NEXT: s_lshr_b32 s23, s20, 16
+; GFX11-NEXT: s_lshr_b32 s24, s20, 8
+; GFX11-NEXT: s_lshr_b32 s25, s19, 24
+; GFX11-NEXT: s_lshr_b32 s26, s19, 16
+; GFX11-NEXT: s_lshr_b32 s27, s19, 8
+; GFX11-NEXT: s_lshr_b32 s28, s18, 16
+; GFX11-NEXT: s_lshr_b32 s29, s18, 8
+; GFX11-NEXT: s_lshr_b32 s40, s17, 24
+; GFX11-NEXT: s_lshr_b32 s41, s17, 16
+; GFX11-NEXT: s_lshr_b32 s42, s17, 8
; GFX11-NEXT: s_lshr_b32 s43, s16, 16
; GFX11-NEXT: s_lshr_b32 s44, s16, 8
; GFX11-NEXT: s_lshr_b32 s45, s3, 24
@@ -3928,18 +3918,18 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; GFX11-NEXT: s_lshr_b64 s[10:11], s[2:3], 24
; GFX11-NEXT: s_lshr_b64 s[12:13], s[0:1], 24
; GFX11-NEXT: s_lshr_b32 s14, s21, 24
-; GFX11-NEXT: s_lshr_b32 s22, s21, 16
-; GFX11-NEXT: s_lshr_b32 s15, s21, 8
-; GFX11-NEXT: s_lshr_b32 s24, s20, 16
-; GFX11-NEXT: s_lshr_b32 s23, s20, 8
-; GFX11-NEXT: s_lshr_b32 s26, s19, 24
-; GFX11-NEXT: s_lshr_b32 s27, s19, 16
-; GFX11-NEXT: s_lshr_b32 s25, s19, 8
-; GFX11-NEXT: s_lshr_b32 s29, s18, 16
-; GFX11-NEXT: s_lshr_b32 s28, s18, 8
-; GFX11-NEXT: s_lshr_b32 s41, s17, 24
-; GFX11-NEXT: s_lshr_b32 s42, s17, 16
-; GFX11-NEXT: s_lshr_b32 s40, s17, 8
+; GFX11-NEXT: s_lshr_b32 s15, s21, 16
+; GFX11-NEXT: s_lshr_b32 s22, s21, 8
+; GFX11-NEXT: s_lshr_b32 s23, s20, 16
+; GFX11-NEXT: s_lshr_b32 s24, s20, 8
+; GFX11-NEXT: s_lshr_b32 s25, s19, 24
+; GFX11-NEXT: s_lshr_b32 s26, s19, 16
+; GFX11-NEXT: s_lshr_b32 s27, s19, 8
+; GFX11-NEXT: s_lshr_b32 s28, s18, 16
+; GFX11-NEXT: s_lshr_b32 s29, s18, 8
+; GFX11-NEXT: s_lshr_b32 s40, s17, 24
+; GFX11-NEXT: s_lshr_b32 s41, s17, 16
+; GFX11-NEXT: s_lshr_b32 s42, s17, 8
; GFX11-NEXT: s_lshr_b32 s43, s16, 16
; GFX11-NEXT: s_lshr_b32 s44, s16, 8
; GFX11-NEXT: s_lshr_b32 s45, s3, 24
@@ -3954,47 +3944,37 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; GFX11-NEXT: s_lshr_b32 s62, s0, 8
; GFX11-NEXT: .LBB13_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v6, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v2, s61, s12, v6
-; GFX11-NEXT: v_perm_b32 v4, s59, s58, v6
-; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
-; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s0, s62, v6
+; GFX11-NEXT: v_perm_b32 v2, s61, s12, v6
; GFX11-NEXT: v_perm_b32 v3, s1, s60, v6
+; GFX11-NEXT: v_perm_b32 v4, s59, s58, v6
; GFX11-NEXT: v_perm_b32 v5, s2, s57, v6
+; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
; GFX11-NEXT: v_perm_b32 v8, s3, s47, v6
+; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
; GFX11-NEXT: v_perm_b32 v10, s16, s44, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v12, s24, s4, v6
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v5, v7
-; GFX11-NEXT: v_perm_b32 v7, s42, s41, v6
-; GFX11-NEXT: v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v11
-; GFX11-NEXT: v_perm_b32 v8, s29, s6, v6
-; GFX11-NEXT: v_perm_b32 v11, s27, s26, v6
-; GFX11-NEXT: v_perm_b32 v14, s22, s14, v6
-; GFX11-NEXT: v_perm_b32 v9, s17, s40, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v10, s18, s28, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_perm_b32 v13, s19, s25, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v15, s20, s23, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT: v_perm_b32 v16, s21, s15, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v10, v8
-; GFX11-NEXT: v_or_b32_e32 v8, v13, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v12
-; GFX11-NEXT: v_or_b32_e32 v10, v16, v14
+; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v7, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-NEXT: v_perm_b32 v7, s17, s42, v6
+; GFX11-NEXT: v_perm_b32 v8, s41, s40, v6
+; GFX11-NEXT: v_perm_b32 v9, s18, s29, v6
+; GFX11-NEXT: v_perm_b32 v10, s28, s6, v6
+; GFX11-NEXT: v_perm_b32 v11, s19, s27, v6
+; GFX11-NEXT: v_perm_b32 v12, s26, s25, v6
+; GFX11-NEXT: v_perm_b32 v13, s20, s24, v6
+; GFX11-NEXT: v_perm_b32 v14, s23, s4, v6
+; GFX11-NEXT: v_perm_b32 v15, s21, s22, v6
+; GFX11-NEXT: v_perm_b32 v16, s15, s14, v6
+; GFX11-NEXT: v_lshl_or_b32 v6, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v11
+; GFX11-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v10, v16, 16, v15
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -4016,20 +3996,20 @@ define inreg <40 x i8> @bitcast_v10i32_to_v40i8_scalar(<10 x i32> inreg %a, i32
; GFX11-NEXT: ; implicit-def: $sgpr44
; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: ; implicit-def: $sgpr8
-; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: ; implicit-def: $sgpr42
; GFX11-NEXT: ; implicit-def: $sgpr41
-; GFX11-NEXT: ; implicit-def: $sgpr28
+; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: ; implicit-def: $sgpr29
+; GFX11-NEXT: ; implicit-def: $sgpr28
; GFX11-NEXT: ; implicit-def: $sgpr6
-; GFX11-NEXT: ; implicit-def: $sgpr25
; GFX11-NEXT: ; implicit-def: $sgpr27
; GFX11-NEXT: ; implicit-def: $sgpr26
-; GFX11-NEXT: ; implicit-def: $sgpr23
+; GFX11-NEXT: ; implicit-def: $sgpr25
; GFX11-NEXT: ; implicit-def: $sgpr24
+; GFX11-NEXT: ; implicit-def: $sgpr23
; GFX11-NEXT: ; implicit-def: $sgpr4
-; GFX11-NEXT: ; implicit-def: $sgpr15
; GFX11-NEXT: ; implicit-def: $sgpr22
+; GFX11-NEXT: ; implicit-def: $sgpr15
; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: s_branch .LBB13_2
%cmp = icmp eq i32 %b, 0
@@ -5755,67 +5735,57 @@ define inreg <10 x i32> @bitcast_v40i8_to_v10i32_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB15_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_mov_b32_e32 v4, s62
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s60
-; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_mov_b32_e32 v5, s58
; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s56
-; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_mov_b32_e32 v6, s46
; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s44
-; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_mov_b32_e32 v7, s42
; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s40
-; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v8, s14
; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s12
-; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_mov_b32_e32 v10, s10
; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; GFX9-NEXT: s_cbranch_execnz .LBB15_3
; GFX9-NEXT: .LBB15_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -5947,47 +5917,37 @@ define inreg <10 x i32> @bitcast_v40i8_to_v10i32_scalar(<40 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB15_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
-; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
+; GFX11-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-NEXT: v_perm_b32 v15, s5, s4, v5
+; GFX11-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v6, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v7, v11, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v8, v13, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v9, v15, 16, v14
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB15_3
; GFX11-NEXT: .LBB15_2: ; %cmp.true
@@ -10520,53 +10480,43 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
+; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v38, s4
; GFX9-NEXT: v_perm_b32 v10, v36, v37, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v33, s4
; GFX9-NEXT: v_perm_b32 v8, v31, v32, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v28, s4
; GFX9-NEXT: v_perm_b32 v6, v26, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v23, s4
; GFX9-NEXT: v_perm_b32 v4, v21, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v18, s4
; GFX9-NEXT: v_perm_b32 v2, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -10626,31 +10576,31 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX11-NEXT: v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-NEXT: v_lshrrev_b64 v[14:15], 24, v[7:8]
; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[9:10]
-; GFX11-NEXT: v_lshrrev_b32_e32 v19, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v16, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v20, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v24, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v27, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v17, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v18, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v20, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v22, 24, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v23, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v28, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v29, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 8, v8
; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v37, 24, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v38, 8, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 8, v9
; GFX11-NEXT: s_branch .LBB33_5
; GFX11-NEXT: .LBB33_3:
; GFX11-NEXT: ; implicit-def: $sgpr63
@@ -10690,63 +10640,53 @@ define inreg <40 x i8> @bitcast_v10f32_to_v40i8_scalar(<10 x float> inreg %a, i3
; GFX11-NEXT: v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v6, s17
; GFX11-NEXT: v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
; GFX11-NEXT: v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v2, s21
-; GFX11-NEXT: v_dual_mov_b32 v39, s63 :: v_dual_mov_b32 v48, s61
+; GFX11-NEXT: v_dual_mov_b32 v48, s63 :: v_dual_mov_b32 v39, s61
; GFX11-NEXT: v_dual_mov_b32 v38, s62 :: v_dual_mov_b32 v37, s59
; GFX11-NEXT: v_dual_mov_b32 v36, s60 :: v_dual_mov_b32 v35, s58
-; GFX11-NEXT: v_dual_mov_b32 v34, s56 :: v_dual_mov_b32 v33, s46
-; GFX11-NEXT: v_dual_mov_b32 v30, s57 :: v_dual_mov_b32 v29, s45
-; GFX11-NEXT: v_dual_mov_b32 v32, s47 :: v_dual_mov_b32 v31, s43
-; GFX11-NEXT: v_dual_mov_b32 v25, s44 :: v_dual_mov_b32 v28, s41
-; GFX11-NEXT: v_dual_mov_b32 v27, s42 :: v_dual_mov_b32 v24, s40
-; GFX11-NEXT: v_dual_mov_b32 v26, s28 :: v_dual_mov_b32 v23, s26
-; GFX11-NEXT: v_dual_mov_b32 v20, s29 :: v_dual_mov_b32 v17, s25
-; GFX11-NEXT: v_dual_mov_b32 v22, s27 :: v_dual_mov_b32 v21, s23
-; GFX11-NEXT: v_dual_mov_b32 v16, s24 :: v_dual_mov_b32 v19, s15
-; GFX11-NEXT: v_dual_mov_b32 v18, s22 :: v_dual_mov_b32 v15, s4
+; GFX11-NEXT: v_dual_mov_b32 v34, s56 :: v_dual_mov_b32 v33, s57
+; GFX11-NEXT: v_dual_mov_b32 v31, s47 :: v_dual_mov_b32 v32, s46
+; GFX11-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v29, s43
+; GFX11-NEXT: v_dual_mov_b32 v28, s44 :: v_dual_mov_b32 v27, s41
+; GFX11-NEXT: v_dual_mov_b32 v26, s42 :: v_dual_mov_b32 v25, s40
+; GFX11-NEXT: v_dual_mov_b32 v24, s28 :: v_dual_mov_b32 v23, s29
+; GFX11-NEXT: v_dual_mov_b32 v21, s27 :: v_dual_mov_b32 v22, s26
+; GFX11-NEXT: v_dual_mov_b32 v20, s25 :: v_dual_mov_b32 v19, s23
+; GFX11-NEXT: v_dual_mov_b32 v18, s24 :: v_dual_mov_b32 v17, s15
+; GFX11-NEXT: v_dual_mov_b32 v16, s22 :: v_dual_mov_b32 v15, s4
; GFX11-NEXT: v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v13, s8
; GFX11-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v11, s12
; GFX11-NEXT: .LBB33_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v15, v48, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v9, v39, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v30, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v13, v29, v13, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v9, v48, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v39, v15, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v36, v36, v37, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v35, v7, v35, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v14, v34, v14, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v15
-; GFX11-NEXT: v_perm_b32 v15, v32, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v36
-; GFX11-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v14
-; GFX11-NEXT: v_perm_b32 v14, v8, v30, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT: v_perm_b32 v5, v5, v29, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v8, v10, v31
-; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT: v_perm_b32 v14, v22, v23, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v13, v5, v13
-; GFX11-NEXT: v_perm_b32 v5, v26, v12, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v25, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v27
-; GFX11-NEXT: v_perm_b32 v3, v3, v24, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v20, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-NEXT: v_perm_b32 v1, v1, v17, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v2, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v15
-; GFX11-NEXT: v_or_b32_e32 v9, v35, v9
-; GFX11-NEXT: v_or_b32_e32 v14, v6, v12
-; GFX11-NEXT: v_or_b32_e32 v15, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v16, v4, v18
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v11
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
+; GFX11-NEXT: v_perm_b32 v33, v8, v33, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v31, v32, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v28, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v26, v27, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v25, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v24, v12, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v21, v21, v22, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v1, v1, v20, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v19, v11, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v2, v2, v18, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v17, v16, v17, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v7, v15, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v36, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v9, v14, 16, v35
+; GFX11-NEXT: v_lshl_or_b32 v10, v31, 16, v33
+; GFX11-NEXT: v_lshl_or_b32 v14, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v15, v12, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v16, v21, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v1, v11, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v17, 16, v2
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:16
@@ -12475,67 +12415,57 @@ define inreg <10 x float> @bitcast_v40i8_to_v10f32_scalar(<40 x i8> inreg %a, i3
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB35_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_mov_b32_e32 v4, s62
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s60
-; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_mov_b32_e32 v5, s58
; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s56
-; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_mov_b32_e32 v6, s46
; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s44
-; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_mov_b32_e32 v7, s42
; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s40
-; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v8, s14
; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s12
-; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_mov_b32_e32 v10, s10
; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; GFX9-NEXT: s_cbranch_execnz .LBB35_3
; GFX9-NEXT: .LBB35_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -12667,47 +12597,37 @@ define inreg <10 x float> @bitcast_v40i8_to_v10f32_scalar(<40 x i8> inreg %a, i3
; GFX11-NEXT: s_cbranch_scc0 .LBB35_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
+; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
-; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
-; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
-; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
-; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
-; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
+; GFX11-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-NEXT: v_perm_b32 v15, s5, s4, v5
+; GFX11-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v6, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v7, v11, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v8, v13, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v9, v15, 16, v14
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB35_3
; GFX11-NEXT: .LBB35_2: ; %cmp.true
@@ -16833,53 +16753,43 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
+; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v38, s4
; GFX9-NEXT: v_perm_b32 v10, v36, v37, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v33, s4
; GFX9-NEXT: v_perm_b32 v8, v31, v32, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v28, s4
; GFX9-NEXT: v_perm_b32 v6, v26, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v23, s4
; GFX9-NEXT: v_perm_b32 v4, v21, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v18, s4
; GFX9-NEXT: v_perm_b32 v2, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -16939,31 +16849,31 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX11-NEXT: v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-NEXT: v_lshrrev_b64 v[14:15], 24, v[7:8]
; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[9:10]
-; GFX11-NEXT: v_lshrrev_b32_e32 v19, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v16, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v20, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v24, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v27, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v17, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v18, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v20, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v22, 24, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v23, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v28, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v29, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 8, v8
; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v37, 24, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v38, 8, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 8, v9
; GFX11-NEXT: s_branch .LBB49_5
; GFX11-NEXT: .LBB49_3:
; GFX11-NEXT: ; implicit-def: $sgpr63
@@ -17003,63 +16913,54 @@ define inreg <40 x i8> @bitcast_v20i16_to_v40i8_scalar(<20 x i16> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v6, s17
; GFX11-NEXT: v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
; GFX11-NEXT: v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v2, s21
-; GFX11-NEXT: v_dual_mov_b32 v39, s63 :: v_dual_mov_b32 v48, s61
+; GFX11-NEXT: v_dual_mov_b32 v48, s63 :: v_dual_mov_b32 v39, s61
; GFX11-NEXT: v_dual_mov_b32 v38, s62 :: v_dual_mov_b32 v37, s59
; GFX11-NEXT: v_dual_mov_b32 v36, s60 :: v_dual_mov_b32 v35, s58
-; GFX11-NEXT: v_dual_mov_b32 v34, s56 :: v_dual_mov_b32 v33, s46
-; GFX11-NEXT: v_dual_mov_b32 v30, s57 :: v_dual_mov_b32 v29, s45
-; GFX11-NEXT: v_dual_mov_b32 v32, s47 :: v_dual_mov_b32 v31, s43
-; GFX11-NEXT: v_dual_mov_b32 v25, s44 :: v_dual_mov_b32 v28, s41
-; GFX11-NEXT: v_dual_mov_b32 v27, s42 :: v_dual_mov_b32 v24, s40
-; GFX11-NEXT: v_dual_mov_b32 v26, s28 :: v_dual_mov_b32 v23, s26
-; GFX11-NEXT: v_dual_mov_b32 v20, s29 :: v_dual_mov_b32 v17, s25
-; GFX11-NEXT: v_dual_mov_b32 v22, s27 :: v_dual_mov_b32 v21, s23
-; GFX11-NEXT: v_dual_mov_b32 v16, s24 :: v_dual_mov_b32 v19, s15
-; GFX11-NEXT: v_dual_mov_b32 v18, s22 :: v_dual_mov_b32 v11, s12
+; GFX11-NEXT: v_dual_mov_b32 v34, s56 :: v_dual_mov_b32 v33, s57
+; GFX11-NEXT: v_dual_mov_b32 v31, s47 :: v_dual_mov_b32 v32, s46
+; GFX11-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v29, s43
+; GFX11-NEXT: v_dual_mov_b32 v28, s44 :: v_dual_mov_b32 v27, s41
+; GFX11-NEXT: v_dual_mov_b32 v26, s42 :: v_dual_mov_b32 v25, s40
+; GFX11-NEXT: v_dual_mov_b32 v24, s28 :: v_dual_mov_b32 v23, s29
+; GFX11-NEXT: v_dual_mov_b32 v21, s27 :: v_dual_mov_b32 v22, s26
+; GFX11-NEXT: v_dual_mov_b32 v20, s25 :: v_dual_mov_b32 v19, s23
+; GFX11-NEXT: v_dual_mov_b32 v18, s24 :: v_dual_mov_b32 v17, s15
+; GFX11-NEXT: v_dual_mov_b32 v16, s22 :: v_dual_mov_b32 v11, s12
; GFX11-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s8
; GFX11-NEXT: v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v15, s4
; GFX11-NEXT: .LBB49_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v15, v48, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v9, v39, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v30, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v13, v29, v13, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v9, v48, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v15, v39, v15, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v36, v36, v37, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v35, v7, v35, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v14, v34, v14, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v15
-; GFX11-NEXT: v_perm_b32 v15, v32, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v36
-; GFX11-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v14
-; GFX11-NEXT: v_perm_b32 v14, v8, v30, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT: v_perm_b32 v5, v5, v29, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v8, v10, v31
-; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT: v_perm_b32 v14, v22, v23, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v13, v5, v13
-; GFX11-NEXT: v_perm_b32 v5, v26, v12, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v25, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v27
-; GFX11-NEXT: v_perm_b32 v3, v3, v24, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v20, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-NEXT: v_perm_b32 v1, v1, v17, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v2, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v15
-; GFX11-NEXT: v_or_b32_e32 v9, v35, v9
-; GFX11-NEXT: v_or_b32_e32 v14, v6, v12
-; GFX11-NEXT: v_or_b32_e32 v15, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v16, v4, v18
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v11
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
+; GFX11-NEXT: v_perm_b32 v33, v8, v33, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v31, v32, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v28, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v26, v27, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v25, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v24, v12, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v21, v21, v22, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v1, v1, v20, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v19, v11, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v2, v2, v18, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v17, v16, v17, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v7, v15, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v36, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v9, v14, 16, v35
+; GFX11-NEXT: v_lshl_or_b32 v10, v31, 16, v33
+; GFX11-NEXT: v_lshl_or_b32 v14, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v15, v12, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v16, v21, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v1, v11, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v17, 16, v2
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:16
@@ -19057,31 +18958,31 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s9
+; GFX9-NEXT: s_and_b32 s4, s61, 0xff
; GFX9-NEXT: v_perm_b32 v6, s10, v6, v8
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: s_lshl_b32 s5, s60, 8
; GFX9-NEXT: v_perm_b32 v7, s8, v7, v8
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s56
+; GFX9-NEXT: s_and_b32 s4, s47, 0xff
; GFX9-NEXT: v_perm_b32 v7, s58, v7, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s7
-; GFX9-NEXT: s_and_b32 s4, s61, 0xff
-; GFX9-NEXT: s_lshl_b32 s5, s60, 8
+; GFX9-NEXT: s_lshl_b32 s72, s46, 8
; GFX9-NEXT: v_perm_b32 v9, s45, v9, v8
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s47, 0xff
-; GFX9-NEXT: s_lshl_b32 s72, s46, 8
+; GFX9-NEXT: s_or_b32 s72, s72, s4
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
-; GFX9-NEXT: s_or_b32 s5, s5, s72
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s72
; GFX9-NEXT: v_mov_b32_e32 v9, s62
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: v_perm_b32 v8, s63, v9, v8
; GFX9-NEXT: s_and_b32 s5, s59, 0xff
+; GFX9-NEXT: v_perm_b32 v8, s63, v9, v8
; GFX9-NEXT: s_lshl_b32 s72, s57, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s72
+; GFX9-NEXT: s_or_b32 s72, s72, s5
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX9-NEXT: v_lshl_or_b32 v9, s5, 16, v8
+; GFX9-NEXT: v_lshl_or_b32 v9, s72, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
@@ -19223,43 +19124,43 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB51_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_and_b32 s59, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s60, s8, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s59, s6, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s60, s43, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s61, s4, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s59, s59, s60
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_or_b32 s61, s61, s59
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s42, s13, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s45, s14, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s60, s6, 0xff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s42, s13, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s10, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s60, s60, s61
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s9, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s62, s11, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s61, s7, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s59, s11, 0xff
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s60
+; GFX11-TRUE16-NEXT: s_lshl_b32 s62, s8, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s57, s56, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s60, s62, s61
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s10, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s62, s62, s60
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s9, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s60, s7, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s60, s60, s59
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s47, s44, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s41, v8
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s59, s59, s60
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s59, s62, s60
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s15, s5, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, s61
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s59
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB51_3
@@ -19371,53 +19272,57 @@ define inreg <20 x i16> @bitcast_v40i8_to_v20i16_scalar(<40 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: s_mov_b32 s58, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB51_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s59, s56, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s60, s42, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s61, s15, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s59, s59, s60
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_or_b32 s60, s60, s59
+; GFX11-FAKE16-NEXT: s_and_b32 s59, s45, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s61, s46, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s62, s15, 8
+; GFX11-FAKE16-NEXT: s_or_b32 s62, s62, s59
+; GFX11-FAKE16-NEXT: s_lshl_b32 s59, s13, 8
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s60, s60, s62
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_or_b32 s59, s59, s61
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s6, s4, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s60, s45, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: s_or_b32 s60, s60, s61
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s41, s9, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s8, s5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s47, s44, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s11, s7, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s14, s10, v8
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s59, s59, s60
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s40, s12, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s57, s43, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_and_b32 s62, s46, 0xff
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s41, s9, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v10, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s40, s12, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s8, s5, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s47, s44, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s11, s7, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s10, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s57, s43, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s63, s13, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
-; GFX11-FAKE16-NEXT: s_or_b32 s61, s62, s63
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s61, 16, v8
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s59
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v10, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s60
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s59, 16, v12
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-FAKE16-NEXT: .LBB51_2: ; %cmp.true
@@ -23175,53 +23080,43 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v48, v15, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
+; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v38, s4
; GFX9-NEXT: v_perm_b32 v10, v36, v37, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v34, v14, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v33, s4
; GFX9-NEXT: v_perm_b32 v8, v31, v32, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v30, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v29, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v5, v6, v28, s4
; GFX9-NEXT: v_perm_b32 v6, v26, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
; GFX9-NEXT: v_perm_b32 v3, v3, v25, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_perm_b32 v5, v24, v12, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v23, s4
; GFX9-NEXT: v_perm_b32 v4, v21, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, v19, v11, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v18, s4
; GFX9-NEXT: v_perm_b32 v2, v16, v17, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -23281,31 +23176,31 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX11-NEXT: v_lshrrev_b64 v[13:14], 24, v[5:6]
; GFX11-NEXT: v_lshrrev_b64 v[14:15], 24, v[7:8]
; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[9:10]
-; GFX11-NEXT: v_lshrrev_b32_e32 v19, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v16, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v20, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v24, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v27, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v17, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v16, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v18, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v20, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v22, 24, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v23, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v27, 24, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v28, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v29, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 8, v8
; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v37, 24, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v10
; GFX11-NEXT: v_lshrrev_b32_e32 v38, 8, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 8, v9
; GFX11-NEXT: s_branch .LBB61_5
; GFX11-NEXT: .LBB61_3:
; GFX11-NEXT: ; implicit-def: $sgpr63
@@ -23345,63 +23240,54 @@ define inreg <40 x i8> @bitcast_v20f16_to_v40i8_scalar(<20 x half> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v6, s17
; GFX11-NEXT: v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
; GFX11-NEXT: v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v2, s21
-; GFX11-NEXT: v_dual_mov_b32 v39, s63 :: v_dual_mov_b32 v48, s61
+; GFX11-NEXT: v_dual_mov_b32 v48, s63 :: v_dual_mov_b32 v39, s61
; GFX11-NEXT: v_dual_mov_b32 v38, s62 :: v_dual_mov_b32 v37, s59
; GFX11-NEXT: v_dual_mov_b32 v36, s60 :: v_dual_mov_b32 v35, s58
-; GFX11-NEXT: v_dual_mov_b32 v34, s56 :: v_dual_mov_b32 v33, s46
-; GFX11-NEXT: v_dual_mov_b32 v30, s57 :: v_dual_mov_b32 v29, s45
-; GFX11-NEXT: v_dual_mov_b32 v32, s47 :: v_dual_mov_b32 v31, s43
-; GFX11-NEXT: v_dual_mov_b32 v25, s44 :: v_dual_mov_b32 v28, s41
-; GFX11-NEXT: v_dual_mov_b32 v27, s42 :: v_dual_mov_b32 v24, s40
-; GFX11-NEXT: v_dual_mov_b32 v26, s28 :: v_dual_mov_b32 v23, s26
-; GFX11-NEXT: v_dual_mov_b32 v20, s29 :: v_dual_mov_b32 v17, s25
-; GFX11-NEXT: v_dual_mov_b32 v22, s27 :: v_dual_mov_b32 v21, s23
-; GFX11-NEXT: v_dual_mov_b32 v16, s24 :: v_dual_mov_b32 v19, s15
-; GFX11-NEXT: v_dual_mov_b32 v18, s22 :: v_dual_mov_b32 v11, s12
+; GFX11-NEXT: v_dual_mov_b32 v34, s56 :: v_dual_mov_b32 v33, s57
+; GFX11-NEXT: v_dual_mov_b32 v31, s47 :: v_dual_mov_b32 v32, s46
+; GFX11-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v29, s43
+; GFX11-NEXT: v_dual_mov_b32 v28, s44 :: v_dual_mov_b32 v27, s41
+; GFX11-NEXT: v_dual_mov_b32 v26, s42 :: v_dual_mov_b32 v25, s40
+; GFX11-NEXT: v_dual_mov_b32 v24, s28 :: v_dual_mov_b32 v23, s29
+; GFX11-NEXT: v_dual_mov_b32 v21, s27 :: v_dual_mov_b32 v22, s26
+; GFX11-NEXT: v_dual_mov_b32 v20, s25 :: v_dual_mov_b32 v19, s23
+; GFX11-NEXT: v_dual_mov_b32 v18, s24 :: v_dual_mov_b32 v17, s15
+; GFX11-NEXT: v_dual_mov_b32 v16, s22 :: v_dual_mov_b32 v11, s12
; GFX11-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s8
; GFX11-NEXT: v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v15, s4
; GFX11-NEXT: .LBB61_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v15, v48, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v9, v39, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v30, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v13, v29, v13, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v9, v48, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v15, v39, v15, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v36, v36, v37, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v35, v7, v35, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v14, v34, v14, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v15
-; GFX11-NEXT: v_perm_b32 v15, v32, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v31, v13, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v10, v38, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v31, 16, v36
-; GFX11-NEXT: v_or_b32_e32 v7, v9, v7
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v14
-; GFX11-NEXT: v_perm_b32 v14, v8, v30, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT: v_perm_b32 v5, v5, v29, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v8, v10, v31
-; GFX11-NEXT: v_perm_b32 v27, v27, v28, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v10, v14, v15
-; GFX11-NEXT: v_perm_b32 v14, v22, v23, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v13, v5, v13
-; GFX11-NEXT: v_perm_b32 v5, v26, v12, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v18, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v25, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v27
-; GFX11-NEXT: v_perm_b32 v3, v3, v24, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v20, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-NEXT: v_perm_b32 v1, v1, v17, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v2, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v15
-; GFX11-NEXT: v_or_b32_e32 v9, v35, v9
-; GFX11-NEXT: v_or_b32_e32 v14, v6, v12
-; GFX11-NEXT: v_or_b32_e32 v15, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v16, v4, v18
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v11
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v17
+; GFX11-NEXT: v_perm_b32 v33, v8, v33, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v31, v31, v32, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v13, v13, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v28, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v26, v27, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v3, v3, v25, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v24, v12, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v21, v21, v22, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v1, v1, v20, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v19, v11, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v2, v2, v18, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v17, v16, v17, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v7, v15, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v36, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v9, v14, 16, v35
+; GFX11-NEXT: v_lshl_or_b32 v10, v31, 16, v33
+; GFX11-NEXT: v_lshl_or_b32 v14, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v15, v12, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v16, v21, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v1, v11, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v17, 16, v2
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off
; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off offset:16
@@ -25399,31 +25285,31 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_and_b32_e32 v5, 0xffff, v5
; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s9
+; GFX9-NEXT: s_and_b32 s4, s61, 0xff
; GFX9-NEXT: v_perm_b32 v6, s10, v6, v8
; GFX9-NEXT: v_mov_b32_e32 v7, s6
+; GFX9-NEXT: s_lshl_b32 s5, s60, 8
; GFX9-NEXT: v_perm_b32 v7, s8, v7, v8
; GFX9-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s56
+; GFX9-NEXT: s_and_b32 s4, s47, 0xff
; GFX9-NEXT: v_perm_b32 v7, s58, v7, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s7
-; GFX9-NEXT: s_and_b32 s4, s61, 0xff
-; GFX9-NEXT: s_lshl_b32 s5, s60, 8
+; GFX9-NEXT: s_lshl_b32 s72, s46, 8
; GFX9-NEXT: v_perm_b32 v9, s45, v9, v8
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s47, 0xff
-; GFX9-NEXT: s_lshl_b32 s72, s46, 8
+; GFX9-NEXT: s_or_b32 s72, s72, s4
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
-; GFX9-NEXT: s_or_b32 s5, s5, s72
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s72
; GFX9-NEXT: v_mov_b32_e32 v9, s62
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
-; GFX9-NEXT: v_perm_b32 v8, s63, v9, v8
; GFX9-NEXT: s_and_b32 s5, s59, 0xff
+; GFX9-NEXT: v_perm_b32 v8, s63, v9, v8
; GFX9-NEXT: s_lshl_b32 s72, s57, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s72
+; GFX9-NEXT: s_or_b32 s72, s72, s5
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX9-NEXT: v_lshl_or_b32 v9, s5, 16, v8
+; GFX9-NEXT: v_lshl_or_b32 v9, s72, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: s_cbranch_execnz .LBB63_3
; GFX9-NEXT: .LBB63_2: ; %cmp.true
@@ -25565,43 +25451,43 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB63_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_and_b32 s59, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s60, s8, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s59, s6, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s60, s43, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s61, s4, 8
-; GFX11-TRUE16-NEXT: s_or_b32 s59, s59, s60
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: s_or_b32 s61, s61, s59
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s42, s13, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s45, s14, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s60, s6, 0xff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s42, s13, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s10, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s60, s60, s61
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s9, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s62, s11, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s61, s7, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s59, s11, 0xff
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s60
+; GFX11-TRUE16-NEXT: s_lshl_b32 s62, s8, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s57, s56, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s60, s62, s61
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s40, s10, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s62, s62, s60
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s9, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s60, s7, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s60, s60, s59
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s47, s44, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s46, s41, v8
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s59, s59, s60
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s59, s62, s60
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s15, s5, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, s61
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s59
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB63_3
@@ -25713,53 +25599,57 @@ define inreg <20 x half> @bitcast_v40i8_to_v20f16_scalar(<40 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: s_mov_b32 s58, 0
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB63_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s59, s56, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s60, s42, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s61, s15, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s59, s59, s60
-; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v8
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_or_b32 s60, s60, s59
+; GFX11-FAKE16-NEXT: s_and_b32 s59, s45, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s61, s46, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s62, s15, 8
+; GFX11-FAKE16-NEXT: s_or_b32 s62, s62, s59
+; GFX11-FAKE16-NEXT: s_lshl_b32 s59, s13, 8
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s60, s60, s62
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_or_b32 s59, s59, s61
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s22, s23, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s6, s4, v5
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s60, s45, 0xff
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: s_or_b32 s60, s60, s61
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s41, s9, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s8, s5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s47, s44, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s11, s7, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s14, s10, v8
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s59, s59, s60
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s40, s12, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s57, s43, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: s_and_b32 s62, s46, 0xff
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s41, s9, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v8, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v10, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s40, s12, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s8, s5, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s47, s44, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s11, s7, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s14, s10, v5
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s57, s43, v5
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s63, s13, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
-; GFX11-FAKE16-NEXT: s_or_b32 s61, s62, s63
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s61, 16, v8
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s59
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v8, 16, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v10, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v11, 16, v9
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s60
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s59, 16, v12
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB63_3
; GFX11-FAKE16-NEXT: .LBB63_2: ; %cmp.true
@@ -29675,67 +29565,57 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB73_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_mov_b32_e32 v4, s62
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s60
-; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_mov_b32_e32 v5, s58
; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s56
-; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_mov_b32_e32 v6, s46
; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s44
-; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_mov_b32_e32 v7, s42
; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s40
-; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v8, s14
; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s12
-; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_mov_b32_e32 v10, s10
; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; GFX9-NEXT: s_cbranch_execnz .LBB73_3
; GFX9-NEXT: .LBB73_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -29867,47 +29747,37 @@ define inreg <5 x double> @bitcast_v40i8_to_v5f64_scalar(<40 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB73_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
-; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
+; GFX11-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-NEXT: v_perm_b32 v15, s5, s4, v5
+; GFX11-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v6, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v7, v11, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v8, v13, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v9, v15, 16, v14
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB73_3
; GFX11-NEXT: .LBB73_2: ; %cmp.true
@@ -31399,20 +31269,20 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 24, v6
-; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v6
-; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v6
+; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v6
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v5
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 8, v5
-; GFX9-NEXT: v_lshrrev_b32_e32 v34, 24, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v35, 24, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v37, 8, v8
-; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v7
-; GFX9-NEXT: v_lshrrev_b32_e32 v32, 8, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v7
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v10
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 8, v9
; GFX9-NEXT: s_branch .LBB75_5
; GFX9-NEXT: .LBB75_3:
; GFX9-NEXT: ; implicit-def: $sgpr75
@@ -31458,9 +31328,9 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v8, s19
; GFX9-NEXT: v_mov_b32_e32 v10, s17
; GFX9-NEXT: v_mov_b32_e32 v33, s76
-; GFX9-NEXT: v_mov_b32_e32 v35, s75
-; GFX9-NEXT: v_mov_b32_e32 v30, s74
-; GFX9-NEXT: v_mov_b32_e32 v32, s73
+; GFX9-NEXT: v_mov_b32_e32 v34, s75
+; GFX9-NEXT: v_mov_b32_e32 v29, s74
+; GFX9-NEXT: v_mov_b32_e32 v31, s73
; GFX9-NEXT: v_mov_b32_e32 v26, s72
; GFX9-NEXT: v_mov_b32_e32 v27, s63
; GFX9-NEXT: v_mov_b32_e32 v21, s62
@@ -31474,9 +31344,9 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v24, s46
; GFX9-NEXT: v_mov_b32_e32 v25, s45
; GFX9-NEXT: v_mov_b32_e32 v28, s44
-; GFX9-NEXT: v_mov_b32_e32 v29, s43
-; GFX9-NEXT: v_mov_b32_e32 v31, s42
-; GFX9-NEXT: v_mov_b32_e32 v34, s41
+; GFX9-NEXT: v_mov_b32_e32 v30, s43
+; GFX9-NEXT: v_mov_b32_e32 v32, s42
+; GFX9-NEXT: v_mov_b32_e32 v35, s41
; GFX9-NEXT: v_mov_b32_e32 v36, s40
; GFX9-NEXT: v_mov_b32_e32 v37, s29
; GFX9-NEXT: v_mov_b32_e32 v38, s28
@@ -31490,54 +31360,44 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; GFX9-NEXT: .LBB75_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_perm_b32 v15, v33, v15, s4
-; GFX9-NEXT: v_perm_b32 v9, v9, v35, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v15
+; GFX9-NEXT: v_perm_b32 v9, v9, v34, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v15, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen
; GFX9-NEXT: v_perm_b32 v9, v10, v48, s4
; GFX9-NEXT: v_perm_b32 v10, v39, v38, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v9, v30, v14, s4
-; GFX9-NEXT: v_perm_b32 v7, v7, v32, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v7, v7, v31, s4
+; GFX9-NEXT: v_perm_b32 v9, v29, v14, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v7, v8, v37, s4
-; GFX9-NEXT: v_perm_b32 v8, v36, v34, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, v36, v35, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v7, v26, v13, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v26, v13, s4
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: v_perm_b32 v5, v6, v31, s4
-; GFX9-NEXT: v_perm_b32 v6, v29, v28, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v5, v6, v32, s4
+; GFX9-NEXT: v_perm_b32 v6, v30, v28, s4
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v5, v21, v12, s4
; GFX9-NEXT: v_perm_b32 v3, v3, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_perm_b32 v5, v21, v12, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v3, v4, v25, s4
; GFX9-NEXT: v_perm_b32 v4, v24, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v3, v17, v11, s4
; GFX9-NEXT: v_perm_b32 v1, v1, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, v17, v11, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v1, v2, v20, s4
; GFX9-NEXT: v_perm_b32 v2, v18, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -31582,41 +31442,41 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s14
; GFX11-NEXT: s_cbranch_vccnz .LBB75_4
; GFX11-NEXT: .LBB75_2: ; %cmp.true
+; GFX11-NEXT: v_add_f64 v[3:4], s[18:19], 1.0
; GFX11-NEXT: v_add_f64 v[5:6], s[16:17], 1.0
-; GFX11-NEXT: v_add_f64 v[1:2], s[20:21], 1.0
; GFX11-NEXT: v_add_f64 v[7:8], s[2:3], 1.0
-; GFX11-NEXT: v_add_f64 v[3:4], s[18:19], 1.0
-; GFX11-NEXT: v_add_f64 v[12:13], s[0:1], 1.0
+; GFX11-NEXT: v_add_f64 v[1:2], s[20:21], 1.0
+; GFX11-NEXT: v_add_f64 v[11:12], s[0:1], 1.0
+; GFX11-NEXT: v_lshrrev_b64 v[13:14], 24, v[3:4]
; GFX11-NEXT: v_lshrrev_b64 v[14:15], 24, v[5:6]
-; GFX11-NEXT: v_lshrrev_b64 v[9:10], 24, v[1:2]
; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[7:8]
-; GFX11-NEXT: v_lshrrev_b64 v[10:11], 24, v[3:4]
-; GFX11-NEXT: v_lshrrev_b64 v[16:17], 24, v[12:13]
-; GFX11-NEXT: v_lshrrev_b32_e32 v18, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v20, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v17, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v19, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v11, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v24, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v25, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v21, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v23, 16, v3
+; GFX11-NEXT: v_lshrrev_b64 v[9:10], 24, v[1:2]
+; GFX11-NEXT: v_lshrrev_b64 v[16:17], 24, v[11:12]
+; GFX11-NEXT: v_lshrrev_b32_e32 v17, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v18, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v20, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v10, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v19, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v23, 24, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v24, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v25, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v21, 16, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v22, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v29, 24, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v27, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v28, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v36, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v29, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v26, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v27, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v35, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v37, 8, v8
; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v32, 8, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v38, 24, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v48, 8, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v38, 24, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 8, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v11
; GFX11-NEXT: s_branch .LBB75_5
; GFX11-NEXT: .LBB75_3:
; GFX11-NEXT: ; implicit-def: $sgpr62
@@ -31651,70 +31511,61 @@ define inreg <40 x i8> @bitcast_v5f64_to_v40i8_scalar(<5 x double> inreg %a, i32
; GFX11-NEXT: ; implicit-def: $sgpr45
; GFX11-NEXT: s_branch .LBB75_2
; GFX11-NEXT: .LBB75_4:
-; GFX11-NEXT: v_dual_mov_b32 v12, s0 :: v_dual_mov_b32 v7, s2
-; GFX11-NEXT: v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v2, s21
-; GFX11-NEXT: v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v4, s19
-; GFX11-NEXT: v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v6, s17
-; GFX11-NEXT: v_dual_mov_b32 v8, s3 :: v_dual_mov_b32 v13, s1
-; GFX11-NEXT: v_dual_mov_b32 v34, s63 :: v_dual_mov_b32 v35, s62
+; GFX11-NEXT: v_dual_mov_b32 v11, s0 :: v_dual_mov_b32 v2, s21
+; GFX11-NEXT: v_dual_mov_b32 v7, s2 :: v_dual_mov_b32 v4, s19
+; GFX11-NEXT: v_dual_mov_b32 v5, s16 :: v_dual_mov_b32 v6, s17
+; GFX11-NEXT: v_dual_mov_b32 v3, s18 :: v_dual_mov_b32 v8, s3
+; GFX11-NEXT: v_dual_mov_b32 v1, s20 :: v_dual_mov_b32 v12, s1
+; GFX11-NEXT: v_dual_mov_b32 v33, s63 :: v_dual_mov_b32 v34, s62
; GFX11-NEXT: v_dual_mov_b32 v31, s61 :: v_dual_mov_b32 v32, s60
-; GFX11-NEXT: v_dual_mov_b32 v28, s59 :: v_dual_mov_b32 v23, s57
-; GFX11-NEXT: v_dual_mov_b32 v26, s58 :: v_dual_mov_b32 v19, s47
-; GFX11-NEXT: v_dual_mov_b32 v22, s56 :: v_dual_mov_b32 v11, s46
+; GFX11-NEXT: v_dual_mov_b32 v26, s59 :: v_dual_mov_b32 v27, s58
+; GFX11-NEXT: v_dual_mov_b32 v21, s57 :: v_dual_mov_b32 v22, s56
+; GFX11-NEXT: v_dual_mov_b32 v10, s47 :: v_dual_mov_b32 v19, s46
; GFX11-NEXT: v_dual_mov_b32 v16, s4 :: v_dual_mov_b32 v15, s6
-; GFX11-NEXT: v_dual_mov_b32 v14, s8 :: v_dual_mov_b32 v9, s12
-; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v17, s43
-; GFX11-NEXT: v_dual_mov_b32 v18, s45 :: v_dual_mov_b32 v25, s41
-; GFX11-NEXT: v_dual_mov_b32 v20, s44 :: v_dual_mov_b32 v21, s40
-; GFX11-NEXT: v_dual_mov_b32 v24, s42 :: v_dual_mov_b32 v29, s29
-; GFX11-NEXT: v_dual_mov_b32 v30, s28 :: v_dual_mov_b32 v27, s27
-; GFX11-NEXT: v_dual_mov_b32 v36, s26 :: v_dual_mov_b32 v37, s25
-; GFX11-NEXT: v_dual_mov_b32 v33, s24 :: v_dual_mov_b32 v38, s23
+; GFX11-NEXT: v_dual_mov_b32 v14, s8 :: v_dual_mov_b32 v13, s10
+; GFX11-NEXT: v_dual_mov_b32 v9, s12 :: v_dual_mov_b32 v18, s44
+; GFX11-NEXT: v_dual_mov_b32 v17, s45 :: v_dual_mov_b32 v20, s43
+; GFX11-NEXT: v_dual_mov_b32 v23, s42 :: v_dual_mov_b32 v24, s41
+; GFX11-NEXT: v_dual_mov_b32 v25, s40 :: v_dual_mov_b32 v28, s29
+; GFX11-NEXT: v_dual_mov_b32 v29, s28 :: v_dual_mov_b32 v30, s27
+; GFX11-NEXT: v_dual_mov_b32 v35, s26 :: v_dual_mov_b32 v36, s25
+; GFX11-NEXT: v_dual_mov_b32 v37, s24 :: v_dual_mov_b32 v38, s23
; GFX11-NEXT: v_dual_mov_b32 v39, s22 :: v_dual_mov_b32 v48, s15
; GFX11-NEXT: .LBB75_5: ; %end
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v16, v34, v16, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v12, v12, v35, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v31, v37, v36, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v11, v11, v34, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v33, v16, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-NEXT: v_perm_b32 v12, v12, v48, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v33, v39, v38, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v7, v7, v32, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-NEXT: v_perm_b32 v14, v28, v14, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT: v_perm_b32 v8, v8, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v34, v39, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v16
-; GFX11-NEXT: v_lshlrev_b32_e32 v16, 16, v31
-; GFX11-NEXT: v_perm_b32 v5, v5, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v14
-; GFX11-NEXT: v_or_b32_e32 v14, v7, v15
-; GFX11-NEXT: v_perm_b32 v7, v30, v29, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v15, v8, v16
-; GFX11-NEXT: v_perm_b32 v8, v23, v10, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v25, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v19, v9, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v16, v20, v18, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v48, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v28, 16, v34
-; GFX11-NEXT: v_perm_b32 v6, v6, v27, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-NEXT: v_perm_b32 v15, v31, v15, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v8, v8, v37, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v34, v36, v35, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v27, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v14, v26, v14, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v31, v16, 16, v11
+; GFX11-NEXT: v_lshl_or_b32 v32, v33, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v33, v15, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v34, v34, 16, v8
+; GFX11-NEXT: v_perm_b32 v6, v6, v30, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v29, v28, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v3, v3, v22, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_perm_b32 v4, v4, v21, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v1, v1, v11, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v2, v2, v17, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v16
-; GFX11-NEXT: v_or_b32_e32 v13, v13, v28
-; GFX11-NEXT: v_or_b32_e32 v5, v5, v26
-; GFX11-NEXT: v_or_b32_e32 v6, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v3, v8
-; GFX11-NEXT: v_or_b32_e32 v8, v4, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v9
-; GFX11-NEXT: v_or_b32_e32 v2, v2, v11
+; GFX11-NEXT: v_perm_b32 v8, v21, v13, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v25, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v24, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v1, v1, v19, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v9, v10, v9, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v2, v2, v20, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v10, v18, v17, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v5, v14, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v8, v11, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v1, v9, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v10, 16, v2
; GFX11-NEXT: s_clause 0x2
-; GFX11-NEXT: scratch_store_b128 v0, v[12:15], off
+; GFX11-NEXT: scratch_store_b128 v0, v[31:34], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
; GFX11-NEXT: scratch_store_b64 v0, v[1:2], off offset:32
; GFX11-NEXT: s_setpc_b64 s[30:31]
@@ -33522,67 +33373,57 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; GFX9-NEXT: v_readfirstlane_b32 s63, v0
; GFX9-NEXT: s_cbranch_scc0 .LBB77_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v9, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v2, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v9
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_mov_b32_e32 v2, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, s22, v2, v9
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s62
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v9
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_mov_b32_e32 v4, s62
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s58
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s63, v4, v9
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s60
-; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_mov_b32_e32 v5, s58
; GFX9-NEXT: v_perm_b32 v4, s61, v4, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s46
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s59, v5, v9
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s56
-; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_mov_b32_e32 v6, s46
; GFX9-NEXT: v_perm_b32 v5, s57, v5, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s42
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s47, v6, v9
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s44
-; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_mov_b32_e32 v7, s42
; GFX9-NEXT: v_perm_b32 v6, s45, v6, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s14
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s43, v7, v9
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s40
-; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_mov_b32_e32 v8, s14
; GFX9-NEXT: v_perm_b32 v7, s41, v7, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v10, s10
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s15, v8, v9
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s12
-; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_mov_b32_e32 v10, s10
; GFX9-NEXT: v_perm_b32 v8, s13, v8, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v10
+; GFX9-NEXT: v_perm_b32 v10, s11, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v8, v10, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v10, s8
; GFX9-NEXT: v_mov_b32_e32 v11, s6
; GFX9-NEXT: v_perm_b32 v10, s9, v10, v9
; GFX9-NEXT: v_perm_b32 v9, s7, v11, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v9, v10, v9
+; GFX9-NEXT: v_lshl_or_b32 v9, v9, 16, v10
; GFX9-NEXT: s_cbranch_execnz .LBB77_3
; GFX9-NEXT: .LBB77_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -33714,47 +33555,37 @@ define inreg <5 x i64> @bitcast_v40i8_to_v5i64_scalar(<40 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB77_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v5, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
-; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
-; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v0, s0, s1, v5
+; GFX11-NEXT: v_perm_b32 v1, s2, s3, v5
; GFX11-NEXT: v_perm_b32 v2, s16, s17, v5
+; GFX11-NEXT: v_perm_b32 v3, s18, s19, v5
; GFX11-NEXT: v_perm_b32 v4, s20, s21, v5
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v5
; GFX11-NEXT: v_perm_b32 v7, s24, s25, v5
+; GFX11-NEXT: v_perm_b32 v8, s26, s27, v5
; GFX11-NEXT: v_perm_b32 v9, s28, s29, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v11, s9, s8, v5
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v6
-; GFX11-NEXT: v_perm_b32 v6, s45, s44, v5
-; GFX11-NEXT: v_or_b32_e32 v3, v7, v8
-; GFX11-NEXT: v_or_b32_e32 v4, v9, v10
-; GFX11-NEXT: v_perm_b32 v7, s41, s40, v5
-; GFX11-NEXT: v_perm_b32 v10, s13, s12, v5
-; GFX11-NEXT: v_perm_b32 v13, s5, s4, v5
-; GFX11-NEXT: v_perm_b32 v8, s47, s46, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-NEXT: v_perm_b32 v9, s43, s42, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v12, s15, s14, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v14, s11, s10, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v15, s7, s6, v5
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_or_b32_e32 v5, v8, v6
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v12, v10
-; GFX11-NEXT: v_or_b32_e32 v8, v14, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v13
+; GFX11-NEXT: v_perm_b32 v10, s57, s56, v5
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v4, v10, 16, v9
+; GFX11-NEXT: v_perm_b32 v6, s47, s46, v5
+; GFX11-NEXT: v_perm_b32 v7, s45, s44, v5
+; GFX11-NEXT: v_perm_b32 v8, s43, s42, v5
+; GFX11-NEXT: v_perm_b32 v9, s41, s40, v5
+; GFX11-NEXT: v_perm_b32 v10, s15, s14, v5
+; GFX11-NEXT: v_perm_b32 v11, s13, s12, v5
+; GFX11-NEXT: v_perm_b32 v12, s11, s10, v5
+; GFX11-NEXT: v_perm_b32 v13, s9, s8, v5
+; GFX11-NEXT: v_perm_b32 v14, s7, s6, v5
+; GFX11-NEXT: v_perm_b32 v15, s5, s4, v5
+; GFX11-NEXT: v_lshl_or_b32 v5, v7, 16, v6
+; GFX11-NEXT: v_lshl_or_b32 v6, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v7, v11, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v8, v13, 16, v12
+; GFX11-NEXT: v_lshl_or_b32 v9, v15, 16, v14
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s58
; GFX11-NEXT: s_cbranch_vccnz .LBB77_3
; GFX11-NEXT: .LBB77_2: ; %cmp.true
@@ -35262,76 +35093,66 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; GFX9-NEXT: s_lshr_b32 s75, s16, 16
; GFX9-NEXT: s_lshr_b32 s76, s16, 8
; GFX9-NEXT: .LBB79_3: ; %end
+; GFX9-NEXT: v_mov_b32_e32 v1, s76
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s12
-; GFX9-NEXT: v_mov_b32_e32 v1, s76
-; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s72
+; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s74
-; GFX9-NEXT: v_perm_b32 v3, s73, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s72
; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
+; GFX9-NEXT: v_perm_b32 v3, s73, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s59
+; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s61
-; GFX9-NEXT: v_perm_b32 v3, s60, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s59
; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_perm_b32 v3, s60, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s58
-; GFX9-NEXT: v_perm_b32 v3, s57, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s46
+; GFX9-NEXT: v_perm_b32 v3, s57, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s56
-; GFX9-NEXT: v_perm_b32 v3, s47, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s46
; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
+; GFX9-NEXT: v_perm_b32 v3, s47, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s45
-; GFX9-NEXT: v_perm_b32 v3, s44, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s41
+; GFX9-NEXT: v_perm_b32 v3, s44, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s43
-; GFX9-NEXT: v_perm_b32 v3, s42, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s41
; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s4
+; GFX9-NEXT: v_perm_b32 v3, s42, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s40
-; GFX9-NEXT: v_perm_b32 v3, s29, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s29, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s28
; GFX9-NEXT: v_mov_b32_e32 v3, s26
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s27, v3, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -35376,18 +35197,18 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB79_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s14, s21, 24
-; GFX11-NEXT: s_lshr_b32 s22, s21, 16
-; GFX11-NEXT: s_lshr_b32 s15, s21, 8
-; GFX11-NEXT: s_lshr_b32 s24, s20, 16
-; GFX11-NEXT: s_lshr_b32 s23, s20, 8
-; GFX11-NEXT: s_lshr_b32 s26, s19, 24
-; GFX11-NEXT: s_lshr_b32 s27, s19, 16
-; GFX11-NEXT: s_lshr_b32 s25, s19, 8
-; GFX11-NEXT: s_lshr_b32 s29, s18, 16
-; GFX11-NEXT: s_lshr_b32 s28, s18, 8
-; GFX11-NEXT: s_lshr_b32 s41, s17, 24
-; GFX11-NEXT: s_lshr_b32 s42, s17, 16
-; GFX11-NEXT: s_lshr_b32 s40, s17, 8
+; GFX11-NEXT: s_lshr_b32 s15, s21, 16
+; GFX11-NEXT: s_lshr_b32 s22, s21, 8
+; GFX11-NEXT: s_lshr_b32 s23, s20, 16
+; GFX11-NEXT: s_lshr_b32 s24, s20, 8
+; GFX11-NEXT: s_lshr_b32 s25, s19, 24
+; GFX11-NEXT: s_lshr_b32 s26, s19, 16
+; GFX11-NEXT: s_lshr_b32 s27, s19, 8
+; GFX11-NEXT: s_lshr_b32 s28, s18, 16
+; GFX11-NEXT: s_lshr_b32 s29, s18, 8
+; GFX11-NEXT: s_lshr_b32 s40, s17, 24
+; GFX11-NEXT: s_lshr_b32 s41, s17, 16
+; GFX11-NEXT: s_lshr_b32 s42, s17, 8
; GFX11-NEXT: s_lshr_b32 s43, s16, 16
; GFX11-NEXT: s_lshr_b32 s44, s16, 8
; GFX11-NEXT: s_lshr_b32 s45, s3, 24
@@ -35424,18 +35245,18 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; GFX11-NEXT: s_lshr_b64 s[10:11], s[2:3], 24
; GFX11-NEXT: s_lshr_b64 s[12:13], s[0:1], 24
; GFX11-NEXT: s_lshr_b32 s14, s21, 24
-; GFX11-NEXT: s_lshr_b32 s22, s21, 16
-; GFX11-NEXT: s_lshr_b32 s15, s21, 8
-; GFX11-NEXT: s_lshr_b32 s24, s20, 16
-; GFX11-NEXT: s_lshr_b32 s23, s20, 8
-; GFX11-NEXT: s_lshr_b32 s26, s19, 24
-; GFX11-NEXT: s_lshr_b32 s27, s19, 16
-; GFX11-NEXT: s_lshr_b32 s25, s19, 8
-; GFX11-NEXT: s_lshr_b32 s29, s18, 16
-; GFX11-NEXT: s_lshr_b32 s28, s18, 8
-; GFX11-NEXT: s_lshr_b32 s41, s17, 24
-; GFX11-NEXT: s_lshr_b32 s42, s17, 16
-; GFX11-NEXT: s_lshr_b32 s40, s17, 8
+; GFX11-NEXT: s_lshr_b32 s15, s21, 16
+; GFX11-NEXT: s_lshr_b32 s22, s21, 8
+; GFX11-NEXT: s_lshr_b32 s23, s20, 16
+; GFX11-NEXT: s_lshr_b32 s24, s20, 8
+; GFX11-NEXT: s_lshr_b32 s25, s19, 24
+; GFX11-NEXT: s_lshr_b32 s26, s19, 16
+; GFX11-NEXT: s_lshr_b32 s27, s19, 8
+; GFX11-NEXT: s_lshr_b32 s28, s18, 16
+; GFX11-NEXT: s_lshr_b32 s29, s18, 8
+; GFX11-NEXT: s_lshr_b32 s40, s17, 24
+; GFX11-NEXT: s_lshr_b32 s41, s17, 16
+; GFX11-NEXT: s_lshr_b32 s42, s17, 8
; GFX11-NEXT: s_lshr_b32 s43, s16, 16
; GFX11-NEXT: s_lshr_b32 s44, s16, 8
; GFX11-NEXT: s_lshr_b32 s45, s3, 24
@@ -35450,47 +35271,37 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; GFX11-NEXT: s_lshr_b32 s62, s0, 8
; GFX11-NEXT: .LBB79_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v6, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v2, s61, s12, v6
-; GFX11-NEXT: v_perm_b32 v4, s59, s58, v6
-; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
-; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s0, s62, v6
+; GFX11-NEXT: v_perm_b32 v2, s61, s12, v6
; GFX11-NEXT: v_perm_b32 v3, s1, s60, v6
+; GFX11-NEXT: v_perm_b32 v4, s59, s58, v6
; GFX11-NEXT: v_perm_b32 v5, s2, s57, v6
+; GFX11-NEXT: v_perm_b32 v7, s56, s10, v6
; GFX11-NEXT: v_perm_b32 v8, s3, s47, v6
+; GFX11-NEXT: v_perm_b32 v9, s46, s45, v6
; GFX11-NEXT: v_perm_b32 v10, s16, s44, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v12, s24, s4, v6
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v5, v7
-; GFX11-NEXT: v_perm_b32 v7, s42, s41, v6
-; GFX11-NEXT: v_or_b32_e32 v4, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v5, v10, v11
-; GFX11-NEXT: v_perm_b32 v8, s29, s6, v6
-; GFX11-NEXT: v_perm_b32 v11, s27, s26, v6
-; GFX11-NEXT: v_perm_b32 v14, s22, s14, v6
-; GFX11-NEXT: v_perm_b32 v9, s17, s40, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v10, s18, s28, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_perm_b32 v13, s19, s25, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v15, s20, s23, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT: v_perm_b32 v16, s21, s15, v6
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_or_b32_e32 v6, v9, v7
-; GFX11-NEXT: v_or_b32_e32 v7, v10, v8
-; GFX11-NEXT: v_or_b32_e32 v8, v13, v11
-; GFX11-NEXT: v_or_b32_e32 v9, v15, v12
-; GFX11-NEXT: v_or_b32_e32 v10, v16, v14
+; GFX11-NEXT: v_perm_b32 v11, s43, s8, v6
+; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v7, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-NEXT: v_perm_b32 v7, s17, s42, v6
+; GFX11-NEXT: v_perm_b32 v8, s41, s40, v6
+; GFX11-NEXT: v_perm_b32 v9, s18, s29, v6
+; GFX11-NEXT: v_perm_b32 v10, s28, s6, v6
+; GFX11-NEXT: v_perm_b32 v11, s19, s27, v6
+; GFX11-NEXT: v_perm_b32 v12, s26, s25, v6
+; GFX11-NEXT: v_perm_b32 v13, s20, s24, v6
+; GFX11-NEXT: v_perm_b32 v14, s23, s4, v6
+; GFX11-NEXT: v_perm_b32 v15, s21, s22, v6
+; GFX11-NEXT: v_perm_b32 v16, s15, s14, v6
+; GFX11-NEXT: v_lshl_or_b32 v6, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v7, v10, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v8, v12, 16, v11
+; GFX11-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v10, v16, 16, v15
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
; GFX11-NEXT: scratch_store_b128 v0, v[5:8], off offset:16
@@ -35512,20 +35323,20 @@ define inreg <40 x i8> @bitcast_v5i64_to_v40i8_scalar(<5 x i64> inreg %a, i32 in
; GFX11-NEXT: ; implicit-def: $sgpr44
; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: ; implicit-def: $sgpr8
-; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: ; implicit-def: $sgpr42
; GFX11-NEXT: ; implicit-def: $sgpr41
-; GFX11-NEXT: ; implicit-def: $sgpr28
+; GFX11-NEXT: ; implicit-def: $sgpr40
; GFX11-NEXT: ; implicit-def: $sgpr29
+; GFX11-NEXT: ; implicit-def: $sgpr28
; GFX11-NEXT: ; implicit-def: $sgpr6
-; GFX11-NEXT: ; implicit-def: $sgpr25
; GFX11-NEXT: ; implicit-def: $sgpr27
; GFX11-NEXT: ; implicit-def: $sgpr26
-; GFX11-NEXT: ; implicit-def: $sgpr23
+; GFX11-NEXT: ; implicit-def: $sgpr25
; GFX11-NEXT: ; implicit-def: $sgpr24
+; GFX11-NEXT: ; implicit-def: $sgpr23
; GFX11-NEXT: ; implicit-def: $sgpr4
-; GFX11-NEXT: ; implicit-def: $sgpr15
; GFX11-NEXT: ; implicit-def: $sgpr22
+; GFX11-NEXT: ; implicit-def: $sgpr15
; GFX11-NEXT: ; implicit-def: $sgpr14
; GFX11-NEXT: s_branch .LBB79_2
%cmp = icmp eq i32 %b, 0
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
index 123d1042e27c9..7332c2966234c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.32bit.ll
@@ -2482,8 +2482,7 @@ define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) #0
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB23_3
; GFX9-NEXT: .LBB23_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -2511,12 +2510,10 @@ define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) #0
; GFX11-NEXT: s_cbranch_scc0 .LBB23_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v0, s2, s3, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB23_3
; GFX11-NEXT: .LBB23_2: ; %cmp.true
@@ -4745,8 +4742,7 @@ define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b)
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB43_3
; GFX9-NEXT: .LBB43_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -4774,12 +4770,10 @@ define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b)
; GFX11-NEXT: s_cbranch_scc0 .LBB43_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v0, s2, s3, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB43_3
; GFX11-NEXT: .LBB43_2: ; %cmp.true
@@ -6732,8 +6726,7 @@ define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inre
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB59_3
; GFX9-NEXT: .LBB59_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -6761,12 +6754,10 @@ define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_cbranch_scc0 .LBB59_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v0, s2, s3, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB59_3
; GFX11-NEXT: .LBB59_2: ; %cmp.true
@@ -8391,8 +8382,7 @@ define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inr
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -8420,12 +8410,10 @@ define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inr
; GFX11-NEXT: s_cbranch_scc0 .LBB71_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v0, s2, s3, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-NEXT: .LBB71_2: ; %cmp.true
@@ -9830,8 +9818,7 @@ define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB79_3
; GFX9-NEXT: .LBB79_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9859,12 +9846,10 @@ define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB79_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v0, s2, s3, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB79_3
; GFX11-NEXT: .LBB79_2: ; %cmp.true
@@ -10512,8 +10497,7 @@ define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inre
; GFX9-NEXT: v_mov_b32_e32 v2, s19
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
; GFX9-NEXT: v_perm_b32 v1, s18, v2, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: s_cbranch_execnz .LBB83_3
; GFX9-NEXT: .LBB83_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -10541,12 +10525,10 @@ define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_cbranch_scc0 .LBB83_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-NEXT: v_perm_b32 v0, s0, s1, v0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v0, s2, s3, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB83_3
; GFX11-NEXT: .LBB83_2: ; %cmp.true
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index d43b0226756d5..5a3ab768e543d 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -10887,118 +10887,102 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX9-NEXT: s_lshr_b32 s54, s16, 16
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
; GFX9-NEXT: .LBB25_3: ; %end
+; GFX9-NEXT: v_mov_b32_e32 v1, s55
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s44
-; GFX9-NEXT: v_mov_b32_e32 v1, s55
-; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s51
+; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s53
-; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s51
; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s42
+; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s50
-; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s42
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s38
+; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s48
-; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s38
; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s40
+; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s37
-; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s40
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s31
+; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s35
-; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s31
; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s14
+; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s30
-; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s92
+; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s94
-; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s92
; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s12
+; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s91
-; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s79
+; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s89
-; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s79
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
+; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: v_mov_b32_e32 v1, s78
-; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_perm_b32 v1, s26, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s74
+; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_mov_b32_e32 v1, s76
-; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: v_perm_b32 v1, s27, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_mov_b32_e32 v1, s73
-; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_perm_b32 v1, s28, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s61
+; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s61
; GFX9-NEXT: v_perm_b32 v1, s29, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
+; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v1, s60
-; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_perm_b32 v1, s4, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v1, s58
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_perm_b32 v1, s5, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s57, v3, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_readlane_b32 s30, v4, 14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_readlane_b32 s31, v4, 15
@@ -11092,35 +11076,35 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB25_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
-; GFX11-NEXT: s_lshr_b32 s44, s27, 16
-; GFX11-NEXT: s_lshr_b32 s43, s27, 8
-; GFX11-NEXT: s_lshr_b32 s46, s26, 16
-; GFX11-NEXT: s_lshr_b32 s45, s26, 8
-; GFX11-NEXT: s_lshr_b32 s56, s25, 24
-; GFX11-NEXT: s_lshr_b32 s57, s25, 16
-; GFX11-NEXT: s_lshr_b32 s47, s25, 8
-; GFX11-NEXT: s_lshr_b32 s59, s24, 16
-; GFX11-NEXT: s_lshr_b32 s58, s24, 8
-; GFX11-NEXT: s_lshr_b32 s61, s23, 24
-; GFX11-NEXT: s_lshr_b32 s62, s23, 16
-; GFX11-NEXT: s_lshr_b32 s60, s23, 8
-; GFX11-NEXT: s_lshr_b32 s72, s22, 16
-; GFX11-NEXT: s_lshr_b32 s63, s22, 8
-; GFX11-NEXT: s_lshr_b32 s74, s21, 24
-; GFX11-NEXT: s_lshr_b32 s75, s21, 16
-; GFX11-NEXT: s_lshr_b32 s73, s21, 8
-; GFX11-NEXT: s_lshr_b32 s77, s20, 16
-; GFX11-NEXT: s_lshr_b32 s76, s20, 8
+; GFX11-NEXT: s_lshr_b32 s43, s27, 16
+; GFX11-NEXT: s_lshr_b32 s44, s27, 8
+; GFX11-NEXT: s_lshr_b32 s45, s26, 16
+; GFX11-NEXT: s_lshr_b32 s46, s26, 8
+; GFX11-NEXT: s_lshr_b32 s47, s25, 24
+; GFX11-NEXT: s_lshr_b32 s56, s25, 16
+; GFX11-NEXT: s_lshr_b32 s57, s25, 8
+; GFX11-NEXT: s_lshr_b32 s58, s24, 16
+; GFX11-NEXT: s_lshr_b32 s59, s24, 8
+; GFX11-NEXT: s_lshr_b32 s60, s23, 24
+; GFX11-NEXT: s_lshr_b32 s61, s23, 16
+; GFX11-NEXT: s_lshr_b32 s62, s23, 8
+; GFX11-NEXT: s_lshr_b32 s63, s22, 16
+; GFX11-NEXT: s_lshr_b32 s72, s22, 8
+; GFX11-NEXT: s_lshr_b32 s73, s21, 24
+; GFX11-NEXT: s_lshr_b32 s74, s21, 16
+; GFX11-NEXT: s_lshr_b32 s75, s21, 8
+; GFX11-NEXT: s_lshr_b32 s76, s20, 16
+; GFX11-NEXT: s_lshr_b32 s77, s20, 8
; GFX11-NEXT: s_lshr_b32 s78, s19, 24
-; GFX11-NEXT: s_lshr_b32 s88, s19, 16
-; GFX11-NEXT: s_lshr_b32 s79, s19, 8
-; GFX11-NEXT: s_lshr_b32 s90, s18, 16
-; GFX11-NEXT: s_lshr_b32 s89, s18, 8
-; GFX11-NEXT: s_lshr_b32 s92, s17, 24
-; GFX11-NEXT: s_lshr_b32 s93, s17, 16
-; GFX11-NEXT: s_lshr_b32 s91, s17, 8
-; GFX11-NEXT: s_lshr_b32 s95, s16, 16
-; GFX11-NEXT: s_lshr_b32 s94, s16, 8
+; GFX11-NEXT: s_lshr_b32 s79, s19, 16
+; GFX11-NEXT: s_lshr_b32 s88, s19, 8
+; GFX11-NEXT: s_lshr_b32 s89, s18, 16
+; GFX11-NEXT: s_lshr_b32 s90, s18, 8
+; GFX11-NEXT: s_lshr_b32 s91, s17, 24
+; GFX11-NEXT: s_lshr_b32 s92, s17, 16
+; GFX11-NEXT: s_lshr_b32 s93, s17, 8
+; GFX11-NEXT: s_lshr_b32 s94, s16, 16
+; GFX11-NEXT: s_lshr_b32 s95, s16, 8
; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 24
; GFX11-NEXT: s_lshr_b32 s30, s3, 16
; GFX11-NEXT: s_lshr_b32 s31, s3, 8
@@ -11167,35 +11151,35 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: s_lshr_b64 s[28:29], s[2:3], 24
; GFX11-NEXT: s_lshr_b64 s[40:41], s[0:1], 24
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
-; GFX11-NEXT: s_lshr_b32 s44, s27, 16
-; GFX11-NEXT: s_lshr_b32 s43, s27, 8
-; GFX11-NEXT: s_lshr_b32 s46, s26, 16
-; GFX11-NEXT: s_lshr_b32 s45, s26, 8
-; GFX11-NEXT: s_lshr_b32 s56, s25, 24
-; GFX11-NEXT: s_lshr_b32 s57, s25, 16
-; GFX11-NEXT: s_lshr_b32 s47, s25, 8
-; GFX11-NEXT: s_lshr_b32 s59, s24, 16
-; GFX11-NEXT: s_lshr_b32 s58, s24, 8
-; GFX11-NEXT: s_lshr_b32 s61, s23, 24
-; GFX11-NEXT: s_lshr_b32 s62, s23, 16
-; GFX11-NEXT: s_lshr_b32 s60, s23, 8
-; GFX11-NEXT: s_lshr_b32 s72, s22, 16
-; GFX11-NEXT: s_lshr_b32 s63, s22, 8
-; GFX11-NEXT: s_lshr_b32 s74, s21, 24
-; GFX11-NEXT: s_lshr_b32 s75, s21, 16
-; GFX11-NEXT: s_lshr_b32 s73, s21, 8
-; GFX11-NEXT: s_lshr_b32 s77, s20, 16
-; GFX11-NEXT: s_lshr_b32 s76, s20, 8
+; GFX11-NEXT: s_lshr_b32 s43, s27, 16
+; GFX11-NEXT: s_lshr_b32 s44, s27, 8
+; GFX11-NEXT: s_lshr_b32 s45, s26, 16
+; GFX11-NEXT: s_lshr_b32 s46, s26, 8
+; GFX11-NEXT: s_lshr_b32 s47, s25, 24
+; GFX11-NEXT: s_lshr_b32 s56, s25, 16
+; GFX11-NEXT: s_lshr_b32 s57, s25, 8
+; GFX11-NEXT: s_lshr_b32 s58, s24, 16
+; GFX11-NEXT: s_lshr_b32 s59, s24, 8
+; GFX11-NEXT: s_lshr_b32 s60, s23, 24
+; GFX11-NEXT: s_lshr_b32 s61, s23, 16
+; GFX11-NEXT: s_lshr_b32 s62, s23, 8
+; GFX11-NEXT: s_lshr_b32 s63, s22, 16
+; GFX11-NEXT: s_lshr_b32 s72, s22, 8
+; GFX11-NEXT: s_lshr_b32 s73, s21, 24
+; GFX11-NEXT: s_lshr_b32 s74, s21, 16
+; GFX11-NEXT: s_lshr_b32 s75, s21, 8
+; GFX11-NEXT: s_lshr_b32 s76, s20, 16
+; GFX11-NEXT: s_lshr_b32 s77, s20, 8
; GFX11-NEXT: s_lshr_b32 s78, s19, 24
-; GFX11-NEXT: s_lshr_b32 s88, s19, 16
-; GFX11-NEXT: s_lshr_b32 s79, s19, 8
-; GFX11-NEXT: s_lshr_b32 s90, s18, 16
-; GFX11-NEXT: s_lshr_b32 s89, s18, 8
-; GFX11-NEXT: s_lshr_b32 s92, s17, 24
-; GFX11-NEXT: s_lshr_b32 s93, s17, 16
-; GFX11-NEXT: s_lshr_b32 s91, s17, 8
-; GFX11-NEXT: s_lshr_b32 s95, s16, 16
-; GFX11-NEXT: s_lshr_b32 s94, s16, 8
+; GFX11-NEXT: s_lshr_b32 s79, s19, 16
+; GFX11-NEXT: s_lshr_b32 s88, s19, 8
+; GFX11-NEXT: s_lshr_b32 s89, s18, 16
+; GFX11-NEXT: s_lshr_b32 s90, s18, 8
+; GFX11-NEXT: s_lshr_b32 s91, s17, 24
+; GFX11-NEXT: s_lshr_b32 s92, s17, 16
+; GFX11-NEXT: s_lshr_b32 s93, s17, 8
+; GFX11-NEXT: s_lshr_b32 s94, s16, 16
+; GFX11-NEXT: s_lshr_b32 s95, s16, 8
; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 24
; GFX11-NEXT: s_lshr_b32 s30, s3, 16
; GFX11-NEXT: s_lshr_b32 s31, s3, 8
@@ -11208,72 +11192,55 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
; GFX11-NEXT: .LBB25_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v12, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
-; GFX11-NEXT: v_readlane_b32 s34, v23, 0
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
-; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s0, s48, v12
+; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
; GFX11-NEXT: v_perm_b32 v3, s1, s38, v12
-; GFX11-NEXT: v_perm_b32 v6, s2, s35, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v8, s30, vcc_hi, v12
-; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
-; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v6, v5
-; GFX11-NEXT: v_perm_b32 v5, s93, s92, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s16, s94, v12
-; GFX11-NEXT: v_perm_b32 v8, s90, s12, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
+; GFX11-NEXT: v_perm_b32 v5, s2, s35, v12
+; GFX11-NEXT: v_perm_b32 v6, s34, s28, v12
; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
-; GFX11-NEXT: v_perm_b32 v13, s18, s89, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_or_b32_e32 v5, v6, v9
-; GFX11-NEXT: v_perm_b32 v9, s88, s78, v12
-; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT: v_perm_b32 v10, s77, s10, v12
-; GFX11-NEXT: v_perm_b32 v11, s75, s74, v12
-; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
-; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v8
-; GFX11-NEXT: v_perm_b32 v8, s19, s79, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v13, s20, s76, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v15, s21, s73, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v16, s22, s63, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v9, v13, v10
-; GFX11-NEXT: v_perm_b32 v13, s62, s61, v12
-; GFX11-NEXT: v_or_b32_e32 v10, v15, v11
-; GFX11-NEXT: v_or_b32_e32 v11, v16, v14
-; GFX11-NEXT: v_perm_b32 v14, s59, s6, v12
-; GFX11-NEXT: v_perm_b32 v17, s57, s56, v12
-; GFX11-NEXT: v_perm_b32 v18, s46, s4, v12
-; GFX11-NEXT: v_perm_b32 v20, s44, s42, v12
-; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v19, s25, s47, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT: v_perm_b32 v21, s26, s45, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v22, s27, s43, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT: v_or_b32_e32 v12, v15, v13
-; GFX11-NEXT: v_or_b32_e32 v13, v16, v14
-; GFX11-NEXT: v_or_b32_e32 v14, v19, v17
-; GFX11-NEXT: v_or_b32_e32 v15, v21, v18
-; GFX11-NEXT: v_or_b32_e32 v16, v22, v20
+; GFX11-NEXT: v_perm_b32 v8, s30, vcc_hi, v12
+; GFX11-NEXT: v_perm_b32 v9, s16, s95, v12
+; GFX11-NEXT: v_perm_b32 v10, s94, s14, v12
+; GFX11-NEXT: v_perm_b32 v11, s17, s93, v12
+; GFX11-NEXT: v_perm_b32 v13, s92, s91, v12
+; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v4, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v5, v10, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v6, v13, 16, v11
+; GFX11-NEXT: v_perm_b32 v7, s18, s90, v12
+; GFX11-NEXT: v_perm_b32 v8, s89, s12, v12
+; GFX11-NEXT: v_perm_b32 v9, s19, s88, v12
+; GFX11-NEXT: v_perm_b32 v10, s79, s78, v12
+; GFX11-NEXT: v_perm_b32 v11, s20, s77, v12
+; GFX11-NEXT: v_perm_b32 v13, s76, s10, v12
+; GFX11-NEXT: v_perm_b32 v14, s21, s75, v12
+; GFX11-NEXT: v_perm_b32 v15, s74, s73, v12
+; GFX11-NEXT: v_perm_b32 v16, s22, s72, v12
+; GFX11-NEXT: v_perm_b32 v17, s63, s8, v12
+; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v8, v10, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v9, v13, 16, v11
+; GFX11-NEXT: v_lshl_or_b32 v10, v15, 16, v14
+; GFX11-NEXT: v_perm_b32 v13, s23, s62, v12
+; GFX11-NEXT: v_perm_b32 v14, s61, s60, v12
+; GFX11-NEXT: v_lshl_or_b32 v11, v17, 16, v16
+; GFX11-NEXT: v_perm_b32 v15, s24, s59, v12
+; GFX11-NEXT: v_perm_b32 v16, s58, s6, v12
+; GFX11-NEXT: v_perm_b32 v17, s25, s57, v12
+; GFX11-NEXT: v_perm_b32 v18, s56, s47, v12
+; GFX11-NEXT: v_perm_b32 v19, s26, s46, v12
+; GFX11-NEXT: v_perm_b32 v20, s45, s4, v12
+; GFX11-NEXT: v_perm_b32 v21, s27, s44, v12
+; GFX11-NEXT: v_perm_b32 v22, s43, s42, v12
+; GFX11-NEXT: v_lshl_or_b32 v12, v14, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v16, 16, v15
+; GFX11-NEXT: v_lshl_or_b32 v14, v18, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v15, v20, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v16, v22, 16, v21
; GFX11-NEXT: v_readlane_b32 s30, v23, 7
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
@@ -11287,6 +11254,7 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: v_readlane_b32 s37, v23, 3
; GFX11-NEXT: v_readlane_b32 s36, v23, 2
; GFX11-NEXT: v_readlane_b32 s35, v23, 1
+; GFX11-NEXT: v_readlane_b32 s34, v23, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v23, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -11305,41 +11273,41 @@ define inreg <64 x i8> @bitcast_v16i32_to_v64i8_scalar(<16 x i32> inreg %a, i32
; GFX11-NEXT: ; implicit-def: $sgpr31
; GFX11-NEXT: ; implicit-def: $sgpr30
; GFX11-NEXT: ; implicit-def: $vcc_hi
-; GFX11-NEXT: ; implicit-def: $sgpr94
; GFX11-NEXT: ; implicit-def: $sgpr95
+; GFX11-NEXT: ; implicit-def: $sgpr94
; GFX11-NEXT: ; implicit-def: $sgpr14
-; GFX11-NEXT: ; implicit-def: $sgpr91
; GFX11-NEXT: ; implicit-def: $sgpr93
; GFX11-NEXT: ; implicit-def: $sgpr92
-; GFX11-NEXT: ; implicit-def: $sgpr89
+; GFX11-NEXT: ; implicit-def: $sgpr91
; GFX11-NEXT: ; implicit-def: $sgpr90
+; GFX11-NEXT: ; implicit-def: $sgpr89
; GFX11-NEXT: ; implicit-def: $sgpr12
-; GFX11-NEXT: ; implicit-def: $sgpr79
; GFX11-NEXT: ; implicit-def: $sgpr88
+; GFX11-NEXT: ; implicit-def: $sgpr79
; GFX11-NEXT: ; implicit-def: $sgpr78
-; GFX11-NEXT: ; implicit-def: $sgpr76
; GFX11-NEXT: ; implicit-def: $sgpr77
+; GFX11-NEXT: ; implicit-def: $sgpr76
; GFX11-NEXT: ; implicit-def: $sgpr10
-; GFX11-NEXT: ; implicit-def: $sgpr73
; GFX11-NEXT: ; implicit-def: $sgpr75
; GFX11-NEXT: ; implicit-def: $sgpr74
-; GFX11-NEXT: ; implicit-def: $sgpr63
+; GFX11-NEXT: ; implicit-def: $sgpr73
; GFX11-NEXT: ; implicit-def: $sgpr72
+; GFX11-NEXT: ; implicit-def: $sgpr63
; GFX11-NEXT: ; implicit-def: $sgpr8
-; GFX11-NEXT: ; implicit-def: $sgpr60
; GFX11-NEXT: ; implicit-def: $sgpr62
; GFX11-NEXT: ; implicit-def: $sgpr61
-; GFX11-NEXT: ; implicit-def: $sgpr58
+; GFX11-NEXT: ; implicit-def: $sgpr60
; GFX11-NEXT: ; implicit-def: $sgpr59
+; GFX11-NEXT: ; implicit-def: $sgpr58
; GFX11-NEXT: ; implicit-def: $sgpr6
-; GFX11-NEXT: ; implicit-def: $sgpr47
; GFX11-NEXT: ; implicit-def: $sgpr57
; GFX11-NEXT: ; implicit-def: $sgpr56
-; GFX11-NEXT: ; implicit-def: $sgpr45
+; GFX11-NEXT: ; implicit-def: $sgpr47
; GFX11-NEXT: ; implicit-def: $sgpr46
+; GFX11-NEXT: ; implicit-def: $sgpr45
; GFX11-NEXT: ; implicit-def: $sgpr4
-; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: ; implicit-def: $sgpr44
+; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: ; implicit-def: $sgpr42
; GFX11-NEXT: s_branch .LBB25_2
%cmp = icmp eq i32 %b, 0
@@ -14447,98 +14415,80 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
+; GFX9-NEXT: v_perm_b32 v12, v34, v33, s4
+; GFX9-NEXT: v_perm_b32 v13, v32, v31, s4
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX9-NEXT: v_perm_b32 v13, v30, v29, s4
+; GFX9-NEXT: v_perm_b32 v14, v28, v27, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_perm_b32 v14, v26, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v22, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX9-NEXT: v_perm_b32 v15, v19, v18, s4
+; GFX9-NEXT: v_perm_b32 v35, v17, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v35, 16, v15
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -14746,75 +14696,56 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB27_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s72, s63, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s62, s61, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v12, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s44, s43, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s42, s41, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s40, s15, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s14, s13, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s10, s9, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v16, 16, v15
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v52, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v11, 16, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-TRUE16-NEXT: .LBB27_2: ; %cmp.true
@@ -15030,75 +14961,56 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB27_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v36, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s72, s63, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s62, s61, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s43, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s42, s41, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s40, s15, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s14, s13, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s10, s9, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v16, 16, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s8, s7, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s4, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-FAKE16-NEXT: .LBB27_2: ; %cmp.true
@@ -25717,32 +25629,32 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_add_f32_e64 v1, s4, 1.0
; GFX9-NEXT: v_add_f32_e64 v8, s25, 1.0
; GFX9-NEXT: v_add_f32_e64 v7, s24, 1.0
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
+; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[5:6]
; GFX9-NEXT: v_add_f32_e64 v10, s23, 1.0
; GFX9-NEXT: v_add_f32_e64 v9, s22, 1.0
-; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[7:8]
; GFX9-NEXT: v_add_f32_e64 v12, s21, 1.0
; GFX9-NEXT: v_add_f32_e64 v11, s20, 1.0
; GFX9-NEXT: v_add_f32_e64 v4, s29, 1.0
; GFX9-NEXT: v_add_f32_e64 v3, s28, 1.0
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[9:10]
; GFX9-NEXT: v_add_f32_e64 v14, s19, 1.0
; GFX9-NEXT: v_add_f32_e64 v13, s18, 1.0
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4]
-; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
-; GFX9-NEXT: v_add_f32_e64 v19, s17, 1.0
-; GFX9-NEXT: v_add_f32_e64 v18, s16, 1.0
-; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[3:4]
+; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[11:12]
+; GFX9-NEXT: v_add_f32_e64 v16, s17, 1.0
+; GFX9-NEXT: v_add_f32_e64 v15, s16, 1.0
+; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[25:26], 24, v[18:19]
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[15:16]
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 8, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v1
@@ -25776,11 +25688,11 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v13
-; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v62, 8, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v18
+; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v16
+; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v16
+; GFX9-NEXT: v_lshrrev_b32_e32 v62, 8, v16
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v15
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v15
; GFX9-NEXT: s_branch .LBB49_5
; GFX9-NEXT: .LBB49_3:
; GFX9-NEXT: ; implicit-def: $sgpr55
@@ -25833,13 +25745,13 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: s_branch .LBB49_2
; GFX9-NEXT: .LBB49_4:
-; GFX9-NEXT: v_mov_b32_e32 v20, s44
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v19, s44
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v20, s42
-; GFX9-NEXT: v_mov_b32_e32 v18, s16
-; GFX9-NEXT: v_mov_b32_e32 v19, s17
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v19, s42
+; GFX9-NEXT: v_mov_b32_e32 v15, s16
+; GFX9-NEXT: v_mov_b32_e32 v16, s17
; GFX9-NEXT: v_mov_b32_e32 v13, s18
; GFX9-NEXT: v_mov_b32_e32 v14, s19
; GFX9-NEXT: v_mov_b32_e32 v11, s20
@@ -25854,8 +25766,8 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s5
-; GFX9-NEXT: v_mov_b32_e32 v15, s55
-; GFX9-NEXT: v_mov_b32_e32 v16, s53
+; GFX9-NEXT: v_mov_b32_e32 v17, s55
+; GFX9-NEXT: v_mov_b32_e32 v18, s53
; GFX9-NEXT: v_mov_b32_e32 v62, s54
; GFX9-NEXT: v_mov_b32_e32 v59, s52
; GFX9-NEXT: v_mov_b32_e32 v60, s51
@@ -25892,78 +25804,66 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_mov_b32_e32 v29, s60
; GFX9-NEXT: v_mov_b32_e32 v28, s58
; GFX9-NEXT: v_mov_b32_e32 v27, s59
-; GFX9-NEXT: v_mov_b32_e32 v17, s57
+; GFX9-NEXT: v_mov_b32_e32 v25, s57
; GFX9-NEXT: v_mov_b32_e32 v26, s56
-; GFX9-NEXT: v_mov_b32_e32 v22, s12
-; GFX9-NEXT: v_mov_b32_e32 v23, s10
-; GFX9-NEXT: v_mov_b32_e32 v24, s8
-; GFX9-NEXT: v_mov_b32_e32 v25, s6
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v21, s12
+; GFX9-NEXT: v_mov_b32_e32 v22, s10
+; GFX9-NEXT: v_mov_b32_e32 v23, s8
+; GFX9-NEXT: v_mov_b32_e32 v24, s6
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v20, s40
-; GFX9-NEXT: v_mov_b32_e32 v21, s14
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v19, s40
+; GFX9-NEXT: v_mov_b32_e32 v20, s14
; GFX9-NEXT: .LBB49_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
-; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
-; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_perm_b32 v15, v15, v17, s4
+; GFX9-NEXT: v_perm_b32 v17, v61, v23, s4
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v17, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_perm_b32 v13, v45, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_perm_b32 v11, v40, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v51, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_perm_b32 v18, v18, v24, s4
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v38, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v18, 16, v15
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_perm_b32 v16, v16, v62, s4
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -25988,26 +25888,22 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
-; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, v25, v26, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -26101,6 +25997,8 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-NEXT: s_cbranch_vccnz .LBB49_4
; GFX11-NEXT: .LBB49_2: ; %cmp.true
+; GFX11-NEXT: v_add_f32_e64 v2, s27, 1.0
+; GFX11-NEXT: v_add_f32_e64 v1, s26, 1.0
; GFX11-NEXT: v_add_f32_e64 v4, s25, 1.0
; GFX11-NEXT: v_add_f32_e64 v3, s24, 1.0
; GFX11-NEXT: v_add_f32_e64 v6, s23, 1.0
@@ -26111,60 +26009,58 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX11-NEXT: v_add_f32_e64 v9, s18, 1.0
; GFX11-NEXT: v_add_f32_e64 v12, s17, 1.0
; GFX11-NEXT: v_add_f32_e64 v11, s16, 1.0
+; GFX11-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
; GFX11-NEXT: v_add_f32_e64 v14, s3, 1.0
; GFX11-NEXT: v_add_f32_e64 v13, s2, 1.0
-; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[3:4]
-; GFX11-NEXT: v_add_f32_e64 v18, s1, 1.0
-; GFX11-NEXT: v_add_f32_e64 v17, s0, 1.0
-; GFX11-NEXT: v_add_f32_e64 v2, s27, 1.0
-; GFX11-NEXT: v_add_f32_e64 v1, s26, 1.0
-; GFX11-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
-; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
-; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
-; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
-; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[17:18]
-; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v27, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v16, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v37, 24, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v38, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v51, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v49, 8, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v55, 24, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v53, 8, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v64, 8, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v69, 24, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v65, 8, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v67, 8, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v81, 24, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v71, 8, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v82, 8, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v87, 24, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v85, 8, v17
+; GFX11-NEXT: v_lshrrev_b64 v[18:19], 24, v[3:4]
+; GFX11-NEXT: v_add_f32_e64 v16, s1, 1.0
+; GFX11-NEXT: v_add_f32_e64 v15, s0, 1.0
+; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[5:6]
+; GFX11-NEXT: v_lshrrev_b64 v[20:21], 24, v[7:8]
+; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[9:10]
+; GFX11-NEXT: v_lshrrev_b64 v[22:23], 24, v[11:12]
+; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14]
+; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[15:16]
+; GFX11-NEXT: v_lshrrev_b32_e32 v26, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v25, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v27, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v28, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v36, 24, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v37, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v49, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v50, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v52, 8, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v54, 24, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v64, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v65, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v67, 24, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v68, 8, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v70, 8, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v80, 24, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v81, 8, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v85, 24, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v86, 8, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v96, 8, v15
; GFX11-NEXT: s_branch .LBB49_5
; GFX11-NEXT: .LBB49_3:
; GFX11-NEXT: ; implicit-def: $sgpr49
@@ -26217,7 +26113,7 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: s_branch .LBB49_2
; GFX11-NEXT: .LBB49_4:
-; GFX11-NEXT: v_dual_mov_b32 v17, s0 :: v_dual_mov_b32 v18, s1
+; GFX11-NEXT: v_dual_mov_b32 v15, s0 :: v_dual_mov_b32 v16, s1
; GFX11-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v14, s3
; GFX11-NEXT: v_dual_mov_b32 v11, s16 :: v_dual_mov_b32 v12, s17
; GFX11-NEXT: v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
@@ -26225,100 +26121,84 @@ define inreg <64 x i8> @bitcast_v16f32_to_v64i8_scalar(<16 x float> inreg %a, i3
; GFX11-NEXT: v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v6, s23
; GFX11-NEXT: v_dual_mov_b32 v3, s24 :: v_dual_mov_b32 v4, s25
; GFX11-NEXT: v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v2, s27
-; GFX11-NEXT: v_dual_mov_b32 v85, s49 :: v_dual_mov_b32 v96, s39
-; GFX11-NEXT: v_dual_mov_b32 v83, s48 :: v_dual_mov_b32 v86, s38
-; GFX11-NEXT: v_dual_mov_b32 v87, s37 :: v_dual_mov_b32 v82, s36
-; GFX11-NEXT: v_dual_mov_b32 v84, s34 :: v_dual_mov_b32 v71, s35
-; GFX11-NEXT: v_dual_mov_b32 v80, s31 :: v_dual_mov_b32 v81, s30
-; GFX11-NEXT: v_dual_mov_b32 v67, vcc_hi :: v_dual_mov_b32 v70, s94
-; GFX11-NEXT: v_dual_mov_b32 v65, s95 :: v_dual_mov_b32 v68, s93
-; GFX11-NEXT: v_dual_mov_b32 v69, s92 :: v_dual_mov_b32 v64, s91
-; GFX11-NEXT: v_dual_mov_b32 v66, s89 :: v_dual_mov_b32 v53, s90
-; GFX11-NEXT: v_dual_mov_b32 v54, s88 :: v_dual_mov_b32 v55, s79
-; GFX11-NEXT: v_dual_mov_b32 v49, s78 :: v_dual_mov_b32 v52, s76
-; GFX11-NEXT: v_dual_mov_b32 v39, s77 :: v_dual_mov_b32 v50, s75
-; GFX11-NEXT: v_dual_mov_b32 v51, s74 :: v_dual_mov_b32 v38, s73
-; GFX11-NEXT: v_dual_mov_b32 v48, s63 :: v_dual_mov_b32 v37, s61
-; GFX11-NEXT: v_dual_mov_b32 v34, s72 :: v_dual_mov_b32 v33, s60
-; GFX11-NEXT: v_dual_mov_b32 v36, s62 :: v_dual_mov_b32 v35, s58
-; GFX11-NEXT: v_dual_mov_b32 v29, s59 :: v_dual_mov_b32 v32, s56
-; GFX11-NEXT: v_dual_mov_b32 v31, s57 :: v_dual_mov_b32 v26, s47
-; GFX11-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v27, s44
-; GFX11-NEXT: v_dual_mov_b32 v16, s46 :: v_dual_mov_b32 v15, s40
-; GFX11-NEXT: v_dual_mov_b32 v28, s43 :: v_dual_mov_b32 v19, s28
-; GFX11-NEXT: v_dual_mov_b32 v20, s14 :: v_dual_mov_b32 v21, s12
-; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
-; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
+; GFX11-NEXT: v_dual_mov_b32 v96, s49 :: v_dual_mov_b32 v87, s39
+; GFX11-NEXT: v_dual_mov_b32 v86, s48 :: v_dual_mov_b32 v85, s37
+; GFX11-NEXT: v_dual_mov_b32 v84, s38 :: v_dual_mov_b32 v83, s36
+; GFX11-NEXT: v_dual_mov_b32 v82, s34 :: v_dual_mov_b32 v81, s35
+; GFX11-NEXT: v_dual_mov_b32 v71, s31 :: v_dual_mov_b32 v80, s30
+; GFX11-NEXT: v_dual_mov_b32 v70, vcc_hi :: v_dual_mov_b32 v69, s94
+; GFX11-NEXT: v_dual_mov_b32 v68, s95 :: v_dual_mov_b32 v67, s92
+; GFX11-NEXT: v_dual_mov_b32 v66, s93 :: v_dual_mov_b32 v65, s91
+; GFX11-NEXT: v_dual_mov_b32 v64, s89 :: v_dual_mov_b32 v55, s90
+; GFX11-NEXT: v_dual_mov_b32 v53, s88 :: v_dual_mov_b32 v54, s79
+; GFX11-NEXT: v_dual_mov_b32 v52, s78 :: v_dual_mov_b32 v51, s76
+; GFX11-NEXT: v_dual_mov_b32 v50, s77 :: v_dual_mov_b32 v49, s74
+; GFX11-NEXT: v_dual_mov_b32 v48, s75 :: v_dual_mov_b32 v39, s73
+; GFX11-NEXT: v_dual_mov_b32 v38, s63 :: v_dual_mov_b32 v37, s72
+; GFX11-NEXT: v_dual_mov_b32 v35, s62 :: v_dual_mov_b32 v36, s61
+; GFX11-NEXT: v_dual_mov_b32 v34, s60 :: v_dual_mov_b32 v33, s58
+; GFX11-NEXT: v_dual_mov_b32 v32, s59 :: v_dual_mov_b32 v31, s56
+; GFX11-NEXT: v_dual_mov_b32 v30, s57 :: v_dual_mov_b32 v29, s47
+; GFX11-NEXT: v_dual_mov_b32 v28, s45 :: v_dual_mov_b32 v27, s46
+; GFX11-NEXT: v_dual_mov_b32 v25, s44 :: v_dual_mov_b32 v26, s43
+; GFX11-NEXT: v_dual_mov_b32 v17, s40 :: v_dual_mov_b32 v18, s28
+; GFX11-NEXT: v_dual_mov_b32 v19, s14 :: v_dual_mov_b32 v20, s12
+; GFX11-NEXT: v_dual_mov_b32 v21, s10 :: v_dual_mov_b32 v22, s8
+; GFX11-NEXT: v_dual_mov_b32 v23, s6 :: v_dual_mov_b32 v24, s4
; GFX11-NEXT: .LBB49_5: ; %end
-; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
-; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
-; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
-; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
-; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
-; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
-; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
-; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
-; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
-; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
-; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
+; GFX11-NEXT: v_perm_b32 v11, v11, v70, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v22, v69, v22, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v12, v68, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v67, v66, v67, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v15, v96, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v87, v24, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v66, v22, 16, v11
+; GFX11-NEXT: v_perm_b32 v9, v9, v65, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v64, v21, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v39, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v19, v38, v19, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v67, v67, 16, v12
+; GFX11-NEXT: v_perm_b32 v10, v10, v55, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v53, v54, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v52, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v51, v20, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v16, v86, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v84, v84, v85, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v83, v13, v83, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v13, v24, 16, v15
+; GFX11-NEXT: v_perm_b32 v15, v82, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v23, v14, v81, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v71, v80, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v8, v8, v50, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v21, v48, v49, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v68, v11, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v9, v19, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v37, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v35, v36, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v69, v12, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v20, 16, v7
+; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v33, v18, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v32, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v30, v31, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v18, v1, v29, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v17, v28, v17, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v19, v2, v27, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v25, v26, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v84, 16, v16
+; GFX11-NEXT: v_lshl_or_b32 v15, v15, 16, v83
+; GFX11-NEXT: v_lshl_or_b32 v16, v24, 16, v23
+; GFX11-NEXT: v_lshl_or_b32 v8, v21, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v10, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v1, v11, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v12, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v17, 16, v18
+; GFX11-NEXT: v_lshl_or_b32 v4, v20, 16, v19
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
-; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
-; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:16
+; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off
+; GFX11-NEXT: scratch_store_b128 v0, v[66:69], off offset:16
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
@@ -29440,98 +29320,80 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
+; GFX9-NEXT: v_perm_b32 v12, v34, v33, s4
+; GFX9-NEXT: v_perm_b32 v13, v32, v31, s4
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX9-NEXT: v_perm_b32 v13, v30, v29, s4
+; GFX9-NEXT: v_perm_b32 v14, v28, v27, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_perm_b32 v14, v26, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v22, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX9-NEXT: v_perm_b32 v15, v19, v18, s4
+; GFX9-NEXT: v_perm_b32 v35, v17, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v35, 16, v15
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -29739,75 +29601,56 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB51_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s72, s63, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s62, s61, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v12, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s44, s43, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s42, s41, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s40, s15, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s14, s13, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s10, s9, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v16, 16, v15
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v52, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v11, 16, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-TRUE16-NEXT: .LBB51_2: ; %cmp.true
@@ -30023,75 +29866,56 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB51_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v36, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s72, s63, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s62, s61, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s43, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s42, s41, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s40, s15, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s14, s13, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s10, s9, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v16, 16, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s8, s7, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s4, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-FAKE16-NEXT: .LBB51_2: ; %cmp.true
@@ -39791,118 +39615,102 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX9-NEXT: s_lshr_b32 s54, s16, 16
; GFX9-NEXT: s_lshr_b32 s55, s16, 8
; GFX9-NEXT: .LBB69_3: ; %end
+; GFX9-NEXT: v_mov_b32_e32 v1, s55
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v3, s44
-; GFX9-NEXT: v_mov_b32_e32 v1, s55
-; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
; GFX9-NEXT: v_perm_b32 v1, s16, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s51
+; GFX9-NEXT: v_perm_b32 v3, s54, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GFX9-NEXT: v_mov_b32_e32 v1, s53
-; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s51
; GFX9-NEXT: v_perm_b32 v1, s17, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s42
+; GFX9-NEXT: v_perm_b32 v3, s52, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: v_mov_b32_e32 v1, s50
-; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s42
; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s38
+; GFX9-NEXT: v_perm_b32 v3, s49, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_mov_b32_e32 v1, s48
-; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s38
; GFX9-NEXT: v_perm_b32 v1, s19, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s40
+; GFX9-NEXT: v_perm_b32 v3, s39, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
; GFX9-NEXT: v_mov_b32_e32 v1, s37
-; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s40
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s31
+; GFX9-NEXT: v_perm_b32 v3, s36, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_mov_b32_e32 v1, s35
-; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s31
; GFX9-NEXT: v_perm_b32 v1, s21, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s14
+; GFX9-NEXT: v_perm_b32 v3, s34, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
; GFX9-NEXT: v_mov_b32_e32 v1, s30
-; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s14
; GFX9-NEXT: v_perm_b32 v1, s22, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s92
+; GFX9-NEXT: v_perm_b32 v3, s95, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_mov_b32_e32 v1, s94
-; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s92
; GFX9-NEXT: v_perm_b32 v1, s23, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s12
+; GFX9-NEXT: v_perm_b32 v3, s93, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
; GFX9-NEXT: v_mov_b32_e32 v1, s91
-; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s12
; GFX9-NEXT: v_perm_b32 v1, s24, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s79
+; GFX9-NEXT: v_perm_b32 v3, s90, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_mov_b32_e32 v1, s89
-; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s79
; GFX9-NEXT: v_perm_b32 v1, s25, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s10
+; GFX9-NEXT: v_perm_b32 v3, s88, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: v_mov_b32_e32 v1, s78
-; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s10
; GFX9-NEXT: v_perm_b32 v1, s26, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s74
+; GFX9-NEXT: v_perm_b32 v3, s77, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_mov_b32_e32 v1, s76
-; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s74
; GFX9-NEXT: v_perm_b32 v1, s27, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-NEXT: v_perm_b32 v3, s75, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: v_mov_b32_e32 v1, s73
-; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_perm_b32 v1, s28, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s61
+; GFX9-NEXT: v_perm_b32 v3, s72, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_mov_b32_e32 v1, s63
-; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s61
; GFX9-NEXT: v_perm_b32 v1, s29, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s6
+; GFX9-NEXT: v_perm_b32 v3, s62, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: v_mov_b32_e32 v1, s60
-; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s6
; GFX9-NEXT: v_perm_b32 v1, s4, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s59, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_mov_b32_e32 v1, s58
; GFX9-NEXT: v_mov_b32_e32 v3, s56
; GFX9-NEXT: v_perm_b32 v1, s5, v1, v2
; GFX9-NEXT: v_perm_b32 v2, s57, v3, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: v_readlane_b32 s30, v4, 14
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: v_readlane_b32 s31, v4, 15
@@ -39996,35 +39804,35 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB69_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
-; GFX11-NEXT: s_lshr_b32 s44, s27, 16
-; GFX11-NEXT: s_lshr_b32 s43, s27, 8
-; GFX11-NEXT: s_lshr_b32 s46, s26, 16
-; GFX11-NEXT: s_lshr_b32 s45, s26, 8
-; GFX11-NEXT: s_lshr_b32 s56, s25, 24
-; GFX11-NEXT: s_lshr_b32 s57, s25, 16
-; GFX11-NEXT: s_lshr_b32 s47, s25, 8
-; GFX11-NEXT: s_lshr_b32 s59, s24, 16
-; GFX11-NEXT: s_lshr_b32 s58, s24, 8
-; GFX11-NEXT: s_lshr_b32 s61, s23, 24
-; GFX11-NEXT: s_lshr_b32 s62, s23, 16
-; GFX11-NEXT: s_lshr_b32 s60, s23, 8
-; GFX11-NEXT: s_lshr_b32 s72, s22, 16
-; GFX11-NEXT: s_lshr_b32 s63, s22, 8
-; GFX11-NEXT: s_lshr_b32 s74, s21, 24
-; GFX11-NEXT: s_lshr_b32 s75, s21, 16
-; GFX11-NEXT: s_lshr_b32 s73, s21, 8
-; GFX11-NEXT: s_lshr_b32 s77, s20, 16
-; GFX11-NEXT: s_lshr_b32 s76, s20, 8
+; GFX11-NEXT: s_lshr_b32 s43, s27, 16
+; GFX11-NEXT: s_lshr_b32 s44, s27, 8
+; GFX11-NEXT: s_lshr_b32 s45, s26, 16
+; GFX11-NEXT: s_lshr_b32 s46, s26, 8
+; GFX11-NEXT: s_lshr_b32 s47, s25, 24
+; GFX11-NEXT: s_lshr_b32 s56, s25, 16
+; GFX11-NEXT: s_lshr_b32 s57, s25, 8
+; GFX11-NEXT: s_lshr_b32 s58, s24, 16
+; GFX11-NEXT: s_lshr_b32 s59, s24, 8
+; GFX11-NEXT: s_lshr_b32 s60, s23, 24
+; GFX11-NEXT: s_lshr_b32 s61, s23, 16
+; GFX11-NEXT: s_lshr_b32 s62, s23, 8
+; GFX11-NEXT: s_lshr_b32 s63, s22, 16
+; GFX11-NEXT: s_lshr_b32 s72, s22, 8
+; GFX11-NEXT: s_lshr_b32 s73, s21, 24
+; GFX11-NEXT: s_lshr_b32 s74, s21, 16
+; GFX11-NEXT: s_lshr_b32 s75, s21, 8
+; GFX11-NEXT: s_lshr_b32 s76, s20, 16
+; GFX11-NEXT: s_lshr_b32 s77, s20, 8
; GFX11-NEXT: s_lshr_b32 s78, s19, 24
-; GFX11-NEXT: s_lshr_b32 s88, s19, 16
-; GFX11-NEXT: s_lshr_b32 s79, s19, 8
-; GFX11-NEXT: s_lshr_b32 s90, s18, 16
-; GFX11-NEXT: s_lshr_b32 s89, s18, 8
-; GFX11-NEXT: s_lshr_b32 s92, s17, 24
-; GFX11-NEXT: s_lshr_b32 s93, s17, 16
-; GFX11-NEXT: s_lshr_b32 s91, s17, 8
-; GFX11-NEXT: s_lshr_b32 s95, s16, 16
-; GFX11-NEXT: s_lshr_b32 s94, s16, 8
+; GFX11-NEXT: s_lshr_b32 s79, s19, 16
+; GFX11-NEXT: s_lshr_b32 s88, s19, 8
+; GFX11-NEXT: s_lshr_b32 s89, s18, 16
+; GFX11-NEXT: s_lshr_b32 s90, s18, 8
+; GFX11-NEXT: s_lshr_b32 s91, s17, 24
+; GFX11-NEXT: s_lshr_b32 s92, s17, 16
+; GFX11-NEXT: s_lshr_b32 s93, s17, 8
+; GFX11-NEXT: s_lshr_b32 s94, s16, 16
+; GFX11-NEXT: s_lshr_b32 s95, s16, 8
; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 24
; GFX11-NEXT: s_lshr_b32 s30, s3, 16
; GFX11-NEXT: s_lshr_b32 s31, s3, 8
@@ -40071,35 +39879,35 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: s_lshr_b64 s[28:29], s[2:3], 24
; GFX11-NEXT: s_lshr_b64 s[40:41], s[0:1], 24
; GFX11-NEXT: s_lshr_b32 s42, s27, 24
-; GFX11-NEXT: s_lshr_b32 s44, s27, 16
-; GFX11-NEXT: s_lshr_b32 s43, s27, 8
-; GFX11-NEXT: s_lshr_b32 s46, s26, 16
-; GFX11-NEXT: s_lshr_b32 s45, s26, 8
-; GFX11-NEXT: s_lshr_b32 s56, s25, 24
-; GFX11-NEXT: s_lshr_b32 s57, s25, 16
-; GFX11-NEXT: s_lshr_b32 s47, s25, 8
-; GFX11-NEXT: s_lshr_b32 s59, s24, 16
-; GFX11-NEXT: s_lshr_b32 s58, s24, 8
-; GFX11-NEXT: s_lshr_b32 s61, s23, 24
-; GFX11-NEXT: s_lshr_b32 s62, s23, 16
-; GFX11-NEXT: s_lshr_b32 s60, s23, 8
-; GFX11-NEXT: s_lshr_b32 s72, s22, 16
-; GFX11-NEXT: s_lshr_b32 s63, s22, 8
-; GFX11-NEXT: s_lshr_b32 s74, s21, 24
-; GFX11-NEXT: s_lshr_b32 s75, s21, 16
-; GFX11-NEXT: s_lshr_b32 s73, s21, 8
-; GFX11-NEXT: s_lshr_b32 s77, s20, 16
-; GFX11-NEXT: s_lshr_b32 s76, s20, 8
+; GFX11-NEXT: s_lshr_b32 s43, s27, 16
+; GFX11-NEXT: s_lshr_b32 s44, s27, 8
+; GFX11-NEXT: s_lshr_b32 s45, s26, 16
+; GFX11-NEXT: s_lshr_b32 s46, s26, 8
+; GFX11-NEXT: s_lshr_b32 s47, s25, 24
+; GFX11-NEXT: s_lshr_b32 s56, s25, 16
+; GFX11-NEXT: s_lshr_b32 s57, s25, 8
+; GFX11-NEXT: s_lshr_b32 s58, s24, 16
+; GFX11-NEXT: s_lshr_b32 s59, s24, 8
+; GFX11-NEXT: s_lshr_b32 s60, s23, 24
+; GFX11-NEXT: s_lshr_b32 s61, s23, 16
+; GFX11-NEXT: s_lshr_b32 s62, s23, 8
+; GFX11-NEXT: s_lshr_b32 s63, s22, 16
+; GFX11-NEXT: s_lshr_b32 s72, s22, 8
+; GFX11-NEXT: s_lshr_b32 s73, s21, 24
+; GFX11-NEXT: s_lshr_b32 s74, s21, 16
+; GFX11-NEXT: s_lshr_b32 s75, s21, 8
+; GFX11-NEXT: s_lshr_b32 s76, s20, 16
+; GFX11-NEXT: s_lshr_b32 s77, s20, 8
; GFX11-NEXT: s_lshr_b32 s78, s19, 24
-; GFX11-NEXT: s_lshr_b32 s88, s19, 16
-; GFX11-NEXT: s_lshr_b32 s79, s19, 8
-; GFX11-NEXT: s_lshr_b32 s90, s18, 16
-; GFX11-NEXT: s_lshr_b32 s89, s18, 8
-; GFX11-NEXT: s_lshr_b32 s92, s17, 24
-; GFX11-NEXT: s_lshr_b32 s93, s17, 16
-; GFX11-NEXT: s_lshr_b32 s91, s17, 8
-; GFX11-NEXT: s_lshr_b32 s95, s16, 16
-; GFX11-NEXT: s_lshr_b32 s94, s16, 8
+; GFX11-NEXT: s_lshr_b32 s79, s19, 16
+; GFX11-NEXT: s_lshr_b32 s88, s19, 8
+; GFX11-NEXT: s_lshr_b32 s89, s18, 16
+; GFX11-NEXT: s_lshr_b32 s90, s18, 8
+; GFX11-NEXT: s_lshr_b32 s91, s17, 24
+; GFX11-NEXT: s_lshr_b32 s92, s17, 16
+; GFX11-NEXT: s_lshr_b32 s93, s17, 8
+; GFX11-NEXT: s_lshr_b32 s94, s16, 16
+; GFX11-NEXT: s_lshr_b32 s95, s16, 8
; GFX11-NEXT: s_lshr_b32 vcc_hi, s3, 24
; GFX11-NEXT: s_lshr_b32 s30, s3, 16
; GFX11-NEXT: s_lshr_b32 s31, s3, 8
@@ -40112,72 +39920,55 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: s_lshr_b32 s48, s0, 8
; GFX11-NEXT: .LBB69_3: ; %end
; GFX11-NEXT: v_mov_b32_e32 v12, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_perm_b32 v5, s34, s28, v12
-; GFX11-NEXT: v_readlane_b32 s34, v23, 0
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
-; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_perm_b32 v1, s0, s48, v12
+; GFX11-NEXT: v_perm_b32 v2, s39, s40, v12
; GFX11-NEXT: v_perm_b32 v3, s1, s38, v12
-; GFX11-NEXT: v_perm_b32 v6, s2, s35, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-NEXT: v_perm_b32 v8, s30, vcc_hi, v12
-; GFX11-NEXT: v_perm_b32 v9, s95, s14, v12
-; GFX11-NEXT: v_perm_b32 v10, s17, s91, v12
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-NEXT: v_or_b32_e32 v3, v6, v5
-; GFX11-NEXT: v_perm_b32 v5, s93, s92, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v8
-; GFX11-NEXT: v_perm_b32 v6, s16, s94, v12
-; GFX11-NEXT: v_perm_b32 v8, s90, s12, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v5
+; GFX11-NEXT: v_perm_b32 v4, s37, s36, v12
+; GFX11-NEXT: v_perm_b32 v5, s2, s35, v12
+; GFX11-NEXT: v_perm_b32 v6, s34, s28, v12
; GFX11-NEXT: v_perm_b32 v7, s3, s31, v12
-; GFX11-NEXT: v_perm_b32 v13, s18, s89, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_or_b32_e32 v5, v6, v9
-; GFX11-NEXT: v_perm_b32 v9, s88, s78, v12
-; GFX11-NEXT: v_or_b32_e32 v6, v10, v11
-; GFX11-NEXT: v_perm_b32 v10, s77, s10, v12
-; GFX11-NEXT: v_perm_b32 v11, s75, s74, v12
-; GFX11-NEXT: v_perm_b32 v14, s72, s8, v12
-; GFX11-NEXT: v_or_b32_e32 v4, v7, v4
-; GFX11-NEXT: v_or_b32_e32 v7, v13, v8
-; GFX11-NEXT: v_perm_b32 v8, s19, s79, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v13, s20, s76, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v15, s21, s73, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_perm_b32 v16, s22, s63, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v9
-; GFX11-NEXT: v_or_b32_e32 v9, v13, v10
-; GFX11-NEXT: v_perm_b32 v13, s62, s61, v12
-; GFX11-NEXT: v_or_b32_e32 v10, v15, v11
-; GFX11-NEXT: v_or_b32_e32 v11, v16, v14
-; GFX11-NEXT: v_perm_b32 v14, s59, s6, v12
-; GFX11-NEXT: v_perm_b32 v17, s57, s56, v12
-; GFX11-NEXT: v_perm_b32 v18, s46, s4, v12
-; GFX11-NEXT: v_perm_b32 v20, s44, s42, v12
-; GFX11-NEXT: v_perm_b32 v15, s23, s60, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-NEXT: v_perm_b32 v16, s24, s58, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v19, s25, s47, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT: v_perm_b32 v21, s26, s45, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v22, s27, s43, v12
-; GFX11-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-NEXT: v_or_b32_e32 v12, v15, v13
-; GFX11-NEXT: v_or_b32_e32 v13, v16, v14
-; GFX11-NEXT: v_or_b32_e32 v14, v19, v17
-; GFX11-NEXT: v_or_b32_e32 v15, v21, v18
-; GFX11-NEXT: v_or_b32_e32 v16, v22, v20
+; GFX11-NEXT: v_perm_b32 v8, s30, vcc_hi, v12
+; GFX11-NEXT: v_perm_b32 v9, s16, s95, v12
+; GFX11-NEXT: v_perm_b32 v10, s94, s14, v12
+; GFX11-NEXT: v_perm_b32 v11, s17, s93, v12
+; GFX11-NEXT: v_perm_b32 v13, s92, s91, v12
+; GFX11-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v3, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v4, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v5, v10, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v6, v13, 16, v11
+; GFX11-NEXT: v_perm_b32 v7, s18, s90, v12
+; GFX11-NEXT: v_perm_b32 v8, s89, s12, v12
+; GFX11-NEXT: v_perm_b32 v9, s19, s88, v12
+; GFX11-NEXT: v_perm_b32 v10, s79, s78, v12
+; GFX11-NEXT: v_perm_b32 v11, s20, s77, v12
+; GFX11-NEXT: v_perm_b32 v13, s76, s10, v12
+; GFX11-NEXT: v_perm_b32 v14, s21, s75, v12
+; GFX11-NEXT: v_perm_b32 v15, s74, s73, v12
+; GFX11-NEXT: v_perm_b32 v16, s22, s72, v12
+; GFX11-NEXT: v_perm_b32 v17, s63, s8, v12
+; GFX11-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v8, v10, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v9, v13, 16, v11
+; GFX11-NEXT: v_lshl_or_b32 v10, v15, 16, v14
+; GFX11-NEXT: v_perm_b32 v13, s23, s62, v12
+; GFX11-NEXT: v_perm_b32 v14, s61, s60, v12
+; GFX11-NEXT: v_lshl_or_b32 v11, v17, 16, v16
+; GFX11-NEXT: v_perm_b32 v15, s24, s59, v12
+; GFX11-NEXT: v_perm_b32 v16, s58, s6, v12
+; GFX11-NEXT: v_perm_b32 v17, s25, s57, v12
+; GFX11-NEXT: v_perm_b32 v18, s56, s47, v12
+; GFX11-NEXT: v_perm_b32 v19, s26, s46, v12
+; GFX11-NEXT: v_perm_b32 v20, s45, s4, v12
+; GFX11-NEXT: v_perm_b32 v21, s27, s44, v12
+; GFX11-NEXT: v_perm_b32 v22, s43, s42, v12
+; GFX11-NEXT: v_lshl_or_b32 v12, v14, 16, v13
+; GFX11-NEXT: v_lshl_or_b32 v13, v16, 16, v15
+; GFX11-NEXT: v_lshl_or_b32 v14, v18, 16, v17
+; GFX11-NEXT: v_lshl_or_b32 v15, v20, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v16, v22, 16, v21
; GFX11-NEXT: v_readlane_b32 s30, v23, 7
; GFX11-NEXT: s_clause 0x3
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off
@@ -40191,6 +39982,7 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: v_readlane_b32 s37, v23, 3
; GFX11-NEXT: v_readlane_b32 s36, v23, 2
; GFX11-NEXT: v_readlane_b32 s35, v23, 1
+; GFX11-NEXT: v_readlane_b32 s34, v23, 0
; GFX11-NEXT: s_xor_saveexec_b32 s0, -1
; GFX11-NEXT: scratch_load_b32 v23, off, s32 ; 4-byte Folded Reload
; GFX11-NEXT: s_mov_b32 exec_lo, s0
@@ -40209,41 +40001,41 @@ define inreg <64 x i8> @bitcast_v8i64_to_v64i8_scalar(<8 x i64> inreg %a, i32 in
; GFX11-NEXT: ; implicit-def: $sgpr31
; GFX11-NEXT: ; implicit-def: $sgpr30
; GFX11-NEXT: ; implicit-def: $vcc_hi
-; GFX11-NEXT: ; implicit-def: $sgpr94
; GFX11-NEXT: ; implicit-def: $sgpr95
+; GFX11-NEXT: ; implicit-def: $sgpr94
; GFX11-NEXT: ; implicit-def: $sgpr14
-; GFX11-NEXT: ; implicit-def: $sgpr91
; GFX11-NEXT: ; implicit-def: $sgpr93
; GFX11-NEXT: ; implicit-def: $sgpr92
-; GFX11-NEXT: ; implicit-def: $sgpr89
+; GFX11-NEXT: ; implicit-def: $sgpr91
; GFX11-NEXT: ; implicit-def: $sgpr90
+; GFX11-NEXT: ; implicit-def: $sgpr89
; GFX11-NEXT: ; implicit-def: $sgpr12
-; GFX11-NEXT: ; implicit-def: $sgpr79
; GFX11-NEXT: ; implicit-def: $sgpr88
+; GFX11-NEXT: ; implicit-def: $sgpr79
; GFX11-NEXT: ; implicit-def: $sgpr78
-; GFX11-NEXT: ; implicit-def: $sgpr76
; GFX11-NEXT: ; implicit-def: $sgpr77
+; GFX11-NEXT: ; implicit-def: $sgpr76
; GFX11-NEXT: ; implicit-def: $sgpr10
-; GFX11-NEXT: ; implicit-def: $sgpr73
; GFX11-NEXT: ; implicit-def: $sgpr75
; GFX11-NEXT: ; implicit-def: $sgpr74
-; GFX11-NEXT: ; implicit-def: $sgpr63
+; GFX11-NEXT: ; implicit-def: $sgpr73
; GFX11-NEXT: ; implicit-def: $sgpr72
+; GFX11-NEXT: ; implicit-def: $sgpr63
; GFX11-NEXT: ; implicit-def: $sgpr8
-; GFX11-NEXT: ; implicit-def: $sgpr60
; GFX11-NEXT: ; implicit-def: $sgpr62
; GFX11-NEXT: ; implicit-def: $sgpr61
-; GFX11-NEXT: ; implicit-def: $sgpr58
+; GFX11-NEXT: ; implicit-def: $sgpr60
; GFX11-NEXT: ; implicit-def: $sgpr59
+; GFX11-NEXT: ; implicit-def: $sgpr58
; GFX11-NEXT: ; implicit-def: $sgpr6
-; GFX11-NEXT: ; implicit-def: $sgpr47
; GFX11-NEXT: ; implicit-def: $sgpr57
; GFX11-NEXT: ; implicit-def: $sgpr56
-; GFX11-NEXT: ; implicit-def: $sgpr45
+; GFX11-NEXT: ; implicit-def: $sgpr47
; GFX11-NEXT: ; implicit-def: $sgpr46
+; GFX11-NEXT: ; implicit-def: $sgpr45
; GFX11-NEXT: ; implicit-def: $sgpr4
-; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: ; implicit-def: $sgpr44
+; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: ; implicit-def: $sgpr42
; GFX11-NEXT: s_branch .LBB69_2
%cmp = icmp eq i32 %b, 0
@@ -43351,98 +43143,80 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
+; GFX9-NEXT: v_perm_b32 v12, v34, v33, s4
+; GFX9-NEXT: v_perm_b32 v13, v32, v31, s4
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX9-NEXT: v_perm_b32 v13, v30, v29, s4
+; GFX9-NEXT: v_perm_b32 v14, v28, v27, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_perm_b32 v14, v26, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v22, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX9-NEXT: v_perm_b32 v15, v19, v18, s4
+; GFX9-NEXT: v_perm_b32 v35, v17, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v35, 16, v15
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -43650,75 +43424,56 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB71_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s72, s63, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s62, s61, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v12, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s44, s43, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s42, s41, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s40, s15, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s14, s13, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s10, s9, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v16, 16, v15
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v52, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v11, 16, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-TRUE16-NEXT: .LBB71_2: ; %cmp.true
@@ -43934,75 +43689,56 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB71_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v36, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s72, s63, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s62, s61, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s43, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s42, s41, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s40, s15, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s14, s13, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s10, s9, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v16, 16, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s8, s7, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s4, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-FAKE16-NEXT: .LBB71_2: ; %cmp.true
@@ -53039,39 +52775,39 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 8, v11
; GFX9-NEXT: v_lshrrev_b32_e32 v32, 24, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v34, 8, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v35, 8, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v31, 8, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v37, 24, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v38, 24, v4
+; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v4
; GFX9-NEXT: v_lshrrev_b32_e32 v49, 8, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v36, 8, v3
; GFX9-NEXT: v_lshrrev_b32_e32 v52, 24, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v6
; GFX9-NEXT: v_lshrrev_b32_e32 v54, 8, v6
-; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v5
-; GFX9-NEXT: v_lshrrev_b32_e32 v48, 8, v5
-; GFX9-NEXT: v_lshrrev_b32_e32 v55, 24, v8
-; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v8
-; GFX9-NEXT: v_lshrrev_b32_e32 v41, 8, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v5
+; GFX9-NEXT: v_lshrrev_b32_e32 v39, 8, v5
+; GFX9-NEXT: v_lshrrev_b32_e32 v40, 24, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v42, 8, v8
; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v51, 8, v7
; GFX9-NEXT: v_lshrrev_b32_e32 v44, 24, v10
-; GFX9-NEXT: v_lshrrev_b32_e32 v45, 16, v10
-; GFX9-NEXT: v_lshrrev_b32_e32 v46, 8, v10
-; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v10
+; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v10
+; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v9
; GFX9-NEXT: v_lshrrev_b32_e32 v43, 8, v9
-; GFX9-NEXT: v_lshrrev_b32_e32 v58, 24, v14
+; GFX9-NEXT: v_lshrrev_b32_e32 v59, 24, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v60, 16, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 8, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v13
-; GFX9-NEXT: v_lshrrev_b32_e32 v47, 8, v13
+; GFX9-NEXT: v_lshrrev_b32_e32 v45, 8, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v62, 24, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v18, 8, v16
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 16, v15
-; GFX9-NEXT: v_lshrrev_b32_e32 v59, 8, v15
+; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v15
; GFX9-NEXT: s_branch .LBB85_5
; GFX9-NEXT: .LBB85_3:
; GFX9-NEXT: ; implicit-def: $sgpr54
@@ -53147,16 +52883,16 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v14, s19
; GFX9-NEXT: v_mov_b32_e32 v16, s17
; GFX9-NEXT: v_mov_b32_e32 v57, s55
-; GFX9-NEXT: v_mov_b32_e32 v59, s54
+; GFX9-NEXT: v_mov_b32_e32 v58, s54
; GFX9-NEXT: v_mov_b32_e32 v56, s53
-; GFX9-NEXT: v_mov_b32_e32 v47, s52
-; GFX9-NEXT: v_mov_b32_e32 v42, s51
+; GFX9-NEXT: v_mov_b32_e32 v45, s52
+; GFX9-NEXT: v_mov_b32_e32 v55, s51
; GFX9-NEXT: v_mov_b32_e32 v43, s50
; GFX9-NEXT: v_mov_b32_e32 v50, s49
; GFX9-NEXT: v_mov_b32_e32 v51, s48
-; GFX9-NEXT: v_mov_b32_e32 v38, s39
-; GFX9-NEXT: v_mov_b32_e32 v48, s38
-; GFX9-NEXT: v_mov_b32_e32 v35, s37
+; GFX9-NEXT: v_mov_b32_e32 v37, s39
+; GFX9-NEXT: v_mov_b32_e32 v39, s38
+; GFX9-NEXT: v_mov_b32_e32 v34, s37
; GFX9-NEXT: v_mov_b32_e32 v36, s36
; GFX9-NEXT: v_mov_b32_e32 v30, s35
; GFX9-NEXT: v_mov_b32_e32 v31, s34
@@ -53166,20 +52902,20 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v29, s93
; GFX9-NEXT: v_mov_b32_e32 v32, s92
; GFX9-NEXT: v_mov_b32_e32 v33, s91
-; GFX9-NEXT: v_mov_b32_e32 v34, s90
-; GFX9-NEXT: v_mov_b32_e32 v37, s89
-; GFX9-NEXT: v_mov_b32_e32 v39, s88
+; GFX9-NEXT: v_mov_b32_e32 v35, s90
+; GFX9-NEXT: v_mov_b32_e32 v38, s89
+; GFX9-NEXT: v_mov_b32_e32 v48, s88
; GFX9-NEXT: v_mov_b32_e32 v49, s79
; GFX9-NEXT: v_mov_b32_e32 v52, s78
; GFX9-NEXT: v_mov_b32_e32 v53, s77
; GFX9-NEXT: v_mov_b32_e32 v54, s76
-; GFX9-NEXT: v_mov_b32_e32 v55, s75
-; GFX9-NEXT: v_mov_b32_e32 v40, s74
-; GFX9-NEXT: v_mov_b32_e32 v41, s73
+; GFX9-NEXT: v_mov_b32_e32 v40, s75
+; GFX9-NEXT: v_mov_b32_e32 v41, s74
+; GFX9-NEXT: v_mov_b32_e32 v42, s73
; GFX9-NEXT: v_mov_b32_e32 v44, s72
-; GFX9-NEXT: v_mov_b32_e32 v45, s63
-; GFX9-NEXT: v_mov_b32_e32 v46, s62
-; GFX9-NEXT: v_mov_b32_e32 v58, s61
+; GFX9-NEXT: v_mov_b32_e32 v46, s63
+; GFX9-NEXT: v_mov_b32_e32 v47, s62
+; GFX9-NEXT: v_mov_b32_e32 v59, s61
; GFX9-NEXT: v_mov_b32_e32 v60, s60
; GFX9-NEXT: v_mov_b32_e32 v61, s59
; GFX9-NEXT: v_mov_b32_e32 v62, s58
@@ -53199,55 +52935,45 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: buffer_store_dword v26, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: .LBB85_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v24, v57, v24, s4
-; GFX9-NEXT: v_perm_b32 v15, v15, v59, s4
; GFX9-NEXT: v_perm_b32 v16, v16, v18, s4
; GFX9-NEXT: v_perm_b32 v18, v56, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v23, 16, v24
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v23
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v17, v62, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_or_b32_e32 v15, v16, v15
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v13, v13, v47, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v18
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_perm_b32 v13, v13, v45, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v18, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v61, s4
-; GFX9-NEXT: v_perm_b32 v14, v60, v58, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_perm_b32 v14, v60, v59, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v13, v42, v22, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v43, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v13
+; GFX9-NEXT: v_perm_b32 v13, v55, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v13, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: v_perm_b32 v9, v10, v46, s4
-; GFX9-NEXT: v_perm_b32 v10, v45, v44, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v9, v10, v47, s4
+; GFX9-NEXT: v_perm_b32 v10, v46, v44, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v9, v50, v21, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v51, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v50, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: v_perm_b32 v7, v8, v41, s4
-; GFX9-NEXT: v_perm_b32 v8, v40, v55, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v7, v8, v42, s4
+; GFX9-NEXT: v_perm_b32 v8, v41, v40, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_perm_b32 v24, v57, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v15, v58, s4
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
-; GFX9-NEXT: v_perm_b32 v5, v5, v48, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
+; GFX9-NEXT: v_perm_b32 v7, v37, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v24, 16, v15
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v17, v62, s4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v5, v6, v54, s4
; GFX9-NEXT: v_perm_b32 v6, v53, v52, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:36
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -53271,40 +52997,34 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_perm_b32 v5, v35, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_perm_b32 v5, v34, v5, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v3, v4, v49, s4
-; GFX9-NEXT: v_perm_b32 v4, v39, v37, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, v48, v38, s4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v30, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
-; GFX9-NEXT: v_perm_b32 v1, v2, v34, s4
+; GFX9-NEXT: v_perm_b32 v1, v2, v35, s4
; GFX9-NEXT: v_perm_b32 v2, v33, v32, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: v_perm_b32 v1, v11, v27, s4
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v2, v26, v2, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
-; GFX9-NEXT: v_perm_b32 v2, v28, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v12, v29, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, v28, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -53398,62 +53118,62 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-NEXT: s_cbranch_vccnz .LBB85_4
; GFX11-NEXT: .LBB85_2: ; %cmp.true
+; GFX11-NEXT: v_add_f64 v[5:6], s[22:23], 1.0
; GFX11-NEXT: v_add_f64 v[7:8], s[20:21], 1.0
-; GFX11-NEXT: v_add_f64 v[11:12], s[18:19], 1.0
-; GFX11-NEXT: v_add_f64 v[15:16], s[16:17], 1.0
-; GFX11-NEXT: v_add_f64 v[17:18], s[2:3], 1.0
+; GFX11-NEXT: v_add_f64 v[9:10], s[18:19], 1.0
+; GFX11-NEXT: v_add_f64 v[11:12], s[16:17], 1.0
; GFX11-NEXT: v_add_f64 v[1:2], s[26:27], 1.0
+; GFX11-NEXT: v_add_f64 v[16:17], s[2:3], 1.0
; GFX11-NEXT: v_add_f64 v[3:4], s[24:25], 1.0
-; GFX11-NEXT: v_add_f64 v[5:6], s[22:23], 1.0
-; GFX11-NEXT: v_add_f64 v[21:22], s[0:1], 1.0
-; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[7:8]
-; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[11:12]
-; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[15:16]
-; GFX11-NEXT: v_lshrrev_b64 v[26:27], 24, v[17:18]
-; GFX11-NEXT: v_lshrrev_b64 v[9:10], 24, v[1:2]
-; GFX11-NEXT: v_lshrrev_b64 v[13:14], 24, v[3:4]
-; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[5:6]
-; GFX11-NEXT: v_lshrrev_b64 v[27:28], 24, v[21:22]
-; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v29, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v20, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v14, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v10, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v34, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v3
+; GFX11-NEXT: v_add_f64 v[18:19], s[0:1], 1.0
+; GFX11-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
+; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX11-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
+; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
+; GFX11-NEXT: v_lshrrev_b64 v[13:14], 24, v[1:2]
+; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[16:17]
+; GFX11-NEXT: v_lshrrev_b64 v[14:15], 24, v[3:4]
+; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[18:19]
+; GFX11-NEXT: v_lshrrev_b32_e32 v27, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v28, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v30, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v15, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 24, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v29, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v31, 8, v3
; GFX11-NEXT: v_lshrrev_b32_e32 v38, 24, v6
; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v36, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v35, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v51, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v50, 8, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v49, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v49, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v36, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v52, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v54, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v37, 16, v7
; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v65, 24, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v67, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v66, 8, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v53, 8, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v71, 24, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v70, 8, v16
-; GFX11-NEXT: v_lshrrev_b32_e32 v64, 16, v15
-; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v15
-; GFX11-NEXT: v_lshrrev_b32_e32 v84, 24, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v85, 16, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v68, 8, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v87, 24, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v86, 8, v22
-; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v21
-; GFX11-NEXT: v_lshrrev_b32_e32 v81, 8, v21
+; GFX11-NEXT: v_lshrrev_b32_e32 v65, 24, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v68, 8, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v51, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v80, 24, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v81, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v82, 8, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v55, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v64, 8, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v83, 24, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v85, 8, v17
+; GFX11-NEXT: v_lshrrev_b32_e32 v67, 16, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v69, 8, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v86, 24, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v96, 8, v19
+; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v18
+; GFX11-NEXT: v_lshrrev_b32_e32 v71, 8, v18
; GFX11-NEXT: s_branch .LBB85_5
; GFX11-NEXT: .LBB85_3:
; GFX11-NEXT: ; implicit-def: $sgpr48
@@ -53506,109 +53226,92 @@ define inreg <64 x i8> @bitcast_v8f64_to_v64i8_scalar(<8 x double> inreg %a, i32
; GFX11-NEXT: ; implicit-def: $sgpr90
; GFX11-NEXT: s_branch .LBB85_2
; GFX11-NEXT: .LBB85_4:
-; GFX11-NEXT: v_dual_mov_b32 v21, s0 :: v_dual_mov_b32 v2, s27
-; GFX11-NEXT: v_dual_mov_b32 v17, s2 :: v_dual_mov_b32 v4, s25
-; GFX11-NEXT: v_dual_mov_b32 v15, s16 :: v_dual_mov_b32 v6, s23
-; GFX11-NEXT: v_dual_mov_b32 v11, s18 :: v_dual_mov_b32 v8, s21
-; GFX11-NEXT: v_dual_mov_b32 v7, s20 :: v_dual_mov_b32 v12, s19
-; GFX11-NEXT: v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v16, s17
-; GFX11-NEXT: v_dual_mov_b32 v3, s24 :: v_dual_mov_b32 v18, s3
-; GFX11-NEXT: v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v22, s1
-; GFX11-NEXT: v_dual_mov_b32 v82, s49 :: v_dual_mov_b32 v81, s48
-; GFX11-NEXT: v_dual_mov_b32 v69, s39 :: v_dual_mov_b32 v68, s38
-; GFX11-NEXT: v_dual_mov_b32 v64, s37 :: v_dual_mov_b32 v55, s36
-; GFX11-NEXT: v_dual_mov_b32 v54, s35 :: v_dual_mov_b32 v53, s34
-; GFX11-NEXT: v_dual_mov_b32 v49, s31 :: v_dual_mov_b32 v30, s93
-; GFX11-NEXT: v_dual_mov_b32 v39, s30 :: v_dual_mov_b32 v14, s92
-; GFX11-NEXT: v_dual_mov_b32 v37, vcc_hi :: v_dual_mov_b32 v10, s91
-; GFX11-NEXT: v_dual_mov_b32 v35, s95 :: v_dual_mov_b32 v26, s6
-; GFX11-NEXT: v_dual_mov_b32 v31, s94 :: v_dual_mov_b32 v24, s10
-; GFX11-NEXT: v_dual_mov_b32 v27, s4 :: v_dual_mov_b32 v28, s90
-; GFX11-NEXT: v_dual_mov_b32 v25, s8 :: v_dual_mov_b32 v20, s88
-; GFX11-NEXT: v_dual_mov_b32 v23, s12 :: v_dual_mov_b32 v34, s78
-; GFX11-NEXT: v_dual_mov_b32 v19, s14 :: v_dual_mov_b32 v32, s77
-; GFX11-NEXT: v_dual_mov_b32 v13, s28 :: v_dual_mov_b32 v38, s76
-; GFX11-NEXT: v_dual_mov_b32 v9, s40 :: v_dual_mov_b32 v48, s75
-; GFX11-NEXT: v_dual_mov_b32 v29, s89 :: v_dual_mov_b32 v36, s74
-; GFX11-NEXT: v_dual_mov_b32 v33, s79 :: v_dual_mov_b32 v52, s72
-; GFX11-NEXT: v_dual_mov_b32 v51, s73 :: v_dual_mov_b32 v50, s63
-; GFX11-NEXT: v_dual_mov_b32 v65, s62 :: v_dual_mov_b32 v66, s60
-; GFX11-NEXT: v_dual_mov_b32 v67, s61 :: v_dual_mov_b32 v80, s58
-; GFX11-NEXT: v_dual_mov_b32 v71, s59 :: v_dual_mov_b32 v70, s57
-; GFX11-NEXT: v_dual_mov_b32 v84, s56 :: v_dual_mov_b32 v85, s47
-; GFX11-NEXT: v_dual_mov_b32 v83, s46 :: v_dual_mov_b32 v96, s44
-; GFX11-NEXT: v_dual_mov_b32 v87, s45 :: v_dual_mov_b32 v86, s43
+; GFX11-NEXT: v_dual_mov_b32 v18, s0 :: v_dual_mov_b32 v11, s16
+; GFX11-NEXT: v_dual_mov_b32 v16, s2 :: v_dual_mov_b32 v9, s18
+; GFX11-NEXT: v_dual_mov_b32 v7, s20 :: v_dual_mov_b32 v2, s27
+; GFX11-NEXT: v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v4, s25
+; GFX11-NEXT: v_dual_mov_b32 v3, s24 :: v_dual_mov_b32 v6, s23
+; GFX11-NEXT: v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v8, s21
+; GFX11-NEXT: v_dual_mov_b32 v10, s19 :: v_dual_mov_b32 v17, s3
+; GFX11-NEXT: v_dual_mov_b32 v12, s17 :: v_dual_mov_b32 v19, s1
+; GFX11-NEXT: v_dual_mov_b32 v70, s49 :: v_dual_mov_b32 v71, s48
+; GFX11-NEXT: v_dual_mov_b32 v67, s39 :: v_dual_mov_b32 v64, s36
+; GFX11-NEXT: v_dual_mov_b32 v69, s38 :: v_dual_mov_b32 v50, s35
+; GFX11-NEXT: v_dual_mov_b32 v55, s37 :: v_dual_mov_b32 v36, s95
+; GFX11-NEXT: v_dual_mov_b32 v51, s34 :: v_dual_mov_b32 v26, s91
+; GFX11-NEXT: v_dual_mov_b32 v37, s31 :: v_dual_mov_b32 v24, s6
+; GFX11-NEXT: v_dual_mov_b32 v39, s30 :: v_dual_mov_b32 v22, s10
+; GFX11-NEXT: v_dual_mov_b32 v35, vcc_hi :: v_dual_mov_b32 v20, s14
+; GFX11-NEXT: v_dual_mov_b32 v29, s94 :: v_dual_mov_b32 v14, s28
+; GFX11-NEXT: v_dual_mov_b32 v31, s93 :: v_dual_mov_b32 v28, s89
+; GFX11-NEXT: v_dual_mov_b32 v15, s92 :: v_dual_mov_b32 v30, s88
+; GFX11-NEXT: v_dual_mov_b32 v25, s4 :: v_dual_mov_b32 v32, s79
+; GFX11-NEXT: v_dual_mov_b32 v23, s8 :: v_dual_mov_b32 v34, s77
+; GFX11-NEXT: v_dual_mov_b32 v21, s12 :: v_dual_mov_b32 v38, s76
+; GFX11-NEXT: v_dual_mov_b32 v13, s40 :: v_dual_mov_b32 v48, s75
+; GFX11-NEXT: v_dual_mov_b32 v27, s90 :: v_dual_mov_b32 v52, s73
+; GFX11-NEXT: v_dual_mov_b32 v33, s78 :: v_dual_mov_b32 v54, s63
+; GFX11-NEXT: v_dual_mov_b32 v49, s74 :: v_dual_mov_b32 v66, s61
+; GFX11-NEXT: v_dual_mov_b32 v53, s72 :: v_dual_mov_b32 v68, s60
+; GFX11-NEXT: v_dual_mov_b32 v65, s62 :: v_dual_mov_b32 v80, s59
+; GFX11-NEXT: v_dual_mov_b32 v81, s58 :: v_dual_mov_b32 v82, s57
+; GFX11-NEXT: v_dual_mov_b32 v83, s56 :: v_dual_mov_b32 v84, s47
+; GFX11-NEXT: v_dual_mov_b32 v85, s46 :: v_dual_mov_b32 v86, s45
+; GFX11-NEXT: v_dual_mov_b32 v87, s44 :: v_dual_mov_b32 v96, s43
; GFX11-NEXT: .LBB85_5: ; %end
-; GFX11-NEXT: v_perm_b32 v26, v69, v26, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v27, v82, v27, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v82, v96, v87, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v17, v17, v68, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v21, v21, v81, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-NEXT: v_perm_b32 v68, v85, v84, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v24, v54, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v22, v22, v86, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v69, 16, v82
-; GFX11-NEXT: v_or_b32_e32 v86, v17, v26
-; GFX11-NEXT: v_perm_b32 v17, v18, v83, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v64, v25, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v84, v21, v27
-; GFX11-NEXT: v_lshlrev_b32_e32 v21, 16, v68
-; GFX11-NEXT: v_perm_b32 v11, v11, v53, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_or_b32_e32 v85, v22, v69
-; GFX11-NEXT: v_perm_b32 v22, v80, v71, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v15, v55, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v87, v17, v21
-; GFX11-NEXT: v_or_b32_e32 v17, v11, v24
-; GFX11-NEXT: v_perm_b32 v11, v12, v66, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v12, v49, v23, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v16, v16, v70, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_or_b32_e32 v15, v15, v18
-; GFX11-NEXT: v_perm_b32 v18, v67, v65, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v21, v52, v51, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v19, v37, v19, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v11, v64, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v23, v55, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v12, v82, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v55, v81, v80, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v18, v18, v71, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v70, v25, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v80, v23, 16, v11
+; GFX11-NEXT: v_perm_b32 v9, v9, v51, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v50, v22, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v36, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v35, v20, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v81, v55, 16, v12
+; GFX11-NEXT: v_perm_b32 v10, v10, v68, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v66, v65, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v19, v19, v96, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v70, v87, v86, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v69, v16, v69, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v16, v25, 16, v18
+; GFX11-NEXT: v_perm_b32 v18, v67, v24, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v17, v85, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v25, v84, v83, 0xc0c0004
; GFX11-NEXT: v_perm_b32 v7, v7, v39, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-NEXT: v_or_b32_e32 v16, v16, v22
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_perm_b32 v8, v8, v50, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v21
-; GFX11-NEXT: v_perm_b32 v5, v5, v35, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-NEXT: v_or_b32_e32 v21, v7, v12
-; GFX11-NEXT: v_perm_b32 v7, v48, v38, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v18, v11, v18
-; GFX11-NEXT: v_or_b32_e32 v22, v8, v22
-; GFX11-NEXT: v_or_b32_e32 v23, v5, v19
-; GFX11-NEXT: v_perm_b32 v5, v31, v13, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v8, v34, v33, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v9, v14, v9, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v11, v29, v28, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v36, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-NEXT: v_perm_b32 v3, v3, v30, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v32, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-NEXT: v_perm_b32 v10, v1, v10, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-NEXT: v_perm_b32 v12, v2, v20, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-NEXT: v_or_b32_e32 v24, v6, v7
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v8
-; GFX11-NEXT: v_or_b32_e32 v3, v10, v9
-; GFX11-NEXT: v_or_b32_e32 v4, v12, v11
+; GFX11-NEXT: v_perm_b32 v21, v37, v21, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v8, v8, v54, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v22, v53, v52, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v82, v11, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v9, v20, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v49, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v48, v38, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v83, v12, 16, v10
+; GFX11-NEXT: v_perm_b32 v3, v3, v31, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v29, v14, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v34, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v33, v32, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v14, v1, v26, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v13, v15, v13, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v2, v30, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v28, v27, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v17, v70, 16, v19
+; GFX11-NEXT: v_lshl_or_b32 v18, v18, 16, v69
+; GFX11-NEXT: v_lshl_or_b32 v19, v25, 16, v24
+; GFX11-NEXT: v_lshl_or_b32 v7, v21, 16, v7
+; GFX11-NEXT: v_lshl_or_b32 v8, v22, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v10, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v1, v11, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v12, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v13, 16, v14
+; GFX11-NEXT: v_lshl_or_b32 v4, v20, 16, v15
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
-; GFX11-NEXT: scratch_store_b128 v0, v[84:87], off
-; GFX11-NEXT: scratch_store_b128 v0, v[15:18], off offset:16
-; GFX11-NEXT: scratch_store_b128 v0, v[21:24], off offset:32
+; GFX11-NEXT: scratch_store_b128 v0, v[16:19], off
+; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off offset:16
+; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-NEXT: v_readlane_b32 s49, v40, 7
@@ -56729,98 +56432,80 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: s_and_b64 s[4:5], vcc, exec
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v11, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_mov_b32_e32 v2, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v11
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX9-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v2, s25
-; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_mov_b32_e32 v3, s27
; GFX9-NEXT: v_perm_b32 v2, s24, v2, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_mov_b32_e32 v4, s75
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_perm_b32 v3, s26, v3, v11
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: v_mov_b32_e32 v3, s29
-; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_mov_b32_e32 v4, s75
; GFX9-NEXT: v_perm_b32 v3, s28, v3, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_mov_b32_e32 v5, s63
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v4, s76, v4, v11
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s73
-; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_mov_b32_e32 v5, s63
; GFX9-NEXT: v_perm_b32 v4, s74, v4, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_mov_b32_e32 v6, s59
-; GFX9-NEXT: v_or_b32_e32 v4, v4, v5
+; GFX9-NEXT: v_perm_b32 v5, s72, v5, v11
+; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v4
; GFX9-NEXT: v_mov_b32_e32 v5, s61
-; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_mov_b32_e32 v6, s59
; GFX9-NEXT: v_perm_b32 v5, s62, v5, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_mov_b32_e32 v7, s47
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_perm_b32 v6, s60, v6, v11
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
; GFX9-NEXT: v_mov_b32_e32 v6, s57
-; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_mov_b32_e32 v7, s47
; GFX9-NEXT: v_perm_b32 v6, s58, v6, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_mov_b32_e32 v8, s43
-; GFX9-NEXT: v_or_b32_e32 v6, v6, v7
+; GFX9-NEXT: v_perm_b32 v7, s56, v7, v11
+; GFX9-NEXT: v_lshl_or_b32 v6, v7, 16, v6
; GFX9-NEXT: v_mov_b32_e32 v7, s45
-; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_mov_b32_e32 v8, s43
; GFX9-NEXT: v_perm_b32 v7, s46, v7, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_mov_b32_e32 v9, s15
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_perm_b32 v8, s44, v8, v11
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
; GFX9-NEXT: v_mov_b32_e32 v8, s41
-; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_mov_b32_e32 v9, s15
; GFX9-NEXT: v_perm_b32 v8, s42, v8, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_mov_b32_e32 v10, s11
-; GFX9-NEXT: v_or_b32_e32 v8, v8, v9
+; GFX9-NEXT: v_perm_b32 v9, s40, v9, v11
+; GFX9-NEXT: v_lshl_or_b32 v8, v9, 16, v8
; GFX9-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_mov_b32_e32 v10, s11
; GFX9-NEXT: v_perm_b32 v9, s14, v9, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_mov_b32_e32 v12, s7
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_perm_b32 v10, s12, v10, v11
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: v_mov_b32_e32 v10, s9
-; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
+; GFX9-NEXT: v_mov_b32_e32 v12, s7
; GFX9-NEXT: v_perm_b32 v10, s10, v10, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, s8, v12, v11
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX9-NEXT: s_waitcnt vmcnt(17)
-; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v10, v12, 16, v10
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v11, s6, v25, v11
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_perm_b32 v12, v32, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX9-NEXT: v_perm_b32 v12, v23, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v13, v34, v33, s4
-; GFX9-NEXT: v_or_b32_e32 v12, v13, v12
-; GFX9-NEXT: v_perm_b32 v13, v28, v27, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_perm_b32 v14, v30, v29, s4
-; GFX9-NEXT: v_or_b32_e32 v13, v14, v13
-; GFX9-NEXT: v_perm_b32 v14, v22, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_perm_b32 v15, v26, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v14, v15, v14
-; GFX9-NEXT: v_perm_b32 v15, v17, v16, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v35, v19, v18, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v35, v15
+; GFX9-NEXT: v_perm_b32 v12, v34, v33, s4
+; GFX9-NEXT: v_perm_b32 v13, v32, v31, s4
+; GFX9-NEXT: v_lshl_or_b32 v12, v13, 16, v12
+; GFX9-NEXT: v_perm_b32 v13, v30, v29, s4
+; GFX9-NEXT: v_perm_b32 v14, v28, v27, s4
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
+; GFX9-NEXT: v_perm_b32 v14, v26, v24, s4
+; GFX9-NEXT: v_perm_b32 v15, v22, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX9-NEXT: v_perm_b32 v15, v19, v18, s4
+; GFX9-NEXT: v_perm_b32 v35, v17, v16, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v35, 16, v15
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -57028,75 +56713,56 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB87_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s16, s17, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s20, s21, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s28, s29, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s74, s73, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s72, s63, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s62, s61, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v12, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s59, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s60, s59, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, s46, s45, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, s56, s47, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s46, s45, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, s44, s43, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s42, s41, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s40, s15, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s14, s13, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v12, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v15, v13
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v48, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s10, s9, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v12, 16, v10
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v16, 16, v15
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v52, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v48, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v11, 16, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-TRUE16-NEXT: .LBB87_2: ; %cmp.true
@@ -57312,75 +56978,56 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB87_4
; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v11, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v39, v35, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s22, s23, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v35, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v37, v34, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v36, v32, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v33, v31, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s20, s21, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-FAKE16-NEXT: v_perm_b32 v3, s18, s19, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v4, s20, s21, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s74, s73, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s72, s63, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v2, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s62, s61, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s28, s29, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s74, s73, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s72, s63, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s62, s61, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s59, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s58, s57, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v6, s24, s25, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s60, s59, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, s46, s45, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v9, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s42, s41, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s13, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s10, s9, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v6, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v12, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, s56, s47, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s44, s43, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s40, s15, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
+; GFX11-FAKE16-NEXT: v_perm_b32 v8, s56, s47, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s46, s45, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s44, s43, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s42, s41, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s40, s15, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, s14, s13, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v15, s12, s11, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v12, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s6, s5, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v13
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v53, v50, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v48, v38, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s8, s7, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, s10, s9, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v7, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v9, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v12, 16, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v14, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v16, 16, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, s8, s7, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v11, v12
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v14, v13
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v17, v15
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v19, v16
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v20, v18
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, s4, v52, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v53, v50, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v51, v49, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v48, v38, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v11, 16, v12
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v14, 16, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v18, 16, v17
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v16, 16, v15
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v20, 16, v19
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-FAKE16-NEXT: .LBB87_2: ; %cmp.true
@@ -66525,32 +66172,32 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_pk_add_u16 v1, s4, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v8, s25, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v7, s24, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
+; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[5:6]
; GFX9-NEXT: v_pk_add_u16 v10, s23, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v9, s22, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
+; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[7:8]
; GFX9-NEXT: v_pk_add_u16 v12, s21, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v11, s20, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v4, s29, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v3, s28, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[9:10]
; GFX9-NEXT: v_pk_add_u16 v14, s19, 3 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_u16 v13, s18, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4]
-; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
-; GFX9-NEXT: v_pk_add_u16 v19, s17, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_u16 v18, s16, 3 op_sel_hi:[1,0]
-; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[3:4]
+; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[11:12]
+; GFX9-NEXT: v_pk_add_u16 v16, s17, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_u16 v15, s16, 3 op_sel_hi:[1,0]
+; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[25:26], 24, v[18:19]
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[15:16]
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 8, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v1
@@ -66584,11 +66231,11 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v13
-; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v62, 8, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v18
+; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v16
+; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v16
+; GFX9-NEXT: v_lshrrev_b32_e32 v62, 8, v16
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v15
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v15
; GFX9-NEXT: s_branch .LBB97_5
; GFX9-NEXT: .LBB97_3:
; GFX9-NEXT: ; implicit-def: $sgpr55
@@ -66641,13 +66288,13 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: s_branch .LBB97_2
; GFX9-NEXT: .LBB97_4:
-; GFX9-NEXT: v_mov_b32_e32 v20, s44
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v19, s44
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v20, s42
-; GFX9-NEXT: v_mov_b32_e32 v18, s16
-; GFX9-NEXT: v_mov_b32_e32 v19, s17
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v19, s42
+; GFX9-NEXT: v_mov_b32_e32 v15, s16
+; GFX9-NEXT: v_mov_b32_e32 v16, s17
; GFX9-NEXT: v_mov_b32_e32 v13, s18
; GFX9-NEXT: v_mov_b32_e32 v14, s19
; GFX9-NEXT: v_mov_b32_e32 v11, s20
@@ -66662,8 +66309,8 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s5
-; GFX9-NEXT: v_mov_b32_e32 v15, s55
-; GFX9-NEXT: v_mov_b32_e32 v16, s53
+; GFX9-NEXT: v_mov_b32_e32 v17, s55
+; GFX9-NEXT: v_mov_b32_e32 v18, s53
; GFX9-NEXT: v_mov_b32_e32 v62, s54
; GFX9-NEXT: v_mov_b32_e32 v59, s52
; GFX9-NEXT: v_mov_b32_e32 v60, s51
@@ -66700,78 +66347,66 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v29, s60
; GFX9-NEXT: v_mov_b32_e32 v28, s58
; GFX9-NEXT: v_mov_b32_e32 v27, s59
-; GFX9-NEXT: v_mov_b32_e32 v17, s57
+; GFX9-NEXT: v_mov_b32_e32 v25, s57
; GFX9-NEXT: v_mov_b32_e32 v26, s56
-; GFX9-NEXT: v_mov_b32_e32 v22, s12
-; GFX9-NEXT: v_mov_b32_e32 v23, s10
-; GFX9-NEXT: v_mov_b32_e32 v24, s8
-; GFX9-NEXT: v_mov_b32_e32 v25, s6
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v21, s12
+; GFX9-NEXT: v_mov_b32_e32 v22, s10
+; GFX9-NEXT: v_mov_b32_e32 v23, s8
+; GFX9-NEXT: v_mov_b32_e32 v24, s6
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v20, s40
-; GFX9-NEXT: v_mov_b32_e32 v21, s14
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v19, s40
+; GFX9-NEXT: v_mov_b32_e32 v20, s14
; GFX9-NEXT: .LBB97_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
-; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
-; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_perm_b32 v15, v15, v17, s4
+; GFX9-NEXT: v_perm_b32 v17, v61, v23, s4
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v17, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_perm_b32 v13, v45, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_perm_b32 v11, v40, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v51, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_perm_b32 v18, v18, v24, s4
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v38, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v18, 16, v15
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_perm_b32 v16, v16, v62, s4
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -66796,26 +66431,22 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
-; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, v25, v26, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -66909,6 +66540,8 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-NEXT: s_cbranch_vccnz .LBB97_4
; GFX11-NEXT: .LBB97_2: ; %cmp.true
+; GFX11-NEXT: v_pk_add_u16 v2, s27, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v1, s26, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v4, s25, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v3, s24, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v6, s23, 3 op_sel_hi:[1,0]
@@ -66919,60 +66552,58 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX11-NEXT: v_pk_add_u16 v9, s18, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v12, s17, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v11, s16, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
; GFX11-NEXT: v_pk_add_u16 v14, s3, 3 op_sel_hi:[1,0]
; GFX11-NEXT: v_pk_add_u16 v13, s2, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[3:4]
-; GFX11-NEXT: v_pk_add_u16 v18, s1, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v17, s0, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v2, s27, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_pk_add_u16 v1, s26, 3 op_sel_hi:[1,0]
-; GFX11-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
-; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
-; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
-; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
-; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[17:18]
-; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v27, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v16, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v37, 24, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v38, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v51, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v49, 8, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v55, 24, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v53, 8, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v64, 8, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v69, 24, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v65, 8, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v67, 8, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v81, 24, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v71, 8, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v82, 8, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v87, 24, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v85, 8, v17
+; GFX11-NEXT: v_lshrrev_b64 v[18:19], 24, v[3:4]
+; GFX11-NEXT: v_pk_add_u16 v16, s1, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_pk_add_u16 v15, s0, 3 op_sel_hi:[1,0]
+; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[5:6]
+; GFX11-NEXT: v_lshrrev_b64 v[20:21], 24, v[7:8]
+; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[9:10]
+; GFX11-NEXT: v_lshrrev_b64 v[22:23], 24, v[11:12]
+; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14]
+; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[15:16]
+; GFX11-NEXT: v_lshrrev_b32_e32 v26, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v25, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v27, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v28, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v36, 24, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v37, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v49, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v50, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v52, 8, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v54, 24, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v64, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v65, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v67, 24, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v68, 8, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v70, 8, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v80, 24, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v81, 8, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v85, 24, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v86, 8, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v96, 8, v15
; GFX11-NEXT: s_branch .LBB97_5
; GFX11-NEXT: .LBB97_3:
; GFX11-NEXT: ; implicit-def: $sgpr49
@@ -67025,7 +66656,7 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: s_branch .LBB97_2
; GFX11-NEXT: .LBB97_4:
-; GFX11-NEXT: v_dual_mov_b32 v17, s0 :: v_dual_mov_b32 v18, s1
+; GFX11-NEXT: v_dual_mov_b32 v15, s0 :: v_dual_mov_b32 v16, s1
; GFX11-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v14, s3
; GFX11-NEXT: v_dual_mov_b32 v11, s16 :: v_dual_mov_b32 v12, s17
; GFX11-NEXT: v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
@@ -67033,100 +66664,84 @@ define inreg <64 x i8> @bitcast_v32i16_to_v64i8_scalar(<32 x i16> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v6, s23
; GFX11-NEXT: v_dual_mov_b32 v3, s24 :: v_dual_mov_b32 v4, s25
; GFX11-NEXT: v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v2, s27
-; GFX11-NEXT: v_dual_mov_b32 v85, s49 :: v_dual_mov_b32 v96, s39
-; GFX11-NEXT: v_dual_mov_b32 v83, s48 :: v_dual_mov_b32 v86, s38
-; GFX11-NEXT: v_dual_mov_b32 v87, s37 :: v_dual_mov_b32 v82, s36
-; GFX11-NEXT: v_dual_mov_b32 v84, s34 :: v_dual_mov_b32 v71, s35
-; GFX11-NEXT: v_dual_mov_b32 v80, s31 :: v_dual_mov_b32 v81, s30
-; GFX11-NEXT: v_dual_mov_b32 v67, vcc_hi :: v_dual_mov_b32 v70, s94
-; GFX11-NEXT: v_dual_mov_b32 v65, s95 :: v_dual_mov_b32 v68, s93
-; GFX11-NEXT: v_dual_mov_b32 v69, s92 :: v_dual_mov_b32 v64, s91
-; GFX11-NEXT: v_dual_mov_b32 v66, s89 :: v_dual_mov_b32 v53, s90
-; GFX11-NEXT: v_dual_mov_b32 v54, s88 :: v_dual_mov_b32 v55, s79
-; GFX11-NEXT: v_dual_mov_b32 v49, s78 :: v_dual_mov_b32 v52, s76
-; GFX11-NEXT: v_dual_mov_b32 v39, s77 :: v_dual_mov_b32 v50, s75
-; GFX11-NEXT: v_dual_mov_b32 v51, s74 :: v_dual_mov_b32 v38, s73
-; GFX11-NEXT: v_dual_mov_b32 v48, s63 :: v_dual_mov_b32 v37, s61
-; GFX11-NEXT: v_dual_mov_b32 v34, s72 :: v_dual_mov_b32 v33, s60
-; GFX11-NEXT: v_dual_mov_b32 v36, s62 :: v_dual_mov_b32 v35, s58
-; GFX11-NEXT: v_dual_mov_b32 v29, s59 :: v_dual_mov_b32 v32, s56
-; GFX11-NEXT: v_dual_mov_b32 v31, s57 :: v_dual_mov_b32 v26, s47
-; GFX11-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v27, s44
-; GFX11-NEXT: v_dual_mov_b32 v16, s46 :: v_dual_mov_b32 v15, s40
-; GFX11-NEXT: v_dual_mov_b32 v28, s43 :: v_dual_mov_b32 v19, s28
-; GFX11-NEXT: v_dual_mov_b32 v20, s14 :: v_dual_mov_b32 v21, s12
-; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
-; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
+; GFX11-NEXT: v_dual_mov_b32 v96, s49 :: v_dual_mov_b32 v87, s39
+; GFX11-NEXT: v_dual_mov_b32 v86, s48 :: v_dual_mov_b32 v85, s37
+; GFX11-NEXT: v_dual_mov_b32 v84, s38 :: v_dual_mov_b32 v83, s36
+; GFX11-NEXT: v_dual_mov_b32 v82, s34 :: v_dual_mov_b32 v81, s35
+; GFX11-NEXT: v_dual_mov_b32 v71, s31 :: v_dual_mov_b32 v80, s30
+; GFX11-NEXT: v_dual_mov_b32 v70, vcc_hi :: v_dual_mov_b32 v69, s94
+; GFX11-NEXT: v_dual_mov_b32 v68, s95 :: v_dual_mov_b32 v67, s92
+; GFX11-NEXT: v_dual_mov_b32 v66, s93 :: v_dual_mov_b32 v65, s91
+; GFX11-NEXT: v_dual_mov_b32 v64, s89 :: v_dual_mov_b32 v55, s90
+; GFX11-NEXT: v_dual_mov_b32 v53, s88 :: v_dual_mov_b32 v54, s79
+; GFX11-NEXT: v_dual_mov_b32 v52, s78 :: v_dual_mov_b32 v51, s76
+; GFX11-NEXT: v_dual_mov_b32 v50, s77 :: v_dual_mov_b32 v49, s74
+; GFX11-NEXT: v_dual_mov_b32 v48, s75 :: v_dual_mov_b32 v39, s73
+; GFX11-NEXT: v_dual_mov_b32 v38, s63 :: v_dual_mov_b32 v37, s72
+; GFX11-NEXT: v_dual_mov_b32 v35, s62 :: v_dual_mov_b32 v36, s61
+; GFX11-NEXT: v_dual_mov_b32 v34, s60 :: v_dual_mov_b32 v33, s58
+; GFX11-NEXT: v_dual_mov_b32 v32, s59 :: v_dual_mov_b32 v31, s56
+; GFX11-NEXT: v_dual_mov_b32 v30, s57 :: v_dual_mov_b32 v29, s47
+; GFX11-NEXT: v_dual_mov_b32 v28, s45 :: v_dual_mov_b32 v27, s46
+; GFX11-NEXT: v_dual_mov_b32 v25, s44 :: v_dual_mov_b32 v26, s43
+; GFX11-NEXT: v_dual_mov_b32 v17, s40 :: v_dual_mov_b32 v18, s28
+; GFX11-NEXT: v_dual_mov_b32 v19, s14 :: v_dual_mov_b32 v20, s12
+; GFX11-NEXT: v_dual_mov_b32 v21, s10 :: v_dual_mov_b32 v22, s8
+; GFX11-NEXT: v_dual_mov_b32 v23, s6 :: v_dual_mov_b32 v24, s4
; GFX11-NEXT: .LBB97_5: ; %end
-; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
-; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
-; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
-; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
-; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
-; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
-; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
-; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
-; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
-; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
-; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
+; GFX11-NEXT: v_perm_b32 v11, v11, v70, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v22, v69, v22, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v12, v68, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v67, v66, v67, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v15, v96, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v87, v24, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v66, v22, 16, v11
+; GFX11-NEXT: v_perm_b32 v9, v9, v65, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v64, v21, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v39, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v19, v38, v19, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v67, v67, 16, v12
+; GFX11-NEXT: v_perm_b32 v10, v10, v55, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v53, v54, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v52, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v51, v20, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v16, v86, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v84, v84, v85, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v83, v13, v83, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v13, v24, 16, v15
+; GFX11-NEXT: v_perm_b32 v15, v82, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v23, v14, v81, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v71, v80, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v8, v8, v50, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v21, v48, v49, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v68, v11, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v9, v19, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v37, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v35, v36, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v69, v12, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v20, 16, v7
+; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v33, v18, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v32, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v30, v31, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v18, v1, v29, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v17, v28, v17, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v19, v2, v27, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v25, v26, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v84, 16, v16
+; GFX11-NEXT: v_lshl_or_b32 v15, v15, 16, v83
+; GFX11-NEXT: v_lshl_or_b32 v16, v24, 16, v23
+; GFX11-NEXT: v_lshl_or_b32 v8, v21, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v10, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v1, v11, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v12, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v17, 16, v18
+; GFX11-NEXT: v_lshl_or_b32 v4, v20, 16, v19
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
-; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
-; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:16
+; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off
+; GFX11-NEXT: scratch_store_b128 v0, v[66:69], off offset:16
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
@@ -70836,59 +70451,58 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: v_perm_b32 v9, s12, v9, v8
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v16
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v17
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v10, s72, v18, v8
-; GFX9-NEXT: v_or_b32_sdwa v9, v17, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v16, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v10
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v29, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v19
-; GFX9-NEXT: v_or_b32_sdwa v10, v21, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v29
+; GFX9-NEXT: v_lshl_or_b32 v9, v26, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v21
+; GFX9-NEXT: v_lshl_or_b32 v10, v19, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_lshl_or_b32 v12, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v20
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v23
; GFX9-NEXT: v_perm_b32 v10, v31, v28, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v23, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v20, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v13, v9, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v30
-; GFX9-NEXT: v_or_b32_sdwa v9, v33, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v22
-; GFX9-NEXT: v_or_b32_sdwa v10, v25, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v33
+; GFX9-NEXT: v_lshl_or_b32 v9, v30, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v25
+; GFX9-NEXT: v_lshl_or_b32 v10, v22, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_lshl_or_b32 v14, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v24
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v27
; GFX9-NEXT: v_perm_b32 v10, v34, v32, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v27, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v24, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX9-NEXT: s_and_b32 s4, s47, 0xff
; GFX9-NEXT: v_lshl_or_b32 v15, v9, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v9, s58
-; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
-; GFX9-NEXT: s_and_b32 s4, s47, 0xff
; GFX9-NEXT: s_lshl_b32 s5, s7, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s5
+; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX9-NEXT: v_lshl_or_b32 v9, s4, 16, v8
; GFX9-NEXT: s_and_b32 s4, s10, 0xff
+; GFX9-NEXT: v_lshl_or_b32 v9, s5, 16, v8
; GFX9-NEXT: s_lshl_b32 s5, s9, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s8, 0xff
+; GFX9-NEXT: s_or_b32 s5, s5, s4
+; GFX9-NEXT: s_and_b32 s4, s8, 0xff
; GFX9-NEXT: s_lshl_b32 s77, s6, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
+; GFX9-NEXT: s_or_b32 s77, s77, s4
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s77
; GFX9-NEXT: s_and_b32 s5, s63, 0xff
; GFX9-NEXT: s_lshl_b32 s77, s61, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_and_b32 s77, s57, 0xff
+; GFX9-NEXT: s_or_b32 s77, s77, s5
+; GFX9-NEXT: s_and_b32 s5, s57, 0xff
; GFX9-NEXT: s_lshl_b32 s78, s56, 8
-; GFX9-NEXT: s_or_b32 s77, s77, s78
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s77
+; GFX9-NEXT: s_or_b32 s78, s78, s5
+; GFX9-NEXT: s_pack_ll_b32_b16 s5, s77, s78
; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: v_mov_b32_e32 v10, s5
; GFX9-NEXT: s_cbranch_execnz .LBB99_3
@@ -71113,83 +70727,77 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB99_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v49
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s76
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s8, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s8, 8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s78
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s7, v8
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v13, 0xff, v38
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s46, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s73, 0xff
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s79
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s56, 0xff
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s57, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s12, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s76
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v34, 8, v13
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s88, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xff, v37
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v50, 8, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v52
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v36
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v35, 8, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v48, 8, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v32, 8, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, s79
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s77
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s76
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB99_3
; GFX11-TRUE16-NEXT: .LBB99_2: ; %cmp.true
@@ -71376,8 +70984,8 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s41, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v50
+; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s76
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
@@ -71387,83 +70995,76 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s77, s44, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s44, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s46, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s41, 8
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s11, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s40, s13, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s79
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s6, s4, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s7, s5, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s43, s15, v8
+; GFX11-FAKE16-NEXT: s_lshl_b32 s76, s42, 8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s40, s13, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s57, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s78
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s72, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s88, s56, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s89, s62, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s10, s8, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s89, s89, s78
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v6
+; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s45, 8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
+; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s88
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v9, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s76, 16, v12
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v34, 8, s79
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v51
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v35, 8, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v49
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v38, 8, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v39
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v52, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s89, s78
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s61, 0xff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v20
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v31, 8, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v33, 8, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 8, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v10, 16, v14
+; GFX11-FAKE16-NEXT: s_or_b32 s88, s88, s78
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s88, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v19, 16, v20
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v16, 16, v17
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s77
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s76
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB99_3
; GFX11-FAKE16-NEXT: .LBB99_2: ; %cmp.true
@@ -79264,8 +78865,8 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: s_cbranch_execnz .LBB105_4
; GFX9-NEXT: .LBB105_2: ; %cmp.true
; GFX9-NEXT: v_mov_b32_e32 v1, 0x200
-; GFX9-NEXT: v_pk_add_f16 v19, s17, v1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_pk_add_f16 v18, s16, v1 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v16, s17, v1 op_sel_hi:[1,0]
+; GFX9-NEXT: v_pk_add_f16 v15, s16, v1 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v14, s19, v1 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v13, s18, v1 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v12, s21, v1 op_sel_hi:[1,0]
@@ -79280,22 +78881,22 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_pk_add_f16 v3, s28, v1 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v2, s5, v1 op_sel_hi:[1,0]
; GFX9-NEXT: v_pk_add_f16 v1, s4, v1 op_sel_hi:[1,0]
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
-; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
+; GFX9-NEXT: v_lshrrev_b64 v[19:20], 24, v[5:6]
+; GFX9-NEXT: v_lshrrev_b64 v[20:21], 24, v[7:8]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
-; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[3:4]
-; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
-; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
-; GFX9-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[21:22], 24, v[9:10]
+; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[3:4]
+; GFX9-NEXT: v_lshrrev_b64 v[22:23], 24, v[11:12]
+; GFX9-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14]
+; GFX9-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_lshrrev_b64 v[25:26], 24, v[18:19]
+; GFX9-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: v_lshrrev_b64 v[24:25], 24, v[15:16]
; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v2
-; GFX9-NEXT: v_lshrrev_b32_e32 v17, 16, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v25, 16, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v27, 8, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v1
; GFX9-NEXT: v_lshrrev_b32_e32 v29, 8, v1
@@ -79329,11 +78930,11 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v61, 16, v13
; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v13
-; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v62, 8, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v16, 16, v18
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v18
+; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v16
+; GFX9-NEXT: v_lshrrev_b32_e32 v59, 16, v16
+; GFX9-NEXT: v_lshrrev_b32_e32 v62, 8, v16
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 16, v15
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v15
; GFX9-NEXT: s_branch .LBB105_5
; GFX9-NEXT: .LBB105_3:
; GFX9-NEXT: ; implicit-def: $sgpr55
@@ -79386,13 +78987,13 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: ; implicit-def: $sgpr56
; GFX9-NEXT: s_branch .LBB105_2
; GFX9-NEXT: .LBB105_4:
-; GFX9-NEXT: v_mov_b32_e32 v20, s44
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v19, s44
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v20, s42
-; GFX9-NEXT: v_mov_b32_e32 v18, s16
-; GFX9-NEXT: v_mov_b32_e32 v19, s17
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v19, s42
+; GFX9-NEXT: v_mov_b32_e32 v15, s16
+; GFX9-NEXT: v_mov_b32_e32 v16, s17
; GFX9-NEXT: v_mov_b32_e32 v13, s18
; GFX9-NEXT: v_mov_b32_e32 v14, s19
; GFX9-NEXT: v_mov_b32_e32 v11, s20
@@ -79407,8 +79008,8 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v4, s29
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s5
-; GFX9-NEXT: v_mov_b32_e32 v15, s55
-; GFX9-NEXT: v_mov_b32_e32 v16, s53
+; GFX9-NEXT: v_mov_b32_e32 v17, s55
+; GFX9-NEXT: v_mov_b32_e32 v18, s53
; GFX9-NEXT: v_mov_b32_e32 v62, s54
; GFX9-NEXT: v_mov_b32_e32 v59, s52
; GFX9-NEXT: v_mov_b32_e32 v60, s51
@@ -79445,78 +79046,66 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_mov_b32_e32 v29, s60
; GFX9-NEXT: v_mov_b32_e32 v28, s58
; GFX9-NEXT: v_mov_b32_e32 v27, s59
-; GFX9-NEXT: v_mov_b32_e32 v17, s57
+; GFX9-NEXT: v_mov_b32_e32 v25, s57
; GFX9-NEXT: v_mov_b32_e32 v26, s56
-; GFX9-NEXT: v_mov_b32_e32 v22, s12
-; GFX9-NEXT: v_mov_b32_e32 v23, s10
-; GFX9-NEXT: v_mov_b32_e32 v24, s8
-; GFX9-NEXT: v_mov_b32_e32 v25, s6
-; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v21, s12
+; GFX9-NEXT: v_mov_b32_e32 v22, s10
+; GFX9-NEXT: v_mov_b32_e32 v23, s8
+; GFX9-NEXT: v_mov_b32_e32 v24, s6
+; GFX9-NEXT: buffer_store_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
; GFX9-NEXT: s_nop 0
-; GFX9-NEXT: buffer_store_dword v21, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v20, s40
-; GFX9-NEXT: v_mov_b32_e32 v21, s14
+; GFX9-NEXT: buffer_store_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
+; GFX9-NEXT: v_mov_b32_e32 v19, s40
+; GFX9-NEXT: v_mov_b32_e32 v20, s14
; GFX9-NEXT: .LBB105_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v16, v16, v25, s4
-; GFX9-NEXT: v_perm_b32 v15, v18, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v15, v15, v16
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
-; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
-; GFX9-NEXT: v_perm_b32 v18, v19, v62, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX9-NEXT: v_perm_b32 v19, v61, v24, s4
-; GFX9-NEXT: v_or_b32_e32 v15, v18, v15
-; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_perm_b32 v15, v15, v17, s4
+; GFX9-NEXT: v_perm_b32 v17, v61, v23, s4
; GFX9-NEXT: v_perm_b32 v13, v13, v58, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v15, 16, v19
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v15
+; GFX9-NEXT: v_lshl_or_b32 v13, v17, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:8
; GFX9-NEXT: v_perm_b32 v13, v14, v57, s4
; GFX9-NEXT: v_perm_b32 v14, v47, v56, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX9-NEXT: v_or_b32_e32 v13, v13, v14
+; GFX9-NEXT: v_lshl_or_b32 v13, v14, 16, v13
; GFX9-NEXT: buffer_store_dword v13, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v13, v45, v23, s4
; GFX9-NEXT: v_perm_b32 v11, v11, v46, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v13
+; GFX9-NEXT: v_perm_b32 v13, v45, v22, s4
+; GFX9-NEXT: v_lshl_or_b32 v11, v13, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:16
; GFX9-NEXT: v_perm_b32 v11, v12, v44, s4
; GFX9-NEXT: v_perm_b32 v12, v42, v43, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX9-NEXT: v_or_b32_e32 v11, v11, v12
+; GFX9-NEXT: v_lshl_or_b32 v11, v12, 16, v11
; GFX9-NEXT: buffer_store_dword v11, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v11, v40, v22, s4
; GFX9-NEXT: v_perm_b32 v9, v9, v41, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v11
+; GFX9-NEXT: v_perm_b32 v11, v40, v21, s4
+; GFX9-NEXT: v_lshl_or_b32 v9, v11, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:24
; GFX9-NEXT: v_perm_b32 v9, v10, v55, s4
; GFX9-NEXT: v_perm_b32 v10, v53, v54, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX9-NEXT: v_or_b32_e32 v9, v9, v10
+; GFX9-NEXT: v_lshl_or_b32 v9, v10, 16, v9
; GFX9-NEXT: buffer_store_dword v9, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v9, v51, v21, s4
; GFX9-NEXT: v_perm_b32 v7, v7, v52, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v9
+; GFX9-NEXT: v_perm_b32 v9, v51, v20, s4
+; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:32
; GFX9-NEXT: v_perm_b32 v7, v8, v50, s4
; GFX9-NEXT: v_perm_b32 v8, v48, v49, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX9-NEXT: v_or_b32_e32 v7, v7, v8
+; GFX9-NEXT: v_lshl_or_b32 v7, v8, 16, v7
+; GFX9-NEXT: v_perm_b32 v18, v18, v24, s4
; GFX9-NEXT: buffer_store_dword v7, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_perm_b32 v7, v38, v20, s4
; GFX9-NEXT: v_perm_b32 v5, v5, v39, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v7
+; GFX9-NEXT: v_perm_b32 v7, v38, v19, s4
+; GFX9-NEXT: v_lshl_or_b32 v15, v18, 16, v15
+; GFX9-NEXT: v_lshl_or_b32 v5, v7, 16, v5
+; GFX9-NEXT: v_perm_b32 v16, v16, v62, s4
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen
+; GFX9-NEXT: v_perm_b32 v15, v59, v60, s4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:40
; GFX9-NEXT: v_perm_b32 v5, v6, v37, s4
; GFX9-NEXT: v_perm_b32 v6, v35, v36, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v5, v5, v6
+; GFX9-NEXT: v_lshl_or_b32 v15, v15, 16, v16
+; GFX9-NEXT: v_lshl_or_b32 v5, v6, 16, v5
+; GFX9-NEXT: buffer_store_dword v15, v0, s[0:3], 0 offen offset:4
; GFX9-NEXT: buffer_store_dword v5, v0, s[0:3], 0 offen offset:44
; GFX9-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
@@ -79541,26 +79130,22 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v5, v33, v5, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v5
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
; GFX9-NEXT: v_perm_b32 v3, v4, v32, s4
; GFX9-NEXT: v_perm_b32 v4, v30, v31, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_perm_b32 v3, v28, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
; GFX9-NEXT: v_perm_b32 v1, v2, v27, s4
-; GFX9-NEXT: v_perm_b32 v2, v17, v26, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v2, v25, v26, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -79654,6 +79239,8 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42
; GFX11-NEXT: s_cbranch_vccnz .LBB105_4
; GFX11-NEXT: .LBB105_2: ; %cmp.true
+; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s27 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s26 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s25 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s24 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s23 op_sel_hi:[0,1]
@@ -79664,60 +79251,58 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX11-NEXT: v_pk_add_f16 v9, 0x200, s18 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v12, 0x200, s17 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v11, 0x200, s16 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b64 v[17:18], 24, v[1:2]
; GFX11-NEXT: v_pk_add_f16 v14, 0x200, s3 op_sel_hi:[0,1]
; GFX11-NEXT: v_pk_add_f16 v13, 0x200, s2 op_sel_hi:[0,1]
-; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[3:4]
-; GFX11-NEXT: v_pk_add_f16 v18, 0x200, s1 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v17, 0x200, s0 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s27 op_sel_hi:[0,1]
-; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s26 op_sel_hi:[0,1]
-; GFX11-NEXT: v_lshrrev_b64 v[20:21], 24, v[5:6]
-; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[7:8]
-; GFX11-NEXT: v_lshrrev_b64 v[22:23], 24, v[9:10]
-; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[11:12]
-; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[13:14]
-; GFX11-NEXT: v_lshrrev_b64 v[15:16], 24, v[1:2]
-; GFX11-NEXT: v_lshrrev_b64 v[25:26], 24, v[17:18]
-; GFX11-NEXT: v_lshrrev_b32_e32 v28, 24, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v27, 16, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v16, 8, v2
-; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v26, 8, v1
-; GFX11-NEXT: v_lshrrev_b32_e32 v32, 24, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v31, 16, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v33, 8, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v37, 24, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v36, 16, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v6
-; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v38, 8, v5
-; GFX11-NEXT: v_lshrrev_b32_e32 v51, 24, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v50, 16, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v8
-; GFX11-NEXT: v_lshrrev_b32_e32 v52, 16, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v49, 8, v7
-; GFX11-NEXT: v_lshrrev_b32_e32 v55, 24, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v53, 8, v10
-; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v64, 8, v9
-; GFX11-NEXT: v_lshrrev_b32_e32 v69, 24, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v68, 16, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v65, 8, v12
-; GFX11-NEXT: v_lshrrev_b32_e32 v70, 16, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v67, 8, v11
-; GFX11-NEXT: v_lshrrev_b32_e32 v81, 24, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v80, 16, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v71, 8, v14
-; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v82, 8, v13
-; GFX11-NEXT: v_lshrrev_b32_e32 v87, 24, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v86, 16, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v18
-; GFX11-NEXT: v_lshrrev_b32_e32 v96, 16, v17
-; GFX11-NEXT: v_lshrrev_b32_e32 v85, 8, v17
+; GFX11-NEXT: v_lshrrev_b64 v[18:19], 24, v[3:4]
+; GFX11-NEXT: v_pk_add_f16 v16, 0x200, s1 op_sel_hi:[0,1]
+; GFX11-NEXT: v_pk_add_f16 v15, 0x200, s0 op_sel_hi:[0,1]
+; GFX11-NEXT: v_lshrrev_b64 v[19:20], 24, v[5:6]
+; GFX11-NEXT: v_lshrrev_b64 v[20:21], 24, v[7:8]
+; GFX11-NEXT: v_lshrrev_b64 v[21:22], 24, v[9:10]
+; GFX11-NEXT: v_lshrrev_b64 v[22:23], 24, v[11:12]
+; GFX11-NEXT: v_lshrrev_b64 v[23:24], 24, v[13:14]
+; GFX11-NEXT: v_lshrrev_b64 v[24:25], 24, v[15:16]
+; GFX11-NEXT: v_lshrrev_b32_e32 v26, 24, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v25, 16, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v27, 8, v2
+; GFX11-NEXT: v_lshrrev_b32_e32 v28, 16, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v29, 8, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v31, 24, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v30, 16, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v32, 8, v4
+; GFX11-NEXT: v_lshrrev_b32_e32 v33, 16, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v34, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v36, 24, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v35, 16, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v37, 8, v6
+; GFX11-NEXT: v_lshrrev_b32_e32 v38, 16, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v39, 8, v5
+; GFX11-NEXT: v_lshrrev_b32_e32 v49, 24, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v48, 16, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v50, 8, v8
+; GFX11-NEXT: v_lshrrev_b32_e32 v51, 16, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v52, 8, v7
+; GFX11-NEXT: v_lshrrev_b32_e32 v54, 24, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v53, 16, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v55, 8, v10
+; GFX11-NEXT: v_lshrrev_b32_e32 v64, 16, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v65, 8, v9
+; GFX11-NEXT: v_lshrrev_b32_e32 v67, 24, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v66, 16, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v68, 8, v12
+; GFX11-NEXT: v_lshrrev_b32_e32 v69, 16, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v70, 8, v11
+; GFX11-NEXT: v_lshrrev_b32_e32 v80, 24, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v71, 16, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v81, 8, v14
+; GFX11-NEXT: v_lshrrev_b32_e32 v82, 16, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v83, 8, v13
+; GFX11-NEXT: v_lshrrev_b32_e32 v85, 24, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v84, 16, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v86, 8, v16
+; GFX11-NEXT: v_lshrrev_b32_e32 v87, 16, v15
+; GFX11-NEXT: v_lshrrev_b32_e32 v96, 8, v15
; GFX11-NEXT: s_branch .LBB105_5
; GFX11-NEXT: .LBB105_3:
; GFX11-NEXT: ; implicit-def: $sgpr49
@@ -79770,7 +79355,7 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX11-NEXT: ; implicit-def: $sgpr43
; GFX11-NEXT: s_branch .LBB105_2
; GFX11-NEXT: .LBB105_4:
-; GFX11-NEXT: v_dual_mov_b32 v17, s0 :: v_dual_mov_b32 v18, s1
+; GFX11-NEXT: v_dual_mov_b32 v15, s0 :: v_dual_mov_b32 v16, s1
; GFX11-NEXT: v_dual_mov_b32 v13, s2 :: v_dual_mov_b32 v14, s3
; GFX11-NEXT: v_dual_mov_b32 v11, s16 :: v_dual_mov_b32 v12, s17
; GFX11-NEXT: v_dual_mov_b32 v9, s18 :: v_dual_mov_b32 v10, s19
@@ -79778,100 +79363,84 @@ define inreg <64 x i8> @bitcast_v32f16_to_v64i8_scalar(<32 x half> inreg %a, i32
; GFX11-NEXT: v_dual_mov_b32 v5, s22 :: v_dual_mov_b32 v6, s23
; GFX11-NEXT: v_dual_mov_b32 v3, s24 :: v_dual_mov_b32 v4, s25
; GFX11-NEXT: v_dual_mov_b32 v1, s26 :: v_dual_mov_b32 v2, s27
-; GFX11-NEXT: v_dual_mov_b32 v85, s49 :: v_dual_mov_b32 v96, s39
-; GFX11-NEXT: v_dual_mov_b32 v83, s48 :: v_dual_mov_b32 v86, s38
-; GFX11-NEXT: v_dual_mov_b32 v87, s37 :: v_dual_mov_b32 v82, s36
-; GFX11-NEXT: v_dual_mov_b32 v84, s34 :: v_dual_mov_b32 v71, s35
-; GFX11-NEXT: v_dual_mov_b32 v80, s31 :: v_dual_mov_b32 v81, s30
-; GFX11-NEXT: v_dual_mov_b32 v67, vcc_hi :: v_dual_mov_b32 v70, s94
-; GFX11-NEXT: v_dual_mov_b32 v65, s95 :: v_dual_mov_b32 v68, s93
-; GFX11-NEXT: v_dual_mov_b32 v69, s92 :: v_dual_mov_b32 v64, s91
-; GFX11-NEXT: v_dual_mov_b32 v66, s89 :: v_dual_mov_b32 v53, s90
-; GFX11-NEXT: v_dual_mov_b32 v54, s88 :: v_dual_mov_b32 v55, s79
-; GFX11-NEXT: v_dual_mov_b32 v49, s78 :: v_dual_mov_b32 v52, s76
-; GFX11-NEXT: v_dual_mov_b32 v39, s77 :: v_dual_mov_b32 v50, s75
-; GFX11-NEXT: v_dual_mov_b32 v51, s74 :: v_dual_mov_b32 v38, s73
-; GFX11-NEXT: v_dual_mov_b32 v48, s63 :: v_dual_mov_b32 v37, s61
-; GFX11-NEXT: v_dual_mov_b32 v34, s72 :: v_dual_mov_b32 v33, s60
-; GFX11-NEXT: v_dual_mov_b32 v36, s62 :: v_dual_mov_b32 v35, s58
-; GFX11-NEXT: v_dual_mov_b32 v29, s59 :: v_dual_mov_b32 v32, s56
-; GFX11-NEXT: v_dual_mov_b32 v31, s57 :: v_dual_mov_b32 v26, s47
-; GFX11-NEXT: v_dual_mov_b32 v30, s45 :: v_dual_mov_b32 v27, s44
-; GFX11-NEXT: v_dual_mov_b32 v16, s46 :: v_dual_mov_b32 v15, s40
-; GFX11-NEXT: v_dual_mov_b32 v28, s43 :: v_dual_mov_b32 v19, s28
-; GFX11-NEXT: v_dual_mov_b32 v20, s14 :: v_dual_mov_b32 v21, s12
-; GFX11-NEXT: v_dual_mov_b32 v22, s10 :: v_dual_mov_b32 v23, s8
-; GFX11-NEXT: v_dual_mov_b32 v24, s6 :: v_dual_mov_b32 v25, s4
+; GFX11-NEXT: v_dual_mov_b32 v96, s49 :: v_dual_mov_b32 v87, s39
+; GFX11-NEXT: v_dual_mov_b32 v86, s48 :: v_dual_mov_b32 v85, s37
+; GFX11-NEXT: v_dual_mov_b32 v84, s38 :: v_dual_mov_b32 v83, s36
+; GFX11-NEXT: v_dual_mov_b32 v82, s34 :: v_dual_mov_b32 v81, s35
+; GFX11-NEXT: v_dual_mov_b32 v71, s31 :: v_dual_mov_b32 v80, s30
+; GFX11-NEXT: v_dual_mov_b32 v70, vcc_hi :: v_dual_mov_b32 v69, s94
+; GFX11-NEXT: v_dual_mov_b32 v68, s95 :: v_dual_mov_b32 v67, s92
+; GFX11-NEXT: v_dual_mov_b32 v66, s93 :: v_dual_mov_b32 v65, s91
+; GFX11-NEXT: v_dual_mov_b32 v64, s89 :: v_dual_mov_b32 v55, s90
+; GFX11-NEXT: v_dual_mov_b32 v53, s88 :: v_dual_mov_b32 v54, s79
+; GFX11-NEXT: v_dual_mov_b32 v52, s78 :: v_dual_mov_b32 v51, s76
+; GFX11-NEXT: v_dual_mov_b32 v50, s77 :: v_dual_mov_b32 v49, s74
+; GFX11-NEXT: v_dual_mov_b32 v48, s75 :: v_dual_mov_b32 v39, s73
+; GFX11-NEXT: v_dual_mov_b32 v38, s63 :: v_dual_mov_b32 v37, s72
+; GFX11-NEXT: v_dual_mov_b32 v35, s62 :: v_dual_mov_b32 v36, s61
+; GFX11-NEXT: v_dual_mov_b32 v34, s60 :: v_dual_mov_b32 v33, s58
+; GFX11-NEXT: v_dual_mov_b32 v32, s59 :: v_dual_mov_b32 v31, s56
+; GFX11-NEXT: v_dual_mov_b32 v30, s57 :: v_dual_mov_b32 v29, s47
+; GFX11-NEXT: v_dual_mov_b32 v28, s45 :: v_dual_mov_b32 v27, s46
+; GFX11-NEXT: v_dual_mov_b32 v25, s44 :: v_dual_mov_b32 v26, s43
+; GFX11-NEXT: v_dual_mov_b32 v17, s40 :: v_dual_mov_b32 v18, s28
+; GFX11-NEXT: v_dual_mov_b32 v19, s14 :: v_dual_mov_b32 v20, s12
+; GFX11-NEXT: v_dual_mov_b32 v21, s10 :: v_dual_mov_b32 v22, s8
+; GFX11-NEXT: v_dual_mov_b32 v23, s6 :: v_dual_mov_b32 v24, s4
; GFX11-NEXT: .LBB105_5: ; %end
-; GFX11-NEXT: v_perm_b32 v86, v86, v87, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_perm_b32 v24, v84, v24, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v25, v96, v25, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v18, v83, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v13, v13, v82, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v83, 16, v86
-; GFX11-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-NEXT: v_perm_b32 v17, v17, v85, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-NEXT: v_perm_b32 v84, v80, v81, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v22, v66, v22, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v81, v18, v83
-; GFX11-NEXT: v_or_b32_e32 v82, v13, v24
-; GFX11-NEXT: v_perm_b32 v13, v14, v71, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v14, v70, v23, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v68, v69, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v80, v17, v25
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v84
-; GFX11-NEXT: v_perm_b32 v9, v9, v64, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-NEXT: v_perm_b32 v11, v11, v67, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v12, v12, v65, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v83, v13, v17
-; GFX11-NEXT: v_or_b32_e32 v13, v9, v22
-; GFX11-NEXT: v_perm_b32 v9, v10, v53, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v10, v52, v21, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v11, v11, v14
-; GFX11-NEXT: v_perm_b32 v14, v54, v55, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v12, v12, v18
-; GFX11-NEXT: v_perm_b32 v17, v50, v51, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v48, v20, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v7, v7, v49, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-NEXT: v_perm_b32 v8, v8, v39, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT: v_perm_b32 v5, v5, v38, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v7, v7, v10
-; GFX11-NEXT: v_perm_b32 v10, v36, v37, 0xc0c0004
-; GFX11-NEXT: v_or_b32_e32 v14, v9, v14
-; GFX11-NEXT: v_or_b32_e32 v8, v8, v17
-; GFX11-NEXT: v_or_b32_e32 v9, v5, v18
-; GFX11-NEXT: v_perm_b32 v5, v35, v19, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v17, v31, v32, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v15, v30, v15, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v18, v27, v28, 0xc0c0004
-; GFX11-NEXT: v_perm_b32 v6, v6, v34, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-NEXT: v_perm_b32 v3, v3, v33, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-NEXT: v_perm_b32 v4, v4, v29, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-NEXT: v_perm_b32 v19, v1, v26, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-NEXT: v_perm_b32 v16, v2, v16, 0xc0c0004
-; GFX11-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-NEXT: v_or_b32_e32 v10, v6, v10
-; GFX11-NEXT: v_or_b32_e32 v1, v3, v5
-; GFX11-NEXT: v_or_b32_e32 v2, v4, v17
-; GFX11-NEXT: v_or_b32_e32 v3, v19, v15
-; GFX11-NEXT: v_or_b32_e32 v4, v16, v18
+; GFX11-NEXT: v_perm_b32 v11, v11, v70, 0xc0c0004
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v22, v69, v22, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v12, v68, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v67, v66, v67, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v15, v15, v96, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v87, v24, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v66, v22, 16, v11
+; GFX11-NEXT: v_perm_b32 v9, v9, v65, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v64, v21, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v5, v5, v39, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v19, v38, v19, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v67, v67, 16, v12
+; GFX11-NEXT: v_perm_b32 v10, v10, v55, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v53, v54, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v7, v7, v52, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v51, v20, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v16, v16, v86, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v84, v84, v85, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v83, v13, v83, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v13, v24, 16, v15
+; GFX11-NEXT: v_perm_b32 v15, v82, v23, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v23, v14, v81, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v24, v71, v80, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v8, v8, v50, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v21, v48, v49, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v68, v11, 16, v9
+; GFX11-NEXT: v_lshl_or_b32 v9, v19, 16, v5
+; GFX11-NEXT: v_perm_b32 v5, v6, v37, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v6, v35, v36, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v69, v12, 16, v10
+; GFX11-NEXT: v_lshl_or_b32 v7, v20, 16, v7
+; GFX11-NEXT: v_perm_b32 v3, v3, v34, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v11, v33, v18, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v4, v4, v32, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v12, v30, v31, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v18, v1, v29, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v17, v28, v17, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v19, v2, v27, 0xc0c0004
+; GFX11-NEXT: v_perm_b32 v20, v25, v26, 0xc0c0004
+; GFX11-NEXT: v_lshl_or_b32 v14, v84, 16, v16
+; GFX11-NEXT: v_lshl_or_b32 v15, v15, 16, v83
+; GFX11-NEXT: v_lshl_or_b32 v16, v24, 16, v23
+; GFX11-NEXT: v_lshl_or_b32 v8, v21, 16, v8
+; GFX11-NEXT: v_lshl_or_b32 v10, v6, 16, v5
+; GFX11-NEXT: v_lshl_or_b32 v1, v11, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v12, 16, v4
+; GFX11-NEXT: v_lshl_or_b32 v3, v17, 16, v18
+; GFX11-NEXT: v_lshl_or_b32 v4, v20, 16, v19
; GFX11-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-NEXT: s_clause 0x3
-; GFX11-NEXT: scratch_store_b128 v0, v[80:83], off
-; GFX11-NEXT: scratch_store_b128 v0, v[11:14], off offset:16
+; GFX11-NEXT: scratch_store_b128 v0, v[13:16], off
+; GFX11-NEXT: scratch_store_b128 v0, v[66:69], off offset:16
; GFX11-NEXT: scratch_store_b128 v0, v[7:10], off offset:32
; GFX11-NEXT: scratch_store_b128 v0, v[1:4], off offset:48
; GFX11-NEXT: v_readlane_b32 s31, v40, 9
@@ -83581,59 +83150,58 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX9-NEXT: v_perm_b32 v9, s12, v9, v8
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v16
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v17
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v10, s72, v18, v8
-; GFX9-NEXT: v_or_b32_sdwa v9, v17, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v16, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v10
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v29, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v19
-; GFX9-NEXT: v_or_b32_sdwa v10, v21, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v29
+; GFX9-NEXT: v_lshl_or_b32 v9, v26, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v21
+; GFX9-NEXT: v_lshl_or_b32 v10, v19, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_lshl_or_b32 v12, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v20
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v23
; GFX9-NEXT: v_perm_b32 v10, v31, v28, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v23, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v20, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v13, v9, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v30
-; GFX9-NEXT: v_or_b32_sdwa v9, v33, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v22
-; GFX9-NEXT: v_or_b32_sdwa v10, v25, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v33
+; GFX9-NEXT: v_lshl_or_b32 v9, v30, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v25
+; GFX9-NEXT: v_lshl_or_b32 v10, v22, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_lshl_or_b32 v14, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v24
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v27
; GFX9-NEXT: v_perm_b32 v10, v34, v32, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v27, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v24, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX9-NEXT: s_and_b32 s4, s47, 0xff
; GFX9-NEXT: v_lshl_or_b32 v15, v9, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v9, s58
-; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
-; GFX9-NEXT: s_and_b32 s4, s47, 0xff
; GFX9-NEXT: s_lshl_b32 s5, s7, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s5
+; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX9-NEXT: v_lshl_or_b32 v9, s4, 16, v8
; GFX9-NEXT: s_and_b32 s4, s10, 0xff
+; GFX9-NEXT: v_lshl_or_b32 v9, s5, 16, v8
; GFX9-NEXT: s_lshl_b32 s5, s9, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s8, 0xff
+; GFX9-NEXT: s_or_b32 s5, s5, s4
+; GFX9-NEXT: s_and_b32 s4, s8, 0xff
; GFX9-NEXT: s_lshl_b32 s77, s6, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
+; GFX9-NEXT: s_or_b32 s77, s77, s4
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s77
; GFX9-NEXT: s_and_b32 s5, s63, 0xff
; GFX9-NEXT: s_lshl_b32 s77, s61, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_and_b32 s77, s57, 0xff
+; GFX9-NEXT: s_or_b32 s77, s77, s5
+; GFX9-NEXT: s_and_b32 s5, s57, 0xff
; GFX9-NEXT: s_lshl_b32 s78, s56, 8
-; GFX9-NEXT: s_or_b32 s77, s77, s78
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s77
+; GFX9-NEXT: s_or_b32 s78, s78, s5
+; GFX9-NEXT: s_pack_ll_b32_b16 s5, s77, s78
; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: v_mov_b32_e32 v10, s5
; GFX9-NEXT: s_cbranch_execnz .LBB107_3
@@ -83858,83 +83426,77 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB107_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v49
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s76
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s8, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s8, 8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s78
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s7, v8
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v13, 0xff, v38
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s46, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s73, 0xff
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s79
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s56, 0xff
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s57, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s12, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s76
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v34, 8, v13
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s88, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xff, v37
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v50, 8, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v52
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v36
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v35, 8, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v48, 8, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v32, 8, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, s79
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s77
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s76
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB107_3
; GFX11-TRUE16-NEXT: .LBB107_2: ; %cmp.true
@@ -84121,8 +83683,8 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s41, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v50
+; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s76
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
@@ -84132,83 +83694,76 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s77, s44, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s44, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s46, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s41, 8
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s11, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s40, s13, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s79
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s6, s4, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s7, s5, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s43, s15, v8
+; GFX11-FAKE16-NEXT: s_lshl_b32 s76, s42, 8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s40, s13, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s57, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s78
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s72, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s88, s56, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s89, s62, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s10, s8, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s89, s89, s78
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v6
+; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s45, 8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
+; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s88
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v9, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s76, 16, v12
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v34, 8, s79
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v51
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v35, 8, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v49
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v38, 8, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v39
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v52, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s89, s78
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s61, 0xff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v20
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v31, 8, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v33, 8, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 8, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v10, 16, v14
+; GFX11-FAKE16-NEXT: s_or_b32 s88, s88, s78
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s88, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v19, 16, v20
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v16, 16, v17
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s77
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s76
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB107_3
; GFX11-FAKE16-NEXT: .LBB107_2: ; %cmp.true
@@ -88872,360 +88427,360 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: s_cbranch_execnz .LBB109_4
; GFX9-NEXT: .LBB109_2: ; %cmp.true
; GFX9-NEXT: s_and_b32 s6, s17, 0xffff0000
-; GFX9-NEXT: v_mov_b32_e32 v1, 0x40c00000
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
-; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
-; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
+; GFX9-NEXT: v_mov_b32_e32 v3, 0x40c00000
+; GFX9-NEXT: v_add_f32_e32 v1, s6, v3
+; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
+; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
+; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
; GFX9-NEXT: s_lshl_b32 s6, s17, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
-; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
-; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v4, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX9-NEXT: v_add_f32_e32 v1, s6, v3
+; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
+; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
+; GFX9-NEXT: v_or_b32_e32 v4, 0x400000, v1
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX9-NEXT: s_and_b32 s6, s16, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v4, v5, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v5, 16, v1
+; GFX9-NEXT: v_add_f32_e32 v1, s6, v3
+; GFX9-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v1
; GFX9-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
-; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
+; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4
+; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
; GFX9-NEXT: s_lshl_b32 s6, s16, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v3, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v3, v3, v2
-; GFX9-NEXT: v_add_u32_e32 v3, 0x7fff, v3
-; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v30
+; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v1
+; GFX9-NEXT: v_add_f32_e32 v1, s6, v3
+; GFX9-NEXT: v_bfe_u32 v4, v1, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v1
+; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4
+; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v1
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
; GFX9-NEXT: s_and_b32 s6, s19, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v3, v31, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s19, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v32
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v30, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v30
; GFX9-NEXT: s_and_b32 s6, s18, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v11, v29, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v9, v28, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s18, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v35
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v32, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v32
; GFX9-NEXT: s_and_b32 s6, s21, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v10, v37, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v8, v33, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s21, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v27, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v29, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v28, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v28
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v31, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v31
; GFX9-NEXT: s_and_b32 s6, s20, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v15, v27, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v14, v29, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s20, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v35, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v50
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v39
; GFX9-NEXT: s_and_b32 s6, s23, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v14, v36, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v13, v35, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s23, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v33, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v34, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v34
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v36, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v36
; GFX9-NEXT: s_and_b32 s6, s22, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v20, v33, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v19, v34, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s22, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v37, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v48
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v48, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v48
; GFX9-NEXT: s_and_b32 s6, s25, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v19, v38, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v18, v37, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s25, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v39, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v38, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v49
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v49, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v49
; GFX9-NEXT: s_and_b32 s6, s24, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v22, v39, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v21, v38, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s24, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v50, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v53
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v52
; GFX9-NEXT: s_and_b32 s6, s27, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v21, v51, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v20, v50, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s27, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v52, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v51, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v54
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v53, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v53
; GFX9-NEXT: s_and_b32 s6, s26, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v24, v52, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v23, v51, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s26, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v54, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v41
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v40
; GFX9-NEXT: s_and_b32 s6, s29, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v23, v55, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v22, v54, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s29, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v40, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v55, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v42
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v41, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v41
; GFX9-NEXT: s_and_b32 s6, s28, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v26, v40, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v25, v55, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s6, s28, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v42, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v45, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v45
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v44, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v44
; GFX9-NEXT: s_and_b32 s6, s5, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v25, v43, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s6, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v24, v42, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s6, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
; GFX9-NEXT: s_lshl_b32 s5, s5, 16
-; GFX9-NEXT: v_lshrrev_b32_e32 v44, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s5, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v43, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s5, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v2
-; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v46
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v45, 16, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v45
; GFX9-NEXT: s_and_b32 s5, s4, 0xffff0000
-; GFX9-NEXT: v_lshl_or_b32 v58, v44, 16, v2
-; GFX9-NEXT: v_add_f32_e32 v2, s5, v1
-; GFX9-NEXT: v_bfe_u32 v5, v2, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v5, v5, v2
+; GFX9-NEXT: v_lshl_or_b32 v57, v43, 16, v4
+; GFX9-NEXT: v_add_f32_e32 v4, s5, v3
+; GFX9-NEXT: v_bfe_u32 v5, v4, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v5, v5, v4
; GFX9-NEXT: v_add_u32_e32 v5, 0x7fff, v5
-; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v2
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v2, v2
+; GFX9-NEXT: v_or_b32_e32 v6, 0x400000, v4
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v4, v4
; GFX9-NEXT: s_lshl_b32 s4, s4, 16
-; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v6, vcc
-; GFX9-NEXT: v_add_f32_e32 v1, s4, v1
-; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v2
-; GFX9-NEXT: v_bfe_u32 v2, v1, 16, 1
-; GFX9-NEXT: v_add_u32_e32 v2, v2, v1
-; GFX9-NEXT: v_add_u32_e32 v2, 0x7fff, v2
-; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v1, v1
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
-; GFX9-NEXT: v_lshrrev_b32_e32 v56, 16, v1
-; GFX9-NEXT: v_lshrrev_b64 v[5:6], 24, v[25:26]
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v56
-; GFX9-NEXT: v_lshrrev_b64 v[6:7], 24, v[23:24]
-; GFX9-NEXT: v_lshl_or_b32 v57, v47, 16, v1
-; GFX9-NEXT: v_lshrrev_b64 v[7:8], 24, v[21:22]
-; GFX9-NEXT: v_lshrrev_b64 v[16:17], 24, v[10:11]
-; GFX9-NEXT: v_lshrrev_b64 v[1:2], 24, v[57:58]
-; GFX9-NEXT: v_lshrrev_b64 v[8:9], 24, v[19:20]
-; GFX9-NEXT: v_lshrrev_b64 v[12:13], 24, v[14:15]
-; GFX9-NEXT: v_lshrrev_b64 v[17:18], 24, v[3:4]
-; GFX9-NEXT: v_lshrrev_b32_e32 v2, 24, v58
-; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v58
-; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v57
-; GFX9-NEXT: v_lshrrev_b32_e32 v18, 24, v26
-; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v26
-; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v25
-; GFX9-NEXT: v_lshrrev_b32_e32 v59, 24, v24
-; GFX9-NEXT: v_lshrrev_b32_e32 v24, 8, v24
+; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v6, vcc
+; GFX9-NEXT: v_add_f32_e32 v3, s4, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v46, 16, v4
+; GFX9-NEXT: v_bfe_u32 v4, v3, 16, 1
+; GFX9-NEXT: v_add_u32_e32 v4, v4, v3
+; GFX9-NEXT: v_add_u32_e32 v4, 0x7fff, v4
+; GFX9-NEXT: v_or_b32_e32 v5, 0x400000, v3
+; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v3, v3
+; GFX9-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc
+; GFX9-NEXT: v_lshrrev_b32_e32 v47, 16, v3
+; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v47
+; GFX9-NEXT: v_lshl_or_b32 v56, v46, 16, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v26, 16, v1
+; GFX9-NEXT: v_lshrrev_b64 v[3:4], 24, v[56:57]
+; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v26
+; GFX9-NEXT: v_lshrrev_b64 v[4:5], 24, v[24:25]
+; GFX9-NEXT: v_lshl_or_b32 v1, v27, 16, v1
+; GFX9-NEXT: v_lshrrev_b64 v[5:6], 24, v[22:23]
+; GFX9-NEXT: v_lshrrev_b64 v[10:11], 24, v[18:19]
+; GFX9-NEXT: v_lshrrev_b64 v[15:16], 24, v[8:9]
+; GFX9-NEXT: v_lshrrev_b64 v[6:7], 24, v[20:21]
+; GFX9-NEXT: v_lshrrev_b64 v[11:12], 24, v[13:14]
+; GFX9-NEXT: v_lshrrev_b64 v[16:17], 24, v[1:2]
+; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v57
+; GFX9-NEXT: v_lshrrev_b32_e32 v12, 8, v57
+; GFX9-NEXT: v_lshrrev_b32_e32 v17, 8, v56
+; GFX9-NEXT: v_lshrrev_b32_e32 v56, 24, v25
+; GFX9-NEXT: v_lshrrev_b32_e32 v57, 8, v25
+; GFX9-NEXT: v_lshrrev_b32_e32 v58, 8, v24
+; GFX9-NEXT: v_lshrrev_b32_e32 v59, 24, v23
; GFX9-NEXT: v_lshrrev_b32_e32 v23, 8, v23
-; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v22
; GFX9-NEXT: v_lshrrev_b32_e32 v22, 8, v22
+; GFX9-NEXT: v_lshrrev_b32_e32 v60, 24, v21
; GFX9-NEXT: v_lshrrev_b32_e32 v21, 8, v21
-; GFX9-NEXT: v_lshrrev_b32_e32 v61, 24, v20
; GFX9-NEXT: v_lshrrev_b32_e32 v20, 8, v20
+; GFX9-NEXT: v_lshrrev_b32_e32 v61, 24, v19
; GFX9-NEXT: v_lshrrev_b32_e32 v19, 8, v19
-; GFX9-NEXT: v_lshrrev_b32_e32 v62, 24, v15
-; GFX9-NEXT: v_lshrrev_b32_e32 v15, 8, v15
+; GFX9-NEXT: v_lshrrev_b32_e32 v18, 8, v18
+; GFX9-NEXT: v_lshrrev_b32_e32 v62, 24, v14
; GFX9-NEXT: v_lshrrev_b32_e32 v14, 8, v14
-; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v11
-; GFX9-NEXT: v_lshrrev_b32_e32 v11, 8, v11
-; GFX9-NEXT: v_lshrrev_b32_e32 v10, 8, v10
-; GFX9-NEXT: v_lshrrev_b32_e32 v26, 24, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v4
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v3
+; GFX9-NEXT: v_lshrrev_b32_e32 v13, 8, v13
+; GFX9-NEXT: v_lshrrev_b32_e32 v24, 24, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v9, 8, v9
+; GFX9-NEXT: v_lshrrev_b32_e32 v8, 8, v8
+; GFX9-NEXT: v_lshrrev_b32_e32 v25, 24, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v2
+; GFX9-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX9-NEXT: s_branch .LBB109_5
; GFX9-NEXT: .LBB109_3:
; GFX9-NEXT: ; implicit-def: $sgpr61
@@ -89281,82 +88836,77 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
; GFX9-NEXT: v_mov_b32_e32 v1, s30
-; GFX9-NEXT: v_mov_b32_e32 v56, s4
-; GFX9-NEXT: v_mov_b32_e32 v47, s55
-; GFX9-NEXT: v_mov_b32_e32 v46, s5
-; GFX9-NEXT: v_mov_b32_e32 v44, s54
-; GFX9-NEXT: v_mov_b32_e32 v45, s28
-; GFX9-NEXT: v_mov_b32_e32 v43, s53
-; GFX9-NEXT: v_mov_b32_e32 v42, s29
-; GFX9-NEXT: v_mov_b32_e32 v40, s52
-; GFX9-NEXT: v_mov_b32_e32 v41, s26
-; GFX9-NEXT: v_mov_b32_e32 v55, s51
-; GFX9-NEXT: v_mov_b32_e32 v54, s27
-; GFX9-NEXT: v_mov_b32_e32 v52, s50
-; GFX9-NEXT: v_mov_b32_e32 v53, s24
-; GFX9-NEXT: v_mov_b32_e32 v51, s49
+; GFX9-NEXT: v_mov_b32_e32 v47, s4
+; GFX9-NEXT: v_mov_b32_e32 v46, s55
+; GFX9-NEXT: v_mov_b32_e32 v45, s5
+; GFX9-NEXT: v_mov_b32_e32 v43, s54
+; GFX9-NEXT: v_mov_b32_e32 v44, s28
+; GFX9-NEXT: v_mov_b32_e32 v42, s53
+; GFX9-NEXT: v_mov_b32_e32 v41, s29
+; GFX9-NEXT: v_mov_b32_e32 v55, s52
+; GFX9-NEXT: v_mov_b32_e32 v40, s26
+; GFX9-NEXT: v_mov_b32_e32 v54, s51
+; GFX9-NEXT: v_mov_b32_e32 v53, s27
+; GFX9-NEXT: v_mov_b32_e32 v51, s50
+; GFX9-NEXT: v_mov_b32_e32 v52, s24
+; GFX9-NEXT: v_mov_b32_e32 v50, s49
; GFX9-NEXT: v_mov_b32_e32 v49, s25
-; GFX9-NEXT: v_mov_b32_e32 v39, s48
+; GFX9-NEXT: v_mov_b32_e32 v38, s48
; GFX9-NEXT: v_mov_b32_e32 v48, s22
-; GFX9-NEXT: v_mov_b32_e32 v38, s39
-; GFX9-NEXT: v_mov_b32_e32 v34, s23
-; GFX9-NEXT: v_mov_b32_e32 v33, s38
-; GFX9-NEXT: v_mov_b32_e32 v50, s20
-; GFX9-NEXT: v_mov_b32_e32 v36, s37
-; GFX9-NEXT: v_mov_b32_e32 v28, s21
-; GFX9-NEXT: v_mov_b32_e32 v27, s36
-; GFX9-NEXT: v_mov_b32_e32 v35, s18
-; GFX9-NEXT: v_mov_b32_e32 v37, s35
-; GFX9-NEXT: v_mov_b32_e32 v32, s19
-; GFX9-NEXT: v_mov_b32_e32 v29, s34
-; GFX9-NEXT: v_mov_b32_e32 v30, s16
-; GFX9-NEXT: v_mov_b32_e32 v31, s31
+; GFX9-NEXT: v_mov_b32_e32 v37, s39
+; GFX9-NEXT: v_mov_b32_e32 v36, s23
+; GFX9-NEXT: v_mov_b32_e32 v34, s38
+; GFX9-NEXT: v_mov_b32_e32 v39, s20
+; GFX9-NEXT: v_mov_b32_e32 v35, s37
+; GFX9-NEXT: v_mov_b32_e32 v31, s21
+; GFX9-NEXT: v_mov_b32_e32 v29, s36
+; GFX9-NEXT: v_mov_b32_e32 v32, s18
+; GFX9-NEXT: v_mov_b32_e32 v33, s35
+; GFX9-NEXT: v_mov_b32_e32 v30, s19
+; GFX9-NEXT: v_mov_b32_e32 v28, s34
+; GFX9-NEXT: v_mov_b32_e32 v26, s16
+; GFX9-NEXT: v_mov_b32_e32 v27, s31
; GFX9-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-NEXT: v_mov_b32_e32 v13, s95
-; GFX9-NEXT: v_mov_b32_e32 v2, s91
-; GFX9-NEXT: v_mov_b32_e32 v9, s93
+; GFX9-NEXT: v_mov_b32_e32 v17, s95
+; GFX9-NEXT: v_mov_b32_e32 v7, s91
+; GFX9-NEXT: v_mov_b32_e32 v12, s93
; GFX9-NEXT: v_mov_b32_e32 v58, s94
-; GFX9-NEXT: v_mov_b32_e32 v18, s88
+; GFX9-NEXT: v_mov_b32_e32 v56, s88
; GFX9-NEXT: v_mov_b32_e32 v57, s90
-; GFX9-NEXT: v_mov_b32_e32 v23, s92
+; GFX9-NEXT: v_mov_b32_e32 v22, s92
; GFX9-NEXT: v_mov_b32_e32 v59, s77
-; GFX9-NEXT: v_mov_b32_e32 v24, s79
-; GFX9-NEXT: v_mov_b32_e32 v21, s89
+; GFX9-NEXT: v_mov_b32_e32 v23, s79
+; GFX9-NEXT: v_mov_b32_e32 v20, s89
; GFX9-NEXT: v_mov_b32_e32 v60, s74
-; GFX9-NEXT: v_mov_b32_e32 v22, s76
-; GFX9-NEXT: v_mov_b32_e32 v19, s78
+; GFX9-NEXT: v_mov_b32_e32 v21, s76
+; GFX9-NEXT: v_mov_b32_e32 v18, s78
; GFX9-NEXT: v_mov_b32_e32 v61, s63
-; GFX9-NEXT: v_mov_b32_e32 v20, s73
-; GFX9-NEXT: v_mov_b32_e32 v14, s75
+; GFX9-NEXT: v_mov_b32_e32 v19, s73
+; GFX9-NEXT: v_mov_b32_e32 v13, s75
; GFX9-NEXT: v_mov_b32_e32 v62, s60
-; GFX9-NEXT: v_mov_b32_e32 v15, s62
-; GFX9-NEXT: v_mov_b32_e32 v10, s72
-; GFX9-NEXT: v_mov_b32_e32 v25, s58
-; GFX9-NEXT: v_mov_b32_e32 v11, s59
-; GFX9-NEXT: v_mov_b32_e32 v3, s61
-; GFX9-NEXT: v_mov_b32_e32 v26, s56
-; GFX9-NEXT: v_mov_b32_e32 v4, s57
-; GFX9-NEXT: v_mov_b32_e32 v1, s44
-; GFX9-NEXT: v_mov_b32_e32 v5, s42
-; GFX9-NEXT: v_mov_b32_e32 v6, s40
-; GFX9-NEXT: v_mov_b32_e32 v7, s14
-; GFX9-NEXT: v_mov_b32_e32 v8, s12
-; GFX9-NEXT: v_mov_b32_e32 v12, s10
-; GFX9-NEXT: v_mov_b32_e32 v16, s8
-; GFX9-NEXT: v_mov_b32_e32 v17, s6
+; GFX9-NEXT: v_mov_b32_e32 v14, s62
+; GFX9-NEXT: v_mov_b32_e32 v8, s72
+; GFX9-NEXT: v_mov_b32_e32 v24, s58
+; GFX9-NEXT: v_mov_b32_e32 v9, s59
+; GFX9-NEXT: v_mov_b32_e32 v1, s61
+; GFX9-NEXT: v_mov_b32_e32 v25, s56
+; GFX9-NEXT: v_mov_b32_e32 v2, s57
+; GFX9-NEXT: v_mov_b32_e32 v3, s44
+; GFX9-NEXT: v_mov_b32_e32 v4, s42
+; GFX9-NEXT: v_mov_b32_e32 v5, s40
+; GFX9-NEXT: v_mov_b32_e32 v6, s14
+; GFX9-NEXT: v_mov_b32_e32 v10, s12
+; GFX9-NEXT: v_mov_b32_e32 v11, s10
+; GFX9-NEXT: v_mov_b32_e32 v15, s8
+; GFX9-NEXT: v_mov_b32_e32 v16, s6
; GFX9-NEXT: .LBB109_5: ; %end
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
-; GFX9-NEXT: v_perm_b32 v17, v31, v17, s4
-; GFX9-NEXT: v_perm_b32 v3, v30, v3, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v17
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen
-; GFX9-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; GFX9-NEXT: v_perm_b32 v16, v37, v16, s4
-; GFX9-NEXT: v_perm_b32 v1, v47, v1, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_perm_b32 v2, v44, v2, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX9-NEXT: v_perm_b32 v16, v27, v16, s4
+; GFX9-NEXT: v_perm_b32 v1, v26, v1, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v16, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
+; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v15, v33, v15, s4
; GFX9-NEXT: v_readlane_b32 s30, v63, 14
; GFX9-NEXT: v_readlane_b32 s31, v63, 15
; GFX9-NEXT: v_readlane_b32 s55, v63, 13
@@ -89374,77 +88924,66 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX9-NEXT: v_readlane_b32 s35, v63, 1
; GFX9-NEXT: v_readlane_b32 s34, v63, 0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v3, v3, v4, s4
-; GFX9-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
+; GFX9-NEXT: v_perm_b32 v1, v1, v2, s4
+; GFX9-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_perm_b32 v4, v4, v26, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:4
-; GFX9-NEXT: v_perm_b32 v3, v35, v10, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v16
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v29, v25, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:8
-; GFX9-NEXT: v_perm_b32 v3, v32, v11, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v36, v12, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:12
-; GFX9-NEXT: v_perm_b32 v3, v50, v14, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v27, v62, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:16
-; GFX9-NEXT: v_perm_b32 v3, v28, v15, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v38, v8, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:20
-; GFX9-NEXT: v_perm_b32 v3, v48, v19, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v33, v61, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:24
-; GFX9-NEXT: v_perm_b32 v3, v34, v20, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v51, v7, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:28
-; GFX9-NEXT: v_perm_b32 v3, v53, v21, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v39, v60, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:32
-; GFX9-NEXT: v_perm_b32 v3, v49, v22, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v55, v6, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:36
-; GFX9-NEXT: v_perm_b32 v3, v41, v23, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v52, v59, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:40
-; GFX9-NEXT: v_perm_b32 v3, v54, v24, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v43, v5, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:44
-; GFX9-NEXT: v_perm_b32 v3, v45, v58, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_perm_b32 v4, v40, v18, s4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:48
-; GFX9-NEXT: v_perm_b32 v3, v42, v57, s4
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: buffer_store_dword v3, v0, s[0:3], 0 offen offset:52
-; GFX9-NEXT: v_perm_b32 v3, v56, v13, s4
-; GFX9-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX9-NEXT: v_perm_b32 v2, v2, v25, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4
+; GFX9-NEXT: v_perm_b32 v1, v32, v8, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v15, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:8
+; GFX9-NEXT: v_perm_b32 v1, v30, v9, s4
+; GFX9-NEXT: v_perm_b32 v2, v28, v24, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:12
+; GFX9-NEXT: v_perm_b32 v1, v39, v13, s4
+; GFX9-NEXT: v_perm_b32 v2, v35, v11, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:16
+; GFX9-NEXT: v_perm_b32 v1, v31, v14, s4
+; GFX9-NEXT: v_perm_b32 v2, v29, v62, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:20
+; GFX9-NEXT: v_perm_b32 v1, v48, v18, s4
+; GFX9-NEXT: v_perm_b32 v2, v37, v10, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:24
+; GFX9-NEXT: v_perm_b32 v1, v36, v19, s4
+; GFX9-NEXT: v_perm_b32 v2, v34, v61, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:28
+; GFX9-NEXT: v_perm_b32 v1, v52, v20, s4
+; GFX9-NEXT: v_perm_b32 v2, v50, v6, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:32
+; GFX9-NEXT: v_perm_b32 v1, v49, v21, s4
+; GFX9-NEXT: v_perm_b32 v2, v38, v60, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:36
+; GFX9-NEXT: v_perm_b32 v1, v40, v22, s4
+; GFX9-NEXT: v_perm_b32 v2, v54, v5, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:40
+; GFX9-NEXT: v_perm_b32 v1, v53, v23, s4
+; GFX9-NEXT: v_perm_b32 v2, v51, v59, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:44
+; GFX9-NEXT: v_perm_b32 v1, v44, v58, s4
+; GFX9-NEXT: v_perm_b32 v2, v42, v4, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:48
+; GFX9-NEXT: v_perm_b32 v1, v41, v57, s4
+; GFX9-NEXT: v_perm_b32 v2, v55, v56, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
+; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:52
+; GFX9-NEXT: v_perm_b32 v1, v47, v17, s4
+; GFX9-NEXT: v_perm_b32 v2, v46, v3, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:56
-; GFX9-NEXT: v_perm_b32 v1, v46, v9, s4
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v2
+; GFX9-NEXT: v_perm_b32 v1, v45, v12, s4
+; GFX9-NEXT: v_perm_b32 v2, v43, v7, s4
+; GFX9-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX9-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:60
; GFX9-NEXT: buffer_load_dword v62, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v61, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
@@ -89650,13 +89189,13 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, 0x400000, v11
; GFX11-TRUE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s18, 16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-TRUE16-NEXT: v_bfe_u32 v8, v10, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v13, 16, 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v24.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v7
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v8, v10
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc_lo
@@ -89672,7 +89211,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v11, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v7
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v8, v12 :: v_dual_add_nc_u32 v7, v9, v11
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v10, 16, 1
@@ -89693,7 +89232,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v13, 16, 1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v7
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v14, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v9, v13
@@ -89710,7 +89249,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s23, 16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, 0x400000, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v30, 16, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v9, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v12, 16, 1
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
@@ -89731,7 +89270,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v15, v11
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, 0x400000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v7
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_add_nc_u32 v7, v9, v13
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, 0x400000, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
@@ -89749,7 +89288,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: s_and_b32 s0, s25, 0xffff0000
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v15, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v7, v7, v12 :: v_dual_add_nc_u32 v8, v9, v10
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v11, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
@@ -89774,7 +89313,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_bfe_u32 v9, v13, 16, 1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v81.l, v36.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v8
; GFX11-TRUE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v13
@@ -89784,14 +89323,14 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_bfe_u32 v11, v8, 16, 1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x7fff, v9
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v80.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v84.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.h, v33.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v8
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, 0x400000, v13
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v83.h, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.l, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v82.h, v34.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.l, v28.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v86.h, v29.l
; GFX11-TRUE16-NEXT: v_dual_cndmask_b32 v9, v9, v10 :: v_dual_add_nc_u32 v10, 0x7fff, v11
@@ -89805,7 +89344,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.l, v31.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.h, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v85.h, v30.l
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v12, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v49, 16, v9
; GFX11-TRUE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
@@ -89834,57 +89373,57 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v51, 0x400000, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v55, 16, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v50.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v14, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v55.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v25.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v68.l, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v26.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v27.l
; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v15, v51, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v51, 16, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v26.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v27.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v20.l
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v52, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v67.l, v51.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v22.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v24.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v52, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v52, 16, v9
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v23.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.l, v53.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v54, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.l, v52.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v52.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v18.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v19.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 24, v67
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v66.h, v54.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 24, v81
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 8, v69
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v65.h, v54.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v66
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v70, 8, v81
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 8, v80
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 24, v84
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[7:8], 24, v[66:67]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 8, v86
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[7:8], 24, v[65:66]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[68:69]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[9:10], 24, v[80:81]
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[10:11], 24, v[83:84]
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[10:11], 24, v[82:83]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[85:86]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[12:13], 24, v[5:6]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[13:14], 24, v[3:4]
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[14:15], 24, v[1:2]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 8, v67
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 8, v66
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 24, v69
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 8, v69
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 24, v66
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 8, v65
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 24, v69
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 8, v68
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 8, v81
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 8, v84
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v69, 24, v81
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 24, v83
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v81, 8, v83
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 24, v86
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 8, v86
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v82, 8, v82
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 24, v86
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v85, 8, v85
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v86, 24, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 24, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
@@ -89941,30 +89480,30 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: ; implicit-def: $sgpr78
; GFX11-TRUE16-NEXT: s_branch .LBB109_2
; GFX11-TRUE16-NEXT: .LBB109_4:
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v52, s26 :: v_dual_mov_b32 v51, s27
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v54, s49 :: v_dual_mov_b32 v53, s48
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v53, s26 :: v_dual_mov_b32 v54, s49
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v51, s27 :: v_dual_mov_b32 v52, s48
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v55, s24 :: v_dual_mov_b32 v50, s39
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v49, s25 :: v_dual_mov_b32 v48, s22
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v39, s38 :: v_dual_mov_b32 v38, s37
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v34, s23 :: v_dual_mov_b32 v37, s36
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, s20 :: v_dual_mov_b32 v36, s35
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v30, s21 :: v_dual_mov_b32 v33, s34
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, s18 :: v_dual_mov_b32 v32, s31
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v36, s23 :: v_dual_mov_b32 v37, s36
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v35, s20 :: v_dual_mov_b32 v34, s35
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v32, s21 :: v_dual_mov_b32 v33, s34
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v31, s18 :: v_dual_mov_b32 v30, s31
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v28, s19 :: v_dual_mov_b32 v29, s30
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v26, s16 :: v_dual_mov_b32 v27, vcc_hi
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v23, s17 :: v_dual_mov_b32 v22, s2
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v25, s95 :: v_dual_mov_b32 v24, s94
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v24, s17 :: v_dual_mov_b32 v25, s95
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v22, s2 :: v_dual_mov_b32 v23, s94
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v20, s3 :: v_dual_mov_b32 v21, s93
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v18, s0 :: v_dual_mov_b32 v19, s92
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, s1 :: v_dual_mov_b32 v17, s91
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v64, s90 :: v_dual_mov_b32 v65, s78
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, s88 :: v_dual_mov_b32 v68, s89
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v67, s75 :: v_dual_mov_b32 v66, s77
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v71, s79 :: v_dual_mov_b32 v70, s72
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v69, s74 :: v_dual_mov_b32 v82, s61
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v81, s76 :: v_dual_mov_b32 v80, s63
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v85, s73 :: v_dual_mov_b32 v84, s58
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v83, s60 :: v_dual_mov_b32 v86, s47
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v65, s90 :: v_dual_mov_b32 v64, s88
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v15, s78 :: v_dual_mov_b32 v68, s89
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v66, s75 :: v_dual_mov_b32 v67, s77
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v71, s79 :: v_dual_mov_b32 v70, s74
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v69, s72 :: v_dual_mov_b32 v82, s76
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v80, s61 :: v_dual_mov_b32 v81, s63
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v85, s73 :: v_dual_mov_b32 v84, s60
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v83, s58 :: v_dual_mov_b32 v86, s47
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, s62 :: v_dual_mov_b32 v6, s57
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, s59 :: v_dual_mov_b32 v4, s46
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v87, s45 :: v_dual_mov_b32 v96, s43
@@ -89975,76 +89514,59 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v13, s6 :: v_dual_mov_b32 v14, s4
; GFX11-TRUE16-NEXT: .LBB109_5: ; %end
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v19, v14, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v18, v1, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v96, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v24, v13, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v27, v12, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v19, v14, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v2, v16, v2, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, v22, v3, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v25, v86, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v21, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v17, v96, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v5, v26, v5, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, v32, v11, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v23, v6, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v3, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v5, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v29, v84, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v2, v16
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v27, v12, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v24, v6, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v25, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, v22, v3, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v1, v14, 16, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v23, v13, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, v20, v4, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v31, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v6, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v36, v10, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v33, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v38, v9, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v28, v83, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, v4, v13
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v35, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v30, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v48, v71, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v6, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, v37, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v16, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v17, v18
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v9
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, v50, v8, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v39, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v21, v87, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v16, 16, v2
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v16, v12, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v17, v17, 16, v6
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v31, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v30, v11, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v3, v13, 16, v3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v4, v14, 16, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, v28, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v29, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v35, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v34, v10, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v32, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v33, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v48, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v38, v9, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v18, v6, 16, v5
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, v36, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, v37, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v19, v12, 16, v11
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v9, v10, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v20, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v11, v22, 16, v21
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v55, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v50, v8, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v49, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v39, v66, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v53, v65, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v7, v54, v7, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v53, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v34, v69, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, v55, v68, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v49, v66, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v52, v64, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v51, v15, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v19
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v8, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v9, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v20, v10
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v7, v21, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v22
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v51, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v52, v15, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v6, 16, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v5, v8, 16, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v20, 16, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v7, v7, 16, v21
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v15, 16, v22
; GFX11-TRUE16-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-TRUE16-NEXT: s_clause 0x3
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[1:4], off
-; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[11:14], off offset:16
-; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[16:19], off offset:32
+; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[16:19], off offset:16
+; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:32
; GFX11-TRUE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
; GFX11-TRUE16-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-TRUE16-NEXT: v_readlane_b32 s49, v40, 7
@@ -90229,19 +89751,19 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v3, v9, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v6
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v20
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v12, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v10, v13, 16, 1
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v22, 16, v6
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v21, 16, v6
; GFX11-FAKE16-NEXT: s_and_b32 s0, s19, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v10, v13
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v21, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, 0x400000, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v23, 16, v9
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v22, 16, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v13
@@ -90250,42 +89772,42 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s19, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v9, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: s_and_b32 s0, s18, 0xffff0000
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v10, 16, 1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v21
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v23
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v25, 16, v6
; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, 0x400000, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v12, v9
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
; GFX11-FAKE16-NEXT: v_add_f32_e64 v9, 0x40c00000, s1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v25
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v97, v23, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v87, v22, 16, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v10
; GFX11-FAKE16-NEXT: v_or_b32_e32 v29, 0x400000, v9
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v96, v27, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v86, v24, 16, v12
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v5, v5, v6, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_bfe_u32 v13, v9, 16, 1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 24, v97
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 8, v87
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v26, 16, v5
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v7, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s18, 16
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v15, 16, v2
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v85, 8, v96
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v24, 16, v6
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v27, 16, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v7, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s21, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 24, v4
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 24, v2
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v24
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v27
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v6, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, v5, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v28, 0x400000, v6
@@ -90302,7 +89824,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, 0x7fff, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-FAKE16-NEXT: s_and_b32 s0, s20, 0xffff0000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 8, v84
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v28, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v9, v12, v29, vcc_lo
@@ -90320,9 +89842,9 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s23, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v5
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v5
; GFX11-FAKE16-NEXT: v_bfe_u32 v5, v6, 16, 1
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v82, v29, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v81, v29, 16, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v8, 16, 1
; GFX11-FAKE16-NEXT: v_add_f32_e64 v10, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_and_b32 s0, s23, 0xffff0000
@@ -90332,13 +89854,13 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_bfe_u32 v12, v10, 16, 1
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v5, 0x7fff, v5
-; GFX11-FAKE16-NEXT: v_bfe_u32 v31, v11, 16, 1
+; GFX11-FAKE16-NEXT: v_bfe_u32 v32, v11, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_or_b32_e32 v33, 0x400000, v8
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v5, v5, v13 :: v_dual_add_nc_u32 v12, v12, v10
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v31, v11
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, v32, v11
; GFX11-FAKE16-NEXT: s_and_b32 s0, s22, 0xffff0000
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v10
@@ -90353,12 +89875,12 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s22, 16
; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v10, 16, 1
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v35, 16, v5
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v31, 16, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v32, 16, v8
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v10
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v34
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v31
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v32
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v33, 16, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
@@ -90369,7 +89891,7 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, 0x400000, v10
; GFX11-FAKE16-NEXT: v_add_f32_e64 v12, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s25, 16
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v81, v35, 16, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v80, v35, 16, v5
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v11, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v8, 0x40c00000, s0
@@ -90379,113 +89901,114 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v6
; GFX11-FAKE16-NEXT: v_bfe_u32 v36, v8, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s24, 0xffff0000
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v83, v31, 16, v9
; GFX11-FAKE16-NEXT: v_add_f32_e64 v39, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, v13, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v11, v36, v8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v39, 16, 1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v37, 16, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v6, 0x7fff, v10
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v10, 0x7fff, v11
; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, 0x400000, v8
+; GFX11-FAKE16-NEXT: v_bfe_u32 v7, v39, 16, 1
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s24, 16
; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, 0x400000, v12
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v39
; GFX11-FAKE16-NEXT: v_add_f32_e64 v49, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v10, v11, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, v7, v39
; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, 0x400000, v39
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_bfe_u32 v11, v49, 16, 1
; GFX11-FAKE16-NEXT: s_and_b32 s0, s27, 0xffff0000
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v6, v6, v13 :: v_dual_add_nc_u32 v7, 0x7fff, v7
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v39, v39
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v36, 16, v8
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v38, 16, v8
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v11, v49
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v49
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v39, 16, v6
; GFX11-FAKE16-NEXT: v_add_f32_e64 v6, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s27, 16
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
; GFX11-FAKE16-NEXT: v_add_f32_e64 v11, 0x40c00000, s0
; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s26, 16
-; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, 0x400000, v49
; GFX11-FAKE16-NEXT: v_add_f32_e64 v13, 0x40c00000, s0
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v48, 16, v7
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v7, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_bfe_u32 v50, v11, 16, 1
-; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
+; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v49, v49
; GFX11-FAKE16-NEXT: v_bfe_u32 v52, v13, 16, 1
+; GFX11-FAKE16-NEXT: s_and_b32 s0, s26, 0xffff0000
; GFX11-FAKE16-NEXT: v_bfe_u32 v8, v6, 16, 1
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v12 :: v_dual_add_nc_u32 v12, v50, v11
; GFX11-FAKE16-NEXT: v_add_f32_e64 v51, 0x40c00000, s0
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v7, v7, v12 :: v_dual_add_nc_u32 v12, v50, v11
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v50, v52, v13
; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v11
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, v8, v6
+; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v12
; GFX11-FAKE16-NEXT: v_bfe_u32 v49, v51, 16, 1
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v50, 0x7fff, v50
; GFX11-FAKE16-NEXT: v_or_b32_e32 v54, 0x400000, v13
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v11, v12, v53, vcc_lo
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: v_dual_cndmask_b32 v11, v12, v53 :: v_dual_add_nc_u32 v8, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v13, v13
-; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v8, 0x7fff, v8
; GFX11-FAKE16-NEXT: v_or_b32_e32 v52, 0x400000, v6
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v49, v49, v51
; GFX11-FAKE16-NEXT: v_or_b32_e32 v53, 0x400000, v51
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v38
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v13, v50, v54, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v36
; GFX11-FAKE16-NEXT: v_add_nc_u32_e32 v12, 0x7fff, v49
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v49, 16, v11
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v37
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v50, 16, v13
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v6, v8, v52, vcc_lo
; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v51, v51
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v37
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v67, v39, 16, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v83, v32, 16, v9
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v69, v36, 16, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 8, v70
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v51, 16, v6
; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v8, v12, v53, vcc_lo
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v53, 16, v7
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v49
; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v50
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v69, v38, 16, v11
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v81
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v52, 16, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v53
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v65, v51, 16, v6
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v68, 24, v70
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 24, v82
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v64, v52, 16, v7
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v66, v48, 16, v8
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 24, v65
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v71, 8, v81
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 8, v65
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[5:6], 24, v[64:65]
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[66:67]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[7:8], 24, v[69:70]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[81:82]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[80:81]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[9:10], 24, v[83:84]
-; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[10:11], 24, v[96:97]
+; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[10:11], 24, v[86:87]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[11:12], 24, v[3:4]
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[12:13], 24, v[1:2]
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 8, v65
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v54, 8, v64
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 24, v67
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 8, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v13, 24, v65
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v55, 8, v64
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v64, 24, v67
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v65, 8, v67
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v66, 8, v66
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 8, v70
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v67, 24, v70
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v69, 8, v69
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 8, v82
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v82, 24, v84
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 8, v84
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v70, 24, v81
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v80, 8, v80
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v81, 24, v84
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v83, 8, v83
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 8, v97
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v84, 24, v87
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v86, 8, v86
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v87, 24, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 8, v4
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 8, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v96, 24, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 8, v2
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: s_branch .LBB109_5
@@ -90543,28 +90066,28 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v50, s26 :: v_dual_mov_b32 v49, s27
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v52, s49 :: v_dual_mov_b32 v51, s48
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v53, s24 :: v_dual_mov_b32 v48, s39
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v36, s25 :: v_dual_mov_b32 v39, s38
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, s22 :: v_dual_mov_b32 v38, s37
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v31, s23 :: v_dual_mov_b32 v34, s20
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v33, s36 :: v_dual_mov_b32 v28, s21
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v35, s35 :: v_dual_mov_b32 v30, s18
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v29, s34 :: v_dual_mov_b32 v32, s31
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v24, s19 :: v_dual_mov_b32 v25, s16
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v26, s30 :: v_dual_mov_b32 v27, vcc_hi
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v21, s17 :: v_dual_mov_b32 v20, s2
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v23, s95 :: v_dual_mov_b32 v22, s94
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v38, s25 :: v_dual_mov_b32 v39, s38
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v37, s22 :: v_dual_mov_b32 v36, s37
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v32, s23 :: v_dual_mov_b32 v33, s36
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v34, s20 :: v_dual_mov_b32 v35, s35
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v28, s21 :: v_dual_mov_b32 v29, s34
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v30, s18 :: v_dual_mov_b32 v31, s31
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v27, s19 :: v_dual_mov_b32 v26, s30
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v25, s16 :: v_dual_mov_b32 v24, vcc_hi
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v23, s17 :: v_dual_mov_b32 v22, s95
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v20, s2 :: v_dual_mov_b32 v21, s94
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v18, s3 :: v_dual_mov_b32 v19, s93
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v16, s0 :: v_dual_mov_b32 v17, s92
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v14, s1 :: v_dual_mov_b32 v15, s91
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v54, s90 :: v_dual_mov_b32 v55, s78
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v13, s88 :: v_dual_mov_b32 v66, s89
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v65, s75 :: v_dual_mov_b32 v64, s77
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, s79 :: v_dual_mov_b32 v68, s72
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, s74 :: v_dual_mov_b32 v80, s61
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v71, s76 :: v_dual_mov_b32 v70, s63
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, s73 :: v_dual_mov_b32 v82, s58
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v81, s60 :: v_dual_mov_b32 v86, s47
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v85, s62 :: v_dual_mov_b32 v84, s57
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v55, s90 :: v_dual_mov_b32 v54, s88
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v13, s78 :: v_dual_mov_b32 v66, s89
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v64, s75 :: v_dual_mov_b32 v65, s77
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v69, s79 :: v_dual_mov_b32 v68, s74
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v67, s72 :: v_dual_mov_b32 v80, s76
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v70, s61 :: v_dual_mov_b32 v71, s63
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v83, s73 :: v_dual_mov_b32 v82, s60
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v81, s58 :: v_dual_mov_b32 v86, s62
+; GFX11-FAKE16-NEXT: v_dual_mov_b32 v84, s47 :: v_dual_mov_b32 v85, s57
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, s59 :: v_dual_mov_b32 v4, s46
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v87, s45 :: v_dual_mov_b32 v96, s43
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, s56 :: v_dual_mov_b32 v2, s44
@@ -90573,78 +90096,61 @@ define inreg <64 x i8> @bitcast_v32bf16_to_v64i8_scalar(<32 x bfloat> inreg %a,
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v9, s10 :: v_dual_mov_b32 v10, s8
; GFX11-FAKE16-NEXT: v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s4
; GFX11-FAKE16-NEXT: .LBB109_5: ; %end
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v17, v12, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v15, v96, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-FAKE16-NEXT: v_perm_b32 v1, v16, v1, 0xc0c0004
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, v22, v11, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v17, v12, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v2, v14, v2, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, v27, v10, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v14, v15, v96, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v3, v20, v3, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v19, v87, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v23, v86, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v2, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v25, v85, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, v32, v9, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v11
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v11, 16, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v21, v84, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v21, v11, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v12, 16, v1
; GFX11-FAKE16-NEXT: v_perm_b32 v4, v18, v4, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v30, v83, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v14, v10
-; GFX11-FAKE16-NEXT: v_perm_b32 v14, v26, v82, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v19, v87, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v15, v25, v86, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v24, v10, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v16, v23, v85, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v22, v84, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v14, 16, v2
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v11, 16, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v12, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v10, 16, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v30, v83, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, v31, v9, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v27, v82, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v26, v81, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v18, v34, v80, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v8, v35, v8, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, v15, v12
-; GFX11-FAKE16-NEXT: v_perm_b32 v15, v29, v80, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v4, v4, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v11, v16, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, v24, v81, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-FAKE16-NEXT: v_perm_b32 v16, v34, v71, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v38, v7, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v28, v70, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v37, v69, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v12, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v8, v33, v68, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v17, v15
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v28, v71, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v29, v70, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v37, v69, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v36, v7, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v17, 16, v16
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v9, 16, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v17, v12, 16, v11
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, v32, v68, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, v33, v67, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v8, 16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v20, 16, v19
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, v22, 16, v21
+; GFX11-FAKE16-NEXT: v_perm_b32 v12, v53, v66, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v6, v48, v6, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v17, v39, v65, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v19, v38, v65, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v20, v39, v64, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v21, v50, v55, 0xc0c0004
; GFX11-FAKE16-NEXT: v_perm_b32 v5, v52, v5, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_perm_b32 v20, v51, v55, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v18, v7
-; GFX11-FAKE16-NEXT: v_perm_b32 v7, v31, v67, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v18, v53, v66, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v36, v64, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX11-FAKE16-NEXT: v_perm_b32 v22, v50, v54, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, v49, v13, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v20, 16, v20
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v17, v7, v8
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v18, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v19, v21
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v7, v22, v23
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v13, v20
+; GFX11-FAKE16-NEXT: v_perm_b32 v22, v49, v54, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_perm_b32 v13, v51, v13, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v18, v6, 16, v12
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v20, 16, v19
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v20, v5, 16, v21
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v21, v13, 16, v22
; GFX11-FAKE16-NEXT: v_readlane_b32 s30, v40, 8
; GFX11-FAKE16-NEXT: s_clause 0x3
; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[1:4], off
-; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[9:12], off offset:16
-; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[14:17], off offset:32
-; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[5:8], off offset:48
+; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[14:17], off offset:16
+; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[7:10], off offset:32
+; GFX11-FAKE16-NEXT: scratch_store_b128 v0, v[18:21], off offset:48
; GFX11-FAKE16-NEXT: v_readlane_b32 s31, v40, 9
; GFX11-FAKE16-NEXT: v_readlane_b32 s49, v40, 7
; GFX11-FAKE16-NEXT: v_readlane_b32 s48, v40, 6
@@ -94273,59 +93779,58 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX9-NEXT: v_perm_b32 v9, s12, v9, v8
; GFX9-NEXT: v_and_b32_e32 v7, 0xffff, v7
; GFX9-NEXT: v_lshl_or_b32 v7, v9, 16, v7
-; GFX9-NEXT: s_waitcnt vmcnt(18)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v16
+; GFX9-NEXT: s_waitcnt vmcnt(17)
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v17
; GFX9-NEXT: s_waitcnt vmcnt(16)
; GFX9-NEXT: v_perm_b32 v10, s72, v18, v8
-; GFX9-NEXT: v_or_b32_sdwa v9, v17, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v16, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v11, v9, 16, v10
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v26
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v9, v29, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v19
-; GFX9-NEXT: v_or_b32_sdwa v10, v21, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v29
+; GFX9-NEXT: v_lshl_or_b32 v9, v26, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v21
+; GFX9-NEXT: v_lshl_or_b32 v10, v19, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: s_mov_b32 s4, 0xc0c0004
; GFX9-NEXT: v_lshl_or_b32 v12, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v20
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v23
; GFX9-NEXT: v_perm_b32 v10, v31, v28, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v23, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v20, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
; GFX9-NEXT: v_lshl_or_b32 v13, v9, 16, v10
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v30
-; GFX9-NEXT: v_or_b32_sdwa v9, v33, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v10, 8, v22
-; GFX9-NEXT: v_or_b32_sdwa v10, v25, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v33
+; GFX9-NEXT: v_lshl_or_b32 v9, v30, 8, v9
+; GFX9-NEXT: v_and_b32_e32 v10, 0xff, v25
+; GFX9-NEXT: v_lshl_or_b32 v10, v22, 8, v10
; GFX9-NEXT: v_and_b32_e32 v9, 0xffff, v9
; GFX9-NEXT: v_lshl_or_b32 v14, v10, 16, v9
-; GFX9-NEXT: v_lshlrev_b32_e32 v9, 8, v24
+; GFX9-NEXT: v_and_b32_e32 v9, 0xff, v27
; GFX9-NEXT: v_perm_b32 v10, v34, v32, s4
-; GFX9-NEXT: v_or_b32_sdwa v9, v27, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v9, v24, 8, v9
; GFX9-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX9-NEXT: s_and_b32 s4, s47, 0xff
; GFX9-NEXT: v_lshl_or_b32 v15, v9, 16, v10
; GFX9-NEXT: v_mov_b32_e32 v9, s58
-; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
-; GFX9-NEXT: s_and_b32 s4, s47, 0xff
; GFX9-NEXT: s_lshl_b32 s5, s7, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s5
+; GFX9-NEXT: v_perm_b32 v8, s60, v9, v8
+; GFX9-NEXT: s_or_b32 s5, s5, s4
; GFX9-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX9-NEXT: v_lshl_or_b32 v9, s4, 16, v8
; GFX9-NEXT: s_and_b32 s4, s10, 0xff
+; GFX9-NEXT: v_lshl_or_b32 v9, s5, 16, v8
; GFX9-NEXT: s_lshl_b32 s5, s9, 8
-; GFX9-NEXT: s_or_b32 s4, s4, s5
-; GFX9-NEXT: s_and_b32 s5, s8, 0xff
+; GFX9-NEXT: s_or_b32 s5, s5, s4
+; GFX9-NEXT: s_and_b32 s4, s8, 0xff
; GFX9-NEXT: s_lshl_b32 s77, s6, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s5
+; GFX9-NEXT: s_or_b32 s77, s77, s4
+; GFX9-NEXT: s_pack_ll_b32_b16 s4, s5, s77
; GFX9-NEXT: s_and_b32 s5, s63, 0xff
; GFX9-NEXT: s_lshl_b32 s77, s61, 8
-; GFX9-NEXT: s_or_b32 s5, s5, s77
-; GFX9-NEXT: s_and_b32 s77, s57, 0xff
+; GFX9-NEXT: s_or_b32 s77, s77, s5
+; GFX9-NEXT: s_and_b32 s5, s57, 0xff
; GFX9-NEXT: s_lshl_b32 s78, s56, 8
-; GFX9-NEXT: s_or_b32 s77, s77, s78
-; GFX9-NEXT: s_pack_ll_b32_b16 s5, s5, s77
+; GFX9-NEXT: s_or_b32 s78, s78, s5
+; GFX9-NEXT: s_pack_ll_b32_b16 s5, s77, s78
; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: v_mov_b32_e32 v10, s5
; GFX9-NEXT: s_cbranch_execnz .LBB111_3
@@ -94550,83 +94055,77 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_and_b32 s76, vcc_lo, exec_lo
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB111_4
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v50
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-TRUE16-NEXT: s_and_b32 s76, s62, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s44, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v49
+; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s76
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s18, s19, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s8, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s14, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s8, 8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
+; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s78
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s41, s7, v8
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_and_b32 v13, 0xff, v38
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s46, 0xff
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s73, 0xff
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s79
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s26, s27, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
+; GFX11-TRUE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v7.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s56, 0xff
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s57, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s0, s1, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
+; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
+; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s12, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s73, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s78, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s79, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s88, s12, 8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
+; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s76
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
-; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
-; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v34, 8, v13
+; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s88, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xff, v37
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v12, v50, 8, s78
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v52
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v8.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v36
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v15, v31, 8, v13
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v14, v35, 8, v14
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v10, v48, 8, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v32, 8, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v15.l
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, s79
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v10.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s77
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s76
; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB111_3
; GFX11-TRUE16-NEXT: .LBB111_2: ; %cmp.true
@@ -94813,8 +94312,8 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, 0xc0c0004
; GFX11-FAKE16-NEXT: s_and_b32 s76, s58, 0xff
; GFX11-FAKE16-NEXT: s_lshl_b32 s77, s47, 8
-; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s41, 8
-; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s77
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v50
+; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s76
; GFX11-FAKE16-NEXT: v_perm_b32 v0, s0, s1, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v2, s16, s17, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v1, s2, s3, v8
@@ -94824,83 +94323,76 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: v_perm_b32 v9, s28, s29, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s77, s44, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s76, s44, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s46, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s79, s41, 8
; GFX11-FAKE16-NEXT: v_perm_b32 v5, s22, s23, v8
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
+; GFX11-FAKE16-NEXT: s_or_b32 s79, s79, s76
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s14, s11, v8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s40, s13, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
-; GFX11-FAKE16-NEXT: v_perm_b32 v4, s6, s4, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v12, s10, s8, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s46, 0xff
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s42, 8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v4, 16, v6
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_perm_b32 v5, s14, s11, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v12, 16, v9
-; GFX11-FAKE16-NEXT: v_perm_b32 v9, s60, s57, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v11, s43, s15, v8
-; GFX11-FAKE16-NEXT: s_and_b32 s77, s72, 0xff
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s56, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s45, 8
; GFX11-FAKE16-NEXT: v_and_b32_e32 v9, 0xffff, v9
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s79
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s6, s4, v8
; GFX11-FAKE16-NEXT: v_perm_b32 v7, s26, s27, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v10, s7, s5, v8
-; GFX11-FAKE16-NEXT: v_perm_b32 v13, s12, s9, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s78, 16, v9
-; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s62, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v11, s7, s5, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v5, 16, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, v6, 16, v9
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s43, s15, v8
+; GFX11-FAKE16-NEXT: s_lshl_b32 s76, s42, 8
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v7, 16, v3
-; GFX11-FAKE16-NEXT: s_or_b32 s77, s77, s78
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v13, 16, v11
-; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xff, v37
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v12, 8, v31
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v13, 0xff, v51
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v14, 8, v38
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v10, 16, v5
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v10, 8, v34
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v50
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v35
-; GFX11-FAKE16-NEXT: s_and_b32 s79, s61, 0xff
-; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v7, s40, s13, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v5, v11, 16, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v11, 0xffff, v6
+; GFX11-FAKE16-NEXT: v_perm_b32 v6, s60, s57, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s76, s76, s78
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s72, 0xff
+; GFX11-FAKE16-NEXT: s_and_b32 s88, s56, 0xff
+; GFX11-FAKE16-NEXT: s_lshl_b32 s89, s62, 8
+; GFX11-FAKE16-NEXT: v_perm_b32 v9, s10, s8, v8
+; GFX11-FAKE16-NEXT: s_or_b32 s89, s89, s78
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xffff, v7
+; GFX11-FAKE16-NEXT: v_perm_b32 v10, s12, s9, v8
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xffff, v6
+; GFX11-FAKE16-NEXT: s_lshl_b32 s78, s45, 8
; GFX11-FAKE16-NEXT: v_perm_b32 v8, s73, s63, v8
-; GFX11-FAKE16-NEXT: s_or_b32 s78, s79, s88
+; GFX11-FAKE16-NEXT: s_or_b32 s78, s78, s88
; GFX11-FAKE16-NEXT: s_and_b32 s79, s74, 0xff
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v12, v11, v12
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v10, s79, v10
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v9, 16, v7
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v7, v10, 16, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v9, s76, 16, v12
+; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v34, 8, s79
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v51
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xff, v37
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v35, 8, v13
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v16, 0xff, v49
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v11
; GFX11-FAKE16-NEXT: v_perm_b32 v11, v53, v48, 0xc0c0004
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v13, v13, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v15, 0xff, v39
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xff, v49
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v18, 8, v32
-; GFX11-FAKE16-NEXT: v_perm_b32 v19, v52, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v38, 8, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v12, 0xff, v39
+; GFX11-FAKE16-NEXT: v_perm_b32 v17, v52, v36, 0xc0c0004
+; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s76, s89, s78
+; GFX11-FAKE16-NEXT: s_and_b32 s78, s61, 0xff
; GFX11-FAKE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v10, 0xffff, v10
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v11
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v15, v15, v16
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v14, 0xffff, v14
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v16, v17, v18
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v19
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s78, 16, v8
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v12, 16, v10
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v13, 16, v20
-; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v15, 16, v14
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v31, 8, v10
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v18, 0xffff, v11
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v19, v33, 8, v12
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v20, 0xffff, v13
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v16, v32, 8, v16
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; GFX11-FAKE16-NEXT: s_lshl_b32 s88, s59, 8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v12, v10, 16, v14
+; GFX11-FAKE16-NEXT: s_or_b32 s88, s88, s78
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v13, v15, 16, v18
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s88, 16, v8
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v14, v19, 16, v20
; GFX11-FAKE16-NEXT: v_lshl_or_b32 v15, v16, 16, v17
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s76
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s77
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, s77
+; GFX11-FAKE16-NEXT: v_mov_b32_e32 v10, s76
; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s75
; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB111_3
; GFX11-FAKE16-NEXT: .LBB111_2: ; %cmp.true
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
index 77c047f492cac..6a31f220d0077 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.64bit.ll
@@ -3402,19 +3402,17 @@ define inreg i64 @bitcast_v8i8_to_i64_scalar(<8 x i8> inreg %a, i32 inreg %b) #0
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB27_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB27_3
; GFX9-NEXT: .LBB27_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -3451,17 +3449,14 @@ define inreg i64 @bitcast_v8i8_to_i64_scalar(<8 x i8> inreg %a, i32 inreg %b) #0
; GFX11-NEXT: s_cbranch_scc0 .LBB27_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v2, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v3, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v4, s16, s17, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB27_3
; GFX11-NEXT: .LBB27_2: ; %cmp.true
@@ -6580,19 +6575,17 @@ define inreg double @bitcast_v8i8_to_f64_scalar(<8 x i8> inreg %a, i32 inreg %b)
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB51_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB51_3
; GFX9-NEXT: .LBB51_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -6629,17 +6622,14 @@ define inreg double @bitcast_v8i8_to_f64_scalar(<8 x i8> inreg %a, i32 inreg %b)
; GFX11-NEXT: s_cbranch_scc0 .LBB51_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v2, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v3, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v4, s16, s17, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB51_3
; GFX11-NEXT: .LBB51_2: ; %cmp.true
@@ -9437,19 +9427,17 @@ define inreg <2 x i32> @bitcast_v8i8_to_v2i32_scalar(<8 x i8> inreg %a, i32 inre
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB71_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB71_3
; GFX9-NEXT: .LBB71_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9486,17 +9474,14 @@ define inreg <2 x i32> @bitcast_v8i8_to_v2i32_scalar(<8 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_cbranch_scc0 .LBB71_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v2, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v3, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v4, s16, s17, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB71_3
; GFX11-NEXT: .LBB71_2: ; %cmp.true
@@ -12003,19 +11988,17 @@ define inreg <2 x float> @bitcast_v8i8_to_v2f32_scalar(<8 x i8> inreg %a, i32 in
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB87_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB87_3
; GFX9-NEXT: .LBB87_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -12052,17 +12035,14 @@ define inreg <2 x float> @bitcast_v8i8_to_v2f32_scalar(<8 x i8> inreg %a, i32 in
; GFX11-NEXT: s_cbranch_scc0 .LBB87_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v2, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v3, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v4, s16, s17, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB87_3
; GFX11-NEXT: .LBB87_2: ; %cmp.true
@@ -14278,19 +14258,17 @@ define inreg <4 x i16> @bitcast_v8i8_to_v4i16_scalar(<8 x i8> inreg %a, i32 inre
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB99_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB99_3
; GFX9-NEXT: .LBB99_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -14327,17 +14305,14 @@ define inreg <4 x i16> @bitcast_v8i8_to_v4i16_scalar(<8 x i8> inreg %a, i32 inre
; GFX11-NEXT: s_cbranch_scc0 .LBB99_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v2, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v3, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v4, s16, s17, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB99_3
; GFX11-NEXT: .LBB99_2: ; %cmp.true
@@ -16147,19 +16122,17 @@ define inreg <4 x half> @bitcast_v8i8_to_v4f16_scalar(<8 x i8> inreg %a, i32 inr
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB107_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB107_3
; GFX9-NEXT: .LBB107_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -16196,17 +16169,14 @@ define inreg <4 x half> @bitcast_v8i8_to_v4f16_scalar(<8 x i8> inreg %a, i32 inr
; GFX11-NEXT: s_cbranch_scc0 .LBB107_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v2, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v3, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v4, s16, s17, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB107_3
; GFX11-NEXT: .LBB107_2: ; %cmp.true
@@ -17506,19 +17476,17 @@ define inreg <4 x bfloat> @bitcast_v8i8_to_v4bf16_scalar(<8 x i8> inreg %a, i32
; GFX9-NEXT: s_cmp_lg_u32 s24, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB111_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v2, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_perm_b32 v2, s18, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s21
; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v2, s20, v2, v1
; GFX9-NEXT: v_perm_b32 v1, s22, v3, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v1, v1, 16, v2
; GFX9-NEXT: s_cbranch_execnz .LBB111_3
; GFX9-NEXT: .LBB111_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -17555,17 +17523,14 @@ define inreg <4 x bfloat> @bitcast_v8i8_to_v4bf16_scalar(<8 x i8> inreg %a, i32
; GFX11-NEXT: s_cbranch_scc0 .LBB111_4
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-NEXT: v_perm_b32 v1, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v2, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v3, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v4, s16, s17, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v2
-; GFX11-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-NEXT: v_or_b32_e32 v1, v4, v1
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB111_3
; GFX11-NEXT: .LBB111_2: ; %cmp.true
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
index a1c0db086bf3c..edb84a81313ec 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.96bit.ll
@@ -1438,25 +1438,22 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB7_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: s_cbranch_execnz .LBB7_3
; GFX9-NEXT: .LBB7_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -1503,20 +1500,16 @@ define inreg <3 x i32> @bitcast_v12i8_to_v3i32_scalar(<12 x i8> inreg %a, i32 in
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v4, s22, s23, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v5, s16, s17, v0
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v3
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB7_3
; GFX11-NEXT: .LBB7_2: ; %cmp.true
@@ -4601,25 +4594,22 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB23_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: s_cbranch_execnz .LBB23_3
; GFX9-NEXT: .LBB23_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -4666,20 +4656,16 @@ define inreg <3 x float> @bitcast_v12i8_to_v3f32_scalar(<12 x i8> inreg %a, i32
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v4, s22, s23, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v5, s16, s17, v0
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v3
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB23_3
; GFX11-NEXT: .LBB23_2: ; %cmp.true
@@ -7305,25 +7291,22 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB37_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: s_cbranch_execnz .LBB37_3
; GFX9-NEXT: .LBB37_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -7370,20 +7353,16 @@ define inreg <6 x bfloat> @bitcast_v12i8_to_v6bf16_scalar(<12 x i8> inreg %a, i3
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v4, s22, s23, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v5, s16, s17, v0
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v3
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB37_3
; GFX11-NEXT: .LBB37_2: ; %cmp.true
@@ -9132,25 +9111,22 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB41_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: s_cbranch_execnz .LBB41_3
; GFX9-NEXT: .LBB41_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -9197,20 +9173,16 @@ define inreg <6 x half> @bitcast_v12i8_to_v6f16_scalar(<12 x i8> inreg %a, i32 i
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v4, s22, s23, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v5, s16, s17, v0
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v3
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB41_3
; GFX11-NEXT: .LBB41_2: ; %cmp.true
@@ -10495,25 +10467,22 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX9-NEXT: s_cmp_lg_u32 s28, 0
; GFX9-NEXT: s_cbranch_scc0 .LBB45_4
; GFX9-NEXT: ; %bb.1: ; %cmp.false
+; GFX9-NEXT: v_mov_b32_e32 v0, s17
; GFX9-NEXT: v_mov_b32_e32 v2, 0xc0c0004
; GFX9-NEXT: v_mov_b32_e32 v1, s19
-; GFX9-NEXT: v_mov_b32_e32 v0, s17
-; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
; GFX9-NEXT: v_perm_b32 v0, s16, v0, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_mov_b32_e32 v3, s23
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_perm_b32 v1, s18, v1, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s21
-; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_mov_b32_e32 v3, s23
; GFX9-NEXT: v_perm_b32 v1, s20, v1, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX9-NEXT: v_perm_b32 v3, s22, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
; GFX9-NEXT: v_mov_b32_e32 v3, s25
; GFX9-NEXT: v_mov_b32_e32 v4, s27
; GFX9-NEXT: v_perm_b32 v3, s24, v3, v2
; GFX9-NEXT: v_perm_b32 v2, s26, v4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX9-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v3
; GFX9-NEXT: s_cbranch_execnz .LBB45_3
; GFX9-NEXT: .LBB45_2: ; %cmp.true
; GFX9-NEXT: s_add_i32 s16, s16, 3
@@ -10560,20 +10529,16 @@ define inreg <6 x i16> @bitcast_v12i8_to_v6i16_scalar(<12 x i8> inreg %a, i32 in
; GFX11-NEXT: ; %bb.1: ; %cmp.false
; GFX11-NEXT: v_mov_b32_e32 v0, 0xc0c0004
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
-; GFX11-NEXT: v_perm_b32 v3, s18, s19, v0
-; GFX11-NEXT: v_perm_b32 v4, s22, s23, v0
; GFX11-NEXT: v_perm_b32 v1, s0, s1, v0
-; GFX11-NEXT: v_perm_b32 v5, s16, s17, v0
-; GFX11-NEXT: v_perm_b32 v6, s20, s21, v0
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 16, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v5, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-NEXT: v_or_b32_e32 v2, v6, v3
+; GFX11-NEXT: v_perm_b32 v2, s2, s3, v0
+; GFX11-NEXT: v_perm_b32 v3, s16, s17, v0
+; GFX11-NEXT: v_perm_b32 v4, s18, s19, v0
+; GFX11-NEXT: v_perm_b32 v5, s20, s21, v0
+; GFX11-NEXT: v_perm_b32 v6, s22, s23, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v1
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-NEXT: v_lshl_or_b32 v1, v4, 16, v3
+; GFX11-NEXT: v_lshl_or_b32 v2, v6, 16, v5
; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
; GFX11-NEXT: s_cbranch_vccnz .LBB45_3
; GFX11-NEXT: .LBB45_2: ; %cmp.true
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
index b883f82c0ca27..cda20e5a04c9c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
@@ -4695,12 +4695,11 @@ define amdgpu_kernel void @udiv_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v0
; GFX9-NEXT: v_mad_f32 v0, -v0, v1, v6
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1
-; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
+; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v5, vcc
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
-; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 15, v3
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
@@ -4885,21 +4884,20 @@ define amdgpu_kernel void @urem_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: v_cvt_u32_f32_e32 v5, v4
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: v_mad_f32 v4, -v4, v3, v6
-; GFX9-NEXT: s_lshr_b32 s4, s6, 15
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v4|, v3
+; GFX9-NEXT: s_lshr_b32 s4, s6, 15
+; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v0, v0, s6
; GFX9-NEXT: v_mul_lo_u32 v1, v1, s4
-; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v5, vcc
; GFX9-NEXT: v_mul_lo_u32 v3, v3, s3
; GFX9-NEXT: s_lshr_b32 s3, s2, 15
; GFX9-NEXT: v_sub_u32_e32 v4, s2, v0
; GFX9-NEXT: v_sub_u32_e32 v5, s3, v1
; GFX9-NEXT: v_sub_u32_e32 v0, s8, v3
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v4
; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v5
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 15, v3
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
@@ -5114,11 +5112,10 @@ define amdgpu_kernel void @sdiv_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: s_and_b64 s[2:3], s[2:3], exec
; GFX9-NEXT: s_cselect_b32 s2, s4, 0
; GFX9-NEXT: v_add_u32_e32 v0, s2, v5
-; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fff, v3
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v4
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 15, v3
; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
; GFX9-NEXT: global_store_dword v2, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
@@ -5359,11 +5356,10 @@ define amdgpu_kernel void @srem_v3i15(ptr addrspace(1) %out, <3 x i15> %x, <3 x
; GFX9-NEXT: v_sub_u32_e32 v5, s3, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: v_sub_u32_e32 v0, s9, v2
+; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
; GFX9-NEXT: v_and_b32_e32 v2, 0x7fff, v4
; GFX9-NEXT: v_and_b32_e32 v4, 0x7fff, v5
-; GFX9-NEXT: v_lshlrev_b64 v[0:1], 30, v[0:1]
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 15, v4
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v4
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 15, v2
; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
; GFX9-NEXT: global_store_dword v3, v0, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v0, 0x1fff, v1
diff --git a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
index 77ee1ada2af94..4819a5272efe0 100644
--- a/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
+++ b/llvm/test/CodeGen/AMDGPU/calling-conventions.ll
@@ -1488,14 +1488,15 @@ define amdgpu_kernel void @amd_kernel_v2i8(<2 x i8> %arg0) {
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_bfe_u32 s1, s0, 0x80008
+; GFX11-NEXT: s_add_i32 s1, s0, s0
+; GFX11-NEXT: s_bfe_u32 s0, s0, 0x80008
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_add_i32 s0, s0, s0
-; GFX11-NEXT: s_add_i32 s1, s1, s1
-; GFX11-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-NEXT: s_lshl_b32 s1, s1, 8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: v_mov_b32_e32 v2, s0
+; GFX11-NEXT: s_lshl_b32 s2, s0, 8
+; GFX11-NEXT: s_or_b32 s2, s2, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
@@ -1505,14 +1506,15 @@ define amdgpu_kernel void @amd_kernel_v2i8(<2 x i8> %arg0) {
; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x24 nv
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_bfe_u32 s1, s0, 0x80008
+; GFX1250-NEXT: s_add_co_i32 s1, s0, s0
+; GFX1250-NEXT: s_bfe_u32 s0, s0, 0x80008
+; GFX1250-NEXT: s_and_b32 s1, s1, 0xff
; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
-; GFX1250-NEXT: s_add_co_i32 s1, s1, s1
-; GFX1250-NEXT: s_and_b32 s0, s0, 0xff
-; GFX1250-NEXT: s_lshl_b32 s1, s1, 8
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: v_mov_b32_e32 v2, s0
+; GFX1250-NEXT: s_lshl_b32 s2, s0, 8
+; GFX1250-NEXT: s_or_b32 s2, s2, s1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: v_mov_b32_e32 v2, s2
; GFX1250-NEXT: global_store_b16 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
entry:
@@ -1580,23 +1582,24 @@ define amdgpu_kernel void @amd_kernel_v4i8(<4 x i8> %arg0) {
; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x24
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s1, s0, 16
-; GFX11-NEXT: s_lshr_b32 s2, s0, 24
-; GFX11-NEXT: s_add_i32 s3, s0, s0
-; GFX11-NEXT: s_bfe_u32 s0, s0, 0x80008
-; GFX11-NEXT: s_add_i32 s2, s2, s2
+; GFX11-NEXT: s_lshr_b32 s2, s0, 16
+; GFX11-NEXT: s_lshr_b32 s1, s0, 24
+; GFX11-NEXT: s_bfe_u32 s3, s0, 0x80008
; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: s_add_i32 s2, s2, s2
; GFX11-NEXT: s_add_i32 s1, s1, s1
-; GFX11-NEXT: s_and_b32 s3, s3, 0xff
-; GFX11-NEXT: s_lshl_b32 s0, s0, 8
-; GFX11-NEXT: s_lshl_b32 s2, s2, 8
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_or_b32 s0, s3, s0
-; GFX11-NEXT: s_or_b32 s1, s1, s2
-; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX11-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_add_i32 s3, s3, s3
+; GFX11-NEXT: s_lshl_b32 s4, s1, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s4, s4, s2
+; GFX11-NEXT: s_lshl_b32 s1, s3, 8
+; GFX11-NEXT: s_or_b32 s1, s1, s0
+; GFX11-NEXT: s_lshl_b32 s0, s4, 16
+; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: s_or_b32 s0, s1, s0
; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b32 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
@@ -1607,23 +1610,24 @@ define amdgpu_kernel void @amd_kernel_v4i8(<4 x i8> %arg0) {
; GFX1250-NEXT: s_load_b32 s0, s[4:5], 0x24 nv
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s1, s0, 16
-; GFX1250-NEXT: s_lshr_b32 s2, s0, 24
-; GFX1250-NEXT: s_add_co_i32 s3, s0, s0
-; GFX1250-NEXT: s_bfe_u32 s0, s0, 0x80008
-; GFX1250-NEXT: s_add_co_i32 s2, s2, s2
+; GFX1250-NEXT: s_lshr_b32 s2, s0, 16
+; GFX1250-NEXT: s_lshr_b32 s1, s0, 24
+; GFX1250-NEXT: s_bfe_u32 s3, s0, 0x80008
; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
+; GFX1250-NEXT: s_add_co_i32 s2, s2, s2
; GFX1250-NEXT: s_add_co_i32 s1, s1, s1
-; GFX1250-NEXT: s_and_b32 s3, s3, 0xff
-; GFX1250-NEXT: s_lshl_b32 s0, s0, 8
-; GFX1250-NEXT: s_lshl_b32 s2, s2, 8
-; GFX1250-NEXT: s_and_b32 s1, s1, 0xff
-; GFX1250-NEXT: s_or_b32 s0, s3, s0
-; GFX1250-NEXT: s_or_b32 s1, s1, s2
-; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
+; GFX1250-NEXT: s_and_b32 s0, s0, 0xff
+; GFX1250-NEXT: s_and_b32 s2, s2, 0xff
+; GFX1250-NEXT: s_add_co_i32 s3, s3, s3
+; GFX1250-NEXT: s_lshl_b32 s4, s1, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s4, s4, s2
+; GFX1250-NEXT: s_lshl_b32 s1, s3, 8
+; GFX1250-NEXT: s_or_b32 s1, s1, s0
+; GFX1250-NEXT: s_lshl_b32 s0, s4, 16
+; GFX1250-NEXT: s_and_b32 s1, s1, 0xffff
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
+; GFX1250-NEXT: s_or_b32 s0, s1, s0
; GFX1250-NEXT: v_mov_b32_e32 v2, s0
; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
; GFX1250-NEXT: s_endpgm
@@ -1686,15 +1690,16 @@ define amdgpu_kernel void @amd_kernel_v3i8(<3 x i8> %arg0) {
; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_bfe_u32 s2, s0, 0x80008
-; GFX11-NEXT: s_lshr_b32 s1, s0, 16
-; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: s_add_i32 s1, s0, s0
; GFX11-NEXT: s_add_i32 s2, s2, s2
-; GFX11-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-NEXT: s_lshl_b32 s2, s2, 8
-; GFX11-NEXT: s_add_i32 s1, s1, s1
-; GFX11-NEXT: s_or_b32 s0, s0, s2
-; GFX11-NEXT: v_mov_b32_e32 v4, s1
-; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s0
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_lshr_b32 s0, s0, 16
+; GFX11-NEXT: s_lshl_b32 s3, s2, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s3, s3, s1
+; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s3
+; GFX11-NEXT: v_mov_b32_e32 v4, s0
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b8 v[0:1], v4, off
; GFX11-NEXT: global_store_b16 v[2:3], v5, off
@@ -1708,15 +1713,15 @@ define amdgpu_kernel void @amd_kernel_v3i8(<3 x i8> %arg0) {
; GFX1250-NEXT: v_mov_b64_e32 v[2:3], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_bfe_u32 s2, s0, 0x80008
-; GFX1250-NEXT: s_lshr_b32 s1, s0, 16
-; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
+; GFX1250-NEXT: s_add_co_i32 s1, s0, s0
; GFX1250-NEXT: s_add_co_i32 s2, s2, s2
-; GFX1250-NEXT: s_and_b32 s0, s0, 0xff
-; GFX1250-NEXT: s_lshl_b32 s2, s2, 8
-; GFX1250-NEXT: s_add_co_i32 s1, s1, s1
-; GFX1250-NEXT: s_or_b32 s0, s0, s2
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s0
+; GFX1250-NEXT: s_and_b32 s1, s1, 0xff
+; GFX1250-NEXT: s_lshr_b32 s0, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s3, s2, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s3, s3, s1
+; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
+; GFX1250-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s0
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: global_store_b8 v[0:1], v4, off
; GFX1250-NEXT: global_store_b16 v[2:3], v5, off
@@ -1797,23 +1802,24 @@ define amdgpu_kernel void @amd_kernel_v5i8(<5 x i8> %arg0) {
; GFX11-NEXT: v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: v_mov_b32_e32 v3, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-NEXT: s_lshr_b32 s3, s0, 24
-; GFX11-NEXT: s_add_i32 s4, s0, s0
-; GFX11-NEXT: s_bfe_u32 s0, s0, 0x80008
-; GFX11-NEXT: s_add_i32 s3, s3, s3
+; GFX11-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-NEXT: s_bfe_u32 s4, s0, 0x80008
+; GFX11-NEXT: s_lshr_b32 s2, s0, 24
; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: s_add_i32 s3, s3, s3
+; GFX11-NEXT: s_add_i32 s4, s4, s4
; GFX11-NEXT: s_add_i32 s2, s2, s2
-; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: s_lshl_b32 s0, s0, 8
-; GFX11-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: s_or_b32 s0, s4, s0
-; GFX11-NEXT: s_or_b32 s2, s2, s3
-; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX11-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_and_b32 s3, s3, 0xff
+; GFX11-NEXT: s_lshl_b32 s5, s4, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s5, s5, s0
+; GFX11-NEXT: s_lshl_b32 s0, s2, 8
+; GFX11-NEXT: s_or_b32 s0, s0, s3
+; GFX11-NEXT: s_and_b32 s2, s5, 0xffff
+; GFX11-NEXT: s_lshl_b32 s0, s0, 16
; GFX11-NEXT: s_add_i32 s1, s1, s1
-; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_or_b32 s0, s2, s0
; GFX11-NEXT: v_mov_b32_e32 v4, s1
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s0
; GFX11-NEXT: s_clause 0x1
@@ -1828,23 +1834,24 @@ define amdgpu_kernel void @amd_kernel_v5i8(<5 x i8> %arg0) {
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 4
; GFX1250-NEXT: v_mov_b64_e32 v[2:3], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s2, s0, 16
-; GFX1250-NEXT: s_lshr_b32 s3, s0, 24
-; GFX1250-NEXT: s_add_co_i32 s4, s0, s0
-; GFX1250-NEXT: s_bfe_u32 s0, s0, 0x80008
-; GFX1250-NEXT: s_add_co_i32 s3, s3, s3
+; GFX1250-NEXT: s_lshr_b32 s3, s0, 16
+; GFX1250-NEXT: s_bfe_u32 s4, s0, 0x80008
+; GFX1250-NEXT: s_lshr_b32 s2, s0, 24
; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
+; GFX1250-NEXT: s_add_co_i32 s3, s3, s3
+; GFX1250-NEXT: s_add_co_i32 s4, s4, s4
; GFX1250-NEXT: s_add_co_i32 s2, s2, s2
-; GFX1250-NEXT: s_and_b32 s4, s4, 0xff
-; GFX1250-NEXT: s_lshl_b32 s0, s0, 8
-; GFX1250-NEXT: s_lshl_b32 s3, s3, 8
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xff
-; GFX1250-NEXT: s_or_b32 s0, s4, s0
-; GFX1250-NEXT: s_or_b32 s2, s2, s3
-; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s2, s2, 16
+; GFX1250-NEXT: s_and_b32 s0, s0, 0xff
+; GFX1250-NEXT: s_and_b32 s3, s3, 0xff
+; GFX1250-NEXT: s_lshl_b32 s5, s4, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s5, s5, s0
+; GFX1250-NEXT: s_lshl_b32 s0, s2, 8
+; GFX1250-NEXT: s_or_b32 s0, s0, s3
+; GFX1250-NEXT: s_and_b32 s2, s5, 0xffff
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
; GFX1250-NEXT: s_add_co_i32 s1, s1, s1
-; GFX1250-NEXT: s_or_b32 s0, s0, s2
+; GFX1250-NEXT: s_or_b32 s0, s2, s0
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v5, s0
; GFX1250-NEXT: s_clause 0x1
@@ -1948,86 +1955,90 @@ define amdgpu_kernel void @amd_kernel_v8i8(<8 x i8> %arg0) {
; GFX11-LABEL: amd_kernel_v8i8:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-NEXT: v_mov_b32_e32 v3, 0
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-NEXT: s_lshr_b32 s3, s0, 24
-; GFX11-NEXT: s_lshr_b32 s4, s1, 16
-; GFX11-NEXT: s_lshr_b32 s5, s1, 24
-; GFX11-NEXT: s_bfe_u32 s6, s0, 0x80008
+; GFX11-NEXT: s_lshr_b32 s5, s1, 16
; GFX11-NEXT: s_bfe_u32 s7, s1, 0x80008
+; GFX11-NEXT: s_lshr_b32 s2, s0, 24
+; GFX11-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-NEXT: s_lshr_b32 s4, s1, 24
+; GFX11-NEXT: s_bfe_u32 s6, s0, 0x80008
; GFX11-NEXT: s_add_i32 s1, s1, s1
; GFX11-NEXT: s_add_i32 s0, s0, s0
-; GFX11-NEXT: s_add_i32 s7, s7, s7
; GFX11-NEXT: s_add_i32 s5, s5, s5
+; GFX11-NEXT: s_add_i32 s7, s7, s7
; GFX11-NEXT: s_add_i32 s4, s4, s4
-; GFX11-NEXT: s_add_i32 s6, s6, s6
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_add_i32 s3, s3, s3
; GFX11-NEXT: s_add_i32 s2, s2, s2
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
; GFX11-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-NEXT: s_lshl_b32 s7, s7, 8
-; GFX11-NEXT: s_lshl_b32 s5, s5, 8
-; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: s_lshl_b32 s6, s6, 8
-; GFX11-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: s_or_b32 s1, s1, s7
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_or_b32 s0, s0, s6
-; GFX11-NEXT: s_or_b32 s2, s2, s3
-; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
-; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX11-NEXT: s_lshl_b32 s2, s2, 16
-; GFX11-NEXT: s_lshl_b32 s3, s4, 16
-; GFX11-NEXT: s_or_b32 s0, s0, s2
-; GFX11-NEXT: s_or_b32 s1, s1, s3
-; GFX11-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX11-NEXT: s_add_i32 s6, s6, s6
+; GFX11-NEXT: s_and_b32 s5, s5, 0xff
+; GFX11-NEXT: s_lshl_b32 s8, s7, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s8, s8, s1
+; GFX11-NEXT: s_and_b32 s1, s3, 0xff
+; GFX11-NEXT: s_lshl_b32 s3, s6, 8
+; GFX11-NEXT: s_or_b32 s3, s3, s0
+; GFX11-NEXT: s_lshl_b32 s0, s2, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: s_lshl_b32 s1, s4, 8
+; GFX11-NEXT: s_or_b32 s1, s1, s5
+; GFX11-NEXT: s_and_b32 s2, s8, 0xffff
+; GFX11-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX11-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-NEXT: s_lshl_b32 s1, s1, 16
+; GFX11-NEXT: s_or_b32 s0, s3, s0
+; GFX11-NEXT: s_or_b32 s1, s2, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX11-NEXT: s_endpgm
;
; GFX1250-LABEL: amd_kernel_v8i8:
; GFX1250: ; %bb.0: ; %entry
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
-; GFX1250-NEXT: v_mov_b64_e32 v[2:3], 0
+; GFX1250-NEXT: v_mov_b64_e32 v[0:1], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s2, s0, 16
-; GFX1250-NEXT: s_lshr_b32 s3, s0, 24
-; GFX1250-NEXT: s_lshr_b32 s4, s1, 16
-; GFX1250-NEXT: s_lshr_b32 s5, s1, 24
-; GFX1250-NEXT: s_bfe_u32 s6, s0, 0x80008
+; GFX1250-NEXT: s_lshr_b32 s5, s1, 16
; GFX1250-NEXT: s_bfe_u32 s7, s1, 0x80008
+; GFX1250-NEXT: s_lshr_b32 s2, s0, 24
+; GFX1250-NEXT: s_lshr_b32 s3, s0, 16
+; GFX1250-NEXT: s_lshr_b32 s4, s1, 24
+; GFX1250-NEXT: s_bfe_u32 s6, s0, 0x80008
; GFX1250-NEXT: s_add_co_i32 s1, s1, s1
; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
-; GFX1250-NEXT: s_add_co_i32 s7, s7, s7
; GFX1250-NEXT: s_add_co_i32 s5, s5, s5
+; GFX1250-NEXT: s_add_co_i32 s7, s7, s7
; GFX1250-NEXT: s_add_co_i32 s4, s4, s4
-; GFX1250-NEXT: s_add_co_i32 s6, s6, s6
+; GFX1250-NEXT: s_and_b32 s1, s1, 0xff
; GFX1250-NEXT: s_add_co_i32 s3, s3, s3
; GFX1250-NEXT: s_add_co_i32 s2, s2, s2
-; GFX1250-NEXT: s_and_b32 s1, s1, 0xff
; GFX1250-NEXT: s_and_b32 s0, s0, 0xff
-; GFX1250-NEXT: s_lshl_b32 s7, s7, 8
-; GFX1250-NEXT: s_lshl_b32 s5, s5, 8
-; GFX1250-NEXT: s_and_b32 s4, s4, 0xff
-; GFX1250-NEXT: s_lshl_b32 s6, s6, 8
-; GFX1250-NEXT: s_lshl_b32 s3, s3, 8
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xff
-; GFX1250-NEXT: s_or_b32 s1, s1, s7
-; GFX1250-NEXT: s_or_b32 s4, s4, s5
-; GFX1250-NEXT: s_or_b32 s0, s0, s6
-; GFX1250-NEXT: s_or_b32 s2, s2, s3
-; GFX1250-NEXT: s_and_b32 s1, s1, 0xffff
-; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s2, s2, 16
-; GFX1250-NEXT: s_lshl_b32 s3, s4, 16
-; GFX1250-NEXT: s_or_b32 s0, s0, s2
-; GFX1250-NEXT: s_or_b32 s1, s1, s3
+; GFX1250-NEXT: s_add_co_i32 s6, s6, s6
+; GFX1250-NEXT: s_and_b32 s5, s5, 0xff
+; GFX1250-NEXT: s_lshl_b32 s8, s7, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s8, s8, s1
+; GFX1250-NEXT: s_and_b32 s1, s3, 0xff
+; GFX1250-NEXT: s_lshl_b32 s3, s6, 8
+; GFX1250-NEXT: s_or_b32 s3, s3, s0
+; GFX1250-NEXT: s_lshl_b32 s0, s2, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s0, s0, s1
+; GFX1250-NEXT: s_lshl_b32 s1, s4, 8
+; GFX1250-NEXT: s_or_b32 s1, s1, s5
+; GFX1250-NEXT: s_and_b32 s2, s8, 0xffff
+; GFX1250-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
+; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
+; GFX1250-NEXT: s_or_b32 s0, s3, s0
+; GFX1250-NEXT: s_or_b32 s1, s2, s1
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX1250-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off
; GFX1250-NEXT: s_endpgm
entry:
%add = add <8 x i8> %arg0, %arg0
@@ -2196,74 +2207,78 @@ define amdgpu_kernel void @amd_kernel_v16i8(<16 x i8> %arg0) {
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: v_mov_b32_e32 v5, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s6, s1, 16
-; GFX11-NEXT: s_lshr_b32 s7, s1, 24
-; GFX11-NEXT: s_lshr_b32 s8, s2, 16
-; GFX11-NEXT: s_lshr_b32 s9, s2, 24
-; GFX11-NEXT: s_lshr_b32 s10, s3, 16
-; GFX11-NEXT: s_lshr_b32 s11, s3, 24
-; GFX11-NEXT: s_lshr_b32 s4, s0, 16
-; GFX11-NEXT: s_lshr_b32 s5, s0, 24
-; GFX11-NEXT: s_bfe_u32 s12, s0, 0x80008
-; GFX11-NEXT: s_bfe_u32 s13, s1, 0x80008
-; GFX11-NEXT: s_bfe_u32 s14, s2, 0x80008
+; GFX11-NEXT: s_lshr_b32 s11, s3, 16
; GFX11-NEXT: s_bfe_u32 s15, s3, 0x80008
+; GFX11-NEXT: s_lshr_b32 s8, s2, 24
+; GFX11-NEXT: s_lshr_b32 s9, s2, 16
+; GFX11-NEXT: s_lshr_b32 s10, s3, 24
+; GFX11-NEXT: s_bfe_u32 s14, s2, 0x80008
+; GFX11-NEXT: s_add_i32 s3, s3, s3
+; GFX11-NEXT: s_add_i32 s2, s2, s2
; GFX11-NEXT: s_add_i32 s11, s11, s11
+; GFX11-NEXT: s_add_i32 s15, s15, s15
+; GFX11-NEXT: s_lshr_b32 s4, s0, 24
+; GFX11-NEXT: s_lshr_b32 s5, s0, 16
+; GFX11-NEXT: s_lshr_b32 s6, s1, 24
+; GFX11-NEXT: s_lshr_b32 s7, s1, 16
+; GFX11-NEXT: s_bfe_u32 s12, s0, 0x80008
+; GFX11-NEXT: s_bfe_u32 s13, s1, 0x80008
; GFX11-NEXT: s_add_i32 s10, s10, s10
+; GFX11-NEXT: s_and_b32 s3, s3, 0xff
; GFX11-NEXT: s_add_i32 s9, s9, s9
; GFX11-NEXT: s_add_i32 s8, s8, s8
+; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_add_i32 s14, s14, s14
+; GFX11-NEXT: s_and_b32 s11, s11, 0xff
+; GFX11-NEXT: s_lshl_b32 s16, s15, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s16, s16, s3
+; GFX11-NEXT: s_and_b32 s3, s9, 0xff
+; GFX11-NEXT: s_lshl_b32 s9, s14, 8
+; GFX11-NEXT: s_or_b32 s9, s9, s2
+; GFX11-NEXT: s_lshl_b32 s2, s10, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s2, s2, s11
+; GFX11-NEXT: s_lshl_b32 s10, s8, 8
+; GFX11-NEXT: s_or_b32 s10, s10, s3
; GFX11-NEXT: s_add_i32 s7, s7, s7
+; GFX11-NEXT: s_and_b32 s3, s16, 0xffff
+; GFX11-NEXT: s_lshl_b32 s2, s2, 16
; GFX11-NEXT: s_add_i32 s6, s6, s6
-; GFX11-NEXT: s_add_i32 s3, s3, s3
-; GFX11-NEXT: s_add_i32 s2, s2, s2
-; GFX11-NEXT: s_add_i32 s15, s15, s15
-; GFX11-NEXT: s_add_i32 s14, s14, s14
-; GFX11-NEXT: s_lshl_b32 s11, s11, 8
-; GFX11-NEXT: s_and_b32 s10, s10, 0xff
-; GFX11-NEXT: s_lshl_b32 s9, s9, 8
-; GFX11-NEXT: s_and_b32 s8, s8, 0xff
+; GFX11-NEXT: s_and_b32 s8, s9, 0xffff
+; GFX11-NEXT: s_lshl_b32 s9, s10, 16
+; GFX11-NEXT: s_or_b32 s2, s3, s2
+; GFX11-NEXT: s_and_b32 s3, s7, 0xff
; GFX11-NEXT: s_add_i32 s1, s1, s1
-; GFX11-NEXT: s_add_i32 s13, s13, s13
-; GFX11-NEXT: s_lshl_b32 s7, s7, 8
-; GFX11-NEXT: s_and_b32 s6, s6, 0xff
-; GFX11-NEXT: s_add_i32 s0, s0, s0
-; GFX11-NEXT: s_add_i32 s12, s12, s12
+; GFX11-NEXT: s_lshl_b32 s7, s6, 8
+; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT: s_or_b32 s7, s7, s3
; GFX11-NEXT: s_add_i32 s5, s5, s5
+; GFX11-NEXT: s_add_i32 s0, s0, s0
; GFX11-NEXT: s_add_i32 s4, s4, s4
-; GFX11-NEXT: s_and_b32 s3, s3, 0xff
-; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: s_lshl_b32 s15, s15, 8
-; GFX11-NEXT: s_or_b32 s10, s10, s11
-; GFX11-NEXT: s_lshl_b32 s11, s14, 8
-; GFX11-NEXT: s_or_b32 s8, s8, s9
; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s9, s13, 8
-; GFX11-NEXT: s_or_b32 s6, s6, s7
+; GFX11-NEXT: s_add_i32 s13, s13, s13
+; GFX11-NEXT: s_and_b32 s3, s5, 0xff
; GFX11-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-NEXT: s_lshl_b32 s7, s12, 8
-; GFX11-NEXT: s_lshl_b32 s5, s5, 8
-; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: s_or_b32 s3, s3, s15
-; GFX11-NEXT: s_or_b32 s2, s2, s11
-; GFX11-NEXT: s_or_b32 s1, s1, s9
-; GFX11-NEXT: s_or_b32 s0, s0, s7
-; GFX11-NEXT: s_or_b32 s4, s4, s5
+; GFX11-NEXT: s_add_i32 s12, s12, s12
+; GFX11-NEXT: s_lshl_b32 s5, s4, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s5, s5, s3
+; GFX11-NEXT: s_lshl_b32 s3, s12, 8
+; GFX11-NEXT: s_or_b32 s3, s3, s0
+; GFX11-NEXT: s_lshl_b32 s0, s13, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: s_lshl_b32 s4, s7, 16
+; GFX11-NEXT: s_lshl_b32 s5, s5, 16
; GFX11-NEXT: s_and_b32 s3, s3, 0xffff
-; GFX11-NEXT: s_lshl_b32 s10, s10, 16
-; GFX11-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX11-NEXT: s_lshl_b32 s8, s8, 16
-; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX11-NEXT: s_lshl_b32 s4, s4, 16
-; GFX11-NEXT: s_lshl_b32 s5, s6, 16
-; GFX11-NEXT: s_or_b32 s3, s3, s10
-; GFX11-NEXT: s_or_b32 s2, s2, s8
+; GFX11-NEXT: s_or_b32 s1, s8, s9
+; GFX11-NEXT: s_or_b32 s3, s3, s5
; GFX11-NEXT: s_or_b32 s0, s0, s4
-; GFX11-NEXT: s_or_b32 s1, s1, s5
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX11-NEXT: v_mov_b32_e32 v2, s2
-; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s1
; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off
; GFX11-NEXT: s_endpgm
;
@@ -2273,73 +2288,78 @@ define amdgpu_kernel void @amd_kernel_v16i8(<16 x i8> %arg0) {
; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX1250-NEXT: v_mov_b64_e32 v[4:5], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s6, s1, 16
-; GFX1250-NEXT: s_lshr_b32 s7, s1, 24
-; GFX1250-NEXT: s_lshr_b32 s8, s2, 16
-; GFX1250-NEXT: s_lshr_b32 s9, s2, 24
-; GFX1250-NEXT: s_lshr_b32 s10, s3, 16
-; GFX1250-NEXT: s_lshr_b32 s11, s3, 24
-; GFX1250-NEXT: s_lshr_b32 s4, s0, 16
-; GFX1250-NEXT: s_lshr_b32 s5, s0, 24
-; GFX1250-NEXT: s_bfe_u32 s12, s0, 0x80008
-; GFX1250-NEXT: s_bfe_u32 s13, s1, 0x80008
-; GFX1250-NEXT: s_bfe_u32 s14, s2, 0x80008
+; GFX1250-NEXT: s_lshr_b32 s11, s3, 16
; GFX1250-NEXT: s_bfe_u32 s15, s3, 0x80008
+; GFX1250-NEXT: s_lshr_b32 s8, s2, 24
+; GFX1250-NEXT: s_lshr_b32 s9, s2, 16
+; GFX1250-NEXT: s_lshr_b32 s10, s3, 24
+; GFX1250-NEXT: s_bfe_u32 s14, s2, 0x80008
+; GFX1250-NEXT: s_add_co_i32 s3, s3, s3
+; GFX1250-NEXT: s_add_co_i32 s2, s2, s2
; GFX1250-NEXT: s_add_co_i32 s11, s11, s11
+; GFX1250-NEXT: s_add_co_i32 s15, s15, s15
+; GFX1250-NEXT: s_lshr_b32 s4, s0, 24
+; GFX1250-NEXT: s_lshr_b32 s5, s0, 16
+; GFX1250-NEXT: s_lshr_b32 s6, s1, 24
+; GFX1250-NEXT: s_lshr_b32 s7, s1, 16
+; GFX1250-NEXT: s_bfe_u32 s12, s0, 0x80008
+; GFX1250-NEXT: s_bfe_u32 s13, s1, 0x80008
; GFX1250-NEXT: s_add_co_i32 s10, s10, s10
+; GFX1250-NEXT: s_and_b32 s3, s3, 0xff
; GFX1250-NEXT: s_add_co_i32 s9, s9, s9
; GFX1250-NEXT: s_add_co_i32 s8, s8, s8
+; GFX1250-NEXT: s_and_b32 s2, s2, 0xff
+; GFX1250-NEXT: s_add_co_i32 s14, s14, s14
+; GFX1250-NEXT: s_and_b32 s11, s11, 0xff
+; GFX1250-NEXT: s_lshl_b32 s16, s15, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s16, s16, s3
+; GFX1250-NEXT: s_and_b32 s3, s9, 0xff
+; GFX1250-NEXT: s_lshl_b32 s9, s14, 8
+; GFX1250-NEXT: s_or_b32 s9, s9, s2
+; GFX1250-NEXT: s_lshl_b32 s2, s10, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s2, s2, s11
+; GFX1250-NEXT: s_lshl_b32 s10, s8, 8
+; GFX1250-NEXT: s_or_b32 s10, s10, s3
; GFX1250-NEXT: s_add_co_i32 s7, s7, s7
+; GFX1250-NEXT: s_and_b32 s3, s16, 0xffff
+; GFX1250-NEXT: s_lshl_b32 s2, s2, 16
; GFX1250-NEXT: s_add_co_i32 s6, s6, s6
-; GFX1250-NEXT: s_add_co_i32 s3, s3, s3
-; GFX1250-NEXT: s_add_co_i32 s2, s2, s2
-; GFX1250-NEXT: s_add_co_i32 s15, s15, s15
-; GFX1250-NEXT: s_add_co_i32 s14, s14, s14
-; GFX1250-NEXT: s_lshl_b32 s11, s11, 8
-; GFX1250-NEXT: s_and_b32 s10, s10, 0xff
-; GFX1250-NEXT: s_lshl_b32 s9, s9, 8
-; GFX1250-NEXT: s_and_b32 s8, s8, 0xff
+; GFX1250-NEXT: s_and_b32 s8, s9, 0xffff
+; GFX1250-NEXT: s_lshl_b32 s9, s10, 16
+; GFX1250-NEXT: s_or_b32 s2, s3, s2
+; GFX1250-NEXT: s_and_b32 s3, s7, 0xff
; GFX1250-NEXT: s_add_co_i32 s1, s1, s1
-; GFX1250-NEXT: s_add_co_i32 s13, s13, s13
-; GFX1250-NEXT: s_lshl_b32 s7, s7, 8
-; GFX1250-NEXT: s_and_b32 s6, s6, 0xff
-; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
-; GFX1250-NEXT: s_add_co_i32 s12, s12, s12
+; GFX1250-NEXT: s_lshl_b32 s7, s6, 8
+; GFX1250-NEXT: v_mov_b32_e32 v3, s2
+; GFX1250-NEXT: s_or_b32 s7, s7, s3
; GFX1250-NEXT: s_add_co_i32 s5, s5, s5
+; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
; GFX1250-NEXT: s_add_co_i32 s4, s4, s4
-; GFX1250-NEXT: s_and_b32 s3, s3, 0xff
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xff
-; GFX1250-NEXT: s_lshl_b32 s15, s15, 8
-; GFX1250-NEXT: s_or_b32 s10, s10, s11
-; GFX1250-NEXT: s_lshl_b32 s11, s14, 8
-; GFX1250-NEXT: s_or_b32 s8, s8, s9
; GFX1250-NEXT: s_and_b32 s1, s1, 0xff
-; GFX1250-NEXT: s_lshl_b32 s9, s13, 8
-; GFX1250-NEXT: s_or_b32 s6, s6, s7
+; GFX1250-NEXT: s_add_co_i32 s13, s13, s13
+; GFX1250-NEXT: s_and_b32 s3, s5, 0xff
; GFX1250-NEXT: s_and_b32 s0, s0, 0xff
-; GFX1250-NEXT: s_lshl_b32 s7, s12, 8
-; GFX1250-NEXT: s_lshl_b32 s5, s5, 8
-; GFX1250-NEXT: s_and_b32 s4, s4, 0xff
-; GFX1250-NEXT: s_or_b32 s3, s3, s15
-; GFX1250-NEXT: s_or_b32 s2, s2, s11
-; GFX1250-NEXT: s_or_b32 s1, s1, s9
-; GFX1250-NEXT: s_or_b32 s0, s0, s7
-; GFX1250-NEXT: s_or_b32 s4, s4, s5
+; GFX1250-NEXT: s_add_co_i32 s12, s12, s12
+; GFX1250-NEXT: s_lshl_b32 s5, s4, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s5, s5, s3
+; GFX1250-NEXT: s_lshl_b32 s3, s12, 8
+; GFX1250-NEXT: s_or_b32 s3, s3, s0
+; GFX1250-NEXT: s_lshl_b32 s0, s13, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s0, s0, s1
+; GFX1250-NEXT: s_lshl_b32 s4, s7, 16
+; GFX1250-NEXT: s_lshl_b32 s5, s5, 16
; GFX1250-NEXT: s_and_b32 s3, s3, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s10, s10, 16
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s8, s8, 16
-; GFX1250-NEXT: s_and_b32 s1, s1, 0xffff
; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s4, s4, 16
-; GFX1250-NEXT: s_lshl_b32 s5, s6, 16
-; GFX1250-NEXT: s_or_b32 s3, s3, s10
-; GFX1250-NEXT: s_or_b32 s2, s2, s8
+; GFX1250-NEXT: s_or_b32 s1, s8, s9
+; GFX1250-NEXT: s_or_b32 s3, s3, s5
; GFX1250-NEXT: s_or_b32 s0, s0, s4
-; GFX1250-NEXT: s_or_b32 s1, s1, s5
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX1250-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX1250-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s0
+; GFX1250-NEXT: v_mov_b32_e32 v2, s1
; GFX1250-NEXT: global_store_b128 v[4:5], v[0:3], off
; GFX1250-NEXT: s_endpgm
entry:
@@ -2652,139 +2672,148 @@ define amdgpu_kernel void @amd_kernel_v32i8(<32 x i8> %arg0) {
; GFX11-NEXT: v_dual_mov_b32 v8, 16 :: v_dual_mov_b32 v9, 0
; GFX11-NEXT: v_mov_b32_e32 v11, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_lshr_b32 s16, s0, 16
-; GFX11-NEXT: s_lshr_b32 s17, s0, 24
-; GFX11-NEXT: s_lshr_b32 s20, s2, 16
-; GFX11-NEXT: s_lshr_b32 s21, s2, 24
-; GFX11-NEXT: s_lshr_b32 s14, s7, 16
-; GFX11-NEXT: s_lshr_b32 s15, s7, 24
-; GFX11-NEXT: s_bfe_u32 s27, s7, 0x80008
-; GFX11-NEXT: s_add_i32 s17, s17, s17
-; GFX11-NEXT: s_add_i32 s16, s16, s16
-; GFX11-NEXT: s_lshr_b32 s18, s1, 16
-; GFX11-NEXT: s_lshr_b32 s19, s1, 24
-; GFX11-NEXT: s_lshr_b32 s22, s3, 16
-; GFX11-NEXT: s_lshr_b32 s23, s3, 24
-; GFX11-NEXT: s_bfe_u32 s29, s1, 0x80008
-; GFX11-NEXT: s_bfe_u32 s30, s3, 0x80008
-; GFX11-NEXT: s_add_i32 s21, s21, s21
-; GFX11-NEXT: s_add_i32 s20, s20, s20
-; GFX11-NEXT: s_lshl_b32 s17, s17, 8
-; GFX11-NEXT: s_and_b32 s16, s16, 0xff
-; GFX11-NEXT: s_add_i32 s7, s7, s7
-; GFX11-NEXT: s_add_i32 s27, s27, s27
-; GFX11-NEXT: s_add_i32 s15, s15, s15
-; GFX11-NEXT: s_add_i32 s14, s14, s14
+; GFX11-NEXT: s_lshr_b32 s23, s3, 16
+; GFX11-NEXT: s_lshr_b32 s22, s3, 24
+; GFX11-NEXT: s_bfe_u32 s28, s3, 0x80008
; GFX11-NEXT: s_add_i32 s3, s3, s3
-; GFX11-NEXT: s_add_i32 s30, s30, s30
; GFX11-NEXT: s_add_i32 s23, s23, s23
; GFX11-NEXT: s_add_i32 s22, s22, s22
-; GFX11-NEXT: s_lshl_b32 s21, s21, 8
-; GFX11-NEXT: s_and_b32 s20, s20, 0xff
-; GFX11-NEXT: s_add_i32 s1, s1, s1
-; GFX11-NEXT: s_add_i32 s29, s29, s29
-; GFX11-NEXT: s_add_i32 s19, s19, s19
-; GFX11-NEXT: s_add_i32 s18, s18, s18
-; GFX11-NEXT: s_lshr_b32 s10, s5, 16
-; GFX11-NEXT: s_lshr_b32 s11, s5, 24
-; GFX11-NEXT: s_lshr_b32 s12, s6, 16
-; GFX11-NEXT: s_lshr_b32 s13, s6, 24
-; GFX11-NEXT: s_or_b32 s16, s16, s17
-; GFX11-NEXT: s_and_b32 s7, s7, 0xff
-; GFX11-NEXT: s_lshl_b32 s17, s27, 8
-; GFX11-NEXT: s_lshl_b32 s15, s15, 8
-; GFX11-NEXT: s_and_b32 s14, s14, 0xff
-; GFX11-NEXT: s_and_b32 s3, s3, 0xff
-; GFX11-NEXT: s_lshl_b32 s30, s30, 8
-; GFX11-NEXT: s_lshl_b32 s23, s23, 8
-; GFX11-NEXT: s_and_b32 s22, s22, 0xff
-; GFX11-NEXT: s_or_b32 s20, s20, s21
-; GFX11-NEXT: s_and_b32 s1, s1, 0xff
-; GFX11-NEXT: s_lshl_b32 s21, s29, 8
-; GFX11-NEXT: s_lshl_b32 s19, s19, 8
-; GFX11-NEXT: s_and_b32 s18, s18, 0xff
-; GFX11-NEXT: s_lshr_b32 s8, s4, 16
-; GFX11-NEXT: s_lshr_b32 s9, s4, 24
+; GFX11-NEXT: s_lshr_b32 s8, s4, 24
+; GFX11-NEXT: s_lshr_b32 s9, s4, 16
+; GFX11-NEXT: s_lshr_b32 s10, s5, 24
+; GFX11-NEXT: s_lshr_b32 s11, s5, 16
+; GFX11-NEXT: s_lshr_b32 s12, s6, 24
+; GFX11-NEXT: s_lshr_b32 s13, s6, 16
+; GFX11-NEXT: s_lshr_b32 s14, s7, 24
+; GFX11-NEXT: s_lshr_b32 s15, s7, 16
+; GFX11-NEXT: s_lshr_b32 s16, s0, 24
+; GFX11-NEXT: s_lshr_b32 s17, s0, 16
+; GFX11-NEXT: s_lshr_b32 s18, s1, 24
+; GFX11-NEXT: s_lshr_b32 s19, s1, 16
+; GFX11-NEXT: s_lshr_b32 s20, s2, 24
+; GFX11-NEXT: s_lshr_b32 s21, s2, 16
; GFX11-NEXT: s_bfe_u32 s24, s4, 0x80008
; GFX11-NEXT: s_bfe_u32 s25, s5, 0x80008
; GFX11-NEXT: s_bfe_u32 s26, s6, 0x80008
-; GFX11-NEXT: s_or_b32 s7, s7, s17
-; GFX11-NEXT: s_or_b32 s14, s14, s15
+; GFX11-NEXT: s_bfe_u32 s27, s7, 0x80008
+; GFX11-NEXT: s_and_b32 s23, s23, 0xff
+; GFX11-NEXT: s_and_b32 s3, s3, 0xff
+; GFX11-NEXT: s_lshl_b32 s29, s22, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s29, s29, s23
+; GFX11-NEXT: s_add_i32 s28, s28, s28
+; GFX11-NEXT: s_bfe_u32 s22, s0, 0x80008
+; GFX11-NEXT: s_lshl_b32 s23, s28, 8
+; GFX11-NEXT: s_or_b32 s23, s23, s3
+; GFX11-NEXT: s_add_i32 s21, s21, s21
+; GFX11-NEXT: s_add_i32 s20, s20, s20
+; GFX11-NEXT: s_bfe_u32 s3, s1, 0x80008
+; GFX11-NEXT: s_bfe_u32 s28, s2, 0x80008
+; GFX11-NEXT: s_lshl_b32 s29, s29, 16
+; GFX11-NEXT: s_and_b32 s23, s23, 0xffff
+; GFX11-NEXT: s_and_b32 s21, s21, 0xff
+; GFX11-NEXT: s_add_i32 s2, s2, s2
+; GFX11-NEXT: s_lshl_b32 s30, s20, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s30, s30, s21
+; GFX11-NEXT: s_add_i32 s28, s28, s28
+; GFX11-NEXT: s_and_b32 s2, s2, 0xff
+; GFX11-NEXT: s_add_i32 s19, s19, s19
+; GFX11-NEXT: s_lshl_b32 s20, s28, 8
+; GFX11-NEXT: s_or_b32 s20, s20, s2
+; GFX11-NEXT: s_add_i32 s18, s18, s18
+; GFX11-NEXT: s_and_b32 s2, s19, 0xff
+; GFX11-NEXT: s_lshl_b32 s19, s30, 16
+; GFX11-NEXT: s_lshl_b32 s21, s18, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s21, s21, s2
+; GFX11-NEXT: s_and_b32 s2, s20, 0xffff
+; GFX11-NEXT: s_add_i32 s1, s1, s1
+; GFX11-NEXT: s_add_i32 s3, s3, s3
+; GFX11-NEXT: s_or_b32 s18, s23, s29
+; GFX11-NEXT: s_or_b32 s2, s2, s19
+; GFX11-NEXT: s_lshl_b32 s19, s21, 16
+; GFX11-NEXT: s_and_b32 s1, s1, 0xff
+; GFX11-NEXT: s_add_i32 s17, s17, s17
+; GFX11-NEXT: s_lshl_b32 s20, s3, 8
+; GFX11-NEXT: v_mov_b32_e32 v6, s2
+; GFX11-NEXT: s_or_b32 s20, s20, s1
+; GFX11-NEXT: s_add_i32 s16, s16, s16
+; GFX11-NEXT: s_and_b32 s1, s17, 0xff
+; GFX11-NEXT: s_add_i32 s0, s0, s0
+; GFX11-NEXT: s_lshl_b32 s3, s16, 8
+; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v7, s18
+; GFX11-NEXT: s_or_b32 s3, s3, s1
+; GFX11-NEXT: s_add_i32 s22, s22, s22
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_add_i32 s15, s15, s15
+; GFX11-NEXT: s_lshl_b32 s1, s22, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s1, s1, s0
+; GFX11-NEXT: s_add_i32 s14, s14, s14
+; GFX11-NEXT: s_and_b32 s0, s15, 0xff
+; GFX11-NEXT: s_and_b32 s15, s20, 0xffff
+; GFX11-NEXT: s_lshl_b32 s16, s14, 8
+; GFX11-NEXT: s_or_b32 s16, s16, s0
+; GFX11-NEXT: s_add_i32 s7, s7, s7
+; GFX11-NEXT: s_add_i32 s27, s27, s27
+; GFX11-NEXT: s_or_b32 s0, s15, s19
+; GFX11-NEXT: s_lshl_b32 s3, s3, 16
+; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX11-NEXT: s_lshl_b32 s14, s16, 16
+; GFX11-NEXT: s_and_b32 s7, s7, 0xff
; GFX11-NEXT: s_add_i32 s13, s13, s13
+; GFX11-NEXT: s_lshl_b32 s15, s27, 8
+; GFX11-NEXT: v_mov_b32_e32 v5, s0
+; GFX11-NEXT: s_or_b32 s15, s15, s7
; GFX11-NEXT: s_add_i32 s12, s12, s12
-; GFX11-NEXT: s_add_i32 s11, s11, s11
-; GFX11-NEXT: s_add_i32 s10, s10, s10
-; GFX11-NEXT: s_bfe_u32 s28, s0, 0x80008
-; GFX11-NEXT: s_or_b32 s3, s3, s30
-; GFX11-NEXT: s_or_b32 s22, s22, s23
-; GFX11-NEXT: s_bfe_u32 s23, s2, 0x80008
-; GFX11-NEXT: s_or_b32 s1, s1, s21
-; GFX11-NEXT: s_or_b32 s18, s18, s19
-; GFX11-NEXT: s_and_b32 s7, s7, 0xffff
-; GFX11-NEXT: s_lshl_b32 s14, s14, 16
+; GFX11-NEXT: s_and_b32 s7, s13, 0xff
; GFX11-NEXT: s_add_i32 s6, s6, s6
+; GFX11-NEXT: s_lshl_b32 s13, s12, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s13, s13, s7
; GFX11-NEXT: s_add_i32 s26, s26, s26
-; GFX11-NEXT: s_lshl_b32 s13, s13, 8
-; GFX11-NEXT: s_and_b32 s12, s12, 0xff
+; GFX11-NEXT: s_and_b32 s6, s6, 0xff
+; GFX11-NEXT: s_and_b32 s7, s15, 0xffff
+; GFX11-NEXT: s_lshl_b32 s12, s26, 8
+; GFX11-NEXT: s_or_b32 s12, s12, s6
+; GFX11-NEXT: s_add_i32 s11, s11, s11
+; GFX11-NEXT: s_add_i32 s10, s10, s10
+; GFX11-NEXT: s_or_b32 s1, s1, s3
+; GFX11-NEXT: s_or_b32 s3, s7, s14
+; GFX11-NEXT: s_lshl_b32 s6, s13, 16
+; GFX11-NEXT: s_and_b32 s7, s12, 0xffff
+; GFX11-NEXT: s_and_b32 s11, s11, 0xff
; GFX11-NEXT: s_add_i32 s5, s5, s5
-; GFX11-NEXT: s_add_i32 s25, s25, s25
-; GFX11-NEXT: s_lshl_b32 s11, s11, 8
-; GFX11-NEXT: s_and_b32 s10, s10, 0xff
-; GFX11-NEXT: s_add_i32 s4, s4, s4
-; GFX11-NEXT: s_add_i32 s24, s24, s24
+; GFX11-NEXT: s_lshl_b32 s12, s10, 8
+; GFX11-NEXT: v_mov_b32_e32 v3, s3
+; GFX11-NEXT: s_or_b32 s12, s12, s11
; GFX11-NEXT: s_add_i32 s9, s9, s9
+; GFX11-NEXT: s_add_i32 s4, s4, s4
; GFX11-NEXT: s_add_i32 s8, s8, s8
-; GFX11-NEXT: s_and_b32 s3, s3, 0xffff
-; GFX11-NEXT: s_lshl_b32 s22, s22, 16
-; GFX11-NEXT: s_add_i32 s2, s2, s2
-; GFX11-NEXT: s_add_i32 s23, s23, s23
-; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
-; GFX11-NEXT: s_lshl_b32 s18, s18, 16
-; GFX11-NEXT: s_add_i32 s0, s0, s0
-; GFX11-NEXT: s_add_i32 s28, s28, s28
-; GFX11-NEXT: s_or_b32 s7, s7, s14
-; GFX11-NEXT: s_and_b32 s6, s6, 0xff
-; GFX11-NEXT: s_lshl_b32 s14, s26, 8
-; GFX11-NEXT: s_or_b32 s12, s12, s13
; GFX11-NEXT: s_and_b32 s5, s5, 0xff
-; GFX11-NEXT: s_lshl_b32 s13, s25, 8
-; GFX11-NEXT: s_or_b32 s10, s10, s11
+; GFX11-NEXT: s_add_i32 s25, s25, s25
+; GFX11-NEXT: s_and_b32 s9, s9, 0xff
; GFX11-NEXT: s_and_b32 s4, s4, 0xff
-; GFX11-NEXT: s_lshl_b32 s11, s24, 8
-; GFX11-NEXT: s_lshl_b32 s9, s9, 8
-; GFX11-NEXT: s_and_b32 s8, s8, 0xff
-; GFX11-NEXT: s_or_b32 s3, s3, s22
-; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: s_lshl_b32 s22, s23, 8
-; GFX11-NEXT: s_or_b32 s1, s1, s18
-; GFX11-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-NEXT: s_lshl_b32 s18, s28, 8
-; GFX11-NEXT: s_or_b32 s6, s6, s14
-; GFX11-NEXT: s_or_b32 s5, s5, s13
-; GFX11-NEXT: s_or_b32 s4, s4, s11
-; GFX11-NEXT: s_or_b32 s8, s8, s9
-; GFX11-NEXT: s_or_b32 s2, s2, s22
-; GFX11-NEXT: s_or_b32 s0, s0, s18
-; GFX11-NEXT: s_and_b32 s6, s6, 0xffff
-; GFX11-NEXT: s_lshl_b32 s12, s12, 16
-; GFX11-NEXT: s_and_b32 s5, s5, 0xffff
+; GFX11-NEXT: s_add_i32 s24, s24, s24
+; GFX11-NEXT: s_lshl_b32 s10, s8, 8
+; GFX11-NEXT: v_mov_b32_e32 v4, s1
+; GFX11-NEXT: s_or_b32 s10, s10, s9
+; GFX11-NEXT: s_lshl_b32 s8, s24, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s8, s8, s4
+; GFX11-NEXT: s_lshl_b32 s4, s25, 8
+; GFX11-NEXT: s_or_b32 s4, s4, s5
+; GFX11-NEXT: s_or_b32 s5, s7, s6
+; GFX11-NEXT: s_lshl_b32 s6, s12, 16
+; GFX11-NEXT: s_lshl_b32 s7, s10, 16
+; GFX11-NEXT: s_and_b32 s8, s8, 0xffff
; GFX11-NEXT: s_and_b32 s4, s4, 0xffff
-; GFX11-NEXT: s_lshl_b32 s8, s8, 16
-; GFX11-NEXT: s_lshl_b32 s9, s10, 16
-; GFX11-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX11-NEXT: s_lshl_b32 s20, s20, 16
-; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX11-NEXT: s_lshl_b32 s16, s16, 16
-; GFX11-NEXT: s_or_b32 s6, s6, s12
-; GFX11-NEXT: s_or_b32 s4, s4, s8
-; GFX11-NEXT: s_or_b32 s5, s5, s9
-; GFX11-NEXT: s_or_b32 s2, s2, s20
-; GFX11-NEXT: s_or_b32 s0, s0, s16
-; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
-; GFX11-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
-; GFX11-NEXT: v_dual_mov_b32 v4, s0 :: v_dual_mov_b32 v5, s1
-; GFX11-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-NEXT: v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v7, s3
+; GFX11-NEXT: s_or_b32 s7, s8, s7
+; GFX11-NEXT: s_or_b32 s4, s4, s6
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, s7 :: v_dual_mov_b32 v1, s4
+; GFX11-NEXT: v_mov_b32_e32 v2, s5
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off
; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off
@@ -2797,138 +2826,148 @@ define amdgpu_kernel void @amd_kernel_v32i8(<32 x i8> %arg0) {
; GFX1250-NEXT: v_mov_b64_e32 v[8:9], 16
; GFX1250-NEXT: v_mov_b64_e32 v[10:11], 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: s_lshr_b32 s16, s8, 16
-; GFX1250-NEXT: s_lshr_b32 s17, s8, 24
-; GFX1250-NEXT: s_lshr_b32 s6, s15, 16
-; GFX1250-NEXT: s_lshr_b32 s7, s15, 24
+; GFX1250-NEXT: s_lshr_b32 s23, s11, 16
+; GFX1250-NEXT: s_lshr_b32 s22, s11, 24
+; GFX1250-NEXT: s_bfe_u32 s28, s11, 0x80008
+; GFX1250-NEXT: s_add_co_i32 s11, s11, s11
+; GFX1250-NEXT: s_add_co_i32 s23, s23, s23
+; GFX1250-NEXT: s_add_co_i32 s22, s22, s22
+; GFX1250-NEXT: s_lshr_b32 s0, s12, 24
+; GFX1250-NEXT: s_lshr_b32 s1, s12, 16
+; GFX1250-NEXT: s_lshr_b32 s2, s13, 24
+; GFX1250-NEXT: s_lshr_b32 s3, s13, 16
+; GFX1250-NEXT: s_lshr_b32 s4, s14, 24
+; GFX1250-NEXT: s_lshr_b32 s5, s14, 16
+; GFX1250-NEXT: s_lshr_b32 s6, s15, 24
+; GFX1250-NEXT: s_lshr_b32 s7, s15, 16
+; GFX1250-NEXT: s_lshr_b32 s16, s8, 24
+; GFX1250-NEXT: s_lshr_b32 s17, s8, 16
+; GFX1250-NEXT: s_lshr_b32 s18, s9, 24
+; GFX1250-NEXT: s_lshr_b32 s19, s9, 16
+; GFX1250-NEXT: s_lshr_b32 s20, s10, 24
+; GFX1250-NEXT: s_lshr_b32 s21, s10, 16
+; GFX1250-NEXT: s_bfe_u32 s24, s12, 0x80008
+; GFX1250-NEXT: s_bfe_u32 s25, s13, 0x80008
+; GFX1250-NEXT: s_bfe_u32 s26, s14, 0x80008
; GFX1250-NEXT: s_bfe_u32 s27, s15, 0x80008
+; GFX1250-NEXT: s_and_b32 s23, s23, 0xff
+; GFX1250-NEXT: s_and_b32 s11, s11, 0xff
+; GFX1250-NEXT: s_lshl_b32 s29, s22, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s29, s29, s23
+; GFX1250-NEXT: s_add_co_i32 s28, s28, s28
+; GFX1250-NEXT: s_bfe_u32 s22, s8, 0x80008
+; GFX1250-NEXT: s_lshl_b32 s23, s28, 8
+; GFX1250-NEXT: s_or_b32 s23, s23, s11
+; GFX1250-NEXT: s_add_co_i32 s21, s21, s21
+; GFX1250-NEXT: s_add_co_i32 s20, s20, s20
+; GFX1250-NEXT: s_bfe_u32 s11, s9, 0x80008
+; GFX1250-NEXT: s_bfe_u32 s28, s10, 0x80008
+; GFX1250-NEXT: s_lshl_b32 s29, s29, 16
+; GFX1250-NEXT: s_and_b32 s23, s23, 0xffff
+; GFX1250-NEXT: s_and_b32 s21, s21, 0xff
+; GFX1250-NEXT: s_add_co_i32 s10, s10, s10
+; GFX1250-NEXT: s_lshl_b32 s30, s20, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s30, s30, s21
+; GFX1250-NEXT: s_add_co_i32 s28, s28, s28
+; GFX1250-NEXT: s_and_b32 s10, s10, 0xff
+; GFX1250-NEXT: s_add_co_i32 s19, s19, s19
+; GFX1250-NEXT: s_lshl_b32 s20, s28, 8
+; GFX1250-NEXT: s_or_b32 s20, s20, s10
+; GFX1250-NEXT: s_add_co_i32 s18, s18, s18
+; GFX1250-NEXT: s_and_b32 s10, s19, 0xff
+; GFX1250-NEXT: s_lshl_b32 s19, s30, 16
+; GFX1250-NEXT: s_lshl_b32 s21, s18, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s21, s21, s10
+; GFX1250-NEXT: s_and_b32 s10, s20, 0xffff
+; GFX1250-NEXT: s_add_co_i32 s9, s9, s9
+; GFX1250-NEXT: s_add_co_i32 s11, s11, s11
+; GFX1250-NEXT: s_or_b32 s18, s23, s29
+; GFX1250-NEXT: s_or_b32 s10, s10, s19
+; GFX1250-NEXT: s_lshl_b32 s19, s21, 16
+; GFX1250-NEXT: s_and_b32 s9, s9, 0xff
; GFX1250-NEXT: s_add_co_i32 s17, s17, s17
+; GFX1250-NEXT: s_lshl_b32 s20, s11, 8
+; GFX1250-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s18
+; GFX1250-NEXT: s_or_b32 s20, s20, s9
; GFX1250-NEXT: s_add_co_i32 s16, s16, s16
-; GFX1250-NEXT: s_lshl_b32 s17, s17, 8
-; GFX1250-NEXT: s_and_b32 s16, s16, 0xff
-; GFX1250-NEXT: s_add_co_i32 s15, s15, s15
-; GFX1250-NEXT: s_add_co_i32 s27, s27, s27
+; GFX1250-NEXT: s_and_b32 s9, s17, 0xff
+; GFX1250-NEXT: s_add_co_i32 s8, s8, s8
+; GFX1250-NEXT: s_lshl_b32 s11, s16, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s11, s11, s9
+; GFX1250-NEXT: s_add_co_i32 s22, s22, s22
+; GFX1250-NEXT: s_and_b32 s8, s8, 0xff
; GFX1250-NEXT: s_add_co_i32 s7, s7, s7
+; GFX1250-NEXT: s_lshl_b32 s9, s22, 8
+; GFX1250-NEXT: s_or_b32 s9, s9, s8
; GFX1250-NEXT: s_add_co_i32 s6, s6, s6
-; GFX1250-NEXT: s_or_b32 s16, s16, s17
-; GFX1250-NEXT: s_and_b32 s15, s15, 0xff
-; GFX1250-NEXT: s_lshl_b32 s17, s27, 8
-; GFX1250-NEXT: s_lshl_b32 s7, s7, 8
-; GFX1250-NEXT: s_and_b32 s6, s6, 0xff
-; GFX1250-NEXT: s_or_b32 s15, s15, s17
-; GFX1250-NEXT: s_or_b32 s6, s6, s7
-; GFX1250-NEXT: s_bfe_u32 s26, s14, 0x80008
-; GFX1250-NEXT: s_and_b32 s7, s15, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s6, s6, 16
-; GFX1250-NEXT: s_lshr_b32 s20, s10, 16
-; GFX1250-NEXT: s_lshr_b32 s21, s10, 24
-; GFX1250-NEXT: s_lshr_b32 s4, s14, 16
-; GFX1250-NEXT: s_lshr_b32 s5, s14, 24
-; GFX1250-NEXT: s_or_b32 s6, s7, s6
-; GFX1250-NEXT: s_add_co_i32 s7, s14, s14
-; GFX1250-NEXT: s_add_co_i32 s26, s26, s26
-; GFX1250-NEXT: s_lshr_b32 s18, s9, 16
-; GFX1250-NEXT: s_lshr_b32 s19, s9, 24
-; GFX1250-NEXT: s_lshr_b32 s22, s11, 16
-; GFX1250-NEXT: s_lshr_b32 s23, s11, 24
-; GFX1250-NEXT: s_bfe_u32 s29, s9, 0x80008
-; GFX1250-NEXT: s_bfe_u32 s30, s11, 0x80008
-; GFX1250-NEXT: s_add_co_i32 s21, s21, s21
-; GFX1250-NEXT: s_add_co_i32 s20, s20, s20
-; GFX1250-NEXT: s_lshr_b32 s2, s13, 16
-; GFX1250-NEXT: s_lshr_b32 s3, s13, 24
; GFX1250-NEXT: s_and_b32 s7, s7, 0xff
-; GFX1250-NEXT: s_lshl_b32 s14, s26, 8
+; GFX1250-NEXT: s_and_b32 s8, s20, 0xffff
+; GFX1250-NEXT: s_lshl_b32 s16, s6, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s16, s16, s7
+; GFX1250-NEXT: s_or_b32 s6, s8, s19
+; GFX1250-NEXT: s_and_b32 s8, s9, 0xffff
+; GFX1250-NEXT: s_add_co_i32 s9, s15, s15
+; GFX1250-NEXT: s_add_co_i32 s27, s27, s27
+; GFX1250-NEXT: s_lshl_b32 s7, s11, 16
+; GFX1250-NEXT: s_lshl_b32 s11, s16, 16
+; GFX1250-NEXT: s_and_b32 s9, s9, 0xff
; GFX1250-NEXT: s_add_co_i32 s5, s5, s5
+; GFX1250-NEXT: s_lshl_b32 s15, s27, 8
+; GFX1250-NEXT: v_mov_b32_e32 v5, s6
+; GFX1250-NEXT: s_or_b32 s15, s15, s9
; GFX1250-NEXT: s_add_co_i32 s4, s4, s4
-; GFX1250-NEXT: s_add_co_i32 s11, s11, s11
-; GFX1250-NEXT: s_add_co_i32 s30, s30, s30
-; GFX1250-NEXT: s_add_co_i32 s23, s23, s23
-; GFX1250-NEXT: s_add_co_i32 s22, s22, s22
-; GFX1250-NEXT: s_lshl_b32 s21, s21, 8
-; GFX1250-NEXT: s_and_b32 s20, s20, 0xff
-; GFX1250-NEXT: s_add_co_i32 s9, s9, s9
-; GFX1250-NEXT: s_add_co_i32 s29, s29, s29
-; GFX1250-NEXT: s_add_co_i32 s19, s19, s19
-; GFX1250-NEXT: s_add_co_i32 s18, s18, s18
-; GFX1250-NEXT: s_bfe_u32 s25, s13, 0x80008
-; GFX1250-NEXT: s_lshl_b32 s5, s5, 8
-; GFX1250-NEXT: s_and_b32 s4, s4, 0xff
-; GFX1250-NEXT: s_or_b32 s7, s7, s14
+; GFX1250-NEXT: s_and_b32 s5, s5, 0xff
+; GFX1250-NEXT: s_add_co_i32 s9, s14, s14
+; GFX1250-NEXT: s_lshl_b32 s14, s4, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s14, s14, s5
+; GFX1250-NEXT: s_add_co_i32 s26, s26, s26
+; GFX1250-NEXT: s_and_b32 s4, s9, 0xff
+; GFX1250-NEXT: s_and_b32 s5, s15, 0xffff
+; GFX1250-NEXT: s_lshl_b32 s9, s26, 8
+; GFX1250-NEXT: s_or_b32 s9, s9, s4
; GFX1250-NEXT: s_add_co_i32 s3, s3, s3
; GFX1250-NEXT: s_add_co_i32 s2, s2, s2
-; GFX1250-NEXT: s_and_b32 s11, s11, 0xff
-; GFX1250-NEXT: s_lshl_b32 s30, s30, 8
-; GFX1250-NEXT: s_lshl_b32 s23, s23, 8
-; GFX1250-NEXT: s_and_b32 s22, s22, 0xff
-; GFX1250-NEXT: s_or_b32 s20, s20, s21
-; GFX1250-NEXT: s_and_b32 s9, s9, 0xff
-; GFX1250-NEXT: s_lshl_b32 s21, s29, 8
-; GFX1250-NEXT: s_lshl_b32 s19, s19, 8
-; GFX1250-NEXT: s_and_b32 s18, s18, 0xff
-; GFX1250-NEXT: s_lshr_b32 s0, s12, 16
-; GFX1250-NEXT: s_lshr_b32 s1, s12, 24
-; GFX1250-NEXT: s_bfe_u32 s24, s12, 0x80008
-; GFX1250-NEXT: s_or_b32 s4, s4, s5
-; GFX1250-NEXT: s_and_b32 s5, s7, 0xffff
-; GFX1250-NEXT: s_add_co_i32 s7, s13, s13
-; GFX1250-NEXT: s_add_co_i32 s25, s25, s25
-; GFX1250-NEXT: s_lshl_b32 s3, s3, 8
-; GFX1250-NEXT: s_and_b32 s2, s2, 0xff
-; GFX1250-NEXT: s_bfe_u32 s28, s8, 0x80008
-; GFX1250-NEXT: s_or_b32 s11, s11, s30
-; GFX1250-NEXT: s_or_b32 s22, s22, s23
-; GFX1250-NEXT: s_bfe_u32 s23, s10, 0x80008
-; GFX1250-NEXT: s_or_b32 s9, s9, s21
-; GFX1250-NEXT: s_or_b32 s18, s18, s19
-; GFX1250-NEXT: s_lshl_b32 s4, s4, 16
-; GFX1250-NEXT: s_and_b32 s7, s7, 0xff
-; GFX1250-NEXT: s_lshl_b32 s13, s25, 8
-; GFX1250-NEXT: s_or_b32 s2, s2, s3
-; GFX1250-NEXT: s_add_co_i32 s3, s12, s12
-; GFX1250-NEXT: s_add_co_i32 s24, s24, s24
+; GFX1250-NEXT: s_or_b32 s4, s8, s7
+; GFX1250-NEXT: s_or_b32 s5, s5, s11
+; GFX1250-NEXT: s_lshl_b32 s7, s14, 16
+; GFX1250-NEXT: s_and_b32 s8, s9, 0xffff
+; GFX1250-NEXT: s_and_b32 s3, s3, 0xff
+; GFX1250-NEXT: s_add_co_i32 s9, s13, s13
+; GFX1250-NEXT: s_lshl_b32 s11, s2, 8
+; GFX1250-NEXT: v_mov_b32_e32 v3, s5
+; GFX1250-NEXT: s_or_b32 s11, s11, s3
; GFX1250-NEXT: s_add_co_i32 s1, s1, s1
+; GFX1250-NEXT: s_add_co_i32 s3, s12, s12
; GFX1250-NEXT: s_add_co_i32 s0, s0, s0
-; GFX1250-NEXT: s_and_b32 s11, s11, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s22, s22, 16
-; GFX1250-NEXT: s_add_co_i32 s10, s10, s10
-; GFX1250-NEXT: s_add_co_i32 s23, s23, s23
-; GFX1250-NEXT: s_and_b32 s9, s9, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s18, s18, 16
-; GFX1250-NEXT: s_add_co_i32 s8, s8, s8
-; GFX1250-NEXT: s_add_co_i32 s28, s28, s28
-; GFX1250-NEXT: s_or_b32 s4, s5, s4
-; GFX1250-NEXT: s_or_b32 s5, s7, s13
+; GFX1250-NEXT: s_and_b32 s2, s9, 0xff
+; GFX1250-NEXT: s_add_co_i32 s25, s25, s25
+; GFX1250-NEXT: s_and_b32 s1, s1, 0xff
; GFX1250-NEXT: s_and_b32 s3, s3, 0xff
-; GFX1250-NEXT: s_lshl_b32 s7, s24, 8
-; GFX1250-NEXT: s_lshl_b32 s1, s1, 8
-; GFX1250-NEXT: s_and_b32 s0, s0, 0xff
-; GFX1250-NEXT: s_or_b32 s11, s11, s22
-; GFX1250-NEXT: s_and_b32 s10, s10, 0xff
-; GFX1250-NEXT: s_lshl_b32 s22, s23, 8
-; GFX1250-NEXT: s_or_b32 s9, s9, s18
-; GFX1250-NEXT: s_and_b32 s8, s8, 0xff
-; GFX1250-NEXT: s_lshl_b32 s18, s28, 8
-; GFX1250-NEXT: s_or_b32 s3, s3, s7
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_or_b32 s10, s10, s22
-; GFX1250-NEXT: s_or_b32 s8, s8, s18
-; GFX1250-NEXT: s_and_b32 s5, s5, 0xffff
-; GFX1250-NEXT: s_and_b32 s1, s3, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s0, s0, 16
-; GFX1250-NEXT: s_lshl_b32 s2, s2, 16
-; GFX1250-NEXT: s_and_b32 s10, s10, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s20, s20, 16
-; GFX1250-NEXT: s_and_b32 s8, s8, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s16, s16, 16
-; GFX1250-NEXT: s_or_b32 s0, s1, s0
-; GFX1250-NEXT: s_or_b32 s1, s5, s2
-; GFX1250-NEXT: s_or_b32 s10, s10, s20
-; GFX1250-NEXT: s_or_b32 s8, s8, s16
+; GFX1250-NEXT: s_add_co_i32 s24, s24, s24
+; GFX1250-NEXT: s_lshl_b32 s9, s0, 8
+; GFX1250-NEXT: v_mov_b32_e32 v4, s4
+; GFX1250-NEXT: s_or_b32 s9, s9, s1
+; GFX1250-NEXT: s_lshl_b32 s0, s24, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s0, s0, s3
+; GFX1250-NEXT: s_lshl_b32 s1, s25, 8
+; GFX1250-NEXT: s_or_b32 s1, s1, s2
+; GFX1250-NEXT: s_or_b32 s2, s8, s7
+; GFX1250-NEXT: s_lshl_b32 s3, s11, 16
+; GFX1250-NEXT: s_lshl_b32 s7, s9, 16
+; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff
+; GFX1250-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX1250-NEXT: s_or_b32 s0, s0, s7
+; GFX1250-NEXT: s_or_b32 s1, s1, s3
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX1250-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s6
-; GFX1250-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9
-; GFX1250-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
+; GFX1250-NEXT: v_mov_b32_e32 v2, s2
; GFX1250-NEXT: s_clause 0x1
; GFX1250-NEXT: global_store_b128 v[8:9], v[0:3], off
; GFX1250-NEXT: global_store_b128 v[10:11], v[4:7], off
@@ -4100,28 +4139,30 @@ define amdgpu_cs void @amdgpu_cs_inreg_v8i1(<8 x i1> inreg %arg0) {
; GFX11-LABEL: amdgpu_cs_inreg_v8i1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_and_b32 s6, s6, 1
-; GFX11-NEXT: s_lshl_b32 s5, s5, 1
-; GFX11-NEXT: s_and_b32 s4, s4, 1
; GFX11-NEXT: s_and_b32 s2, s2, 1
-; GFX11-NEXT: s_lshl_b32 s1, s1, 1
-; GFX11-NEXT: s_and_b32 s0, s0, 1
-; GFX11-NEXT: s_lshl_b32 s7, s7, 3
; GFX11-NEXT: s_lshl_b32 s6, s6, 2
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_lshl_b32 s3, s3, 3
+; GFX11-NEXT: s_and_b32 s4, s4, 1
+; GFX11-NEXT: s_and_b32 s0, s0, 1
; GFX11-NEXT: s_lshl_b32 s2, s2, 2
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_or_b32 s5, s7, s6
-; GFX11-NEXT: s_and_b32 s4, s4, 3
-; GFX11-NEXT: s_or_b32 s1, s3, s2
+; GFX11-NEXT: s_lshl_b32 s8, s1, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s8, s8, s0
+; GFX11-NEXT: s_lshl_b32 s0, s5, 1
+; GFX11-NEXT: s_or_b32 s0, s0, s4
+; GFX11-NEXT: s_lshl_b32 s1, s3, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s1, s1, s2
+; GFX11-NEXT: s_lshl_b32 s2, s7, 3
+; GFX11-NEXT: s_or_b32 s2, s2, s6
+; GFX11-NEXT: s_and_b32 s3, s8, 3
; GFX11-NEXT: s_and_b32 s0, s0, 3
-; GFX11-NEXT: s_or_b32 s2, s4, s5
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_lshl_b32 s1, s2, 4
-; GFX11-NEXT: s_and_b32 s0, s0, 15
+; GFX11-NEXT: s_or_b32 s1, s3, s1
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_and_b32 s1, s1, 15
+; GFX11-NEXT: s_lshl_b32 s2, s0, 4
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: s_or_b32 s2, s2, s1
+; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b8 v[0:1], v0, off
; GFX11-NEXT: s_endpgm
;
@@ -4129,28 +4170,30 @@ define amdgpu_cs void @amdgpu_cs_inreg_v8i1(<8 x i1> inreg %arg0) {
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_and_b32 s6, s6, 1
-; GFX1250-NEXT: s_lshl_b32 s5, s5, 1
-; GFX1250-NEXT: s_and_b32 s4, s4, 1
; GFX1250-NEXT: s_and_b32 s2, s2, 1
-; GFX1250-NEXT: s_lshl_b32 s1, s1, 1
-; GFX1250-NEXT: s_and_b32 s0, s0, 1
-; GFX1250-NEXT: s_lshl_b32 s7, s7, 3
; GFX1250-NEXT: s_lshl_b32 s6, s6, 2
-; GFX1250-NEXT: s_or_b32 s4, s4, s5
-; GFX1250-NEXT: s_lshl_b32 s3, s3, 3
+; GFX1250-NEXT: s_and_b32 s4, s4, 1
+; GFX1250-NEXT: s_and_b32 s0, s0, 1
; GFX1250-NEXT: s_lshl_b32 s2, s2, 2
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_or_b32 s5, s7, s6
-; GFX1250-NEXT: s_and_b32 s4, s4, 3
-; GFX1250-NEXT: s_or_b32 s1, s3, s2
+; GFX1250-NEXT: s_lshl_b32 s8, s1, 1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s8, s8, s0
+; GFX1250-NEXT: s_lshl_b32 s0, s5, 1
+; GFX1250-NEXT: s_or_b32 s0, s0, s4
+; GFX1250-NEXT: s_lshl_b32 s1, s3, 3
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s1, s1, s2
+; GFX1250-NEXT: s_lshl_b32 s2, s7, 3
+; GFX1250-NEXT: s_or_b32 s2, s2, s6
+; GFX1250-NEXT: s_and_b32 s3, s8, 3
; GFX1250-NEXT: s_and_b32 s0, s0, 3
-; GFX1250-NEXT: s_or_b32 s2, s4, s5
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_lshl_b32 s1, s2, 4
-; GFX1250-NEXT: s_and_b32 s0, s0, 15
+; GFX1250-NEXT: s_or_b32 s1, s3, s1
+; GFX1250-NEXT: s_or_b32 s0, s0, s2
+; GFX1250-NEXT: s_and_b32 s1, s1, 15
+; GFX1250-NEXT: s_lshl_b32 s2, s0, 4
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-NEXT: s_or_b32 s2, s2, s1
+; GFX1250-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-NEXT: global_store_b8 v[0:1], v0, off
; GFX1250-NEXT: s_endpgm
store <8 x i1> %arg0, ptr addrspace(1) poison
@@ -4264,52 +4307,57 @@ define amdgpu_cs void @amdgpu_cs_inreg_v16i1(<16 x i1> inreg %arg0) {
;
; GFX11-LABEL: amdgpu_cs_inreg_v16i1:
; GFX11: ; %bb.0:
+; GFX11-NEXT: s_and_b32 s14, s14, 1
+; GFX11-NEXT: s_and_b32 s12, s12, 1
+; GFX11-NEXT: s_lshl_b32 s14, s14, 2
+; GFX11-NEXT: s_lshl_b32 s16, s15, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s16, s16, s14
+; GFX11-NEXT: s_lshl_b32 s14, s13, 1
+; GFX11-NEXT: s_or_b32 s14, s14, s12
; GFX11-NEXT: s_and_b32 s10, s10, 1
-; GFX11-NEXT: s_lshl_b32 s9, s9, 1
; GFX11-NEXT: s_and_b32 s8, s8, 1
+; GFX11-NEXT: s_lshl_b32 s10, s10, 2
+; GFX11-NEXT: s_lshl_b32 s12, s9, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s12, s12, s8
+; GFX11-NEXT: s_and_b32 s8, s14, 3
+; GFX11-NEXT: s_lshl_b32 s9, s11, 3
+; GFX11-NEXT: s_or_b32 s9, s9, s10
+; GFX11-NEXT: s_and_b32 s10, s12, 3
; GFX11-NEXT: s_and_b32 s6, s6, 1
-; GFX11-NEXT: s_lshl_b32 s5, s5, 1
-; GFX11-NEXT: s_and_b32 s4, s4, 1
; GFX11-NEXT: s_and_b32 s2, s2, 1
-; GFX11-NEXT: s_lshl_b32 s1, s1, 1
-; GFX11-NEXT: s_and_b32 s0, s0, 1
-; GFX11-NEXT: s_and_b32 s14, s14, 1
-; GFX11-NEXT: s_lshl_b32 s13, s13, 1
-; GFX11-NEXT: s_and_b32 s12, s12, 1
-; GFX11-NEXT: s_lshl_b32 s11, s11, 3
-; GFX11-NEXT: s_lshl_b32 s10, s10, 2
-; GFX11-NEXT: s_or_b32 s8, s8, s9
-; GFX11-NEXT: s_lshl_b32 s7, s7, 3
+; GFX11-NEXT: s_or_b32 s8, s8, s16
+; GFX11-NEXT: s_or_b32 s9, s10, s9
; GFX11-NEXT: s_lshl_b32 s6, s6, 2
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_lshl_b32 s3, s3, 3
+; GFX11-NEXT: s_and_b32 s4, s4, 1
+; GFX11-NEXT: s_and_b32 s0, s0, 1
; GFX11-NEXT: s_lshl_b32 s2, s2, 2
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_lshl_b32 s15, s15, 3
-; GFX11-NEXT: s_lshl_b32 s14, s14, 2
-; GFX11-NEXT: s_or_b32 s12, s12, s13
-; GFX11-NEXT: s_or_b32 s9, s11, s10
-; GFX11-NEXT: s_and_b32 s8, s8, 3
-; GFX11-NEXT: s_or_b32 s5, s7, s6
-; GFX11-NEXT: s_and_b32 s4, s4, 3
-; GFX11-NEXT: s_or_b32 s1, s3, s2
+; GFX11-NEXT: s_lshl_b32 s10, s1, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s10, s10, s0
+; GFX11-NEXT: s_lshl_b32 s0, s5, 1
+; GFX11-NEXT: s_or_b32 s0, s0, s4
+; GFX11-NEXT: s_lshl_b32 s1, s3, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s1, s1, s2
+; GFX11-NEXT: s_lshl_b32 s2, s7, 3
+; GFX11-NEXT: s_or_b32 s2, s2, s6
+; GFX11-NEXT: s_and_b32 s4, s10, 3
; GFX11-NEXT: s_and_b32 s0, s0, 3
-; GFX11-NEXT: s_or_b32 s13, s15, s14
-; GFX11-NEXT: s_and_b32 s12, s12, 3
-; GFX11-NEXT: s_or_b32 s8, s8, s9
-; GFX11-NEXT: s_or_b32 s2, s4, s5
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_or_b32 s10, s12, s13
-; GFX11-NEXT: s_and_b32 s8, s8, 15
-; GFX11-NEXT: s_lshl_b32 s1, s2, 4
-; GFX11-NEXT: s_and_b32 s0, s0, 15
-; GFX11-NEXT: s_lshl_b32 s9, s10, 12
-; GFX11-NEXT: s_lshl_b32 s2, s8, 8
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_or_b32 s1, s9, s2
-; GFX11-NEXT: s_and_b32 s0, s0, 0xff
+; GFX11-NEXT: s_and_b32 s3, s9, 15
+; GFX11-NEXT: s_or_b32 s1, s4, s1
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_and_b32 s1, s1, 15
+; GFX11-NEXT: s_lshl_b32 s2, s3, 8
+; GFX11-NEXT: s_lshl_b32 s3, s0, 4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s3, s3, s1
+; GFX11-NEXT: s_lshl_b32 s0, s8, 12
+; GFX11-NEXT: s_or_b32 s0, s0, s2
+; GFX11-NEXT: s_and_b32 s1, s3, 0xff
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
+; GFX11-NEXT: s_or_b32 s0, s1, s0
; GFX11-NEXT: v_mov_b32_e32 v0, s0
; GFX11-NEXT: global_store_b16 v[0:1], v0, off
; GFX11-NEXT: s_endpgm
@@ -4317,52 +4365,57 @@ define amdgpu_cs void @amdgpu_cs_inreg_v16i1(<16 x i1> inreg %arg0) {
; GFX1250-LABEL: amdgpu_cs_inreg_v16i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_and_b32 s14, s14, 1
+; GFX1250-NEXT: s_and_b32 s12, s12, 1
+; GFX1250-NEXT: s_lshl_b32 s14, s14, 2
+; GFX1250-NEXT: s_lshl_b32 s16, s15, 3
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s16, s16, s14
+; GFX1250-NEXT: s_lshl_b32 s14, s13, 1
+; GFX1250-NEXT: s_or_b32 s14, s14, s12
; GFX1250-NEXT: s_and_b32 s10, s10, 1
-; GFX1250-NEXT: s_lshl_b32 s9, s9, 1
; GFX1250-NEXT: s_and_b32 s8, s8, 1
+; GFX1250-NEXT: s_lshl_b32 s10, s10, 2
+; GFX1250-NEXT: s_lshl_b32 s12, s9, 1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s12, s12, s8
+; GFX1250-NEXT: s_and_b32 s8, s14, 3
+; GFX1250-NEXT: s_lshl_b32 s9, s11, 3
+; GFX1250-NEXT: s_or_b32 s9, s9, s10
+; GFX1250-NEXT: s_and_b32 s10, s12, 3
; GFX1250-NEXT: s_and_b32 s6, s6, 1
-; GFX1250-NEXT: s_lshl_b32 s5, s5, 1
-; GFX1250-NEXT: s_and_b32 s4, s4, 1
; GFX1250-NEXT: s_and_b32 s2, s2, 1
-; GFX1250-NEXT: s_lshl_b32 s1, s1, 1
-; GFX1250-NEXT: s_and_b32 s0, s0, 1
-; GFX1250-NEXT: s_and_b32 s14, s14, 1
-; GFX1250-NEXT: s_lshl_b32 s13, s13, 1
-; GFX1250-NEXT: s_and_b32 s12, s12, 1
-; GFX1250-NEXT: s_lshl_b32 s11, s11, 3
-; GFX1250-NEXT: s_lshl_b32 s10, s10, 2
-; GFX1250-NEXT: s_or_b32 s8, s8, s9
-; GFX1250-NEXT: s_lshl_b32 s7, s7, 3
+; GFX1250-NEXT: s_or_b32 s8, s8, s16
+; GFX1250-NEXT: s_or_b32 s9, s10, s9
; GFX1250-NEXT: s_lshl_b32 s6, s6, 2
-; GFX1250-NEXT: s_or_b32 s4, s4, s5
-; GFX1250-NEXT: s_lshl_b32 s3, s3, 3
+; GFX1250-NEXT: s_and_b32 s4, s4, 1
+; GFX1250-NEXT: s_and_b32 s0, s0, 1
; GFX1250-NEXT: s_lshl_b32 s2, s2, 2
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_lshl_b32 s15, s15, 3
-; GFX1250-NEXT: s_lshl_b32 s14, s14, 2
-; GFX1250-NEXT: s_or_b32 s12, s12, s13
-; GFX1250-NEXT: s_or_b32 s9, s11, s10
-; GFX1250-NEXT: s_and_b32 s8, s8, 3
-; GFX1250-NEXT: s_or_b32 s5, s7, s6
-; GFX1250-NEXT: s_and_b32 s4, s4, 3
-; GFX1250-NEXT: s_or_b32 s1, s3, s2
+; GFX1250-NEXT: s_lshl_b32 s10, s1, 1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s10, s10, s0
+; GFX1250-NEXT: s_lshl_b32 s0, s5, 1
+; GFX1250-NEXT: s_or_b32 s0, s0, s4
+; GFX1250-NEXT: s_lshl_b32 s1, s3, 3
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s1, s1, s2
+; GFX1250-NEXT: s_lshl_b32 s2, s7, 3
+; GFX1250-NEXT: s_or_b32 s2, s2, s6
+; GFX1250-NEXT: s_and_b32 s4, s10, 3
; GFX1250-NEXT: s_and_b32 s0, s0, 3
-; GFX1250-NEXT: s_or_b32 s13, s15, s14
-; GFX1250-NEXT: s_and_b32 s12, s12, 3
-; GFX1250-NEXT: s_or_b32 s8, s8, s9
-; GFX1250-NEXT: s_or_b32 s2, s4, s5
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_or_b32 s10, s12, s13
-; GFX1250-NEXT: s_and_b32 s8, s8, 15
-; GFX1250-NEXT: s_lshl_b32 s1, s2, 4
-; GFX1250-NEXT: s_and_b32 s0, s0, 15
-; GFX1250-NEXT: s_lshl_b32 s9, s10, 12
-; GFX1250-NEXT: s_lshl_b32 s2, s8, 8
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_or_b32 s1, s9, s2
-; GFX1250-NEXT: s_and_b32 s0, s0, 0xff
+; GFX1250-NEXT: s_and_b32 s3, s9, 15
+; GFX1250-NEXT: s_or_b32 s1, s4, s1
+; GFX1250-NEXT: s_or_b32 s0, s0, s2
+; GFX1250-NEXT: s_and_b32 s1, s1, 15
+; GFX1250-NEXT: s_lshl_b32 s2, s3, 8
+; GFX1250-NEXT: s_lshl_b32 s3, s0, 4
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s3, s3, s1
+; GFX1250-NEXT: s_lshl_b32 s0, s8, 12
+; GFX1250-NEXT: s_or_b32 s0, s0, s2
+; GFX1250-NEXT: s_and_b32 s1, s3, 0xff
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
+; GFX1250-NEXT: s_or_b32 s0, s1, s0
; GFX1250-NEXT: v_mov_b32_e32 v0, s0
; GFX1250-NEXT: global_store_b16 v[0:1], v0, off
; GFX1250-NEXT: s_endpgm
@@ -4573,96 +4626,107 @@ define amdgpu_cs void @amdgpu_cs_inreg_v32i1(<32 x i1> inreg %arg0) {
;
; GFX11-LABEL: amdgpu_cs_inreg_v32i1:
; GFX11: ; %bb.0:
-; GFX11-NEXT: s_and_b32 s10, s10, 1
-; GFX11-NEXT: s_lshl_b32 s9, s9, 1
-; GFX11-NEXT: s_and_b32 s8, s8, 1
; GFX11-NEXT: s_and_b32 s14, s14, 1
-; GFX11-NEXT: s_lshl_b32 s13, s13, 1
+; GFX11-NEXT: s_and_b32 s10, s10, 1
+; GFX11-NEXT: s_lshl_b32 s14, s14, 2
; GFX11-NEXT: s_and_b32 s12, s12, 1
-; GFX11-NEXT: s_lshl_b32 s11, s11, 3
+; GFX11-NEXT: s_and_b32 s8, s8, 1
; GFX11-NEXT: s_lshl_b32 s10, s10, 2
-; GFX11-NEXT: s_or_b32 s8, s8, s9
+; GFX11-NEXT: s_lshl_b32 s33, s9, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s33, s33, s8
+; GFX11-NEXT: s_lshl_b32 s8, s13, 1
+; GFX11-NEXT: s_or_b32 s8, s8, s12
+; GFX11-NEXT: s_lshl_b32 s9, s11, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s9, s9, s10
+; GFX11-NEXT: s_lshl_b32 s10, s15, 3
+; GFX11-NEXT: s_or_b32 s10, s10, s14
+; GFX11-NEXT: s_and_b32 s11, s33, 3
+; GFX11-NEXT: s_and_b32 s8, s8, 3
+; GFX11-NEXT: s_or_b32 s9, s11, s9
; GFX11-NEXT: s_and_b32 s6, s6, 1
-; GFX11-NEXT: s_lshl_b32 s5, s5, 1
+; GFX11-NEXT: s_or_b32 s8, s8, s10
+; GFX11-NEXT: s_and_b32 s9, s9, 15
; GFX11-NEXT: s_and_b32 s4, s4, 1
+; GFX11-NEXT: s_lshl_b32 s6, s6, 2
+; GFX11-NEXT: s_lshl_b32 s10, s5, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s10, s10, s4
; GFX11-NEXT: s_and_b32 s2, s2, 1
-; GFX11-NEXT: s_lshl_b32 s1, s1, 1
; GFX11-NEXT: s_and_b32 s0, s0, 1
-; GFX11-NEXT: s_lshl_b32 s15, s15, 3
-; GFX11-NEXT: s_lshl_b32 s14, s14, 2
-; GFX11-NEXT: s_or_b32 s12, s12, s13
-; GFX11-NEXT: s_or_b32 s9, s11, s10
-; GFX11-NEXT: s_and_b32 s8, s8, 3
-; GFX11-NEXT: s_lshl_b32 s7, s7, 3
-; GFX11-NEXT: s_lshl_b32 s6, s6, 2
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_lshl_b32 s3, s3, 3
; GFX11-NEXT: s_lshl_b32 s2, s2, 2
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_or_b32 s13, s15, s14
-; GFX11-NEXT: s_and_b32 s12, s12, 3
-; GFX11-NEXT: s_or_b32 s8, s8, s9
-; GFX11-NEXT: s_or_b32 s5, s7, s6
+; GFX11-NEXT: s_lshl_b32 s4, s1, 1
+; GFX11-NEXT: s_or_b32 s4, s4, s0
+; GFX11-NEXT: s_lshl_b32 s0, s7, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s0, s0, s6
+; GFX11-NEXT: s_lshl_b32 s1, s3, 3
+; GFX11-NEXT: s_or_b32 s1, s1, s2
+; GFX11-NEXT: s_and_b32 s3, s10, 3
; GFX11-NEXT: s_and_b32 s4, s4, 3
-; GFX11-NEXT: s_or_b32 s1, s3, s2
-; GFX11-NEXT: s_and_b32 s0, s0, 3
-; GFX11-NEXT: s_or_b32 s10, s12, s13
-; GFX11-NEXT: s_and_b32 s8, s8, 15
-; GFX11-NEXT: s_or_b32 s2, s4, s5
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_lshl_b32 s9, s10, 12
-; GFX11-NEXT: s_lshl_b32 s1, s2, 4
-; GFX11-NEXT: s_and_b32 s0, s0, 15
-; GFX11-NEXT: s_lshl_b32 s2, s8, 8
+; GFX11-NEXT: s_or_b32 s0, s3, s0
+; GFX11-NEXT: s_or_b32 s1, s4, s1
; GFX11-NEXT: s_and_b32 s3, s30, 1
-; GFX11-NEXT: s_lshl_b32 s4, s29, 1
-; GFX11-NEXT: s_and_b32 s5, s28, 1
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_or_b32 s1, s9, s2
-; GFX11-NEXT: s_lshl_b32 s2, s31, 3
+; GFX11-NEXT: s_lshl_b32 s2, s9, 8
+; GFX11-NEXT: s_and_b32 s1, s1, 15
; GFX11-NEXT: s_lshl_b32 s3, s3, 2
-; GFX11-NEXT: s_or_b32 s4, s5, s4
-; GFX11-NEXT: s_and_b32 s5, s26, 1
-; GFX11-NEXT: s_lshl_b32 s6, s25, 1
-; GFX11-NEXT: s_and_b32 s7, s24, 1
-; GFX11-NEXT: s_or_b32 s2, s2, s3
-; GFX11-NEXT: s_and_b32 s3, s4, 3
-; GFX11-NEXT: s_lshl_b32 s4, s27, 3
-; GFX11-NEXT: s_lshl_b32 s5, s5, 2
-; GFX11-NEXT: s_or_b32 s6, s7, s6
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_and_b32 s5, s6, 3
-; GFX11-NEXT: s_or_b32 s2, s3, s2
-; GFX11-NEXT: s_or_b32 s3, s5, s4
-; GFX11-NEXT: s_and_b32 s5, s22, 1
-; GFX11-NEXT: s_lshl_b32 s6, s21, 1
-; GFX11-NEXT: s_and_b32 s7, s20, 1
-; GFX11-NEXT: s_lshl_b32 s4, s23, 3
-; GFX11-NEXT: s_lshl_b32 s5, s5, 2
-; GFX11-NEXT: s_or_b32 s6, s7, s6
-; GFX11-NEXT: s_and_b32 s7, s18, 1
-; GFX11-NEXT: s_lshl_b32 s8, s17, 1
-; GFX11-NEXT: s_and_b32 s9, s16, 1
-; GFX11-NEXT: s_or_b32 s4, s4, s5
-; GFX11-NEXT: s_and_b32 s5, s6, 3
-; GFX11-NEXT: s_lshl_b32 s6, s19, 3
-; GFX11-NEXT: s_lshl_b32 s7, s7, 2
-; GFX11-NEXT: s_or_b32 s8, s9, s8
-; GFX11-NEXT: s_or_b32 s6, s6, s7
-; GFX11-NEXT: s_and_b32 s7, s8, 3
-; GFX11-NEXT: s_or_b32 s4, s5, s4
+; GFX11-NEXT: s_and_b32 s4, s28, 1
+; GFX11-NEXT: s_lshl_b32 s5, s31, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s5, s5, s3
+; GFX11-NEXT: s_lshl_b32 s3, s29, 1
+; GFX11-NEXT: s_or_b32 s3, s3, s4
+; GFX11-NEXT: s_and_b32 s4, s26, 1
+; GFX11-NEXT: s_and_b32 s6, s24, 1
+; GFX11-NEXT: s_lshl_b32 s4, s4, 2
+; GFX11-NEXT: s_lshl_b32 s7, s25, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s7, s7, s6
+; GFX11-NEXT: s_and_b32 s3, s3, 3
+; GFX11-NEXT: s_lshl_b32 s6, s27, 3
+; GFX11-NEXT: s_or_b32 s6, s6, s4
+; GFX11-NEXT: s_lshl_b32 s4, s0, 4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s4, s4, s1
+; GFX11-NEXT: s_and_b32 s1, s7, 3
+; GFX11-NEXT: s_or_b32 s0, s3, s5
+; GFX11-NEXT: s_and_b32 s3, s22, 1
+; GFX11-NEXT: s_or_b32 s1, s1, s6
+; GFX11-NEXT: s_and_b32 s6, s18, 1
+; GFX11-NEXT: s_lshl_b32 s3, s3, 2
+; GFX11-NEXT: s_and_b32 s5, s20, 1
+; GFX11-NEXT: s_and_b32 s7, s16, 1
+; GFX11-NEXT: s_lshl_b32 s6, s6, 2
+; GFX11-NEXT: s_lshl_b32 s9, s17, 1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s9, s9, s7
+; GFX11-NEXT: s_lshl_b32 s7, s21, 1
+; GFX11-NEXT: s_or_b32 s7, s7, s5
+; GFX11-NEXT: s_lshl_b32 s5, s19, 3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s5, s5, s6
+; GFX11-NEXT: s_lshl_b32 s6, s23, 3
+; GFX11-NEXT: s_or_b32 s6, s6, s3
+; GFX11-NEXT: s_and_b32 s3, s9, 3
+; GFX11-NEXT: s_and_b32 s7, s7, 3
+; GFX11-NEXT: s_and_b32 s1, s1, 15
+; GFX11-NEXT: s_or_b32 s3, s3, s5
; GFX11-NEXT: s_or_b32 s5, s7, s6
; GFX11-NEXT: s_and_b32 s3, s3, 15
-; GFX11-NEXT: s_lshl_b32 s4, s4, 4
-; GFX11-NEXT: s_and_b32 s5, s5, 15
-; GFX11-NEXT: s_lshl_b32 s2, s2, 12
-; GFX11-NEXT: s_lshl_b32 s3, s3, 8
-; GFX11-NEXT: s_or_b32 s4, s5, s4
-; GFX11-NEXT: s_and_b32 s0, s0, 0xff
-; GFX11-NEXT: s_or_b32 s2, s2, s3
-; GFX11-NEXT: s_and_b32 s3, s4, 0xff
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_or_b32 s1, s3, s2
+; GFX11-NEXT: s_lshl_b32 s1, s1, 8
+; GFX11-NEXT: s_lshl_b32 s6, s5, 4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s6, s6, s3
+; GFX11-NEXT: s_lshl_b32 s3, s8, 12
+; GFX11-NEXT: s_or_b32 s3, s3, s2
+; GFX11-NEXT: s_lshl_b32 s2, s0, 12
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s2, s2, s1
+; GFX11-NEXT: s_and_b32 s0, s4, 0xff
+; GFX11-NEXT: s_and_b32 s1, s6, 0xff
+; GFX11-NEXT: s_or_b32 s0, s0, s3
+; GFX11-NEXT: s_or_b32 s1, s1, s2
; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
; GFX11-NEXT: s_lshl_b32 s1, s1, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
@@ -4674,96 +4738,107 @@ define amdgpu_cs void @amdgpu_cs_inreg_v32i1(<32 x i1> inreg %arg0) {
; GFX1250-LABEL: amdgpu_cs_inreg_v32i1:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_and_b32 s10, s10, 1
-; GFX1250-NEXT: s_lshl_b32 s9, s9, 1
-; GFX1250-NEXT: s_and_b32 s8, s8, 1
; GFX1250-NEXT: s_and_b32 s14, s14, 1
-; GFX1250-NEXT: s_lshl_b32 s13, s13, 1
+; GFX1250-NEXT: s_and_b32 s10, s10, 1
+; GFX1250-NEXT: s_lshl_b32 s14, s14, 2
; GFX1250-NEXT: s_and_b32 s12, s12, 1
-; GFX1250-NEXT: s_lshl_b32 s11, s11, 3
+; GFX1250-NEXT: s_and_b32 s8, s8, 1
; GFX1250-NEXT: s_lshl_b32 s10, s10, 2
-; GFX1250-NEXT: s_or_b32 s8, s8, s9
+; GFX1250-NEXT: s_lshl_b32 s33, s9, 1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s33, s33, s8
+; GFX1250-NEXT: s_lshl_b32 s8, s13, 1
+; GFX1250-NEXT: s_or_b32 s8, s8, s12
+; GFX1250-NEXT: s_lshl_b32 s9, s11, 3
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s9, s9, s10
+; GFX1250-NEXT: s_lshl_b32 s10, s15, 3
+; GFX1250-NEXT: s_or_b32 s10, s10, s14
+; GFX1250-NEXT: s_and_b32 s11, s33, 3
+; GFX1250-NEXT: s_and_b32 s8, s8, 3
+; GFX1250-NEXT: s_or_b32 s9, s11, s9
; GFX1250-NEXT: s_and_b32 s6, s6, 1
-; GFX1250-NEXT: s_lshl_b32 s5, s5, 1
+; GFX1250-NEXT: s_or_b32 s8, s8, s10
+; GFX1250-NEXT: s_and_b32 s9, s9, 15
; GFX1250-NEXT: s_and_b32 s4, s4, 1
+; GFX1250-NEXT: s_lshl_b32 s6, s6, 2
+; GFX1250-NEXT: s_lshl_b32 s10, s5, 1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s10, s10, s4
; GFX1250-NEXT: s_and_b32 s2, s2, 1
-; GFX1250-NEXT: s_lshl_b32 s1, s1, 1
; GFX1250-NEXT: s_and_b32 s0, s0, 1
-; GFX1250-NEXT: s_lshl_b32 s15, s15, 3
-; GFX1250-NEXT: s_lshl_b32 s14, s14, 2
-; GFX1250-NEXT: s_or_b32 s12, s12, s13
-; GFX1250-NEXT: s_or_b32 s9, s11, s10
-; GFX1250-NEXT: s_and_b32 s8, s8, 3
-; GFX1250-NEXT: s_lshl_b32 s7, s7, 3
-; GFX1250-NEXT: s_lshl_b32 s6, s6, 2
-; GFX1250-NEXT: s_or_b32 s4, s4, s5
-; GFX1250-NEXT: s_lshl_b32 s3, s3, 3
; GFX1250-NEXT: s_lshl_b32 s2, s2, 2
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_or_b32 s13, s15, s14
-; GFX1250-NEXT: s_and_b32 s12, s12, 3
-; GFX1250-NEXT: s_or_b32 s8, s8, s9
-; GFX1250-NEXT: s_or_b32 s5, s7, s6
+; GFX1250-NEXT: s_lshl_b32 s4, s1, 1
+; GFX1250-NEXT: s_or_b32 s4, s4, s0
+; GFX1250-NEXT: s_lshl_b32 s0, s7, 3
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s0, s0, s6
+; GFX1250-NEXT: s_lshl_b32 s1, s3, 3
+; GFX1250-NEXT: s_or_b32 s1, s1, s2
+; GFX1250-NEXT: s_and_b32 s3, s10, 3
; GFX1250-NEXT: s_and_b32 s4, s4, 3
-; GFX1250-NEXT: s_or_b32 s1, s3, s2
-; GFX1250-NEXT: s_and_b32 s0, s0, 3
-; GFX1250-NEXT: s_or_b32 s10, s12, s13
-; GFX1250-NEXT: s_and_b32 s8, s8, 15
-; GFX1250-NEXT: s_or_b32 s2, s4, s5
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_lshl_b32 s9, s10, 12
-; GFX1250-NEXT: s_lshl_b32 s1, s2, 4
-; GFX1250-NEXT: s_and_b32 s0, s0, 15
-; GFX1250-NEXT: s_lshl_b32 s2, s8, 8
+; GFX1250-NEXT: s_or_b32 s0, s3, s0
+; GFX1250-NEXT: s_or_b32 s1, s4, s1
; GFX1250-NEXT: s_and_b32 s3, s30, 1
-; GFX1250-NEXT: s_lshl_b32 s4, s29, 1
-; GFX1250-NEXT: s_and_b32 s5, s28, 1
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_or_b32 s1, s9, s2
-; GFX1250-NEXT: s_lshl_b32 s2, s31, 3
+; GFX1250-NEXT: s_lshl_b32 s2, s9, 8
+; GFX1250-NEXT: s_and_b32 s1, s1, 15
; GFX1250-NEXT: s_lshl_b32 s3, s3, 2
-; GFX1250-NEXT: s_or_b32 s4, s5, s4
-; GFX1250-NEXT: s_and_b32 s5, s26, 1
-; GFX1250-NEXT: s_lshl_b32 s6, s25, 1
-; GFX1250-NEXT: s_and_b32 s7, s24, 1
-; GFX1250-NEXT: s_or_b32 s2, s2, s3
-; GFX1250-NEXT: s_and_b32 s3, s4, 3
-; GFX1250-NEXT: s_lshl_b32 s4, s27, 3
-; GFX1250-NEXT: s_lshl_b32 s5, s5, 2
-; GFX1250-NEXT: s_or_b32 s6, s7, s6
-; GFX1250-NEXT: s_or_b32 s4, s4, s5
-; GFX1250-NEXT: s_and_b32 s5, s6, 3
-; GFX1250-NEXT: s_or_b32 s2, s3, s2
-; GFX1250-NEXT: s_or_b32 s3, s5, s4
-; GFX1250-NEXT: s_and_b32 s5, s22, 1
-; GFX1250-NEXT: s_lshl_b32 s6, s21, 1
-; GFX1250-NEXT: s_and_b32 s7, s20, 1
-; GFX1250-NEXT: s_lshl_b32 s4, s23, 3
-; GFX1250-NEXT: s_lshl_b32 s5, s5, 2
-; GFX1250-NEXT: s_or_b32 s6, s7, s6
-; GFX1250-NEXT: s_and_b32 s7, s18, 1
-; GFX1250-NEXT: s_lshl_b32 s8, s17, 1
-; GFX1250-NEXT: s_and_b32 s9, s16, 1
-; GFX1250-NEXT: s_or_b32 s4, s4, s5
-; GFX1250-NEXT: s_and_b32 s5, s6, 3
-; GFX1250-NEXT: s_lshl_b32 s6, s19, 3
-; GFX1250-NEXT: s_lshl_b32 s7, s7, 2
-; GFX1250-NEXT: s_or_b32 s8, s9, s8
-; GFX1250-NEXT: s_or_b32 s6, s6, s7
-; GFX1250-NEXT: s_and_b32 s7, s8, 3
-; GFX1250-NEXT: s_or_b32 s4, s5, s4
+; GFX1250-NEXT: s_and_b32 s4, s28, 1
+; GFX1250-NEXT: s_lshl_b32 s5, s31, 3
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s5, s5, s3
+; GFX1250-NEXT: s_lshl_b32 s3, s29, 1
+; GFX1250-NEXT: s_or_b32 s3, s3, s4
+; GFX1250-NEXT: s_and_b32 s4, s26, 1
+; GFX1250-NEXT: s_and_b32 s6, s24, 1
+; GFX1250-NEXT: s_lshl_b32 s4, s4, 2
+; GFX1250-NEXT: s_lshl_b32 s7, s25, 1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s7, s7, s6
+; GFX1250-NEXT: s_and_b32 s3, s3, 3
+; GFX1250-NEXT: s_lshl_b32 s6, s27, 3
+; GFX1250-NEXT: s_or_b32 s6, s6, s4
+; GFX1250-NEXT: s_lshl_b32 s4, s0, 4
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s4, s4, s1
+; GFX1250-NEXT: s_and_b32 s1, s7, 3
+; GFX1250-NEXT: s_or_b32 s0, s3, s5
+; GFX1250-NEXT: s_and_b32 s3, s22, 1
+; GFX1250-NEXT: s_or_b32 s1, s1, s6
+; GFX1250-NEXT: s_and_b32 s6, s18, 1
+; GFX1250-NEXT: s_lshl_b32 s3, s3, 2
+; GFX1250-NEXT: s_and_b32 s5, s20, 1
+; GFX1250-NEXT: s_and_b32 s7, s16, 1
+; GFX1250-NEXT: s_lshl_b32 s6, s6, 2
+; GFX1250-NEXT: s_lshl_b32 s9, s17, 1
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s9, s9, s7
+; GFX1250-NEXT: s_lshl_b32 s7, s21, 1
+; GFX1250-NEXT: s_or_b32 s7, s7, s5
+; GFX1250-NEXT: s_lshl_b32 s5, s19, 3
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s5, s5, s6
+; GFX1250-NEXT: s_lshl_b32 s6, s23, 3
+; GFX1250-NEXT: s_or_b32 s6, s6, s3
+; GFX1250-NEXT: s_and_b32 s3, s9, 3
+; GFX1250-NEXT: s_and_b32 s7, s7, 3
+; GFX1250-NEXT: s_and_b32 s1, s1, 15
+; GFX1250-NEXT: s_or_b32 s3, s3, s5
; GFX1250-NEXT: s_or_b32 s5, s7, s6
; GFX1250-NEXT: s_and_b32 s3, s3, 15
-; GFX1250-NEXT: s_lshl_b32 s4, s4, 4
-; GFX1250-NEXT: s_and_b32 s5, s5, 15
-; GFX1250-NEXT: s_lshl_b32 s2, s2, 12
-; GFX1250-NEXT: s_lshl_b32 s3, s3, 8
-; GFX1250-NEXT: s_or_b32 s4, s5, s4
-; GFX1250-NEXT: s_and_b32 s0, s0, 0xff
-; GFX1250-NEXT: s_or_b32 s2, s2, s3
-; GFX1250-NEXT: s_and_b32 s3, s4, 0xff
-; GFX1250-NEXT: s_or_b32 s0, s0, s1
-; GFX1250-NEXT: s_or_b32 s1, s3, s2
+; GFX1250-NEXT: s_lshl_b32 s1, s1, 8
+; GFX1250-NEXT: s_lshl_b32 s6, s5, 4
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s6, s6, s3
+; GFX1250-NEXT: s_lshl_b32 s3, s8, 12
+; GFX1250-NEXT: s_or_b32 s3, s3, s2
+; GFX1250-NEXT: s_lshl_b32 s2, s0, 12
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s2, s2, s1
+; GFX1250-NEXT: s_and_b32 s0, s4, 0xff
+; GFX1250-NEXT: s_and_b32 s1, s6, 0xff
+; GFX1250-NEXT: s_or_b32 s0, s0, s3
+; GFX1250-NEXT: s_or_b32 s1, s1, s2
; GFX1250-NEXT: s_and_b32 s0, s0, 0xffff
; GFX1250-NEXT: s_lshl_b32 s1, s1, 16
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
diff --git a/llvm/test/CodeGen/AMDGPU/ds_read2.ll b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
index 9f1b55ea3b1ef..7f1231edb1e9b 100644
--- a/llvm/test/CodeGen/AMDGPU/ds_read2.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds_read2.ll
@@ -1489,24 +1489,20 @@ define amdgpu_kernel void @read2_v2i32_align1_odd_offset(ptr addrspace(1) %out)
; GFX9-ALIGNED-NEXT: v_mov_b32_e32 v2, 0
; GFX9-ALIGNED-NEXT: ds_read_u8 v0, v2 offset:65
; GFX9-ALIGNED-NEXT: ds_read_u8 v3, v2 offset:66
-; GFX9-ALIGNED-NEXT: ds_read_u8 v4, v2 offset:67
-; GFX9-ALIGNED-NEXT: ds_read_u8 v5, v2 offset:68
-; GFX9-ALIGNED-NEXT: ds_read_u8 v1, v2 offset:70
-; GFX9-ALIGNED-NEXT: ds_read_u8 v6, v2 offset:69
-; GFX9-ALIGNED-NEXT: ds_read_u8 v7, v2 offset:72
-; GFX9-ALIGNED-NEXT: ds_read_u8 v8, v2 offset:71
+; GFX9-ALIGNED-NEXT: ds_read_u8 v1, v2 offset:69
+; GFX9-ALIGNED-NEXT: ds_read_u8 v4, v2 offset:70
+; GFX9-ALIGNED-NEXT: ds_read_u8 v5, v2 offset:71
+; GFX9-ALIGNED-NEXT: ds_read_u8 v6, v2 offset:72
+; GFX9-ALIGNED-NEXT: ds_read_u8 v7, v2 offset:67
+; GFX9-ALIGNED-NEXT: ds_read_u8 v8, v2 offset:68
; GFX9-ALIGNED-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-ALIGNED-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX9-ALIGNED-NEXT: v_or_b32_e32 v1, v1, v6
-; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v6, 8, v7
-; GFX9-ALIGNED-NEXT: v_or_b32_e32 v0, v3, v0
-; GFX9-ALIGNED-NEXT: v_lshlrev_b32_e32 v3, 8, v5
-; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-ALIGNED-NEXT: v_or_b32_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-ALIGNED-NEXT: v_or_b32_e32 v1, v6, v1
-; GFX9-ALIGNED-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v1, v4, 8, v1
+; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v4, v6, 8, v5
+; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v0, v3, 8, v0
+; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v3, v8, 8, v7
+; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v1, v4, 16, v1
+; GFX9-ALIGNED-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; GFX9-ALIGNED-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-ALIGNED-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll b/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
index 217868d5b7b59..a78887097f11f 100644
--- a/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract-i8-codegen.ll
@@ -19,8 +19,7 @@ define void @extract_multiple_v16i8(ptr addrspace(1) %out) {
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_perm_b32 v2, v2, v3, s0
; GFX9-NEXT: v_perm_b32 v3, v4, v5, s0
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
@@ -32,11 +31,10 @@ define void @extract_multiple_v16i8(ptr addrspace(1) %out) {
; GFX12-NEXT: v_mov_b32_e32 v2, 0
; GFX12-NEXT: ds_load_b128 v[2:5], v2
; GFX12-NEXT: s_wait_dscnt 0x0
-; GFX12-NEXT: v_perm_b32 v4, v4, v5, 0xc0c0004
; GFX12-NEXT: v_perm_b32 v2, v2, v3, 0xc0c0004
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-NEXT: v_lshlrev_b32_e32 v3, 16, v4
-; GFX12-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX12-NEXT: v_perm_b32 v3, v4, v5, 0xc0c0004
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_lshl_or_b32 v2, v3, 16, v2
; GFX12-NEXT: global_store_b32 v[0:1], v2, off
; GFX12-NEXT: s_set_pc_i64 s[30:31]
%ptr = getelementptr inbounds i8, ptr addrspace(3) @lds, i32 0
@@ -67,9 +65,9 @@ define void @extract_multiple_v8i8(ptr addrspace(1) %out) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v3
; GFX9-NEXT: s_and_b32 s1, s0, 0xff
; GFX9-NEXT: s_lshr_b32 s0, s0, 24
-; GFX9-NEXT: s_lshl_b32 s0, s0, 8
-; GFX9-NEXT: s_or_b32 s0, s1, s0
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: s_lshl_b32 s2, s0, 8
+; GFX9-NEXT: s_or_b32 s2, s2, s1
+; GFX9-NEXT: s_lshl_b32 s0, s2, 16
; GFX9-NEXT: v_or_b32_sdwa v2, v2, s0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 0ae807783a151..9bec0c11c3c45 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -1195,10 +1195,10 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f64_sign_f16(double inreg %mag, hal
; GFX9-NEXT: s_lshl_b32 s4, s5, s4
; GFX9-NEXT: s_cmp_lg_u32 s4, s3
; GFX9-NEXT: s_cselect_b32 s3, 1, 0
+; GFX9-NEXT: s_or_b32 s3, s5, s3
; GFX9-NEXT: s_addk_i32 s1, 0xfc10
; GFX9-NEXT: s_lshl_b32 s4, s1, 12
-; GFX9-NEXT: s_or_b32 s3, s5, s3
-; GFX9-NEXT: s_or_b32 s4, s0, s4
+; GFX9-NEXT: s_or_b32 s4, s4, s0
; GFX9-NEXT: s_cmp_lt_i32 s1, 1
; GFX9-NEXT: s_cselect_b32 s3, s3, s4
; GFX9-NEXT: s_and_b32 s4, s3, 7
@@ -1247,14 +1247,14 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f64_sign_f16(double inreg %mag, hal
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s4, s3
; GFX11-TRUE16-NEXT: s_cselect_b32 s3, 1, 0
; GFX11-TRUE16-NEXT: s_addk_i32 s0, 0xfc10
-; GFX11-TRUE16-NEXT: s_or_b32 s3, s5, s3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s0, 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: s_or_b32 s4, s1, s4
+; GFX11-TRUE16-NEXT: s_or_b32 s4, s4, s1
+; GFX11-TRUE16-NEXT: s_or_b32 s3, s5, s3
; GFX11-TRUE16-NEXT: s_cmp_lt_i32 s0, 1
; GFX11-TRUE16-NEXT: s_cselect_b32 s3, s3, s4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s4, s3, 7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s4, 5
; GFX11-TRUE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_eq_u32 s4, 3
@@ -1298,17 +1298,18 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f64_sign_f16(double inreg %mag, hal
; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s3, s4
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s5, s4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s4, s3
; GFX11-FAKE16-NEXT: s_cselect_b32 s3, 1, 0
; GFX11-FAKE16-NEXT: s_addk_i32 s0, 0xfc10
-; GFX11-FAKE16-NEXT: s_or_b32 s3, s5, s3
; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s0, 12
-; GFX11-FAKE16-NEXT: s_or_b32 s4, s1, s4
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-FAKE16-NEXT: s_or_b32 s4, s4, s1
+; GFX11-FAKE16-NEXT: s_or_b32 s3, s5, s3
; GFX11-FAKE16-NEXT: s_cmp_lt_i32 s0, 1
; GFX11-FAKE16-NEXT: s_cselect_b32 s3, s3, s4
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_and_b32 s4, s3, 7
+; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-FAKE16-NEXT: s_cmp_gt_i32 s4, 5
; GFX11-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-FAKE16-NEXT: s_cmp_eq_u32 s4, 3
@@ -3962,10 +3963,10 @@ define amdgpu_ps i32 @s_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> inr
; GFX9-NEXT: s_lshl_b32 s7, s8, s7
; GFX9-NEXT: s_cmp_lg_u32 s7, s5
; GFX9-NEXT: s_cselect_b32 s5, 1, 0
+; GFX9-NEXT: s_or_b32 s5, s8, s5
; GFX9-NEXT: s_addk_i32 s6, 0xfc10
; GFX9-NEXT: s_lshl_b32 s7, s6, 12
-; GFX9-NEXT: s_or_b32 s5, s8, s5
-; GFX9-NEXT: s_or_b32 s7, s2, s7
+; GFX9-NEXT: s_or_b32 s7, s7, s2
; GFX9-NEXT: s_cmp_lt_i32 s6, 1
; GFX9-NEXT: s_cselect_b32 s5, s5, s7
; GFX9-NEXT: s_and_b32 s7, s5, 7
@@ -4003,10 +4004,10 @@ define amdgpu_ps i32 @s_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> inr
; GFX9-NEXT: s_lshl_b32 s6, s8, s6
; GFX9-NEXT: s_cmp_lg_u32 s6, s2
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_or_b32 s2, s8, s2
; GFX9-NEXT: s_addk_i32 s3, 0xfc10
; GFX9-NEXT: s_lshl_b32 s6, s3, 12
-; GFX9-NEXT: s_or_b32 s2, s8, s2
-; GFX9-NEXT: s_or_b32 s6, s0, s6
+; GFX9-NEXT: s_or_b32 s6, s6, s0
; GFX9-NEXT: s_cmp_lt_i32 s3, 1
; GFX9-NEXT: s_cselect_b32 s2, s2, s6
; GFX9-NEXT: s_and_b32 s6, s2, 7
@@ -4055,17 +4056,18 @@ define amdgpu_ps i32 @s_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> inr
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s8, s6, s7
; GFX11-NEXT: s_lshl_b32 s7, s8, s7
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_cmp_lg_u32 s7, s6
; GFX11-NEXT: s_cselect_b32 s6, 1, 0
; GFX11-NEXT: s_addk_i32 s2, 0xfc10
-; GFX11-NEXT: s_or_b32 s6, s8, s6
; GFX11-NEXT: s_lshl_b32 s7, s2, 12
-; GFX11-NEXT: s_or_b32 s7, s5, s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s7, s7, s5
+; GFX11-NEXT: s_or_b32 s6, s8, s6
; GFX11-NEXT: s_cmp_lt_i32 s2, 1
; GFX11-NEXT: s_cselect_b32 s6, s6, s7
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s7, s6, 7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_cmp_gt_i32 s7, 5
; GFX11-NEXT: s_cselect_b32 s8, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s7, 3
@@ -4104,17 +4106,18 @@ define amdgpu_ps i32 @s_copysign_out_v2f16_mag_v2f64_sign_v2f16(<2 x double> inr
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b32 s8, s5, s6
; GFX11-NEXT: s_lshl_b32 s6, s8, s6
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_cmp_lg_u32 s6, s5
; GFX11-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-NEXT: s_addk_i32 s0, 0xfc10
-; GFX11-NEXT: s_or_b32 s5, s8, s5
; GFX11-NEXT: s_lshl_b32 s6, s0, 12
-; GFX11-NEXT: s_or_b32 s6, s3, s6
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s6, s6, s3
+; GFX11-NEXT: s_or_b32 s5, s8, s5
; GFX11-NEXT: s_cmp_lt_i32 s0, 1
; GFX11-NEXT: s_cselect_b32 s5, s5, s6
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s6, s5, 7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_cmp_gt_i32 s6, 5
; GFX11-NEXT: s_cselect_b32 s8, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s6, 3
@@ -6876,12 +6879,12 @@ define amdgpu_ps i32 @s_copysign_f16_0_f64(double inreg %sign) {
; GFX9-NEXT: s_lshl_b32 s4, s5, s4
; GFX9-NEXT: s_cmp_lg_u32 s4, s2
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
+; GFX9-NEXT: s_or_b32 s2, s5, s2
; GFX9-NEXT: s_add_i32 s4, s3, 0xfffffc10
; GFX9-NEXT: s_lshl_b32 s3, s4, 12
-; GFX9-NEXT: s_or_b32 s2, s5, s2
-; GFX9-NEXT: s_or_b32 s0, s0, s3
+; GFX9-NEXT: s_or_b32 s3, s3, s0
; GFX9-NEXT: s_cmp_lt_i32 s4, 1
-; GFX9-NEXT: s_cselect_b32 s0, s2, s0
+; GFX9-NEXT: s_cselect_b32 s0, s2, s3
; GFX9-NEXT: s_and_b32 s2, s0, 7
; GFX9-NEXT: s_cmp_gt_i32 s2, 5
; GFX9-NEXT: s_cselect_b32 s3, 1, 0
@@ -6926,14 +6929,14 @@ define amdgpu_ps i32 @s_copysign_f16_0_f64(double inreg %sign) {
; GFX11-NEXT: s_cmp_lg_u32 s4, s3
; GFX11-NEXT: s_cselect_b32 s3, 1, 0
; GFX11-NEXT: s_addk_i32 s0, 0xfc10
-; GFX11-NEXT: s_or_b32 s3, s5, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshl_b32 s4, s0, 12
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s2, s2, s4
+; GFX11-NEXT: s_or_b32 s4, s4, s2
+; GFX11-NEXT: s_or_b32 s2, s5, s3
; GFX11-NEXT: s_cmp_lt_i32 s0, 1
-; GFX11-NEXT: s_cselect_b32 s2, s3, s2
+; GFX11-NEXT: s_cselect_b32 s2, s2, s4
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_and_b32 s3, s2, 7
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: s_cmp_gt_i32 s3, 5
; GFX11-NEXT: s_cselect_b32 s4, 1, 0
; GFX11-NEXT: s_cmp_eq_u32 s3, 3
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index a893711ce0942..cb02c1da85b3f 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -2006,24 +2006,23 @@ define <2 x i8> @test_s_signed_v2f64_v2i8(<2 x double> inreg %f) {
; GFX9-NEXT: s_movk_i32 s4, 0xff80
; GFX9-NEXT: v_mov_b32_e32 v2, 0x7f
; GFX9-NEXT: v_med3_i32 v3, v0, s4, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v3
-; GFX9-NEXT: v_med3_i32 v1, v1, s4, v2
-; GFX9-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_med3_i32 v0, v1, s4, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX9-NEXT: v_lshl_or_b32 v0, v3, 8, v0
; GFX9-NEXT: v_and_b32_e32 v1, 0xff, v3
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_signed_v2f64_v2i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_i32_f64_e32 v0, s[2:3]
-; GFX11-NEXT: v_cvt_i32_f64_e32 v1, s[0:1]
+; GFX11-NEXT: v_cvt_i32_f64_e32 v0, s[0:1]
+; GFX11-NEXT: v_cvt_i32_f64_e32 v1, s[2:3]
; GFX11-NEXT: s_movk_i32 s0, 0xff80
-; GFX11-NEXT: v_med3_i32 v2, v0, s0, 0x7f
-; GFX11-NEXT: v_med3_i32 v0, v1, s0, 0x7f
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v2
+; GFX11-NEXT: v_med3_i32 v0, v0, s0, 0x7f
+; GFX11-NEXT: v_med3_i32 v1, v1, s0, 0x7f
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 8, v0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_v2f64_v2i8:
@@ -2033,16 +2032,15 @@ define <2 x i8> @test_s_signed_v2f64_v2i8(<2 x double> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-ISEL-NEXT: v_cvt_i32_f64_e32 v0, s[2:3]
-; GFX12-ISEL-NEXT: v_cvt_i32_f64_e32 v1, s[0:1]
+; GFX12-ISEL-NEXT: v_cvt_i32_f64_e32 v0, s[0:1]
+; GFX12-ISEL-NEXT: v_cvt_i32_f64_e32 v1, s[2:3]
; GFX12-ISEL-NEXT: s_movk_i32 s0, 0xff80
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_med3_i32 v2, v0, s0, 0x7f
-; GFX12-ISEL-NEXT: v_med3_i32 v0, v1, s0, 0x7f
-; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v2
+; GFX12-ISEL-NEXT: v_med3_i32 v0, v0, s0, 0x7f
+; GFX12-ISEL-NEXT: v_med3_i32 v1, v1, s0, 0x7f
; GFX12-ISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-ISEL-NEXT: v_or_b32_e32 v0, v0, v1
-; GFX12-ISEL-NEXT: v_and_b32_e32 v1, 0xff, v2
+; GFX12-ISEL-NEXT: v_lshl_or_b32 v0, v1, 8, v0
+; GFX12-ISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_v2f64_v2i8:
@@ -3542,19 +3540,19 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7f
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX9-NEXT: v_med3_i32 v2, v2, s4, v1
-; GFX9-NEXT: s_lshr_b32 s5, s17, 16
-; GFX9-NEXT: v_cvt_i16_f16_e32 v0, s16
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v2
; GFX9-NEXT: v_cvt_i16_f16_e32 v2, s17
+; GFX9-NEXT: s_lshr_b32 s5, s17, 16
+; GFX9-NEXT: v_cvt_i16_f16_e32 v0, s16
+; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX9-NEXT: v_cvt_i16_f16_e32 v4, s5
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX9-NEXT: v_med3_i32 v2, v2, s4, v1
; GFX9-NEXT: v_bfe_i32 v4, v4, 0, 16
; GFX9-NEXT: v_med3_i32 v0, v0, s4, v1
-; GFX9-NEXT: v_med3_i32 v2, v2, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v2
; GFX9-NEXT: v_med3_i32 v1, v4, s4, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_or_b32_sdwa v2, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v2, v1, 8, v2
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX9-NEXT: v_and_b32_e32 v3, 0xff00, v3
@@ -3566,63 +3564,61 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-FAKE16-LABEL: test_s_signed_v4f16_v4i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, s1
+; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s0, 16
+; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s2
-; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, s1
; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-FAKE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
+; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-FAKE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
+; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX11-FAKE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX11-FAKE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v0, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v2, 8, v0
; GFX11-FAKE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff00, v1
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_s_signed_v4f16_v4i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
+; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
+; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
-; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-TRUE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
+; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
+; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v0, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 8, v0
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xff00, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_s_signed_v4f16_v4i8:
@@ -3632,35 +3628,33 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, s1
+; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s0, 16
+; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s2
-; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, s1
; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-FAKE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX12-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s0
+; GFX12-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
+; GFX12-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX12-FAKE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX12-FAKE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v0, v1
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v2, 8, v0
; GFX12-FAKE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xff00, v1
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX12-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-TRUE16-LABEL: test_s_signed_v4f16_v4i8:
@@ -3670,35 +3664,33 @@ define <4 x i8> @test_s_signed_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
+; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
+; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
-; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-TRUE16-NEXT: s_movk_i32 s1, 0xff80
-; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
+; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, s1, 0x7f
+; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
; GFX12-TRUE16-NEXT: v_med3_i32 v1, v1, s1, 0x7f
; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, s1, 0x7f
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v0, v1
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v2, v2, 8, v0
; GFX12-TRUE16-NEXT: v_med3_i32 v0, v3, s1, 0x7f
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xff00, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xff00, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_v4f16_v4i8:
@@ -5819,36 +5811,36 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX9-LABEL: test_s_signed_v8f16_v8i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_lshr_b32 s5, s18, 16
-; GFX9-NEXT: v_cvt_i16_f16_e32 v2, s5
; GFX9-NEXT: v_cvt_i16_f16_e32 v0, s18
+; GFX9-NEXT: s_lshr_b32 s5, s18, 16
+; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX9-NEXT: s_movk_i32 s4, 0xff80
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7f
+; GFX9-NEXT: v_cvt_i16_f16_e32 v2, s5
+; GFX9-NEXT: v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: v_med3_i32 v2, v2, s4, v1
-; GFX9-NEXT: v_med3_i32 v0, v0, s4, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX9-NEXT: v_lshl_or_b32 v8, v2, 8, v0
+; GFX9-NEXT: v_cvt_i16_f16_e32 v0, s19
; GFX9-NEXT: s_lshr_b32 s5, s19, 16
-; GFX9-NEXT: v_or_b32_sdwa v8, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX9-NEXT: v_cvt_i16_f16_e32 v2, s5
-; GFX9-NEXT: v_cvt_i16_f16_e32 v0, s19
+; GFX9-NEXT: v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: v_med3_i32 v2, v2, s4, v1
-; GFX9-NEXT: v_med3_i32 v0, v0, s4, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX9-NEXT: v_lshl_or_b32 v6, v2, 8, v0
+; GFX9-NEXT: v_cvt_i16_f16_e32 v0, s17
; GFX9-NEXT: s_lshr_b32 s5, s17, 16
-; GFX9-NEXT: v_or_b32_sdwa v6, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX9-NEXT: v_cvt_i16_f16_e32 v2, s5
-; GFX9-NEXT: v_cvt_i16_f16_e32 v0, s17
+; GFX9-NEXT: v_med3_i32 v0, v0, s4, v1
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX9-NEXT: v_med3_i32 v2, v2, s4, v1
-; GFX9-NEXT: v_med3_i32 v0, v0, s4, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
; GFX9-NEXT: s_lshr_b32 s5, s16, 16
-; GFX9-NEXT: v_or_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 8, v0
; GFX9-NEXT: v_cvt_i16_f16_e32 v0, s16
; GFX9-NEXT: v_cvt_i16_f16_e32 v9, s5
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
@@ -5872,54 +5864,51 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-FAKE16-LABEL: test_s_signed_v8f16_v8i8:
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, s3
-; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s2, 16
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s4
-; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, s2
+; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s3
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, s2
; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s1
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v4, s4
-; GFX11-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v5, s3
+; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX11-FAKE16-NEXT: s_movk_i32 s2, 0xff80
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v4, s1
; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, 16
; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX11-FAKE16-NEXT: v_bfe_i32 v4, v4, 0, 16
-; GFX11-FAKE16-NEXT: v_med3_i32 v2, v2, s2, 0x7f
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v6, s1
-; GFX11-FAKE16-NEXT: v_bfe_i32 v5, v5, 0, 16
+; GFX11-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-FAKE16-NEXT: v_med3_i32 v0, v0, s2, 0x7f
+; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v5, s1
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v6, s3
; GFX11-FAKE16-NEXT: v_med3_i32 v1, v1, s2, 0x7f
+; GFX11-FAKE16-NEXT: v_med3_i32 v2, v2, s2, 0x7f
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_med3_i32 v3, v3, s2, 0x7f
+; GFX11-FAKE16-NEXT: v_bfe_i32 v4, v4, 0, 16
+; GFX11-FAKE16-NEXT: v_bfe_i32 v5, v5, 0, 16
+; GFX11-FAKE16-NEXT: v_bfe_i32 v6, v6, 0, 16
+; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v7, s0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-FAKE16-NEXT: v_med3_i32 v4, v4, s2, 0x7f
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v2
-; GFX11-FAKE16-NEXT: v_bfe_i32 v2, v6, 0, 16
; GFX11-FAKE16-NEXT: v_med3_i32 v5, v5, s2, 0x7f
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX11-FAKE16-NEXT: v_cvt_i16_f16_e32 v6, s0
-; GFX11-FAKE16-NEXT: v_med3_i32 v9, v2, s2, 0x7f
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v0, v1
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v6, 0, 16
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v9
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v5
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; GFX11-FAKE16-NEXT: v_med3_i32 v6, v6, s2, 0x7f
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 8, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 8, v3
+; GFX11-FAKE16-NEXT: v_bfe_i32 v0, v7, 0, 16
+; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v5
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 8, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX11-FAKE16-NEXT: v_med3_i32 v0, v0, s2, 0x7f
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff00, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xff00, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v9, v5, v4
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, v1, v7
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX11-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
@@ -5929,54 +5918,51 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-TRUE16-LABEL: test_s_signed_v8f16_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s3
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s2, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s4
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s3
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s2
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s1
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.l, s4
-; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v5.l, s3
+; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX11-TRUE16-NEXT: s_movk_i32 s2, 0xff80
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.l, s1
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 16
-; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, s2, 0x7f
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v6.l, s1
-; GFX11-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, s2, 0x7f
+; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v5.l, s1
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v6.l, s3
; GFX11-TRUE16-NEXT: v_med3_i32 v1, v1, s2, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, s2, 0x7f
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_med3_i32 v3, v3, s2, 0x7f
+; GFX11-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v6, v6, 0, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v7.l, s0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX11-TRUE16-NEXT: v_med3_i32 v4, v4, s2, 0x7f
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xff, v2
-; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v5, v5, s2, 0x7f
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v6.l, s0
-; GFX11-TRUE16-NEXT: v_med3_i32 v9, v2, s2, 0x7f
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v0, v1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v6, 0, 16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v9
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v7, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; GFX11-TRUE16-NEXT: v_med3_i32 v6, v6, s2, 0x7f
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v2, 8, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 8, v3
+; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v7, 0, 16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v5
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 8, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, s2, 0x7f
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xff00, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xff00, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_or_b32_e32 v9, v5, v4
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v3, v7
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, v1, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, v0, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
@@ -5990,57 +5976,54 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, s3
-; GFX12-FAKE16-NEXT: s_lshr_b32 s4, s2, 16
-; GFX12-FAKE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s4
-; GFX12-FAKE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v0, s2
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s1
+; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s2, 16
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v1, s3
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v4, s4
-; GFX12-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v5, s3
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v2, s2
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v3, s1
+; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX12-FAKE16-NEXT: s_movk_i32 s2, 0xff80
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v4, s1
; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-FAKE16-NEXT: s_lshr_b32 s3, s3, 16
; GFX12-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-FAKE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX12-FAKE16-NEXT: v_med3_i32 v0, v0, s2, 0x7f
; GFX12-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX12-FAKE16-NEXT: v_bfe_i32 v4, v4, 0, 16
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_med3_i32 v2, v2, s2, 0x7f
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v6, s1
-; GFX12-FAKE16-NEXT: v_bfe_i32 v5, v5, 0, 16
-; GFX12-FAKE16-NEXT: v_med3_i32 v0, v0, s2, 0x7f
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v5, s1
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v6, s3
; GFX12-FAKE16-NEXT: v_med3_i32 v1, v1, s2, 0x7f
+; GFX12-FAKE16-NEXT: v_med3_i32 v2, v2, s2, 0x7f
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: v_med3_i32 v3, v3, s2, 0x7f
+; GFX12-FAKE16-NEXT: v_bfe_i32 v4, v4, 0, 16
+; GFX12-FAKE16-NEXT: v_bfe_i32 v5, v5, 0, 16
+; GFX12-FAKE16-NEXT: v_bfe_i32 v6, v6, 0, 16
+; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v7, s0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX12-FAKE16-NEXT: v_med3_i32 v4, v4, s2, 0x7f
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v7, 0xff, v2
-; GFX12-FAKE16-NEXT: v_bfe_i32 v2, v6, 0, 16
; GFX12-FAKE16-NEXT: v_med3_i32 v5, v5, s2, 0x7f
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX12-FAKE16-NEXT: v_cvt_i16_f16_e32 v6, s0
-; GFX12-FAKE16-NEXT: v_med3_i32 v9, v2, s2, 0x7f
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, v0, v1
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v6, 0, 16
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v9
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, v7, v5
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; GFX12-FAKE16-NEXT: v_med3_i32 v6, v6, s2, 0x7f
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v8, v2, 8, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 8, v3
+; GFX12-FAKE16-NEXT: v_bfe_i32 v0, v7, 0, 16
+; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v5
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v6, v6, 8, v1
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX12-FAKE16-NEXT: v_med3_i32 v0, v0, s2, 0x7f
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xff00, v1
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xff00, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: v_or_b32_e32 v9, v5, v4
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, v3, v7
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v5, v1, v7
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-FAKE16-NEXT: v_or_b32_e32 v0, v0, v3
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX12-FAKE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX12-FAKE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
@@ -6054,57 +6037,54 @@ define <8 x i8> @test_s_signed_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s3
-; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s2, 16
-; GFX12-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s4
-; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s2
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s1
+; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.l, s4
-; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v5.l, s3
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s2
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s1
+; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX12-TRUE16-NEXT: s_movk_i32 s2, 0xff80
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.l, s1
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, s2, 0x7f
; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, s2, 0x7f
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v6.l, s1
-; GFX12-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 16
-; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, s2, 0x7f
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v5.l, s1
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v6.l, s3
; GFX12-TRUE16-NEXT: v_med3_i32 v1, v1, s2, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, s2, 0x7f
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: v_med3_i32 v3, v3, s2, 0x7f
+; GFX12-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v6, v6, 0, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v7.l, s0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xff, v3
; GFX12-TRUE16-NEXT: v_med3_i32 v4, v4, s2, 0x7f
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xff, v2
-; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 16
; GFX12-TRUE16-NEXT: v_med3_i32 v5, v5, s2, 0x7f
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xff, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v6.l, s0
-; GFX12-TRUE16-NEXT: v_med3_i32 v9, v2, s2, 0x7f
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 8, v5
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, v0, v1
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v3, v4
-; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v6, 0, 16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v9
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, v7, v5
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
+; GFX12-TRUE16-NEXT: v_med3_i32 v6, v6, s2, 0x7f
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v8, v2, 8, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v2, v4, 8, v3
+; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v7, 0, 16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v5
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v6, v6, 8, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v8
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, s2, 0x7f
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xff00, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xff00, v3
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: v_or_b32_e32 v9, v5, v4
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, v3, v7
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v5, v1, v7
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX12-TRUE16-NEXT: v_or_b32_e32 v0, v0, v3
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v9
; GFX12-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[4:5]
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v5
@@ -6948,18 +6928,18 @@ define <4 x i8> @test_s_signed_v4f32_v4i8(<4 x float> inreg %f) {
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_cvt_i32_f32_e32 v0, s17
; GFX9-NEXT: v_cvt_i32_f32_e32 v2, s16
+; GFX9-NEXT: v_cvt_i32_f32_e32 v4, s19
+; GFX9-NEXT: v_cvt_i32_f32_e32 v5, s18
; GFX9-NEXT: s_movk_i32 s4, 0xff80
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7f
; GFX9-NEXT: v_med3_i32 v0, v0, s4, v1
-; GFX9-NEXT: v_cvt_i32_f32_e32 v4, s19
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v0
; GFX9-NEXT: v_med3_i32 v0, v2, s4, v1
-; GFX9-NEXT: v_cvt_i32_f32_e32 v2, s18
-; GFX9-NEXT: v_med3_i32 v4, v4, s4, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX9-NEXT: v_med3_i32 v2, v4, s4, v1
+; GFX9-NEXT: v_med3_i32 v1, v5, s4, v1
+; GFX9-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 8, v1
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX9-NEXT: v_med3_i32 v1, v2, s4, v1
-; GFX9-NEXT: v_or_b32_sdwa v2, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v2
; GFX9-NEXT: v_and_b32_e32 v3, 0xff00, v3
; GFX9-NEXT: v_or_b32_e32 v4, v3, v1
@@ -6970,26 +6950,25 @@ define <4 x i8> @test_s_signed_v4f32_v4i8(<4 x float> inreg %f) {
; GFX11-LABEL: test_s_signed_v4f32_v4i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_i32_f32_e32 v0, s3
-; GFX11-NEXT: v_cvt_i32_f32_e32 v1, s2
-; GFX11-NEXT: s_movk_i32 s2, 0xff80
-; GFX11-NEXT: v_cvt_i32_f32_e32 v2, s1
+; GFX11-NEXT: v_cvt_i32_f32_e32 v0, s2
+; GFX11-NEXT: v_cvt_i32_f32_e32 v1, s1
+; GFX11-NEXT: s_movk_i32 s1, 0xff80
+; GFX11-NEXT: v_cvt_i32_f32_e32 v2, s3
; GFX11-NEXT: v_cvt_i32_f32_e32 v3, s0
-; GFX11-NEXT: v_med3_i32 v0, v0, s2, 0x7f
-; GFX11-NEXT: v_med3_i32 v1, v1, s2, 0x7f
-; GFX11-NEXT: v_med3_i32 v2, v2, s2, 0x7f
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
-; GFX11-NEXT: v_lshlrev_b32_e32 v4, 8, v2
-; GFX11-NEXT: v_or_b32_e32 v2, v1, v0
-; GFX11-NEXT: v_med3_i32 v0, v3, s2, 0x7f
-; GFX11-NEXT: v_and_b32_e32 v1, 0xff00, v4
-; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11-NEXT: v_med3_i32 v0, v0, s1, 0x7f
+; GFX11-NEXT: v_med3_i32 v1, v1, s1, 0x7f
+; GFX11-NEXT: v_med3_i32 v2, v2, s1, 0x7f
+; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX11-NEXT: v_lshl_or_b32 v2, v2, 8, v0
+; GFX11-NEXT: v_med3_i32 v0, v3, s1, 0x7f
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff00, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v4
-; GFX11-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX11-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX11-NEXT: v_lshrrev_b32_e32 v1, 8, v3
+; GFX11-NEXT: v_lshrrev_b32_e32 v3, 24, v4
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_signed_v4f32_v4i8:
@@ -7000,26 +6979,26 @@ define <4 x i8> @test_s_signed_v4f32_v4i8(<4 x float> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-ISEL-NEXT: v_mov_b32_e32 v0, 0x7f
-; GFX12-ISEL-NEXT: s_cvt_i32_f32 s3, s3
; GFX12-ISEL-NEXT: s_cvt_i32_f32 s2, s2
; GFX12-ISEL-NEXT: s_cvt_i32_f32 s1, s1
; GFX12-ISEL-NEXT: s_cvt_i32_f32 s0, s0
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: v_med3_i32 v1, 0xffffff80, s3, v0
-; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX12-ISEL-NEXT: v_med3_i32 v2, 0xffffff80, s2, v0
-; GFX12-ISEL-NEXT: v_med3_i32 v3, 0xffffff80, s1, v0
+; GFX12-ISEL-NEXT: v_med3_i32 v1, 0xffffff80, s2, v0
+; GFX12-ISEL-NEXT: s_cvt_i32_f32 s2, s3
+; GFX12-ISEL-NEXT: v_med3_i32 v2, 0xffffff80, s1, v0
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-ISEL-NEXT: v_med3_i32 v3, 0xffffff80, s2, v0
+; GFX12-ISEL-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v4, 8, v2
+; GFX12-ISEL-NEXT: v_lshl_or_b32 v2, v3, 8, v1
+; GFX12-ISEL-NEXT: v_and_b32_e32 v1, 0xff00, v4
+; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX12-ISEL-NEXT: v_med3_i32 v0, 0xffffff80, s0, v0
-; GFX12-ISEL-NEXT: v_and_b32_e32 v2, 0xff, v2
-; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX12-ISEL-NEXT: v_or_b32_e32 v1, v1, v3
; GFX12-ISEL-NEXT: v_and_b32_e32 v0, 0xff, v0
-; GFX12-ISEL-NEXT: v_or_b32_e32 v2, v2, v1
-; GFX12-ISEL-NEXT: v_and_b32_e32 v1, 0xff00, v3
-; GFX12-ISEL-NEXT: v_or_b32_e32 v0, v0, v3
-; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v4, 16, v2
-; GFX12-ISEL-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX12-ISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v4
+; GFX12-ISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX12-ISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-ISEL-NEXT: v_or_b32_e32 v0, v0, v4
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_v4f32_v4i8:
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index 14094c50e2290..3cdfb9ba88585 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -1891,23 +1891,21 @@ define <2 x i8> @test_s_unsigned_v2f64_v2i8(<2 x double> inreg %f) {
; GFX9-LABEL: test_s_unsigned_v2f64_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_u32_f64_e32 v1, s[18:19]
; GFX9-NEXT: v_cvt_u32_f64_e32 v0, s[16:17]
-; GFX9-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX9-NEXT: v_cvt_u32_f64_e32 v1, s[18:19]
; GFX9-NEXT: v_min_u32_e32 v0, 0xff, v0
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX9-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: test_s_unsigned_v2f64_v2i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_u32_f64_e32 v0, s[2:3]
-; GFX11-NEXT: v_cvt_u32_f64_e32 v2, s[0:1]
-; GFX11-NEXT: v_min_u32_e32 v1, 0xff, v0
-; GFX11-NEXT: v_min_u32_e32 v0, 0xff, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v1
-; GFX11-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX11-NEXT: v_cvt_u32_f64_e32 v0, s[0:1]
+; GFX11-NEXT: v_cvt_u32_f64_e32 v1, s[2:3]
+; GFX11-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_lshl_or_b32 v0, v1, 8, v0
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-ISEL-LABEL: test_s_unsigned_v2f64_v2i8:
@@ -1917,12 +1915,11 @@ define <2 x i8> @test_s_unsigned_v2f64_v2i8(<2 x double> inreg %f) {
; GFX12-ISEL-NEXT: s_wait_samplecnt 0x0
; GFX12-ISEL-NEXT: s_wait_bvhcnt 0x0
; GFX12-ISEL-NEXT: s_wait_kmcnt 0x0
-; GFX12-ISEL-NEXT: v_cvt_u32_f64_e32 v0, s[2:3]
-; GFX12-ISEL-NEXT: v_cvt_u32_f64_e32 v2, s[0:1]
-; GFX12-ISEL-NEXT: v_min_u32_e32 v1, 0xff, v0
-; GFX12-ISEL-NEXT: v_min_u32_e32 v0, 0xff, v2
-; GFX12-ISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v1
-; GFX12-ISEL-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX12-ISEL-NEXT: v_cvt_u32_f64_e32 v0, s[0:1]
+; GFX12-ISEL-NEXT: v_cvt_u32_f64_e32 v1, s[2:3]
+; GFX12-ISEL-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-ISEL-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX12-ISEL-NEXT: v_lshl_or_b32 v0, v1, 8, v0
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_unsigned_v2f64_v2i8:
@@ -3280,14 +3277,13 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
; GFX9-NEXT: s_lshr_b32 s5, s17, 16
; GFX9-NEXT: s_movk_i32 s4, 0xff
-; GFX9-NEXT: v_cvt_u16_f16_e32 v3, s5
; GFX9-NEXT: v_cvt_u16_f16_e32 v2, s17
-; GFX9-NEXT: v_min_u32_sdwa v3, v3, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_cvt_u16_f16_e32 v3, s5
; GFX9-NEXT: v_min_u32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX9-NEXT: v_min_u32_sdwa v3, v3, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s16
; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3301,19 +3297,18 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v1, s1
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s2
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s1
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v1, s2
; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v3, s0
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v2, s1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3328,19 +3323,18 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s1
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s2
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s0
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3359,21 +3353,20 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v1, s1
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s1
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s2
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v1, s2
; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v3, s0
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v2, s1
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX12-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -3392,21 +3385,20 @@ define <4 x i8> @test_s_unsigned_v4f16_v4i8(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s2
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v2, v1, 8, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v3
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v4
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -5394,30 +5386,27 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_lshr_b32 s5, s18, 16
+; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s18
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
-; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s18
-; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: s_lshr_b32 s5, s19, 16
-; GFX9-NEXT: v_or_b32_e32 v8, v0, v1
-; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
+; GFX9-NEXT: v_lshl_or_b32 v8, v1, 8, v0
; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s19
+; GFX9-NEXT: v_cvt_u16_f16_e32 v1, s5
+; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_min_u32_sdwa v1, v1, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: s_lshr_b32 s5, s17, 16
-; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
-; GFX9-NEXT: v_cvt_u16_f16_e32 v2, s5
-; GFX9-NEXT: v_or_b32_e32 v6, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v6, v1, 8, v0
; GFX9-NEXT: v_cvt_u16_f16_e32 v0, s17
-; GFX9-NEXT: v_min_u32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; GFX9-NEXT: v_cvt_u16_f16_e32 v2, s5
; GFX9-NEXT: s_lshr_b32 s5, s16, 16
; GFX9-NEXT: v_min_u32_sdwa v0, v0, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX9-NEXT: v_min_u32_sdwa v2, v2, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_cvt_u16_f16_e32 v7, s5
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v6
-; GFX9-NEXT: v_or_b32_e32 v2, v0, v2
+; GFX9-NEXT: v_lshl_or_b32 v2, v2, 8, v0
; GFX9-NEXT: v_min_u32_sdwa v7, v7, s4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v4, v8, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -5437,37 +5426,34 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-FAKE16: ; %bb.0:
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s2, 16
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v2, s3
-; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v1, s2
-; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s4
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s2
+; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s3, 16
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v1, s4
+; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v4, s3
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v3, s2
-; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v5, s1
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v5, s2
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v2, s1
+; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v3, s4
; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v6, s1
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX11-FAKE16-NEXT: v_min_u32_e32 v7, 0xff, v2
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX11-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX11-FAKE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v8, v1, v0
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v8, v1, 8, v0
; GFX11-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v6, v5, 8, v4
; GFX11-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s0
-; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
+; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
@@ -5488,37 +5474,34 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s2, 16
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s3
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s2
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s4
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s3, 16
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s4
+; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, s3
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s2
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s1
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s2
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s1
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s4
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v6.l, s1
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v7, 0xff, v2
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX11-TRUE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v1, v0
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v8, v1, 8, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v6, v5, 8, v4
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, v5, v3
+; GFX11-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
@@ -5543,39 +5526,37 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-FAKE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-FAKE16-NEXT: s_wait_kmcnt 0x0
; GFX12-FAKE16-NEXT: s_lshr_b32 s4, s2, 16
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v2, s3
-; GFX12-FAKE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v1, s2
-; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s1, 16
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s2
+; GFX12-FAKE16-NEXT: s_lshr_b32 s2, s3, 16
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s4
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v1, s4
+; GFX12-FAKE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v4, s3
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v3, s2
-; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v5, s1
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v5, s2
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v2, s1
+; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v3, s4
; GFX12-FAKE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-FAKE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v6, s1
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX12-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX12-FAKE16-NEXT: v_min_u32_e32 v7, 0xff, v2
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX12-FAKE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX12-FAKE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v8, v1, v0
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX12-FAKE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v8, v1, 8, v0
; GFX12-FAKE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v6, v5, 8, v4
; GFX12-FAKE16-NEXT: v_cvt_u16_f16_e32 v0, s0
-; GFX12-FAKE16-NEXT: v_or_b32_e32 v2, v5, v3
+; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-FAKE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
@@ -5600,39 +5581,37 @@ define <8 x i8> @test_s_unsigned_v8f16_v8i8(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s2, 16
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s3
-; GFX12-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s2
-; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s3, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s4
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s4
+; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, s3
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s2
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s1
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v5.l, s2
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s4
; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s0, 16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v6.l, s1
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff, v5
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v7, 0xff, v2
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v4, 0xff, v4
; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 8, v4
; GFX12-TRUE16-NEXT: v_min_u32_e32 v5, 0xff, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v8, v1, v0
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v2, 0xff, v2
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v8, v1, 8, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v6
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v6, v7, v4
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v6, v5, 8, v4
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
-; GFX12-TRUE16-NEXT: v_or_b32_e32 v2, v5, v3
+; GFX12-TRUE16-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v8
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
@@ -6395,15 +6374,14 @@ define <4 x i8> @test_s_unsigned_v4f32_v4i8(<4 x float> inreg %f) {
; GFX9-LABEL: test_s_unsigned_v4f32_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cvt_u32_f32_e32 v3, s19
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, s18
+; GFX9-NEXT: v_cvt_u32_f32_e32 v3, s19
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, s17
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, s16
-; GFX9-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX9-NEXT: v_min_u32_e32 v2, 0xff, v2
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX9-NEXT: v_min_u32_e32 v3, 0xff, v3
; GFX9-NEXT: v_min_u32_e32 v1, 0xff, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX9-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -6416,14 +6394,13 @@ define <4 x i8> @test_s_unsigned_v4f32_v4i8(<4 x float> inreg %f) {
; GFX11-LABEL: test_s_unsigned_v4f32_v4i8:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_cvt_u32_f32_e32 v0, s3
-; GFX11-NEXT: v_cvt_u32_f32_e32 v1, s2
+; GFX11-NEXT: v_cvt_u32_f32_e32 v0, s2
+; GFX11-NEXT: v_cvt_u32_f32_e32 v1, s3
; GFX11-NEXT: v_cvt_u32_f32_e32 v2, s1
; GFX11-NEXT: v_min_u32_e32 v0, 0xff, v0
; GFX11-NEXT: v_min_u32_e32 v1, 0xff, v1
; GFX11-NEXT: v_min_u32_e32 v3, 0xff, v2
-; GFX11-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX11-NEXT: v_or_b32_e32 v2, v1, v0
+; GFX11-NEXT: v_lshl_or_b32 v2, v1, 8, v0
; GFX11-NEXT: v_cvt_u32_f32_e32 v0, s0
; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v3
; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v2
@@ -6449,23 +6426,23 @@ define <4 x i8> @test_s_unsigned_v4f32_v4i8(<4 x float> inreg %f) {
; GFX12-ISEL-NEXT: s_min_u32 s3, s3, 0xff
; GFX12-ISEL-NEXT: s_min_u32 s2, s2, 0xff
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_lshl_b32 s3, s3, 8
-; GFX12-ISEL-NEXT: s_min_u32 s1, s1, 0xff
+; GFX12-ISEL-NEXT: s_lshl_b32 s4, s3, 8
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_or_b32 s2, s2, s3
+; GFX12-ISEL-NEXT: s_or_b32 s4, s4, s2
+; GFX12-ISEL-NEXT: s_min_u32 s1, s1, 0xff
; GFX12-ISEL-NEXT: s_min_u32 s0, s0, 0xff
+; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT: s_lshl_b32 s1, s1, 8
+; GFX12-ISEL-NEXT: s_lshl_b32 s2, s4, 16
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_lshl_b32 s3, s2, 16
; GFX12-ISEL-NEXT: s_or_b32 s0, s0, s1
-; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-ISEL-NEXT: s_or_b32 s1, s1, s3
-; GFX12-ISEL-NEXT: s_lshr_b32 s3, s3, 24
+; GFX12-ISEL-NEXT: s_or_b32 s1, s1, s2
+; GFX12-ISEL-NEXT: s_lshr_b32 s2, s2, 24
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT: s_lshr_b32 s1, s1, 8
; GFX12-ISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-ISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
-; GFX12-ISEL-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX12-ISEL-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s2
; GFX12-ISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_unsigned_v4f32_v4i8:
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
index 00b18a86f17cf..1207bc62bbddf 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
@@ -802,9 +802,9 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX9-SDAG-NEXT: s_cmp_lg_u32 s9, s7
; GFX9-SDAG-NEXT: s_cselect_b32 s7, 1, 0
; GFX9-SDAG-NEXT: s_addk_i32 s8, 0xfc10
-; GFX9-SDAG-NEXT: s_lshl_b32 s9, s8, 12
; GFX9-SDAG-NEXT: s_or_b32 s7, s10, s7
-; GFX9-SDAG-NEXT: s_or_b32 s9, s6, s9
+; GFX9-SDAG-NEXT: s_lshl_b32 s9, s8, 12
+; GFX9-SDAG-NEXT: s_or_b32 s9, s9, s6
; GFX9-SDAG-NEXT: s_cmp_lt_i32 s8, 1
; GFX9-SDAG-NEXT: s_cselect_b32 s7, s7, s9
; GFX9-SDAG-NEXT: s_and_b32 s9, s7, 7
@@ -915,9 +915,9 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX950-SDAG-NEXT: s_cmp_lg_u32 s9, s7
; GFX950-SDAG-NEXT: s_cselect_b32 s7, 1, 0
; GFX950-SDAG-NEXT: s_addk_i32 s8, 0xfc10
-; GFX950-SDAG-NEXT: s_lshl_b32 s9, s8, 12
; GFX950-SDAG-NEXT: s_or_b32 s7, s10, s7
-; GFX950-SDAG-NEXT: s_or_b32 s9, s6, s9
+; GFX950-SDAG-NEXT: s_lshl_b32 s9, s8, 12
+; GFX950-SDAG-NEXT: s_or_b32 s9, s9, s6
; GFX950-SDAG-NEXT: s_cmp_lt_i32 s8, 1
; GFX950-SDAG-NEXT: s_cselect_b32 s7, s7, s9
; GFX950-SDAG-NEXT: s_and_b32 s9, s7, 7
@@ -1025,17 +1025,18 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_lshr_b32 s9, s5, s8
; GFX11-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s9, s8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s8, s5
; GFX11-SDAG-TRUE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-SDAG-TRUE16-NEXT: s_addk_i32 s3, 0xfc10
-; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s5, s9, s5
; GFX11-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s3, 12
-; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s8, s4, s8
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s8, s8, s4
+; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s5, s9, s5
; GFX11-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s3, 1
; GFX11-SDAG-TRUE16-NEXT: s_cselect_b32 s5, s5, s8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s8, s5, 7
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_cmp_gt_i32 s8, 5
; GFX11-SDAG-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX11-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s8, 3
@@ -1092,17 +1093,18 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_lshr_b32 s9, s5, s8
; GFX11-SDAG-FAKE16-NEXT: s_lshl_b32 s8, s9, s8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_cmp_lg_u32 s8, s5
; GFX11-SDAG-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-SDAG-FAKE16-NEXT: s_addk_i32 s3, 0xfc10
-; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s5, s9, s5
; GFX11-SDAG-FAKE16-NEXT: s_lshl_b32 s8, s3, 12
-; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s8, s4, s8
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s8, s8, s4
+; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s5, s9, s5
; GFX11-SDAG-FAKE16-NEXT: s_cmp_lt_i32 s3, 1
; GFX11-SDAG-FAKE16-NEXT: s_cselect_b32 s5, s5, s8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 s8, s5, 7
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_cmp_gt_i32 s8, 5
; GFX11-SDAG-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX11-SDAG-FAKE16-NEXT: s_cmp_eq_u32 s8, 3
@@ -1276,17 +1278,18 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s9, s5, s8
; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s9, s8
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s8, s5
; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX1250-SDAG-TRUE16-NEXT: s_addk_co_i32 s3, 0xfc10
-; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s5, s9, s5
; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s3, 12
-; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s8, s4, s8
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s8, s8, s4
+; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s5, s9, s5
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s3, 1
; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s5, s5, s8
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s8, s5, 7
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_gt_i32 s8, 5
; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s8, 3
@@ -1344,17 +1347,18 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_lshr_b32 s9, s5, s8
; GFX1250-SDAG-FAKE16-NEXT: s_lshl_b32 s8, s9, s8
-; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_lg_u32 s8, s5
; GFX1250-SDAG-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX1250-SDAG-FAKE16-NEXT: s_addk_co_i32 s3, 0xfc10
-; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s5, s9, s5
; GFX1250-SDAG-FAKE16-NEXT: s_lshl_b32 s8, s3, 12
-; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s8, s4, s8
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s8, s8, s4
+; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s5, s9, s5
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_lt_i32 s3, 1
; GFX1250-SDAG-FAKE16-NEXT: s_cselect_b32 s5, s5, s8
-; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_and_b32 s8, s5, 7
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_gt_i32 s8, 5
; GFX1250-SDAG-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_eq_u32 s8, 3
@@ -2534,9 +2538,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX9-SDAG-NEXT: s_cmp_lg_u32 s10, s8
; GFX9-SDAG-NEXT: s_cselect_b32 s8, 1, 0
; GFX9-SDAG-NEXT: s_addk_i32 s9, 0xfc10
-; GFX9-SDAG-NEXT: s_lshl_b32 s10, s9, 12
; GFX9-SDAG-NEXT: s_or_b32 s8, s11, s8
-; GFX9-SDAG-NEXT: s_or_b32 s10, s7, s10
+; GFX9-SDAG-NEXT: s_lshl_b32 s10, s9, 12
+; GFX9-SDAG-NEXT: s_or_b32 s10, s10, s7
; GFX9-SDAG-NEXT: s_cmp_lt_i32 s9, 1
; GFX9-SDAG-NEXT: s_cselect_b32 s8, s8, s10
; GFX9-SDAG-NEXT: s_and_b32 s10, s8, 7
@@ -2574,9 +2578,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX9-SDAG-NEXT: s_cmp_lg_u32 s9, s8
; GFX9-SDAG-NEXT: s_cselect_b32 s8, 1, 0
; GFX9-SDAG-NEXT: s_addk_i32 s10, 0xfc10
-; GFX9-SDAG-NEXT: s_lshl_b32 s9, s10, 12
; GFX9-SDAG-NEXT: s_or_b32 s8, s11, s8
-; GFX9-SDAG-NEXT: s_or_b32 s9, s7, s9
+; GFX9-SDAG-NEXT: s_lshl_b32 s9, s10, 12
+; GFX9-SDAG-NEXT: s_or_b32 s9, s9, s7
; GFX9-SDAG-NEXT: s_cmp_lt_i32 s10, 1
; GFX9-SDAG-NEXT: s_cselect_b32 s8, s8, s9
; GFX9-SDAG-NEXT: s_and_b32 s9, s8, 7
@@ -2731,9 +2735,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX950-SDAG-NEXT: s_cmp_lg_u32 s10, s8
; GFX950-SDAG-NEXT: s_cselect_b32 s8, 1, 0
; GFX950-SDAG-NEXT: s_addk_i32 s9, 0xfc10
-; GFX950-SDAG-NEXT: s_lshl_b32 s10, s9, 12
; GFX950-SDAG-NEXT: s_or_b32 s8, s11, s8
-; GFX950-SDAG-NEXT: s_or_b32 s10, s7, s10
+; GFX950-SDAG-NEXT: s_lshl_b32 s10, s9, 12
+; GFX950-SDAG-NEXT: s_or_b32 s10, s10, s7
; GFX950-SDAG-NEXT: s_cmp_lt_i32 s9, 1
; GFX950-SDAG-NEXT: s_cselect_b32 s8, s8, s10
; GFX950-SDAG-NEXT: s_and_b32 s10, s8, 7
@@ -2771,9 +2775,9 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX950-SDAG-NEXT: s_cmp_lg_u32 s9, s8
; GFX950-SDAG-NEXT: s_cselect_b32 s8, 1, 0
; GFX950-SDAG-NEXT: s_addk_i32 s10, 0xfc10
-; GFX950-SDAG-NEXT: s_lshl_b32 s9, s10, 12
; GFX950-SDAG-NEXT: s_or_b32 s8, s11, s8
-; GFX950-SDAG-NEXT: s_or_b32 s9, s7, s9
+; GFX950-SDAG-NEXT: s_lshl_b32 s9, s10, 12
+; GFX950-SDAG-NEXT: s_or_b32 s9, s9, s7
; GFX950-SDAG-NEXT: s_cmp_lt_i32 s10, 1
; GFX950-SDAG-NEXT: s_cselect_b32 s8, s8, s9
; GFX950-SDAG-NEXT: s_and_b32 s9, s8, 7
@@ -2924,17 +2928,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_lshr_b32 s9, s5, s8
; GFX11-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s9, s8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s8, s5
; GFX11-SDAG-TRUE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-SDAG-TRUE16-NEXT: s_addk_i32 s3, 0xfc10
-; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s5, s9, s5
; GFX11-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s3, 12
-; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s8, s4, s8
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s8, s8, s4
+; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s5, s9, s5
; GFX11-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s3, 1
; GFX11-SDAG-TRUE16-NEXT: s_cselect_b32 s5, s5, s8
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s8, s5, 7
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_cmp_gt_i32 s8, 5
; GFX11-SDAG-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX11-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s8, 3
@@ -2972,17 +2977,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_lshr_b32 s12, s10, s11
; GFX11-SDAG-TRUE16-NEXT: s_lshl_b32 s11, s12, s11
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s11, s10
; GFX11-SDAG-TRUE16-NEXT: s_cselect_b32 s3, 1, 0
; GFX11-SDAG-TRUE16-NEXT: s_addk_i32 s5, 0xfc10
-; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s3, s12, s3
; GFX11-SDAG-TRUE16-NEXT: s_lshl_b32 s10, s5, 12
-; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s10, s9, s10
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s10, s10, s9
+; GFX11-SDAG-TRUE16-NEXT: s_or_b32 s3, s12, s3
; GFX11-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s5, 1
; GFX11-SDAG-TRUE16-NEXT: s_cselect_b32 s3, s3, s10
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s10, s3, 7
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: s_cmp_gt_i32 s10, 5
; GFX11-SDAG-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX11-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s10, 3
@@ -3040,17 +3046,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_lshr_b32 s9, s5, s8
; GFX11-SDAG-FAKE16-NEXT: s_lshl_b32 s8, s9, s8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_cmp_lg_u32 s8, s5
; GFX11-SDAG-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-SDAG-FAKE16-NEXT: s_addk_i32 s3, 0xfc10
-; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s5, s9, s5
; GFX11-SDAG-FAKE16-NEXT: s_lshl_b32 s8, s3, 12
-; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s8, s4, s8
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s8, s8, s4
+; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s5, s9, s5
; GFX11-SDAG-FAKE16-NEXT: s_cmp_lt_i32 s3, 1
; GFX11-SDAG-FAKE16-NEXT: s_cselect_b32 s5, s5, s8
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 s8, s5, 7
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_cmp_gt_i32 s8, 5
; GFX11-SDAG-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX11-SDAG-FAKE16-NEXT: s_cmp_eq_u32 s8, 3
@@ -3088,17 +3095,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_lshr_b32 s12, s10, s11
; GFX11-SDAG-FAKE16-NEXT: s_lshl_b32 s11, s12, s11
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_cmp_lg_u32 s11, s10
; GFX11-SDAG-FAKE16-NEXT: s_cselect_b32 s3, 1, 0
; GFX11-SDAG-FAKE16-NEXT: s_addk_i32 s5, 0xfc10
-; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s3, s12, s3
; GFX11-SDAG-FAKE16-NEXT: s_lshl_b32 s10, s5, 12
-; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s10, s9, s10
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s10, s10, s9
+; GFX11-SDAG-FAKE16-NEXT: s_or_b32 s3, s12, s3
; GFX11-SDAG-FAKE16-NEXT: s_cmp_lt_i32 s5, 1
; GFX11-SDAG-FAKE16-NEXT: s_cselect_b32 s3, s3, s10
-; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_and_b32 s10, s3, 7
+; GFX11-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-FAKE16-NEXT: s_cmp_gt_i32 s10, 5
; GFX11-SDAG-FAKE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX11-SDAG-FAKE16-NEXT: s_cmp_eq_u32 s10, 3
@@ -3367,17 +3375,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s9, s5, s8
; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s9, s8
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s8, s5
; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX1250-SDAG-TRUE16-NEXT: s_addk_co_i32 s3, 0xfc10
-; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s5, s9, s5
; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s8, s3, 12
-; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s8, s4, s8
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s8, s8, s4
+; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s5, s9, s5
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s3, 1
; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s5, s5, s8
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s8, s5, 7
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_gt_i32 s8, 5
; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s8, 3
@@ -3415,17 +3424,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_lshr_b32 s12, s10, s11
; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s11, s12, s11
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lg_u32 s11, s10
; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s3, 1, 0
; GFX1250-SDAG-TRUE16-NEXT: s_addk_co_i32 s5, 0xfc10
-; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s3, s12, s3
; GFX1250-SDAG-TRUE16-NEXT: s_lshl_b32 s10, s5, 12
-; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s10, s9, s10
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s10, s10, s9
+; GFX1250-SDAG-TRUE16-NEXT: s_or_b32 s3, s12, s3
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_lt_i32 s5, 1
; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s3, s3, s10
-; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_and_b32 s10, s3, 7
+; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_gt_i32 s10, 5
; GFX1250-SDAG-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1250-SDAG-TRUE16-NEXT: s_cmp_eq_u32 s10, 3
@@ -3484,17 +3494,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_lshr_b32 s9, s5, s8
; GFX1250-SDAG-FAKE16-NEXT: s_lshl_b32 s8, s9, s8
-; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_lg_u32 s8, s5
; GFX1250-SDAG-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
; GFX1250-SDAG-FAKE16-NEXT: s_addk_co_i32 s3, 0xfc10
-; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s5, s9, s5
; GFX1250-SDAG-FAKE16-NEXT: s_lshl_b32 s8, s3, 12
-; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s8, s4, s8
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s8, s8, s4
+; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s5, s9, s5
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_lt_i32 s3, 1
; GFX1250-SDAG-FAKE16-NEXT: s_cselect_b32 s5, s5, s8
-; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_and_b32 s8, s5, 7
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_gt_i32 s8, 5
; GFX1250-SDAG-FAKE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_eq_u32 s8, 3
@@ -3532,17 +3543,18 @@ define amdgpu_kernel void @fptrunc_v2f64_to_v2f16(
; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_lshr_b32 s12, s10, s11
; GFX1250-SDAG-FAKE16-NEXT: s_lshl_b32 s11, s12, s11
-; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_lg_u32 s11, s10
; GFX1250-SDAG-FAKE16-NEXT: s_cselect_b32 s3, 1, 0
; GFX1250-SDAG-FAKE16-NEXT: s_addk_co_i32 s5, 0xfc10
-; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s3, s12, s3
; GFX1250-SDAG-FAKE16-NEXT: s_lshl_b32 s10, s5, 12
-; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s10, s9, s10
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s10, s10, s9
+; GFX1250-SDAG-FAKE16-NEXT: s_or_b32 s3, s12, s3
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_lt_i32 s5, 1
; GFX1250-SDAG-FAKE16-NEXT: s_cselect_b32 s3, s3, s10
-; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_and_b32 s10, s3, 7
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_gt_i32 s10, 5
; GFX1250-SDAG-FAKE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1250-SDAG-FAKE16-NEXT: s_cmp_eq_u32 s10, 3
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
index 3e344af903a1e..094dcb353d1a3 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
@@ -351,9 +351,9 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; GFX10-SDAG-NEXT: s_cmp_lg_u32 s6, s5
; GFX10-SDAG-NEXT: s_cselect_b32 s5, 1, 0
; GFX10-SDAG-NEXT: s_addk_i32 s2, 0xfc10
-; GFX10-SDAG-NEXT: s_or_b32 s5, s7, s5
; GFX10-SDAG-NEXT: s_lshl_b32 s6, s2, 12
-; GFX10-SDAG-NEXT: s_or_b32 s6, s4, s6
+; GFX10-SDAG-NEXT: s_or_b32 s6, s6, s4
+; GFX10-SDAG-NEXT: s_or_b32 s5, s7, s5
; GFX10-SDAG-NEXT: s_cmp_lt_i32 s2, 1
; GFX10-SDAG-NEXT: s_cselect_b32 s5, s5, s6
; GFX10-SDAG-NEXT: s_and_b32 s6, s5, 7
@@ -454,17 +454,18 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: s_lshr_b32 s7, s5, s6
; GFX11-SDAG-NEXT: s_lshl_b32 s6, s7, s6
-; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: s_cmp_lg_u32 s6, s5
; GFX11-SDAG-NEXT: s_cselect_b32 s5, 1, 0
; GFX11-SDAG-NEXT: s_addk_i32 s2, 0xfc10
-; GFX11-SDAG-NEXT: s_or_b32 s5, s7, s5
; GFX11-SDAG-NEXT: s_lshl_b32 s6, s2, 12
-; GFX11-SDAG-NEXT: s_or_b32 s6, s4, s6
+; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-NEXT: s_or_b32 s6, s6, s4
+; GFX11-SDAG-NEXT: s_or_b32 s5, s7, s5
; GFX11-SDAG-NEXT: s_cmp_lt_i32 s2, 1
; GFX11-SDAG-NEXT: s_cselect_b32 s5, s5, s6
-; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: s_and_b32 s6, s5, 7
+; GFX11-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-SDAG-NEXT: s_cmp_gt_i32 s6, 5
; GFX11-SDAG-NEXT: s_cselect_b32 s7, 1, 0
; GFX11-SDAG-NEXT: s_cmp_eq_u32 s6, 3
diff --git a/llvm/test/CodeGen/AMDGPU/fshl.ll b/llvm/test/CodeGen/AMDGPU/fshl.ll
index 1233c1fe12f72..fae4897487702 100644
--- a/llvm/test/CodeGen/AMDGPU/fshl.ll
+++ b/llvm/test/CodeGen/AMDGPU/fshl.ll
@@ -905,8 +905,9 @@ define amdgpu_kernel void @orxor2or1(ptr addrspace(1) %in, i32 %a, i32 %b) {
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s4, s2, 7
-; GFX9-NEXT: s_or_b32 s4, s3, s4
-; GFX9-NEXT: s_cselect_b32 s2, s3, s2
+; GFX9-NEXT: s_or_b32 s4, s4, s3
+; GFX9-NEXT: s_cmp_eq_u32 s4, 0
+; GFX9-NEXT: s_cselect_b32 s2, s2, s3
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
@@ -931,8 +932,9 @@ define amdgpu_kernel void @orxor2or1(ptr addrspace(1) %in, i32 %a, i32 %b) {
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshl_b32 s4, s2, 7
-; GFX10-NEXT: s_or_b32 s4, s3, s4
-; GFX10-NEXT: s_cselect_b32 s2, s3, s2
+; GFX10-NEXT: s_or_b32 s4, s4, s3
+; GFX10-NEXT: s_cmp_eq_u32 s4, 0
+; GFX10-NEXT: s_cselect_b32 s2, s2, s3
; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm
@@ -942,9 +944,11 @@ define amdgpu_kernel void @orxor2or1(ptr addrspace(1) %in, i32 %a, i32 %b) {
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_lshl_b32 s4, s2, 7
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s4, s3, s4
-; GFX11-NEXT: s_cselect_b32 s2, s3, s2
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s4, s4, s3
+; GFX11-NEXT: s_cmp_eq_u32 s4, 0
+; GFX11-NEXT: s_cselect_b32 s2, s2, s3
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll b/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
index 50e7a3a322e09..44ce73f5b3c65 100644
--- a/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
+++ b/llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll
@@ -52,11 +52,11 @@ define amdgpu_kernel void @v5i8_arg(<5 x i8> %in) nounwind {
; GCN-NEXT: s_and_b32 s2, s0, 0xff
; GCN-NEXT: v_mov_b32_e32 v1, s0
; GCN-NEXT: s_lshr_b32 s3, s0, 24
+; GCN-NEXT: s_bfe_u32 s0, s0, 0x80010
; GCN-NEXT: v_perm_b32 v0, s2, v1, v0
; GCN-NEXT: s_lshl_b32 s2, s3, 8
-; GCN-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GCN-NEXT: s_or_b32 s0, s0, s2
-; GCN-NEXT: s_lshl_b32 s0, s0, 16
+; GCN-NEXT: s_or_b32 s2, s2, s0
+; GCN-NEXT: s_lshl_b32 s0, s2, 16
; GCN-NEXT: v_or_b32_e32 v4, s0, v0
; GCN-NEXT: v_mov_b32_e32 v0, 4
; GCN-NEXT: v_mov_b32_e32 v1, 0
@@ -79,11 +79,11 @@ define amdgpu_kernel void @v6i8_arg(<6 x i8> %in) nounwind {
; GCN-NEXT: s_and_b32 s2, s0, 0xff
; GCN-NEXT: v_mov_b32_e32 v1, s0
; GCN-NEXT: s_lshr_b32 s3, s0, 24
+; GCN-NEXT: s_bfe_u32 s0, s0, 0x80010
; GCN-NEXT: v_perm_b32 v1, s2, v1, v0
; GCN-NEXT: s_lshl_b32 s2, s3, 8
-; GCN-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GCN-NEXT: s_or_b32 s0, s0, s2
-; GCN-NEXT: s_lshl_b32 s0, s0, 16
+; GCN-NEXT: s_or_b32 s2, s2, s0
+; GCN-NEXT: s_lshl_b32 s0, s2, 16
; GCN-NEXT: v_or_b32_e32 v4, s0, v1
; GCN-NEXT: s_and_b32 s0, s1, 0xff
; GCN-NEXT: v_mov_b32_e32 v1, s1
@@ -387,9 +387,9 @@ define amdgpu_kernel void @v2i15_arg(ptr addrspace(1) nocapture %out, <2 x i15>
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_and_b32 s3, s2, 0x7fff
; GCN-NEXT: s_bfe_u32 s2, s2, 0x100010
-; GCN-NEXT: s_lshl_b32 s2, s2, 15
-; GCN-NEXT: s_or_b32 s2, s3, s2
-; GCN-NEXT: s_andn2_b32 s2, s2, -2.0
+; GCN-NEXT: s_lshl_b32 s4, s2, 15
+; GCN-NEXT: s_or_b32 s4, s4, s3
+; GCN-NEXT: s_and_b32 s2, s4, 0x3fffffff
; GCN-NEXT: v_mov_b32_e32 v1, s2
; GCN-NEXT: global_store_dword v0, v1, s[0:1]
; GCN-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/lshl_or-expand.mir b/llvm/test/CodeGen/AMDGPU/lshl_or-expand.mir
new file mode 100644
index 0000000000000..c053c142e81a7
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/lshl_or-expand.mir
@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=postrapseudos -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+
+---
+name: lshl_or_expand
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0, $sgpr1, $sgpr2
+ ; GCN-LABEL: name: lshl_or_expand
+ ; GCN: liveins: $sgpr0, $sgpr1, $sgpr2
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: $sgpr3 = S_LSHL_B32 killed $sgpr0, killed $sgpr1, implicit-def $scc
+ ; GCN-NEXT: $sgpr3 = S_OR_B32 $sgpr3, killed $sgpr2, implicit-def $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit $sgpr3
+ renamable $sgpr3 = S_LSHL_OR_B32 killed $sgpr0, killed $sgpr1, killed $sgpr2, implicit-def $scc
+ S_ENDPGM 0, implicit $sgpr3
+...
+
+---
+name: lshl_or_expand_pack
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; GCN-LABEL: name: lshl_or_expand_pack
+ ; GCN: liveins: $sgpr0
+ ; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: $sgpr3 = S_LSHL_B32 $sgpr0, 16, implicit-def $scc
+ ; GCN-NEXT: $sgpr3 = S_OR_B32 $sgpr3, $sgpr0, implicit-def $scc
+ ; GCN-NEXT: S_ENDPGM 0, implicit $sgpr3
+ renamable $sgpr3 = S_LSHL_OR_B32 killed $sgpr0, 16, $sgpr0, implicit-def $scc
+ S_ENDPGM 0, implicit $sgpr3
+...
diff --git a/llvm/test/CodeGen/AMDGPU/lshl_or-promote.mir b/llvm/test/CodeGen/AMDGPU/lshl_or-promote.mir
new file mode 100644
index 0000000000000..81f82861229f5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/lshl_or-promote.mir
@@ -0,0 +1,24 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+
+---
+name: lshl_or_promote
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; GCN-LABEL: name: lshl_or_promote
+ ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[DEF2:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GCN-NEXT: [[V_CVT_U32_F32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_U32_F32_e64 0, [[DEF]], 0, 0, implicit $mode, implicit $exec
+ ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF2]]
+ ; GCN-NEXT: [[V_LSHL_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_OR_B32_e64 [[V_CVT_U32_F32_e64_]], [[DEF1]], [[COPY]], implicit $exec
+ ; GCN-NEXT: S_ENDPGM 0, implicit [[V_LSHL_OR_B32_e64_]]
+ %0:vgpr_32 = IMPLICIT_DEF
+ %1:sreg_32 = IMPLICIT_DEF
+ %2:sreg_32 = IMPLICIT_DEF
+ %3:vgpr_32 = V_CVT_U32_F32_e64 0, %0:vgpr_32, 0, 0, implicit $mode, implicit $exec
+ %4:sreg_32 = COPY %3:vgpr_32
+ %5:sreg_32 = S_LSHL_OR_B32 %4:sreg_32, %1:sreg_32, %2:sreg_32, implicit-def $scc
+ S_ENDPGM 0, implicit %5:sreg_32
+...
diff --git a/llvm/test/CodeGen/AMDGPU/lshl_or.ll b/llvm/test/CodeGen/AMDGPU/lshl_or.ll
new file mode 100644
index 0000000000000..6c9a41591e099
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/lshl_or.ll
@@ -0,0 +1,171 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s
+
+declare i32 @llvm.amdgcn.workitem.id.x()
+
+define amdgpu_kernel void @uniform_lshl_or(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
+; GFX8-LABEL: uniform_lshl_or:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_lshl_b32 s0, s0, s1
+; GFX8-NEXT: s_or_b32 s0, s0, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX9-LABEL: uniform_lshl_or:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b32 s3, s0, s1
+; GFX9-NEXT: s_or_b32 s3, s3, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
+; GFX9-NEXT: s_endpgm
+;
+; GFX11-LABEL: uniform_lshl_or:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshl_b32 s3, s0, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s3, s3, s2
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: global_store_b32 v0, v1, s[4:5]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: uniform_lshl_or:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c
+; GFX12-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_lshl_b32 s3, s0, s1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_or_b32 s3, s3, s2
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: global_store_b32 v0, v1, s[4:5]
+; GFX12-NEXT: s_endpgm
+ %shl = shl i32 %a, %b
+ %or = or i32 %shl, %c
+ store i32 %or, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @uniform_lshl_or_pack(ptr addrspace(1) %out, i32 %x) {
+; GFX8-LABEL: uniform_lshl_or_pack:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_lshl_b32 s3, s2, 16
+; GFX8-NEXT: s_or_b32 s2, s3, s2
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX9-LABEL: uniform_lshl_or_pack:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: s_lshl_b32 s3, s2, 16
+; GFX9-NEXT: s_or_b32 s3, s3, s2
+; GFX9-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-NEXT: s_endpgm
+;
+; GFX11-LABEL: uniform_lshl_or_pack:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_lshl_b32 s3, s2, 16
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s3, s3, s2
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: uniform_lshl_or_pack:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_lshl_b32 s3, s2, 16
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: s_or_b32 s3, s3, s2
+; GFX12-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
+; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: s_endpgm
+ %shl = shl i32 %x, 16
+ %or = or i32 %shl, %x
+ store i32 %or, ptr addrspace(1) %out
+ ret void
+}
+
+define amdgpu_kernel void @divergent_lshl_or(ptr addrspace(1) %out) {
+; GFX8-LABEL: divergent_lshl_or:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX8-NEXT: v_lshlrev_b32_e32 v1, 3, v0
+; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX8-NEXT: v_or_b32_e32 v2, 7, v1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0
+; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX9-LABEL: divergent_lshl_or:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX9-NEXT: v_lshl_or_b32 v1, v0, 3, 7
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-NEXT: s_endpgm
+;
+; GFX11-LABEL: divergent_lshl_or:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_lshl_or_b32 v1, v0, 3, 7
+; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
+;
+; GFX12-LABEL: divergent_lshl_or:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_lshl_or_b32 v1, v0, 3, 7
+; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX12-NEXT: s_endpgm
+ %tid = call i32 @llvm.amdgcn.workitem.id.x()
+ %shl = shl i32 %tid, 3
+ %or = or i32 %shl, 7
+ %gep = getelementptr i32, ptr addrspace(1) %out, i32 %tid
+ store i32 %or, ptr addrspace(1) %gep
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll
index 6ebb6aaa4520f..4f907c52340d7 100644
--- a/llvm/test/CodeGen/AMDGPU/min.ll
+++ b/llvm/test/CodeGen/AMDGPU/min.ll
@@ -738,24 +738,24 @@ define amdgpu_kernel void @s_test_imin_sle_v4i8(ptr addrspace(1) %out, [8 x i32]
; GFX9-NEXT: s_sext_i32_i16 s7, s3
; GFX9-NEXT: s_ashr_i32 s7, s7, 8
; GFX9-NEXT: s_ashr_i32 s5, s5, 8
-; GFX9-NEXT: s_ashr_i32 s4, s2, 24
-; GFX9-NEXT: s_ashr_i32 s6, s3, 24
; GFX9-NEXT: s_min_i32 s5, s5, s7
; GFX9-NEXT: s_sext_i32_i8 s7, s3
; GFX9-NEXT: s_sext_i32_i8 s8, s2
+; GFX9-NEXT: s_min_i32 s7, s8, s7
+; GFX9-NEXT: s_ashr_i32 s4, s2, 24
+; GFX9-NEXT: s_ashr_i32 s6, s3, 24
+; GFX9-NEXT: s_and_b32 s7, s7, 0xff
+; GFX9-NEXT: s_lshl_b32 s8, s5, 8
+; GFX9-NEXT: s_or_b32 s8, s8, s7
; GFX9-NEXT: s_bfe_i32 s3, s3, 0x80010
; GFX9-NEXT: s_bfe_i32 s2, s2, 0x80010
-; GFX9-NEXT: s_min_i32 s7, s8, s7
-; GFX9-NEXT: s_min_i32 s4, s4, s6
; GFX9-NEXT: s_min_i32 s2, s2, s3
-; GFX9-NEXT: s_lshl_b32 s5, s5, 8
-; GFX9-NEXT: s_and_b32 s7, s7, 0xff
-; GFX9-NEXT: s_lshl_b32 s4, s4, 8
+; GFX9-NEXT: s_and_b32 s5, s8, 0xffff
+; GFX9-NEXT: s_min_i32 s4, s4, s6
; GFX9-NEXT: s_and_b32 s2, s2, 0xff
-; GFX9-NEXT: s_or_b32 s5, s7, s5
-; GFX9-NEXT: s_or_b32 s2, s2, s4
-; GFX9-NEXT: s_and_b32 s5, s5, 0xffff
-; GFX9-NEXT: s_lshl_b32 s2, s2, 16
+; GFX9-NEXT: s_lshl_b32 s3, s4, 8
+; GFX9-NEXT: s_or_b32 s3, s3, s2
+; GFX9-NEXT: s_lshl_b32 s2, s3, 16
; GFX9-NEXT: s_or_b32 s2, s5, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
@@ -780,18 +780,18 @@ define amdgpu_kernel void @s_test_imin_sle_v4i8(ptr addrspace(1) %out, [8 x i32]
; GFX10-NEXT: s_ashr_i32 s7, s7, 8
; GFX10-NEXT: s_ashr_i32 s5, s5, 8
; GFX10-NEXT: s_min_i32 s8, s9, s8
-; GFX10-NEXT: s_min_i32 s4, s4, s6
; GFX10-NEXT: s_min_i32 s2, s2, s3
; GFX10-NEXT: s_min_i32 s3, s5, s7
+; GFX10-NEXT: s_min_i32 s4, s4, s6
; GFX10-NEXT: s_and_b32 s5, s8, 0xff
-; GFX10-NEXT: s_lshl_b32 s4, s4, 8
-; GFX10-NEXT: s_lshl_b32 s3, s3, 8
; GFX10-NEXT: s_and_b32 s2, s2, 0xff
-; GFX10-NEXT: s_or_b32 s3, s5, s3
-; GFX10-NEXT: s_or_b32 s2, s2, s4
-; GFX10-NEXT: s_and_b32 s3, s3, 0xffff
-; GFX10-NEXT: s_lshl_b32 s2, s2, 16
-; GFX10-NEXT: s_or_b32 s2, s3, s2
+; GFX10-NEXT: s_lshl_b32 s6, s3, 8
+; GFX10-NEXT: s_or_b32 s6, s6, s5
+; GFX10-NEXT: s_lshl_b32 s3, s4, 8
+; GFX10-NEXT: s_or_b32 s3, s3, s2
+; GFX10-NEXT: s_and_b32 s2, s6, 0xffff
+; GFX10-NEXT: s_lshl_b32 s3, s3, 16
+; GFX10-NEXT: s_or_b32 s2, s2, s3
; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm
@@ -815,19 +815,20 @@ define amdgpu_kernel void @s_test_imin_sle_v4i8(ptr addrspace(1) %out, [8 x i32]
; GFX11-NEXT: s_ashr_i32 s7, s7, 8
; GFX11-NEXT: s_ashr_i32 s5, s5, 8
; GFX11-NEXT: s_min_i32 s8, s9, s8
-; GFX11-NEXT: s_min_i32 s4, s4, s6
; GFX11-NEXT: s_min_i32 s2, s2, s3
; GFX11-NEXT: s_min_i32 s3, s5, s7
+; GFX11-NEXT: s_min_i32 s4, s4, s6
; GFX11-NEXT: s_and_b32 s5, s8, 0xff
-; GFX11-NEXT: s_lshl_b32 s4, s4, 8
-; GFX11-NEXT: s_lshl_b32 s3, s3, 8
; GFX11-NEXT: s_and_b32 s2, s2, 0xff
-; GFX11-NEXT: s_or_b32 s3, s5, s3
-; GFX11-NEXT: s_or_b32 s2, s2, s4
-; GFX11-NEXT: s_and_b32 s3, s3, 0xffff
-; GFX11-NEXT: s_lshl_b32 s2, s2, 16
+; GFX11-NEXT: s_lshl_b32 s6, s3, 8
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: s_or_b32 s6, s6, s5
+; GFX11-NEXT: s_lshl_b32 s3, s4, 8
+; GFX11-NEXT: s_or_b32 s3, s3, s2
+; GFX11-NEXT: s_and_b32 s2, s6, 0xffff
+; GFX11-NEXT: s_lshl_b32 s3, s3, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s2, s3, s2
+; GFX11-NEXT: s_or_b32 s2, s2, s3
; GFX11-NEXT: v_mov_b32_e32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
@@ -852,19 +853,20 @@ define amdgpu_kernel void @s_test_imin_sle_v4i8(ptr addrspace(1) %out, [8 x i32]
; GFX1250-NEXT: s_ashr_i32 s7, s7, 8
; GFX1250-NEXT: s_ashr_i32 s5, s5, 8
; GFX1250-NEXT: s_min_i32 s8, s9, s8
-; GFX1250-NEXT: s_min_i32 s4, s4, s6
; GFX1250-NEXT: s_min_i32 s2, s2, s3
; GFX1250-NEXT: s_min_i32 s3, s5, s7
+; GFX1250-NEXT: s_min_i32 s4, s4, s6
; GFX1250-NEXT: s_and_b32 s5, s8, 0xff
-; GFX1250-NEXT: s_lshl_b32 s4, s4, 8
-; GFX1250-NEXT: s_lshl_b32 s3, s3, 8
; GFX1250-NEXT: s_and_b32 s2, s2, 0xff
-; GFX1250-NEXT: s_or_b32 s3, s5, s3
-; GFX1250-NEXT: s_or_b32 s2, s2, s4
-; GFX1250-NEXT: s_and_b32 s3, s3, 0xffff
-; GFX1250-NEXT: s_lshl_b32 s2, s2, 16
+; GFX1250-NEXT: s_lshl_b32 s6, s3, 8
+; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1250-NEXT: s_or_b32 s6, s6, s5
+; GFX1250-NEXT: s_lshl_b32 s3, s4, 8
+; GFX1250-NEXT: s_or_b32 s3, s3, s2
+; GFX1250-NEXT: s_and_b32 s2, s6, 0xffff
+; GFX1250-NEXT: s_lshl_b32 s3, s3, 16
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: s_or_b32 s2, s3, s2
+; GFX1250-NEXT: s_or_b32 s2, s2, s3
; GFX1250-NEXT: v_mov_b32_e32 v1, s2
; GFX1250-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX1250-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
index 30ad3be46053c..30a9d9f7422aa 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-ctlz-cttz.ll
@@ -11,33 +11,26 @@ define amdgpu_kernel void @ctlz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_ubyte v0, v1, s[2:3] offset:5
-; GFX9-NEXT: global_load_ubyte v2, v1, s[2:3] offset:6
-; GFX9-NEXT: global_load_ubyte v3, v1, s[2:3] offset:7
-; GFX9-NEXT: global_load_ubyte v4, v1, s[2:3] offset:1
-; GFX9-NEXT: global_load_ubyte v5, v1, s[2:3] offset:3
-; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
-; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
-; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX9-NEXT: s_waitcnt vmcnt(7)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX9-NEXT: s_waitcnt vmcnt(5)
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX9-NEXT: global_load_ubyte v0, v1, s[2:3] offset:4
+; GFX9-NEXT: global_load_ubyte v2, v1, s[2:3] offset:5
+; GFX9-NEXT: global_load_ubyte v3, v1, s[2:3] offset:6
+; GFX9-NEXT: global_load_ubyte v4, v1, s[2:3] offset:7
+; GFX9-NEXT: global_load_ubyte v5, v1, s[2:3]
+; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:1
+; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
+; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:3
+; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 8, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v6, 8, v5
+; GFX9-NEXT: v_ffbh_u32_e32 v0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX9-NEXT: v_or_b32_e32 v2, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v4, v8, 8, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v3
; GFX9-NEXT: v_ffbh_u32_e32 v2, v2
-; GFX9-NEXT: v_ffbh_u32_e32 v0, v0
; GFX9-NEXT: v_add_u32_e64 v2, v2, 32 clamp
; GFX9-NEXT: v_min_u32_e32 v0, v2, v0
; GFX9-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
@@ -52,26 +45,21 @@ define amdgpu_kernel void @ctlz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX10-NEXT: global_load_ubyte v0, v1, s[2:3] offset:5
; GFX10-NEXT: global_load_ubyte v2, v1, s[2:3] offset:6
; GFX10-NEXT: global_load_ubyte v3, v1, s[2:3] offset:7
-; GFX10-NEXT: global_load_ubyte v4, v1, s[2:3] offset:1
-; GFX10-NEXT: global_load_ubyte v5, v1, s[2:3] offset:3
-; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3]
-; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
+; GFX10-NEXT: global_load_ubyte v4, v1, s[2:3]
+; GFX10-NEXT: global_load_ubyte v5, v1, s[2:3] offset:1
+; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3] offset:2
+; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3] offset:3
; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:4
-; GFX10-NEXT: s_waitcnt vmcnt(7)
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(5)
-; GFX10-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX10-NEXT: s_waitcnt vmcnt(4)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX10-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX10-NEXT: s_waitcnt vmcnt(3)
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX10-NEXT: v_lshl_or_b32 v4, v5, 8, v4
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: v_lshl_or_b32 v5, v7, 8, v6
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v8
-; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX10-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v8
+; GFX10-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX10-NEXT: v_ffbh_u32_e32 v2, v3
; GFX10-NEXT: v_ffbh_u32_e32 v0, v0
; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, 32 clamp
@@ -90,33 +78,26 @@ define amdgpu_kernel void @ctlz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_ubyte v0, v1, s[2:3] offset:5
-; GFX9-NEXT: global_load_ubyte v2, v1, s[2:3] offset:6
-; GFX9-NEXT: global_load_ubyte v3, v1, s[2:3] offset:7
-; GFX9-NEXT: global_load_ubyte v4, v1, s[2:3] offset:1
-; GFX9-NEXT: global_load_ubyte v5, v1, s[2:3] offset:3
-; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
-; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
-; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX9-NEXT: s_waitcnt vmcnt(7)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX9-NEXT: s_waitcnt vmcnt(5)
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX9-NEXT: global_load_ubyte v0, v1, s[2:3] offset:4
+; GFX9-NEXT: global_load_ubyte v2, v1, s[2:3] offset:5
+; GFX9-NEXT: global_load_ubyte v3, v1, s[2:3] offset:6
+; GFX9-NEXT: global_load_ubyte v4, v1, s[2:3] offset:7
+; GFX9-NEXT: global_load_ubyte v5, v1, s[2:3]
+; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:1
+; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
+; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:3
+; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 8, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX9-NEXT: v_lshl_or_b32 v3, v6, 8, v5
+; GFX9-NEXT: v_ffbh_u32_e32 v0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX9-NEXT: v_or_b32_e32 v2, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v4, v8, 8, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v3
; GFX9-NEXT: v_ffbh_u32_e32 v2, v2
-; GFX9-NEXT: v_ffbh_u32_e32 v0, v0
; GFX9-NEXT: v_add_u32_e64 v2, v2, 32 clamp
; GFX9-NEXT: v_min_u32_e32 v0, v2, v0
; GFX9-NEXT: v_min_u32_e32 v0, 64, v0
@@ -132,26 +113,21 @@ define amdgpu_kernel void @ctlz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX10-NEXT: global_load_ubyte v0, v1, s[2:3] offset:5
; GFX10-NEXT: global_load_ubyte v2, v1, s[2:3] offset:6
; GFX10-NEXT: global_load_ubyte v3, v1, s[2:3] offset:7
-; GFX10-NEXT: global_load_ubyte v4, v1, s[2:3] offset:1
-; GFX10-NEXT: global_load_ubyte v5, v1, s[2:3] offset:3
-; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3]
-; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
+; GFX10-NEXT: global_load_ubyte v4, v1, s[2:3]
+; GFX10-NEXT: global_load_ubyte v5, v1, s[2:3] offset:1
+; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3] offset:2
+; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3] offset:3
; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:4
-; GFX10-NEXT: s_waitcnt vmcnt(7)
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(5)
-; GFX10-NEXT: v_lshlrev_b32_e32 v3, 8, v3
-; GFX10-NEXT: s_waitcnt vmcnt(4)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
+; GFX10-NEXT: v_lshl_or_b32 v2, v3, 8, v2
; GFX10-NEXT: s_waitcnt vmcnt(3)
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX10-NEXT: v_lshl_or_b32 v4, v5, 8, v4
+; GFX10-NEXT: s_waitcnt vmcnt(1)
+; GFX10-NEXT: v_lshl_or_b32 v5, v7, 8, v6
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v8
-; GFX10-NEXT: v_or_b32_e32 v4, v4, v6
-; GFX10-NEXT: v_or_b32_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v3, v5, v4
-; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 8, v8
+; GFX10-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX10-NEXT: v_ffbh_u32_e32 v2, v3
; GFX10-NEXT: v_ffbh_u32_e32 v0, v0
; GFX10-NEXT: v_add_nc_u32_e64 v2, v2, 32 clamp
@@ -171,32 +147,25 @@ define amdgpu_kernel void @cttz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_ubyte v0, v1, s[2:3] offset:5
-; GFX9-NEXT: global_load_ubyte v2, v1, s[2:3] offset:6
-; GFX9-NEXT: global_load_ubyte v3, v1, s[2:3] offset:7
-; GFX9-NEXT: global_load_ubyte v4, v1, s[2:3] offset:1
-; GFX9-NEXT: global_load_ubyte v5, v1, s[2:3] offset:3
-; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
-; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
-; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX9-NEXT: s_waitcnt vmcnt(7)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX9-NEXT: s_waitcnt vmcnt(5)
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX9-NEXT: global_load_ubyte v0, v1, s[2:3] offset:4
+; GFX9-NEXT: global_load_ubyte v2, v1, s[2:3] offset:5
+; GFX9-NEXT: global_load_ubyte v3, v1, s[2:3] offset:6
+; GFX9-NEXT: global_load_ubyte v4, v1, s[2:3] offset:7
+; GFX9-NEXT: global_load_ubyte v5, v1, s[2:3]
+; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:1
+; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
+; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:3
+; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 8, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX9-NEXT: v_or_b32_e32 v2, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v6, 8, v5
; GFX9-NEXT: v_ffbl_b32_e32 v0, v0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshl_or_b32 v4, v8, 8, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v3
; GFX9-NEXT: v_ffbl_b32_e32 v2, v2
; GFX9-NEXT: v_add_u32_e64 v0, v0, 32 clamp
; GFX9-NEXT: v_min_u32_e32 v0, v0, v2
@@ -209,31 +178,24 @@ define amdgpu_kernel void @cttz_i64_poison(ptr addrspace(1) noalias %out, ptr ad
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x7
-; GFX10-NEXT: global_load_ubyte v0, v1, s[2:3] offset:5
-; GFX10-NEXT: global_load_ubyte v2, v1, s[2:3] offset:7
+; GFX10-NEXT: global_load_ubyte v0, v1, s[2:3] offset:4
+; GFX10-NEXT: global_load_ubyte v2, v1, s[2:3] offset:5
; GFX10-NEXT: global_load_ubyte v3, v1, s[2:3] offset:6
-; GFX10-NEXT: global_load_ubyte v4, v1, s[2:3] offset:1
-; GFX10-NEXT: global_load_ubyte v5, v1, s[2:3] offset:3
-; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
-; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3]
-; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX10-NEXT: s_waitcnt vmcnt(7)
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX10-NEXT: global_load_ubyte v4, v1, s[2:3] offset:7
+; GFX10-NEXT: global_load_ubyte v5, v1, s[2:3]
+; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3] offset:1
+; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
+; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:3
; GFX10-NEXT: s_waitcnt vmcnt(6)
-; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX10-NEXT: v_lshl_or_b32 v0, v2, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(4)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX10-NEXT: s_waitcnt vmcnt(3)
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX10-NEXT: v_lshl_or_b32 v2, v4, 8, v3
; GFX10-NEXT: s_waitcnt vmcnt(2)
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX10-NEXT: v_lshl_or_b32 v3, v6, 8, v5
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX10-NEXT: v_or_b32_e32 v2, v4, v3
+; GFX10-NEXT: v_lshl_or_b32 v4, v8, 8, v7
+; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX10-NEXT: v_lshl_or_b32 v2, v4, 16, v3
; GFX10-NEXT: v_ffbl_b32_e32 v0, v0
; GFX10-NEXT: v_ffbl_b32_e32 v2, v2
; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, 32 clamp
@@ -252,32 +214,25 @@ define amdgpu_kernel void @cttz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: global_load_ubyte v0, v1, s[2:3] offset:5
-; GFX9-NEXT: global_load_ubyte v2, v1, s[2:3] offset:6
-; GFX9-NEXT: global_load_ubyte v3, v1, s[2:3] offset:7
-; GFX9-NEXT: global_load_ubyte v4, v1, s[2:3] offset:1
-; GFX9-NEXT: global_load_ubyte v5, v1, s[2:3] offset:3
-; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
-; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3]
-; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX9-NEXT: s_waitcnt vmcnt(7)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
-; GFX9-NEXT: s_waitcnt vmcnt(5)
-; GFX9-NEXT: v_lshlrev_b32_e32 v3, 8, v3
+; GFX9-NEXT: global_load_ubyte v0, v1, s[2:3] offset:4
+; GFX9-NEXT: global_load_ubyte v2, v1, s[2:3] offset:5
+; GFX9-NEXT: global_load_ubyte v3, v1, s[2:3] offset:6
+; GFX9-NEXT: global_load_ubyte v4, v1, s[2:3] offset:7
+; GFX9-NEXT: global_load_ubyte v5, v1, s[2:3]
+; GFX9-NEXT: global_load_ubyte v6, v1, s[2:3] offset:1
+; GFX9-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
+; GFX9-NEXT: global_load_ubyte v8, v1, s[2:3] offset:3
+; GFX9-NEXT: s_waitcnt vmcnt(6)
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 8, v0
; GFX9-NEXT: s_waitcnt vmcnt(4)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 8, v3
+; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX9-NEXT: v_or_b32_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_e32 v3, v4, v7
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX9-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX9-NEXT: v_or_b32_e32 v2, v4, v3
+; GFX9-NEXT: v_lshl_or_b32 v3, v6, 8, v5
; GFX9-NEXT: v_ffbl_b32_e32 v0, v0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshl_or_b32 v4, v8, 8, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v4, 16, v3
; GFX9-NEXT: v_ffbl_b32_e32 v2, v2
; GFX9-NEXT: v_add_u32_e64 v0, v0, 32 clamp
; GFX9-NEXT: v_min_u32_e32 v0, v0, v2
@@ -291,31 +246,24 @@ define amdgpu_kernel void @cttz_i64(ptr addrspace(1) noalias %out, ptr addrspace
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x7
-; GFX10-NEXT: global_load_ubyte v0, v1, s[2:3] offset:5
-; GFX10-NEXT: global_load_ubyte v2, v1, s[2:3] offset:7
+; GFX10-NEXT: global_load_ubyte v0, v1, s[2:3] offset:4
+; GFX10-NEXT: global_load_ubyte v2, v1, s[2:3] offset:5
; GFX10-NEXT: global_load_ubyte v3, v1, s[2:3] offset:6
-; GFX10-NEXT: global_load_ubyte v4, v1, s[2:3] offset:1
-; GFX10-NEXT: global_load_ubyte v5, v1, s[2:3] offset:3
-; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3] offset:4
-; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3]
-; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:2
-; GFX10-NEXT: s_waitcnt vmcnt(7)
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
+; GFX10-NEXT: global_load_ubyte v4, v1, s[2:3] offset:7
+; GFX10-NEXT: global_load_ubyte v5, v1, s[2:3]
+; GFX10-NEXT: global_load_ubyte v6, v1, s[2:3] offset:1
+; GFX10-NEXT: global_load_ubyte v7, v1, s[2:3] offset:2
+; GFX10-NEXT: global_load_ubyte v8, v1, s[2:3] offset:3
; GFX10-NEXT: s_waitcnt vmcnt(6)
-; GFX10-NEXT: v_lshlrev_b32_e32 v2, 8, v2
+; GFX10-NEXT: v_lshl_or_b32 v0, v2, 8, v0
; GFX10-NEXT: s_waitcnt vmcnt(4)
-; GFX10-NEXT: v_lshlrev_b32_e32 v4, 8, v4
-; GFX10-NEXT: s_waitcnt vmcnt(3)
-; GFX10-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX10-NEXT: v_lshl_or_b32 v2, v4, 8, v3
; GFX10-NEXT: s_waitcnt vmcnt(2)
-; GFX10-NEXT: v_or_b32_e32 v0, v0, v6
-; GFX10-NEXT: v_or_b32_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: s_waitcnt vmcnt(1)
-; GFX10-NEXT: v_or_b32_e32 v3, v4, v7
+; GFX10-NEXT: v_lshl_or_b32 v3, v6, 8, v5
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_or_b32_sdwa v4, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
-; GFX10-NEXT: v_or_b32_e32 v0, v2, v0
-; GFX10-NEXT: v_or_b32_e32 v2, v4, v3
+; GFX10-NEXT: v_lshl_or_b32 v4, v8, 8, v7
+; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v0
+; GFX10-NEXT: v_lshl_or_b32 v2, v4, 16, v3
; GFX10-NEXT: v_ffbl_b32_e32 v0, v0
; GFX10-NEXT: v_ffbl_b32_e32 v2, v2
; GFX10-NEXT: v_add_nc_u32_e64 v0, v0, 32 clamp
diff --git a/llvm/test/CodeGen/AMDGPU/permute_i8.ll b/llvm/test/CodeGen/AMDGPU/permute_i8.ll
index b54d80a03abd0..a60caa2db7537 100644
--- a/llvm/test/CodeGen/AMDGPU/permute_i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/permute_i8.ll
@@ -615,22 +615,21 @@ define amdgpu_kernel void @shuffle8i8(ptr addrspace(1) %in0, ptr addrspace(1) %i
; GFX10-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_bfe_u32 s0, s4, 0x80008
+; GFX10-NEXT: s_bfe_u32 s1, s5, 0x80008
+; GFX10-NEXT: s_and_b32 s2, s4, 0xff
+; GFX10-NEXT: s_bfe_u32 s3, s9, 0x100010
+; GFX10-NEXT: s_lshl_b32 s5, s8, 8
; GFX10-NEXT: v_perm_b32 v0, s4, s8, v0
-; GFX10-NEXT: s_lshl_b32 s1, s9, 8
-; GFX10-NEXT: s_bfe_u32 s2, s5, 0x80008
-; GFX10-NEXT: s_lshl_b32 s3, s8, 8
-; GFX10-NEXT: s_bfe_u32 s9, s9, 0x100010
-; GFX10-NEXT: s_and_b32 s5, s4, 0xff
-; GFX10-NEXT: s_or_b32 s1, s2, s1
-; GFX10-NEXT: s_lshl_b32 s2, s9, 8
-; GFX10-NEXT: s_or_b32 s0, s0, s3
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX10-NEXT: s_or_b32 s2, s5, s2
-; GFX10-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX10-NEXT: s_lshl_b32 s1, s1, 16
-; GFX10-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX10-NEXT: s_or_b32 s5, s5, s0
+; GFX10-NEXT: s_lshl_b32 s0, s9, 8
; GFX10-NEXT: s_or_b32 s0, s0, s1
-; GFX10-NEXT: v_or_b32_e32 v1, s2, v0
+; GFX10-NEXT: s_lshl_b32 s1, s3, 8
+; GFX10-NEXT: s_or_b32 s1, s1, s2
+; GFX10-NEXT: s_and_b32 s2, s5, 0xffff
+; GFX10-NEXT: s_lshl_b32 s0, s0, 16
+; GFX10-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX10-NEXT: s_or_b32 s0, s2, s0
+; GFX10-NEXT: v_lshl_or_b32 v1, v0, 16, s1
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX10-NEXT: s_endpgm
@@ -645,24 +644,23 @@ define amdgpu_kernel void @shuffle8i8(ptr addrspace(1) %in0, ptr addrspace(1) %i
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_bfe_u32 s2, s5, 0x80008
-; GFX9-NEXT: s_lshl_b32 s1, s9, 8
; GFX9-NEXT: s_bfe_u32 s0, s4, 0x80008
-; GFX9-NEXT: s_lshl_b32 s3, s8, 8
-; GFX9-NEXT: s_or_b32 s1, s2, s1
-; GFX9-NEXT: s_bfe_u32 s2, s9, 0x100010
-; GFX9-NEXT: s_and_b32 s5, s4, 0xff
-; GFX9-NEXT: s_or_b32 s0, s0, s3
-; GFX9-NEXT: s_lshl_b32 s2, s2, 8
+; GFX9-NEXT: s_bfe_u32 s1, s5, 0x80008
+; GFX9-NEXT: s_and_b32 s2, s4, 0xff
+; GFX9-NEXT: s_bfe_u32 s3, s9, 0x100010
+; GFX9-NEXT: s_lshl_b32 s5, s9, 8
+; GFX9-NEXT: s_or_b32 s5, s5, s1
+; GFX9-NEXT: s_lshl_b32 s1, s8, 8
+; GFX9-NEXT: s_or_b32 s1, s1, s0
+; GFX9-NEXT: s_lshl_b32 s0, s3, 8
+; GFX9-NEXT: s_or_b32 s0, s0, s2
; GFX9-NEXT: v_mov_b32_e32 v0, s8
-; GFX9-NEXT: s_or_b32 s2, s5, s2
; GFX9-NEXT: v_perm_b32 v0, s4, v0, v1
; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX9-NEXT: v_lshl_or_b32 v1, v0, 16, s0
+; GFX9-NEXT: s_and_b32 s0, s1, 0xffff
+; GFX9-NEXT: s_lshl_b32 s1, s5, 16
; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: v_or_b32_e32 v1, s2, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX9-NEXT: s_endpgm
@@ -3873,8 +3871,7 @@ define amdgpu_kernel void @any_extend_to_perm(i8 %arg, <4 x i8> %arg1) {
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_perm_b32 v0, s1, s0, v0
; GFX10-NEXT: s_and_b32 s0, s1, 0xffff
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX10-NEXT: v_lshl_or_b32 v0, v0, 16, s0
; GFX10-NEXT: ds_write_b32 v1, v0
; GFX10-NEXT: s_endpgm
;
@@ -3884,10 +3881,9 @@ define amdgpu_kernel void @any_extend_to_perm(i8 %arg, <4 x i8> %arg1) {
; GFX9-NEXT: v_mov_b32_e32 v0, 0xc0c0006
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s0
-; GFX9-NEXT: v_perm_b32 v0, s1, v1, v0
; GFX9-NEXT: s_and_b32 s2, s1, 0xffff
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX9-NEXT: v_or_b32_e32 v0, s2, v0
+; GFX9-NEXT: v_perm_b32 v0, s1, v1, v0
+; GFX9-NEXT: v_lshl_or_b32 v0, v0, 16, s2
; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: ds_write_b32 v1, v0
; GFX9-NEXT: s_endpgm
@@ -3904,19 +3900,17 @@ define amdgpu_kernel void @more_any_extend_to_perm(i8 %arg, <4 x i8> %arg1, i8 %
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; GFX10-NEXT: v_mov_b32_e32 v0, 0xc0c0304
-; GFX10-NEXT: v_mov_b32_e32 v1, 0xc0c0104
+; GFX10-NEXT: v_mov_b32_e32 v0, 0xc0c0104
+; GFX10-NEXT: v_mov_b32_e32 v1, 0xc0c0304
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v2, s6, s7, v0
-; GFX10-NEXT: v_perm_b32 v0, s0, s7, v0
-; GFX10-NEXT: v_perm_b32 v3, s0, s7, v1
-; GFX10-NEXT: v_perm_b32 v1, s6, s7, v1
+; GFX10-NEXT: v_perm_b32 v3, s6, s7, v1
+; GFX10-NEXT: v_perm_b32 v2, s0, s7, v0
+; GFX10-NEXT: v_perm_b32 v0, s6, s7, v0
+; GFX10-NEXT: v_perm_b32 v1, s0, s7, v1
; GFX10-NEXT: v_mov_b32_e32 v4, s1
-; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX10-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX10-NEXT: v_mov_b32_e32 v5, s2
-; GFX10-NEXT: v_or_b32_e32 v2, v3, v2
-; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
+; GFX10-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX10-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX10-NEXT: ds_write_b32 v4, v2
; GFX10-NEXT: ds_write_b32 v5, v0
; GFX10-NEXT: s_endpgm
@@ -3925,19 +3919,17 @@ define amdgpu_kernel void @more_any_extend_to_perm(i8 %arg, <4 x i8> %arg1, i8 %
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
-; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0304
; GFX9-NEXT: v_mov_b32_e32 v0, 0xc0c0104
+; GFX9-NEXT: v_mov_b32_e32 v1, 0xc0c0304
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v2, s7
-; GFX9-NEXT: v_perm_b32 v4, s6, v2, v1
-; GFX9-NEXT: v_perm_b32 v1, s0, v2, v1
; GFX9-NEXT: v_perm_b32 v3, s0, v2, v0
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX9-NEXT: v_perm_b32 v4, s6, v2, v1
; GFX9-NEXT: v_perm_b32 v0, s6, v2, v0
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
+; GFX9-NEXT: v_perm_b32 v1, s0, v2, v1
+; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3
; GFX9-NEXT: v_mov_b32_e32 v4, s1
-; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: ds_write_b32 v4, v3
; GFX9-NEXT: ds_write_b32 v1, v0
diff --git a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
index 70d08930e3b9c..4d52b0d41c4aa 100644
--- a/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
+++ b/llvm/test/CodeGen/AMDGPU/preload-kernargs.ll
@@ -639,12 +639,12 @@ define amdgpu_kernel void @v5i8_preload_arg(ptr addrspace(1) nocapture inreg %ou
; GFX942-NEXT: .p2align 8
; GFX942-NEXT: ; %bb.2:
; GFX942-NEXT: .LBB13_0:
-; GFX942-NEXT: s_lshr_b32 s1, s4, 24
; GFX942-NEXT: s_and_b32 s0, s4, 0xffff
-; GFX942-NEXT: s_lshl_b32 s1, s1, 8
+; GFX942-NEXT: s_lshr_b32 s1, s4, 24
; GFX942-NEXT: s_bfe_u32 s4, s4, 0x80010
-; GFX942-NEXT: s_or_b32 s1, s4, s1
-; GFX942-NEXT: s_lshl_b32 s1, s1, 16
+; GFX942-NEXT: s_lshl_b32 s6, s1, 8
+; GFX942-NEXT: s_or_b32 s6, s6, s4
+; GFX942-NEXT: s_lshl_b32 s1, s6, 16
; GFX942-NEXT: s_or_b32 s0, s0, s1
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: v_mov_b32_e32 v1, s5
@@ -661,12 +661,12 @@ define amdgpu_kernel void @v5i8_preload_arg(ptr addrspace(1) nocapture inreg %ou
; GFX90a-NEXT: .p2align 8
; GFX90a-NEXT: ; %bb.2:
; GFX90a-NEXT: .LBB13_0:
+; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff
; GFX90a-NEXT: s_lshr_b32 s1, s10, 24
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 8
; GFX90a-NEXT: s_bfe_u32 s2, s10, 0x80010
-; GFX90a-NEXT: s_or_b32 s1, s2, s1
-; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 16
+; GFX90a-NEXT: s_lshl_b32 s3, s1, 8
+; GFX90a-NEXT: s_or_b32 s3, s3, s2
+; GFX90a-NEXT: s_lshl_b32 s1, s3, 16
; GFX90a-NEXT: s_or_b32 s0, s0, s1
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
; GFX90a-NEXT: v_mov_b32_e32 v1, s11
@@ -779,19 +779,19 @@ define amdgpu_kernel void @v8i8_preload_arg(ptr addrspace(1) inreg %out, <8 x i8
; GFX942-NEXT: .p2align 8
; GFX942-NEXT: ; %bb.2:
; GFX942-NEXT: .LBB15_0:
-; GFX942-NEXT: s_lshr_b32 s1, s5, 24
; GFX942-NEXT: s_and_b32 s0, s5, 0xffff
-; GFX942-NEXT: s_lshl_b32 s1, s1, 8
+; GFX942-NEXT: s_lshr_b32 s1, s5, 24
; GFX942-NEXT: s_bfe_u32 s5, s5, 0x80010
-; GFX942-NEXT: s_or_b32 s1, s5, s1
-; GFX942-NEXT: s_lshl_b32 s1, s1, 16
-; GFX942-NEXT: s_lshr_b32 s5, s4, 24
+; GFX942-NEXT: s_lshl_b32 s6, s1, 8
+; GFX942-NEXT: s_or_b32 s6, s6, s5
+; GFX942-NEXT: s_lshl_b32 s1, s6, 16
; GFX942-NEXT: s_or_b32 s0, s0, s1
; GFX942-NEXT: s_and_b32 s1, s4, 0xffff
-; GFX942-NEXT: s_lshl_b32 s5, s5, 8
+; GFX942-NEXT: s_lshr_b32 s5, s4, 24
; GFX942-NEXT: s_bfe_u32 s4, s4, 0x80010
-; GFX942-NEXT: s_or_b32 s4, s4, s5
-; GFX942-NEXT: s_lshl_b32 s4, s4, 16
+; GFX942-NEXT: s_lshl_b32 s6, s5, 8
+; GFX942-NEXT: s_or_b32 s6, s6, s4
+; GFX942-NEXT: s_lshl_b32 s4, s6, 16
; GFX942-NEXT: s_or_b32 s1, s1, s4
; GFX942-NEXT: v_mov_b32_e32 v0, s1
; GFX942-NEXT: v_mov_b32_e32 v1, s0
@@ -807,19 +807,19 @@ define amdgpu_kernel void @v8i8_preload_arg(ptr addrspace(1) inreg %out, <8 x i8
; GFX90a-NEXT: .p2align 8
; GFX90a-NEXT: ; %bb.2:
; GFX90a-NEXT: .LBB15_0:
+; GFX90a-NEXT: s_and_b32 s0, s11, 0xffff
; GFX90a-NEXT: s_lshr_b32 s1, s11, 24
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 8
; GFX90a-NEXT: s_bfe_u32 s2, s11, 0x80010
-; GFX90a-NEXT: s_or_b32 s1, s2, s1
-; GFX90a-NEXT: s_lshr_b32 s2, s10, 24
-; GFX90a-NEXT: s_lshl_b32 s2, s2, 8
-; GFX90a-NEXT: s_bfe_u32 s3, s10, 0x80010
-; GFX90a-NEXT: s_and_b32 s0, s11, 0xffff
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 16
-; GFX90a-NEXT: s_or_b32 s2, s3, s2
+; GFX90a-NEXT: s_lshl_b32 s3, s1, 8
+; GFX90a-NEXT: s_or_b32 s3, s3, s2
+; GFX90a-NEXT: s_lshl_b32 s1, s3, 16
; GFX90a-NEXT: s_or_b32 s0, s0, s1
; GFX90a-NEXT: s_and_b32 s1, s10, 0xffff
-; GFX90a-NEXT: s_lshl_b32 s2, s2, 16
+; GFX90a-NEXT: s_lshr_b32 s2, s10, 24
+; GFX90a-NEXT: s_bfe_u32 s3, s10, 0x80010
+; GFX90a-NEXT: s_lshl_b32 s4, s2, 8
+; GFX90a-NEXT: s_or_b32 s4, s4, s3
+; GFX90a-NEXT: s_lshl_b32 s2, s4, 16
; GFX90a-NEXT: s_or_b32 s1, s1, s2
; GFX90a-NEXT: v_mov_b32_e32 v0, s1
; GFX90a-NEXT: v_mov_b32_e32 v1, s0
@@ -1287,12 +1287,12 @@ define amdgpu_kernel void @v7i8_kernel_preload_arg(ptr addrspace(1) inreg %out,
; GFX942-NEXT: .p2align 8
; GFX942-NEXT: ; %bb.2:
; GFX942-NEXT: .LBB26_0:
-; GFX942-NEXT: s_lshr_b32 s1, s4, 24
; GFX942-NEXT: s_and_b32 s0, s4, 0xffff
-; GFX942-NEXT: s_lshl_b32 s1, s1, 8
+; GFX942-NEXT: s_lshr_b32 s1, s4, 24
; GFX942-NEXT: s_bfe_u32 s4, s4, 0x80010
-; GFX942-NEXT: s_or_b32 s1, s4, s1
-; GFX942-NEXT: s_lshl_b32 s1, s1, 16
+; GFX942-NEXT: s_lshl_b32 s6, s1, 8
+; GFX942-NEXT: s_or_b32 s6, s6, s4
+; GFX942-NEXT: s_lshl_b32 s1, s6, 16
; GFX942-NEXT: s_or_b32 s0, s0, s1
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: v_mov_b32_e32 v1, s5
@@ -1310,12 +1310,12 @@ define amdgpu_kernel void @v7i8_kernel_preload_arg(ptr addrspace(1) inreg %out,
; GFX90a-NEXT: .p2align 8
; GFX90a-NEXT: ; %bb.2:
; GFX90a-NEXT: .LBB26_0:
+; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff
; GFX90a-NEXT: s_lshr_b32 s1, s10, 24
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 8
; GFX90a-NEXT: s_bfe_u32 s2, s10, 0x80010
-; GFX90a-NEXT: s_or_b32 s1, s2, s1
-; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff
-; GFX90a-NEXT: s_lshl_b32 s1, s1, 16
+; GFX90a-NEXT: s_lshl_b32 s3, s1, 8
+; GFX90a-NEXT: s_or_b32 s3, s3, s2
+; GFX90a-NEXT: s_lshl_b32 s1, s3, 16
; GFX90a-NEXT: s_or_b32 s0, s0, s1
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
; GFX90a-NEXT: v_mov_b32_e32 v1, s11
@@ -1549,13 +1549,13 @@ define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %o
; GFX942-NEXT: ; %bb.2:
; GFX942-NEXT: .LBB31_0:
; GFX942-NEXT: s_lshr_b32 s0, s4, 24
-; GFX942-NEXT: s_lshl_b32 s0, s0, 8
; GFX942-NEXT: s_bfe_u32 s1, s4, 0x80010
-; GFX942-NEXT: s_or_b32 s0, s1, s0
+; GFX942-NEXT: s_lshl_b32 s5, s0, 8
+; GFX942-NEXT: s_or_b32 s5, s5, s1
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: v_mov_b32_e32 v1, s4
; GFX942-NEXT: global_store_short v0, v1, s[2:3]
-; GFX942-NEXT: v_mov_b32_e32 v1, s0
+; GFX942-NEXT: v_mov_b32_e32 v1, s5
; GFX942-NEXT: global_store_short v0, v1, s[6:7]
; GFX942-NEXT: s_endpgm
;
@@ -1569,13 +1569,13 @@ define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %o
; GFX90a-NEXT: ; %bb.2:
; GFX90a-NEXT: .LBB31_0:
; GFX90a-NEXT: s_lshr_b32 s0, s10, 24
-; GFX90a-NEXT: s_lshl_b32 s0, s0, 8
; GFX90a-NEXT: s_bfe_u32 s1, s10, 0x80010
-; GFX90a-NEXT: s_or_b32 s0, s1, s0
+; GFX90a-NEXT: s_lshl_b32 s2, s0, 8
+; GFX90a-NEXT: s_or_b32 s2, s2, s1
; GFX90a-NEXT: v_mov_b32_e32 v0, 0
; GFX90a-NEXT: v_mov_b32_e32 v1, s10
; GFX90a-NEXT: global_store_short v0, v1, s[8:9]
-; GFX90a-NEXT: v_mov_b32_e32 v1, s0
+; GFX90a-NEXT: v_mov_b32_e32 v1, s2
; GFX90a-NEXT: global_store_short v0, v1, s[12:13]
; GFX90a-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
index ab6597363825e..f033e8520aaa3 100644
--- a/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
+++ b/llvm/test/CodeGen/AMDGPU/promote-alloca-vector-dynamic-idx-bitcasts-llc.ll
@@ -6,14 +6,14 @@
define amdgpu_kernel void @test_bitcast_llc_v128i8_v16i8(ptr addrspace(1) %out, i32 %idx) {
; GFX9-LABEL: test_bitcast_llc_v128i8_v16i8:
; GFX9: ; %bb.0: ; %entry
-; GFX9-NEXT: s_lshl_b32 s0, s0, 8
+; GFX9-NEXT: s_and_b32 s0, s0, 0xff
; GFX9-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x0
; GFX9-NEXT: s_load_dword s33, s[4:5], 0x8
-; GFX9-NEXT: s_and_b32 s1, s0, 0xff
-; GFX9-NEXT: s_or_b32 s0, s1, s0
-; GFX9-NEXT: s_and_b32 s1, s0, 0xffff
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
-; GFX9-NEXT: s_or_b32 s0, s1, s0
+; GFX9-NEXT: s_lshl_b32 s1, s0, 8
+; GFX9-NEXT: s_or_b32 s1, s1, s0
+; GFX9-NEXT: s_and_b32 s0, s1, 0xffff
+; GFX9-NEXT: s_lshl_b32 s1, s1, 16
+; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: s_mov_b32 s1, s0
; GFX9-NEXT: s_mov_b32 s2, s0
; GFX9-NEXT: s_mov_b32 s3, s0
@@ -80,15 +80,15 @@ define amdgpu_kernel void @test_bitcast_llc_v128i8_v16i8(ptr addrspace(1) %out,
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b64 s[34:35], s[4:5], 0x0
; GFX11-NEXT: s_load_b32 s33, s[4:5], 0x8
-; GFX11-NEXT: s_lshl_b32 s0, s0, 8
+; GFX11-NEXT: s_and_b32 s0, s0, 0xff
; GFX11-NEXT: v_mov_b32_e32 v35, 0
-; GFX11-NEXT: s_and_b32 s1, s0, 0xff
+; GFX11-NEXT: s_lshl_b32 s1, s0, 8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s1, s0
-; GFX11-NEXT: s_and_b32 s1, s0, 0xffff
-; GFX11-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-NEXT: s_or_b32 s1, s1, s0
+; GFX11-NEXT: s_and_b32 s0, s1, 0xffff
+; GFX11-NEXT: s_lshl_b32 s1, s1, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s1, s0
+; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: s_mov_b32 s1, s0
; GFX11-NEXT: s_mov_b32 s2, s0
; GFX11-NEXT: s_mov_b32 s3, s0
@@ -148,15 +148,15 @@ define amdgpu_kernel void @test_bitcast_llc_v128i8_v16i8(ptr addrspace(1) %out,
; GFX12-LABEL: test_bitcast_llc_v128i8_v16i8:
; GFX12: ; %bb.0: ; %entry
; GFX12-NEXT: s_load_b96 s[36:38], s[4:5], 0x0
-; GFX12-NEXT: s_lshl_b32 s0, s0, 8
+; GFX12-NEXT: s_and_b32 s0, s0, 0xff
; GFX12-NEXT: v_mov_b32_e32 v35, 0
-; GFX12-NEXT: s_and_b32 s1, s0, 0xff
+; GFX12-NEXT: s_lshl_b32 s1, s0, 8
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_or_b32 s0, s1, s0
-; GFX12-NEXT: s_and_b32 s1, s0, 0xffff
-; GFX12-NEXT: s_lshl_b32 s0, s0, 16
+; GFX12-NEXT: s_or_b32 s1, s1, s0
+; GFX12-NEXT: s_and_b32 s0, s1, 0xffff
+; GFX12-NEXT: s_lshl_b32 s1, s1, 16
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: s_or_b32 s0, s1, s0
+; GFX12-NEXT: s_or_b32 s0, s0, s1
; GFX12-NEXT: s_mov_b32 s1, s0
; GFX12-NEXT: s_mov_b32 s2, s0
; GFX12-NEXT: s_mov_b32 s3, s0
diff --git a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
index a82415e2e8303..f5f0fe7ecf3f6 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar_to_vector.ll
@@ -223,10 +223,10 @@ define amdgpu_kernel void @scalar_to_vector_v4i16() {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: s_lshl_b32 s1, s0, 8
+; GFX9-NEXT: s_or_b32 s1, s1, s0
+; GFX9-NEXT: s_and_b32 s0, s1, 0xffff
+; GFX9-NEXT: s_lshl_b32 s1, s1, 16
; GFX9-NEXT: s_or_b32 s0, s0, s1
-; GFX9-NEXT: s_and_b32 s1, s0, 0xffff
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
-; GFX9-NEXT: s_or_b32 s0, s1, s0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
@@ -241,11 +241,11 @@ define amdgpu_kernel void @scalar_to_vector_v4i16() {
; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: s_lshl_b32 s1, s0, 8
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s0, s1
-; GFX11-NEXT: s_and_b32 s1, s0, 0xffff
-; GFX11-NEXT: s_lshl_b32 s0, s0, 16
+; GFX11-NEXT: s_or_b32 s1, s1, s0
+; GFX11-NEXT: s_and_b32 s0, s1, 0xffff
+; GFX11-NEXT: s_lshl_b32 s1, s1, 16
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: s_or_b32 s0, s1, s0
+; GFX11-NEXT: s_or_b32 s0, s0, s1
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX11-NEXT: s_endpgm
@@ -304,15 +304,15 @@ define amdgpu_kernel void @scalar_to_vector_v4f16() {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: s_lshl_b32 s1, s0, 8
+; GFX9-NEXT: s_or_b32 s1, s1, s0
+; GFX9-NEXT: s_and_b32 s0, s1, 0xff00
+; GFX9-NEXT: s_bfe_u32 s4, s1, 0x80008
+; GFX9-NEXT: s_or_b32 s0, s4, s0
+; GFX9-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX9-NEXT: s_and_b32 s4, s0, 0xffff
+; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: s_or_b32 s4, s4, s0
; GFX9-NEXT: s_or_b32 s0, s1, s0
-; GFX9-NEXT: s_and_b32 s1, s0, 0xff00
-; GFX9-NEXT: s_bfe_u32 s4, s0, 0x80008
-; GFX9-NEXT: s_or_b32 s1, s4, s1
-; GFX9-NEXT: s_and_b32 s0, s0, 0xffff
-; GFX9-NEXT: s_and_b32 s4, s1, 0xffff
-; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: s_or_b32 s4, s4, s1
-; GFX9-NEXT: s_or_b32 s0, s0, s1
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
@@ -322,24 +322,22 @@ define amdgpu_kernel void @scalar_to_vector_v4f16() {
; GFX11: ; %bb.0: ; %bb
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
; GFX11-NEXT: s_mov_b32 s2, -1
+; GFX11-NEXT: ; kill: def $vgpr1_hi16 killed $sgpr0 killed $exec
; GFX11-NEXT: buffer_load_d16_u8 v0, off, s[0:3], 0
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v0
+; GFX11-NEXT: v_lshl_or_b32 v0, v0, 8, v0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: v_or_b32_e32 v0, v1, v0
-; GFX11-NEXT: ; kill: def $vgpr1_hi16 killed $sgpr0 killed $exec
; GFX11-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v1
; GFX11-NEXT: s_and_b32 s1, s0, 0xff00
; GFX11-NEXT: s_bfe_u32 s4, s0, 0x80008
; GFX11-NEXT: s_and_b32 s0, s0, 0xffff
; GFX11-NEXT: s_or_b32 s1, s4, s1
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshl_b32 s4, s1, 16
; GFX11-NEXT: s_and_b32 s1, s1, 0xffff
; GFX11-NEXT: s_or_b32 s0, s0, s4
; GFX11-NEXT: s_or_b32 s1, s1, s4
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX11-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/sdiv.ll b/llvm/test/CodeGen/AMDGPU/sdiv.ll
index b690879dab99b..702cbc03294da 100644
--- a/llvm/test/CodeGen/AMDGPU/sdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdiv.ll
@@ -1688,33 +1688,29 @@ define amdgpu_kernel void @v_sdiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, s10
; GFX9-NEXT: s_mov_b32 s5, s11
-; GFX9-NEXT: buffer_load_ubyte v0, off, s[4:7], 0 offset:2
+; GFX9-NEXT: buffer_load_ushort v0, off, s[4:7], 0 offset:4
; GFX9-NEXT: buffer_load_ubyte v1, off, s[4:7], 0 offset:6
-; GFX9-NEXT: buffer_load_ushort v2, off, s[4:7], 0 offset:4
-; GFX9-NEXT: buffer_load_ushort v3, off, s[4:7], 0
+; GFX9-NEXT: buffer_load_ushort v2, off, s[4:7], 0
+; GFX9-NEXT: buffer_load_ubyte v3, off, s[4:7], 0 offset:2
; GFX9-NEXT: s_mov_b32 s0, s8
; GFX9-NEXT: s_mov_b32 s1, s9
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX9-NEXT: v_bfe_i32 v1, v1, 0, 23
-; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v1
-; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_e32 v0, v3, v0
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 23
-; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v0
-; GFX9-NEXT: v_rcp_f32_e32 v4, v2
-; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1
+; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v0
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 23
+; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v2
+; GFX9-NEXT: v_rcp_f32_e32 v4, v1
+; GFX9-NEXT: v_xor_b32_e32 v0, v2, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0
; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
-; GFX9-NEXT: v_mul_f32_e32 v1, v3, v4
-; GFX9-NEXT: v_trunc_f32_e32 v1, v1
-; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v1
-; GFX9-NEXT: v_mad_f32 v1, -v1, v2, v3
-; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v2|
+; GFX9-NEXT: v_mul_f32_e32 v2, v3, v4
+; GFX9-NEXT: v_trunc_f32_e32 v2, v2
+; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v2
+; GFX9-NEXT: v_mad_f32 v2, -v2, v1, v3
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
; GFX9-NEXT: v_add_u32_e32 v0, v4, v0
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 23
@@ -1865,43 +1861,39 @@ define amdgpu_kernel void @v_sdiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
;
; GFX9-LABEL: v_sdiv_i24:
; GFX9: ; %bb.0:
-; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24
-; GFX9-NEXT: s_mov_b32 s3, 0xf000
-; GFX9-NEXT: s_mov_b32 s2, -1
-; GFX9-NEXT: s_mov_b32 s6, s2
-; GFX9-NEXT: s_mov_b32 s7, s3
+; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX9-NEXT: s_mov_b32 s7, 0xf000
+; GFX9-NEXT: s_mov_b32 s6, -1
+; GFX9-NEXT: s_mov_b32 s10, s6
+; GFX9-NEXT: s_mov_b32 s11, s7
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s4, s10
-; GFX9-NEXT: s_mov_b32 s5, s11
-; GFX9-NEXT: buffer_load_sbyte v0, off, s[4:7], 0 offset:6
-; GFX9-NEXT: buffer_load_ushort v1, off, s[4:7], 0 offset:4
-; GFX9-NEXT: buffer_load_sbyte v2, off, s[4:7], 0 offset:2
-; GFX9-NEXT: buffer_load_ushort v3, off, s[4:7], 0
-; GFX9-NEXT: s_mov_b32 s0, s8
-; GFX9-NEXT: s_mov_b32 s1, s9
-; GFX9-NEXT: s_waitcnt vmcnt(3)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v0
+; GFX9-NEXT: s_mov_b32 s8, s2
+; GFX9-NEXT: s_mov_b32 s9, s3
+; GFX9-NEXT: buffer_load_ushort v0, off, s[8:11], 0 offset:4
+; GFX9-NEXT: buffer_load_sbyte v1, off, s[8:11], 0 offset:6
+; GFX9-NEXT: buffer_load_ushort v2, off, s[8:11], 0
+; GFX9-NEXT: buffer_load_sbyte v3, off, s[8:11], 0 offset:2
+; GFX9-NEXT: s_mov_b32 s4, s0
+; GFX9-NEXT: s_mov_b32 s5, s1
; GFX9-NEXT: s_waitcnt vmcnt(2)
-; GFX9-NEXT: v_or_b32_e32 v1, v1, v4
-; GFX9-NEXT: v_cvt_f32_i32_e32 v1, v1
-; GFX9-NEXT: s_waitcnt vmcnt(1)
-; GFX9-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX9-NEXT: v_lshl_or_b32 v0, v1, 16, v0
+; GFX9-NEXT: v_cvt_f32_i32_e32 v0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_or_b32_e32 v3, v3, v4
-; GFX9-NEXT: v_cvt_f32_i32_e32 v3, v3
-; GFX9-NEXT: v_rcp_f32_e32 v4, v1
-; GFX9-NEXT: v_xor_b32_e32 v0, v2, v0
-; GFX9-NEXT: v_ashrrev_i32_e32 v0, 30, v0
-; GFX9-NEXT: v_or_b32_e32 v0, 1, v0
-; GFX9-NEXT: v_mul_f32_e32 v2, v3, v4
-; GFX9-NEXT: v_trunc_f32_e32 v2, v2
-; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v2
-; GFX9-NEXT: v_mad_f32 v2, -v2, v1, v3
-; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v1|
-; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_cvt_f32_i32_e32 v2, v2
+; GFX9-NEXT: v_xor_b32_e32 v1, v3, v1
+; GFX9-NEXT: v_rcp_f32_e32 v4, v0
+; GFX9-NEXT: v_ashrrev_i32_e32 v1, 30, v1
+; GFX9-NEXT: v_or_b32_e32 v1, 1, v1
+; GFX9-NEXT: v_mul_f32_e32 v3, v2, v4
+; GFX9-NEXT: v_trunc_f32_e32 v3, v3
+; GFX9-NEXT: v_cvt_i32_f32_e32 v4, v3
+; GFX9-NEXT: v_mad_f32 v2, -v3, v0, v2
+; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, |v0|
+; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
; GFX9-NEXT: v_add_u32_e32 v0, v4, v0
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 24
-; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX9-NEXT: s_endpgm
;
; EG-LABEL: v_sdiv_i24:
diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
index fa705fb455ba8..bdb3d0c636054 100644
--- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll
@@ -1932,20 +1932,20 @@ define amdgpu_kernel void @pulled_out_test(ptr addrspace(1) %sourceA, ptr addrsp
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_readfirstlane_b32 s0, v1
; GFX9-NEXT: v_readfirstlane_b32 s1, v0
-; GFX9-NEXT: s_lshr_b32 s6, s0, 24
+; GFX9-NEXT: v_perm_b32 v0, s1, s1, v3
; GFX9-NEXT: s_lshr_b32 s4, s1, 24
+; GFX9-NEXT: s_bfe_u32 s1, s1, 0x80010
; GFX9-NEXT: s_and_b32 s5, s0, 0xffff
+; GFX9-NEXT: s_lshr_b32 s6, s0, 24
; GFX9-NEXT: s_bfe_u32 s0, s0, 0x80010
-; GFX9-NEXT: s_lshl_b32 s6, s6, 8
-; GFX9-NEXT: v_perm_b32 v0, s1, s1, v3
-; GFX9-NEXT: s_bfe_u32 s1, s1, 0x80010
-; GFX9-NEXT: s_lshl_b32 s4, s4, 8
-; GFX9-NEXT: s_or_b32 s0, s0, s6
-; GFX9-NEXT: s_or_b32 s1, s1, s4
-; GFX9-NEXT: s_lshl_b32 s0, s0, 16
+; GFX9-NEXT: s_lshl_b32 s7, s4, 8
+; GFX9-NEXT: s_or_b32 s7, s7, s1
+; GFX9-NEXT: s_lshl_b32 s1, s6, 8
+; GFX9-NEXT: s_or_b32 s1, s1, s0
+; GFX9-NEXT: s_lshl_b32 s0, s7, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, 16
-; GFX9-NEXT: s_or_b32 s0, s5, s0
-; GFX9-NEXT: v_or_b32_e32 v0, s1, v0
+; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX9-NEXT: s_or_b32 s0, s5, s1
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX9-NEXT: s_endpgm
@@ -1957,23 +1957,23 @@ define amdgpu_kernel void @pulled_out_test(ptr addrspace(1) %sourceA, ptr addrsp
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: s_lshr_b32 s4, s0, 24
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: s_lshr_b32 s5, s1, 24
-; GFX10-NEXT: v_perm_b32 v0, s0, s0, 0xc0c0104
-; GFX10-NEXT: s_bfe_u32 s0, s0, 0x80010
+; GFX10-NEXT: s_lshr_b32 s4, s0, 24
; GFX10-NEXT: s_bfe_u32 s6, s1, 0x80010
-; GFX10-NEXT: s_lshl_b32 s4, s4, 8
-; GFX10-NEXT: s_lshl_b32 s5, s5, 8
-; GFX10-NEXT: s_or_b32 s0, s0, s4
-; GFX10-NEXT: s_or_b32 s4, s6, s5
-; GFX10-NEXT: s_and_b32 s1, s1, 0xffff
-; GFX10-NEXT: s_lshl_b32 s4, s4, 16
-; GFX10-NEXT: s_lshl_b32 s0, s0, 16
-; GFX10-NEXT: s_or_b32 s1, s1, s4
-; GFX10-NEXT: v_or_b32_e32 v0, s0, v0
-; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: s_bfe_u32 s7, s0, 0x80010
+; GFX10-NEXT: s_lshl_b32 s8, s5, 8
+; GFX10-NEXT: v_perm_b32 v0, s0, s0, 0xc0c0104
+; GFX10-NEXT: s_or_b32 s8, s8, s6
+; GFX10-NEXT: s_lshl_b32 s5, s4, 8
+; GFX10-NEXT: s_or_b32 s5, s5, s7
+; GFX10-NEXT: s_and_b32 s0, s1, 0xffff
+; GFX10-NEXT: s_lshl_b32 s1, s8, 16
+; GFX10-NEXT: s_lshl_b32 s4, s5, 16
+; GFX10-NEXT: s_or_b32 s0, s0, s1
+; GFX10-NEXT: v_or_b32_e32 v0, s4, v0
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; GFX10-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
index 76f8f484fc763..b485ce521924e 100644
--- a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
@@ -861,26 +861,25 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
; GFX9-NEXT: v_cmp_gt_i32_sdwa vcc, sext(v1), sext(v2) src0_sel:WORD_0 src1_sel:WORD_0
-; GFX9-NEXT: v_cmp_gt_i32_sdwa s[0:1], sext(v1), sext(v2) src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
; GFX9-NEXT: v_cndmask_b32_e32 v5, v2, v1, vcc
+; GFX9-NEXT: v_cmp_gt_i32_sdwa s[0:1], sext(v1), sext(v2) src0_sel:WORD_1 src1_sel:WORD_1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v6, v4, v3, s[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
+; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2
; GFX9-NEXT: v_lshl_or_b32 v4, v6, 16, v4
+; GFX9-NEXT: v_lshl_or_b32 v2, v5, 1, v2
; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
; GFX9-NEXT: global_store_dword v0, v4, s[8:9]
; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: v_and_b32_e32 v2, 3, v2
; GFX9-NEXT: global_store_dword v0, v1, s[10:11]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v0, 3, v2
-; GFX9-NEXT: global_store_byte v[0:1], v0, off
+; GFX9-NEXT: global_store_byte v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.ll b/llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.ll
index 676e1bb154e97..277ad0eef2824 100644
--- a/llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.ll
+++ b/llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.ll
@@ -9,8 +9,8 @@ define amdgpu_kernel void @test_should_convert_to_v_readfirstlane_b32(float %fva
; GCN-NEXT: v_cvt_u32_f32_e32 v0, s0
; GCN-NEXT: s_nop 0
; GCN-NEXT: v_readfirstlane_b32 s0, v0
-; GCN-NEXT: s_lshl_b32 s0, s0, 16
-; GCN-NEXT: s_or_b32 s5, s0, s1
+; GCN-NEXT: s_lshl_b32 s5, s0, 16
+; GCN-NEXT: s_or_b32 s5, s5, s1
; GCN-NEXT: s_and_b32 s6, s5, s2
; GCN-NEXT: s_lshr_b32 s4, s6, 2
; GCN-NEXT: s_mov_b32 s7, s4
diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll
index 859a65f88800d..7564f97744958 100644
--- a/llvm/test/CodeGen/AMDGPU/udiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/udiv.ll
@@ -1802,21 +1802,17 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1030-NEXT: v_mov_b32_e32 v0, 0
; GFX1030-NEXT: s_waitcnt lgkmcnt(0)
; GFX1030-NEXT: s_clause 0x3
-; GFX1030-NEXT: global_load_ubyte v1, v0, s[2:3] offset:6
-; GFX1030-NEXT: global_load_ushort v2, v0, s[2:3] offset:4
-; GFX1030-NEXT: global_load_ubyte v3, v0, s[2:3] offset:2
-; GFX1030-NEXT: global_load_ushort v4, v0, s[2:3]
-; GFX1030-NEXT: s_waitcnt vmcnt(3)
-; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX1030-NEXT: global_load_ushort v1, v0, s[2:3] offset:4
+; GFX1030-NEXT: global_load_ubyte v2, v0, s[2:3] offset:6
+; GFX1030-NEXT: global_load_ushort v3, v0, s[2:3]
+; GFX1030-NEXT: global_load_ubyte v4, v0, s[2:3] offset:2
; GFX1030-NEXT: s_waitcnt vmcnt(2)
-; GFX1030-NEXT: v_or_b32_e32 v1, v2, v1
-; GFX1030-NEXT: s_waitcnt vmcnt(1)
-; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 16, v3
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1
+; GFX1030-NEXT: v_lshl_or_b32 v1, v2, 16, v1
; GFX1030-NEXT: s_waitcnt vmcnt(0)
-; GFX1030-NEXT: v_or_b32_e32 v2, v4, v2
-; GFX1030-NEXT: v_rcp_f32_e32 v3, v1
+; GFX1030-NEXT: v_lshl_or_b32 v2, v4, 16, v3
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1
; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v2
+; GFX1030-NEXT: v_rcp_f32_e32 v3, v1
; GFX1030-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1030-NEXT: v_trunc_f32_e32 v3, v3
; GFX1030-NEXT: v_fma_f32 v2, -v3, v1, v2
@@ -2040,34 +2036,33 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1030-NEXT: v_readfirstlane_b32 s2, v1
; GFX1030-NEXT: s_waitcnt vmcnt(2)
; GFX1030-NEXT: v_readfirstlane_b32 s3, v2
-; GFX1030-NEXT: s_waitcnt vmcnt(1)
-; GFX1030-NEXT: v_readfirstlane_b32 s4, v3
; GFX1030-NEXT: s_waitcnt vmcnt(0)
; GFX1030-NEXT: v_readfirstlane_b32 s5, v4
-; GFX1030-NEXT: s_lshl_b32 s2, s2, 16
-; GFX1030-NEXT: s_or_b32 s2, s3, s2
-; GFX1030-NEXT: s_lshl_b32 s4, s4, 16
-; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, s2
-; GFX1030-NEXT: s_sub_i32 s6, 0, s2
-; GFX1030-NEXT: s_or_b32 s4, s5, s4
+; GFX1030-NEXT: s_lshl_b32 s4, s2, 16
+; GFX1030-NEXT: v_readfirstlane_b32 s2, v3
+; GFX1030-NEXT: s_or_b32 s4, s4, s3
+; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, s4
+; GFX1030-NEXT: s_sub_i32 s6, 0, s4
+; GFX1030-NEXT: s_lshl_b32 s7, s2, 16
+; GFX1030-NEXT: s_or_b32 s7, s7, s5
; GFX1030-NEXT: v_rcp_f32_e32 v1, v1
; GFX1030-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1
; GFX1030-NEXT: v_cvt_u32_f32_e32 v1, v1
; GFX1030-NEXT: v_readfirstlane_b32 s3, v1
; GFX1030-NEXT: s_mul_i32 s6, s6, s3
-; GFX1030-NEXT: s_mul_hi_u32 s6, s3, s6
-; GFX1030-NEXT: s_add_i32 s3, s3, s6
-; GFX1030-NEXT: s_mul_hi_u32 s3, s4, s3
-; GFX1030-NEXT: s_mul_i32 s5, s3, s2
-; GFX1030-NEXT: s_sub_i32 s4, s4, s5
-; GFX1030-NEXT: s_add_i32 s5, s3, 1
-; GFX1030-NEXT: s_sub_i32 s6, s4, s2
-; GFX1030-NEXT: s_cmp_ge_u32 s4, s2
-; GFX1030-NEXT: s_cselect_b32 s3, s5, s3
-; GFX1030-NEXT: s_cselect_b32 s4, s6, s4
-; GFX1030-NEXT: s_add_i32 s5, s3, 1
-; GFX1030-NEXT: s_cmp_ge_u32 s4, s2
-; GFX1030-NEXT: s_cselect_b32 s2, s5, s3
+; GFX1030-NEXT: s_mul_hi_u32 s2, s3, s6
+; GFX1030-NEXT: s_add_i32 s3, s3, s2
+; GFX1030-NEXT: s_mul_hi_u32 s2, s7, s3
+; GFX1030-NEXT: s_mul_i32 s3, s2, s4
+; GFX1030-NEXT: s_add_i32 s5, s2, 1
+; GFX1030-NEXT: s_sub_i32 s3, s7, s3
+; GFX1030-NEXT: s_sub_i32 s6, s3, s4
+; GFX1030-NEXT: s_cmp_ge_u32 s3, s4
+; GFX1030-NEXT: s_cselect_b32 s2, s5, s2
+; GFX1030-NEXT: s_cselect_b32 s3, s6, s3
+; GFX1030-NEXT: s_add_i32 s5, s2, 1
+; GFX1030-NEXT: s_cmp_ge_u32 s3, s4
+; GFX1030-NEXT: s_cselect_b32 s2, s5, s2
; GFX1030-NEXT: s_and_b32 s2, s2, 0xffffff
; GFX1030-NEXT: v_mov_b32_e32 v1, s2
; GFX1030-NEXT: global_store_dword v0, v1, s[0:1]
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