[llvm] [mlir] [mlir][SPIR-V] Add SPIRVToLLVM conversions for non-trivial elementwise operations (PR #202574)
Arseniy Obolenskiy via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 05:02:11 PDT 2026
https://github.com/aobolensk updated https://github.com/llvm/llvm-project/pull/202574
>From ab9d2c1afcb4d4c9ff46671a51cc9fa007cf738a Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Tue, 9 Jun 2026 12:31:34 +0200
Subject: [PATCH 1/2] [mlir][SPIR-V] Add SPIRVToLLVM conversions for SNegate,
VectorTimesScalar, F/SMod, sign, fract and mix ops
---
.../Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp | 235 +++++++++++++++++-
.../SPIRVToLLVM/arithmetic-ops-to-llvm.mlir | 89 +++++++
.../SPIRVToLLVM/cl-ops-to-llvm.mlir | 20 ++
.../SPIRVToLLVM/gl-ops-to-llvm.mlir | 89 +++++++
4 files changed, 432 insertions(+), 1 deletion(-)
diff --git a/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp b/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
index c43415b27b1b3..6005019b562e9 100644
--- a/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
+++ b/mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp
@@ -118,6 +118,21 @@ static Value createFPConstant(Location loc, Type srcType, Type dstType,
rewriter.getFloatAttr(floatType, value));
}
+/// Creates `llvm.mlir.constant` with an integer scalar or vector value.
+static Value createIntConstant(Location loc, Type srcType, Type dstType,
+ PatternRewriter &rewriter, int64_t value) {
+ if (auto vecType = dyn_cast<VectorType>(srcType)) {
+ auto intType = cast<IntegerType>(vecType.getElementType());
+ return LLVM::ConstantOp::create(
+ rewriter, loc, dstType,
+ SplatElementsAttr::get(vecType,
+ rewriter.getIntegerAttr(intType, value)));
+ }
+ auto intType = cast<IntegerType>(srcType);
+ return LLVM::ConstantOp::create(rewriter, loc, dstType,
+ rewriter.getIntegerAttr(intType, value));
+}
+
/// Utility function for bitfield ops:
/// - `BitFieldInsert`
/// - `BitFieldSExtract`
@@ -921,6 +936,123 @@ class InverseSqrtPattern
}
};
+/// Converts `spirv.SNegate` to `0 - x`.
+class SNegatePattern : public SPIRVToLLVMConversion<spirv::SNegateOp> {
+public:
+ using SPIRVToLLVMConversion<spirv::SNegateOp>::SPIRVToLLVMConversion;
+
+ LogicalResult
+ matchAndRewrite(spirv::SNegateOp op, OpAdaptor adaptor,
+ ConversionPatternRewriter &rewriter) const override {
+ auto srcType = op.getType();
+ auto dstType = getTypeConverter()->convertType(srcType);
+ if (!dstType)
+ return rewriter.notifyMatchFailure(op, "type conversion failed");
+
+ Location loc = op.getLoc();
+ Value zero = createIntConstant(loc, srcType, dstType, rewriter, 0);
+ rewriter.replaceOpWithNewOp<LLVM::SubOp>(op, dstType, zero,
+ adaptor.getOperand());
+ return success();
+ }
+};
+
+/// Converts `spirv.VectorTimesScalar` to a broadcast of the scalar followed by
+/// an `llvm.fmul`.
+class VectorTimesScalarPattern
+ : public SPIRVToLLVMConversion<spirv::VectorTimesScalarOp> {
+public:
+ using SPIRVToLLVMConversion<
+ spirv::VectorTimesScalarOp>::SPIRVToLLVMConversion;
+
+ LogicalResult
+ matchAndRewrite(spirv::VectorTimesScalarOp op, OpAdaptor adaptor,
+ ConversionPatternRewriter &rewriter) const override {
+ auto srcType = op.getType();
+ auto dstType = getTypeConverter()->convertType(srcType);
+ if (!dstType)
+ return rewriter.notifyMatchFailure(op, "type conversion failed");
+
+ unsigned numElements = cast<VectorType>(srcType).getNumElements();
+ Value broadcasted = broadcast(op.getLoc(), adaptor.getScalar(), numElements,
+ *getTypeConverter(), rewriter);
+ rewriter.replaceOpWithNewOp<LLVM::FMulOp>(op, dstType, adaptor.getVector(),
+ broadcasted);
+ return success();
+ }
+};
+
+/// Converts `spirv.FMod` to `x - y * floor(x / y)`. The SPIR-V op requires the
+/// result to take the sign of the divisor, whereas `llvm.frem` keeps the sign
+/// of the dividend, so `frem` cannot be used directly.
+class FModPattern : public SPIRVToLLVMConversion<spirv::FModOp> {
+public:
+ using SPIRVToLLVMConversion<spirv::FModOp>::SPIRVToLLVMConversion;
+
+ LogicalResult
+ matchAndRewrite(spirv::FModOp op, OpAdaptor adaptor,
+ ConversionPatternRewriter &rewriter) const override {
+ auto dstType = getTypeConverter()->convertType(op.getType());
+ if (!dstType)
+ return rewriter.notifyMatchFailure(op, "type conversion failed");
+
+ Location loc = op.getLoc();
+ Value lhs = adaptor.getOperand1();
+ Value rhs = adaptor.getOperand2();
+ Value div = LLVM::FDivOp::create(rewriter, loc, dstType, lhs, rhs);
+ Value floored = LLVM::FFloorOp::create(rewriter, loc, dstType, div);
+ Value scaled = LLVM::FMulOp::create(rewriter, loc, dstType, rhs, floored);
+ rewriter.replaceOpWithNewOp<LLVM::FSubOp>(op, dstType, lhs, scaled);
+ return success();
+ }
+};
+
+/// Converts `spirv.SMod` to a signed remainder corrected to take the sign of
+/// the divisor. `llvm.srem` keeps the sign of the dividend, so the result is
+/// adjusted by adding the divisor when the remainder is non-zero and its sign
+/// differs from the divisor's.
+class SModPattern : public SPIRVToLLVMConversion<spirv::SModOp> {
+public:
+ using SPIRVToLLVMConversion<spirv::SModOp>::SPIRVToLLVMConversion;
+
+ LogicalResult
+ matchAndRewrite(spirv::SModOp op, OpAdaptor adaptor,
+ ConversionPatternRewriter &rewriter) const override {
+ auto srcType = op.getType();
+ auto dstType = getTypeConverter()->convertType(srcType);
+ if (!dstType)
+ return rewriter.notifyMatchFailure(op, "type conversion failed");
+
+ Location loc = op.getLoc();
+ Value lhs = adaptor.getOperand1();
+ Value rhs = adaptor.getOperand2();
+ Type i1Type = rewriter.getI1Type();
+ Type cmpType = isa<VectorType>(srcType)
+ ? cast<Type>(VectorType::get(
+ cast<VectorType>(srcType).getShape(), i1Type))
+ : i1Type;
+
+ Value rem = LLVM::SRemOp::create(rewriter, loc, dstType, lhs, rhs);
+ Value zero = createIntConstant(loc, srcType, dstType, rewriter, 0);
+
+ Value remNonZero = LLVM::ICmpOp::create(rewriter, loc, cmpType,
+ LLVM::ICmpPredicate::ne, rem, zero);
+ Value remNeg = LLVM::ICmpOp::create(rewriter, loc, cmpType,
+ LLVM::ICmpPredicate::slt, rem, zero);
+ Value rhsNeg = LLVM::ICmpOp::create(rewriter, loc, cmpType,
+ LLVM::ICmpPredicate::slt, rhs, zero);
+ Value signMismatch =
+ LLVM::XOrOp::create(rewriter, loc, cmpType, remNeg, rhsNeg);
+ Value needsAdjust =
+ LLVM::AndOp::create(rewriter, loc, cmpType, remNonZero, signMismatch);
+
+ Value adjusted = LLVM::AddOp::create(rewriter, loc, dstType, rem, rhs);
+ rewriter.replaceOpWithNewOp<LLVM::SelectOp>(op, dstType, needsAdjust,
+ adjusted, rem);
+ return success();
+ }
+};
+
/// Converts `spirv.Load` and `spirv.Store` to LLVM dialect.
template <typename SPIRVOp>
class LoadStorePattern : public SPIRVToLLVMConversion<SPIRVOp> {
@@ -1564,6 +1696,102 @@ class SAbsPattern : public SPIRVToLLVMConversion<spirv::GLSAbsOp> {
}
};
+/// Converts `spirv.GL.FSign`/`spirv.GL.SSign` to a `sign(x)` sequence that maps
+/// the operand to -1/0/1 using two comparisons and two selects. The `isFloat`
+/// flag selects between floating-point and integer comparisons/constants.
+template <typename SPIRVOp, bool isFloat>
+class SignPattern : public SPIRVToLLVMConversion<SPIRVOp> {
+public:
+ using SPIRVToLLVMConversion<SPIRVOp>::SPIRVToLLVMConversion;
+
+ LogicalResult
+ matchAndRewrite(SPIRVOp op, typename SPIRVOp::Adaptor adaptor,
+ ConversionPatternRewriter &rewriter) const override {
+ auto srcType = op.getType();
+ auto dstType = this->getTypeConverter()->convertType(srcType);
+ if (!dstType)
+ return rewriter.notifyMatchFailure(op, "type conversion failed");
+
+ Location loc = op.getLoc();
+ Value operand = adaptor.getOperand();
+ Type i1Type = rewriter.getI1Type();
+ Type cmpType = isa<VectorType>(srcType)
+ ? cast<Type>(VectorType::get(
+ cast<VectorType>(srcType).getShape(), i1Type))
+ : i1Type;
+
+ Value zero, one, minusOne, gt, lt;
+ if constexpr (isFloat) {
+ zero = createFPConstant(loc, srcType, dstType, rewriter, 0.0);
+ one = createFPConstant(loc, srcType, dstType, rewriter, 1.0);
+ minusOne = createFPConstant(loc, srcType, dstType, rewriter, -1.0);
+ gt = LLVM::FCmpOp::create(rewriter, loc, cmpType,
+ LLVM::FCmpPredicate::ogt, operand, zero);
+ lt = LLVM::FCmpOp::create(rewriter, loc, cmpType,
+ LLVM::FCmpPredicate::olt, operand, zero);
+ } else {
+ zero = createIntConstant(loc, srcType, dstType, rewriter, 0);
+ one = createIntConstant(loc, srcType, dstType, rewriter, 1);
+ minusOne = createIntConstant(loc, srcType, dstType, rewriter, -1);
+ gt = LLVM::ICmpOp::create(rewriter, loc, cmpType,
+ LLVM::ICmpPredicate::sgt, operand, zero);
+ lt = LLVM::ICmpOp::create(rewriter, loc, cmpType,
+ LLVM::ICmpPredicate::slt, operand, zero);
+ }
+
+ Value negOrZero =
+ LLVM::SelectOp::create(rewriter, loc, dstType, lt, minusOne, zero);
+ rewriter.replaceOpWithNewOp<LLVM::SelectOp>(op, dstType, gt, one,
+ negOrZero);
+ return success();
+ }
+};
+
+/// Converts `spirv.GL.Fract` to `x - floor(x)`.
+class FractPattern : public SPIRVToLLVMConversion<spirv::GLFractOp> {
+public:
+ using SPIRVToLLVMConversion<spirv::GLFractOp>::SPIRVToLLVMConversion;
+
+ LogicalResult
+ matchAndRewrite(spirv::GLFractOp op, OpAdaptor adaptor,
+ ConversionPatternRewriter &rewriter) const override {
+ auto dstType = getTypeConverter()->convertType(op.getType());
+ if (!dstType)
+ return rewriter.notifyMatchFailure(op, "type conversion failed");
+
+ Location loc = op.getLoc();
+ Value operand = adaptor.getOperand();
+ Value floored = LLVM::FFloorOp::create(rewriter, loc, dstType, operand);
+ rewriter.replaceOpWithNewOp<LLVM::FSubOp>(op, dstType, operand, floored);
+ return success();
+ }
+};
+
+/// Converts `spirv.GL.FMix`/`spirv.CL.mix` to `fma(a, y - x, x)`, the linear
+/// blend `x * (1 - a) + y * a`. Operands are taken positionally because the GL
+/// and CL ops name their third operand differently (`a` vs. `z`).
+template <typename SPIRVOp>
+class MixPattern : public SPIRVToLLVMConversion<SPIRVOp> {
+public:
+ using SPIRVToLLVMConversion<SPIRVOp>::SPIRVToLLVMConversion;
+
+ LogicalResult
+ matchAndRewrite(SPIRVOp op, typename SPIRVOp::Adaptor adaptor,
+ ConversionPatternRewriter &rewriter) const override {
+ auto dstType = this->getTypeConverter()->convertType(op.getType());
+ if (!dstType)
+ return rewriter.notifyMatchFailure(op, "type conversion failed");
+
+ Location loc = op.getLoc();
+ Value x = adaptor.getOperands()[0];
+ Value y = adaptor.getOperands()[1];
+ Value a = adaptor.getOperands()[2];
+ Value diff = LLVM::FSubOp::create(rewriter, loc, dstType, y, x);
+ rewriter.replaceOpWithNewOp<LLVM::FMAOp>(op, dstType, a, diff, x);
+ return success();
+ }
+};
+
class VariablePattern : public SPIRVToLLVMConversion<spirv::VariableOp> {
public:
using SPIRVToLLVMConversion<spirv::VariableOp>::SPIRVToLLVMConversion;
@@ -1824,7 +2052,8 @@ void mlir::populateSPIRVToLLVMConversionPatterns(
DirectConversionPattern<spirv::SDivOp, LLVM::SDivOp>,
DirectConversionPattern<spirv::SRemOp, LLVM::SRemOp>,
DirectConversionPattern<spirv::UDivOp, LLVM::UDivOp>,
- DirectConversionPattern<spirv::UModOp, LLVM::URemOp>,
+ DirectConversionPattern<spirv::UModOp, LLVM::URemOp>, SNegatePattern,
+ VectorTimesScalarPattern, FModPattern, SModPattern,
// Bitwise ops
BitFieldInsertPattern, BitFieldUExtractPattern, BitFieldSExtractPattern,
@@ -1917,6 +2146,9 @@ void mlir::populateSPIRVToLLVMConversionPatterns(
DirectConversionPattern<spirv::GLAcosOp, LLVM::ACosOp>,
DirectConversionPattern<spirv::GLAtanOp, LLVM::ATanOp>,
InverseSqrtPattern, SAbsPattern, TanPattern, TanhPattern,
+ SignPattern<spirv::GLFSignOp, /*isFloat=*/true>,
+ SignPattern<spirv::GLSSignOp, /*isFloat=*/false>, FractPattern,
+ MixPattern<spirv::GLFMixOp>,
// OpenCL extended instruction set ops
DirectConversionPattern<spirv::CLCeilOp, LLVM::FCeilOp>,
@@ -1950,6 +2182,7 @@ void mlir::populateSPIRVToLLVMConversionPatterns(
DirectConversionPattern<spirv::CLSMinOp, LLVM::SMinOp>,
DirectConversionPattern<spirv::CLUMaxOp, LLVM::UMaxOp>,
DirectConversionPattern<spirv::CLUMinOp, LLVM::UMinOp>,
+ MixPattern<spirv::CLMixOp>,
// Logical ops
DirectConversionPattern<spirv::LogicalAndOp, LLVM::AndOp>,
diff --git a/mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir b/mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
index dbbf8610afb4d..5e417d7e78a3f 100644
--- a/mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
+++ b/mlir/test/Conversion/SPIRVToLLVM/arithmetic-ops-to-llvm.mlir
@@ -233,3 +233,92 @@ spirv.func @srem_vector(%arg0: vector<4xi32>, %arg1: vector<4xi32>) "None" {
%0 = spirv.SRem %arg0, %arg1 : vector<4xi32>
spirv.Return
}
+
+//===----------------------------------------------------------------------===//
+// spirv.SNegate
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @snegate_scalar
+spirv.func @snegate_scalar(%arg0: i32) "None" {
+ // CHECK: %[[ZERO:.*]] = llvm.mlir.constant(0 : i32) : i32
+ // CHECK: llvm.sub %[[ZERO]], %{{.*}} : i32
+ %0 = spirv.SNegate %arg0 : i32
+ spirv.Return
+}
+
+// CHECK-LABEL: @snegate_vector
+spirv.func @snegate_vector(%arg0: vector<4xi32>) "None" {
+ // CHECK: %[[ZERO:.*]] = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
+ // CHECK: llvm.sub %[[ZERO]], %{{.*}} : vector<4xi32>
+ %0 = spirv.SNegate %arg0 : vector<4xi32>
+ spirv.Return
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.VectorTimesScalar
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @vector_times_scalar
+spirv.func @vector_times_scalar(%vector: vector<4xf32>, %scalar: f32) "None" {
+ // CHECK: %[[UNDEF:.*]] = llvm.mlir.poison : vector<4xf32>
+ // CHECK: llvm.insertelement %{{.*}}, %[[UNDEF]]
+ // CHECK-COUNT-2: llvm.insertelement
+ // CHECK: %[[BCAST:.*]] = llvm.insertelement
+ // CHECK: llvm.fmul %{{.*}}, %[[BCAST]] : vector<4xf32>
+ %0 = spirv.VectorTimesScalar %vector, %scalar : (vector<4xf32>, f32) -> vector<4xf32>
+ spirv.Return
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.FMod
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @fmod_scalar
+spirv.func @fmod_scalar(%arg0: f32, %arg1: f32) "None" {
+ // CHECK: %[[DIV:.*]] = llvm.fdiv %{{.*}}, %{{.*}} : f32
+ // CHECK: %[[FLOOR:.*]] = llvm.intr.floor(%[[DIV]]) : (f32) -> f32
+ // CHECK: %[[MUL:.*]] = llvm.fmul %{{.*}}, %[[FLOOR]] : f32
+ // CHECK: llvm.fsub %{{.*}}, %[[MUL]] : f32
+ %0 = spirv.FMod %arg0, %arg1 : f32
+ spirv.Return
+}
+
+// CHECK-LABEL: @fmod_vector
+spirv.func @fmod_vector(%arg0: vector<4xf32>, %arg1: vector<4xf32>) "None" {
+ // CHECK: %[[DIV:.*]] = llvm.fdiv %{{.*}}, %{{.*}} : vector<4xf32>
+ // CHECK: %[[FLOOR:.*]] = llvm.intr.floor(%[[DIV]]) : (vector<4xf32>) -> vector<4xf32>
+ // CHECK: %[[MUL:.*]] = llvm.fmul %{{.*}}, %[[FLOOR]] : vector<4xf32>
+ // CHECK: llvm.fsub %{{.*}}, %[[MUL]] : vector<4xf32>
+ %0 = spirv.FMod %arg0, %arg1 : vector<4xf32>
+ spirv.Return
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.SMod
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @smod_scalar
+spirv.func @smod_scalar(%arg0: i32, %arg1: i32) "None" {
+ // CHECK: %[[REM:.*]] = llvm.srem %{{.*}}, %{{.*}} : i32
+ // CHECK: %[[ZERO:.*]] = llvm.mlir.constant(0 : i32) : i32
+ // CHECK: %[[NZ:.*]] = llvm.icmp "ne" %[[REM]], %[[ZERO]] : i32
+ // CHECK: %[[RNEG:.*]] = llvm.icmp "slt" %[[REM]], %[[ZERO]] : i32
+ // CHECK: %[[DNEG:.*]] = llvm.icmp "slt" %{{.*}}, %[[ZERO]] : i32
+ // CHECK: %[[XOR:.*]] = llvm.xor %[[RNEG]], %[[DNEG]] : i1
+ // CHECK: %[[ADJ:.*]] = llvm.and %[[NZ]], %[[XOR]] : i1
+ // CHECK: %[[ADD:.*]] = llvm.add %[[REM]], %{{.*}} : i32
+ // CHECK: llvm.select %[[ADJ]], %[[ADD]], %[[REM]] : i1, i32
+ %0 = spirv.SMod %arg0, %arg1 : i32
+ spirv.Return
+}
+
+// CHECK-LABEL: @smod_vector
+spirv.func @smod_vector(%arg0: vector<4xi32>, %arg1: vector<4xi32>) "None" {
+ // CHECK: %[[REM:.*]] = llvm.srem %{{.*}}, %{{.*}} : vector<4xi32>
+ // CHECK: %[[ZERO:.*]] = llvm.mlir.constant(dense<0> : vector<4xi32>) : vector<4xi32>
+ // CHECK: %[[NZ:.*]] = llvm.icmp "ne" %[[REM]], %[[ZERO]] : vector<4xi32>
+ // CHECK: %[[ADD:.*]] = llvm.add %[[REM]], %{{.*}} : vector<4xi32>
+ // CHECK: llvm.select %{{.*}}, %[[ADD]], %[[REM]] : vector<4xi1>, vector<4xi32>
+ %0 = spirv.SMod %arg0, %arg1 : vector<4xi32>
+ spirv.Return
+}
diff --git a/mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir b/mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
index f0568e1035cd9..a986be42a5437 100644
--- a/mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
+++ b/mlir/test/Conversion/SPIRVToLLVM/cl-ops-to-llvm.mlir
@@ -99,3 +99,23 @@ spirv.func @cl_integer(%arg0: i32, %arg1: i32) "None" {
%3 = spirv.CL.u_min %arg0, %arg1 : i32
spirv.Return
}
+
+//===----------------------------------------------------------------------===//
+// spirv.CL.mix
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @mix_scalar
+spirv.func @mix_scalar(%x: f32, %y: f32, %a: f32) "None" {
+ // CHECK: %[[DIFF:.*]] = llvm.fsub %{{.*}}, %{{.*}} : f32
+ // CHECK: llvm.intr.fma(%{{.*}}, %[[DIFF]], %{{.*}}) : (f32, f32, f32) -> f32
+ %0 = spirv.CL.mix %x, %y, %a : f32
+ spirv.Return
+}
+
+// CHECK-LABEL: @mix_vector
+spirv.func @mix_vector(%x: vector<4xf32>, %y: vector<4xf32>, %a: vector<4xf32>) "None" {
+ // CHECK: %[[DIFF:.*]] = llvm.fsub %{{.*}}, %{{.*}} : vector<4xf32>
+ // CHECK: llvm.intr.fma(%{{.*}}, %[[DIFF]], %{{.*}}) : (vector<4xf32>, vector<4xf32>, vector<4xf32>) -> vector<4xf32>
+ %0 = spirv.CL.mix %x, %y, %a : vector<4xf32>
+ spirv.Return
+}
diff --git a/mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir b/mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
index ffa47efbf9213..64b22e751068e 100644
--- a/mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
+++ b/mlir/test/Conversion/SPIRVToLLVM/gl-ops-to-llvm.mlir
@@ -361,3 +361,92 @@ spirv.func @asin_acos_atan(%arg0: f32, %arg1: vector<3xf16>) "None" {
%2 = spirv.GL.Atan %arg0 : f32
spirv.Return
}
+
+//===----------------------------------------------------------------------===//
+// spirv.GL.FSign
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @fsign_scalar
+spirv.func @fsign_scalar(%arg0: f32) "None" {
+ // CHECK: %[[ZERO:.*]] = llvm.mlir.constant(0.000000e+00 : f32) : f32
+ // CHECK: %[[ONE:.*]] = llvm.mlir.constant(1.000000e+00 : f32) : f32
+ // CHECK: %[[MONE:.*]] = llvm.mlir.constant(-1.000000e+00 : f32) : f32
+ // CHECK: %[[GT:.*]] = llvm.fcmp "ogt" %{{.*}}, %[[ZERO]] : f32
+ // CHECK: %[[LT:.*]] = llvm.fcmp "olt" %{{.*}}, %[[ZERO]] : f32
+ // CHECK: %[[SEL0:.*]] = llvm.select %[[LT]], %[[MONE]], %[[ZERO]] : i1, f32
+ // CHECK: llvm.select %[[GT]], %[[ONE]], %[[SEL0]] : i1, f32
+ %0 = spirv.GL.FSign %arg0 : f32
+ spirv.Return
+}
+
+// CHECK-LABEL: @fsign_vector
+spirv.func @fsign_vector(%arg0: vector<4xf32>) "None" {
+ // CHECK: %[[GT:.*]] = llvm.fcmp "ogt" %{{.*}}, %{{.*}} : vector<4xf32>
+ // CHECK: %[[LT:.*]] = llvm.fcmp "olt" %{{.*}}, %{{.*}} : vector<4xf32>
+ // CHECK: %[[SEL0:.*]] = llvm.select %[[LT]], %{{.*}}, %{{.*}} : vector<4xi1>, vector<4xf32>
+ // CHECK: llvm.select %[[GT]], %{{.*}}, %[[SEL0]] : vector<4xi1>, vector<4xf32>
+ %0 = spirv.GL.FSign %arg0 : vector<4xf32>
+ spirv.Return
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.GL.SSign
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @ssign_scalar
+spirv.func @ssign_scalar(%arg0: i32) "None" {
+ // CHECK: %[[ZERO:.*]] = llvm.mlir.constant(0 : i32) : i32
+ // CHECK: %[[ONE:.*]] = llvm.mlir.constant(1 : i32) : i32
+ // CHECK: %[[MONE:.*]] = llvm.mlir.constant(-1 : i32) : i32
+ // CHECK: %[[GT:.*]] = llvm.icmp "sgt" %{{.*}}, %[[ZERO]] : i32
+ // CHECK: %[[LT:.*]] = llvm.icmp "slt" %{{.*}}, %[[ZERO]] : i32
+ // CHECK: %[[SEL0:.*]] = llvm.select %[[LT]], %[[MONE]], %[[ZERO]] : i1, i32
+ // CHECK: llvm.select %[[GT]], %[[ONE]], %[[SEL0]] : i1, i32
+ %0 = spirv.GL.SSign %arg0 : i32
+ spirv.Return
+}
+
+// CHECK-LABEL: @ssign_vector
+spirv.func @ssign_vector(%arg0: vector<4xi32>) "None" {
+ // CHECK: %[[GT:.*]] = llvm.icmp "sgt" %{{.*}}, %{{.*}} : vector<4xi32>
+ // CHECK: %[[LT:.*]] = llvm.icmp "slt" %{{.*}}, %{{.*}} : vector<4xi32>
+ // CHECK: %[[SEL0:.*]] = llvm.select %[[LT]], %{{.*}}, %{{.*}} : vector<4xi1>, vector<4xi32>
+ // CHECK: llvm.select %[[GT]], %{{.*}}, %[[SEL0]] : vector<4xi1>, vector<4xi32>
+ %0 = spirv.GL.SSign %arg0 : vector<4xi32>
+ spirv.Return
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.GL.Fract
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @fract
+spirv.func @fract(%arg0: f32, %arg1: vector<3xf16>) "None" {
+ // CHECK: %[[FLOOR:.*]] = llvm.intr.floor(%{{.*}}) : (f32) -> f32
+ // CHECK: llvm.fsub %{{.*}}, %[[FLOOR]] : f32
+ %0 = spirv.GL.Fract %arg0 : f32
+ // CHECK: %[[FLOORV:.*]] = llvm.intr.floor(%{{.*}}) : (vector<3xf16>) -> vector<3xf16>
+ // CHECK: llvm.fsub %{{.*}}, %[[FLOORV]] : vector<3xf16>
+ %1 = spirv.GL.Fract %arg1 : vector<3xf16>
+ spirv.Return
+}
+
+//===----------------------------------------------------------------------===//
+// spirv.GL.FMix
+//===----------------------------------------------------------------------===//
+
+// CHECK-LABEL: @fmix_scalar
+spirv.func @fmix_scalar(%x: f32, %y: f32, %a: f32) "None" {
+ // CHECK: %[[DIFF:.*]] = llvm.fsub %{{.*}}, %{{.*}} : f32
+ // CHECK: llvm.intr.fma(%{{.*}}, %[[DIFF]], %{{.*}}) : (f32, f32, f32) -> f32
+ %0 = spirv.GL.FMix %x : f32, %y : f32, %a : f32 -> f32
+ spirv.Return
+}
+
+// CHECK-LABEL: @fmix_vector
+spirv.func @fmix_vector(%x: vector<4xf32>, %y: vector<4xf32>, %a: vector<4xf32>) "None" {
+ // CHECK: %[[DIFF:.*]] = llvm.fsub %{{.*}}, %{{.*}} : vector<4xf32>
+ // CHECK: llvm.intr.fma(%{{.*}}, %[[DIFF]], %{{.*}}) : (vector<4xf32>, vector<4xf32>, vector<4xf32>) -> vector<4xf32>
+ %0 = spirv.GL.FMix %x : vector<4xf32>, %y : vector<4xf32>, %a : vector<4xf32> -> vector<4xf32>
+ spirv.Return
+}
>From f7c3cc1dee13e64696a1081f28224b40d029f9eb Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Tue, 9 Jun 2026 14:01:19 +0200
Subject: [PATCH 2/2] [SPIR-V] Fix infinite loop on GEP handling for an empty
struct
---
llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp | 9 ++++-----
.../pointers/getelementptr-empty-struct.ll | 18 ++++++++++++++++++
2 files changed, 22 insertions(+), 5 deletions(-)
create mode 100644 llvm/test/CodeGen/SPIRV/pointers/getelementptr-empty-struct.ll
diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
index 25e5736019806..4a8682bfebc87 100644
--- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
@@ -767,11 +767,10 @@ bool SPIRVEmitIntrinsics::walkLogicalAccessChainDynamic(
// of the struct if the current type is a struct.
// Try to find the first array type that is at offset 0 in the struct.
while (auto *ST = dyn_cast<StructType>(CurType)) {
- if (ST->getNumElements() > 0) {
- CurType = ST->getElementType(0);
- OnLiteralIndexing(CurType, 0);
- continue;
- }
+ if (ST->getNumElements() == 0)
+ break;
+ CurType = ST->getElementType(0);
+ OnLiteralIndexing(CurType, 0);
}
assert(CurType);
diff --git a/llvm/test/CodeGen/SPIRV/pointers/getelementptr-empty-struct.ll b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-empty-struct.ll
new file mode 100644
index 0000000000000..ec8fa7209a9f4
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/pointers/getelementptr-empty-struct.ll
@@ -0,0 +1,18 @@
+; RUN: llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv1.6-unknown-vulkan1.3-compute %s -o - -filetype=obj | spirv-val --target-env vulkan1.3 %}
+
+; CHECK: OpFunction
+
+%empty = type {}
+
+ at global = internal addrspace(10) global %empty zeroinitializer
+ at in_idx = internal addrspace(10) global i32 zeroinitializer
+
+define void @main() #0 {
+entry:
+ %idx = load i32, ptr addrspace(10) @in_idx
+ %gep = getelementptr inbounds i8, ptr addrspace(10) @global, i32 %idx
+ ret void
+}
+
+attributes #0 = { "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" }
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