[llvm] [AMDGPU] Add post-RA peephole to fuse v_lshlrev_b32 + v_or_b32 into v_lshl_or_b32 (PR #202585)

[Jay Foad via llvm-commits]

jayfoad wrote:

One possibility for implementing this is to have an S_LSHL_OR_pseudo instruction which is either promoted to V_LSHL_OR by SIFixSGPRCopies or expanded into separate S_LSHL and S_OR instructions.

https://github.com/llvm/llvm-project/pull/202585