[llvm] [RISCV] Set CostPerUse to 1 only when optimizing for size (PR #201501)
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llvm-commits at lists.llvm.org
Wed Jun 3 21:00:35 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Pengcheng Wang (wangpc-pp)
<details>
<summary>Changes</summary>
We saw some regressions because of bad RAs as the cost of registers
beyond x8-x15 are bigger. This is why `DisableCostPerUse` was added
in https://github.com/llvm/llvm-project/issues/83320.
In this PR, we change it to set `CostPerUse=1` only when optimizing
for size.
Code size increases less than 0.1% in llvm-test-suite.
---
Patch is 478.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/201501.diff
17 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp (+4-1)
- (modified) llvm/test/CodeGen/RISCV/add-before-shl.ll (+11-11)
- (modified) llvm/test/CodeGen/RISCV/callee-saved-gprs.ll (+228-228)
- (modified) llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll (+23-23)
- (modified) llvm/test/CodeGen/RISCV/machine-pipeliner.ll (+17-17)
- (modified) llvm/test/CodeGen/RISCV/nontemporal.ll (+380-380)
- (modified) llvm/test/CodeGen/RISCV/push-pop-popret.ll (+600-600)
- (modified) llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll (+384-392)
- (modified) llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll (+600-600)
- (modified) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll (+204-212)
- (modified) llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll (+790-790)
- (modified) llvm/test/CodeGen/RISCV/rvv/pr95865.ll (+54-54)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll (+107-107)
- (modified) llvm/test/CodeGen/RISCV/select-cc.ll (+6-6)
- (modified) llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll (+228-228)
- (modified) llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll (+872-872)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 634f81fa18c53..25a416f06ac90 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -906,7 +906,10 @@ void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
unsigned
RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
- return MF.getSubtarget<RISCVSubtarget>().hasStdExtZca() && !DisableCostPerUse
+ // Set CostPerUse to 1 only when optimizing for size and RVC exists.
+ return MF.getFunction().hasOptSize() &&
+ MF.getSubtarget<RISCVSubtarget>().hasStdExtZca() &&
+ !DisableCostPerUse
? 1
: 0;
}
diff --git a/llvm/test/CodeGen/RISCV/add-before-shl.ll b/llvm/test/CodeGen/RISCV/add-before-shl.ll
index 35a39b89a2cb7..1edab031c86f8 100644
--- a/llvm/test/CodeGen/RISCV/add-before-shl.ll
+++ b/llvm/test/CodeGen/RISCV/add-before-shl.ll
@@ -201,23 +201,23 @@ define i128 @add_wide_operand(i128 %a) nounwind {
; RV32C-LABEL: add_wide_operand:
; RV32C: # %bb.0:
; RV32C-NEXT: c.lw a2, 0(a1)
-; RV32C-NEXT: c.lw a4, 12(a1)
-; RV32C-NEXT: c.lw a3, 4(a1)
+; RV32C-NEXT: c.lw a3, 12(a1)
+; RV32C-NEXT: c.lw a4, 4(a1)
; RV32C-NEXT: c.lw a1, 8(a1)
; RV32C-NEXT: c.lui a5, 16
-; RV32C-NEXT: add a6, a4, a5
+; RV32C-NEXT: c.add a3, a5
; RV32C-NEXT: srli a5, a2, 29
-; RV32C-NEXT: slli a4, a3, 3
-; RV32C-NEXT: c.or a4, a5
-; RV32C-NEXT: srli a5, a1, 29
-; RV32C-NEXT: c.srli a3, 29
+; RV32C-NEXT: slli a6, a4, 3
+; RV32C-NEXT: or a5, a6, a5
+; RV32C-NEXT: srli a6, a1, 29
+; RV32C-NEXT: c.srli a4, 29
; RV32C-NEXT: c.slli a1, 3
; RV32C-NEXT: c.slli a2, 3
-; RV32C-NEXT: c.slli a6, 3
-; RV32C-NEXT: c.or a1, a3
-; RV32C-NEXT: or a3, a6, a5
+; RV32C-NEXT: c.slli a3, 3
+; RV32C-NEXT: c.or a1, a4
+; RV32C-NEXT: or a3, a3, a6
; RV32C-NEXT: c.sw a2, 0(a0)
-; RV32C-NEXT: c.sw a4, 4(a0)
+; RV32C-NEXT: c.sw a5, 4(a0)
; RV32C-NEXT: c.sw a1, 8(a0)
; RV32C-NEXT: c.sw a3, 12(a0)
; RV32C-NEXT: c.jr ra
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
index 4e5d175e0ee12..b6b174b8d5a69 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
@@ -448,60 +448,60 @@ define void @callee() {
; RV32IZCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; RV32IZCMP-NEXT: lw a1, 16(a0)
; RV32IZCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw t3, 20(a0)
-; RV32IZCMP-NEXT: lw t4, 24(a0)
-; RV32IZCMP-NEXT: lw t5, 28(a0)
-; RV32IZCMP-NEXT: lw t6, 32(a0)
-; RV32IZCMP-NEXT: lw s2, 36(a0)
-; RV32IZCMP-NEXT: lw s3, 40(a0)
-; RV32IZCMP-NEXT: lw s4, 44(a0)
-; RV32IZCMP-NEXT: lw s5, 48(a0)
-; RV32IZCMP-NEXT: lw s6, 52(a0)
-; RV32IZCMP-NEXT: lw s7, 56(a0)
-; RV32IZCMP-NEXT: lw s8, 60(a0)
-; RV32IZCMP-NEXT: lw s9, 64(a0)
-; RV32IZCMP-NEXT: lw s10, 68(a0)
-; RV32IZCMP-NEXT: lw s11, 72(a0)
-; RV32IZCMP-NEXT: lw ra, 76(a0)
-; RV32IZCMP-NEXT: lw t2, 80(a0)
-; RV32IZCMP-NEXT: lw s0, 84(a0)
-; RV32IZCMP-NEXT: lw s1, 88(a0)
-; RV32IZCMP-NEXT: lw t1, 92(a0)
-; RV32IZCMP-NEXT: lw t0, 112(a0)
-; RV32IZCMP-NEXT: lw a5, 116(a0)
-; RV32IZCMP-NEXT: lw a3, 120(a0)
+; RV32IZCMP-NEXT: lw a6, 20(a0)
+; RV32IZCMP-NEXT: lw a7, 24(a0)
+; RV32IZCMP-NEXT: lw t0, 28(a0)
+; RV32IZCMP-NEXT: lw t1, 32(a0)
+; RV32IZCMP-NEXT: lw t2, 36(a0)
+; RV32IZCMP-NEXT: lw t3, 40(a0)
+; RV32IZCMP-NEXT: lw t4, 44(a0)
+; RV32IZCMP-NEXT: lw t5, 48(a0)
+; RV32IZCMP-NEXT: lw t6, 52(a0)
+; RV32IZCMP-NEXT: lw s0, 56(a0)
+; RV32IZCMP-NEXT: lw s1, 60(a0)
+; RV32IZCMP-NEXT: lw s2, 64(a0)
+; RV32IZCMP-NEXT: lw s3, 68(a0)
+; RV32IZCMP-NEXT: lw s4, 72(a0)
+; RV32IZCMP-NEXT: lw s5, 76(a0)
+; RV32IZCMP-NEXT: lw s6, 80(a0)
+; RV32IZCMP-NEXT: lw s7, 84(a0)
+; RV32IZCMP-NEXT: lw s8, 88(a0)
+; RV32IZCMP-NEXT: lw s9, 92(a0)
+; RV32IZCMP-NEXT: lw s10, 112(a0)
+; RV32IZCMP-NEXT: lw s11, 116(a0)
+; RV32IZCMP-NEXT: lw ra, 120(a0)
; RV32IZCMP-NEXT: lw a1, 124(a0)
-; RV32IZCMP-NEXT: lw a7, 96(a0)
-; RV32IZCMP-NEXT: lw a6, 100(a0)
-; RV32IZCMP-NEXT: lw a4, 104(a0)
+; RV32IZCMP-NEXT: lw a5, 96(a0)
+; RV32IZCMP-NEXT: lw a4, 100(a0)
+; RV32IZCMP-NEXT: lw a3, 104(a0)
; RV32IZCMP-NEXT: lw a2, 108(a0)
; RV32IZCMP-NEXT: sw a1, 124(a0)
-; RV32IZCMP-NEXT: sw a3, 120(a0)
-; RV32IZCMP-NEXT: sw a5, 116(a0)
-; RV32IZCMP-NEXT: sw t0, 112(a0)
+; RV32IZCMP-NEXT: sw ra, 120(a0)
+; RV32IZCMP-NEXT: sw s11, 116(a0)
+; RV32IZCMP-NEXT: sw s10, 112(a0)
; RV32IZCMP-NEXT: sw a2, 108(a0)
-; RV32IZCMP-NEXT: sw a4, 104(a0)
-; RV32IZCMP-NEXT: sw a6, 100(a0)
-; RV32IZCMP-NEXT: sw a7, 96(a0)
-; RV32IZCMP-NEXT: sw t1, 92(a0)
-; RV32IZCMP-NEXT: sw s1, 88(a0)
-; RV32IZCMP-NEXT: sw s0, 84(a0)
-; RV32IZCMP-NEXT: sw t2, 80(a0)
-; RV32IZCMP-NEXT: sw ra, 76(a0)
-; RV32IZCMP-NEXT: sw s11, 72(a0)
-; RV32IZCMP-NEXT: sw s10, 68(a0)
-; RV32IZCMP-NEXT: sw s9, 64(a0)
-; RV32IZCMP-NEXT: sw s8, 60(a0)
-; RV32IZCMP-NEXT: sw s7, 56(a0)
-; RV32IZCMP-NEXT: sw s6, 52(a0)
-; RV32IZCMP-NEXT: sw s5, 48(a0)
-; RV32IZCMP-NEXT: sw s4, 44(a0)
-; RV32IZCMP-NEXT: sw s3, 40(a0)
-; RV32IZCMP-NEXT: sw s2, 36(a0)
-; RV32IZCMP-NEXT: sw t6, 32(a0)
-; RV32IZCMP-NEXT: sw t5, 28(a0)
-; RV32IZCMP-NEXT: sw t4, 24(a0)
-; RV32IZCMP-NEXT: sw t3, 20(a0)
+; RV32IZCMP-NEXT: sw a3, 104(a0)
+; RV32IZCMP-NEXT: sw a4, 100(a0)
+; RV32IZCMP-NEXT: sw a5, 96(a0)
+; RV32IZCMP-NEXT: sw s9, 92(a0)
+; RV32IZCMP-NEXT: sw s8, 88(a0)
+; RV32IZCMP-NEXT: sw s7, 84(a0)
+; RV32IZCMP-NEXT: sw s6, 80(a0)
+; RV32IZCMP-NEXT: sw s5, 76(a0)
+; RV32IZCMP-NEXT: sw s4, 72(a0)
+; RV32IZCMP-NEXT: sw s3, 68(a0)
+; RV32IZCMP-NEXT: sw s2, 64(a0)
+; RV32IZCMP-NEXT: sw s1, 60(a0)
+; RV32IZCMP-NEXT: sw s0, 56(a0)
+; RV32IZCMP-NEXT: sw t6, 52(a0)
+; RV32IZCMP-NEXT: sw t5, 48(a0)
+; RV32IZCMP-NEXT: sw t4, 44(a0)
+; RV32IZCMP-NEXT: sw t3, 40(a0)
+; RV32IZCMP-NEXT: sw t2, 36(a0)
+; RV32IZCMP-NEXT: sw t1, 32(a0)
+; RV32IZCMP-NEXT: sw t0, 28(a0)
+; RV32IZCMP-NEXT: sw a7, 24(a0)
+; RV32IZCMP-NEXT: sw a6, 20(a0)
; RV32IZCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; RV32IZCMP-NEXT: sw a1, 16(a0)
; RV32IZCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -560,58 +560,58 @@ define void @callee() {
; RV32IZCMP-WITH-FP-NEXT: sw a1, -72(s0) # 4-byte Folded Spill
; RV32IZCMP-WITH-FP-NEXT: lw a1, 20(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a1, -76(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw t4, 24(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t5, 28(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t6, 32(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s2, 36(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s3, 40(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s4, 44(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s5, 48(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s6, 52(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s7, 56(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s8, 60(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s9, 64(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s10, 68(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s11, 72(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw ra, 76(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s1, 80(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t3, 84(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t2, 88(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t1, 92(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t0, 112(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw a6, 116(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a7, 24(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t0, 28(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t1, 32(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t2, 36(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t3, 40(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t4, 44(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t5, 48(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t6, 52(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s1, 56(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s2, 60(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s3, 64(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s4, 68(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s5, 72(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s6, 76(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s7, 80(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s8, 84(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s9, 88(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s10, 92(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s11, 112(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw ra, 116(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a4, 120(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a1, 124(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw a7, 96(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a6, 96(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a5, 100(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a3, 104(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a2, 108(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a1, 124(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a4, 120(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw a6, 116(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t0, 112(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw ra, 116(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s11, 112(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a2, 108(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a3, 104(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a5, 100(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw a7, 96(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t1, 92(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t2, 88(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t3, 84(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s1, 80(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw ra, 76(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s11, 72(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s10, 68(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s9, 64(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s8, 60(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s7, 56(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s6, 52(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s5, 48(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s4, 44(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s3, 40(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s2, 36(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t6, 32(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t5, 28(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t4, 24(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a6, 96(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s10, 92(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s9, 88(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s8, 84(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s7, 80(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s6, 76(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s5, 72(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s4, 68(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s3, 64(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s2, 60(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s1, 56(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t6, 52(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t5, 48(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t4, 44(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t3, 40(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t2, 36(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t1, 32(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t0, 28(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a7, 24(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a1, -76(s0) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: sw a1, 20(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a1, -72(s0) # 4-byte Folded Reload
@@ -1057,60 +1057,60 @@ define void @callee() {
; RV64IZCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
; RV64IZCMP-NEXT: lw a1, 16(a0)
; RV64IZCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw t3, 20(a0)
-; RV64IZCMP-NEXT: lw t4, 24(a0)
-; RV64IZCMP-NEXT: lw t5, 28(a0)
-; RV64IZCMP-NEXT: lw t6, 32(a0)
-; RV64IZCMP-NEXT: lw s2, 36(a0)
-; RV64IZCMP-NEXT: lw s3, 40(a0)
-; RV64IZCMP-NEXT: lw s4, 44(a0)
-; RV64IZCMP-NEXT: lw s5, 48(a0)
-; RV64IZCMP-NEXT: lw s6, 52(a0)
-; RV64IZCMP-NEXT: lw s7, 56(a0)
-; RV64IZCMP-NEXT: lw s8, 60(a0)
-; RV64IZCMP-NEXT: lw s9, 64(a0)
-; RV64IZCMP-NEXT: lw s10, 68(a0)
-; RV64IZCMP-NEXT: lw s11, 72(a0)
-; RV64IZCMP-NEXT: lw ra, 76(a0)
-; RV64IZCMP-NEXT: lw t2, 80(a0)
-; RV64IZCMP-NEXT: lw s0, 84(a0)
-; RV64IZCMP-NEXT: lw s1, 88(a0)
-; RV64IZCMP-NEXT: lw t1, 92(a0)
-; RV64IZCMP-NEXT: lw t0, 112(a0)
-; RV64IZCMP-NEXT: lw a5, 116(a0)
-; RV64IZCMP-NEXT: lw a3, 120(a0)
+; RV64IZCMP-NEXT: lw a6, 20(a0)
+; RV64IZCMP-NEXT: lw a7, 24(a0)
+; RV64IZCMP-NEXT: lw t0, 28(a0)
+; RV64IZCMP-NEXT: lw t1, 32(a0)
+; RV64IZCMP-NEXT: lw t2, 36(a0)
+; RV64IZCMP-NEXT: lw t3, 40(a0)
+; RV64IZCMP-NEXT: lw t4, 44(a0)
+; RV64IZCMP-NEXT: lw t5, 48(a0)
+; RV64IZCMP-NEXT: lw t6, 52(a0)
+; RV64IZCMP-NEXT: lw s0, 56(a0)
+; RV64IZCMP-NEXT: lw s1, 60(a0)
+; RV64IZCMP-NEXT: lw s2, 64(a0)
+; RV64IZCMP-NEXT: lw s3, 68(a0)
+; RV64IZCMP-NEXT: lw s4, 72(a0)
+; RV64IZCMP-NEXT: lw s5, 76(a0)
+; RV64IZCMP-NEXT: lw s6, 80(a0)
+; RV64IZCMP-NEXT: lw s7, 84(a0)
+; RV64IZCMP-NEXT: lw s8, 88(a0)
+; RV64IZCMP-NEXT: lw s9, 92(a0)
+; RV64IZCMP-NEXT: lw s10, 112(a0)
+; RV64IZCMP-NEXT: lw s11, 116(a0)
+; RV64IZCMP-NEXT: lw ra, 120(a0)
; RV64IZCMP-NEXT: lw a1, 124(a0)
-; RV64IZCMP-NEXT: lw a7, 96(a0)
-; RV64IZCMP-NEXT: lw a6, 100(a0)
-; RV64IZCMP-NEXT: lw a4, 104(a0)
+; RV64IZCMP-NEXT: lw a5, 96(a0)
+; RV64IZCMP-NEXT: lw a4, 100(a0)
+; RV64IZCMP-NEXT: lw a3, 104(a0)
; RV64IZCMP-NEXT: lw a2, 108(a0)
; RV64IZCMP-NEXT: sw a1, 124(a0)
-; RV64IZCMP-NEXT: sw a3, 120(a0)
-; RV64IZCMP-NEXT: sw a5, 116(a0)
-; RV64IZCMP-NEXT: sw t0, 112(a0)
+; RV64IZCMP-NEXT: sw ra, 120(a0)
+; RV64IZCMP-NEXT: sw s11, 116(a0)
+; RV64IZCMP-NEXT: sw s10, 112(a0)
; RV64IZCMP-NEXT: sw a2, 108(a0)
-; RV64IZCMP-NEXT: sw a4, 104(a0)
-; RV64IZCMP-NEXT: sw a6, 100(a0)
-; RV64IZCMP-NEXT: sw a7, 96(a0)
-; RV64IZCMP-NEXT: sw t1, 92(a0)
-; RV64IZCMP-NEXT: sw s1, 88(a0)
-; RV64IZCMP-NEXT: sw s0, 84(a0)
-; RV64IZCMP-NEXT: sw t2, 80(a0)
-; RV64IZCMP-NEXT: sw ra, 76(a0)
-; RV64IZCMP-NEXT: sw s11, 72(a0)
-; RV64IZCMP-NEXT: sw s10, 68(a0)
-; RV64IZCMP-NEXT: sw s9, 64(a0)
-; RV64IZCMP-NEXT: sw s8, 60(a0)
-; RV64IZCMP-NEXT: sw s7, 56(a0)
-; RV64IZCMP-NEXT: sw s6, 52(a0)
-; RV64IZCMP-NEXT: sw s5, 48(a0)
-; RV64IZCMP-NEXT: sw s4, 44(a0)
-; RV64IZCMP-NEXT: sw s3, 40(a0)
-; RV64IZCMP-NEXT: sw s2, 36(a0)
-; RV64IZCMP-NEXT: sw t6, 32(a0)
-; RV64IZCMP-NEXT: sw t5, 28(a0)
-; RV64IZCMP-NEXT: sw t4, 24(a0)
-; RV64IZCMP-NEXT: sw t3, 20(a0)
+; RV64IZCMP-NEXT: sw a3, 104(a0)
+; RV64IZCMP-NEXT: sw a4, 100(a0)
+; RV64IZCMP-NEXT: sw a5, 96(a0)
+; RV64IZCMP-NEXT: sw s9, 92(a0)
+; RV64IZCMP-NEXT: sw s8, 88(a0)
+; RV64IZCMP-NEXT: sw s7, 84(a0)
+; RV64IZCMP-NEXT: sw s6, 80(a0)
+; RV64IZCMP-NEXT: sw s5, 76(a0)
+; RV64IZCMP-NEXT: sw s4, 72(a0)
+; RV64IZCMP-NEXT: sw s3, 68(a0)
+; RV64IZCMP-NEXT: sw s2, 64(a0)
+; RV64IZCMP-NEXT: sw s1, 60(a0)
+; RV64IZCMP-NEXT: sw s0, 56(a0)
+; RV64IZCMP-NEXT: sw t6, 52(a0)
+; RV64IZCMP-NEXT: sw t5, 48(a0)
+; RV64IZCMP-NEXT: sw t4, 44(a0)
+; RV64IZCMP-NEXT: sw t3, 40(a0)
+; RV64IZCMP-NEXT: sw t2, 36(a0)
+; RV64IZCMP-NEXT: sw t1, 32(a0)
+; RV64IZCMP-NEXT: sw t0, 28(a0)
+; RV64IZCMP-NEXT: sw a7, 24(a0)
+; RV64IZCMP-NEXT: sw a6, 20(a0)
; RV64IZCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-NEXT: sw a1, 16(a0)
; RV64IZCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
@@ -1169,58 +1169,58 @@ define void @callee() {
; RV64IZCMP-WITH-FP-NEXT: sd a1, -144(s0) # 8-byte Folded Spill
; RV64IZCMP-WITH-FP-NEXT: lw a1, 20(a0)
; RV64IZCMP-WITH-FP-NEXT: sd a1, -152(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw t4, 24(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t5, 28(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t6, 32(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s2, 36(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s3, 40(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s4, 44(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s5, 48(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s6, 52(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s7, 56(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s8, 60(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s9, 64(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s10, 68(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s11, 72(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw ra, 76(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s1, 80(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t3, 84(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t2, 88(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t1, 92(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t0, 112(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw a6, 116(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a7, 24(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t0, 28(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t1, 32(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t2, 36(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t3, 40(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t4, 44(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t5, 48(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t6, 52(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s1, 56(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s2, 60(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s3, 64(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s4, 68(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s5, 72(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s6, 76(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s7, 80(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s8, 84(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s9, 88(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s10, 92(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s11, 112(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw ra, 116(a0)
; RV64IZCMP-WITH-FP-NEXT: lw a4, 120(a0)
; RV64IZCMP-WITH-FP-NEXT: lw a1, 124(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw a7, 96(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a6, 96(a0)
; RV64IZCMP-WITH-FP-NEXT: lw a5, 100(a0)
; RV64IZCMP-WITH-FP-NEXT: lw a3, 104(a0)
; RV64IZCMP-WITH-FP-NEXT: lw a2, 108(a0)
; RV64IZCMP-WITH-FP-NEXT: sw a1, 124(a0)
; RV64IZCMP-WITH-FP-NEXT: sw a4, 120(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw a6, 116(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t0, 112(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw ra, 116(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s11, 112(a0)
; RV64IZCMP-WITH-FP-NEXT: sw a2, 108(a0)
; RV64IZCMP-WITH-FP-NEXT: sw a3, 104(a0)
; RV64IZCMP-WITH-FP-NEXT: sw a5, 100(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw a7, 96(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t1, 92(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t2, 88(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t3, 84(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s1, 80(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw ra, 76(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s11, 72(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s10, 68(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s9, 64(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s8, 60(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s7, 56(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s6, 52(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s5, 48(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s4, 44(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s3, 40(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s2, 36(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t6, 32(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t5, 28(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t4, 24(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a6, 96(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s10, 92(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s9, 88(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s8, 84(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s7, 80(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s6, 76(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s5, 72(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s4, 68(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s3, 64(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s2, 60(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s1, 56(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t6, 52(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t5, 48(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t4, 44(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t3, 40(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t2, 36(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t1, 32(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t0, 28(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a7, 24(a0)
; RV64IZCMP-WITH-FP-NEXT: ld a1, -152(s0) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: sw a1, 20(a0)
; RV64IZCMP-WITH-FP-NEXT: ld a1, -144(s0) # 8-byte Folded Reload
@@ -2228,29 +2228,29 @@ define void @caller() {
; RV32IZCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; RV32IZCMP-NEXT: lw a0, 80(s0)
; RV32IZCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw s1, 84(s0)
-; RV32IZCMP-NEXT: lw s2, 88(s0)
-; RV32IZCMP-NEXT: lw s3, 92(s0)
-; RV32IZCMP-NEXT: lw s4, 96(s0)
-; RV32IZCMP-NEXT: lw s5, 100(s0)
-; RV32IZCMP-NEXT: lw s6, 104(s0)
-; RV32IZCMP-NEXT: lw s7, 108(s0)
-; RV32IZCMP-NEXT: lw s8, 112(s0)
-; RV32IZCMP-NEXT: lw s9, 116(s0)
-; RV32IZCMP-NEXT: lw s10, 120(s0)
-; RV32IZCMP-NEXT: lw s11, 124(s0)
+; RV32IZCMP-NEXT: lw s11, 84(s0)
+; RV32IZCMP-NEXT: lw s1,...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/201501
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