[llvm] [RISCV] Set CostPerUse to 1 only when optimizing for size (PR #201501)

[Pengcheng Wang via llvm-commits]

================
@@ -1893,98 +1893,90 @@ define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) {
 ;
 ; RVA22U64-LABEL: buildvec_v16i8_loads_gather:
 ; RVA22U64:       # %bb.0:
-; RVA22U64-NEXT:    lbu a7, 0(a0)
+; RVA22U64-NEXT:    lbu a1, 0(a0)
 ; RVA22U64-NEXT:    lbu a2, 1(a0)
 ; RVA22U64-NEXT:    lbu a3, 22(a0)
 ; RVA22U64-NEXT:    lbu a4, 31(a0)
-; RVA22U64-NEXT:    lbu a6, 623(a0)
-; RVA22U64-NEXT:    lbu a5, 44(a0)
-; RVA22U64-NEXT:    lbu a1, 55(a0)
+; RVA22U64-NEXT:    lbu a5, 623(a0)
+; RVA22U64-NEXT:    lbu a6, 44(a0)
+; RVA22U64-NEXT:    lbu a7, 55(a0)
 ; RVA22U64-NEXT:    lbu t0, 75(a0)
 ; RVA22U64-NEXT:    lbu t1, 82(a0)
 ; RVA22U64-NEXT:    slli a2, a2, 8
 ; RVA22U64-NEXT:    slli a3, a3, 16
 ; RVA22U64-NEXT:    slli a4, a4, 24
-; RVA22U64-NEXT:    slli a5, a5, 32
-; RVA22U64-NEXT:    slli a1, a1, 40
-; RVA22U64-NEXT:    or a7, a7, a2
-; RVA22U64-NEXT:    or t3, a4, a3
-; RVA22U64-NEXT:    or t2, a1, a5
+; RVA22U64-NEXT:    slli a6, a6, 32
+; RVA22U64-NEXT:    slli a7, a7, 40
+; RVA22U64-NEXT:    or a1, a1, a2
+; RVA22U64-NEXT:    or a3, a3, a4
+; RVA22U64-NEXT:    or a2, a7, a6
 ; RVA22U64-NEXT:    lbu a4, 93(a0)
-; RVA22U64-NEXT:    lbu t4, 105(a0)
-; RVA22U64-NEXT:    lbu a2, 124(a0)
-; RVA22U64-NEXT:    lbu t5, 144(a0)
-; RVA22U64-NEXT:    slli a6, a6, 48
+; RVA22U64-NEXT:    lbu a6, 105(a0)
+; RVA22U64-NEXT:    lbu a7, 124(a0)
+; RVA22U64-NEXT:    lbu t2, 144(a0)
+; RVA22U64-NEXT:    slli a5, a5, 48
 ; RVA22U64-NEXT:    slli t0, t0, 56
 ; RVA22U64-NEXT:    slli a4, a4, 8
-; RVA22U64-NEXT:    or a3, t0, a6
+; RVA22U64-NEXT:    or a5, t0, a5
 ; RVA22U64-NEXT:    or a4, t1, a4
-; RVA22U64-NEXT:    lbu a5, 161(a0)
-; RVA22U64-NEXT:    lbu a1, 154(a0)
+; RVA22U64-NEXT:    lbu t0, 161(a0)
+; RVA22U64-NEXT:    lbu t1, 154(a0)
 ; RVA22U64-NEXT:    lbu a0, 163(a0)
-; RVA22U64-NEXT:    slli t4, t4, 16
-; RVA22U64-NEXT:    slli a5, a5, 24
-; RVA22U64-NEXT:    or a5, a5, t4
-; RVA22U64-NEXT:    slli a2, a2, 32
+; RVA22U64-NEXT:    slli a6, a6, 16
+; RVA22U64-NEXT:    slli t0, t0, 24
+; RVA22U64-NEXT:    or a6, t0, a6
+; RVA22U64-NEXT:    slli a7, a7, 32
 ; RVA22U64-NEXT:    slli a0, a0, 40
-; RVA22U64-NEXT:    or a0, a0, a2
-; RVA22U64-NEXT:    slli t5, t5, 48
-; RVA22U64-NEXT:    slli a1, a1, 56
-; RVA22U64-NEXT:    or a1, a1, t5
-; RVA22U64-NEXT:    or a2, a7, t3
-; RVA22U64-NEXT:    or a3, a3, t2
-; RVA22U64-NEXT:    or a4, a4, a5
-; RVA22U64-NEXT:    or a0, a0, a1
-; RVA22U64-NEXT:    or a2, a2, a3
-; RVA22U64-NEXT:    or a0, a0, a4
+; RVA22U64-NEXT:    or a0, a0, a7
+; RVA22U64-NEXT:    slli t2, t2, 48
+; RVA22U64-NEXT:    slli t1, t1, 56
+; RVA22U64-NEXT:    or a7, t1, t2
+; RVA22U64-NEXT:    or a1, a1, a3
+; RVA22U64-NEXT:    or a2, a2, a5
+; RVA22U64-NEXT:    or a3, a4, a6
+; RVA22U64-NEXT:    or a0, a7, a0
+; RVA22U64-NEXT:    or a1, a1, a2
+; RVA22U64-NEXT:    or a0, a0, a3
 ; RVA22U64-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; RVA22U64-NEXT:    vmv.v.x v8, a2
+; RVA22U64-NEXT:    vmv.v.x v8, a1
 ; RVA22U64-NEXT:    vslide1down.vx v8, v8, a0
 ; RVA22U64-NEXT:    ret
 ;
 ; RVA22U64-PACK-LABEL: buildvec_v16i8_loads_gather:
 ; RVA22U64-PACK:       # %bb.0:
-; RVA22U64-PACK-NEXT:    addi sp, sp, -16
----------------
wangpc-pp wrote:

Small improvement.

https://github.com/llvm/llvm-project/pull/201501