[llvm] [RISCV] Set CostPerUse to 1 only when optimizing for size (PR #201501)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 3 21:00:00 PDT 2026
https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/201501
We saw some regressions because of bad RAs as the cost of registers
beyond x8-x15 are bigger. This is why `DisableCostPerUse` was added
in https://github.com/llvm/llvm-project/issues/83320.
In this PR, we change it to set `CostPerUse=1` only when optimizing
for size.
Code size increases less than 0.1% in llvm-test-suite.
>From 68c086f1d8fd613743102fd72afd1eca07fb40b0 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Thu, 4 Jun 2026 11:49:17 +0800
Subject: [PATCH] [RISCV] Set CostPerUse to 1 only when optimizing for size
We saw some regressions because of bad RAs as the cost of registers
beyond x8-x15 are bigger. This is why `DisableCostPerUse` was added
in https://github.com/llvm/llvm-project/issues/83320.
In this PR, we change it to set `CostPerUse=1` only when optimizing
for size.
Code size increases less than 0.1% in llvm-test-suite.
---
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 5 +-
llvm/test/CodeGen/RISCV/add-before-shl.ll | 22 +-
llvm/test/CodeGen/RISCV/callee-saved-gprs.ll | 456 ++---
.../test/CodeGen/RISCV/fold-addi-loadstore.ll | 46 +-
llvm/test/CodeGen/RISCV/machine-pipeliner.ll | 34 +-
llvm/test/CodeGen/RISCV/nontemporal.ll | 760 +++----
llvm/test/CodeGen/RISCV/push-pop-popret.ll | 1200 ++++++------
.../CodeGen/RISCV/qci-interrupt-attr-fpr.ll | 776 ++++----
llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll | 1200 ++++++------
.../RISCV/rvv/fixed-vectors-int-buildvec.ll | 416 ++--
.../RISCV/rvv/nontemporal-vp-scalable.ll | 1580 +++++++--------
llvm/test/CodeGen/RISCV/rvv/pr95865.ll | 108 +-
.../RISCV/rvv/vsetvli-insert-crossbb.ll | 12 +-
.../RISCV/rvv/vxrm-insert-out-of-loop.ll | 214 +-
llvm/test/CodeGen/RISCV/select-cc.ll | 12 +-
.../CodeGen/RISCV/xqccmp-callee-saved-gprs.ll | 456 ++---
.../CodeGen/RISCV/xqccmp-push-pop-popret.ll | 1744 ++++++++---------
17 files changed, 4514 insertions(+), 4527 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 634f81fa18c53..25a416f06ac90 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -906,7 +906,10 @@ void RISCVRegisterInfo::getOffsetOpcodes(const StackOffset &Offset,
unsigned
RISCVRegisterInfo::getRegisterCostTableIndex(const MachineFunction &MF) const {
- return MF.getSubtarget<RISCVSubtarget>().hasStdExtZca() && !DisableCostPerUse
+ // Set CostPerUse to 1 only when optimizing for size and RVC exists.
+ return MF.getFunction().hasOptSize() &&
+ MF.getSubtarget<RISCVSubtarget>().hasStdExtZca() &&
+ !DisableCostPerUse
? 1
: 0;
}
diff --git a/llvm/test/CodeGen/RISCV/add-before-shl.ll b/llvm/test/CodeGen/RISCV/add-before-shl.ll
index 35a39b89a2cb7..1edab031c86f8 100644
--- a/llvm/test/CodeGen/RISCV/add-before-shl.ll
+++ b/llvm/test/CodeGen/RISCV/add-before-shl.ll
@@ -201,23 +201,23 @@ define i128 @add_wide_operand(i128 %a) nounwind {
; RV32C-LABEL: add_wide_operand:
; RV32C: # %bb.0:
; RV32C-NEXT: c.lw a2, 0(a1)
-; RV32C-NEXT: c.lw a4, 12(a1)
-; RV32C-NEXT: c.lw a3, 4(a1)
+; RV32C-NEXT: c.lw a3, 12(a1)
+; RV32C-NEXT: c.lw a4, 4(a1)
; RV32C-NEXT: c.lw a1, 8(a1)
; RV32C-NEXT: c.lui a5, 16
-; RV32C-NEXT: add a6, a4, a5
+; RV32C-NEXT: c.add a3, a5
; RV32C-NEXT: srli a5, a2, 29
-; RV32C-NEXT: slli a4, a3, 3
-; RV32C-NEXT: c.or a4, a5
-; RV32C-NEXT: srli a5, a1, 29
-; RV32C-NEXT: c.srli a3, 29
+; RV32C-NEXT: slli a6, a4, 3
+; RV32C-NEXT: or a5, a6, a5
+; RV32C-NEXT: srli a6, a1, 29
+; RV32C-NEXT: c.srli a4, 29
; RV32C-NEXT: c.slli a1, 3
; RV32C-NEXT: c.slli a2, 3
-; RV32C-NEXT: c.slli a6, 3
-; RV32C-NEXT: c.or a1, a3
-; RV32C-NEXT: or a3, a6, a5
+; RV32C-NEXT: c.slli a3, 3
+; RV32C-NEXT: c.or a1, a4
+; RV32C-NEXT: or a3, a3, a6
; RV32C-NEXT: c.sw a2, 0(a0)
-; RV32C-NEXT: c.sw a4, 4(a0)
+; RV32C-NEXT: c.sw a5, 4(a0)
; RV32C-NEXT: c.sw a1, 8(a0)
; RV32C-NEXT: c.sw a3, 12(a0)
; RV32C-NEXT: c.jr ra
diff --git a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
index 4e5d175e0ee12..b6b174b8d5a69 100644
--- a/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
+++ b/llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
@@ -448,60 +448,60 @@ define void @callee() {
; RV32IZCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; RV32IZCMP-NEXT: lw a1, 16(a0)
; RV32IZCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw t3, 20(a0)
-; RV32IZCMP-NEXT: lw t4, 24(a0)
-; RV32IZCMP-NEXT: lw t5, 28(a0)
-; RV32IZCMP-NEXT: lw t6, 32(a0)
-; RV32IZCMP-NEXT: lw s2, 36(a0)
-; RV32IZCMP-NEXT: lw s3, 40(a0)
-; RV32IZCMP-NEXT: lw s4, 44(a0)
-; RV32IZCMP-NEXT: lw s5, 48(a0)
-; RV32IZCMP-NEXT: lw s6, 52(a0)
-; RV32IZCMP-NEXT: lw s7, 56(a0)
-; RV32IZCMP-NEXT: lw s8, 60(a0)
-; RV32IZCMP-NEXT: lw s9, 64(a0)
-; RV32IZCMP-NEXT: lw s10, 68(a0)
-; RV32IZCMP-NEXT: lw s11, 72(a0)
-; RV32IZCMP-NEXT: lw ra, 76(a0)
-; RV32IZCMP-NEXT: lw t2, 80(a0)
-; RV32IZCMP-NEXT: lw s0, 84(a0)
-; RV32IZCMP-NEXT: lw s1, 88(a0)
-; RV32IZCMP-NEXT: lw t1, 92(a0)
-; RV32IZCMP-NEXT: lw t0, 112(a0)
-; RV32IZCMP-NEXT: lw a5, 116(a0)
-; RV32IZCMP-NEXT: lw a3, 120(a0)
+; RV32IZCMP-NEXT: lw a6, 20(a0)
+; RV32IZCMP-NEXT: lw a7, 24(a0)
+; RV32IZCMP-NEXT: lw t0, 28(a0)
+; RV32IZCMP-NEXT: lw t1, 32(a0)
+; RV32IZCMP-NEXT: lw t2, 36(a0)
+; RV32IZCMP-NEXT: lw t3, 40(a0)
+; RV32IZCMP-NEXT: lw t4, 44(a0)
+; RV32IZCMP-NEXT: lw t5, 48(a0)
+; RV32IZCMP-NEXT: lw t6, 52(a0)
+; RV32IZCMP-NEXT: lw s0, 56(a0)
+; RV32IZCMP-NEXT: lw s1, 60(a0)
+; RV32IZCMP-NEXT: lw s2, 64(a0)
+; RV32IZCMP-NEXT: lw s3, 68(a0)
+; RV32IZCMP-NEXT: lw s4, 72(a0)
+; RV32IZCMP-NEXT: lw s5, 76(a0)
+; RV32IZCMP-NEXT: lw s6, 80(a0)
+; RV32IZCMP-NEXT: lw s7, 84(a0)
+; RV32IZCMP-NEXT: lw s8, 88(a0)
+; RV32IZCMP-NEXT: lw s9, 92(a0)
+; RV32IZCMP-NEXT: lw s10, 112(a0)
+; RV32IZCMP-NEXT: lw s11, 116(a0)
+; RV32IZCMP-NEXT: lw ra, 120(a0)
; RV32IZCMP-NEXT: lw a1, 124(a0)
-; RV32IZCMP-NEXT: lw a7, 96(a0)
-; RV32IZCMP-NEXT: lw a6, 100(a0)
-; RV32IZCMP-NEXT: lw a4, 104(a0)
+; RV32IZCMP-NEXT: lw a5, 96(a0)
+; RV32IZCMP-NEXT: lw a4, 100(a0)
+; RV32IZCMP-NEXT: lw a3, 104(a0)
; RV32IZCMP-NEXT: lw a2, 108(a0)
; RV32IZCMP-NEXT: sw a1, 124(a0)
-; RV32IZCMP-NEXT: sw a3, 120(a0)
-; RV32IZCMP-NEXT: sw a5, 116(a0)
-; RV32IZCMP-NEXT: sw t0, 112(a0)
+; RV32IZCMP-NEXT: sw ra, 120(a0)
+; RV32IZCMP-NEXT: sw s11, 116(a0)
+; RV32IZCMP-NEXT: sw s10, 112(a0)
; RV32IZCMP-NEXT: sw a2, 108(a0)
-; RV32IZCMP-NEXT: sw a4, 104(a0)
-; RV32IZCMP-NEXT: sw a6, 100(a0)
-; RV32IZCMP-NEXT: sw a7, 96(a0)
-; RV32IZCMP-NEXT: sw t1, 92(a0)
-; RV32IZCMP-NEXT: sw s1, 88(a0)
-; RV32IZCMP-NEXT: sw s0, 84(a0)
-; RV32IZCMP-NEXT: sw t2, 80(a0)
-; RV32IZCMP-NEXT: sw ra, 76(a0)
-; RV32IZCMP-NEXT: sw s11, 72(a0)
-; RV32IZCMP-NEXT: sw s10, 68(a0)
-; RV32IZCMP-NEXT: sw s9, 64(a0)
-; RV32IZCMP-NEXT: sw s8, 60(a0)
-; RV32IZCMP-NEXT: sw s7, 56(a0)
-; RV32IZCMP-NEXT: sw s6, 52(a0)
-; RV32IZCMP-NEXT: sw s5, 48(a0)
-; RV32IZCMP-NEXT: sw s4, 44(a0)
-; RV32IZCMP-NEXT: sw s3, 40(a0)
-; RV32IZCMP-NEXT: sw s2, 36(a0)
-; RV32IZCMP-NEXT: sw t6, 32(a0)
-; RV32IZCMP-NEXT: sw t5, 28(a0)
-; RV32IZCMP-NEXT: sw t4, 24(a0)
-; RV32IZCMP-NEXT: sw t3, 20(a0)
+; RV32IZCMP-NEXT: sw a3, 104(a0)
+; RV32IZCMP-NEXT: sw a4, 100(a0)
+; RV32IZCMP-NEXT: sw a5, 96(a0)
+; RV32IZCMP-NEXT: sw s9, 92(a0)
+; RV32IZCMP-NEXT: sw s8, 88(a0)
+; RV32IZCMP-NEXT: sw s7, 84(a0)
+; RV32IZCMP-NEXT: sw s6, 80(a0)
+; RV32IZCMP-NEXT: sw s5, 76(a0)
+; RV32IZCMP-NEXT: sw s4, 72(a0)
+; RV32IZCMP-NEXT: sw s3, 68(a0)
+; RV32IZCMP-NEXT: sw s2, 64(a0)
+; RV32IZCMP-NEXT: sw s1, 60(a0)
+; RV32IZCMP-NEXT: sw s0, 56(a0)
+; RV32IZCMP-NEXT: sw t6, 52(a0)
+; RV32IZCMP-NEXT: sw t5, 48(a0)
+; RV32IZCMP-NEXT: sw t4, 44(a0)
+; RV32IZCMP-NEXT: sw t3, 40(a0)
+; RV32IZCMP-NEXT: sw t2, 36(a0)
+; RV32IZCMP-NEXT: sw t1, 32(a0)
+; RV32IZCMP-NEXT: sw t0, 28(a0)
+; RV32IZCMP-NEXT: sw a7, 24(a0)
+; RV32IZCMP-NEXT: sw a6, 20(a0)
; RV32IZCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; RV32IZCMP-NEXT: sw a1, 16(a0)
; RV32IZCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -560,58 +560,58 @@ define void @callee() {
; RV32IZCMP-WITH-FP-NEXT: sw a1, -72(s0) # 4-byte Folded Spill
; RV32IZCMP-WITH-FP-NEXT: lw a1, 20(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a1, -76(s0) # 4-byte Folded Spill
-; RV32IZCMP-WITH-FP-NEXT: lw t4, 24(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t5, 28(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t6, 32(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s2, 36(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s3, 40(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s4, 44(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s5, 48(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s6, 52(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s7, 56(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s8, 60(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s9, 64(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s10, 68(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s11, 72(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw ra, 76(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw s1, 80(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t3, 84(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t2, 88(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t1, 92(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw t0, 112(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw a6, 116(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a7, 24(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t0, 28(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t1, 32(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t2, 36(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t3, 40(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t4, 44(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t5, 48(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw t6, 52(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s1, 56(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s2, 60(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s3, 64(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s4, 68(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s5, 72(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s6, 76(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s7, 80(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s8, 84(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s9, 88(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s10, 92(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw s11, 112(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw ra, 116(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a4, 120(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a1, 124(a0)
-; RV32IZCMP-WITH-FP-NEXT: lw a7, 96(a0)
+; RV32IZCMP-WITH-FP-NEXT: lw a6, 96(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a5, 100(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a3, 104(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a2, 108(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a1, 124(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a4, 120(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw a6, 116(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t0, 112(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw ra, 116(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s11, 112(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a2, 108(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a3, 104(a0)
; RV32IZCMP-WITH-FP-NEXT: sw a5, 100(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw a7, 96(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t1, 92(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t2, 88(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t3, 84(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s1, 80(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw ra, 76(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s11, 72(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s10, 68(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s9, 64(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s8, 60(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s7, 56(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s6, 52(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s5, 48(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s4, 44(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s3, 40(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw s2, 36(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t6, 32(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t5, 28(a0)
-; RV32IZCMP-WITH-FP-NEXT: sw t4, 24(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a6, 96(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s10, 92(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s9, 88(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s8, 84(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s7, 80(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s6, 76(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s5, 72(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s4, 68(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s3, 64(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s2, 60(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw s1, 56(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t6, 52(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t5, 48(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t4, 44(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t3, 40(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t2, 36(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t1, 32(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw t0, 28(a0)
+; RV32IZCMP-WITH-FP-NEXT: sw a7, 24(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a1, -76(s0) # 4-byte Folded Reload
; RV32IZCMP-WITH-FP-NEXT: sw a1, 20(a0)
; RV32IZCMP-WITH-FP-NEXT: lw a1, -72(s0) # 4-byte Folded Reload
@@ -1057,60 +1057,60 @@ define void @callee() {
; RV64IZCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
; RV64IZCMP-NEXT: lw a1, 16(a0)
; RV64IZCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw t3, 20(a0)
-; RV64IZCMP-NEXT: lw t4, 24(a0)
-; RV64IZCMP-NEXT: lw t5, 28(a0)
-; RV64IZCMP-NEXT: lw t6, 32(a0)
-; RV64IZCMP-NEXT: lw s2, 36(a0)
-; RV64IZCMP-NEXT: lw s3, 40(a0)
-; RV64IZCMP-NEXT: lw s4, 44(a0)
-; RV64IZCMP-NEXT: lw s5, 48(a0)
-; RV64IZCMP-NEXT: lw s6, 52(a0)
-; RV64IZCMP-NEXT: lw s7, 56(a0)
-; RV64IZCMP-NEXT: lw s8, 60(a0)
-; RV64IZCMP-NEXT: lw s9, 64(a0)
-; RV64IZCMP-NEXT: lw s10, 68(a0)
-; RV64IZCMP-NEXT: lw s11, 72(a0)
-; RV64IZCMP-NEXT: lw ra, 76(a0)
-; RV64IZCMP-NEXT: lw t2, 80(a0)
-; RV64IZCMP-NEXT: lw s0, 84(a0)
-; RV64IZCMP-NEXT: lw s1, 88(a0)
-; RV64IZCMP-NEXT: lw t1, 92(a0)
-; RV64IZCMP-NEXT: lw t0, 112(a0)
-; RV64IZCMP-NEXT: lw a5, 116(a0)
-; RV64IZCMP-NEXT: lw a3, 120(a0)
+; RV64IZCMP-NEXT: lw a6, 20(a0)
+; RV64IZCMP-NEXT: lw a7, 24(a0)
+; RV64IZCMP-NEXT: lw t0, 28(a0)
+; RV64IZCMP-NEXT: lw t1, 32(a0)
+; RV64IZCMP-NEXT: lw t2, 36(a0)
+; RV64IZCMP-NEXT: lw t3, 40(a0)
+; RV64IZCMP-NEXT: lw t4, 44(a0)
+; RV64IZCMP-NEXT: lw t5, 48(a0)
+; RV64IZCMP-NEXT: lw t6, 52(a0)
+; RV64IZCMP-NEXT: lw s0, 56(a0)
+; RV64IZCMP-NEXT: lw s1, 60(a0)
+; RV64IZCMP-NEXT: lw s2, 64(a0)
+; RV64IZCMP-NEXT: lw s3, 68(a0)
+; RV64IZCMP-NEXT: lw s4, 72(a0)
+; RV64IZCMP-NEXT: lw s5, 76(a0)
+; RV64IZCMP-NEXT: lw s6, 80(a0)
+; RV64IZCMP-NEXT: lw s7, 84(a0)
+; RV64IZCMP-NEXT: lw s8, 88(a0)
+; RV64IZCMP-NEXT: lw s9, 92(a0)
+; RV64IZCMP-NEXT: lw s10, 112(a0)
+; RV64IZCMP-NEXT: lw s11, 116(a0)
+; RV64IZCMP-NEXT: lw ra, 120(a0)
; RV64IZCMP-NEXT: lw a1, 124(a0)
-; RV64IZCMP-NEXT: lw a7, 96(a0)
-; RV64IZCMP-NEXT: lw a6, 100(a0)
-; RV64IZCMP-NEXT: lw a4, 104(a0)
+; RV64IZCMP-NEXT: lw a5, 96(a0)
+; RV64IZCMP-NEXT: lw a4, 100(a0)
+; RV64IZCMP-NEXT: lw a3, 104(a0)
; RV64IZCMP-NEXT: lw a2, 108(a0)
; RV64IZCMP-NEXT: sw a1, 124(a0)
-; RV64IZCMP-NEXT: sw a3, 120(a0)
-; RV64IZCMP-NEXT: sw a5, 116(a0)
-; RV64IZCMP-NEXT: sw t0, 112(a0)
+; RV64IZCMP-NEXT: sw ra, 120(a0)
+; RV64IZCMP-NEXT: sw s11, 116(a0)
+; RV64IZCMP-NEXT: sw s10, 112(a0)
; RV64IZCMP-NEXT: sw a2, 108(a0)
-; RV64IZCMP-NEXT: sw a4, 104(a0)
-; RV64IZCMP-NEXT: sw a6, 100(a0)
-; RV64IZCMP-NEXT: sw a7, 96(a0)
-; RV64IZCMP-NEXT: sw t1, 92(a0)
-; RV64IZCMP-NEXT: sw s1, 88(a0)
-; RV64IZCMP-NEXT: sw s0, 84(a0)
-; RV64IZCMP-NEXT: sw t2, 80(a0)
-; RV64IZCMP-NEXT: sw ra, 76(a0)
-; RV64IZCMP-NEXT: sw s11, 72(a0)
-; RV64IZCMP-NEXT: sw s10, 68(a0)
-; RV64IZCMP-NEXT: sw s9, 64(a0)
-; RV64IZCMP-NEXT: sw s8, 60(a0)
-; RV64IZCMP-NEXT: sw s7, 56(a0)
-; RV64IZCMP-NEXT: sw s6, 52(a0)
-; RV64IZCMP-NEXT: sw s5, 48(a0)
-; RV64IZCMP-NEXT: sw s4, 44(a0)
-; RV64IZCMP-NEXT: sw s3, 40(a0)
-; RV64IZCMP-NEXT: sw s2, 36(a0)
-; RV64IZCMP-NEXT: sw t6, 32(a0)
-; RV64IZCMP-NEXT: sw t5, 28(a0)
-; RV64IZCMP-NEXT: sw t4, 24(a0)
-; RV64IZCMP-NEXT: sw t3, 20(a0)
+; RV64IZCMP-NEXT: sw a3, 104(a0)
+; RV64IZCMP-NEXT: sw a4, 100(a0)
+; RV64IZCMP-NEXT: sw a5, 96(a0)
+; RV64IZCMP-NEXT: sw s9, 92(a0)
+; RV64IZCMP-NEXT: sw s8, 88(a0)
+; RV64IZCMP-NEXT: sw s7, 84(a0)
+; RV64IZCMP-NEXT: sw s6, 80(a0)
+; RV64IZCMP-NEXT: sw s5, 76(a0)
+; RV64IZCMP-NEXT: sw s4, 72(a0)
+; RV64IZCMP-NEXT: sw s3, 68(a0)
+; RV64IZCMP-NEXT: sw s2, 64(a0)
+; RV64IZCMP-NEXT: sw s1, 60(a0)
+; RV64IZCMP-NEXT: sw s0, 56(a0)
+; RV64IZCMP-NEXT: sw t6, 52(a0)
+; RV64IZCMP-NEXT: sw t5, 48(a0)
+; RV64IZCMP-NEXT: sw t4, 44(a0)
+; RV64IZCMP-NEXT: sw t3, 40(a0)
+; RV64IZCMP-NEXT: sw t2, 36(a0)
+; RV64IZCMP-NEXT: sw t1, 32(a0)
+; RV64IZCMP-NEXT: sw t0, 28(a0)
+; RV64IZCMP-NEXT: sw a7, 24(a0)
+; RV64IZCMP-NEXT: sw a6, 20(a0)
; RV64IZCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-NEXT: sw a1, 16(a0)
; RV64IZCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
@@ -1169,58 +1169,58 @@ define void @callee() {
; RV64IZCMP-WITH-FP-NEXT: sd a1, -144(s0) # 8-byte Folded Spill
; RV64IZCMP-WITH-FP-NEXT: lw a1, 20(a0)
; RV64IZCMP-WITH-FP-NEXT: sd a1, -152(s0) # 8-byte Folded Spill
-; RV64IZCMP-WITH-FP-NEXT: lw t4, 24(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t5, 28(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t6, 32(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s2, 36(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s3, 40(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s4, 44(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s5, 48(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s6, 52(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s7, 56(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s8, 60(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s9, 64(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s10, 68(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s11, 72(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw ra, 76(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw s1, 80(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t3, 84(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t2, 88(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t1, 92(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw t0, 112(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw a6, 116(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a7, 24(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t0, 28(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t1, 32(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t2, 36(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t3, 40(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t4, 44(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t5, 48(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw t6, 52(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s1, 56(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s2, 60(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s3, 64(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s4, 68(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s5, 72(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s6, 76(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s7, 80(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s8, 84(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s9, 88(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s10, 92(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw s11, 112(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw ra, 116(a0)
; RV64IZCMP-WITH-FP-NEXT: lw a4, 120(a0)
; RV64IZCMP-WITH-FP-NEXT: lw a1, 124(a0)
-; RV64IZCMP-WITH-FP-NEXT: lw a7, 96(a0)
+; RV64IZCMP-WITH-FP-NEXT: lw a6, 96(a0)
; RV64IZCMP-WITH-FP-NEXT: lw a5, 100(a0)
; RV64IZCMP-WITH-FP-NEXT: lw a3, 104(a0)
; RV64IZCMP-WITH-FP-NEXT: lw a2, 108(a0)
; RV64IZCMP-WITH-FP-NEXT: sw a1, 124(a0)
; RV64IZCMP-WITH-FP-NEXT: sw a4, 120(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw a6, 116(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t0, 112(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw ra, 116(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s11, 112(a0)
; RV64IZCMP-WITH-FP-NEXT: sw a2, 108(a0)
; RV64IZCMP-WITH-FP-NEXT: sw a3, 104(a0)
; RV64IZCMP-WITH-FP-NEXT: sw a5, 100(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw a7, 96(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t1, 92(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t2, 88(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t3, 84(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s1, 80(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw ra, 76(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s11, 72(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s10, 68(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s9, 64(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s8, 60(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s7, 56(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s6, 52(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s5, 48(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s4, 44(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s3, 40(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw s2, 36(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t6, 32(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t5, 28(a0)
-; RV64IZCMP-WITH-FP-NEXT: sw t4, 24(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a6, 96(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s10, 92(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s9, 88(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s8, 84(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s7, 80(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s6, 76(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s5, 72(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s4, 68(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s3, 64(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s2, 60(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw s1, 56(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t6, 52(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t5, 48(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t4, 44(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t3, 40(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t2, 36(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t1, 32(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw t0, 28(a0)
+; RV64IZCMP-WITH-FP-NEXT: sw a7, 24(a0)
; RV64IZCMP-WITH-FP-NEXT: ld a1, -152(s0) # 8-byte Folded Reload
; RV64IZCMP-WITH-FP-NEXT: sw a1, 20(a0)
; RV64IZCMP-WITH-FP-NEXT: ld a1, -144(s0) # 8-byte Folded Reload
@@ -2228,29 +2228,29 @@ define void @caller() {
; RV32IZCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; RV32IZCMP-NEXT: lw a0, 80(s0)
; RV32IZCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw s1, 84(s0)
-; RV32IZCMP-NEXT: lw s2, 88(s0)
-; RV32IZCMP-NEXT: lw s3, 92(s0)
-; RV32IZCMP-NEXT: lw s4, 96(s0)
-; RV32IZCMP-NEXT: lw s5, 100(s0)
-; RV32IZCMP-NEXT: lw s6, 104(s0)
-; RV32IZCMP-NEXT: lw s7, 108(s0)
-; RV32IZCMP-NEXT: lw s8, 112(s0)
-; RV32IZCMP-NEXT: lw s9, 116(s0)
-; RV32IZCMP-NEXT: lw s10, 120(s0)
-; RV32IZCMP-NEXT: lw s11, 124(s0)
+; RV32IZCMP-NEXT: lw s11, 84(s0)
+; RV32IZCMP-NEXT: lw s1, 88(s0)
+; RV32IZCMP-NEXT: lw s2, 92(s0)
+; RV32IZCMP-NEXT: lw s3, 96(s0)
+; RV32IZCMP-NEXT: lw s4, 100(s0)
+; RV32IZCMP-NEXT: lw s5, 104(s0)
+; RV32IZCMP-NEXT: lw s6, 108(s0)
+; RV32IZCMP-NEXT: lw s7, 112(s0)
+; RV32IZCMP-NEXT: lw s8, 116(s0)
+; RV32IZCMP-NEXT: lw s9, 120(s0)
+; RV32IZCMP-NEXT: lw s10, 124(s0)
; RV32IZCMP-NEXT: call callee
-; RV32IZCMP-NEXT: sw s11, 124(s0)
-; RV32IZCMP-NEXT: sw s10, 120(s0)
-; RV32IZCMP-NEXT: sw s9, 116(s0)
-; RV32IZCMP-NEXT: sw s8, 112(s0)
-; RV32IZCMP-NEXT: sw s7, 108(s0)
-; RV32IZCMP-NEXT: sw s6, 104(s0)
-; RV32IZCMP-NEXT: sw s5, 100(s0)
-; RV32IZCMP-NEXT: sw s4, 96(s0)
-; RV32IZCMP-NEXT: sw s3, 92(s0)
-; RV32IZCMP-NEXT: sw s2, 88(s0)
-; RV32IZCMP-NEXT: sw s1, 84(s0)
+; RV32IZCMP-NEXT: sw s10, 124(s0)
+; RV32IZCMP-NEXT: sw s9, 120(s0)
+; RV32IZCMP-NEXT: sw s8, 116(s0)
+; RV32IZCMP-NEXT: sw s7, 112(s0)
+; RV32IZCMP-NEXT: sw s6, 108(s0)
+; RV32IZCMP-NEXT: sw s5, 104(s0)
+; RV32IZCMP-NEXT: sw s4, 100(s0)
+; RV32IZCMP-NEXT: sw s3, 96(s0)
+; RV32IZCMP-NEXT: sw s2, 92(s0)
+; RV32IZCMP-NEXT: sw s1, 88(s0)
+; RV32IZCMP-NEXT: sw s11, 84(s0)
; RV32IZCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; RV32IZCMP-NEXT: sw a0, 80(s0)
; RV32IZCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
@@ -3026,29 +3026,29 @@ define void @caller() {
; RV64IZCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
; RV64IZCMP-NEXT: lw a0, 80(s0)
; RV64IZCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw s1, 84(s0)
-; RV64IZCMP-NEXT: lw s2, 88(s0)
-; RV64IZCMP-NEXT: lw s3, 92(s0)
-; RV64IZCMP-NEXT: lw s4, 96(s0)
-; RV64IZCMP-NEXT: lw s5, 100(s0)
-; RV64IZCMP-NEXT: lw s6, 104(s0)
-; RV64IZCMP-NEXT: lw s7, 108(s0)
-; RV64IZCMP-NEXT: lw s8, 112(s0)
-; RV64IZCMP-NEXT: lw s9, 116(s0)
-; RV64IZCMP-NEXT: lw s10, 120(s0)
-; RV64IZCMP-NEXT: lw s11, 124(s0)
+; RV64IZCMP-NEXT: lw s11, 84(s0)
+; RV64IZCMP-NEXT: lw s1, 88(s0)
+; RV64IZCMP-NEXT: lw s2, 92(s0)
+; RV64IZCMP-NEXT: lw s3, 96(s0)
+; RV64IZCMP-NEXT: lw s4, 100(s0)
+; RV64IZCMP-NEXT: lw s5, 104(s0)
+; RV64IZCMP-NEXT: lw s6, 108(s0)
+; RV64IZCMP-NEXT: lw s7, 112(s0)
+; RV64IZCMP-NEXT: lw s8, 116(s0)
+; RV64IZCMP-NEXT: lw s9, 120(s0)
+; RV64IZCMP-NEXT: lw s10, 124(s0)
; RV64IZCMP-NEXT: call callee
-; RV64IZCMP-NEXT: sw s11, 124(s0)
-; RV64IZCMP-NEXT: sw s10, 120(s0)
-; RV64IZCMP-NEXT: sw s9, 116(s0)
-; RV64IZCMP-NEXT: sw s8, 112(s0)
-; RV64IZCMP-NEXT: sw s7, 108(s0)
-; RV64IZCMP-NEXT: sw s6, 104(s0)
-; RV64IZCMP-NEXT: sw s5, 100(s0)
-; RV64IZCMP-NEXT: sw s4, 96(s0)
-; RV64IZCMP-NEXT: sw s3, 92(s0)
-; RV64IZCMP-NEXT: sw s2, 88(s0)
-; RV64IZCMP-NEXT: sw s1, 84(s0)
+; RV64IZCMP-NEXT: sw s10, 124(s0)
+; RV64IZCMP-NEXT: sw s9, 120(s0)
+; RV64IZCMP-NEXT: sw s8, 116(s0)
+; RV64IZCMP-NEXT: sw s7, 112(s0)
+; RV64IZCMP-NEXT: sw s6, 108(s0)
+; RV64IZCMP-NEXT: sw s5, 104(s0)
+; RV64IZCMP-NEXT: sw s4, 100(s0)
+; RV64IZCMP-NEXT: sw s3, 96(s0)
+; RV64IZCMP-NEXT: sw s2, 92(s0)
+; RV64IZCMP-NEXT: sw s1, 88(s0)
+; RV64IZCMP-NEXT: sw s11, 84(s0)
; RV64IZCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-NEXT: sw a0, 80(s0)
; RV64IZCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
index de8ae49dfbb7d..9e29b8e2db927 100644
--- a/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
+++ b/llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll
@@ -1113,47 +1113,47 @@ define i64 @fold_addi_from_different_bb(i64 %k, i64 %n, ptr %a) nounwind {
; RV32IXQCILI-NEXT: sw s5, 20(sp) # 4-byte Folded Spill
; RV32IXQCILI-NEXT: sw s6, 16(sp) # 4-byte Folded Spill
; RV32IXQCILI-NEXT: sw s7, 12(sp) # 4-byte Folded Spill
-; RV32IXQCILI-NEXT: mv s2, a4
-; RV32IXQCILI-NEXT: mv s4, a3
-; RV32IXQCILI-NEXT: mv s3, a2
+; RV32IXQCILI-NEXT: mv s0, a4
+; RV32IXQCILI-NEXT: mv s1, a3
+; RV32IXQCILI-NEXT: mv s2, a2
; RV32IXQCILI-NEXT: beqz a3, .LBB20_3
; RV32IXQCILI-NEXT: # %bb.1: # %entry
-; RV32IXQCILI-NEXT: srli a1, s4, 31
+; RV32IXQCILI-NEXT: srli a1, s1, 31
; RV32IXQCILI-NEXT: beqz a1, .LBB20_4
; RV32IXQCILI-NEXT: .LBB20_2:
-; RV32IXQCILI-NEXT: li s6, 0
-; RV32IXQCILI-NEXT: li s5, 0
+; RV32IXQCILI-NEXT: li s3, 0
+; RV32IXQCILI-NEXT: li s4, 0
; RV32IXQCILI-NEXT: j .LBB20_6
; RV32IXQCILI-NEXT: .LBB20_3:
-; RV32IXQCILI-NEXT: seqz a1, s3
+; RV32IXQCILI-NEXT: seqz a1, s2
; RV32IXQCILI-NEXT: bnez a1, .LBB20_2
; RV32IXQCILI-NEXT: .LBB20_4: # %for.body.lr.ph
-; RV32IXQCILI-NEXT: li s1, 0
-; RV32IXQCILI-NEXT: li s0, 0
-; RV32IXQCILI-NEXT: li s6, 0
; RV32IXQCILI-NEXT: li s5, 0
+; RV32IXQCILI-NEXT: li s6, 0
+; RV32IXQCILI-NEXT: li s3, 0
+; RV32IXQCILI-NEXT: li s4, 0
; RV32IXQCILI-NEXT: slli a0, a0, 4
-; RV32IXQCILI-NEXT: add s7, s2, a0
+; RV32IXQCILI-NEXT: add s7, s0, a0
; RV32IXQCILI-NEXT: .LBB20_5: # %for.body
; RV32IXQCILI-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32IXQCILI-NEXT: mv a0, s2
+; RV32IXQCILI-NEXT: mv a0, s0
; RV32IXQCILI-NEXT: call f
; RV32IXQCILI-NEXT: lw a0, 8(s7)
; RV32IXQCILI-NEXT: lw a1, 12(s7)
-; RV32IXQCILI-NEXT: addi s1, s1, 1
-; RV32IXQCILI-NEXT: seqz a2, s1
-; RV32IXQCILI-NEXT: add s0, s0, a2
-; RV32IXQCILI-NEXT: xor a2, s1, s3
-; RV32IXQCILI-NEXT: add a1, a1, s5
-; RV32IXQCILI-NEXT: xor a3, s0, s4
+; RV32IXQCILI-NEXT: addi s5, s5, 1
+; RV32IXQCILI-NEXT: seqz a2, s5
+; RV32IXQCILI-NEXT: add s6, s6, a2
+; RV32IXQCILI-NEXT: xor a2, s5, s2
+; RV32IXQCILI-NEXT: add a1, a1, s4
+; RV32IXQCILI-NEXT: xor a3, s6, s1
; RV32IXQCILI-NEXT: or a2, a2, a3
-; RV32IXQCILI-NEXT: add s6, s6, a0
-; RV32IXQCILI-NEXT: sltu s5, s6, a0
-; RV32IXQCILI-NEXT: add s5, s5, a1
+; RV32IXQCILI-NEXT: add s3, s3, a0
+; RV32IXQCILI-NEXT: sltu s4, s3, a0
+; RV32IXQCILI-NEXT: add s4, s4, a1
; RV32IXQCILI-NEXT: bnez a2, .LBB20_5
; RV32IXQCILI-NEXT: .LBB20_6: # %for.cond.cleanup
-; RV32IXQCILI-NEXT: mv a0, s6
-; RV32IXQCILI-NEXT: mv a1, s5
+; RV32IXQCILI-NEXT: mv a0, s3
+; RV32IXQCILI-NEXT: mv a1, s4
; RV32IXQCILI-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32IXQCILI-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32IXQCILI-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/machine-pipeliner.ll b/llvm/test/CodeGen/RISCV/machine-pipeliner.ll
index a2a7da7e2d6ef..ce2e6aed75135 100644
--- a/llvm/test/CodeGen/RISCV/machine-pipeliner.ll
+++ b/llvm/test/CodeGen/RISCV/machine-pipeliner.ll
@@ -54,37 +54,37 @@ define void @test_pipelined_1(ptr noalias %in, ptr noalias %out, i32 signext %cn
; CHECK-PIPELINED: # %bb.0: # %entry
; CHECK-PIPELINED-NEXT: blez a2, .LBB1_6
; CHECK-PIPELINED-NEXT: # %bb.1: # %for.body.preheader
-; CHECK-PIPELINED-NEXT: lw a7, 0(a1)
; CHECK-PIPELINED-NEXT: addi a2, a2, -1
; CHECK-PIPELINED-NEXT: addi a3, a0, 4
; CHECK-PIPELINED-NEXT: addi a5, a1, 4
-; CHECK-PIPELINED-NEXT: sh2add.uw a6, a2, a1
-; CHECK-PIPELINED-NEXT: addi a6, a6, 4
-; CHECK-PIPELINED-NEXT: beq a5, a6, .LBB1_5
+; CHECK-PIPELINED-NEXT: sh2add.uw a4, a2, a1
+; CHECK-PIPELINED-NEXT: lw a2, 0(a1)
+; CHECK-PIPELINED-NEXT: addi a4, a4, 4
+; CHECK-PIPELINED-NEXT: beq a5, a4, .LBB1_5
; CHECK-PIPELINED-NEXT: # %bb.2: # %for.body
; CHECK-PIPELINED-NEXT: lw a1, 0(a5)
-; CHECK-PIPELINED-NEXT: addi a4, a3, 4
+; CHECK-PIPELINED-NEXT: addi a6, a3, 4
; CHECK-PIPELINED-NEXT: addi a5, a5, 4
-; CHECK-PIPELINED-NEXT: beq a5, a6, .LBB1_4
+; CHECK-PIPELINED-NEXT: beq a5, a4, .LBB1_4
; CHECK-PIPELINED-NEXT: .LBB1_3: # %for.body
; CHECK-PIPELINED-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-PIPELINED-NEXT: addi a2, a7, 1
-; CHECK-PIPELINED-NEXT: mv a7, a1
+; CHECK-PIPELINED-NEXT: addi a7, a2, 1
+; CHECK-PIPELINED-NEXT: mv a2, a1
; CHECK-PIPELINED-NEXT: lw a1, 0(a5)
-; CHECK-PIPELINED-NEXT: sw a2, 0(a0)
+; CHECK-PIPELINED-NEXT: sw a7, 0(a0)
; CHECK-PIPELINED-NEXT: mv a0, a3
-; CHECK-PIPELINED-NEXT: mv a3, a4
-; CHECK-PIPELINED-NEXT: addi a4, a4, 4
+; CHECK-PIPELINED-NEXT: mv a3, a6
+; CHECK-PIPELINED-NEXT: addi a6, a6, 4
; CHECK-PIPELINED-NEXT: addi a5, a5, 4
-; CHECK-PIPELINED-NEXT: bne a5, a6, .LBB1_3
+; CHECK-PIPELINED-NEXT: bne a5, a4, .LBB1_3
; CHECK-PIPELINED-NEXT: .LBB1_4:
-; CHECK-PIPELINED-NEXT: addi a7, a7, 1
-; CHECK-PIPELINED-NEXT: sw a7, 0(a0)
+; CHECK-PIPELINED-NEXT: addi a2, a2, 1
+; CHECK-PIPELINED-NEXT: sw a2, 0(a0)
; CHECK-PIPELINED-NEXT: mv a0, a3
-; CHECK-PIPELINED-NEXT: mv a7, a1
+; CHECK-PIPELINED-NEXT: mv a2, a1
; CHECK-PIPELINED-NEXT: .LBB1_5:
-; CHECK-PIPELINED-NEXT: addi a7, a7, 1
-; CHECK-PIPELINED-NEXT: sw a7, 0(a0)
+; CHECK-PIPELINED-NEXT: addi a2, a2, 1
+; CHECK-PIPELINED-NEXT: sw a2, 0(a0)
; CHECK-PIPELINED-NEXT: .LBB1_6: # %for.end
; CHECK-PIPELINED-NEXT: ret
entry:
diff --git a/llvm/test/CodeGen/RISCV/nontemporal.ll b/llvm/test/CodeGen/RISCV/nontemporal.ll
index 18e1f5b49032b..6ddf844b975d6 100644
--- a/llvm/test/CodeGen/RISCV/nontemporal.ll
+++ b/llvm/test/CodeGen/RISCV/nontemporal.ll
@@ -1035,24 +1035,24 @@ define void @test_nontemporal_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV64C-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
; CHECK-RV64C-NEXT: .cfi_offset s0, -8
; CHECK-RV64C-NEXT: .cfi_offset s1, -16
-; CHECK-RV64C-NEXT: lbu a6, 0(a1)
-; CHECK-RV64C-NEXT: lbu a7, 8(a1)
-; CHECK-RV64C-NEXT: lbu t0, 16(a1)
-; CHECK-RV64C-NEXT: lbu t1, 24(a1)
-; CHECK-RV64C-NEXT: lbu t2, 32(a1)
-; CHECK-RV64C-NEXT: lbu t3, 40(a1)
-; CHECK-RV64C-NEXT: lbu t4, 48(a1)
-; CHECK-RV64C-NEXT: lbu t5, 56(a1)
-; CHECK-RV64C-NEXT: lbu t6, 64(a1)
-; CHECK-RV64C-NEXT: lbu a3, 72(a1)
-; CHECK-RV64C-NEXT: lbu a4, 80(a1)
-; CHECK-RV64C-NEXT: lbu a5, 88(a1)
-; CHECK-RV64C-NEXT: lbu a2, 96(a1)
+; CHECK-RV64C-NEXT: lbu a2, 0(a1)
+; CHECK-RV64C-NEXT: lbu a3, 8(a1)
+; CHECK-RV64C-NEXT: lbu a4, 16(a1)
+; CHECK-RV64C-NEXT: lbu a5, 24(a1)
+; CHECK-RV64C-NEXT: lbu a6, 32(a1)
+; CHECK-RV64C-NEXT: lbu a7, 40(a1)
+; CHECK-RV64C-NEXT: lbu t0, 48(a1)
+; CHECK-RV64C-NEXT: lbu t1, 56(a1)
+; CHECK-RV64C-NEXT: lbu t2, 64(a1)
+; CHECK-RV64C-NEXT: lbu t3, 72(a1)
+; CHECK-RV64C-NEXT: lbu t4, 80(a1)
+; CHECK-RV64C-NEXT: lbu t5, 88(a1)
+; CHECK-RV64C-NEXT: lbu t6, 96(a1)
; CHECK-RV64C-NEXT: lbu s0, 104(a1)
; CHECK-RV64C-NEXT: lbu s1, 112(a1)
; CHECK-RV64C-NEXT: lbu a1, 120(a1)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a2, 12(a0)
+; CHECK-RV64C-NEXT: sb t6, 12(a0)
; CHECK-RV64C-NEXT: c.ntl.all
; CHECK-RV64C-NEXT: sb s0, 13(a0)
; CHECK-RV64C-NEXT: c.ntl.all
@@ -1060,29 +1060,29 @@ define void @test_nontemporal_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV64C-NEXT: c.ntl.all
; CHECK-RV64C-NEXT: sb a1, 15(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t6, 8(a0)
+; CHECK-RV64C-NEXT: sb t2, 8(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a3, 9(a0)
+; CHECK-RV64C-NEXT: sb t3, 9(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a4, 10(a0)
+; CHECK-RV64C-NEXT: sb t4, 10(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a5, 11(a0)
+; CHECK-RV64C-NEXT: sb t5, 11(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t2, 4(a0)
+; CHECK-RV64C-NEXT: sb a6, 4(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t3, 5(a0)
+; CHECK-RV64C-NEXT: sb a7, 5(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t4, 6(a0)
+; CHECK-RV64C-NEXT: sb t0, 6(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t5, 7(a0)
+; CHECK-RV64C-NEXT: sb t1, 7(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a6, 0(a0)
+; CHECK-RV64C-NEXT: sb a2, 0(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a7, 1(a0)
+; CHECK-RV64C-NEXT: sb a3, 1(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t0, 2(a0)
+; CHECK-RV64C-NEXT: sb a4, 2(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t1, 3(a0)
+; CHECK-RV64C-NEXT: sb a5, 3(a0)
; CHECK-RV64C-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; CHECK-RV64C-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
; CHECK-RV64C-NEXT: .cfi_restore s0
@@ -1099,24 +1099,24 @@ define void @test_nontemporal_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV32C-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; CHECK-RV32C-NEXT: .cfi_offset s0, -4
; CHECK-RV32C-NEXT: .cfi_offset s1, -8
-; CHECK-RV32C-NEXT: lbu a6, 0(a1)
-; CHECK-RV32C-NEXT: lbu a7, 4(a1)
-; CHECK-RV32C-NEXT: lbu t0, 8(a1)
-; CHECK-RV32C-NEXT: lbu t1, 12(a1)
-; CHECK-RV32C-NEXT: lbu t2, 16(a1)
-; CHECK-RV32C-NEXT: lbu t3, 20(a1)
-; CHECK-RV32C-NEXT: lbu t4, 24(a1)
-; CHECK-RV32C-NEXT: lbu t5, 28(a1)
-; CHECK-RV32C-NEXT: lbu t6, 32(a1)
-; CHECK-RV32C-NEXT: lbu a3, 36(a1)
-; CHECK-RV32C-NEXT: lbu a4, 40(a1)
-; CHECK-RV32C-NEXT: lbu a5, 44(a1)
-; CHECK-RV32C-NEXT: lbu a2, 48(a1)
+; CHECK-RV32C-NEXT: lbu a2, 0(a1)
+; CHECK-RV32C-NEXT: lbu a3, 4(a1)
+; CHECK-RV32C-NEXT: lbu a4, 8(a1)
+; CHECK-RV32C-NEXT: lbu a5, 12(a1)
+; CHECK-RV32C-NEXT: lbu a6, 16(a1)
+; CHECK-RV32C-NEXT: lbu a7, 20(a1)
+; CHECK-RV32C-NEXT: lbu t0, 24(a1)
+; CHECK-RV32C-NEXT: lbu t1, 28(a1)
+; CHECK-RV32C-NEXT: lbu t2, 32(a1)
+; CHECK-RV32C-NEXT: lbu t3, 36(a1)
+; CHECK-RV32C-NEXT: lbu t4, 40(a1)
+; CHECK-RV32C-NEXT: lbu t5, 44(a1)
+; CHECK-RV32C-NEXT: lbu t6, 48(a1)
; CHECK-RV32C-NEXT: lbu s0, 52(a1)
; CHECK-RV32C-NEXT: lbu s1, 56(a1)
; CHECK-RV32C-NEXT: lbu a1, 60(a1)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a2, 12(a0)
+; CHECK-RV32C-NEXT: sb t6, 12(a0)
; CHECK-RV32C-NEXT: c.ntl.all
; CHECK-RV32C-NEXT: sb s0, 13(a0)
; CHECK-RV32C-NEXT: c.ntl.all
@@ -1124,29 +1124,29 @@ define void @test_nontemporal_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV32C-NEXT: c.ntl.all
; CHECK-RV32C-NEXT: sb a1, 15(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t6, 8(a0)
+; CHECK-RV32C-NEXT: sb t2, 8(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a3, 9(a0)
+; CHECK-RV32C-NEXT: sb t3, 9(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a4, 10(a0)
+; CHECK-RV32C-NEXT: sb t4, 10(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a5, 11(a0)
+; CHECK-RV32C-NEXT: sb t5, 11(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t2, 4(a0)
+; CHECK-RV32C-NEXT: sb a6, 4(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t3, 5(a0)
+; CHECK-RV32C-NEXT: sb a7, 5(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t4, 6(a0)
+; CHECK-RV32C-NEXT: sb t0, 6(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t5, 7(a0)
+; CHECK-RV32C-NEXT: sb t1, 7(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a6, 0(a0)
+; CHECK-RV32C-NEXT: sb a2, 0(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a7, 1(a0)
+; CHECK-RV32C-NEXT: sb a3, 1(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t0, 2(a0)
+; CHECK-RV32C-NEXT: sb a4, 2(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t1, 3(a0)
+; CHECK-RV32C-NEXT: sb a5, 3(a0)
; CHECK-RV32C-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; CHECK-RV32C-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; CHECK-RV32C-NEXT: .cfi_restore s0
@@ -1231,56 +1231,56 @@ define void @test_nontemporal_store_v8i16(ptr %p, <8 x i16> %v) {
;
; CHECK-RV64C-LABEL: test_nontemporal_store_v8i16:
; CHECK-RV64C: # %bb.0:
-; CHECK-RV64C-NEXT: lh a6, 0(a1)
-; CHECK-RV64C-NEXT: lh a7, 8(a1)
-; CHECK-RV64C-NEXT: lh t0, 16(a1)
+; CHECK-RV64C-NEXT: lh a2, 0(a1)
+; CHECK-RV64C-NEXT: lh a3, 8(a1)
+; CHECK-RV64C-NEXT: lh a4, 16(a1)
; CHECK-RV64C-NEXT: lh a5, 24(a1)
-; CHECK-RV64C-NEXT: lh a2, 32(a1)
-; CHECK-RV64C-NEXT: lh a3, 40(a1)
-; CHECK-RV64C-NEXT: lh a4, 48(a1)
+; CHECK-RV64C-NEXT: lh a6, 32(a1)
+; CHECK-RV64C-NEXT: lh a7, 40(a1)
+; CHECK-RV64C-NEXT: lh t0, 48(a1)
; CHECK-RV64C-NEXT: lh a1, 56(a1)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh a2, 8(a0)
+; CHECK-RV64C-NEXT: sh a6, 8(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh a3, 10(a0)
+; CHECK-RV64C-NEXT: sh a7, 10(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh a4, 12(a0)
+; CHECK-RV64C-NEXT: sh t0, 12(a0)
; CHECK-RV64C-NEXT: c.ntl.all
; CHECK-RV64C-NEXT: sh a1, 14(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh a6, 0(a0)
+; CHECK-RV64C-NEXT: sh a2, 0(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh a7, 2(a0)
+; CHECK-RV64C-NEXT: sh a3, 2(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh t0, 4(a0)
+; CHECK-RV64C-NEXT: sh a4, 4(a0)
; CHECK-RV64C-NEXT: c.ntl.all
; CHECK-RV64C-NEXT: sh a5, 6(a0)
; CHECK-RV64C-NEXT: ret
;
; CHECK-RV32C-LABEL: test_nontemporal_store_v8i16:
; CHECK-RV32C: # %bb.0:
-; CHECK-RV32C-NEXT: lh a6, 0(a1)
-; CHECK-RV32C-NEXT: lh a7, 4(a1)
-; CHECK-RV32C-NEXT: lh t0, 8(a1)
+; CHECK-RV32C-NEXT: lh a2, 0(a1)
+; CHECK-RV32C-NEXT: lh a3, 4(a1)
+; CHECK-RV32C-NEXT: lh a4, 8(a1)
; CHECK-RV32C-NEXT: lh a5, 12(a1)
-; CHECK-RV32C-NEXT: lh a2, 16(a1)
-; CHECK-RV32C-NEXT: lh a3, 20(a1)
-; CHECK-RV32C-NEXT: lh a4, 24(a1)
+; CHECK-RV32C-NEXT: lh a6, 16(a1)
+; CHECK-RV32C-NEXT: lh a7, 20(a1)
+; CHECK-RV32C-NEXT: lh t0, 24(a1)
; CHECK-RV32C-NEXT: lh a1, 28(a1)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh a2, 8(a0)
+; CHECK-RV32C-NEXT: sh a6, 8(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh a3, 10(a0)
+; CHECK-RV32C-NEXT: sh a7, 10(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh a4, 12(a0)
+; CHECK-RV32C-NEXT: sh t0, 12(a0)
; CHECK-RV32C-NEXT: c.ntl.all
; CHECK-RV32C-NEXT: sh a1, 14(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh a6, 0(a0)
+; CHECK-RV32C-NEXT: sh a2, 0(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh a7, 2(a0)
+; CHECK-RV32C-NEXT: sh a3, 2(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh t0, 4(a0)
+; CHECK-RV32C-NEXT: sh a4, 4(a0)
; CHECK-RV32C-NEXT: c.ntl.all
; CHECK-RV32C-NEXT: sh a5, 6(a0)
; CHECK-RV32C-NEXT: ret
@@ -2461,24 +2461,24 @@ define void @test_nontemporal_P1_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV64C-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
; CHECK-RV64C-NEXT: .cfi_offset s0, -8
; CHECK-RV64C-NEXT: .cfi_offset s1, -16
-; CHECK-RV64C-NEXT: lbu a6, 0(a1)
-; CHECK-RV64C-NEXT: lbu a7, 8(a1)
-; CHECK-RV64C-NEXT: lbu t0, 16(a1)
-; CHECK-RV64C-NEXT: lbu t1, 24(a1)
-; CHECK-RV64C-NEXT: lbu t2, 32(a1)
-; CHECK-RV64C-NEXT: lbu t3, 40(a1)
-; CHECK-RV64C-NEXT: lbu t4, 48(a1)
-; CHECK-RV64C-NEXT: lbu t5, 56(a1)
-; CHECK-RV64C-NEXT: lbu t6, 64(a1)
-; CHECK-RV64C-NEXT: lbu a3, 72(a1)
-; CHECK-RV64C-NEXT: lbu a4, 80(a1)
-; CHECK-RV64C-NEXT: lbu a5, 88(a1)
-; CHECK-RV64C-NEXT: lbu a2, 96(a1)
+; CHECK-RV64C-NEXT: lbu a2, 0(a1)
+; CHECK-RV64C-NEXT: lbu a3, 8(a1)
+; CHECK-RV64C-NEXT: lbu a4, 16(a1)
+; CHECK-RV64C-NEXT: lbu a5, 24(a1)
+; CHECK-RV64C-NEXT: lbu a6, 32(a1)
+; CHECK-RV64C-NEXT: lbu a7, 40(a1)
+; CHECK-RV64C-NEXT: lbu t0, 48(a1)
+; CHECK-RV64C-NEXT: lbu t1, 56(a1)
+; CHECK-RV64C-NEXT: lbu t2, 64(a1)
+; CHECK-RV64C-NEXT: lbu t3, 72(a1)
+; CHECK-RV64C-NEXT: lbu t4, 80(a1)
+; CHECK-RV64C-NEXT: lbu t5, 88(a1)
+; CHECK-RV64C-NEXT: lbu t6, 96(a1)
; CHECK-RV64C-NEXT: lbu s0, 104(a1)
; CHECK-RV64C-NEXT: lbu s1, 112(a1)
; CHECK-RV64C-NEXT: lbu a1, 120(a1)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb a2, 12(a0)
+; CHECK-RV64C-NEXT: sb t6, 12(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
; CHECK-RV64C-NEXT: sb s0, 13(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
@@ -2486,29 +2486,29 @@ define void @test_nontemporal_P1_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV64C-NEXT: c.ntl.p1
; CHECK-RV64C-NEXT: sb a1, 15(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb t6, 8(a0)
+; CHECK-RV64C-NEXT: sb t2, 8(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb a3, 9(a0)
+; CHECK-RV64C-NEXT: sb t3, 9(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb a4, 10(a0)
+; CHECK-RV64C-NEXT: sb t4, 10(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb a5, 11(a0)
+; CHECK-RV64C-NEXT: sb t5, 11(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb t2, 4(a0)
+; CHECK-RV64C-NEXT: sb a6, 4(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb t3, 5(a0)
+; CHECK-RV64C-NEXT: sb a7, 5(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb t4, 6(a0)
+; CHECK-RV64C-NEXT: sb t0, 6(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb t5, 7(a0)
+; CHECK-RV64C-NEXT: sb t1, 7(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb a6, 0(a0)
+; CHECK-RV64C-NEXT: sb a2, 0(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb a7, 1(a0)
+; CHECK-RV64C-NEXT: sb a3, 1(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb t0, 2(a0)
+; CHECK-RV64C-NEXT: sb a4, 2(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sb t1, 3(a0)
+; CHECK-RV64C-NEXT: sb a5, 3(a0)
; CHECK-RV64C-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; CHECK-RV64C-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
; CHECK-RV64C-NEXT: .cfi_restore s0
@@ -2525,24 +2525,24 @@ define void @test_nontemporal_P1_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV32C-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; CHECK-RV32C-NEXT: .cfi_offset s0, -4
; CHECK-RV32C-NEXT: .cfi_offset s1, -8
-; CHECK-RV32C-NEXT: lbu a6, 0(a1)
-; CHECK-RV32C-NEXT: lbu a7, 4(a1)
-; CHECK-RV32C-NEXT: lbu t0, 8(a1)
-; CHECK-RV32C-NEXT: lbu t1, 12(a1)
-; CHECK-RV32C-NEXT: lbu t2, 16(a1)
-; CHECK-RV32C-NEXT: lbu t3, 20(a1)
-; CHECK-RV32C-NEXT: lbu t4, 24(a1)
-; CHECK-RV32C-NEXT: lbu t5, 28(a1)
-; CHECK-RV32C-NEXT: lbu t6, 32(a1)
-; CHECK-RV32C-NEXT: lbu a3, 36(a1)
-; CHECK-RV32C-NEXT: lbu a4, 40(a1)
-; CHECK-RV32C-NEXT: lbu a5, 44(a1)
-; CHECK-RV32C-NEXT: lbu a2, 48(a1)
+; CHECK-RV32C-NEXT: lbu a2, 0(a1)
+; CHECK-RV32C-NEXT: lbu a3, 4(a1)
+; CHECK-RV32C-NEXT: lbu a4, 8(a1)
+; CHECK-RV32C-NEXT: lbu a5, 12(a1)
+; CHECK-RV32C-NEXT: lbu a6, 16(a1)
+; CHECK-RV32C-NEXT: lbu a7, 20(a1)
+; CHECK-RV32C-NEXT: lbu t0, 24(a1)
+; CHECK-RV32C-NEXT: lbu t1, 28(a1)
+; CHECK-RV32C-NEXT: lbu t2, 32(a1)
+; CHECK-RV32C-NEXT: lbu t3, 36(a1)
+; CHECK-RV32C-NEXT: lbu t4, 40(a1)
+; CHECK-RV32C-NEXT: lbu t5, 44(a1)
+; CHECK-RV32C-NEXT: lbu t6, 48(a1)
; CHECK-RV32C-NEXT: lbu s0, 52(a1)
; CHECK-RV32C-NEXT: lbu s1, 56(a1)
; CHECK-RV32C-NEXT: lbu a1, 60(a1)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb a2, 12(a0)
+; CHECK-RV32C-NEXT: sb t6, 12(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
; CHECK-RV32C-NEXT: sb s0, 13(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
@@ -2550,29 +2550,29 @@ define void @test_nontemporal_P1_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV32C-NEXT: c.ntl.p1
; CHECK-RV32C-NEXT: sb a1, 15(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb t6, 8(a0)
+; CHECK-RV32C-NEXT: sb t2, 8(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb a3, 9(a0)
+; CHECK-RV32C-NEXT: sb t3, 9(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb a4, 10(a0)
+; CHECK-RV32C-NEXT: sb t4, 10(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb a5, 11(a0)
+; CHECK-RV32C-NEXT: sb t5, 11(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb t2, 4(a0)
+; CHECK-RV32C-NEXT: sb a6, 4(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb t3, 5(a0)
+; CHECK-RV32C-NEXT: sb a7, 5(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb t4, 6(a0)
+; CHECK-RV32C-NEXT: sb t0, 6(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb t5, 7(a0)
+; CHECK-RV32C-NEXT: sb t1, 7(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb a6, 0(a0)
+; CHECK-RV32C-NEXT: sb a2, 0(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb a7, 1(a0)
+; CHECK-RV32C-NEXT: sb a3, 1(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb t0, 2(a0)
+; CHECK-RV32C-NEXT: sb a4, 2(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sb t1, 3(a0)
+; CHECK-RV32C-NEXT: sb a5, 3(a0)
; CHECK-RV32C-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; CHECK-RV32C-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; CHECK-RV32C-NEXT: .cfi_restore s0
@@ -2657,56 +2657,56 @@ define void @test_nontemporal_P1_store_v8i16(ptr %p, <8 x i16> %v) {
;
; CHECK-RV64C-LABEL: test_nontemporal_P1_store_v8i16:
; CHECK-RV64C: # %bb.0:
-; CHECK-RV64C-NEXT: lh a6, 0(a1)
-; CHECK-RV64C-NEXT: lh a7, 8(a1)
-; CHECK-RV64C-NEXT: lh t0, 16(a1)
+; CHECK-RV64C-NEXT: lh a2, 0(a1)
+; CHECK-RV64C-NEXT: lh a3, 8(a1)
+; CHECK-RV64C-NEXT: lh a4, 16(a1)
; CHECK-RV64C-NEXT: lh a5, 24(a1)
-; CHECK-RV64C-NEXT: lh a2, 32(a1)
-; CHECK-RV64C-NEXT: lh a3, 40(a1)
-; CHECK-RV64C-NEXT: lh a4, 48(a1)
+; CHECK-RV64C-NEXT: lh a6, 32(a1)
+; CHECK-RV64C-NEXT: lh a7, 40(a1)
+; CHECK-RV64C-NEXT: lh t0, 48(a1)
; CHECK-RV64C-NEXT: lh a1, 56(a1)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sh a2, 8(a0)
+; CHECK-RV64C-NEXT: sh a6, 8(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sh a3, 10(a0)
+; CHECK-RV64C-NEXT: sh a7, 10(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sh a4, 12(a0)
+; CHECK-RV64C-NEXT: sh t0, 12(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
; CHECK-RV64C-NEXT: sh a1, 14(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sh a6, 0(a0)
+; CHECK-RV64C-NEXT: sh a2, 0(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sh a7, 2(a0)
+; CHECK-RV64C-NEXT: sh a3, 2(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
-; CHECK-RV64C-NEXT: sh t0, 4(a0)
+; CHECK-RV64C-NEXT: sh a4, 4(a0)
; CHECK-RV64C-NEXT: c.ntl.p1
; CHECK-RV64C-NEXT: sh a5, 6(a0)
; CHECK-RV64C-NEXT: ret
;
; CHECK-RV32C-LABEL: test_nontemporal_P1_store_v8i16:
; CHECK-RV32C: # %bb.0:
-; CHECK-RV32C-NEXT: lh a6, 0(a1)
-; CHECK-RV32C-NEXT: lh a7, 4(a1)
-; CHECK-RV32C-NEXT: lh t0, 8(a1)
+; CHECK-RV32C-NEXT: lh a2, 0(a1)
+; CHECK-RV32C-NEXT: lh a3, 4(a1)
+; CHECK-RV32C-NEXT: lh a4, 8(a1)
; CHECK-RV32C-NEXT: lh a5, 12(a1)
-; CHECK-RV32C-NEXT: lh a2, 16(a1)
-; CHECK-RV32C-NEXT: lh a3, 20(a1)
-; CHECK-RV32C-NEXT: lh a4, 24(a1)
+; CHECK-RV32C-NEXT: lh a6, 16(a1)
+; CHECK-RV32C-NEXT: lh a7, 20(a1)
+; CHECK-RV32C-NEXT: lh t0, 24(a1)
; CHECK-RV32C-NEXT: lh a1, 28(a1)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sh a2, 8(a0)
+; CHECK-RV32C-NEXT: sh a6, 8(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sh a3, 10(a0)
+; CHECK-RV32C-NEXT: sh a7, 10(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sh a4, 12(a0)
+; CHECK-RV32C-NEXT: sh t0, 12(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
; CHECK-RV32C-NEXT: sh a1, 14(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sh a6, 0(a0)
+; CHECK-RV32C-NEXT: sh a2, 0(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sh a7, 2(a0)
+; CHECK-RV32C-NEXT: sh a3, 2(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
-; CHECK-RV32C-NEXT: sh t0, 4(a0)
+; CHECK-RV32C-NEXT: sh a4, 4(a0)
; CHECK-RV32C-NEXT: c.ntl.p1
; CHECK-RV32C-NEXT: sh a5, 6(a0)
; CHECK-RV32C-NEXT: ret
@@ -3887,24 +3887,24 @@ define void @test_nontemporal_PALL_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV64C-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
; CHECK-RV64C-NEXT: .cfi_offset s0, -8
; CHECK-RV64C-NEXT: .cfi_offset s1, -16
-; CHECK-RV64C-NEXT: lbu a6, 0(a1)
-; CHECK-RV64C-NEXT: lbu a7, 8(a1)
-; CHECK-RV64C-NEXT: lbu t0, 16(a1)
-; CHECK-RV64C-NEXT: lbu t1, 24(a1)
-; CHECK-RV64C-NEXT: lbu t2, 32(a1)
-; CHECK-RV64C-NEXT: lbu t3, 40(a1)
-; CHECK-RV64C-NEXT: lbu t4, 48(a1)
-; CHECK-RV64C-NEXT: lbu t5, 56(a1)
-; CHECK-RV64C-NEXT: lbu t6, 64(a1)
-; CHECK-RV64C-NEXT: lbu a3, 72(a1)
-; CHECK-RV64C-NEXT: lbu a4, 80(a1)
-; CHECK-RV64C-NEXT: lbu a5, 88(a1)
-; CHECK-RV64C-NEXT: lbu a2, 96(a1)
+; CHECK-RV64C-NEXT: lbu a2, 0(a1)
+; CHECK-RV64C-NEXT: lbu a3, 8(a1)
+; CHECK-RV64C-NEXT: lbu a4, 16(a1)
+; CHECK-RV64C-NEXT: lbu a5, 24(a1)
+; CHECK-RV64C-NEXT: lbu a6, 32(a1)
+; CHECK-RV64C-NEXT: lbu a7, 40(a1)
+; CHECK-RV64C-NEXT: lbu t0, 48(a1)
+; CHECK-RV64C-NEXT: lbu t1, 56(a1)
+; CHECK-RV64C-NEXT: lbu t2, 64(a1)
+; CHECK-RV64C-NEXT: lbu t3, 72(a1)
+; CHECK-RV64C-NEXT: lbu t4, 80(a1)
+; CHECK-RV64C-NEXT: lbu t5, 88(a1)
+; CHECK-RV64C-NEXT: lbu t6, 96(a1)
; CHECK-RV64C-NEXT: lbu s0, 104(a1)
; CHECK-RV64C-NEXT: lbu s1, 112(a1)
; CHECK-RV64C-NEXT: lbu a1, 120(a1)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb a2, 12(a0)
+; CHECK-RV64C-NEXT: sb t6, 12(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
; CHECK-RV64C-NEXT: sb s0, 13(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
@@ -3912,29 +3912,29 @@ define void @test_nontemporal_PALL_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV64C-NEXT: c.ntl.pall
; CHECK-RV64C-NEXT: sb a1, 15(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb t6, 8(a0)
+; CHECK-RV64C-NEXT: sb t2, 8(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb a3, 9(a0)
+; CHECK-RV64C-NEXT: sb t3, 9(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb a4, 10(a0)
+; CHECK-RV64C-NEXT: sb t4, 10(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb a5, 11(a0)
+; CHECK-RV64C-NEXT: sb t5, 11(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb t2, 4(a0)
+; CHECK-RV64C-NEXT: sb a6, 4(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb t3, 5(a0)
+; CHECK-RV64C-NEXT: sb a7, 5(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb t4, 6(a0)
+; CHECK-RV64C-NEXT: sb t0, 6(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb t5, 7(a0)
+; CHECK-RV64C-NEXT: sb t1, 7(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb a6, 0(a0)
+; CHECK-RV64C-NEXT: sb a2, 0(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb a7, 1(a0)
+; CHECK-RV64C-NEXT: sb a3, 1(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb t0, 2(a0)
+; CHECK-RV64C-NEXT: sb a4, 2(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sb t1, 3(a0)
+; CHECK-RV64C-NEXT: sb a5, 3(a0)
; CHECK-RV64C-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; CHECK-RV64C-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
; CHECK-RV64C-NEXT: .cfi_restore s0
@@ -3951,24 +3951,24 @@ define void @test_nontemporal_PALL_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV32C-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; CHECK-RV32C-NEXT: .cfi_offset s0, -4
; CHECK-RV32C-NEXT: .cfi_offset s1, -8
-; CHECK-RV32C-NEXT: lbu a6, 0(a1)
-; CHECK-RV32C-NEXT: lbu a7, 4(a1)
-; CHECK-RV32C-NEXT: lbu t0, 8(a1)
-; CHECK-RV32C-NEXT: lbu t1, 12(a1)
-; CHECK-RV32C-NEXT: lbu t2, 16(a1)
-; CHECK-RV32C-NEXT: lbu t3, 20(a1)
-; CHECK-RV32C-NEXT: lbu t4, 24(a1)
-; CHECK-RV32C-NEXT: lbu t5, 28(a1)
-; CHECK-RV32C-NEXT: lbu t6, 32(a1)
-; CHECK-RV32C-NEXT: lbu a3, 36(a1)
-; CHECK-RV32C-NEXT: lbu a4, 40(a1)
-; CHECK-RV32C-NEXT: lbu a5, 44(a1)
-; CHECK-RV32C-NEXT: lbu a2, 48(a1)
+; CHECK-RV32C-NEXT: lbu a2, 0(a1)
+; CHECK-RV32C-NEXT: lbu a3, 4(a1)
+; CHECK-RV32C-NEXT: lbu a4, 8(a1)
+; CHECK-RV32C-NEXT: lbu a5, 12(a1)
+; CHECK-RV32C-NEXT: lbu a6, 16(a1)
+; CHECK-RV32C-NEXT: lbu a7, 20(a1)
+; CHECK-RV32C-NEXT: lbu t0, 24(a1)
+; CHECK-RV32C-NEXT: lbu t1, 28(a1)
+; CHECK-RV32C-NEXT: lbu t2, 32(a1)
+; CHECK-RV32C-NEXT: lbu t3, 36(a1)
+; CHECK-RV32C-NEXT: lbu t4, 40(a1)
+; CHECK-RV32C-NEXT: lbu t5, 44(a1)
+; CHECK-RV32C-NEXT: lbu t6, 48(a1)
; CHECK-RV32C-NEXT: lbu s0, 52(a1)
; CHECK-RV32C-NEXT: lbu s1, 56(a1)
; CHECK-RV32C-NEXT: lbu a1, 60(a1)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb a2, 12(a0)
+; CHECK-RV32C-NEXT: sb t6, 12(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
; CHECK-RV32C-NEXT: sb s0, 13(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
@@ -3976,29 +3976,29 @@ define void @test_nontemporal_PALL_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV32C-NEXT: c.ntl.pall
; CHECK-RV32C-NEXT: sb a1, 15(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb t6, 8(a0)
+; CHECK-RV32C-NEXT: sb t2, 8(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb a3, 9(a0)
+; CHECK-RV32C-NEXT: sb t3, 9(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb a4, 10(a0)
+; CHECK-RV32C-NEXT: sb t4, 10(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb a5, 11(a0)
+; CHECK-RV32C-NEXT: sb t5, 11(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb t2, 4(a0)
+; CHECK-RV32C-NEXT: sb a6, 4(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb t3, 5(a0)
+; CHECK-RV32C-NEXT: sb a7, 5(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb t4, 6(a0)
+; CHECK-RV32C-NEXT: sb t0, 6(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb t5, 7(a0)
+; CHECK-RV32C-NEXT: sb t1, 7(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb a6, 0(a0)
+; CHECK-RV32C-NEXT: sb a2, 0(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb a7, 1(a0)
+; CHECK-RV32C-NEXT: sb a3, 1(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb t0, 2(a0)
+; CHECK-RV32C-NEXT: sb a4, 2(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sb t1, 3(a0)
+; CHECK-RV32C-NEXT: sb a5, 3(a0)
; CHECK-RV32C-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; CHECK-RV32C-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; CHECK-RV32C-NEXT: .cfi_restore s0
@@ -4083,56 +4083,56 @@ define void @test_nontemporal_PALL_store_v8i16(ptr %p, <8 x i16> %v) {
;
; CHECK-RV64C-LABEL: test_nontemporal_PALL_store_v8i16:
; CHECK-RV64C: # %bb.0:
-; CHECK-RV64C-NEXT: lh a6, 0(a1)
-; CHECK-RV64C-NEXT: lh a7, 8(a1)
-; CHECK-RV64C-NEXT: lh t0, 16(a1)
+; CHECK-RV64C-NEXT: lh a2, 0(a1)
+; CHECK-RV64C-NEXT: lh a3, 8(a1)
+; CHECK-RV64C-NEXT: lh a4, 16(a1)
; CHECK-RV64C-NEXT: lh a5, 24(a1)
-; CHECK-RV64C-NEXT: lh a2, 32(a1)
-; CHECK-RV64C-NEXT: lh a3, 40(a1)
-; CHECK-RV64C-NEXT: lh a4, 48(a1)
+; CHECK-RV64C-NEXT: lh a6, 32(a1)
+; CHECK-RV64C-NEXT: lh a7, 40(a1)
+; CHECK-RV64C-NEXT: lh t0, 48(a1)
; CHECK-RV64C-NEXT: lh a1, 56(a1)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sh a2, 8(a0)
+; CHECK-RV64C-NEXT: sh a6, 8(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sh a3, 10(a0)
+; CHECK-RV64C-NEXT: sh a7, 10(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sh a4, 12(a0)
+; CHECK-RV64C-NEXT: sh t0, 12(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
; CHECK-RV64C-NEXT: sh a1, 14(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sh a6, 0(a0)
+; CHECK-RV64C-NEXT: sh a2, 0(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sh a7, 2(a0)
+; CHECK-RV64C-NEXT: sh a3, 2(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
-; CHECK-RV64C-NEXT: sh t0, 4(a0)
+; CHECK-RV64C-NEXT: sh a4, 4(a0)
; CHECK-RV64C-NEXT: c.ntl.pall
; CHECK-RV64C-NEXT: sh a5, 6(a0)
; CHECK-RV64C-NEXT: ret
;
; CHECK-RV32C-LABEL: test_nontemporal_PALL_store_v8i16:
; CHECK-RV32C: # %bb.0:
-; CHECK-RV32C-NEXT: lh a6, 0(a1)
-; CHECK-RV32C-NEXT: lh a7, 4(a1)
-; CHECK-RV32C-NEXT: lh t0, 8(a1)
+; CHECK-RV32C-NEXT: lh a2, 0(a1)
+; CHECK-RV32C-NEXT: lh a3, 4(a1)
+; CHECK-RV32C-NEXT: lh a4, 8(a1)
; CHECK-RV32C-NEXT: lh a5, 12(a1)
-; CHECK-RV32C-NEXT: lh a2, 16(a1)
-; CHECK-RV32C-NEXT: lh a3, 20(a1)
-; CHECK-RV32C-NEXT: lh a4, 24(a1)
+; CHECK-RV32C-NEXT: lh a6, 16(a1)
+; CHECK-RV32C-NEXT: lh a7, 20(a1)
+; CHECK-RV32C-NEXT: lh t0, 24(a1)
; CHECK-RV32C-NEXT: lh a1, 28(a1)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sh a2, 8(a0)
+; CHECK-RV32C-NEXT: sh a6, 8(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sh a3, 10(a0)
+; CHECK-RV32C-NEXT: sh a7, 10(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sh a4, 12(a0)
+; CHECK-RV32C-NEXT: sh t0, 12(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
; CHECK-RV32C-NEXT: sh a1, 14(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sh a6, 0(a0)
+; CHECK-RV32C-NEXT: sh a2, 0(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sh a7, 2(a0)
+; CHECK-RV32C-NEXT: sh a3, 2(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
-; CHECK-RV32C-NEXT: sh t0, 4(a0)
+; CHECK-RV32C-NEXT: sh a4, 4(a0)
; CHECK-RV32C-NEXT: c.ntl.pall
; CHECK-RV32C-NEXT: sh a5, 6(a0)
; CHECK-RV32C-NEXT: ret
@@ -5313,24 +5313,24 @@ define void @test_nontemporal_S1_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV64C-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
; CHECK-RV64C-NEXT: .cfi_offset s0, -8
; CHECK-RV64C-NEXT: .cfi_offset s1, -16
-; CHECK-RV64C-NEXT: lbu a6, 0(a1)
-; CHECK-RV64C-NEXT: lbu a7, 8(a1)
-; CHECK-RV64C-NEXT: lbu t0, 16(a1)
-; CHECK-RV64C-NEXT: lbu t1, 24(a1)
-; CHECK-RV64C-NEXT: lbu t2, 32(a1)
-; CHECK-RV64C-NEXT: lbu t3, 40(a1)
-; CHECK-RV64C-NEXT: lbu t4, 48(a1)
-; CHECK-RV64C-NEXT: lbu t5, 56(a1)
-; CHECK-RV64C-NEXT: lbu t6, 64(a1)
-; CHECK-RV64C-NEXT: lbu a3, 72(a1)
-; CHECK-RV64C-NEXT: lbu a4, 80(a1)
-; CHECK-RV64C-NEXT: lbu a5, 88(a1)
-; CHECK-RV64C-NEXT: lbu a2, 96(a1)
+; CHECK-RV64C-NEXT: lbu a2, 0(a1)
+; CHECK-RV64C-NEXT: lbu a3, 8(a1)
+; CHECK-RV64C-NEXT: lbu a4, 16(a1)
+; CHECK-RV64C-NEXT: lbu a5, 24(a1)
+; CHECK-RV64C-NEXT: lbu a6, 32(a1)
+; CHECK-RV64C-NEXT: lbu a7, 40(a1)
+; CHECK-RV64C-NEXT: lbu t0, 48(a1)
+; CHECK-RV64C-NEXT: lbu t1, 56(a1)
+; CHECK-RV64C-NEXT: lbu t2, 64(a1)
+; CHECK-RV64C-NEXT: lbu t3, 72(a1)
+; CHECK-RV64C-NEXT: lbu t4, 80(a1)
+; CHECK-RV64C-NEXT: lbu t5, 88(a1)
+; CHECK-RV64C-NEXT: lbu t6, 96(a1)
; CHECK-RV64C-NEXT: lbu s0, 104(a1)
; CHECK-RV64C-NEXT: lbu s1, 112(a1)
; CHECK-RV64C-NEXT: lbu a1, 120(a1)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb a2, 12(a0)
+; CHECK-RV64C-NEXT: sb t6, 12(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
; CHECK-RV64C-NEXT: sb s0, 13(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
@@ -5338,29 +5338,29 @@ define void @test_nontemporal_S1_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV64C-NEXT: c.ntl.s1
; CHECK-RV64C-NEXT: sb a1, 15(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb t6, 8(a0)
+; CHECK-RV64C-NEXT: sb t2, 8(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb a3, 9(a0)
+; CHECK-RV64C-NEXT: sb t3, 9(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb a4, 10(a0)
+; CHECK-RV64C-NEXT: sb t4, 10(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb a5, 11(a0)
+; CHECK-RV64C-NEXT: sb t5, 11(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb t2, 4(a0)
+; CHECK-RV64C-NEXT: sb a6, 4(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb t3, 5(a0)
+; CHECK-RV64C-NEXT: sb a7, 5(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb t4, 6(a0)
+; CHECK-RV64C-NEXT: sb t0, 6(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb t5, 7(a0)
+; CHECK-RV64C-NEXT: sb t1, 7(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb a6, 0(a0)
+; CHECK-RV64C-NEXT: sb a2, 0(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb a7, 1(a0)
+; CHECK-RV64C-NEXT: sb a3, 1(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb t0, 2(a0)
+; CHECK-RV64C-NEXT: sb a4, 2(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sb t1, 3(a0)
+; CHECK-RV64C-NEXT: sb a5, 3(a0)
; CHECK-RV64C-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; CHECK-RV64C-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
; CHECK-RV64C-NEXT: .cfi_restore s0
@@ -5377,24 +5377,24 @@ define void @test_nontemporal_S1_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV32C-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; CHECK-RV32C-NEXT: .cfi_offset s0, -4
; CHECK-RV32C-NEXT: .cfi_offset s1, -8
-; CHECK-RV32C-NEXT: lbu a6, 0(a1)
-; CHECK-RV32C-NEXT: lbu a7, 4(a1)
-; CHECK-RV32C-NEXT: lbu t0, 8(a1)
-; CHECK-RV32C-NEXT: lbu t1, 12(a1)
-; CHECK-RV32C-NEXT: lbu t2, 16(a1)
-; CHECK-RV32C-NEXT: lbu t3, 20(a1)
-; CHECK-RV32C-NEXT: lbu t4, 24(a1)
-; CHECK-RV32C-NEXT: lbu t5, 28(a1)
-; CHECK-RV32C-NEXT: lbu t6, 32(a1)
-; CHECK-RV32C-NEXT: lbu a3, 36(a1)
-; CHECK-RV32C-NEXT: lbu a4, 40(a1)
-; CHECK-RV32C-NEXT: lbu a5, 44(a1)
-; CHECK-RV32C-NEXT: lbu a2, 48(a1)
+; CHECK-RV32C-NEXT: lbu a2, 0(a1)
+; CHECK-RV32C-NEXT: lbu a3, 4(a1)
+; CHECK-RV32C-NEXT: lbu a4, 8(a1)
+; CHECK-RV32C-NEXT: lbu a5, 12(a1)
+; CHECK-RV32C-NEXT: lbu a6, 16(a1)
+; CHECK-RV32C-NEXT: lbu a7, 20(a1)
+; CHECK-RV32C-NEXT: lbu t0, 24(a1)
+; CHECK-RV32C-NEXT: lbu t1, 28(a1)
+; CHECK-RV32C-NEXT: lbu t2, 32(a1)
+; CHECK-RV32C-NEXT: lbu t3, 36(a1)
+; CHECK-RV32C-NEXT: lbu t4, 40(a1)
+; CHECK-RV32C-NEXT: lbu t5, 44(a1)
+; CHECK-RV32C-NEXT: lbu t6, 48(a1)
; CHECK-RV32C-NEXT: lbu s0, 52(a1)
; CHECK-RV32C-NEXT: lbu s1, 56(a1)
; CHECK-RV32C-NEXT: lbu a1, 60(a1)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb a2, 12(a0)
+; CHECK-RV32C-NEXT: sb t6, 12(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
; CHECK-RV32C-NEXT: sb s0, 13(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
@@ -5402,29 +5402,29 @@ define void @test_nontemporal_S1_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV32C-NEXT: c.ntl.s1
; CHECK-RV32C-NEXT: sb a1, 15(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb t6, 8(a0)
+; CHECK-RV32C-NEXT: sb t2, 8(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb a3, 9(a0)
+; CHECK-RV32C-NEXT: sb t3, 9(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb a4, 10(a0)
+; CHECK-RV32C-NEXT: sb t4, 10(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb a5, 11(a0)
+; CHECK-RV32C-NEXT: sb t5, 11(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb t2, 4(a0)
+; CHECK-RV32C-NEXT: sb a6, 4(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb t3, 5(a0)
+; CHECK-RV32C-NEXT: sb a7, 5(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb t4, 6(a0)
+; CHECK-RV32C-NEXT: sb t0, 6(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb t5, 7(a0)
+; CHECK-RV32C-NEXT: sb t1, 7(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb a6, 0(a0)
+; CHECK-RV32C-NEXT: sb a2, 0(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb a7, 1(a0)
+; CHECK-RV32C-NEXT: sb a3, 1(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb t0, 2(a0)
+; CHECK-RV32C-NEXT: sb a4, 2(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sb t1, 3(a0)
+; CHECK-RV32C-NEXT: sb a5, 3(a0)
; CHECK-RV32C-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; CHECK-RV32C-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; CHECK-RV32C-NEXT: .cfi_restore s0
@@ -5509,56 +5509,56 @@ define void @test_nontemporal_S1_store_v8i16(ptr %p, <8 x i16> %v) {
;
; CHECK-RV64C-LABEL: test_nontemporal_S1_store_v8i16:
; CHECK-RV64C: # %bb.0:
-; CHECK-RV64C-NEXT: lh a6, 0(a1)
-; CHECK-RV64C-NEXT: lh a7, 8(a1)
-; CHECK-RV64C-NEXT: lh t0, 16(a1)
+; CHECK-RV64C-NEXT: lh a2, 0(a1)
+; CHECK-RV64C-NEXT: lh a3, 8(a1)
+; CHECK-RV64C-NEXT: lh a4, 16(a1)
; CHECK-RV64C-NEXT: lh a5, 24(a1)
-; CHECK-RV64C-NEXT: lh a2, 32(a1)
-; CHECK-RV64C-NEXT: lh a3, 40(a1)
-; CHECK-RV64C-NEXT: lh a4, 48(a1)
+; CHECK-RV64C-NEXT: lh a6, 32(a1)
+; CHECK-RV64C-NEXT: lh a7, 40(a1)
+; CHECK-RV64C-NEXT: lh t0, 48(a1)
; CHECK-RV64C-NEXT: lh a1, 56(a1)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sh a2, 8(a0)
+; CHECK-RV64C-NEXT: sh a6, 8(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sh a3, 10(a0)
+; CHECK-RV64C-NEXT: sh a7, 10(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sh a4, 12(a0)
+; CHECK-RV64C-NEXT: sh t0, 12(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
; CHECK-RV64C-NEXT: sh a1, 14(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sh a6, 0(a0)
+; CHECK-RV64C-NEXT: sh a2, 0(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sh a7, 2(a0)
+; CHECK-RV64C-NEXT: sh a3, 2(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
-; CHECK-RV64C-NEXT: sh t0, 4(a0)
+; CHECK-RV64C-NEXT: sh a4, 4(a0)
; CHECK-RV64C-NEXT: c.ntl.s1
; CHECK-RV64C-NEXT: sh a5, 6(a0)
; CHECK-RV64C-NEXT: ret
;
; CHECK-RV32C-LABEL: test_nontemporal_S1_store_v8i16:
; CHECK-RV32C: # %bb.0:
-; CHECK-RV32C-NEXT: lh a6, 0(a1)
-; CHECK-RV32C-NEXT: lh a7, 4(a1)
-; CHECK-RV32C-NEXT: lh t0, 8(a1)
+; CHECK-RV32C-NEXT: lh a2, 0(a1)
+; CHECK-RV32C-NEXT: lh a3, 4(a1)
+; CHECK-RV32C-NEXT: lh a4, 8(a1)
; CHECK-RV32C-NEXT: lh a5, 12(a1)
-; CHECK-RV32C-NEXT: lh a2, 16(a1)
-; CHECK-RV32C-NEXT: lh a3, 20(a1)
-; CHECK-RV32C-NEXT: lh a4, 24(a1)
+; CHECK-RV32C-NEXT: lh a6, 16(a1)
+; CHECK-RV32C-NEXT: lh a7, 20(a1)
+; CHECK-RV32C-NEXT: lh t0, 24(a1)
; CHECK-RV32C-NEXT: lh a1, 28(a1)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sh a2, 8(a0)
+; CHECK-RV32C-NEXT: sh a6, 8(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sh a3, 10(a0)
+; CHECK-RV32C-NEXT: sh a7, 10(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sh a4, 12(a0)
+; CHECK-RV32C-NEXT: sh t0, 12(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
; CHECK-RV32C-NEXT: sh a1, 14(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sh a6, 0(a0)
+; CHECK-RV32C-NEXT: sh a2, 0(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sh a7, 2(a0)
+; CHECK-RV32C-NEXT: sh a3, 2(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
-; CHECK-RV32C-NEXT: sh t0, 4(a0)
+; CHECK-RV32C-NEXT: sh a4, 4(a0)
; CHECK-RV32C-NEXT: c.ntl.s1
; CHECK-RV32C-NEXT: sh a5, 6(a0)
; CHECK-RV32C-NEXT: ret
@@ -6739,24 +6739,24 @@ define void @test_nontemporal_ALL_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV64C-NEXT: sd s1, 0(sp) # 8-byte Folded Spill
; CHECK-RV64C-NEXT: .cfi_offset s0, -8
; CHECK-RV64C-NEXT: .cfi_offset s1, -16
-; CHECK-RV64C-NEXT: lbu a6, 0(a1)
-; CHECK-RV64C-NEXT: lbu a7, 8(a1)
-; CHECK-RV64C-NEXT: lbu t0, 16(a1)
-; CHECK-RV64C-NEXT: lbu t1, 24(a1)
-; CHECK-RV64C-NEXT: lbu t2, 32(a1)
-; CHECK-RV64C-NEXT: lbu t3, 40(a1)
-; CHECK-RV64C-NEXT: lbu t4, 48(a1)
-; CHECK-RV64C-NEXT: lbu t5, 56(a1)
-; CHECK-RV64C-NEXT: lbu t6, 64(a1)
-; CHECK-RV64C-NEXT: lbu a3, 72(a1)
-; CHECK-RV64C-NEXT: lbu a4, 80(a1)
-; CHECK-RV64C-NEXT: lbu a5, 88(a1)
-; CHECK-RV64C-NEXT: lbu a2, 96(a1)
+; CHECK-RV64C-NEXT: lbu a2, 0(a1)
+; CHECK-RV64C-NEXT: lbu a3, 8(a1)
+; CHECK-RV64C-NEXT: lbu a4, 16(a1)
+; CHECK-RV64C-NEXT: lbu a5, 24(a1)
+; CHECK-RV64C-NEXT: lbu a6, 32(a1)
+; CHECK-RV64C-NEXT: lbu a7, 40(a1)
+; CHECK-RV64C-NEXT: lbu t0, 48(a1)
+; CHECK-RV64C-NEXT: lbu t1, 56(a1)
+; CHECK-RV64C-NEXT: lbu t2, 64(a1)
+; CHECK-RV64C-NEXT: lbu t3, 72(a1)
+; CHECK-RV64C-NEXT: lbu t4, 80(a1)
+; CHECK-RV64C-NEXT: lbu t5, 88(a1)
+; CHECK-RV64C-NEXT: lbu t6, 96(a1)
; CHECK-RV64C-NEXT: lbu s0, 104(a1)
; CHECK-RV64C-NEXT: lbu s1, 112(a1)
; CHECK-RV64C-NEXT: lbu a1, 120(a1)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a2, 12(a0)
+; CHECK-RV64C-NEXT: sb t6, 12(a0)
; CHECK-RV64C-NEXT: c.ntl.all
; CHECK-RV64C-NEXT: sb s0, 13(a0)
; CHECK-RV64C-NEXT: c.ntl.all
@@ -6764,29 +6764,29 @@ define void @test_nontemporal_ALL_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV64C-NEXT: c.ntl.all
; CHECK-RV64C-NEXT: sb a1, 15(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t6, 8(a0)
+; CHECK-RV64C-NEXT: sb t2, 8(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a3, 9(a0)
+; CHECK-RV64C-NEXT: sb t3, 9(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a4, 10(a0)
+; CHECK-RV64C-NEXT: sb t4, 10(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a5, 11(a0)
+; CHECK-RV64C-NEXT: sb t5, 11(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t2, 4(a0)
+; CHECK-RV64C-NEXT: sb a6, 4(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t3, 5(a0)
+; CHECK-RV64C-NEXT: sb a7, 5(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t4, 6(a0)
+; CHECK-RV64C-NEXT: sb t0, 6(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t5, 7(a0)
+; CHECK-RV64C-NEXT: sb t1, 7(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a6, 0(a0)
+; CHECK-RV64C-NEXT: sb a2, 0(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb a7, 1(a0)
+; CHECK-RV64C-NEXT: sb a3, 1(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t0, 2(a0)
+; CHECK-RV64C-NEXT: sb a4, 2(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sb t1, 3(a0)
+; CHECK-RV64C-NEXT: sb a5, 3(a0)
; CHECK-RV64C-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
; CHECK-RV64C-NEXT: ld s1, 0(sp) # 8-byte Folded Reload
; CHECK-RV64C-NEXT: .cfi_restore s0
@@ -6803,24 +6803,24 @@ define void @test_nontemporal_ALL_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV32C-NEXT: sw s1, 8(sp) # 4-byte Folded Spill
; CHECK-RV32C-NEXT: .cfi_offset s0, -4
; CHECK-RV32C-NEXT: .cfi_offset s1, -8
-; CHECK-RV32C-NEXT: lbu a6, 0(a1)
-; CHECK-RV32C-NEXT: lbu a7, 4(a1)
-; CHECK-RV32C-NEXT: lbu t0, 8(a1)
-; CHECK-RV32C-NEXT: lbu t1, 12(a1)
-; CHECK-RV32C-NEXT: lbu t2, 16(a1)
-; CHECK-RV32C-NEXT: lbu t3, 20(a1)
-; CHECK-RV32C-NEXT: lbu t4, 24(a1)
-; CHECK-RV32C-NEXT: lbu t5, 28(a1)
-; CHECK-RV32C-NEXT: lbu t6, 32(a1)
-; CHECK-RV32C-NEXT: lbu a3, 36(a1)
-; CHECK-RV32C-NEXT: lbu a4, 40(a1)
-; CHECK-RV32C-NEXT: lbu a5, 44(a1)
-; CHECK-RV32C-NEXT: lbu a2, 48(a1)
+; CHECK-RV32C-NEXT: lbu a2, 0(a1)
+; CHECK-RV32C-NEXT: lbu a3, 4(a1)
+; CHECK-RV32C-NEXT: lbu a4, 8(a1)
+; CHECK-RV32C-NEXT: lbu a5, 12(a1)
+; CHECK-RV32C-NEXT: lbu a6, 16(a1)
+; CHECK-RV32C-NEXT: lbu a7, 20(a1)
+; CHECK-RV32C-NEXT: lbu t0, 24(a1)
+; CHECK-RV32C-NEXT: lbu t1, 28(a1)
+; CHECK-RV32C-NEXT: lbu t2, 32(a1)
+; CHECK-RV32C-NEXT: lbu t3, 36(a1)
+; CHECK-RV32C-NEXT: lbu t4, 40(a1)
+; CHECK-RV32C-NEXT: lbu t5, 44(a1)
+; CHECK-RV32C-NEXT: lbu t6, 48(a1)
; CHECK-RV32C-NEXT: lbu s0, 52(a1)
; CHECK-RV32C-NEXT: lbu s1, 56(a1)
; CHECK-RV32C-NEXT: lbu a1, 60(a1)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a2, 12(a0)
+; CHECK-RV32C-NEXT: sb t6, 12(a0)
; CHECK-RV32C-NEXT: c.ntl.all
; CHECK-RV32C-NEXT: sb s0, 13(a0)
; CHECK-RV32C-NEXT: c.ntl.all
@@ -6828,29 +6828,29 @@ define void @test_nontemporal_ALL_store_v16i8(ptr %p, <16 x i8> %v) {
; CHECK-RV32C-NEXT: c.ntl.all
; CHECK-RV32C-NEXT: sb a1, 15(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t6, 8(a0)
+; CHECK-RV32C-NEXT: sb t2, 8(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a3, 9(a0)
+; CHECK-RV32C-NEXT: sb t3, 9(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a4, 10(a0)
+; CHECK-RV32C-NEXT: sb t4, 10(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a5, 11(a0)
+; CHECK-RV32C-NEXT: sb t5, 11(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t2, 4(a0)
+; CHECK-RV32C-NEXT: sb a6, 4(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t3, 5(a0)
+; CHECK-RV32C-NEXT: sb a7, 5(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t4, 6(a0)
+; CHECK-RV32C-NEXT: sb t0, 6(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t5, 7(a0)
+; CHECK-RV32C-NEXT: sb t1, 7(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a6, 0(a0)
+; CHECK-RV32C-NEXT: sb a2, 0(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb a7, 1(a0)
+; CHECK-RV32C-NEXT: sb a3, 1(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t0, 2(a0)
+; CHECK-RV32C-NEXT: sb a4, 2(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sb t1, 3(a0)
+; CHECK-RV32C-NEXT: sb a5, 3(a0)
; CHECK-RV32C-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; CHECK-RV32C-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; CHECK-RV32C-NEXT: .cfi_restore s0
@@ -6935,56 +6935,56 @@ define void @test_nontemporal_ALL_store_v8i16(ptr %p, <8 x i16> %v) {
;
; CHECK-RV64C-LABEL: test_nontemporal_ALL_store_v8i16:
; CHECK-RV64C: # %bb.0:
-; CHECK-RV64C-NEXT: lh a6, 0(a1)
-; CHECK-RV64C-NEXT: lh a7, 8(a1)
-; CHECK-RV64C-NEXT: lh t0, 16(a1)
+; CHECK-RV64C-NEXT: lh a2, 0(a1)
+; CHECK-RV64C-NEXT: lh a3, 8(a1)
+; CHECK-RV64C-NEXT: lh a4, 16(a1)
; CHECK-RV64C-NEXT: lh a5, 24(a1)
-; CHECK-RV64C-NEXT: lh a2, 32(a1)
-; CHECK-RV64C-NEXT: lh a3, 40(a1)
-; CHECK-RV64C-NEXT: lh a4, 48(a1)
+; CHECK-RV64C-NEXT: lh a6, 32(a1)
+; CHECK-RV64C-NEXT: lh a7, 40(a1)
+; CHECK-RV64C-NEXT: lh t0, 48(a1)
; CHECK-RV64C-NEXT: lh a1, 56(a1)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh a2, 8(a0)
+; CHECK-RV64C-NEXT: sh a6, 8(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh a3, 10(a0)
+; CHECK-RV64C-NEXT: sh a7, 10(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh a4, 12(a0)
+; CHECK-RV64C-NEXT: sh t0, 12(a0)
; CHECK-RV64C-NEXT: c.ntl.all
; CHECK-RV64C-NEXT: sh a1, 14(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh a6, 0(a0)
+; CHECK-RV64C-NEXT: sh a2, 0(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh a7, 2(a0)
+; CHECK-RV64C-NEXT: sh a3, 2(a0)
; CHECK-RV64C-NEXT: c.ntl.all
-; CHECK-RV64C-NEXT: sh t0, 4(a0)
+; CHECK-RV64C-NEXT: sh a4, 4(a0)
; CHECK-RV64C-NEXT: c.ntl.all
; CHECK-RV64C-NEXT: sh a5, 6(a0)
; CHECK-RV64C-NEXT: ret
;
; CHECK-RV32C-LABEL: test_nontemporal_ALL_store_v8i16:
; CHECK-RV32C: # %bb.0:
-; CHECK-RV32C-NEXT: lh a6, 0(a1)
-; CHECK-RV32C-NEXT: lh a7, 4(a1)
-; CHECK-RV32C-NEXT: lh t0, 8(a1)
+; CHECK-RV32C-NEXT: lh a2, 0(a1)
+; CHECK-RV32C-NEXT: lh a3, 4(a1)
+; CHECK-RV32C-NEXT: lh a4, 8(a1)
; CHECK-RV32C-NEXT: lh a5, 12(a1)
-; CHECK-RV32C-NEXT: lh a2, 16(a1)
-; CHECK-RV32C-NEXT: lh a3, 20(a1)
-; CHECK-RV32C-NEXT: lh a4, 24(a1)
+; CHECK-RV32C-NEXT: lh a6, 16(a1)
+; CHECK-RV32C-NEXT: lh a7, 20(a1)
+; CHECK-RV32C-NEXT: lh t0, 24(a1)
; CHECK-RV32C-NEXT: lh a1, 28(a1)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh a2, 8(a0)
+; CHECK-RV32C-NEXT: sh a6, 8(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh a3, 10(a0)
+; CHECK-RV32C-NEXT: sh a7, 10(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh a4, 12(a0)
+; CHECK-RV32C-NEXT: sh t0, 12(a0)
; CHECK-RV32C-NEXT: c.ntl.all
; CHECK-RV32C-NEXT: sh a1, 14(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh a6, 0(a0)
+; CHECK-RV32C-NEXT: sh a2, 0(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh a7, 2(a0)
+; CHECK-RV32C-NEXT: sh a3, 2(a0)
; CHECK-RV32C-NEXT: c.ntl.all
-; CHECK-RV32C-NEXT: sh t0, 4(a0)
+; CHECK-RV32C-NEXT: sh a4, 4(a0)
; CHECK-RV32C-NEXT: c.ntl.all
; CHECK-RV32C-NEXT: sh a5, 6(a0)
; CHECK-RV32C-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/push-pop-popret.ll b/llvm/test/CodeGen/RISCV/push-pop-popret.ll
index 0d289c606eff4..bcfab354e229a 100644
--- a/llvm/test/CodeGen/RISCV/push-pop-popret.ll
+++ b/llvm/test/CodeGen/RISCV/push-pop-popret.ll
@@ -803,23 +803,23 @@ define i32 @nocompress(i32 signext %size) {
; RV32IZCMP-NEXT: .cfi_def_cfa s0, 0
; RV32IZCMP-NEXT: addi a0, a0, 15
; RV32IZCMP-NEXT: andi a0, a0, -16
-; RV32IZCMP-NEXT: sub s2, sp, a0
-; RV32IZCMP-NEXT: mv sp, s2
-; RV32IZCMP-NEXT: lui s1, %hi(var)
-; RV32IZCMP-NEXT: addi s1, s1, %lo(var)
-; RV32IZCMP-NEXT: lw s3, 0(s1)
-; RV32IZCMP-NEXT: lw s4, 4(s1)
-; RV32IZCMP-NEXT: lw s5, 8(s1)
-; RV32IZCMP-NEXT: lw s6, 12(s1)
-; RV32IZCMP-NEXT: lw s7, 16(s1)
-; RV32IZCMP-NEXT: mv a0, s2
+; RV32IZCMP-NEXT: sub s1, sp, a0
+; RV32IZCMP-NEXT: mv sp, s1
+; RV32IZCMP-NEXT: lui s2, %hi(var)
+; RV32IZCMP-NEXT: addi s2, s2, %lo(var)
+; RV32IZCMP-NEXT: lw s3, 0(s2)
+; RV32IZCMP-NEXT: lw s4, 4(s2)
+; RV32IZCMP-NEXT: lw s5, 8(s2)
+; RV32IZCMP-NEXT: lw s6, 12(s2)
+; RV32IZCMP-NEXT: lw s7, 16(s2)
+; RV32IZCMP-NEXT: mv a0, s1
; RV32IZCMP-NEXT: call callee_void
-; RV32IZCMP-NEXT: sw s7, 16(s1)
-; RV32IZCMP-NEXT: sw s6, 12(s1)
-; RV32IZCMP-NEXT: sw s5, 8(s1)
-; RV32IZCMP-NEXT: sw s4, 4(s1)
-; RV32IZCMP-NEXT: sw s3, 0(s1)
-; RV32IZCMP-NEXT: mv a0, s2
+; RV32IZCMP-NEXT: sw s7, 16(s2)
+; RV32IZCMP-NEXT: sw s6, 12(s2)
+; RV32IZCMP-NEXT: sw s5, 8(s2)
+; RV32IZCMP-NEXT: sw s4, 4(s2)
+; RV32IZCMP-NEXT: sw s3, 0(s2)
+; RV32IZCMP-NEXT: mv a0, s1
; RV32IZCMP-NEXT: addi sp, s0, -48
; RV32IZCMP-NEXT: .cfi_def_cfa sp, 48
; RV32IZCMP-NEXT: cm.pop {ra, s0-s7}, 48
@@ -854,23 +854,23 @@ define i32 @nocompress(i32 signext %size) {
; RV64IZCMP-NEXT: srli a0, a0, 32
; RV64IZCMP-NEXT: addi a0, a0, 15
; RV64IZCMP-NEXT: andi a0, a0, -16
-; RV64IZCMP-NEXT: sub s2, sp, a0
-; RV64IZCMP-NEXT: mv sp, s2
-; RV64IZCMP-NEXT: lui s1, %hi(var)
-; RV64IZCMP-NEXT: addi s1, s1, %lo(var)
-; RV64IZCMP-NEXT: lw s3, 0(s1)
-; RV64IZCMP-NEXT: lw s4, 4(s1)
-; RV64IZCMP-NEXT: lw s5, 8(s1)
-; RV64IZCMP-NEXT: lw s6, 12(s1)
-; RV64IZCMP-NEXT: lw s7, 16(s1)
-; RV64IZCMP-NEXT: mv a0, s2
+; RV64IZCMP-NEXT: sub s1, sp, a0
+; RV64IZCMP-NEXT: mv sp, s1
+; RV64IZCMP-NEXT: lui s2, %hi(var)
+; RV64IZCMP-NEXT: addi s2, s2, %lo(var)
+; RV64IZCMP-NEXT: lw s3, 0(s2)
+; RV64IZCMP-NEXT: lw s4, 4(s2)
+; RV64IZCMP-NEXT: lw s5, 8(s2)
+; RV64IZCMP-NEXT: lw s6, 12(s2)
+; RV64IZCMP-NEXT: lw s7, 16(s2)
+; RV64IZCMP-NEXT: mv a0, s1
; RV64IZCMP-NEXT: call callee_void
-; RV64IZCMP-NEXT: sw s7, 16(s1)
-; RV64IZCMP-NEXT: sw s6, 12(s1)
-; RV64IZCMP-NEXT: sw s5, 8(s1)
-; RV64IZCMP-NEXT: sw s4, 4(s1)
-; RV64IZCMP-NEXT: sw s3, 0(s1)
-; RV64IZCMP-NEXT: mv a0, s2
+; RV64IZCMP-NEXT: sw s7, 16(s2)
+; RV64IZCMP-NEXT: sw s6, 12(s2)
+; RV64IZCMP-NEXT: sw s5, 8(s2)
+; RV64IZCMP-NEXT: sw s4, 4(s2)
+; RV64IZCMP-NEXT: sw s3, 0(s2)
+; RV64IZCMP-NEXT: mv a0, s1
; RV64IZCMP-NEXT: addi sp, s0, -80
; RV64IZCMP-NEXT: .cfi_def_cfa sp, 80
; RV64IZCMP-NEXT: cm.pop {ra, s0-s7}, 80
@@ -903,23 +903,23 @@ define i32 @nocompress(i32 signext %size) {
; RV32IZCMP-SR-NEXT: .cfi_def_cfa s0, 0
; RV32IZCMP-SR-NEXT: addi a0, a0, 15
; RV32IZCMP-SR-NEXT: andi a0, a0, -16
-; RV32IZCMP-SR-NEXT: sub s2, sp, a0
-; RV32IZCMP-SR-NEXT: mv sp, s2
-; RV32IZCMP-SR-NEXT: lui s1, %hi(var)
-; RV32IZCMP-SR-NEXT: addi s1, s1, %lo(var)
-; RV32IZCMP-SR-NEXT: lw s3, 0(s1)
-; RV32IZCMP-SR-NEXT: lw s4, 4(s1)
-; RV32IZCMP-SR-NEXT: lw s5, 8(s1)
-; RV32IZCMP-SR-NEXT: lw s6, 12(s1)
-; RV32IZCMP-SR-NEXT: lw s7, 16(s1)
-; RV32IZCMP-SR-NEXT: mv a0, s2
+; RV32IZCMP-SR-NEXT: sub s1, sp, a0
+; RV32IZCMP-SR-NEXT: mv sp, s1
+; RV32IZCMP-SR-NEXT: lui s2, %hi(var)
+; RV32IZCMP-SR-NEXT: addi s2, s2, %lo(var)
+; RV32IZCMP-SR-NEXT: lw s3, 0(s2)
+; RV32IZCMP-SR-NEXT: lw s4, 4(s2)
+; RV32IZCMP-SR-NEXT: lw s5, 8(s2)
+; RV32IZCMP-SR-NEXT: lw s6, 12(s2)
+; RV32IZCMP-SR-NEXT: lw s7, 16(s2)
+; RV32IZCMP-SR-NEXT: mv a0, s1
; RV32IZCMP-SR-NEXT: call callee_void
-; RV32IZCMP-SR-NEXT: sw s7, 16(s1)
-; RV32IZCMP-SR-NEXT: sw s6, 12(s1)
-; RV32IZCMP-SR-NEXT: sw s5, 8(s1)
-; RV32IZCMP-SR-NEXT: sw s4, 4(s1)
-; RV32IZCMP-SR-NEXT: sw s3, 0(s1)
-; RV32IZCMP-SR-NEXT: mv a0, s2
+; RV32IZCMP-SR-NEXT: sw s7, 16(s2)
+; RV32IZCMP-SR-NEXT: sw s6, 12(s2)
+; RV32IZCMP-SR-NEXT: sw s5, 8(s2)
+; RV32IZCMP-SR-NEXT: sw s4, 4(s2)
+; RV32IZCMP-SR-NEXT: sw s3, 0(s2)
+; RV32IZCMP-SR-NEXT: mv a0, s1
; RV32IZCMP-SR-NEXT: addi sp, s0, -48
; RV32IZCMP-SR-NEXT: .cfi_def_cfa sp, 48
; RV32IZCMP-SR-NEXT: cm.pop {ra, s0-s7}, 48
@@ -954,23 +954,23 @@ define i32 @nocompress(i32 signext %size) {
; RV64IZCMP-SR-NEXT: srli a0, a0, 32
; RV64IZCMP-SR-NEXT: addi a0, a0, 15
; RV64IZCMP-SR-NEXT: andi a0, a0, -16
-; RV64IZCMP-SR-NEXT: sub s2, sp, a0
-; RV64IZCMP-SR-NEXT: mv sp, s2
-; RV64IZCMP-SR-NEXT: lui s1, %hi(var)
-; RV64IZCMP-SR-NEXT: addi s1, s1, %lo(var)
-; RV64IZCMP-SR-NEXT: lw s3, 0(s1)
-; RV64IZCMP-SR-NEXT: lw s4, 4(s1)
-; RV64IZCMP-SR-NEXT: lw s5, 8(s1)
-; RV64IZCMP-SR-NEXT: lw s6, 12(s1)
-; RV64IZCMP-SR-NEXT: lw s7, 16(s1)
-; RV64IZCMP-SR-NEXT: mv a0, s2
+; RV64IZCMP-SR-NEXT: sub s1, sp, a0
+; RV64IZCMP-SR-NEXT: mv sp, s1
+; RV64IZCMP-SR-NEXT: lui s2, %hi(var)
+; RV64IZCMP-SR-NEXT: addi s2, s2, %lo(var)
+; RV64IZCMP-SR-NEXT: lw s3, 0(s2)
+; RV64IZCMP-SR-NEXT: lw s4, 4(s2)
+; RV64IZCMP-SR-NEXT: lw s5, 8(s2)
+; RV64IZCMP-SR-NEXT: lw s6, 12(s2)
+; RV64IZCMP-SR-NEXT: lw s7, 16(s2)
+; RV64IZCMP-SR-NEXT: mv a0, s1
; RV64IZCMP-SR-NEXT: call callee_void
-; RV64IZCMP-SR-NEXT: sw s7, 16(s1)
-; RV64IZCMP-SR-NEXT: sw s6, 12(s1)
-; RV64IZCMP-SR-NEXT: sw s5, 8(s1)
-; RV64IZCMP-SR-NEXT: sw s4, 4(s1)
-; RV64IZCMP-SR-NEXT: sw s3, 0(s1)
-; RV64IZCMP-SR-NEXT: mv a0, s2
+; RV64IZCMP-SR-NEXT: sw s7, 16(s2)
+; RV64IZCMP-SR-NEXT: sw s6, 12(s2)
+; RV64IZCMP-SR-NEXT: sw s5, 8(s2)
+; RV64IZCMP-SR-NEXT: sw s4, 4(s2)
+; RV64IZCMP-SR-NEXT: sw s3, 0(s2)
+; RV64IZCMP-SR-NEXT: mv a0, s1
; RV64IZCMP-SR-NEXT: addi sp, s0, -80
; RV64IZCMP-SR-NEXT: .cfi_def_cfa sp, 80
; RV64IZCMP-SR-NEXT: cm.pop {ra, s0-s7}, 80
@@ -1263,42 +1263,42 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV32IZCMP-NEXT: .cfi_offset s3, -4
; RV32IZCMP-NEXT: lui a0, %hi(var0)
; RV32IZCMP-NEXT: addi a0, a0, %lo(var0)
-; RV32IZCMP-NEXT: lw a6, 0(a0)
-; RV32IZCMP-NEXT: lw a7, 4(a0)
-; RV32IZCMP-NEXT: lw t0, 8(a0)
-; RV32IZCMP-NEXT: lw t1, 12(a0)
-; RV32IZCMP-NEXT: lw t2, 16(a0)
-; RV32IZCMP-NEXT: lw t3, 20(a0)
-; RV32IZCMP-NEXT: lw t4, 24(a0)
-; RV32IZCMP-NEXT: lw t5, 28(a0)
-; RV32IZCMP-NEXT: lw t6, 48(a0)
-; RV32IZCMP-NEXT: lw s2, 52(a0)
-; RV32IZCMP-NEXT: lw a1, 56(a0)
-; RV32IZCMP-NEXT: lw a2, 60(a0)
-; RV32IZCMP-NEXT: lw a3, 64(a0)
-; RV32IZCMP-NEXT: lw a4, 68(a0)
-; RV32IZCMP-NEXT: lw s3, 32(a0)
+; RV32IZCMP-NEXT: lw a1, 0(a0)
+; RV32IZCMP-NEXT: lw a2, 4(a0)
+; RV32IZCMP-NEXT: lw a3, 8(a0)
+; RV32IZCMP-NEXT: lw a4, 12(a0)
+; RV32IZCMP-NEXT: lw a5, 16(a0)
+; RV32IZCMP-NEXT: lw a6, 20(a0)
+; RV32IZCMP-NEXT: lw a7, 24(a0)
+; RV32IZCMP-NEXT: lw t0, 28(a0)
+; RV32IZCMP-NEXT: lw t1, 48(a0)
+; RV32IZCMP-NEXT: lw t2, 52(a0)
+; RV32IZCMP-NEXT: lw t3, 56(a0)
+; RV32IZCMP-NEXT: lw t4, 60(a0)
+; RV32IZCMP-NEXT: lw t5, 64(a0)
+; RV32IZCMP-NEXT: lw t6, 68(a0)
+; RV32IZCMP-NEXT: lw s0, 32(a0)
; RV32IZCMP-NEXT: lw s1, 36(a0)
-; RV32IZCMP-NEXT: lw a5, 40(a0)
-; RV32IZCMP-NEXT: lw s0, 44(a0)
-; RV32IZCMP-NEXT: sw a4, 68(a0)
-; RV32IZCMP-NEXT: sw a3, 64(a0)
-; RV32IZCMP-NEXT: sw a2, 60(a0)
-; RV32IZCMP-NEXT: sw a1, 56(a0)
-; RV32IZCMP-NEXT: sw s2, 52(a0)
-; RV32IZCMP-NEXT: sw t6, 48(a0)
-; RV32IZCMP-NEXT: sw s0, 44(a0)
-; RV32IZCMP-NEXT: sw a5, 40(a0)
+; RV32IZCMP-NEXT: lw s2, 40(a0)
+; RV32IZCMP-NEXT: lw s3, 44(a0)
+; RV32IZCMP-NEXT: sw t6, 68(a0)
+; RV32IZCMP-NEXT: sw t5, 64(a0)
+; RV32IZCMP-NEXT: sw t4, 60(a0)
+; RV32IZCMP-NEXT: sw t3, 56(a0)
+; RV32IZCMP-NEXT: sw t2, 52(a0)
+; RV32IZCMP-NEXT: sw t1, 48(a0)
+; RV32IZCMP-NEXT: sw s3, 44(a0)
+; RV32IZCMP-NEXT: sw s2, 40(a0)
; RV32IZCMP-NEXT: sw s1, 36(a0)
-; RV32IZCMP-NEXT: sw s3, 32(a0)
-; RV32IZCMP-NEXT: sw t5, 28(a0)
-; RV32IZCMP-NEXT: sw t4, 24(a0)
-; RV32IZCMP-NEXT: sw t3, 20(a0)
-; RV32IZCMP-NEXT: sw t2, 16(a0)
-; RV32IZCMP-NEXT: sw t1, 12(a0)
-; RV32IZCMP-NEXT: sw t0, 8(a0)
-; RV32IZCMP-NEXT: sw a7, 4(a0)
-; RV32IZCMP-NEXT: sw a6, 0(a0)
+; RV32IZCMP-NEXT: sw s0, 32(a0)
+; RV32IZCMP-NEXT: sw t0, 28(a0)
+; RV32IZCMP-NEXT: sw a7, 24(a0)
+; RV32IZCMP-NEXT: sw a6, 20(a0)
+; RV32IZCMP-NEXT: sw a5, 16(a0)
+; RV32IZCMP-NEXT: sw a4, 12(a0)
+; RV32IZCMP-NEXT: sw a3, 8(a0)
+; RV32IZCMP-NEXT: sw a2, 4(a0)
+; RV32IZCMP-NEXT: sw a1, 0(a0)
; RV32IZCMP-NEXT: cm.popret {ra, s0-s3}, 32
;
; RV64IZCMP-LABEL: many_args:
@@ -1311,42 +1311,42 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV64IZCMP-NEXT: .cfi_offset s3, -8
; RV64IZCMP-NEXT: lui a0, %hi(var0)
; RV64IZCMP-NEXT: addi a0, a0, %lo(var0)
-; RV64IZCMP-NEXT: lw a6, 0(a0)
-; RV64IZCMP-NEXT: lw a7, 4(a0)
-; RV64IZCMP-NEXT: lw t0, 8(a0)
-; RV64IZCMP-NEXT: lw t1, 12(a0)
-; RV64IZCMP-NEXT: lw t2, 16(a0)
-; RV64IZCMP-NEXT: lw t3, 20(a0)
-; RV64IZCMP-NEXT: lw t4, 24(a0)
-; RV64IZCMP-NEXT: lw t5, 28(a0)
-; RV64IZCMP-NEXT: lw t6, 48(a0)
-; RV64IZCMP-NEXT: lw s2, 52(a0)
-; RV64IZCMP-NEXT: lw a1, 56(a0)
-; RV64IZCMP-NEXT: lw a2, 60(a0)
-; RV64IZCMP-NEXT: lw a3, 64(a0)
-; RV64IZCMP-NEXT: lw a4, 68(a0)
-; RV64IZCMP-NEXT: lw s3, 32(a0)
+; RV64IZCMP-NEXT: lw a1, 0(a0)
+; RV64IZCMP-NEXT: lw a2, 4(a0)
+; RV64IZCMP-NEXT: lw a3, 8(a0)
+; RV64IZCMP-NEXT: lw a4, 12(a0)
+; RV64IZCMP-NEXT: lw a5, 16(a0)
+; RV64IZCMP-NEXT: lw a6, 20(a0)
+; RV64IZCMP-NEXT: lw a7, 24(a0)
+; RV64IZCMP-NEXT: lw t0, 28(a0)
+; RV64IZCMP-NEXT: lw t1, 48(a0)
+; RV64IZCMP-NEXT: lw t2, 52(a0)
+; RV64IZCMP-NEXT: lw t3, 56(a0)
+; RV64IZCMP-NEXT: lw t4, 60(a0)
+; RV64IZCMP-NEXT: lw t5, 64(a0)
+; RV64IZCMP-NEXT: lw t6, 68(a0)
+; RV64IZCMP-NEXT: lw s0, 32(a0)
; RV64IZCMP-NEXT: lw s1, 36(a0)
-; RV64IZCMP-NEXT: lw a5, 40(a0)
-; RV64IZCMP-NEXT: lw s0, 44(a0)
-; RV64IZCMP-NEXT: sw a4, 68(a0)
-; RV64IZCMP-NEXT: sw a3, 64(a0)
-; RV64IZCMP-NEXT: sw a2, 60(a0)
-; RV64IZCMP-NEXT: sw a1, 56(a0)
-; RV64IZCMP-NEXT: sw s2, 52(a0)
-; RV64IZCMP-NEXT: sw t6, 48(a0)
-; RV64IZCMP-NEXT: sw s0, 44(a0)
-; RV64IZCMP-NEXT: sw a5, 40(a0)
+; RV64IZCMP-NEXT: lw s2, 40(a0)
+; RV64IZCMP-NEXT: lw s3, 44(a0)
+; RV64IZCMP-NEXT: sw t6, 68(a0)
+; RV64IZCMP-NEXT: sw t5, 64(a0)
+; RV64IZCMP-NEXT: sw t4, 60(a0)
+; RV64IZCMP-NEXT: sw t3, 56(a0)
+; RV64IZCMP-NEXT: sw t2, 52(a0)
+; RV64IZCMP-NEXT: sw t1, 48(a0)
+; RV64IZCMP-NEXT: sw s3, 44(a0)
+; RV64IZCMP-NEXT: sw s2, 40(a0)
; RV64IZCMP-NEXT: sw s1, 36(a0)
-; RV64IZCMP-NEXT: sw s3, 32(a0)
-; RV64IZCMP-NEXT: sw t5, 28(a0)
-; RV64IZCMP-NEXT: sw t4, 24(a0)
-; RV64IZCMP-NEXT: sw t3, 20(a0)
-; RV64IZCMP-NEXT: sw t2, 16(a0)
-; RV64IZCMP-NEXT: sw t1, 12(a0)
-; RV64IZCMP-NEXT: sw t0, 8(a0)
-; RV64IZCMP-NEXT: sw a7, 4(a0)
-; RV64IZCMP-NEXT: sw a6, 0(a0)
+; RV64IZCMP-NEXT: sw s0, 32(a0)
+; RV64IZCMP-NEXT: sw t0, 28(a0)
+; RV64IZCMP-NEXT: sw a7, 24(a0)
+; RV64IZCMP-NEXT: sw a6, 20(a0)
+; RV64IZCMP-NEXT: sw a5, 16(a0)
+; RV64IZCMP-NEXT: sw a4, 12(a0)
+; RV64IZCMP-NEXT: sw a3, 8(a0)
+; RV64IZCMP-NEXT: sw a2, 4(a0)
+; RV64IZCMP-NEXT: sw a1, 0(a0)
; RV64IZCMP-NEXT: cm.popret {ra, s0-s3}, 48
;
; RV32IZCMP-SR-LABEL: many_args:
@@ -1359,42 +1359,42 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV32IZCMP-SR-NEXT: .cfi_offset s3, -4
; RV32IZCMP-SR-NEXT: lui a0, %hi(var0)
; RV32IZCMP-SR-NEXT: addi a0, a0, %lo(var0)
-; RV32IZCMP-SR-NEXT: lw a6, 0(a0)
-; RV32IZCMP-SR-NEXT: lw a7, 4(a0)
-; RV32IZCMP-SR-NEXT: lw t0, 8(a0)
-; RV32IZCMP-SR-NEXT: lw t1, 12(a0)
-; RV32IZCMP-SR-NEXT: lw t2, 16(a0)
-; RV32IZCMP-SR-NEXT: lw t3, 20(a0)
-; RV32IZCMP-SR-NEXT: lw t4, 24(a0)
-; RV32IZCMP-SR-NEXT: lw t5, 28(a0)
-; RV32IZCMP-SR-NEXT: lw t6, 48(a0)
-; RV32IZCMP-SR-NEXT: lw s2, 52(a0)
-; RV32IZCMP-SR-NEXT: lw a1, 56(a0)
-; RV32IZCMP-SR-NEXT: lw a2, 60(a0)
-; RV32IZCMP-SR-NEXT: lw a3, 64(a0)
-; RV32IZCMP-SR-NEXT: lw a4, 68(a0)
-; RV32IZCMP-SR-NEXT: lw s3, 32(a0)
+; RV32IZCMP-SR-NEXT: lw a1, 0(a0)
+; RV32IZCMP-SR-NEXT: lw a2, 4(a0)
+; RV32IZCMP-SR-NEXT: lw a3, 8(a0)
+; RV32IZCMP-SR-NEXT: lw a4, 12(a0)
+; RV32IZCMP-SR-NEXT: lw a5, 16(a0)
+; RV32IZCMP-SR-NEXT: lw a6, 20(a0)
+; RV32IZCMP-SR-NEXT: lw a7, 24(a0)
+; RV32IZCMP-SR-NEXT: lw t0, 28(a0)
+; RV32IZCMP-SR-NEXT: lw t1, 48(a0)
+; RV32IZCMP-SR-NEXT: lw t2, 52(a0)
+; RV32IZCMP-SR-NEXT: lw t3, 56(a0)
+; RV32IZCMP-SR-NEXT: lw t4, 60(a0)
+; RV32IZCMP-SR-NEXT: lw t5, 64(a0)
+; RV32IZCMP-SR-NEXT: lw t6, 68(a0)
+; RV32IZCMP-SR-NEXT: lw s0, 32(a0)
; RV32IZCMP-SR-NEXT: lw s1, 36(a0)
-; RV32IZCMP-SR-NEXT: lw a5, 40(a0)
-; RV32IZCMP-SR-NEXT: lw s0, 44(a0)
-; RV32IZCMP-SR-NEXT: sw a4, 68(a0)
-; RV32IZCMP-SR-NEXT: sw a3, 64(a0)
-; RV32IZCMP-SR-NEXT: sw a2, 60(a0)
-; RV32IZCMP-SR-NEXT: sw a1, 56(a0)
-; RV32IZCMP-SR-NEXT: sw s2, 52(a0)
-; RV32IZCMP-SR-NEXT: sw t6, 48(a0)
-; RV32IZCMP-SR-NEXT: sw s0, 44(a0)
-; RV32IZCMP-SR-NEXT: sw a5, 40(a0)
+; RV32IZCMP-SR-NEXT: lw s2, 40(a0)
+; RV32IZCMP-SR-NEXT: lw s3, 44(a0)
+; RV32IZCMP-SR-NEXT: sw t6, 68(a0)
+; RV32IZCMP-SR-NEXT: sw t5, 64(a0)
+; RV32IZCMP-SR-NEXT: sw t4, 60(a0)
+; RV32IZCMP-SR-NEXT: sw t3, 56(a0)
+; RV32IZCMP-SR-NEXT: sw t2, 52(a0)
+; RV32IZCMP-SR-NEXT: sw t1, 48(a0)
+; RV32IZCMP-SR-NEXT: sw s3, 44(a0)
+; RV32IZCMP-SR-NEXT: sw s2, 40(a0)
; RV32IZCMP-SR-NEXT: sw s1, 36(a0)
-; RV32IZCMP-SR-NEXT: sw s3, 32(a0)
-; RV32IZCMP-SR-NEXT: sw t5, 28(a0)
-; RV32IZCMP-SR-NEXT: sw t4, 24(a0)
-; RV32IZCMP-SR-NEXT: sw t3, 20(a0)
-; RV32IZCMP-SR-NEXT: sw t2, 16(a0)
-; RV32IZCMP-SR-NEXT: sw t1, 12(a0)
-; RV32IZCMP-SR-NEXT: sw t0, 8(a0)
-; RV32IZCMP-SR-NEXT: sw a7, 4(a0)
-; RV32IZCMP-SR-NEXT: sw a6, 0(a0)
+; RV32IZCMP-SR-NEXT: sw s0, 32(a0)
+; RV32IZCMP-SR-NEXT: sw t0, 28(a0)
+; RV32IZCMP-SR-NEXT: sw a7, 24(a0)
+; RV32IZCMP-SR-NEXT: sw a6, 20(a0)
+; RV32IZCMP-SR-NEXT: sw a5, 16(a0)
+; RV32IZCMP-SR-NEXT: sw a4, 12(a0)
+; RV32IZCMP-SR-NEXT: sw a3, 8(a0)
+; RV32IZCMP-SR-NEXT: sw a2, 4(a0)
+; RV32IZCMP-SR-NEXT: sw a1, 0(a0)
; RV32IZCMP-SR-NEXT: cm.popret {ra, s0-s3}, 32
;
; RV64IZCMP-SR-LABEL: many_args:
@@ -1407,42 +1407,42 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV64IZCMP-SR-NEXT: .cfi_offset s3, -8
; RV64IZCMP-SR-NEXT: lui a0, %hi(var0)
; RV64IZCMP-SR-NEXT: addi a0, a0, %lo(var0)
-; RV64IZCMP-SR-NEXT: lw a6, 0(a0)
-; RV64IZCMP-SR-NEXT: lw a7, 4(a0)
-; RV64IZCMP-SR-NEXT: lw t0, 8(a0)
-; RV64IZCMP-SR-NEXT: lw t1, 12(a0)
-; RV64IZCMP-SR-NEXT: lw t2, 16(a0)
-; RV64IZCMP-SR-NEXT: lw t3, 20(a0)
-; RV64IZCMP-SR-NEXT: lw t4, 24(a0)
-; RV64IZCMP-SR-NEXT: lw t5, 28(a0)
-; RV64IZCMP-SR-NEXT: lw t6, 48(a0)
-; RV64IZCMP-SR-NEXT: lw s2, 52(a0)
-; RV64IZCMP-SR-NEXT: lw a1, 56(a0)
-; RV64IZCMP-SR-NEXT: lw a2, 60(a0)
-; RV64IZCMP-SR-NEXT: lw a3, 64(a0)
-; RV64IZCMP-SR-NEXT: lw a4, 68(a0)
-; RV64IZCMP-SR-NEXT: lw s3, 32(a0)
+; RV64IZCMP-SR-NEXT: lw a1, 0(a0)
+; RV64IZCMP-SR-NEXT: lw a2, 4(a0)
+; RV64IZCMP-SR-NEXT: lw a3, 8(a0)
+; RV64IZCMP-SR-NEXT: lw a4, 12(a0)
+; RV64IZCMP-SR-NEXT: lw a5, 16(a0)
+; RV64IZCMP-SR-NEXT: lw a6, 20(a0)
+; RV64IZCMP-SR-NEXT: lw a7, 24(a0)
+; RV64IZCMP-SR-NEXT: lw t0, 28(a0)
+; RV64IZCMP-SR-NEXT: lw t1, 48(a0)
+; RV64IZCMP-SR-NEXT: lw t2, 52(a0)
+; RV64IZCMP-SR-NEXT: lw t3, 56(a0)
+; RV64IZCMP-SR-NEXT: lw t4, 60(a0)
+; RV64IZCMP-SR-NEXT: lw t5, 64(a0)
+; RV64IZCMP-SR-NEXT: lw t6, 68(a0)
+; RV64IZCMP-SR-NEXT: lw s0, 32(a0)
; RV64IZCMP-SR-NEXT: lw s1, 36(a0)
-; RV64IZCMP-SR-NEXT: lw a5, 40(a0)
-; RV64IZCMP-SR-NEXT: lw s0, 44(a0)
-; RV64IZCMP-SR-NEXT: sw a4, 68(a0)
-; RV64IZCMP-SR-NEXT: sw a3, 64(a0)
-; RV64IZCMP-SR-NEXT: sw a2, 60(a0)
-; RV64IZCMP-SR-NEXT: sw a1, 56(a0)
-; RV64IZCMP-SR-NEXT: sw s2, 52(a0)
-; RV64IZCMP-SR-NEXT: sw t6, 48(a0)
-; RV64IZCMP-SR-NEXT: sw s0, 44(a0)
-; RV64IZCMP-SR-NEXT: sw a5, 40(a0)
+; RV64IZCMP-SR-NEXT: lw s2, 40(a0)
+; RV64IZCMP-SR-NEXT: lw s3, 44(a0)
+; RV64IZCMP-SR-NEXT: sw t6, 68(a0)
+; RV64IZCMP-SR-NEXT: sw t5, 64(a0)
+; RV64IZCMP-SR-NEXT: sw t4, 60(a0)
+; RV64IZCMP-SR-NEXT: sw t3, 56(a0)
+; RV64IZCMP-SR-NEXT: sw t2, 52(a0)
+; RV64IZCMP-SR-NEXT: sw t1, 48(a0)
+; RV64IZCMP-SR-NEXT: sw s3, 44(a0)
+; RV64IZCMP-SR-NEXT: sw s2, 40(a0)
; RV64IZCMP-SR-NEXT: sw s1, 36(a0)
-; RV64IZCMP-SR-NEXT: sw s3, 32(a0)
-; RV64IZCMP-SR-NEXT: sw t5, 28(a0)
-; RV64IZCMP-SR-NEXT: sw t4, 24(a0)
-; RV64IZCMP-SR-NEXT: sw t3, 20(a0)
-; RV64IZCMP-SR-NEXT: sw t2, 16(a0)
-; RV64IZCMP-SR-NEXT: sw t1, 12(a0)
-; RV64IZCMP-SR-NEXT: sw t0, 8(a0)
-; RV64IZCMP-SR-NEXT: sw a7, 4(a0)
-; RV64IZCMP-SR-NEXT: sw a6, 0(a0)
+; RV64IZCMP-SR-NEXT: sw s0, 32(a0)
+; RV64IZCMP-SR-NEXT: sw t0, 28(a0)
+; RV64IZCMP-SR-NEXT: sw a7, 24(a0)
+; RV64IZCMP-SR-NEXT: sw a6, 20(a0)
+; RV64IZCMP-SR-NEXT: sw a5, 16(a0)
+; RV64IZCMP-SR-NEXT: sw a4, 12(a0)
+; RV64IZCMP-SR-NEXT: sw a3, 8(a0)
+; RV64IZCMP-SR-NEXT: sw a2, 4(a0)
+; RV64IZCMP-SR-NEXT: sw a1, 0(a0)
; RV64IZCMP-SR-NEXT: cm.popret {ra, s0-s3}, 48
;
; RV32I-LABEL: many_args:
@@ -2310,60 +2310,60 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IZCMP-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; RV32IZCMP-NEXT: lw a1, 16(a0)
; RV32IZCMP-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw t3, 20(a0)
-; RV32IZCMP-NEXT: lw t4, 24(a0)
-; RV32IZCMP-NEXT: lw t5, 28(a0)
-; RV32IZCMP-NEXT: lw t6, 32(a0)
-; RV32IZCMP-NEXT: lw s2, 36(a0)
-; RV32IZCMP-NEXT: lw s3, 40(a0)
-; RV32IZCMP-NEXT: lw s4, 44(a0)
-; RV32IZCMP-NEXT: lw s5, 48(a0)
-; RV32IZCMP-NEXT: lw s6, 52(a0)
-; RV32IZCMP-NEXT: lw s7, 56(a0)
-; RV32IZCMP-NEXT: lw s8, 60(a0)
-; RV32IZCMP-NEXT: lw s9, 64(a0)
-; RV32IZCMP-NEXT: lw s10, 68(a0)
-; RV32IZCMP-NEXT: lw s11, 72(a0)
-; RV32IZCMP-NEXT: lw ra, 76(a0)
-; RV32IZCMP-NEXT: lw t2, 80(a0)
-; RV32IZCMP-NEXT: lw s0, 84(a0)
-; RV32IZCMP-NEXT: lw s1, 88(a0)
-; RV32IZCMP-NEXT: lw t1, 92(a0)
-; RV32IZCMP-NEXT: lw t0, 112(a0)
-; RV32IZCMP-NEXT: lw a5, 116(a0)
-; RV32IZCMP-NEXT: lw a3, 120(a0)
+; RV32IZCMP-NEXT: lw a6, 20(a0)
+; RV32IZCMP-NEXT: lw a7, 24(a0)
+; RV32IZCMP-NEXT: lw t0, 28(a0)
+; RV32IZCMP-NEXT: lw t1, 32(a0)
+; RV32IZCMP-NEXT: lw t2, 36(a0)
+; RV32IZCMP-NEXT: lw t3, 40(a0)
+; RV32IZCMP-NEXT: lw t4, 44(a0)
+; RV32IZCMP-NEXT: lw t5, 48(a0)
+; RV32IZCMP-NEXT: lw t6, 52(a0)
+; RV32IZCMP-NEXT: lw s0, 56(a0)
+; RV32IZCMP-NEXT: lw s1, 60(a0)
+; RV32IZCMP-NEXT: lw s2, 64(a0)
+; RV32IZCMP-NEXT: lw s3, 68(a0)
+; RV32IZCMP-NEXT: lw s4, 72(a0)
+; RV32IZCMP-NEXT: lw s5, 76(a0)
+; RV32IZCMP-NEXT: lw s6, 80(a0)
+; RV32IZCMP-NEXT: lw s7, 84(a0)
+; RV32IZCMP-NEXT: lw s8, 88(a0)
+; RV32IZCMP-NEXT: lw s9, 92(a0)
+; RV32IZCMP-NEXT: lw s10, 112(a0)
+; RV32IZCMP-NEXT: lw s11, 116(a0)
+; RV32IZCMP-NEXT: lw ra, 120(a0)
; RV32IZCMP-NEXT: lw a1, 124(a0)
-; RV32IZCMP-NEXT: lw a7, 96(a0)
-; RV32IZCMP-NEXT: lw a6, 100(a0)
-; RV32IZCMP-NEXT: lw a4, 104(a0)
+; RV32IZCMP-NEXT: lw a5, 96(a0)
+; RV32IZCMP-NEXT: lw a4, 100(a0)
+; RV32IZCMP-NEXT: lw a3, 104(a0)
; RV32IZCMP-NEXT: lw a2, 108(a0)
; RV32IZCMP-NEXT: sw a1, 124(a0)
-; RV32IZCMP-NEXT: sw a3, 120(a0)
-; RV32IZCMP-NEXT: sw a5, 116(a0)
-; RV32IZCMP-NEXT: sw t0, 112(a0)
+; RV32IZCMP-NEXT: sw ra, 120(a0)
+; RV32IZCMP-NEXT: sw s11, 116(a0)
+; RV32IZCMP-NEXT: sw s10, 112(a0)
; RV32IZCMP-NEXT: sw a2, 108(a0)
-; RV32IZCMP-NEXT: sw a4, 104(a0)
-; RV32IZCMP-NEXT: sw a6, 100(a0)
-; RV32IZCMP-NEXT: sw a7, 96(a0)
-; RV32IZCMP-NEXT: sw t1, 92(a0)
-; RV32IZCMP-NEXT: sw s1, 88(a0)
-; RV32IZCMP-NEXT: sw s0, 84(a0)
-; RV32IZCMP-NEXT: sw t2, 80(a0)
-; RV32IZCMP-NEXT: sw ra, 76(a0)
-; RV32IZCMP-NEXT: sw s11, 72(a0)
-; RV32IZCMP-NEXT: sw s10, 68(a0)
-; RV32IZCMP-NEXT: sw s9, 64(a0)
-; RV32IZCMP-NEXT: sw s8, 60(a0)
-; RV32IZCMP-NEXT: sw s7, 56(a0)
-; RV32IZCMP-NEXT: sw s6, 52(a0)
-; RV32IZCMP-NEXT: sw s5, 48(a0)
-; RV32IZCMP-NEXT: sw s4, 44(a0)
-; RV32IZCMP-NEXT: sw s3, 40(a0)
-; RV32IZCMP-NEXT: sw s2, 36(a0)
-; RV32IZCMP-NEXT: sw t6, 32(a0)
-; RV32IZCMP-NEXT: sw t5, 28(a0)
-; RV32IZCMP-NEXT: sw t4, 24(a0)
-; RV32IZCMP-NEXT: sw t3, 20(a0)
+; RV32IZCMP-NEXT: sw a3, 104(a0)
+; RV32IZCMP-NEXT: sw a4, 100(a0)
+; RV32IZCMP-NEXT: sw a5, 96(a0)
+; RV32IZCMP-NEXT: sw s9, 92(a0)
+; RV32IZCMP-NEXT: sw s8, 88(a0)
+; RV32IZCMP-NEXT: sw s7, 84(a0)
+; RV32IZCMP-NEXT: sw s6, 80(a0)
+; RV32IZCMP-NEXT: sw s5, 76(a0)
+; RV32IZCMP-NEXT: sw s4, 72(a0)
+; RV32IZCMP-NEXT: sw s3, 68(a0)
+; RV32IZCMP-NEXT: sw s2, 64(a0)
+; RV32IZCMP-NEXT: sw s1, 60(a0)
+; RV32IZCMP-NEXT: sw s0, 56(a0)
+; RV32IZCMP-NEXT: sw t6, 52(a0)
+; RV32IZCMP-NEXT: sw t5, 48(a0)
+; RV32IZCMP-NEXT: sw t4, 44(a0)
+; RV32IZCMP-NEXT: sw t3, 40(a0)
+; RV32IZCMP-NEXT: sw t2, 36(a0)
+; RV32IZCMP-NEXT: sw t1, 32(a0)
+; RV32IZCMP-NEXT: sw t0, 28(a0)
+; RV32IZCMP-NEXT: sw a7, 24(a0)
+; RV32IZCMP-NEXT: sw a6, 20(a0)
; RV32IZCMP-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; RV32IZCMP-NEXT: sw a1, 16(a0)
; RV32IZCMP-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
@@ -2484,60 +2484,60 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IZCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
; RV64IZCMP-NEXT: lw a1, 16(a0)
; RV64IZCMP-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw t3, 20(a0)
-; RV64IZCMP-NEXT: lw t4, 24(a0)
-; RV64IZCMP-NEXT: lw t5, 28(a0)
-; RV64IZCMP-NEXT: lw t6, 32(a0)
-; RV64IZCMP-NEXT: lw s2, 36(a0)
-; RV64IZCMP-NEXT: lw s3, 40(a0)
-; RV64IZCMP-NEXT: lw s4, 44(a0)
-; RV64IZCMP-NEXT: lw s5, 48(a0)
-; RV64IZCMP-NEXT: lw s6, 52(a0)
-; RV64IZCMP-NEXT: lw s7, 56(a0)
-; RV64IZCMP-NEXT: lw s8, 60(a0)
-; RV64IZCMP-NEXT: lw s9, 64(a0)
-; RV64IZCMP-NEXT: lw s10, 68(a0)
-; RV64IZCMP-NEXT: lw s11, 72(a0)
-; RV64IZCMP-NEXT: lw ra, 76(a0)
-; RV64IZCMP-NEXT: lw t2, 80(a0)
-; RV64IZCMP-NEXT: lw s0, 84(a0)
-; RV64IZCMP-NEXT: lw s1, 88(a0)
-; RV64IZCMP-NEXT: lw t1, 92(a0)
-; RV64IZCMP-NEXT: lw t0, 112(a0)
-; RV64IZCMP-NEXT: lw a5, 116(a0)
-; RV64IZCMP-NEXT: lw a3, 120(a0)
+; RV64IZCMP-NEXT: lw a6, 20(a0)
+; RV64IZCMP-NEXT: lw a7, 24(a0)
+; RV64IZCMP-NEXT: lw t0, 28(a0)
+; RV64IZCMP-NEXT: lw t1, 32(a0)
+; RV64IZCMP-NEXT: lw t2, 36(a0)
+; RV64IZCMP-NEXT: lw t3, 40(a0)
+; RV64IZCMP-NEXT: lw t4, 44(a0)
+; RV64IZCMP-NEXT: lw t5, 48(a0)
+; RV64IZCMP-NEXT: lw t6, 52(a0)
+; RV64IZCMP-NEXT: lw s0, 56(a0)
+; RV64IZCMP-NEXT: lw s1, 60(a0)
+; RV64IZCMP-NEXT: lw s2, 64(a0)
+; RV64IZCMP-NEXT: lw s3, 68(a0)
+; RV64IZCMP-NEXT: lw s4, 72(a0)
+; RV64IZCMP-NEXT: lw s5, 76(a0)
+; RV64IZCMP-NEXT: lw s6, 80(a0)
+; RV64IZCMP-NEXT: lw s7, 84(a0)
+; RV64IZCMP-NEXT: lw s8, 88(a0)
+; RV64IZCMP-NEXT: lw s9, 92(a0)
+; RV64IZCMP-NEXT: lw s10, 112(a0)
+; RV64IZCMP-NEXT: lw s11, 116(a0)
+; RV64IZCMP-NEXT: lw ra, 120(a0)
; RV64IZCMP-NEXT: lw a1, 124(a0)
-; RV64IZCMP-NEXT: lw a7, 96(a0)
-; RV64IZCMP-NEXT: lw a6, 100(a0)
-; RV64IZCMP-NEXT: lw a4, 104(a0)
+; RV64IZCMP-NEXT: lw a5, 96(a0)
+; RV64IZCMP-NEXT: lw a4, 100(a0)
+; RV64IZCMP-NEXT: lw a3, 104(a0)
; RV64IZCMP-NEXT: lw a2, 108(a0)
; RV64IZCMP-NEXT: sw a1, 124(a0)
-; RV64IZCMP-NEXT: sw a3, 120(a0)
-; RV64IZCMP-NEXT: sw a5, 116(a0)
-; RV64IZCMP-NEXT: sw t0, 112(a0)
+; RV64IZCMP-NEXT: sw ra, 120(a0)
+; RV64IZCMP-NEXT: sw s11, 116(a0)
+; RV64IZCMP-NEXT: sw s10, 112(a0)
; RV64IZCMP-NEXT: sw a2, 108(a0)
-; RV64IZCMP-NEXT: sw a4, 104(a0)
-; RV64IZCMP-NEXT: sw a6, 100(a0)
-; RV64IZCMP-NEXT: sw a7, 96(a0)
-; RV64IZCMP-NEXT: sw t1, 92(a0)
-; RV64IZCMP-NEXT: sw s1, 88(a0)
-; RV64IZCMP-NEXT: sw s0, 84(a0)
-; RV64IZCMP-NEXT: sw t2, 80(a0)
-; RV64IZCMP-NEXT: sw ra, 76(a0)
-; RV64IZCMP-NEXT: sw s11, 72(a0)
-; RV64IZCMP-NEXT: sw s10, 68(a0)
-; RV64IZCMP-NEXT: sw s9, 64(a0)
-; RV64IZCMP-NEXT: sw s8, 60(a0)
-; RV64IZCMP-NEXT: sw s7, 56(a0)
-; RV64IZCMP-NEXT: sw s6, 52(a0)
-; RV64IZCMP-NEXT: sw s5, 48(a0)
-; RV64IZCMP-NEXT: sw s4, 44(a0)
-; RV64IZCMP-NEXT: sw s3, 40(a0)
-; RV64IZCMP-NEXT: sw s2, 36(a0)
-; RV64IZCMP-NEXT: sw t6, 32(a0)
-; RV64IZCMP-NEXT: sw t5, 28(a0)
-; RV64IZCMP-NEXT: sw t4, 24(a0)
-; RV64IZCMP-NEXT: sw t3, 20(a0)
+; RV64IZCMP-NEXT: sw a3, 104(a0)
+; RV64IZCMP-NEXT: sw a4, 100(a0)
+; RV64IZCMP-NEXT: sw a5, 96(a0)
+; RV64IZCMP-NEXT: sw s9, 92(a0)
+; RV64IZCMP-NEXT: sw s8, 88(a0)
+; RV64IZCMP-NEXT: sw s7, 84(a0)
+; RV64IZCMP-NEXT: sw s6, 80(a0)
+; RV64IZCMP-NEXT: sw s5, 76(a0)
+; RV64IZCMP-NEXT: sw s4, 72(a0)
+; RV64IZCMP-NEXT: sw s3, 68(a0)
+; RV64IZCMP-NEXT: sw s2, 64(a0)
+; RV64IZCMP-NEXT: sw s1, 60(a0)
+; RV64IZCMP-NEXT: sw s0, 56(a0)
+; RV64IZCMP-NEXT: sw t6, 52(a0)
+; RV64IZCMP-NEXT: sw t5, 48(a0)
+; RV64IZCMP-NEXT: sw t4, 44(a0)
+; RV64IZCMP-NEXT: sw t3, 40(a0)
+; RV64IZCMP-NEXT: sw t2, 36(a0)
+; RV64IZCMP-NEXT: sw t1, 32(a0)
+; RV64IZCMP-NEXT: sw t0, 28(a0)
+; RV64IZCMP-NEXT: sw a7, 24(a0)
+; RV64IZCMP-NEXT: sw a6, 20(a0)
; RV64IZCMP-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
; RV64IZCMP-NEXT: sw a1, 16(a0)
; RV64IZCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
@@ -2658,60 +2658,60 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IZCMP-SR-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; RV32IZCMP-SR-NEXT: lw a1, 16(a0)
; RV32IZCMP-SR-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw t3, 20(a0)
-; RV32IZCMP-SR-NEXT: lw t4, 24(a0)
-; RV32IZCMP-SR-NEXT: lw t5, 28(a0)
-; RV32IZCMP-SR-NEXT: lw t6, 32(a0)
-; RV32IZCMP-SR-NEXT: lw s2, 36(a0)
-; RV32IZCMP-SR-NEXT: lw s3, 40(a0)
-; RV32IZCMP-SR-NEXT: lw s4, 44(a0)
-; RV32IZCMP-SR-NEXT: lw s5, 48(a0)
-; RV32IZCMP-SR-NEXT: lw s6, 52(a0)
-; RV32IZCMP-SR-NEXT: lw s7, 56(a0)
-; RV32IZCMP-SR-NEXT: lw s8, 60(a0)
-; RV32IZCMP-SR-NEXT: lw s9, 64(a0)
-; RV32IZCMP-SR-NEXT: lw s10, 68(a0)
-; RV32IZCMP-SR-NEXT: lw s11, 72(a0)
-; RV32IZCMP-SR-NEXT: lw ra, 76(a0)
-; RV32IZCMP-SR-NEXT: lw t2, 80(a0)
-; RV32IZCMP-SR-NEXT: lw s0, 84(a0)
-; RV32IZCMP-SR-NEXT: lw s1, 88(a0)
-; RV32IZCMP-SR-NEXT: lw t1, 92(a0)
-; RV32IZCMP-SR-NEXT: lw t0, 112(a0)
-; RV32IZCMP-SR-NEXT: lw a5, 116(a0)
-; RV32IZCMP-SR-NEXT: lw a3, 120(a0)
+; RV32IZCMP-SR-NEXT: lw a6, 20(a0)
+; RV32IZCMP-SR-NEXT: lw a7, 24(a0)
+; RV32IZCMP-SR-NEXT: lw t0, 28(a0)
+; RV32IZCMP-SR-NEXT: lw t1, 32(a0)
+; RV32IZCMP-SR-NEXT: lw t2, 36(a0)
+; RV32IZCMP-SR-NEXT: lw t3, 40(a0)
+; RV32IZCMP-SR-NEXT: lw t4, 44(a0)
+; RV32IZCMP-SR-NEXT: lw t5, 48(a0)
+; RV32IZCMP-SR-NEXT: lw t6, 52(a0)
+; RV32IZCMP-SR-NEXT: lw s0, 56(a0)
+; RV32IZCMP-SR-NEXT: lw s1, 60(a0)
+; RV32IZCMP-SR-NEXT: lw s2, 64(a0)
+; RV32IZCMP-SR-NEXT: lw s3, 68(a0)
+; RV32IZCMP-SR-NEXT: lw s4, 72(a0)
+; RV32IZCMP-SR-NEXT: lw s5, 76(a0)
+; RV32IZCMP-SR-NEXT: lw s6, 80(a0)
+; RV32IZCMP-SR-NEXT: lw s7, 84(a0)
+; RV32IZCMP-SR-NEXT: lw s8, 88(a0)
+; RV32IZCMP-SR-NEXT: lw s9, 92(a0)
+; RV32IZCMP-SR-NEXT: lw s10, 112(a0)
+; RV32IZCMP-SR-NEXT: lw s11, 116(a0)
+; RV32IZCMP-SR-NEXT: lw ra, 120(a0)
; RV32IZCMP-SR-NEXT: lw a1, 124(a0)
-; RV32IZCMP-SR-NEXT: lw a7, 96(a0)
-; RV32IZCMP-SR-NEXT: lw a6, 100(a0)
-; RV32IZCMP-SR-NEXT: lw a4, 104(a0)
+; RV32IZCMP-SR-NEXT: lw a5, 96(a0)
+; RV32IZCMP-SR-NEXT: lw a4, 100(a0)
+; RV32IZCMP-SR-NEXT: lw a3, 104(a0)
; RV32IZCMP-SR-NEXT: lw a2, 108(a0)
; RV32IZCMP-SR-NEXT: sw a1, 124(a0)
-; RV32IZCMP-SR-NEXT: sw a3, 120(a0)
-; RV32IZCMP-SR-NEXT: sw a5, 116(a0)
-; RV32IZCMP-SR-NEXT: sw t0, 112(a0)
+; RV32IZCMP-SR-NEXT: sw ra, 120(a0)
+; RV32IZCMP-SR-NEXT: sw s11, 116(a0)
+; RV32IZCMP-SR-NEXT: sw s10, 112(a0)
; RV32IZCMP-SR-NEXT: sw a2, 108(a0)
-; RV32IZCMP-SR-NEXT: sw a4, 104(a0)
-; RV32IZCMP-SR-NEXT: sw a6, 100(a0)
-; RV32IZCMP-SR-NEXT: sw a7, 96(a0)
-; RV32IZCMP-SR-NEXT: sw t1, 92(a0)
-; RV32IZCMP-SR-NEXT: sw s1, 88(a0)
-; RV32IZCMP-SR-NEXT: sw s0, 84(a0)
-; RV32IZCMP-SR-NEXT: sw t2, 80(a0)
-; RV32IZCMP-SR-NEXT: sw ra, 76(a0)
-; RV32IZCMP-SR-NEXT: sw s11, 72(a0)
-; RV32IZCMP-SR-NEXT: sw s10, 68(a0)
-; RV32IZCMP-SR-NEXT: sw s9, 64(a0)
-; RV32IZCMP-SR-NEXT: sw s8, 60(a0)
-; RV32IZCMP-SR-NEXT: sw s7, 56(a0)
-; RV32IZCMP-SR-NEXT: sw s6, 52(a0)
-; RV32IZCMP-SR-NEXT: sw s5, 48(a0)
-; RV32IZCMP-SR-NEXT: sw s4, 44(a0)
-; RV32IZCMP-SR-NEXT: sw s3, 40(a0)
-; RV32IZCMP-SR-NEXT: sw s2, 36(a0)
-; RV32IZCMP-SR-NEXT: sw t6, 32(a0)
-; RV32IZCMP-SR-NEXT: sw t5, 28(a0)
-; RV32IZCMP-SR-NEXT: sw t4, 24(a0)
-; RV32IZCMP-SR-NEXT: sw t3, 20(a0)
+; RV32IZCMP-SR-NEXT: sw a3, 104(a0)
+; RV32IZCMP-SR-NEXT: sw a4, 100(a0)
+; RV32IZCMP-SR-NEXT: sw a5, 96(a0)
+; RV32IZCMP-SR-NEXT: sw s9, 92(a0)
+; RV32IZCMP-SR-NEXT: sw s8, 88(a0)
+; RV32IZCMP-SR-NEXT: sw s7, 84(a0)
+; RV32IZCMP-SR-NEXT: sw s6, 80(a0)
+; RV32IZCMP-SR-NEXT: sw s5, 76(a0)
+; RV32IZCMP-SR-NEXT: sw s4, 72(a0)
+; RV32IZCMP-SR-NEXT: sw s3, 68(a0)
+; RV32IZCMP-SR-NEXT: sw s2, 64(a0)
+; RV32IZCMP-SR-NEXT: sw s1, 60(a0)
+; RV32IZCMP-SR-NEXT: sw s0, 56(a0)
+; RV32IZCMP-SR-NEXT: sw t6, 52(a0)
+; RV32IZCMP-SR-NEXT: sw t5, 48(a0)
+; RV32IZCMP-SR-NEXT: sw t4, 44(a0)
+; RV32IZCMP-SR-NEXT: sw t3, 40(a0)
+; RV32IZCMP-SR-NEXT: sw t2, 36(a0)
+; RV32IZCMP-SR-NEXT: sw t1, 32(a0)
+; RV32IZCMP-SR-NEXT: sw t0, 28(a0)
+; RV32IZCMP-SR-NEXT: sw a7, 24(a0)
+; RV32IZCMP-SR-NEXT: sw a6, 20(a0)
; RV32IZCMP-SR-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; RV32IZCMP-SR-NEXT: sw a1, 16(a0)
; RV32IZCMP-SR-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
@@ -2832,60 +2832,60 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IZCMP-SR-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
; RV64IZCMP-SR-NEXT: lw a1, 16(a0)
; RV64IZCMP-SR-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw t3, 20(a0)
-; RV64IZCMP-SR-NEXT: lw t4, 24(a0)
-; RV64IZCMP-SR-NEXT: lw t5, 28(a0)
-; RV64IZCMP-SR-NEXT: lw t6, 32(a0)
-; RV64IZCMP-SR-NEXT: lw s2, 36(a0)
-; RV64IZCMP-SR-NEXT: lw s3, 40(a0)
-; RV64IZCMP-SR-NEXT: lw s4, 44(a0)
-; RV64IZCMP-SR-NEXT: lw s5, 48(a0)
-; RV64IZCMP-SR-NEXT: lw s6, 52(a0)
-; RV64IZCMP-SR-NEXT: lw s7, 56(a0)
-; RV64IZCMP-SR-NEXT: lw s8, 60(a0)
-; RV64IZCMP-SR-NEXT: lw s9, 64(a0)
-; RV64IZCMP-SR-NEXT: lw s10, 68(a0)
-; RV64IZCMP-SR-NEXT: lw s11, 72(a0)
-; RV64IZCMP-SR-NEXT: lw ra, 76(a0)
-; RV64IZCMP-SR-NEXT: lw t2, 80(a0)
-; RV64IZCMP-SR-NEXT: lw s0, 84(a0)
-; RV64IZCMP-SR-NEXT: lw s1, 88(a0)
-; RV64IZCMP-SR-NEXT: lw t1, 92(a0)
-; RV64IZCMP-SR-NEXT: lw t0, 112(a0)
-; RV64IZCMP-SR-NEXT: lw a5, 116(a0)
-; RV64IZCMP-SR-NEXT: lw a3, 120(a0)
+; RV64IZCMP-SR-NEXT: lw a6, 20(a0)
+; RV64IZCMP-SR-NEXT: lw a7, 24(a0)
+; RV64IZCMP-SR-NEXT: lw t0, 28(a0)
+; RV64IZCMP-SR-NEXT: lw t1, 32(a0)
+; RV64IZCMP-SR-NEXT: lw t2, 36(a0)
+; RV64IZCMP-SR-NEXT: lw t3, 40(a0)
+; RV64IZCMP-SR-NEXT: lw t4, 44(a0)
+; RV64IZCMP-SR-NEXT: lw t5, 48(a0)
+; RV64IZCMP-SR-NEXT: lw t6, 52(a0)
+; RV64IZCMP-SR-NEXT: lw s0, 56(a0)
+; RV64IZCMP-SR-NEXT: lw s1, 60(a0)
+; RV64IZCMP-SR-NEXT: lw s2, 64(a0)
+; RV64IZCMP-SR-NEXT: lw s3, 68(a0)
+; RV64IZCMP-SR-NEXT: lw s4, 72(a0)
+; RV64IZCMP-SR-NEXT: lw s5, 76(a0)
+; RV64IZCMP-SR-NEXT: lw s6, 80(a0)
+; RV64IZCMP-SR-NEXT: lw s7, 84(a0)
+; RV64IZCMP-SR-NEXT: lw s8, 88(a0)
+; RV64IZCMP-SR-NEXT: lw s9, 92(a0)
+; RV64IZCMP-SR-NEXT: lw s10, 112(a0)
+; RV64IZCMP-SR-NEXT: lw s11, 116(a0)
+; RV64IZCMP-SR-NEXT: lw ra, 120(a0)
; RV64IZCMP-SR-NEXT: lw a1, 124(a0)
-; RV64IZCMP-SR-NEXT: lw a7, 96(a0)
-; RV64IZCMP-SR-NEXT: lw a6, 100(a0)
-; RV64IZCMP-SR-NEXT: lw a4, 104(a0)
+; RV64IZCMP-SR-NEXT: lw a5, 96(a0)
+; RV64IZCMP-SR-NEXT: lw a4, 100(a0)
+; RV64IZCMP-SR-NEXT: lw a3, 104(a0)
; RV64IZCMP-SR-NEXT: lw a2, 108(a0)
; RV64IZCMP-SR-NEXT: sw a1, 124(a0)
-; RV64IZCMP-SR-NEXT: sw a3, 120(a0)
-; RV64IZCMP-SR-NEXT: sw a5, 116(a0)
-; RV64IZCMP-SR-NEXT: sw t0, 112(a0)
+; RV64IZCMP-SR-NEXT: sw ra, 120(a0)
+; RV64IZCMP-SR-NEXT: sw s11, 116(a0)
+; RV64IZCMP-SR-NEXT: sw s10, 112(a0)
; RV64IZCMP-SR-NEXT: sw a2, 108(a0)
-; RV64IZCMP-SR-NEXT: sw a4, 104(a0)
-; RV64IZCMP-SR-NEXT: sw a6, 100(a0)
-; RV64IZCMP-SR-NEXT: sw a7, 96(a0)
-; RV64IZCMP-SR-NEXT: sw t1, 92(a0)
-; RV64IZCMP-SR-NEXT: sw s1, 88(a0)
-; RV64IZCMP-SR-NEXT: sw s0, 84(a0)
-; RV64IZCMP-SR-NEXT: sw t2, 80(a0)
-; RV64IZCMP-SR-NEXT: sw ra, 76(a0)
-; RV64IZCMP-SR-NEXT: sw s11, 72(a0)
-; RV64IZCMP-SR-NEXT: sw s10, 68(a0)
-; RV64IZCMP-SR-NEXT: sw s9, 64(a0)
-; RV64IZCMP-SR-NEXT: sw s8, 60(a0)
-; RV64IZCMP-SR-NEXT: sw s7, 56(a0)
-; RV64IZCMP-SR-NEXT: sw s6, 52(a0)
-; RV64IZCMP-SR-NEXT: sw s5, 48(a0)
-; RV64IZCMP-SR-NEXT: sw s4, 44(a0)
-; RV64IZCMP-SR-NEXT: sw s3, 40(a0)
-; RV64IZCMP-SR-NEXT: sw s2, 36(a0)
-; RV64IZCMP-SR-NEXT: sw t6, 32(a0)
-; RV64IZCMP-SR-NEXT: sw t5, 28(a0)
-; RV64IZCMP-SR-NEXT: sw t4, 24(a0)
-; RV64IZCMP-SR-NEXT: sw t3, 20(a0)
+; RV64IZCMP-SR-NEXT: sw a3, 104(a0)
+; RV64IZCMP-SR-NEXT: sw a4, 100(a0)
+; RV64IZCMP-SR-NEXT: sw a5, 96(a0)
+; RV64IZCMP-SR-NEXT: sw s9, 92(a0)
+; RV64IZCMP-SR-NEXT: sw s8, 88(a0)
+; RV64IZCMP-SR-NEXT: sw s7, 84(a0)
+; RV64IZCMP-SR-NEXT: sw s6, 80(a0)
+; RV64IZCMP-SR-NEXT: sw s5, 76(a0)
+; RV64IZCMP-SR-NEXT: sw s4, 72(a0)
+; RV64IZCMP-SR-NEXT: sw s3, 68(a0)
+; RV64IZCMP-SR-NEXT: sw s2, 64(a0)
+; RV64IZCMP-SR-NEXT: sw s1, 60(a0)
+; RV64IZCMP-SR-NEXT: sw s0, 56(a0)
+; RV64IZCMP-SR-NEXT: sw t6, 52(a0)
+; RV64IZCMP-SR-NEXT: sw t5, 48(a0)
+; RV64IZCMP-SR-NEXT: sw t4, 44(a0)
+; RV64IZCMP-SR-NEXT: sw t3, 40(a0)
+; RV64IZCMP-SR-NEXT: sw t2, 36(a0)
+; RV64IZCMP-SR-NEXT: sw t1, 32(a0)
+; RV64IZCMP-SR-NEXT: sw t0, 28(a0)
+; RV64IZCMP-SR-NEXT: sw a7, 24(a0)
+; RV64IZCMP-SR-NEXT: sw a6, 20(a0)
; RV64IZCMP-SR-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
; RV64IZCMP-SR-NEXT: sw a1, 16(a0)
; RV64IZCMP-SR-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
@@ -3371,60 +3371,60 @@ define void @callee_no_irq() {
; RV32IZCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; RV32IZCMP-NEXT: lw a1, 16(a0)
; RV32IZCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-NEXT: lw t3, 20(a0)
-; RV32IZCMP-NEXT: lw t4, 24(a0)
-; RV32IZCMP-NEXT: lw t5, 28(a0)
-; RV32IZCMP-NEXT: lw t6, 32(a0)
-; RV32IZCMP-NEXT: lw s2, 36(a0)
-; RV32IZCMP-NEXT: lw s3, 40(a0)
-; RV32IZCMP-NEXT: lw s4, 44(a0)
-; RV32IZCMP-NEXT: lw s5, 48(a0)
-; RV32IZCMP-NEXT: lw s6, 52(a0)
-; RV32IZCMP-NEXT: lw s7, 56(a0)
-; RV32IZCMP-NEXT: lw s8, 60(a0)
-; RV32IZCMP-NEXT: lw s9, 64(a0)
-; RV32IZCMP-NEXT: lw s10, 68(a0)
-; RV32IZCMP-NEXT: lw s11, 72(a0)
-; RV32IZCMP-NEXT: lw ra, 76(a0)
-; RV32IZCMP-NEXT: lw t2, 80(a0)
-; RV32IZCMP-NEXT: lw s0, 84(a0)
-; RV32IZCMP-NEXT: lw s1, 88(a0)
-; RV32IZCMP-NEXT: lw t1, 92(a0)
-; RV32IZCMP-NEXT: lw t0, 112(a0)
-; RV32IZCMP-NEXT: lw a5, 116(a0)
-; RV32IZCMP-NEXT: lw a3, 120(a0)
+; RV32IZCMP-NEXT: lw a6, 20(a0)
+; RV32IZCMP-NEXT: lw a7, 24(a0)
+; RV32IZCMP-NEXT: lw t0, 28(a0)
+; RV32IZCMP-NEXT: lw t1, 32(a0)
+; RV32IZCMP-NEXT: lw t2, 36(a0)
+; RV32IZCMP-NEXT: lw t3, 40(a0)
+; RV32IZCMP-NEXT: lw t4, 44(a0)
+; RV32IZCMP-NEXT: lw t5, 48(a0)
+; RV32IZCMP-NEXT: lw t6, 52(a0)
+; RV32IZCMP-NEXT: lw s0, 56(a0)
+; RV32IZCMP-NEXT: lw s1, 60(a0)
+; RV32IZCMP-NEXT: lw s2, 64(a0)
+; RV32IZCMP-NEXT: lw s3, 68(a0)
+; RV32IZCMP-NEXT: lw s4, 72(a0)
+; RV32IZCMP-NEXT: lw s5, 76(a0)
+; RV32IZCMP-NEXT: lw s6, 80(a0)
+; RV32IZCMP-NEXT: lw s7, 84(a0)
+; RV32IZCMP-NEXT: lw s8, 88(a0)
+; RV32IZCMP-NEXT: lw s9, 92(a0)
+; RV32IZCMP-NEXT: lw s10, 112(a0)
+; RV32IZCMP-NEXT: lw s11, 116(a0)
+; RV32IZCMP-NEXT: lw ra, 120(a0)
; RV32IZCMP-NEXT: lw a1, 124(a0)
-; RV32IZCMP-NEXT: lw a7, 96(a0)
-; RV32IZCMP-NEXT: lw a6, 100(a0)
-; RV32IZCMP-NEXT: lw a4, 104(a0)
+; RV32IZCMP-NEXT: lw a5, 96(a0)
+; RV32IZCMP-NEXT: lw a4, 100(a0)
+; RV32IZCMP-NEXT: lw a3, 104(a0)
; RV32IZCMP-NEXT: lw a2, 108(a0)
; RV32IZCMP-NEXT: sw a1, 124(a0)
-; RV32IZCMP-NEXT: sw a3, 120(a0)
-; RV32IZCMP-NEXT: sw a5, 116(a0)
-; RV32IZCMP-NEXT: sw t0, 112(a0)
+; RV32IZCMP-NEXT: sw ra, 120(a0)
+; RV32IZCMP-NEXT: sw s11, 116(a0)
+; RV32IZCMP-NEXT: sw s10, 112(a0)
; RV32IZCMP-NEXT: sw a2, 108(a0)
-; RV32IZCMP-NEXT: sw a4, 104(a0)
-; RV32IZCMP-NEXT: sw a6, 100(a0)
-; RV32IZCMP-NEXT: sw a7, 96(a0)
-; RV32IZCMP-NEXT: sw t1, 92(a0)
-; RV32IZCMP-NEXT: sw s1, 88(a0)
-; RV32IZCMP-NEXT: sw s0, 84(a0)
-; RV32IZCMP-NEXT: sw t2, 80(a0)
-; RV32IZCMP-NEXT: sw ra, 76(a0)
-; RV32IZCMP-NEXT: sw s11, 72(a0)
-; RV32IZCMP-NEXT: sw s10, 68(a0)
-; RV32IZCMP-NEXT: sw s9, 64(a0)
-; RV32IZCMP-NEXT: sw s8, 60(a0)
-; RV32IZCMP-NEXT: sw s7, 56(a0)
-; RV32IZCMP-NEXT: sw s6, 52(a0)
-; RV32IZCMP-NEXT: sw s5, 48(a0)
-; RV32IZCMP-NEXT: sw s4, 44(a0)
-; RV32IZCMP-NEXT: sw s3, 40(a0)
-; RV32IZCMP-NEXT: sw s2, 36(a0)
-; RV32IZCMP-NEXT: sw t6, 32(a0)
-; RV32IZCMP-NEXT: sw t5, 28(a0)
-; RV32IZCMP-NEXT: sw t4, 24(a0)
-; RV32IZCMP-NEXT: sw t3, 20(a0)
+; RV32IZCMP-NEXT: sw a3, 104(a0)
+; RV32IZCMP-NEXT: sw a4, 100(a0)
+; RV32IZCMP-NEXT: sw a5, 96(a0)
+; RV32IZCMP-NEXT: sw s9, 92(a0)
+; RV32IZCMP-NEXT: sw s8, 88(a0)
+; RV32IZCMP-NEXT: sw s7, 84(a0)
+; RV32IZCMP-NEXT: sw s6, 80(a0)
+; RV32IZCMP-NEXT: sw s5, 76(a0)
+; RV32IZCMP-NEXT: sw s4, 72(a0)
+; RV32IZCMP-NEXT: sw s3, 68(a0)
+; RV32IZCMP-NEXT: sw s2, 64(a0)
+; RV32IZCMP-NEXT: sw s1, 60(a0)
+; RV32IZCMP-NEXT: sw s0, 56(a0)
+; RV32IZCMP-NEXT: sw t6, 52(a0)
+; RV32IZCMP-NEXT: sw t5, 48(a0)
+; RV32IZCMP-NEXT: sw t4, 44(a0)
+; RV32IZCMP-NEXT: sw t3, 40(a0)
+; RV32IZCMP-NEXT: sw t2, 36(a0)
+; RV32IZCMP-NEXT: sw t1, 32(a0)
+; RV32IZCMP-NEXT: sw t0, 28(a0)
+; RV32IZCMP-NEXT: sw a7, 24(a0)
+; RV32IZCMP-NEXT: sw a6, 20(a0)
; RV32IZCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; RV32IZCMP-NEXT: sw a1, 16(a0)
; RV32IZCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -3466,60 +3466,60 @@ define void @callee_no_irq() {
; RV64IZCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
; RV64IZCMP-NEXT: lw a1, 16(a0)
; RV64IZCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-NEXT: lw t3, 20(a0)
-; RV64IZCMP-NEXT: lw t4, 24(a0)
-; RV64IZCMP-NEXT: lw t5, 28(a0)
-; RV64IZCMP-NEXT: lw t6, 32(a0)
-; RV64IZCMP-NEXT: lw s2, 36(a0)
-; RV64IZCMP-NEXT: lw s3, 40(a0)
-; RV64IZCMP-NEXT: lw s4, 44(a0)
-; RV64IZCMP-NEXT: lw s5, 48(a0)
-; RV64IZCMP-NEXT: lw s6, 52(a0)
-; RV64IZCMP-NEXT: lw s7, 56(a0)
-; RV64IZCMP-NEXT: lw s8, 60(a0)
-; RV64IZCMP-NEXT: lw s9, 64(a0)
-; RV64IZCMP-NEXT: lw s10, 68(a0)
-; RV64IZCMP-NEXT: lw s11, 72(a0)
-; RV64IZCMP-NEXT: lw ra, 76(a0)
-; RV64IZCMP-NEXT: lw t2, 80(a0)
-; RV64IZCMP-NEXT: lw s0, 84(a0)
-; RV64IZCMP-NEXT: lw s1, 88(a0)
-; RV64IZCMP-NEXT: lw t1, 92(a0)
-; RV64IZCMP-NEXT: lw t0, 112(a0)
-; RV64IZCMP-NEXT: lw a5, 116(a0)
-; RV64IZCMP-NEXT: lw a3, 120(a0)
+; RV64IZCMP-NEXT: lw a6, 20(a0)
+; RV64IZCMP-NEXT: lw a7, 24(a0)
+; RV64IZCMP-NEXT: lw t0, 28(a0)
+; RV64IZCMP-NEXT: lw t1, 32(a0)
+; RV64IZCMP-NEXT: lw t2, 36(a0)
+; RV64IZCMP-NEXT: lw t3, 40(a0)
+; RV64IZCMP-NEXT: lw t4, 44(a0)
+; RV64IZCMP-NEXT: lw t5, 48(a0)
+; RV64IZCMP-NEXT: lw t6, 52(a0)
+; RV64IZCMP-NEXT: lw s0, 56(a0)
+; RV64IZCMP-NEXT: lw s1, 60(a0)
+; RV64IZCMP-NEXT: lw s2, 64(a0)
+; RV64IZCMP-NEXT: lw s3, 68(a0)
+; RV64IZCMP-NEXT: lw s4, 72(a0)
+; RV64IZCMP-NEXT: lw s5, 76(a0)
+; RV64IZCMP-NEXT: lw s6, 80(a0)
+; RV64IZCMP-NEXT: lw s7, 84(a0)
+; RV64IZCMP-NEXT: lw s8, 88(a0)
+; RV64IZCMP-NEXT: lw s9, 92(a0)
+; RV64IZCMP-NEXT: lw s10, 112(a0)
+; RV64IZCMP-NEXT: lw s11, 116(a0)
+; RV64IZCMP-NEXT: lw ra, 120(a0)
; RV64IZCMP-NEXT: lw a1, 124(a0)
-; RV64IZCMP-NEXT: lw a7, 96(a0)
-; RV64IZCMP-NEXT: lw a6, 100(a0)
-; RV64IZCMP-NEXT: lw a4, 104(a0)
+; RV64IZCMP-NEXT: lw a5, 96(a0)
+; RV64IZCMP-NEXT: lw a4, 100(a0)
+; RV64IZCMP-NEXT: lw a3, 104(a0)
; RV64IZCMP-NEXT: lw a2, 108(a0)
; RV64IZCMP-NEXT: sw a1, 124(a0)
-; RV64IZCMP-NEXT: sw a3, 120(a0)
-; RV64IZCMP-NEXT: sw a5, 116(a0)
-; RV64IZCMP-NEXT: sw t0, 112(a0)
+; RV64IZCMP-NEXT: sw ra, 120(a0)
+; RV64IZCMP-NEXT: sw s11, 116(a0)
+; RV64IZCMP-NEXT: sw s10, 112(a0)
; RV64IZCMP-NEXT: sw a2, 108(a0)
-; RV64IZCMP-NEXT: sw a4, 104(a0)
-; RV64IZCMP-NEXT: sw a6, 100(a0)
-; RV64IZCMP-NEXT: sw a7, 96(a0)
-; RV64IZCMP-NEXT: sw t1, 92(a0)
-; RV64IZCMP-NEXT: sw s1, 88(a0)
-; RV64IZCMP-NEXT: sw s0, 84(a0)
-; RV64IZCMP-NEXT: sw t2, 80(a0)
-; RV64IZCMP-NEXT: sw ra, 76(a0)
-; RV64IZCMP-NEXT: sw s11, 72(a0)
-; RV64IZCMP-NEXT: sw s10, 68(a0)
-; RV64IZCMP-NEXT: sw s9, 64(a0)
-; RV64IZCMP-NEXT: sw s8, 60(a0)
-; RV64IZCMP-NEXT: sw s7, 56(a0)
-; RV64IZCMP-NEXT: sw s6, 52(a0)
-; RV64IZCMP-NEXT: sw s5, 48(a0)
-; RV64IZCMP-NEXT: sw s4, 44(a0)
-; RV64IZCMP-NEXT: sw s3, 40(a0)
-; RV64IZCMP-NEXT: sw s2, 36(a0)
-; RV64IZCMP-NEXT: sw t6, 32(a0)
-; RV64IZCMP-NEXT: sw t5, 28(a0)
-; RV64IZCMP-NEXT: sw t4, 24(a0)
-; RV64IZCMP-NEXT: sw t3, 20(a0)
+; RV64IZCMP-NEXT: sw a3, 104(a0)
+; RV64IZCMP-NEXT: sw a4, 100(a0)
+; RV64IZCMP-NEXT: sw a5, 96(a0)
+; RV64IZCMP-NEXT: sw s9, 92(a0)
+; RV64IZCMP-NEXT: sw s8, 88(a0)
+; RV64IZCMP-NEXT: sw s7, 84(a0)
+; RV64IZCMP-NEXT: sw s6, 80(a0)
+; RV64IZCMP-NEXT: sw s5, 76(a0)
+; RV64IZCMP-NEXT: sw s4, 72(a0)
+; RV64IZCMP-NEXT: sw s3, 68(a0)
+; RV64IZCMP-NEXT: sw s2, 64(a0)
+; RV64IZCMP-NEXT: sw s1, 60(a0)
+; RV64IZCMP-NEXT: sw s0, 56(a0)
+; RV64IZCMP-NEXT: sw t6, 52(a0)
+; RV64IZCMP-NEXT: sw t5, 48(a0)
+; RV64IZCMP-NEXT: sw t4, 44(a0)
+; RV64IZCMP-NEXT: sw t3, 40(a0)
+; RV64IZCMP-NEXT: sw t2, 36(a0)
+; RV64IZCMP-NEXT: sw t1, 32(a0)
+; RV64IZCMP-NEXT: sw t0, 28(a0)
+; RV64IZCMP-NEXT: sw a7, 24(a0)
+; RV64IZCMP-NEXT: sw a6, 20(a0)
; RV64IZCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-NEXT: sw a1, 16(a0)
; RV64IZCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
@@ -3561,60 +3561,60 @@ define void @callee_no_irq() {
; RV32IZCMP-SR-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; RV32IZCMP-SR-NEXT: lw a1, 16(a0)
; RV32IZCMP-SR-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; RV32IZCMP-SR-NEXT: lw t3, 20(a0)
-; RV32IZCMP-SR-NEXT: lw t4, 24(a0)
-; RV32IZCMP-SR-NEXT: lw t5, 28(a0)
-; RV32IZCMP-SR-NEXT: lw t6, 32(a0)
-; RV32IZCMP-SR-NEXT: lw s2, 36(a0)
-; RV32IZCMP-SR-NEXT: lw s3, 40(a0)
-; RV32IZCMP-SR-NEXT: lw s4, 44(a0)
-; RV32IZCMP-SR-NEXT: lw s5, 48(a0)
-; RV32IZCMP-SR-NEXT: lw s6, 52(a0)
-; RV32IZCMP-SR-NEXT: lw s7, 56(a0)
-; RV32IZCMP-SR-NEXT: lw s8, 60(a0)
-; RV32IZCMP-SR-NEXT: lw s9, 64(a0)
-; RV32IZCMP-SR-NEXT: lw s10, 68(a0)
-; RV32IZCMP-SR-NEXT: lw s11, 72(a0)
-; RV32IZCMP-SR-NEXT: lw ra, 76(a0)
-; RV32IZCMP-SR-NEXT: lw t2, 80(a0)
-; RV32IZCMP-SR-NEXT: lw s0, 84(a0)
-; RV32IZCMP-SR-NEXT: lw s1, 88(a0)
-; RV32IZCMP-SR-NEXT: lw t1, 92(a0)
-; RV32IZCMP-SR-NEXT: lw t0, 112(a0)
-; RV32IZCMP-SR-NEXT: lw a5, 116(a0)
-; RV32IZCMP-SR-NEXT: lw a3, 120(a0)
+; RV32IZCMP-SR-NEXT: lw a6, 20(a0)
+; RV32IZCMP-SR-NEXT: lw a7, 24(a0)
+; RV32IZCMP-SR-NEXT: lw t0, 28(a0)
+; RV32IZCMP-SR-NEXT: lw t1, 32(a0)
+; RV32IZCMP-SR-NEXT: lw t2, 36(a0)
+; RV32IZCMP-SR-NEXT: lw t3, 40(a0)
+; RV32IZCMP-SR-NEXT: lw t4, 44(a0)
+; RV32IZCMP-SR-NEXT: lw t5, 48(a0)
+; RV32IZCMP-SR-NEXT: lw t6, 52(a0)
+; RV32IZCMP-SR-NEXT: lw s0, 56(a0)
+; RV32IZCMP-SR-NEXT: lw s1, 60(a0)
+; RV32IZCMP-SR-NEXT: lw s2, 64(a0)
+; RV32IZCMP-SR-NEXT: lw s3, 68(a0)
+; RV32IZCMP-SR-NEXT: lw s4, 72(a0)
+; RV32IZCMP-SR-NEXT: lw s5, 76(a0)
+; RV32IZCMP-SR-NEXT: lw s6, 80(a0)
+; RV32IZCMP-SR-NEXT: lw s7, 84(a0)
+; RV32IZCMP-SR-NEXT: lw s8, 88(a0)
+; RV32IZCMP-SR-NEXT: lw s9, 92(a0)
+; RV32IZCMP-SR-NEXT: lw s10, 112(a0)
+; RV32IZCMP-SR-NEXT: lw s11, 116(a0)
+; RV32IZCMP-SR-NEXT: lw ra, 120(a0)
; RV32IZCMP-SR-NEXT: lw a1, 124(a0)
-; RV32IZCMP-SR-NEXT: lw a7, 96(a0)
-; RV32IZCMP-SR-NEXT: lw a6, 100(a0)
-; RV32IZCMP-SR-NEXT: lw a4, 104(a0)
+; RV32IZCMP-SR-NEXT: lw a5, 96(a0)
+; RV32IZCMP-SR-NEXT: lw a4, 100(a0)
+; RV32IZCMP-SR-NEXT: lw a3, 104(a0)
; RV32IZCMP-SR-NEXT: lw a2, 108(a0)
; RV32IZCMP-SR-NEXT: sw a1, 124(a0)
-; RV32IZCMP-SR-NEXT: sw a3, 120(a0)
-; RV32IZCMP-SR-NEXT: sw a5, 116(a0)
-; RV32IZCMP-SR-NEXT: sw t0, 112(a0)
+; RV32IZCMP-SR-NEXT: sw ra, 120(a0)
+; RV32IZCMP-SR-NEXT: sw s11, 116(a0)
+; RV32IZCMP-SR-NEXT: sw s10, 112(a0)
; RV32IZCMP-SR-NEXT: sw a2, 108(a0)
-; RV32IZCMP-SR-NEXT: sw a4, 104(a0)
-; RV32IZCMP-SR-NEXT: sw a6, 100(a0)
-; RV32IZCMP-SR-NEXT: sw a7, 96(a0)
-; RV32IZCMP-SR-NEXT: sw t1, 92(a0)
-; RV32IZCMP-SR-NEXT: sw s1, 88(a0)
-; RV32IZCMP-SR-NEXT: sw s0, 84(a0)
-; RV32IZCMP-SR-NEXT: sw t2, 80(a0)
-; RV32IZCMP-SR-NEXT: sw ra, 76(a0)
-; RV32IZCMP-SR-NEXT: sw s11, 72(a0)
-; RV32IZCMP-SR-NEXT: sw s10, 68(a0)
-; RV32IZCMP-SR-NEXT: sw s9, 64(a0)
-; RV32IZCMP-SR-NEXT: sw s8, 60(a0)
-; RV32IZCMP-SR-NEXT: sw s7, 56(a0)
-; RV32IZCMP-SR-NEXT: sw s6, 52(a0)
-; RV32IZCMP-SR-NEXT: sw s5, 48(a0)
-; RV32IZCMP-SR-NEXT: sw s4, 44(a0)
-; RV32IZCMP-SR-NEXT: sw s3, 40(a0)
-; RV32IZCMP-SR-NEXT: sw s2, 36(a0)
-; RV32IZCMP-SR-NEXT: sw t6, 32(a0)
-; RV32IZCMP-SR-NEXT: sw t5, 28(a0)
-; RV32IZCMP-SR-NEXT: sw t4, 24(a0)
-; RV32IZCMP-SR-NEXT: sw t3, 20(a0)
+; RV32IZCMP-SR-NEXT: sw a3, 104(a0)
+; RV32IZCMP-SR-NEXT: sw a4, 100(a0)
+; RV32IZCMP-SR-NEXT: sw a5, 96(a0)
+; RV32IZCMP-SR-NEXT: sw s9, 92(a0)
+; RV32IZCMP-SR-NEXT: sw s8, 88(a0)
+; RV32IZCMP-SR-NEXT: sw s7, 84(a0)
+; RV32IZCMP-SR-NEXT: sw s6, 80(a0)
+; RV32IZCMP-SR-NEXT: sw s5, 76(a0)
+; RV32IZCMP-SR-NEXT: sw s4, 72(a0)
+; RV32IZCMP-SR-NEXT: sw s3, 68(a0)
+; RV32IZCMP-SR-NEXT: sw s2, 64(a0)
+; RV32IZCMP-SR-NEXT: sw s1, 60(a0)
+; RV32IZCMP-SR-NEXT: sw s0, 56(a0)
+; RV32IZCMP-SR-NEXT: sw t6, 52(a0)
+; RV32IZCMP-SR-NEXT: sw t5, 48(a0)
+; RV32IZCMP-SR-NEXT: sw t4, 44(a0)
+; RV32IZCMP-SR-NEXT: sw t3, 40(a0)
+; RV32IZCMP-SR-NEXT: sw t2, 36(a0)
+; RV32IZCMP-SR-NEXT: sw t1, 32(a0)
+; RV32IZCMP-SR-NEXT: sw t0, 28(a0)
+; RV32IZCMP-SR-NEXT: sw a7, 24(a0)
+; RV32IZCMP-SR-NEXT: sw a6, 20(a0)
; RV32IZCMP-SR-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; RV32IZCMP-SR-NEXT: sw a1, 16(a0)
; RV32IZCMP-SR-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -3656,60 +3656,60 @@ define void @callee_no_irq() {
; RV64IZCMP-SR-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
; RV64IZCMP-SR-NEXT: lw a1, 16(a0)
; RV64IZCMP-SR-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
-; RV64IZCMP-SR-NEXT: lw t3, 20(a0)
-; RV64IZCMP-SR-NEXT: lw t4, 24(a0)
-; RV64IZCMP-SR-NEXT: lw t5, 28(a0)
-; RV64IZCMP-SR-NEXT: lw t6, 32(a0)
-; RV64IZCMP-SR-NEXT: lw s2, 36(a0)
-; RV64IZCMP-SR-NEXT: lw s3, 40(a0)
-; RV64IZCMP-SR-NEXT: lw s4, 44(a0)
-; RV64IZCMP-SR-NEXT: lw s5, 48(a0)
-; RV64IZCMP-SR-NEXT: lw s6, 52(a0)
-; RV64IZCMP-SR-NEXT: lw s7, 56(a0)
-; RV64IZCMP-SR-NEXT: lw s8, 60(a0)
-; RV64IZCMP-SR-NEXT: lw s9, 64(a0)
-; RV64IZCMP-SR-NEXT: lw s10, 68(a0)
-; RV64IZCMP-SR-NEXT: lw s11, 72(a0)
-; RV64IZCMP-SR-NEXT: lw ra, 76(a0)
-; RV64IZCMP-SR-NEXT: lw t2, 80(a0)
-; RV64IZCMP-SR-NEXT: lw s0, 84(a0)
-; RV64IZCMP-SR-NEXT: lw s1, 88(a0)
-; RV64IZCMP-SR-NEXT: lw t1, 92(a0)
-; RV64IZCMP-SR-NEXT: lw t0, 112(a0)
-; RV64IZCMP-SR-NEXT: lw a5, 116(a0)
-; RV64IZCMP-SR-NEXT: lw a3, 120(a0)
+; RV64IZCMP-SR-NEXT: lw a6, 20(a0)
+; RV64IZCMP-SR-NEXT: lw a7, 24(a0)
+; RV64IZCMP-SR-NEXT: lw t0, 28(a0)
+; RV64IZCMP-SR-NEXT: lw t1, 32(a0)
+; RV64IZCMP-SR-NEXT: lw t2, 36(a0)
+; RV64IZCMP-SR-NEXT: lw t3, 40(a0)
+; RV64IZCMP-SR-NEXT: lw t4, 44(a0)
+; RV64IZCMP-SR-NEXT: lw t5, 48(a0)
+; RV64IZCMP-SR-NEXT: lw t6, 52(a0)
+; RV64IZCMP-SR-NEXT: lw s0, 56(a0)
+; RV64IZCMP-SR-NEXT: lw s1, 60(a0)
+; RV64IZCMP-SR-NEXT: lw s2, 64(a0)
+; RV64IZCMP-SR-NEXT: lw s3, 68(a0)
+; RV64IZCMP-SR-NEXT: lw s4, 72(a0)
+; RV64IZCMP-SR-NEXT: lw s5, 76(a0)
+; RV64IZCMP-SR-NEXT: lw s6, 80(a0)
+; RV64IZCMP-SR-NEXT: lw s7, 84(a0)
+; RV64IZCMP-SR-NEXT: lw s8, 88(a0)
+; RV64IZCMP-SR-NEXT: lw s9, 92(a0)
+; RV64IZCMP-SR-NEXT: lw s10, 112(a0)
+; RV64IZCMP-SR-NEXT: lw s11, 116(a0)
+; RV64IZCMP-SR-NEXT: lw ra, 120(a0)
; RV64IZCMP-SR-NEXT: lw a1, 124(a0)
-; RV64IZCMP-SR-NEXT: lw a7, 96(a0)
-; RV64IZCMP-SR-NEXT: lw a6, 100(a0)
-; RV64IZCMP-SR-NEXT: lw a4, 104(a0)
+; RV64IZCMP-SR-NEXT: lw a5, 96(a0)
+; RV64IZCMP-SR-NEXT: lw a4, 100(a0)
+; RV64IZCMP-SR-NEXT: lw a3, 104(a0)
; RV64IZCMP-SR-NEXT: lw a2, 108(a0)
; RV64IZCMP-SR-NEXT: sw a1, 124(a0)
-; RV64IZCMP-SR-NEXT: sw a3, 120(a0)
-; RV64IZCMP-SR-NEXT: sw a5, 116(a0)
-; RV64IZCMP-SR-NEXT: sw t0, 112(a0)
+; RV64IZCMP-SR-NEXT: sw ra, 120(a0)
+; RV64IZCMP-SR-NEXT: sw s11, 116(a0)
+; RV64IZCMP-SR-NEXT: sw s10, 112(a0)
; RV64IZCMP-SR-NEXT: sw a2, 108(a0)
-; RV64IZCMP-SR-NEXT: sw a4, 104(a0)
-; RV64IZCMP-SR-NEXT: sw a6, 100(a0)
-; RV64IZCMP-SR-NEXT: sw a7, 96(a0)
-; RV64IZCMP-SR-NEXT: sw t1, 92(a0)
-; RV64IZCMP-SR-NEXT: sw s1, 88(a0)
-; RV64IZCMP-SR-NEXT: sw s0, 84(a0)
-; RV64IZCMP-SR-NEXT: sw t2, 80(a0)
-; RV64IZCMP-SR-NEXT: sw ra, 76(a0)
-; RV64IZCMP-SR-NEXT: sw s11, 72(a0)
-; RV64IZCMP-SR-NEXT: sw s10, 68(a0)
-; RV64IZCMP-SR-NEXT: sw s9, 64(a0)
-; RV64IZCMP-SR-NEXT: sw s8, 60(a0)
-; RV64IZCMP-SR-NEXT: sw s7, 56(a0)
-; RV64IZCMP-SR-NEXT: sw s6, 52(a0)
-; RV64IZCMP-SR-NEXT: sw s5, 48(a0)
-; RV64IZCMP-SR-NEXT: sw s4, 44(a0)
-; RV64IZCMP-SR-NEXT: sw s3, 40(a0)
-; RV64IZCMP-SR-NEXT: sw s2, 36(a0)
-; RV64IZCMP-SR-NEXT: sw t6, 32(a0)
-; RV64IZCMP-SR-NEXT: sw t5, 28(a0)
-; RV64IZCMP-SR-NEXT: sw t4, 24(a0)
-; RV64IZCMP-SR-NEXT: sw t3, 20(a0)
+; RV64IZCMP-SR-NEXT: sw a3, 104(a0)
+; RV64IZCMP-SR-NEXT: sw a4, 100(a0)
+; RV64IZCMP-SR-NEXT: sw a5, 96(a0)
+; RV64IZCMP-SR-NEXT: sw s9, 92(a0)
+; RV64IZCMP-SR-NEXT: sw s8, 88(a0)
+; RV64IZCMP-SR-NEXT: sw s7, 84(a0)
+; RV64IZCMP-SR-NEXT: sw s6, 80(a0)
+; RV64IZCMP-SR-NEXT: sw s5, 76(a0)
+; RV64IZCMP-SR-NEXT: sw s4, 72(a0)
+; RV64IZCMP-SR-NEXT: sw s3, 68(a0)
+; RV64IZCMP-SR-NEXT: sw s2, 64(a0)
+; RV64IZCMP-SR-NEXT: sw s1, 60(a0)
+; RV64IZCMP-SR-NEXT: sw s0, 56(a0)
+; RV64IZCMP-SR-NEXT: sw t6, 52(a0)
+; RV64IZCMP-SR-NEXT: sw t5, 48(a0)
+; RV64IZCMP-SR-NEXT: sw t4, 44(a0)
+; RV64IZCMP-SR-NEXT: sw t3, 40(a0)
+; RV64IZCMP-SR-NEXT: sw t2, 36(a0)
+; RV64IZCMP-SR-NEXT: sw t1, 32(a0)
+; RV64IZCMP-SR-NEXT: sw t0, 28(a0)
+; RV64IZCMP-SR-NEXT: sw a7, 24(a0)
+; RV64IZCMP-SR-NEXT: sw a6, 20(a0)
; RV64IZCMP-SR-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
; RV64IZCMP-SR-NEXT: sw a1, 16(a0)
; RV64IZCMP-SR-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll b/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
index 6c8037fb0f006..28b418640f0e9 100644
--- a/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
+++ b/llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll
@@ -540,30 +540,30 @@ define void @test_nest_call() "interrupt"="qci-nest" {
; QCI-F-NEXT: .cfi_offset ft9, -168
; QCI-F-NEXT: .cfi_offset ft10, -172
; QCI-F-NEXT: .cfi_offset ft11, -176
-; QCI-F-NEXT: lui a7, 266496
-; QCI-F-NEXT: li t0, 5
+; QCI-F-NEXT: lui a1, 266496
+; QCI-F-NEXT: li a3, 5
; QCI-F-NEXT: lui a0, 260096
; QCI-F-NEXT: lui a2, 262144
; QCI-F-NEXT: lui a4, 263168
; QCI-F-NEXT: lui a5, 264192
-; QCI-F-NEXT: lui a1, 264704
-; QCI-F-NEXT: lui a6, 265216
+; QCI-F-NEXT: lui a6, 264704
+; QCI-F-NEXT: lui a7, 265216
; QCI-F-NEXT: fmv.w.x fa0, a0
-; QCI-F-NEXT: lui t1, 265728
+; QCI-F-NEXT: lui t0, 265728
; QCI-F-NEXT: fmv.w.x fa1, a2
-; QCI-F-NEXT: lui a3, 266240
+; QCI-F-NEXT: lui t1, 266240
; QCI-F-NEXT: fmv.w.x fa2, a4
; QCI-F-NEXT: li a0, 1
; QCI-F-NEXT: fmv.w.x fa3, a5
; QCI-F-NEXT: li a2, 2
-; QCI-F-NEXT: fmv.w.x fa4, a1
+; QCI-F-NEXT: fmv.w.x fa4, a6
; QCI-F-NEXT: li a4, 3
-; QCI-F-NEXT: fmv.w.x fa5, a6
+; QCI-F-NEXT: fmv.w.x fa5, a7
; QCI-F-NEXT: li a6, 4
-; QCI-F-NEXT: fmv.w.x fa6, t1
-; QCI-F-NEXT: fmv.w.x fa7, a3
-; QCI-F-NEXT: sw t0, 0(sp)
-; QCI-F-NEXT: sw a7, 4(sp)
+; QCI-F-NEXT: fmv.w.x fa6, t0
+; QCI-F-NEXT: fmv.w.x fa7, t1
+; QCI-F-NEXT: sw a3, 0(sp)
+; QCI-F-NEXT: sw a1, 4(sp)
; QCI-F-NEXT: li a1, 0
; QCI-F-NEXT: li a3, 0
; QCI-F-NEXT: li a5, 0
@@ -677,30 +677,30 @@ define void @test_nest_call() "interrupt"="qci-nest" {
; QCI-D-NEXT: .cfi_offset ft9, -240
; QCI-D-NEXT: .cfi_offset ft10, -248
; QCI-D-NEXT: .cfi_offset ft11, -256
-; QCI-D-NEXT: lui a7, 266496
-; QCI-D-NEXT: li t0, 5
+; QCI-D-NEXT: lui a1, 266496
+; QCI-D-NEXT: li a3, 5
; QCI-D-NEXT: lui a0, 260096
; QCI-D-NEXT: lui a2, 262144
; QCI-D-NEXT: lui a4, 263168
; QCI-D-NEXT: lui a5, 264192
-; QCI-D-NEXT: lui a1, 264704
-; QCI-D-NEXT: lui a6, 265216
+; QCI-D-NEXT: lui a6, 264704
+; QCI-D-NEXT: lui a7, 265216
; QCI-D-NEXT: fmv.w.x fa0, a0
-; QCI-D-NEXT: lui t1, 265728
+; QCI-D-NEXT: lui t0, 265728
; QCI-D-NEXT: fmv.w.x fa1, a2
-; QCI-D-NEXT: lui a3, 266240
+; QCI-D-NEXT: lui t1, 266240
; QCI-D-NEXT: fmv.w.x fa2, a4
; QCI-D-NEXT: li a0, 1
; QCI-D-NEXT: fmv.w.x fa3, a5
; QCI-D-NEXT: li a2, 2
-; QCI-D-NEXT: fmv.w.x fa4, a1
+; QCI-D-NEXT: fmv.w.x fa4, a6
; QCI-D-NEXT: li a4, 3
-; QCI-D-NEXT: fmv.w.x fa5, a6
+; QCI-D-NEXT: fmv.w.x fa5, a7
; QCI-D-NEXT: li a6, 4
-; QCI-D-NEXT: fmv.w.x fa6, t1
-; QCI-D-NEXT: fmv.w.x fa7, a3
-; QCI-D-NEXT: sw t0, 0(sp)
-; QCI-D-NEXT: sw a7, 4(sp)
+; QCI-D-NEXT: fmv.w.x fa6, t0
+; QCI-D-NEXT: fmv.w.x fa7, t1
+; QCI-D-NEXT: sw a3, 0(sp)
+; QCI-D-NEXT: sw a1, 4(sp)
; QCI-D-NEXT: li a1, 0
; QCI-D-NEXT: li a3, 0
; QCI-D-NEXT: li a5, 0
@@ -819,30 +819,30 @@ define void @test_nonest_call() "interrupt"="qci-nonest" {
; QCI-F-NEXT: .cfi_offset ft9, -168
; QCI-F-NEXT: .cfi_offset ft10, -172
; QCI-F-NEXT: .cfi_offset ft11, -176
-; QCI-F-NEXT: lui a7, 266496
-; QCI-F-NEXT: li t0, 5
+; QCI-F-NEXT: lui a1, 266496
+; QCI-F-NEXT: li a3, 5
; QCI-F-NEXT: lui a0, 260096
; QCI-F-NEXT: lui a2, 262144
; QCI-F-NEXT: lui a4, 263168
; QCI-F-NEXT: lui a5, 264192
-; QCI-F-NEXT: lui a1, 264704
-; QCI-F-NEXT: lui a6, 265216
+; QCI-F-NEXT: lui a6, 264704
+; QCI-F-NEXT: lui a7, 265216
; QCI-F-NEXT: fmv.w.x fa0, a0
-; QCI-F-NEXT: lui t1, 265728
+; QCI-F-NEXT: lui t0, 265728
; QCI-F-NEXT: fmv.w.x fa1, a2
-; QCI-F-NEXT: lui a3, 266240
+; QCI-F-NEXT: lui t1, 266240
; QCI-F-NEXT: fmv.w.x fa2, a4
; QCI-F-NEXT: li a0, 1
; QCI-F-NEXT: fmv.w.x fa3, a5
; QCI-F-NEXT: li a2, 2
-; QCI-F-NEXT: fmv.w.x fa4, a1
+; QCI-F-NEXT: fmv.w.x fa4, a6
; QCI-F-NEXT: li a4, 3
-; QCI-F-NEXT: fmv.w.x fa5, a6
+; QCI-F-NEXT: fmv.w.x fa5, a7
; QCI-F-NEXT: li a6, 4
-; QCI-F-NEXT: fmv.w.x fa6, t1
-; QCI-F-NEXT: fmv.w.x fa7, a3
-; QCI-F-NEXT: sw t0, 0(sp)
-; QCI-F-NEXT: sw a7, 4(sp)
+; QCI-F-NEXT: fmv.w.x fa6, t0
+; QCI-F-NEXT: fmv.w.x fa7, t1
+; QCI-F-NEXT: sw a3, 0(sp)
+; QCI-F-NEXT: sw a1, 4(sp)
; QCI-F-NEXT: li a1, 0
; QCI-F-NEXT: li a3, 0
; QCI-F-NEXT: li a5, 0
@@ -956,30 +956,30 @@ define void @test_nonest_call() "interrupt"="qci-nonest" {
; QCI-D-NEXT: .cfi_offset ft9, -240
; QCI-D-NEXT: .cfi_offset ft10, -248
; QCI-D-NEXT: .cfi_offset ft11, -256
-; QCI-D-NEXT: lui a7, 266496
-; QCI-D-NEXT: li t0, 5
+; QCI-D-NEXT: lui a1, 266496
+; QCI-D-NEXT: li a3, 5
; QCI-D-NEXT: lui a0, 260096
; QCI-D-NEXT: lui a2, 262144
; QCI-D-NEXT: lui a4, 263168
; QCI-D-NEXT: lui a5, 264192
-; QCI-D-NEXT: lui a1, 264704
-; QCI-D-NEXT: lui a6, 265216
+; QCI-D-NEXT: lui a6, 264704
+; QCI-D-NEXT: lui a7, 265216
; QCI-D-NEXT: fmv.w.x fa0, a0
-; QCI-D-NEXT: lui t1, 265728
+; QCI-D-NEXT: lui t0, 265728
; QCI-D-NEXT: fmv.w.x fa1, a2
-; QCI-D-NEXT: lui a3, 266240
+; QCI-D-NEXT: lui t1, 266240
; QCI-D-NEXT: fmv.w.x fa2, a4
; QCI-D-NEXT: li a0, 1
; QCI-D-NEXT: fmv.w.x fa3, a5
; QCI-D-NEXT: li a2, 2
-; QCI-D-NEXT: fmv.w.x fa4, a1
+; QCI-D-NEXT: fmv.w.x fa4, a6
; QCI-D-NEXT: li a4, 3
-; QCI-D-NEXT: fmv.w.x fa5, a6
+; QCI-D-NEXT: fmv.w.x fa5, a7
; QCI-D-NEXT: li a6, 4
-; QCI-D-NEXT: fmv.w.x fa6, t1
-; QCI-D-NEXT: fmv.w.x fa7, a3
-; QCI-D-NEXT: sw t0, 0(sp)
-; QCI-D-NEXT: sw a7, 4(sp)
+; QCI-D-NEXT: fmv.w.x fa6, t0
+; QCI-D-NEXT: fmv.w.x fa7, t1
+; QCI-D-NEXT: sw a3, 0(sp)
+; QCI-D-NEXT: sw a1, 4(sp)
; QCI-D-NEXT: li a1, 0
; QCI-D-NEXT: li a3, 0
; QCI-D-NEXT: li a5, 0
@@ -1094,60 +1094,60 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-F-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; QCI-F-NEXT: lw a1, 16(a0)
; QCI-F-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw t3, 20(a0)
-; QCI-F-NEXT: lw t4, 24(a0)
-; QCI-F-NEXT: lw t5, 28(a0)
-; QCI-F-NEXT: lw t6, 32(a0)
-; QCI-F-NEXT: lw s2, 36(a0)
-; QCI-F-NEXT: lw s3, 40(a0)
-; QCI-F-NEXT: lw s4, 44(a0)
-; QCI-F-NEXT: lw s5, 48(a0)
-; QCI-F-NEXT: lw s6, 52(a0)
-; QCI-F-NEXT: lw s7, 56(a0)
-; QCI-F-NEXT: lw s8, 60(a0)
-; QCI-F-NEXT: lw s9, 64(a0)
-; QCI-F-NEXT: lw s10, 68(a0)
-; QCI-F-NEXT: lw s11, 72(a0)
-; QCI-F-NEXT: lw ra, 76(a0)
-; QCI-F-NEXT: lw t2, 80(a0)
-; QCI-F-NEXT: lw s0, 84(a0)
-; QCI-F-NEXT: lw s1, 88(a0)
-; QCI-F-NEXT: lw t1, 92(a0)
-; QCI-F-NEXT: lw t0, 112(a0)
-; QCI-F-NEXT: lw a5, 116(a0)
-; QCI-F-NEXT: lw a3, 120(a0)
+; QCI-F-NEXT: lw a6, 20(a0)
+; QCI-F-NEXT: lw a7, 24(a0)
+; QCI-F-NEXT: lw t0, 28(a0)
+; QCI-F-NEXT: lw t1, 32(a0)
+; QCI-F-NEXT: lw t2, 36(a0)
+; QCI-F-NEXT: lw t3, 40(a0)
+; QCI-F-NEXT: lw t4, 44(a0)
+; QCI-F-NEXT: lw t5, 48(a0)
+; QCI-F-NEXT: lw t6, 52(a0)
+; QCI-F-NEXT: lw s0, 56(a0)
+; QCI-F-NEXT: lw s1, 60(a0)
+; QCI-F-NEXT: lw s2, 64(a0)
+; QCI-F-NEXT: lw s3, 68(a0)
+; QCI-F-NEXT: lw s4, 72(a0)
+; QCI-F-NEXT: lw s5, 76(a0)
+; QCI-F-NEXT: lw s6, 80(a0)
+; QCI-F-NEXT: lw s7, 84(a0)
+; QCI-F-NEXT: lw s8, 88(a0)
+; QCI-F-NEXT: lw s9, 92(a0)
+; QCI-F-NEXT: lw s10, 112(a0)
+; QCI-F-NEXT: lw s11, 116(a0)
+; QCI-F-NEXT: lw ra, 120(a0)
; QCI-F-NEXT: lw a1, 124(a0)
-; QCI-F-NEXT: lw a7, 96(a0)
-; QCI-F-NEXT: lw a6, 100(a0)
-; QCI-F-NEXT: lw a4, 104(a0)
+; QCI-F-NEXT: lw a5, 96(a0)
+; QCI-F-NEXT: lw a4, 100(a0)
+; QCI-F-NEXT: lw a3, 104(a0)
; QCI-F-NEXT: lw a2, 108(a0)
; QCI-F-NEXT: sw a1, 124(a0)
-; QCI-F-NEXT: sw a3, 120(a0)
-; QCI-F-NEXT: sw a5, 116(a0)
-; QCI-F-NEXT: sw t0, 112(a0)
+; QCI-F-NEXT: sw ra, 120(a0)
+; QCI-F-NEXT: sw s11, 116(a0)
+; QCI-F-NEXT: sw s10, 112(a0)
; QCI-F-NEXT: sw a2, 108(a0)
-; QCI-F-NEXT: sw a4, 104(a0)
-; QCI-F-NEXT: sw a6, 100(a0)
-; QCI-F-NEXT: sw a7, 96(a0)
-; QCI-F-NEXT: sw t1, 92(a0)
-; QCI-F-NEXT: sw s1, 88(a0)
-; QCI-F-NEXT: sw s0, 84(a0)
-; QCI-F-NEXT: sw t2, 80(a0)
-; QCI-F-NEXT: sw ra, 76(a0)
-; QCI-F-NEXT: sw s11, 72(a0)
-; QCI-F-NEXT: sw s10, 68(a0)
-; QCI-F-NEXT: sw s9, 64(a0)
-; QCI-F-NEXT: sw s8, 60(a0)
-; QCI-F-NEXT: sw s7, 56(a0)
-; QCI-F-NEXT: sw s6, 52(a0)
-; QCI-F-NEXT: sw s5, 48(a0)
-; QCI-F-NEXT: sw s4, 44(a0)
-; QCI-F-NEXT: sw s3, 40(a0)
-; QCI-F-NEXT: sw s2, 36(a0)
-; QCI-F-NEXT: sw t6, 32(a0)
-; QCI-F-NEXT: sw t5, 28(a0)
-; QCI-F-NEXT: sw t4, 24(a0)
-; QCI-F-NEXT: sw t3, 20(a0)
+; QCI-F-NEXT: sw a3, 104(a0)
+; QCI-F-NEXT: sw a4, 100(a0)
+; QCI-F-NEXT: sw a5, 96(a0)
+; QCI-F-NEXT: sw s9, 92(a0)
+; QCI-F-NEXT: sw s8, 88(a0)
+; QCI-F-NEXT: sw s7, 84(a0)
+; QCI-F-NEXT: sw s6, 80(a0)
+; QCI-F-NEXT: sw s5, 76(a0)
+; QCI-F-NEXT: sw s4, 72(a0)
+; QCI-F-NEXT: sw s3, 68(a0)
+; QCI-F-NEXT: sw s2, 64(a0)
+; QCI-F-NEXT: sw s1, 60(a0)
+; QCI-F-NEXT: sw s0, 56(a0)
+; QCI-F-NEXT: sw t6, 52(a0)
+; QCI-F-NEXT: sw t5, 48(a0)
+; QCI-F-NEXT: sw t4, 44(a0)
+; QCI-F-NEXT: sw t3, 40(a0)
+; QCI-F-NEXT: sw t2, 36(a0)
+; QCI-F-NEXT: sw t1, 32(a0)
+; QCI-F-NEXT: sw t0, 28(a0)
+; QCI-F-NEXT: sw a7, 24(a0)
+; QCI-F-NEXT: sw a6, 20(a0)
; QCI-F-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; QCI-F-NEXT: sw a1, 16(a0)
; QCI-F-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
@@ -1241,60 +1241,60 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-D-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; QCI-D-NEXT: lw a1, 16(a0)
; QCI-D-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw t3, 20(a0)
-; QCI-D-NEXT: lw t4, 24(a0)
-; QCI-D-NEXT: lw t5, 28(a0)
-; QCI-D-NEXT: lw t6, 32(a0)
-; QCI-D-NEXT: lw s2, 36(a0)
-; QCI-D-NEXT: lw s3, 40(a0)
-; QCI-D-NEXT: lw s4, 44(a0)
-; QCI-D-NEXT: lw s5, 48(a0)
-; QCI-D-NEXT: lw s6, 52(a0)
-; QCI-D-NEXT: lw s7, 56(a0)
-; QCI-D-NEXT: lw s8, 60(a0)
-; QCI-D-NEXT: lw s9, 64(a0)
-; QCI-D-NEXT: lw s10, 68(a0)
-; QCI-D-NEXT: lw s11, 72(a0)
-; QCI-D-NEXT: lw ra, 76(a0)
-; QCI-D-NEXT: lw t2, 80(a0)
-; QCI-D-NEXT: lw s0, 84(a0)
-; QCI-D-NEXT: lw s1, 88(a0)
-; QCI-D-NEXT: lw t1, 92(a0)
-; QCI-D-NEXT: lw t0, 112(a0)
-; QCI-D-NEXT: lw a5, 116(a0)
-; QCI-D-NEXT: lw a3, 120(a0)
+; QCI-D-NEXT: lw a6, 20(a0)
+; QCI-D-NEXT: lw a7, 24(a0)
+; QCI-D-NEXT: lw t0, 28(a0)
+; QCI-D-NEXT: lw t1, 32(a0)
+; QCI-D-NEXT: lw t2, 36(a0)
+; QCI-D-NEXT: lw t3, 40(a0)
+; QCI-D-NEXT: lw t4, 44(a0)
+; QCI-D-NEXT: lw t5, 48(a0)
+; QCI-D-NEXT: lw t6, 52(a0)
+; QCI-D-NEXT: lw s0, 56(a0)
+; QCI-D-NEXT: lw s1, 60(a0)
+; QCI-D-NEXT: lw s2, 64(a0)
+; QCI-D-NEXT: lw s3, 68(a0)
+; QCI-D-NEXT: lw s4, 72(a0)
+; QCI-D-NEXT: lw s5, 76(a0)
+; QCI-D-NEXT: lw s6, 80(a0)
+; QCI-D-NEXT: lw s7, 84(a0)
+; QCI-D-NEXT: lw s8, 88(a0)
+; QCI-D-NEXT: lw s9, 92(a0)
+; QCI-D-NEXT: lw s10, 112(a0)
+; QCI-D-NEXT: lw s11, 116(a0)
+; QCI-D-NEXT: lw ra, 120(a0)
; QCI-D-NEXT: lw a1, 124(a0)
-; QCI-D-NEXT: lw a7, 96(a0)
-; QCI-D-NEXT: lw a6, 100(a0)
-; QCI-D-NEXT: lw a4, 104(a0)
+; QCI-D-NEXT: lw a5, 96(a0)
+; QCI-D-NEXT: lw a4, 100(a0)
+; QCI-D-NEXT: lw a3, 104(a0)
; QCI-D-NEXT: lw a2, 108(a0)
; QCI-D-NEXT: sw a1, 124(a0)
-; QCI-D-NEXT: sw a3, 120(a0)
-; QCI-D-NEXT: sw a5, 116(a0)
-; QCI-D-NEXT: sw t0, 112(a0)
+; QCI-D-NEXT: sw ra, 120(a0)
+; QCI-D-NEXT: sw s11, 116(a0)
+; QCI-D-NEXT: sw s10, 112(a0)
; QCI-D-NEXT: sw a2, 108(a0)
-; QCI-D-NEXT: sw a4, 104(a0)
-; QCI-D-NEXT: sw a6, 100(a0)
-; QCI-D-NEXT: sw a7, 96(a0)
-; QCI-D-NEXT: sw t1, 92(a0)
-; QCI-D-NEXT: sw s1, 88(a0)
-; QCI-D-NEXT: sw s0, 84(a0)
-; QCI-D-NEXT: sw t2, 80(a0)
-; QCI-D-NEXT: sw ra, 76(a0)
-; QCI-D-NEXT: sw s11, 72(a0)
-; QCI-D-NEXT: sw s10, 68(a0)
-; QCI-D-NEXT: sw s9, 64(a0)
-; QCI-D-NEXT: sw s8, 60(a0)
-; QCI-D-NEXT: sw s7, 56(a0)
-; QCI-D-NEXT: sw s6, 52(a0)
-; QCI-D-NEXT: sw s5, 48(a0)
-; QCI-D-NEXT: sw s4, 44(a0)
-; QCI-D-NEXT: sw s3, 40(a0)
-; QCI-D-NEXT: sw s2, 36(a0)
-; QCI-D-NEXT: sw t6, 32(a0)
-; QCI-D-NEXT: sw t5, 28(a0)
-; QCI-D-NEXT: sw t4, 24(a0)
-; QCI-D-NEXT: sw t3, 20(a0)
+; QCI-D-NEXT: sw a3, 104(a0)
+; QCI-D-NEXT: sw a4, 100(a0)
+; QCI-D-NEXT: sw a5, 96(a0)
+; QCI-D-NEXT: sw s9, 92(a0)
+; QCI-D-NEXT: sw s8, 88(a0)
+; QCI-D-NEXT: sw s7, 84(a0)
+; QCI-D-NEXT: sw s6, 80(a0)
+; QCI-D-NEXT: sw s5, 76(a0)
+; QCI-D-NEXT: sw s4, 72(a0)
+; QCI-D-NEXT: sw s3, 68(a0)
+; QCI-D-NEXT: sw s2, 64(a0)
+; QCI-D-NEXT: sw s1, 60(a0)
+; QCI-D-NEXT: sw s0, 56(a0)
+; QCI-D-NEXT: sw t6, 52(a0)
+; QCI-D-NEXT: sw t5, 48(a0)
+; QCI-D-NEXT: sw t4, 44(a0)
+; QCI-D-NEXT: sw t3, 40(a0)
+; QCI-D-NEXT: sw t2, 36(a0)
+; QCI-D-NEXT: sw t1, 32(a0)
+; QCI-D-NEXT: sw t0, 28(a0)
+; QCI-D-NEXT: sw a7, 24(a0)
+; QCI-D-NEXT: sw a6, 20(a0)
; QCI-D-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; QCI-D-NEXT: sw a1, 16(a0)
; QCI-D-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
@@ -1393,60 +1393,60 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-F-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; QCI-F-NEXT: lw a1, 16(a0)
; QCI-F-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw t3, 20(a0)
-; QCI-F-NEXT: lw t4, 24(a0)
-; QCI-F-NEXT: lw t5, 28(a0)
-; QCI-F-NEXT: lw t6, 32(a0)
-; QCI-F-NEXT: lw s2, 36(a0)
-; QCI-F-NEXT: lw s3, 40(a0)
-; QCI-F-NEXT: lw s4, 44(a0)
-; QCI-F-NEXT: lw s5, 48(a0)
-; QCI-F-NEXT: lw s6, 52(a0)
-; QCI-F-NEXT: lw s7, 56(a0)
-; QCI-F-NEXT: lw s8, 60(a0)
-; QCI-F-NEXT: lw s9, 64(a0)
-; QCI-F-NEXT: lw s10, 68(a0)
-; QCI-F-NEXT: lw s11, 72(a0)
-; QCI-F-NEXT: lw ra, 76(a0)
-; QCI-F-NEXT: lw t2, 80(a0)
-; QCI-F-NEXT: lw s0, 84(a0)
-; QCI-F-NEXT: lw s1, 88(a0)
-; QCI-F-NEXT: lw t1, 92(a0)
-; QCI-F-NEXT: lw t0, 112(a0)
-; QCI-F-NEXT: lw a5, 116(a0)
-; QCI-F-NEXT: lw a3, 120(a0)
+; QCI-F-NEXT: lw a6, 20(a0)
+; QCI-F-NEXT: lw a7, 24(a0)
+; QCI-F-NEXT: lw t0, 28(a0)
+; QCI-F-NEXT: lw t1, 32(a0)
+; QCI-F-NEXT: lw t2, 36(a0)
+; QCI-F-NEXT: lw t3, 40(a0)
+; QCI-F-NEXT: lw t4, 44(a0)
+; QCI-F-NEXT: lw t5, 48(a0)
+; QCI-F-NEXT: lw t6, 52(a0)
+; QCI-F-NEXT: lw s0, 56(a0)
+; QCI-F-NEXT: lw s1, 60(a0)
+; QCI-F-NEXT: lw s2, 64(a0)
+; QCI-F-NEXT: lw s3, 68(a0)
+; QCI-F-NEXT: lw s4, 72(a0)
+; QCI-F-NEXT: lw s5, 76(a0)
+; QCI-F-NEXT: lw s6, 80(a0)
+; QCI-F-NEXT: lw s7, 84(a0)
+; QCI-F-NEXT: lw s8, 88(a0)
+; QCI-F-NEXT: lw s9, 92(a0)
+; QCI-F-NEXT: lw s10, 112(a0)
+; QCI-F-NEXT: lw s11, 116(a0)
+; QCI-F-NEXT: lw ra, 120(a0)
; QCI-F-NEXT: lw a1, 124(a0)
-; QCI-F-NEXT: lw a7, 96(a0)
-; QCI-F-NEXT: lw a6, 100(a0)
-; QCI-F-NEXT: lw a4, 104(a0)
+; QCI-F-NEXT: lw a5, 96(a0)
+; QCI-F-NEXT: lw a4, 100(a0)
+; QCI-F-NEXT: lw a3, 104(a0)
; QCI-F-NEXT: lw a2, 108(a0)
; QCI-F-NEXT: sw a1, 124(a0)
-; QCI-F-NEXT: sw a3, 120(a0)
-; QCI-F-NEXT: sw a5, 116(a0)
-; QCI-F-NEXT: sw t0, 112(a0)
+; QCI-F-NEXT: sw ra, 120(a0)
+; QCI-F-NEXT: sw s11, 116(a0)
+; QCI-F-NEXT: sw s10, 112(a0)
; QCI-F-NEXT: sw a2, 108(a0)
-; QCI-F-NEXT: sw a4, 104(a0)
-; QCI-F-NEXT: sw a6, 100(a0)
-; QCI-F-NEXT: sw a7, 96(a0)
-; QCI-F-NEXT: sw t1, 92(a0)
-; QCI-F-NEXT: sw s1, 88(a0)
-; QCI-F-NEXT: sw s0, 84(a0)
-; QCI-F-NEXT: sw t2, 80(a0)
-; QCI-F-NEXT: sw ra, 76(a0)
-; QCI-F-NEXT: sw s11, 72(a0)
-; QCI-F-NEXT: sw s10, 68(a0)
-; QCI-F-NEXT: sw s9, 64(a0)
-; QCI-F-NEXT: sw s8, 60(a0)
-; QCI-F-NEXT: sw s7, 56(a0)
-; QCI-F-NEXT: sw s6, 52(a0)
-; QCI-F-NEXT: sw s5, 48(a0)
-; QCI-F-NEXT: sw s4, 44(a0)
-; QCI-F-NEXT: sw s3, 40(a0)
-; QCI-F-NEXT: sw s2, 36(a0)
-; QCI-F-NEXT: sw t6, 32(a0)
-; QCI-F-NEXT: sw t5, 28(a0)
-; QCI-F-NEXT: sw t4, 24(a0)
-; QCI-F-NEXT: sw t3, 20(a0)
+; QCI-F-NEXT: sw a3, 104(a0)
+; QCI-F-NEXT: sw a4, 100(a0)
+; QCI-F-NEXT: sw a5, 96(a0)
+; QCI-F-NEXT: sw s9, 92(a0)
+; QCI-F-NEXT: sw s8, 88(a0)
+; QCI-F-NEXT: sw s7, 84(a0)
+; QCI-F-NEXT: sw s6, 80(a0)
+; QCI-F-NEXT: sw s5, 76(a0)
+; QCI-F-NEXT: sw s4, 72(a0)
+; QCI-F-NEXT: sw s3, 68(a0)
+; QCI-F-NEXT: sw s2, 64(a0)
+; QCI-F-NEXT: sw s1, 60(a0)
+; QCI-F-NEXT: sw s0, 56(a0)
+; QCI-F-NEXT: sw t6, 52(a0)
+; QCI-F-NEXT: sw t5, 48(a0)
+; QCI-F-NEXT: sw t4, 44(a0)
+; QCI-F-NEXT: sw t3, 40(a0)
+; QCI-F-NEXT: sw t2, 36(a0)
+; QCI-F-NEXT: sw t1, 32(a0)
+; QCI-F-NEXT: sw t0, 28(a0)
+; QCI-F-NEXT: sw a7, 24(a0)
+; QCI-F-NEXT: sw a6, 20(a0)
; QCI-F-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; QCI-F-NEXT: sw a1, 16(a0)
; QCI-F-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
@@ -1540,60 +1540,60 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-D-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; QCI-D-NEXT: lw a1, 16(a0)
; QCI-D-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw t3, 20(a0)
-; QCI-D-NEXT: lw t4, 24(a0)
-; QCI-D-NEXT: lw t5, 28(a0)
-; QCI-D-NEXT: lw t6, 32(a0)
-; QCI-D-NEXT: lw s2, 36(a0)
-; QCI-D-NEXT: lw s3, 40(a0)
-; QCI-D-NEXT: lw s4, 44(a0)
-; QCI-D-NEXT: lw s5, 48(a0)
-; QCI-D-NEXT: lw s6, 52(a0)
-; QCI-D-NEXT: lw s7, 56(a0)
-; QCI-D-NEXT: lw s8, 60(a0)
-; QCI-D-NEXT: lw s9, 64(a0)
-; QCI-D-NEXT: lw s10, 68(a0)
-; QCI-D-NEXT: lw s11, 72(a0)
-; QCI-D-NEXT: lw ra, 76(a0)
-; QCI-D-NEXT: lw t2, 80(a0)
-; QCI-D-NEXT: lw s0, 84(a0)
-; QCI-D-NEXT: lw s1, 88(a0)
-; QCI-D-NEXT: lw t1, 92(a0)
-; QCI-D-NEXT: lw t0, 112(a0)
-; QCI-D-NEXT: lw a5, 116(a0)
-; QCI-D-NEXT: lw a3, 120(a0)
+; QCI-D-NEXT: lw a6, 20(a0)
+; QCI-D-NEXT: lw a7, 24(a0)
+; QCI-D-NEXT: lw t0, 28(a0)
+; QCI-D-NEXT: lw t1, 32(a0)
+; QCI-D-NEXT: lw t2, 36(a0)
+; QCI-D-NEXT: lw t3, 40(a0)
+; QCI-D-NEXT: lw t4, 44(a0)
+; QCI-D-NEXT: lw t5, 48(a0)
+; QCI-D-NEXT: lw t6, 52(a0)
+; QCI-D-NEXT: lw s0, 56(a0)
+; QCI-D-NEXT: lw s1, 60(a0)
+; QCI-D-NEXT: lw s2, 64(a0)
+; QCI-D-NEXT: lw s3, 68(a0)
+; QCI-D-NEXT: lw s4, 72(a0)
+; QCI-D-NEXT: lw s5, 76(a0)
+; QCI-D-NEXT: lw s6, 80(a0)
+; QCI-D-NEXT: lw s7, 84(a0)
+; QCI-D-NEXT: lw s8, 88(a0)
+; QCI-D-NEXT: lw s9, 92(a0)
+; QCI-D-NEXT: lw s10, 112(a0)
+; QCI-D-NEXT: lw s11, 116(a0)
+; QCI-D-NEXT: lw ra, 120(a0)
; QCI-D-NEXT: lw a1, 124(a0)
-; QCI-D-NEXT: lw a7, 96(a0)
-; QCI-D-NEXT: lw a6, 100(a0)
-; QCI-D-NEXT: lw a4, 104(a0)
+; QCI-D-NEXT: lw a5, 96(a0)
+; QCI-D-NEXT: lw a4, 100(a0)
+; QCI-D-NEXT: lw a3, 104(a0)
; QCI-D-NEXT: lw a2, 108(a0)
; QCI-D-NEXT: sw a1, 124(a0)
-; QCI-D-NEXT: sw a3, 120(a0)
-; QCI-D-NEXT: sw a5, 116(a0)
-; QCI-D-NEXT: sw t0, 112(a0)
+; QCI-D-NEXT: sw ra, 120(a0)
+; QCI-D-NEXT: sw s11, 116(a0)
+; QCI-D-NEXT: sw s10, 112(a0)
; QCI-D-NEXT: sw a2, 108(a0)
-; QCI-D-NEXT: sw a4, 104(a0)
-; QCI-D-NEXT: sw a6, 100(a0)
-; QCI-D-NEXT: sw a7, 96(a0)
-; QCI-D-NEXT: sw t1, 92(a0)
-; QCI-D-NEXT: sw s1, 88(a0)
-; QCI-D-NEXT: sw s0, 84(a0)
-; QCI-D-NEXT: sw t2, 80(a0)
-; QCI-D-NEXT: sw ra, 76(a0)
-; QCI-D-NEXT: sw s11, 72(a0)
-; QCI-D-NEXT: sw s10, 68(a0)
-; QCI-D-NEXT: sw s9, 64(a0)
-; QCI-D-NEXT: sw s8, 60(a0)
-; QCI-D-NEXT: sw s7, 56(a0)
-; QCI-D-NEXT: sw s6, 52(a0)
-; QCI-D-NEXT: sw s5, 48(a0)
-; QCI-D-NEXT: sw s4, 44(a0)
-; QCI-D-NEXT: sw s3, 40(a0)
-; QCI-D-NEXT: sw s2, 36(a0)
-; QCI-D-NEXT: sw t6, 32(a0)
-; QCI-D-NEXT: sw t5, 28(a0)
-; QCI-D-NEXT: sw t4, 24(a0)
-; QCI-D-NEXT: sw t3, 20(a0)
+; QCI-D-NEXT: sw a3, 104(a0)
+; QCI-D-NEXT: sw a4, 100(a0)
+; QCI-D-NEXT: sw a5, 96(a0)
+; QCI-D-NEXT: sw s9, 92(a0)
+; QCI-D-NEXT: sw s8, 88(a0)
+; QCI-D-NEXT: sw s7, 84(a0)
+; QCI-D-NEXT: sw s6, 80(a0)
+; QCI-D-NEXT: sw s5, 76(a0)
+; QCI-D-NEXT: sw s4, 72(a0)
+; QCI-D-NEXT: sw s3, 68(a0)
+; QCI-D-NEXT: sw s2, 64(a0)
+; QCI-D-NEXT: sw s1, 60(a0)
+; QCI-D-NEXT: sw s0, 56(a0)
+; QCI-D-NEXT: sw t6, 52(a0)
+; QCI-D-NEXT: sw t5, 48(a0)
+; QCI-D-NEXT: sw t4, 44(a0)
+; QCI-D-NEXT: sw t3, 40(a0)
+; QCI-D-NEXT: sw t2, 36(a0)
+; QCI-D-NEXT: sw t1, 32(a0)
+; QCI-D-NEXT: sw t0, 28(a0)
+; QCI-D-NEXT: sw a7, 24(a0)
+; QCI-D-NEXT: sw a6, 20(a0)
; QCI-D-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; QCI-D-NEXT: sw a1, 16(a0)
; QCI-D-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
@@ -1764,60 +1764,58 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-F-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; QCI-F-NEXT: lw a0, 80(s0)
; QCI-F-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 84(s0)
-; QCI-F-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw s2, 88(s0)
-; QCI-F-NEXT: lw s3, 92(s0)
-; QCI-F-NEXT: lw s4, 96(s0)
-; QCI-F-NEXT: lw s5, 100(s0)
-; QCI-F-NEXT: lw s6, 104(s0)
-; QCI-F-NEXT: lw s7, 108(s0)
-; QCI-F-NEXT: lw s8, 112(s0)
-; QCI-F-NEXT: lw s9, 116(s0)
-; QCI-F-NEXT: lw s10, 120(s0)
-; QCI-F-NEXT: lw s11, 124(s0)
-; QCI-F-NEXT: lui a7, 266496
-; QCI-F-NEXT: li t0, 5
+; QCI-F-NEXT: lw s11, 84(s0)
+; QCI-F-NEXT: lw s1, 88(s0)
+; QCI-F-NEXT: lw s2, 92(s0)
+; QCI-F-NEXT: lw s3, 96(s0)
+; QCI-F-NEXT: lw s4, 100(s0)
+; QCI-F-NEXT: lw s5, 104(s0)
+; QCI-F-NEXT: lw s6, 108(s0)
+; QCI-F-NEXT: lw s7, 112(s0)
+; QCI-F-NEXT: lw s8, 116(s0)
+; QCI-F-NEXT: lw s9, 120(s0)
+; QCI-F-NEXT: lw s10, 124(s0)
+; QCI-F-NEXT: lui a1, 266496
+; QCI-F-NEXT: li a3, 5
; QCI-F-NEXT: lui a0, 260096
; QCI-F-NEXT: lui a2, 262144
; QCI-F-NEXT: lui a4, 263168
; QCI-F-NEXT: lui a5, 264192
-; QCI-F-NEXT: lui a1, 264704
-; QCI-F-NEXT: lui a6, 265216
+; QCI-F-NEXT: lui a6, 264704
+; QCI-F-NEXT: lui a7, 265216
; QCI-F-NEXT: fmv.w.x fa0, a0
-; QCI-F-NEXT: lui s1, 265728
+; QCI-F-NEXT: lui t0, 265728
; QCI-F-NEXT: fmv.w.x fa1, a2
-; QCI-F-NEXT: lui a3, 266240
+; QCI-F-NEXT: lui t1, 266240
; QCI-F-NEXT: fmv.w.x fa2, a4
; QCI-F-NEXT: li a0, 1
; QCI-F-NEXT: fmv.w.x fa3, a5
; QCI-F-NEXT: li a2, 2
-; QCI-F-NEXT: fmv.w.x fa4, a1
+; QCI-F-NEXT: fmv.w.x fa4, a6
; QCI-F-NEXT: li a4, 3
-; QCI-F-NEXT: fmv.w.x fa5, a6
+; QCI-F-NEXT: fmv.w.x fa5, a7
; QCI-F-NEXT: li a6, 4
-; QCI-F-NEXT: fmv.w.x fa6, s1
-; QCI-F-NEXT: fmv.w.x fa7, a3
-; QCI-F-NEXT: sw t0, 0(sp)
-; QCI-F-NEXT: sw a7, 4(sp)
+; QCI-F-NEXT: fmv.w.x fa6, t0
+; QCI-F-NEXT: fmv.w.x fa7, t1
+; QCI-F-NEXT: sw a3, 0(sp)
+; QCI-F-NEXT: sw a1, 4(sp)
; QCI-F-NEXT: li a1, 0
; QCI-F-NEXT: li a3, 0
; QCI-F-NEXT: li a5, 0
; QCI-F-NEXT: li a7, 0
; QCI-F-NEXT: call function_with_one_stack_arg
; QCI-F-NEXT: call use_float
-; QCI-F-NEXT: sw s11, 124(s0)
-; QCI-F-NEXT: sw s10, 120(s0)
-; QCI-F-NEXT: sw s9, 116(s0)
-; QCI-F-NEXT: sw s8, 112(s0)
-; QCI-F-NEXT: sw s7, 108(s0)
-; QCI-F-NEXT: sw s6, 104(s0)
-; QCI-F-NEXT: sw s5, 100(s0)
-; QCI-F-NEXT: sw s4, 96(s0)
-; QCI-F-NEXT: sw s3, 92(s0)
-; QCI-F-NEXT: sw s2, 88(s0)
-; QCI-F-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 84(s0)
+; QCI-F-NEXT: sw s10, 124(s0)
+; QCI-F-NEXT: sw s9, 120(s0)
+; QCI-F-NEXT: sw s8, 116(s0)
+; QCI-F-NEXT: sw s7, 112(s0)
+; QCI-F-NEXT: sw s6, 108(s0)
+; QCI-F-NEXT: sw s5, 104(s0)
+; QCI-F-NEXT: sw s4, 100(s0)
+; QCI-F-NEXT: sw s3, 96(s0)
+; QCI-F-NEXT: sw s2, 92(s0)
+; QCI-F-NEXT: sw s1, 88(s0)
+; QCI-F-NEXT: sw s11, 84(s0)
; QCI-F-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
; QCI-F-NEXT: sw a0, 80(s0)
; QCI-F-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
@@ -2055,60 +2053,58 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-D-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; QCI-D-NEXT: lw a0, 80(s0)
; QCI-D-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 84(s0)
-; QCI-D-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw s2, 88(s0)
-; QCI-D-NEXT: lw s3, 92(s0)
-; QCI-D-NEXT: lw s4, 96(s0)
-; QCI-D-NEXT: lw s5, 100(s0)
-; QCI-D-NEXT: lw s6, 104(s0)
-; QCI-D-NEXT: lw s7, 108(s0)
-; QCI-D-NEXT: lw s8, 112(s0)
-; QCI-D-NEXT: lw s9, 116(s0)
-; QCI-D-NEXT: lw s10, 120(s0)
-; QCI-D-NEXT: lw s11, 124(s0)
-; QCI-D-NEXT: lui a7, 266496
-; QCI-D-NEXT: li t0, 5
+; QCI-D-NEXT: lw s11, 84(s0)
+; QCI-D-NEXT: lw s1, 88(s0)
+; QCI-D-NEXT: lw s2, 92(s0)
+; QCI-D-NEXT: lw s3, 96(s0)
+; QCI-D-NEXT: lw s4, 100(s0)
+; QCI-D-NEXT: lw s5, 104(s0)
+; QCI-D-NEXT: lw s6, 108(s0)
+; QCI-D-NEXT: lw s7, 112(s0)
+; QCI-D-NEXT: lw s8, 116(s0)
+; QCI-D-NEXT: lw s9, 120(s0)
+; QCI-D-NEXT: lw s10, 124(s0)
+; QCI-D-NEXT: lui a1, 266496
+; QCI-D-NEXT: li a3, 5
; QCI-D-NEXT: lui a0, 260096
; QCI-D-NEXT: lui a2, 262144
; QCI-D-NEXT: lui a4, 263168
; QCI-D-NEXT: lui a5, 264192
-; QCI-D-NEXT: lui a1, 264704
-; QCI-D-NEXT: lui a6, 265216
+; QCI-D-NEXT: lui a6, 264704
+; QCI-D-NEXT: lui a7, 265216
; QCI-D-NEXT: fmv.w.x fa0, a0
-; QCI-D-NEXT: lui s1, 265728
+; QCI-D-NEXT: lui t0, 265728
; QCI-D-NEXT: fmv.w.x fa1, a2
-; QCI-D-NEXT: lui a3, 266240
+; QCI-D-NEXT: lui t1, 266240
; QCI-D-NEXT: fmv.w.x fa2, a4
; QCI-D-NEXT: li a0, 1
; QCI-D-NEXT: fmv.w.x fa3, a5
; QCI-D-NEXT: li a2, 2
-; QCI-D-NEXT: fmv.w.x fa4, a1
+; QCI-D-NEXT: fmv.w.x fa4, a6
; QCI-D-NEXT: li a4, 3
-; QCI-D-NEXT: fmv.w.x fa5, a6
+; QCI-D-NEXT: fmv.w.x fa5, a7
; QCI-D-NEXT: li a6, 4
-; QCI-D-NEXT: fmv.w.x fa6, s1
-; QCI-D-NEXT: fmv.w.x fa7, a3
-; QCI-D-NEXT: sw t0, 0(sp)
-; QCI-D-NEXT: sw a7, 4(sp)
+; QCI-D-NEXT: fmv.w.x fa6, t0
+; QCI-D-NEXT: fmv.w.x fa7, t1
+; QCI-D-NEXT: sw a3, 0(sp)
+; QCI-D-NEXT: sw a1, 4(sp)
; QCI-D-NEXT: li a1, 0
; QCI-D-NEXT: li a3, 0
; QCI-D-NEXT: li a5, 0
; QCI-D-NEXT: li a7, 0
; QCI-D-NEXT: call function_with_one_stack_arg
; QCI-D-NEXT: call use_float
-; QCI-D-NEXT: sw s11, 124(s0)
-; QCI-D-NEXT: sw s10, 120(s0)
-; QCI-D-NEXT: sw s9, 116(s0)
-; QCI-D-NEXT: sw s8, 112(s0)
-; QCI-D-NEXT: sw s7, 108(s0)
-; QCI-D-NEXT: sw s6, 104(s0)
-; QCI-D-NEXT: sw s5, 100(s0)
-; QCI-D-NEXT: sw s4, 96(s0)
-; QCI-D-NEXT: sw s3, 92(s0)
-; QCI-D-NEXT: sw s2, 88(s0)
-; QCI-D-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 84(s0)
+; QCI-D-NEXT: sw s10, 124(s0)
+; QCI-D-NEXT: sw s9, 120(s0)
+; QCI-D-NEXT: sw s8, 116(s0)
+; QCI-D-NEXT: sw s7, 112(s0)
+; QCI-D-NEXT: sw s6, 108(s0)
+; QCI-D-NEXT: sw s5, 104(s0)
+; QCI-D-NEXT: sw s4, 100(s0)
+; QCI-D-NEXT: sw s3, 96(s0)
+; QCI-D-NEXT: sw s2, 92(s0)
+; QCI-D-NEXT: sw s1, 88(s0)
+; QCI-D-NEXT: sw s11, 84(s0)
; QCI-D-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; QCI-D-NEXT: sw a0, 80(s0)
; QCI-D-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
@@ -2353,60 +2349,58 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-F-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; QCI-F-NEXT: lw a0, 80(s0)
; QCI-F-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw a0, 84(s0)
-; QCI-F-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-F-NEXT: lw s2, 88(s0)
-; QCI-F-NEXT: lw s3, 92(s0)
-; QCI-F-NEXT: lw s4, 96(s0)
-; QCI-F-NEXT: lw s5, 100(s0)
-; QCI-F-NEXT: lw s6, 104(s0)
-; QCI-F-NEXT: lw s7, 108(s0)
-; QCI-F-NEXT: lw s8, 112(s0)
-; QCI-F-NEXT: lw s9, 116(s0)
-; QCI-F-NEXT: lw s10, 120(s0)
-; QCI-F-NEXT: lw s11, 124(s0)
-; QCI-F-NEXT: lui a7, 266496
-; QCI-F-NEXT: li t0, 5
+; QCI-F-NEXT: lw s11, 84(s0)
+; QCI-F-NEXT: lw s1, 88(s0)
+; QCI-F-NEXT: lw s2, 92(s0)
+; QCI-F-NEXT: lw s3, 96(s0)
+; QCI-F-NEXT: lw s4, 100(s0)
+; QCI-F-NEXT: lw s5, 104(s0)
+; QCI-F-NEXT: lw s6, 108(s0)
+; QCI-F-NEXT: lw s7, 112(s0)
+; QCI-F-NEXT: lw s8, 116(s0)
+; QCI-F-NEXT: lw s9, 120(s0)
+; QCI-F-NEXT: lw s10, 124(s0)
+; QCI-F-NEXT: lui a1, 266496
+; QCI-F-NEXT: li a3, 5
; QCI-F-NEXT: lui a0, 260096
; QCI-F-NEXT: lui a2, 262144
; QCI-F-NEXT: lui a4, 263168
; QCI-F-NEXT: lui a5, 264192
-; QCI-F-NEXT: lui a1, 264704
-; QCI-F-NEXT: lui a6, 265216
+; QCI-F-NEXT: lui a6, 264704
+; QCI-F-NEXT: lui a7, 265216
; QCI-F-NEXT: fmv.w.x fa0, a0
-; QCI-F-NEXT: lui s1, 265728
+; QCI-F-NEXT: lui t0, 265728
; QCI-F-NEXT: fmv.w.x fa1, a2
-; QCI-F-NEXT: lui a3, 266240
+; QCI-F-NEXT: lui t1, 266240
; QCI-F-NEXT: fmv.w.x fa2, a4
; QCI-F-NEXT: li a0, 1
; QCI-F-NEXT: fmv.w.x fa3, a5
; QCI-F-NEXT: li a2, 2
-; QCI-F-NEXT: fmv.w.x fa4, a1
+; QCI-F-NEXT: fmv.w.x fa4, a6
; QCI-F-NEXT: li a4, 3
-; QCI-F-NEXT: fmv.w.x fa5, a6
+; QCI-F-NEXT: fmv.w.x fa5, a7
; QCI-F-NEXT: li a6, 4
-; QCI-F-NEXT: fmv.w.x fa6, s1
-; QCI-F-NEXT: fmv.w.x fa7, a3
-; QCI-F-NEXT: sw t0, 0(sp)
-; QCI-F-NEXT: sw a7, 4(sp)
+; QCI-F-NEXT: fmv.w.x fa6, t0
+; QCI-F-NEXT: fmv.w.x fa7, t1
+; QCI-F-NEXT: sw a3, 0(sp)
+; QCI-F-NEXT: sw a1, 4(sp)
; QCI-F-NEXT: li a1, 0
; QCI-F-NEXT: li a3, 0
; QCI-F-NEXT: li a5, 0
; QCI-F-NEXT: li a7, 0
; QCI-F-NEXT: call function_with_one_stack_arg
; QCI-F-NEXT: call use_float
-; QCI-F-NEXT: sw s11, 124(s0)
-; QCI-F-NEXT: sw s10, 120(s0)
-; QCI-F-NEXT: sw s9, 116(s0)
-; QCI-F-NEXT: sw s8, 112(s0)
-; QCI-F-NEXT: sw s7, 108(s0)
-; QCI-F-NEXT: sw s6, 104(s0)
-; QCI-F-NEXT: sw s5, 100(s0)
-; QCI-F-NEXT: sw s4, 96(s0)
-; QCI-F-NEXT: sw s3, 92(s0)
-; QCI-F-NEXT: sw s2, 88(s0)
-; QCI-F-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
-; QCI-F-NEXT: sw a0, 84(s0)
+; QCI-F-NEXT: sw s10, 124(s0)
+; QCI-F-NEXT: sw s9, 120(s0)
+; QCI-F-NEXT: sw s8, 116(s0)
+; QCI-F-NEXT: sw s7, 112(s0)
+; QCI-F-NEXT: sw s6, 108(s0)
+; QCI-F-NEXT: sw s5, 104(s0)
+; QCI-F-NEXT: sw s4, 100(s0)
+; QCI-F-NEXT: sw s3, 96(s0)
+; QCI-F-NEXT: sw s2, 92(s0)
+; QCI-F-NEXT: sw s1, 88(s0)
+; QCI-F-NEXT: sw s11, 84(s0)
; QCI-F-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
; QCI-F-NEXT: sw a0, 80(s0)
; QCI-F-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
@@ -2644,60 +2638,58 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-D-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; QCI-D-NEXT: lw a0, 80(s0)
; QCI-D-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw a0, 84(s0)
-; QCI-D-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
-; QCI-D-NEXT: lw s2, 88(s0)
-; QCI-D-NEXT: lw s3, 92(s0)
-; QCI-D-NEXT: lw s4, 96(s0)
-; QCI-D-NEXT: lw s5, 100(s0)
-; QCI-D-NEXT: lw s6, 104(s0)
-; QCI-D-NEXT: lw s7, 108(s0)
-; QCI-D-NEXT: lw s8, 112(s0)
-; QCI-D-NEXT: lw s9, 116(s0)
-; QCI-D-NEXT: lw s10, 120(s0)
-; QCI-D-NEXT: lw s11, 124(s0)
-; QCI-D-NEXT: lui a7, 266496
-; QCI-D-NEXT: li t0, 5
+; QCI-D-NEXT: lw s11, 84(s0)
+; QCI-D-NEXT: lw s1, 88(s0)
+; QCI-D-NEXT: lw s2, 92(s0)
+; QCI-D-NEXT: lw s3, 96(s0)
+; QCI-D-NEXT: lw s4, 100(s0)
+; QCI-D-NEXT: lw s5, 104(s0)
+; QCI-D-NEXT: lw s6, 108(s0)
+; QCI-D-NEXT: lw s7, 112(s0)
+; QCI-D-NEXT: lw s8, 116(s0)
+; QCI-D-NEXT: lw s9, 120(s0)
+; QCI-D-NEXT: lw s10, 124(s0)
+; QCI-D-NEXT: lui a1, 266496
+; QCI-D-NEXT: li a3, 5
; QCI-D-NEXT: lui a0, 260096
; QCI-D-NEXT: lui a2, 262144
; QCI-D-NEXT: lui a4, 263168
; QCI-D-NEXT: lui a5, 264192
-; QCI-D-NEXT: lui a1, 264704
-; QCI-D-NEXT: lui a6, 265216
+; QCI-D-NEXT: lui a6, 264704
+; QCI-D-NEXT: lui a7, 265216
; QCI-D-NEXT: fmv.w.x fa0, a0
-; QCI-D-NEXT: lui s1, 265728
+; QCI-D-NEXT: lui t0, 265728
; QCI-D-NEXT: fmv.w.x fa1, a2
-; QCI-D-NEXT: lui a3, 266240
+; QCI-D-NEXT: lui t1, 266240
; QCI-D-NEXT: fmv.w.x fa2, a4
; QCI-D-NEXT: li a0, 1
; QCI-D-NEXT: fmv.w.x fa3, a5
; QCI-D-NEXT: li a2, 2
-; QCI-D-NEXT: fmv.w.x fa4, a1
+; QCI-D-NEXT: fmv.w.x fa4, a6
; QCI-D-NEXT: li a4, 3
-; QCI-D-NEXT: fmv.w.x fa5, a6
+; QCI-D-NEXT: fmv.w.x fa5, a7
; QCI-D-NEXT: li a6, 4
-; QCI-D-NEXT: fmv.w.x fa6, s1
-; QCI-D-NEXT: fmv.w.x fa7, a3
-; QCI-D-NEXT: sw t0, 0(sp)
-; QCI-D-NEXT: sw a7, 4(sp)
+; QCI-D-NEXT: fmv.w.x fa6, t0
+; QCI-D-NEXT: fmv.w.x fa7, t1
+; QCI-D-NEXT: sw a3, 0(sp)
+; QCI-D-NEXT: sw a1, 4(sp)
; QCI-D-NEXT: li a1, 0
; QCI-D-NEXT: li a3, 0
; QCI-D-NEXT: li a5, 0
; QCI-D-NEXT: li a7, 0
; QCI-D-NEXT: call function_with_one_stack_arg
; QCI-D-NEXT: call use_float
-; QCI-D-NEXT: sw s11, 124(s0)
-; QCI-D-NEXT: sw s10, 120(s0)
-; QCI-D-NEXT: sw s9, 116(s0)
-; QCI-D-NEXT: sw s8, 112(s0)
-; QCI-D-NEXT: sw s7, 108(s0)
-; QCI-D-NEXT: sw s6, 104(s0)
-; QCI-D-NEXT: sw s5, 100(s0)
-; QCI-D-NEXT: sw s4, 96(s0)
-; QCI-D-NEXT: sw s3, 92(s0)
-; QCI-D-NEXT: sw s2, 88(s0)
-; QCI-D-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
-; QCI-D-NEXT: sw a0, 84(s0)
+; QCI-D-NEXT: sw s10, 124(s0)
+; QCI-D-NEXT: sw s9, 120(s0)
+; QCI-D-NEXT: sw s8, 116(s0)
+; QCI-D-NEXT: sw s7, 112(s0)
+; QCI-D-NEXT: sw s6, 108(s0)
+; QCI-D-NEXT: sw s5, 104(s0)
+; QCI-D-NEXT: sw s4, 100(s0)
+; QCI-D-NEXT: sw s3, 96(s0)
+; QCI-D-NEXT: sw s2, 92(s0)
+; QCI-D-NEXT: sw s1, 88(s0)
+; QCI-D-NEXT: sw s11, 84(s0)
; QCI-D-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; QCI-D-NEXT: sw a0, 80(s0)
; QCI-D-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll b/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
index 7e0a7cc52cc51..5c2f4bc7407c0 100644
--- a/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
+++ b/llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll
@@ -1045,60 +1045,60 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; QCI-NEXT: lw a1, 16(a0)
; QCI-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw t3, 20(a0)
-; QCI-NEXT: lw t4, 24(a0)
-; QCI-NEXT: lw t5, 28(a0)
-; QCI-NEXT: lw t6, 32(a0)
-; QCI-NEXT: lw s2, 36(a0)
-; QCI-NEXT: lw s3, 40(a0)
-; QCI-NEXT: lw s4, 44(a0)
-; QCI-NEXT: lw s5, 48(a0)
-; QCI-NEXT: lw s6, 52(a0)
-; QCI-NEXT: lw s7, 56(a0)
-; QCI-NEXT: lw s8, 60(a0)
-; QCI-NEXT: lw s9, 64(a0)
-; QCI-NEXT: lw s10, 68(a0)
-; QCI-NEXT: lw s11, 72(a0)
-; QCI-NEXT: lw ra, 76(a0)
-; QCI-NEXT: lw t2, 80(a0)
-; QCI-NEXT: lw s0, 84(a0)
-; QCI-NEXT: lw s1, 88(a0)
-; QCI-NEXT: lw t1, 92(a0)
-; QCI-NEXT: lw t0, 112(a0)
-; QCI-NEXT: lw a5, 116(a0)
-; QCI-NEXT: lw a3, 120(a0)
+; QCI-NEXT: lw a6, 20(a0)
+; QCI-NEXT: lw a7, 24(a0)
+; QCI-NEXT: lw t0, 28(a0)
+; QCI-NEXT: lw t1, 32(a0)
+; QCI-NEXT: lw t2, 36(a0)
+; QCI-NEXT: lw t3, 40(a0)
+; QCI-NEXT: lw t4, 44(a0)
+; QCI-NEXT: lw t5, 48(a0)
+; QCI-NEXT: lw t6, 52(a0)
+; QCI-NEXT: lw s0, 56(a0)
+; QCI-NEXT: lw s1, 60(a0)
+; QCI-NEXT: lw s2, 64(a0)
+; QCI-NEXT: lw s3, 68(a0)
+; QCI-NEXT: lw s4, 72(a0)
+; QCI-NEXT: lw s5, 76(a0)
+; QCI-NEXT: lw s6, 80(a0)
+; QCI-NEXT: lw s7, 84(a0)
+; QCI-NEXT: lw s8, 88(a0)
+; QCI-NEXT: lw s9, 92(a0)
+; QCI-NEXT: lw s10, 112(a0)
+; QCI-NEXT: lw s11, 116(a0)
+; QCI-NEXT: lw ra, 120(a0)
; QCI-NEXT: lw a1, 124(a0)
-; QCI-NEXT: lw a7, 96(a0)
-; QCI-NEXT: lw a6, 100(a0)
-; QCI-NEXT: lw a4, 104(a0)
+; QCI-NEXT: lw a5, 96(a0)
+; QCI-NEXT: lw a4, 100(a0)
+; QCI-NEXT: lw a3, 104(a0)
; QCI-NEXT: lw a2, 108(a0)
; QCI-NEXT: sw a1, 124(a0)
-; QCI-NEXT: sw a3, 120(a0)
-; QCI-NEXT: sw a5, 116(a0)
-; QCI-NEXT: sw t0, 112(a0)
+; QCI-NEXT: sw ra, 120(a0)
+; QCI-NEXT: sw s11, 116(a0)
+; QCI-NEXT: sw s10, 112(a0)
; QCI-NEXT: sw a2, 108(a0)
-; QCI-NEXT: sw a4, 104(a0)
-; QCI-NEXT: sw a6, 100(a0)
-; QCI-NEXT: sw a7, 96(a0)
-; QCI-NEXT: sw t1, 92(a0)
-; QCI-NEXT: sw s1, 88(a0)
-; QCI-NEXT: sw s0, 84(a0)
-; QCI-NEXT: sw t2, 80(a0)
-; QCI-NEXT: sw ra, 76(a0)
-; QCI-NEXT: sw s11, 72(a0)
-; QCI-NEXT: sw s10, 68(a0)
-; QCI-NEXT: sw s9, 64(a0)
-; QCI-NEXT: sw s8, 60(a0)
-; QCI-NEXT: sw s7, 56(a0)
-; QCI-NEXT: sw s6, 52(a0)
-; QCI-NEXT: sw s5, 48(a0)
-; QCI-NEXT: sw s4, 44(a0)
-; QCI-NEXT: sw s3, 40(a0)
-; QCI-NEXT: sw s2, 36(a0)
-; QCI-NEXT: sw t6, 32(a0)
-; QCI-NEXT: sw t5, 28(a0)
-; QCI-NEXT: sw t4, 24(a0)
-; QCI-NEXT: sw t3, 20(a0)
+; QCI-NEXT: sw a3, 104(a0)
+; QCI-NEXT: sw a4, 100(a0)
+; QCI-NEXT: sw a5, 96(a0)
+; QCI-NEXT: sw s9, 92(a0)
+; QCI-NEXT: sw s8, 88(a0)
+; QCI-NEXT: sw s7, 84(a0)
+; QCI-NEXT: sw s6, 80(a0)
+; QCI-NEXT: sw s5, 76(a0)
+; QCI-NEXT: sw s4, 72(a0)
+; QCI-NEXT: sw s3, 68(a0)
+; QCI-NEXT: sw s2, 64(a0)
+; QCI-NEXT: sw s1, 60(a0)
+; QCI-NEXT: sw s0, 56(a0)
+; QCI-NEXT: sw t6, 52(a0)
+; QCI-NEXT: sw t5, 48(a0)
+; QCI-NEXT: sw t4, 44(a0)
+; QCI-NEXT: sw t3, 40(a0)
+; QCI-NEXT: sw t2, 36(a0)
+; QCI-NEXT: sw t1, 32(a0)
+; QCI-NEXT: sw t0, 28(a0)
+; QCI-NEXT: sw a7, 24(a0)
+; QCI-NEXT: sw a6, 20(a0)
; QCI-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; QCI-NEXT: sw a1, 16(a0)
; QCI-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
@@ -1195,58 +1195,58 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-FP-NEXT: sw a1, -160(s0) # 4-byte Folded Spill
; QCI-FP-NEXT: lw a1, 20(a0)
; QCI-FP-NEXT: sw a1, -164(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw t4, 24(a0)
-; QCI-FP-NEXT: lw t5, 28(a0)
-; QCI-FP-NEXT: lw t6, 32(a0)
-; QCI-FP-NEXT: lw s2, 36(a0)
-; QCI-FP-NEXT: lw s3, 40(a0)
-; QCI-FP-NEXT: lw s4, 44(a0)
-; QCI-FP-NEXT: lw s5, 48(a0)
-; QCI-FP-NEXT: lw s6, 52(a0)
-; QCI-FP-NEXT: lw s7, 56(a0)
-; QCI-FP-NEXT: lw s8, 60(a0)
-; QCI-FP-NEXT: lw s9, 64(a0)
-; QCI-FP-NEXT: lw s10, 68(a0)
-; QCI-FP-NEXT: lw s11, 72(a0)
-; QCI-FP-NEXT: lw ra, 76(a0)
-; QCI-FP-NEXT: lw s1, 80(a0)
-; QCI-FP-NEXT: lw t3, 84(a0)
-; QCI-FP-NEXT: lw t2, 88(a0)
-; QCI-FP-NEXT: lw t1, 92(a0)
-; QCI-FP-NEXT: lw t0, 112(a0)
-; QCI-FP-NEXT: lw a6, 116(a0)
+; QCI-FP-NEXT: lw a7, 24(a0)
+; QCI-FP-NEXT: lw t0, 28(a0)
+; QCI-FP-NEXT: lw t1, 32(a0)
+; QCI-FP-NEXT: lw t2, 36(a0)
+; QCI-FP-NEXT: lw t3, 40(a0)
+; QCI-FP-NEXT: lw t4, 44(a0)
+; QCI-FP-NEXT: lw t5, 48(a0)
+; QCI-FP-NEXT: lw t6, 52(a0)
+; QCI-FP-NEXT: lw s1, 56(a0)
+; QCI-FP-NEXT: lw s2, 60(a0)
+; QCI-FP-NEXT: lw s3, 64(a0)
+; QCI-FP-NEXT: lw s4, 68(a0)
+; QCI-FP-NEXT: lw s5, 72(a0)
+; QCI-FP-NEXT: lw s6, 76(a0)
+; QCI-FP-NEXT: lw s7, 80(a0)
+; QCI-FP-NEXT: lw s8, 84(a0)
+; QCI-FP-NEXT: lw s9, 88(a0)
+; QCI-FP-NEXT: lw s10, 92(a0)
+; QCI-FP-NEXT: lw s11, 112(a0)
+; QCI-FP-NEXT: lw ra, 116(a0)
; QCI-FP-NEXT: lw a4, 120(a0)
; QCI-FP-NEXT: lw a1, 124(a0)
-; QCI-FP-NEXT: lw a7, 96(a0)
+; QCI-FP-NEXT: lw a6, 96(a0)
; QCI-FP-NEXT: lw a5, 100(a0)
; QCI-FP-NEXT: lw a3, 104(a0)
; QCI-FP-NEXT: lw a2, 108(a0)
; QCI-FP-NEXT: sw a1, 124(a0)
; QCI-FP-NEXT: sw a4, 120(a0)
-; QCI-FP-NEXT: sw a6, 116(a0)
-; QCI-FP-NEXT: sw t0, 112(a0)
+; QCI-FP-NEXT: sw ra, 116(a0)
+; QCI-FP-NEXT: sw s11, 112(a0)
; QCI-FP-NEXT: sw a2, 108(a0)
; QCI-FP-NEXT: sw a3, 104(a0)
; QCI-FP-NEXT: sw a5, 100(a0)
-; QCI-FP-NEXT: sw a7, 96(a0)
-; QCI-FP-NEXT: sw t1, 92(a0)
-; QCI-FP-NEXT: sw t2, 88(a0)
-; QCI-FP-NEXT: sw t3, 84(a0)
-; QCI-FP-NEXT: sw s1, 80(a0)
-; QCI-FP-NEXT: sw ra, 76(a0)
-; QCI-FP-NEXT: sw s11, 72(a0)
-; QCI-FP-NEXT: sw s10, 68(a0)
-; QCI-FP-NEXT: sw s9, 64(a0)
-; QCI-FP-NEXT: sw s8, 60(a0)
-; QCI-FP-NEXT: sw s7, 56(a0)
-; QCI-FP-NEXT: sw s6, 52(a0)
-; QCI-FP-NEXT: sw s5, 48(a0)
-; QCI-FP-NEXT: sw s4, 44(a0)
-; QCI-FP-NEXT: sw s3, 40(a0)
-; QCI-FP-NEXT: sw s2, 36(a0)
-; QCI-FP-NEXT: sw t6, 32(a0)
-; QCI-FP-NEXT: sw t5, 28(a0)
-; QCI-FP-NEXT: sw t4, 24(a0)
+; QCI-FP-NEXT: sw a6, 96(a0)
+; QCI-FP-NEXT: sw s10, 92(a0)
+; QCI-FP-NEXT: sw s9, 88(a0)
+; QCI-FP-NEXT: sw s8, 84(a0)
+; QCI-FP-NEXT: sw s7, 80(a0)
+; QCI-FP-NEXT: sw s6, 76(a0)
+; QCI-FP-NEXT: sw s5, 72(a0)
+; QCI-FP-NEXT: sw s4, 68(a0)
+; QCI-FP-NEXT: sw s3, 64(a0)
+; QCI-FP-NEXT: sw s2, 60(a0)
+; QCI-FP-NEXT: sw s1, 56(a0)
+; QCI-FP-NEXT: sw t6, 52(a0)
+; QCI-FP-NEXT: sw t5, 48(a0)
+; QCI-FP-NEXT: sw t4, 44(a0)
+; QCI-FP-NEXT: sw t3, 40(a0)
+; QCI-FP-NEXT: sw t2, 36(a0)
+; QCI-FP-NEXT: sw t1, 32(a0)
+; QCI-FP-NEXT: sw t0, 28(a0)
+; QCI-FP-NEXT: sw a7, 24(a0)
; QCI-FP-NEXT: lw a1, -164(s0) # 4-byte Folded Reload
; QCI-FP-NEXT: sw a1, 20(a0)
; QCI-FP-NEXT: lw a1, -160(s0) # 4-byte Folded Reload
@@ -1332,60 +1332,60 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-PUSH-POP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; QCI-PUSH-POP-NEXT: lw a1, 16(a0)
; QCI-PUSH-POP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw t3, 20(a0)
-; QCI-PUSH-POP-NEXT: lw t4, 24(a0)
-; QCI-PUSH-POP-NEXT: lw t5, 28(a0)
-; QCI-PUSH-POP-NEXT: lw t6, 32(a0)
-; QCI-PUSH-POP-NEXT: lw s2, 36(a0)
-; QCI-PUSH-POP-NEXT: lw s3, 40(a0)
-; QCI-PUSH-POP-NEXT: lw s4, 44(a0)
-; QCI-PUSH-POP-NEXT: lw s5, 48(a0)
-; QCI-PUSH-POP-NEXT: lw s6, 52(a0)
-; QCI-PUSH-POP-NEXT: lw s7, 56(a0)
-; QCI-PUSH-POP-NEXT: lw s8, 60(a0)
-; QCI-PUSH-POP-NEXT: lw s9, 64(a0)
-; QCI-PUSH-POP-NEXT: lw s10, 68(a0)
-; QCI-PUSH-POP-NEXT: lw s11, 72(a0)
-; QCI-PUSH-POP-NEXT: lw ra, 76(a0)
-; QCI-PUSH-POP-NEXT: lw t2, 80(a0)
-; QCI-PUSH-POP-NEXT: lw s0, 84(a0)
-; QCI-PUSH-POP-NEXT: lw s1, 88(a0)
-; QCI-PUSH-POP-NEXT: lw t1, 92(a0)
-; QCI-PUSH-POP-NEXT: lw t0, 112(a0)
-; QCI-PUSH-POP-NEXT: lw a5, 116(a0)
-; QCI-PUSH-POP-NEXT: lw a3, 120(a0)
+; QCI-PUSH-POP-NEXT: lw a6, 20(a0)
+; QCI-PUSH-POP-NEXT: lw a7, 24(a0)
+; QCI-PUSH-POP-NEXT: lw t0, 28(a0)
+; QCI-PUSH-POP-NEXT: lw t1, 32(a0)
+; QCI-PUSH-POP-NEXT: lw t2, 36(a0)
+; QCI-PUSH-POP-NEXT: lw t3, 40(a0)
+; QCI-PUSH-POP-NEXT: lw t4, 44(a0)
+; QCI-PUSH-POP-NEXT: lw t5, 48(a0)
+; QCI-PUSH-POP-NEXT: lw t6, 52(a0)
+; QCI-PUSH-POP-NEXT: lw s0, 56(a0)
+; QCI-PUSH-POP-NEXT: lw s1, 60(a0)
+; QCI-PUSH-POP-NEXT: lw s2, 64(a0)
+; QCI-PUSH-POP-NEXT: lw s3, 68(a0)
+; QCI-PUSH-POP-NEXT: lw s4, 72(a0)
+; QCI-PUSH-POP-NEXT: lw s5, 76(a0)
+; QCI-PUSH-POP-NEXT: lw s6, 80(a0)
+; QCI-PUSH-POP-NEXT: lw s7, 84(a0)
+; QCI-PUSH-POP-NEXT: lw s8, 88(a0)
+; QCI-PUSH-POP-NEXT: lw s9, 92(a0)
+; QCI-PUSH-POP-NEXT: lw s10, 112(a0)
+; QCI-PUSH-POP-NEXT: lw s11, 116(a0)
+; QCI-PUSH-POP-NEXT: lw ra, 120(a0)
; QCI-PUSH-POP-NEXT: lw a1, 124(a0)
-; QCI-PUSH-POP-NEXT: lw a7, 96(a0)
-; QCI-PUSH-POP-NEXT: lw a6, 100(a0)
-; QCI-PUSH-POP-NEXT: lw a4, 104(a0)
+; QCI-PUSH-POP-NEXT: lw a5, 96(a0)
+; QCI-PUSH-POP-NEXT: lw a4, 100(a0)
+; QCI-PUSH-POP-NEXT: lw a3, 104(a0)
; QCI-PUSH-POP-NEXT: lw a2, 108(a0)
; QCI-PUSH-POP-NEXT: sw a1, 124(a0)
-; QCI-PUSH-POP-NEXT: sw a3, 120(a0)
-; QCI-PUSH-POP-NEXT: sw a5, 116(a0)
-; QCI-PUSH-POP-NEXT: sw t0, 112(a0)
+; QCI-PUSH-POP-NEXT: sw ra, 120(a0)
+; QCI-PUSH-POP-NEXT: sw s11, 116(a0)
+; QCI-PUSH-POP-NEXT: sw s10, 112(a0)
; QCI-PUSH-POP-NEXT: sw a2, 108(a0)
-; QCI-PUSH-POP-NEXT: sw a4, 104(a0)
-; QCI-PUSH-POP-NEXT: sw a6, 100(a0)
-; QCI-PUSH-POP-NEXT: sw a7, 96(a0)
-; QCI-PUSH-POP-NEXT: sw t1, 92(a0)
-; QCI-PUSH-POP-NEXT: sw s1, 88(a0)
-; QCI-PUSH-POP-NEXT: sw s0, 84(a0)
-; QCI-PUSH-POP-NEXT: sw t2, 80(a0)
-; QCI-PUSH-POP-NEXT: sw ra, 76(a0)
-; QCI-PUSH-POP-NEXT: sw s11, 72(a0)
-; QCI-PUSH-POP-NEXT: sw s10, 68(a0)
-; QCI-PUSH-POP-NEXT: sw s9, 64(a0)
-; QCI-PUSH-POP-NEXT: sw s8, 60(a0)
-; QCI-PUSH-POP-NEXT: sw s7, 56(a0)
-; QCI-PUSH-POP-NEXT: sw s6, 52(a0)
-; QCI-PUSH-POP-NEXT: sw s5, 48(a0)
-; QCI-PUSH-POP-NEXT: sw s4, 44(a0)
-; QCI-PUSH-POP-NEXT: sw s3, 40(a0)
-; QCI-PUSH-POP-NEXT: sw s2, 36(a0)
-; QCI-PUSH-POP-NEXT: sw t6, 32(a0)
-; QCI-PUSH-POP-NEXT: sw t5, 28(a0)
-; QCI-PUSH-POP-NEXT: sw t4, 24(a0)
-; QCI-PUSH-POP-NEXT: sw t3, 20(a0)
+; QCI-PUSH-POP-NEXT: sw a3, 104(a0)
+; QCI-PUSH-POP-NEXT: sw a4, 100(a0)
+; QCI-PUSH-POP-NEXT: sw a5, 96(a0)
+; QCI-PUSH-POP-NEXT: sw s9, 92(a0)
+; QCI-PUSH-POP-NEXT: sw s8, 88(a0)
+; QCI-PUSH-POP-NEXT: sw s7, 84(a0)
+; QCI-PUSH-POP-NEXT: sw s6, 80(a0)
+; QCI-PUSH-POP-NEXT: sw s5, 76(a0)
+; QCI-PUSH-POP-NEXT: sw s4, 72(a0)
+; QCI-PUSH-POP-NEXT: sw s3, 68(a0)
+; QCI-PUSH-POP-NEXT: sw s2, 64(a0)
+; QCI-PUSH-POP-NEXT: sw s1, 60(a0)
+; QCI-PUSH-POP-NEXT: sw s0, 56(a0)
+; QCI-PUSH-POP-NEXT: sw t6, 52(a0)
+; QCI-PUSH-POP-NEXT: sw t5, 48(a0)
+; QCI-PUSH-POP-NEXT: sw t4, 44(a0)
+; QCI-PUSH-POP-NEXT: sw t3, 40(a0)
+; QCI-PUSH-POP-NEXT: sw t2, 36(a0)
+; QCI-PUSH-POP-NEXT: sw t1, 32(a0)
+; QCI-PUSH-POP-NEXT: sw t0, 28(a0)
+; QCI-PUSH-POP-NEXT: sw a7, 24(a0)
+; QCI-PUSH-POP-NEXT: sw a6, 20(a0)
; QCI-PUSH-POP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; QCI-PUSH-POP-NEXT: sw a1, 16(a0)
; QCI-PUSH-POP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -1457,60 +1457,60 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 16(a0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw t3, 20(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t4, 24(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t5, 28(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t6, 32(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 36(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 40(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 44(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 48(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 52(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 56(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 60(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 64(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 68(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 72(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw ra, 76(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t2, 80(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s0, 84(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 88(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t1, 92(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t0, 112(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a5, 116(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a3, 120(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a6, 20(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a7, 24(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t0, 28(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t1, 32(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t2, 36(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t3, 40(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t4, 44(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t5, 48(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t6, 52(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s0, 56(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 60(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 64(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 68(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 72(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 76(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 80(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 84(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 88(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 92(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 112(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 116(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw ra, 120(a0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 124(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a7, 96(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a6, 100(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a4, 104(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a5, 96(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a4, 100(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a3, 104(a0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a2, 108(a0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 124(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a3, 120(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a5, 116(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw ra, 120(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 116(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 112(a0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a2, 108(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a4, 104(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a6, 100(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a7, 96(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t1, 92(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 88(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s0, 84(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t2, 80(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw ra, 76(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 72(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 68(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 64(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 60(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 56(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 52(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 48(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 44(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 40(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 36(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t6, 32(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t5, 28(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t4, 24(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t3, 20(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a3, 104(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a4, 100(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a5, 96(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 92(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 88(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 84(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 80(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 76(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 72(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 68(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 64(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 60(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s0, 56(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t6, 52(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t5, 48(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t4, 44(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t3, 40(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t2, 36(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t1, 32(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t0, 28(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a7, 24(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a6, 20(a0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 16(a0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -1585,58 +1585,58 @@ define void @test_spill_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -180(s0) # 4-byte Folded Spill
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 20(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -184(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t4, 24(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t5, 28(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t6, 32(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 36(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 40(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 44(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 48(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s6, 52(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 56(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 60(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 64(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 68(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 72(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw ra, 76(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s1, 80(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t3, 84(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t2, 88(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t1, 92(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t0, 112(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a6, 116(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a7, 24(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t0, 28(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t1, 32(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t2, 36(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t3, 40(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t4, 44(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t5, 48(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t6, 52(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s1, 56(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 60(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 64(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 68(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 72(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s6, 76(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 80(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 84(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 88(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 92(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 112(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw ra, 116(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a4, 120(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 124(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a7, 96(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a6, 96(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a5, 100(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a3, 104(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a2, 108(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 124(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a4, 120(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a6, 116(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw ra, 116(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 112(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a2, 108(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a3, 104(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a5, 100(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a7, 96(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t1, 92(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t2, 88(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t3, 84(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s1, 80(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw ra, 76(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 72(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 68(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 64(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 60(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 56(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s6, 52(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 48(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 44(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 40(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 36(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t6, 32(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t5, 28(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t4, 24(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a6, 96(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 92(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 88(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 84(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 80(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s6, 76(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 72(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 68(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 64(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 60(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s1, 56(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t6, 52(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t5, 48(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t4, 44(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t3, 40(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t2, 36(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t1, 32(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t0, 28(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a7, 24(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -184(s0) # 4-byte Folded Reload
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 20(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -180(s0) # 4-byte Folded Reload
@@ -1727,60 +1727,60 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; QCI-NEXT: lw a1, 16(a0)
; QCI-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw t3, 20(a0)
-; QCI-NEXT: lw t4, 24(a0)
-; QCI-NEXT: lw t5, 28(a0)
-; QCI-NEXT: lw t6, 32(a0)
-; QCI-NEXT: lw s2, 36(a0)
-; QCI-NEXT: lw s3, 40(a0)
-; QCI-NEXT: lw s4, 44(a0)
-; QCI-NEXT: lw s5, 48(a0)
-; QCI-NEXT: lw s6, 52(a0)
-; QCI-NEXT: lw s7, 56(a0)
-; QCI-NEXT: lw s8, 60(a0)
-; QCI-NEXT: lw s9, 64(a0)
-; QCI-NEXT: lw s10, 68(a0)
-; QCI-NEXT: lw s11, 72(a0)
-; QCI-NEXT: lw ra, 76(a0)
-; QCI-NEXT: lw t2, 80(a0)
-; QCI-NEXT: lw s0, 84(a0)
-; QCI-NEXT: lw s1, 88(a0)
-; QCI-NEXT: lw t1, 92(a0)
-; QCI-NEXT: lw t0, 112(a0)
-; QCI-NEXT: lw a5, 116(a0)
-; QCI-NEXT: lw a3, 120(a0)
+; QCI-NEXT: lw a6, 20(a0)
+; QCI-NEXT: lw a7, 24(a0)
+; QCI-NEXT: lw t0, 28(a0)
+; QCI-NEXT: lw t1, 32(a0)
+; QCI-NEXT: lw t2, 36(a0)
+; QCI-NEXT: lw t3, 40(a0)
+; QCI-NEXT: lw t4, 44(a0)
+; QCI-NEXT: lw t5, 48(a0)
+; QCI-NEXT: lw t6, 52(a0)
+; QCI-NEXT: lw s0, 56(a0)
+; QCI-NEXT: lw s1, 60(a0)
+; QCI-NEXT: lw s2, 64(a0)
+; QCI-NEXT: lw s3, 68(a0)
+; QCI-NEXT: lw s4, 72(a0)
+; QCI-NEXT: lw s5, 76(a0)
+; QCI-NEXT: lw s6, 80(a0)
+; QCI-NEXT: lw s7, 84(a0)
+; QCI-NEXT: lw s8, 88(a0)
+; QCI-NEXT: lw s9, 92(a0)
+; QCI-NEXT: lw s10, 112(a0)
+; QCI-NEXT: lw s11, 116(a0)
+; QCI-NEXT: lw ra, 120(a0)
; QCI-NEXT: lw a1, 124(a0)
-; QCI-NEXT: lw a7, 96(a0)
-; QCI-NEXT: lw a6, 100(a0)
-; QCI-NEXT: lw a4, 104(a0)
+; QCI-NEXT: lw a5, 96(a0)
+; QCI-NEXT: lw a4, 100(a0)
+; QCI-NEXT: lw a3, 104(a0)
; QCI-NEXT: lw a2, 108(a0)
; QCI-NEXT: sw a1, 124(a0)
-; QCI-NEXT: sw a3, 120(a0)
-; QCI-NEXT: sw a5, 116(a0)
-; QCI-NEXT: sw t0, 112(a0)
+; QCI-NEXT: sw ra, 120(a0)
+; QCI-NEXT: sw s11, 116(a0)
+; QCI-NEXT: sw s10, 112(a0)
; QCI-NEXT: sw a2, 108(a0)
-; QCI-NEXT: sw a4, 104(a0)
-; QCI-NEXT: sw a6, 100(a0)
-; QCI-NEXT: sw a7, 96(a0)
-; QCI-NEXT: sw t1, 92(a0)
-; QCI-NEXT: sw s1, 88(a0)
-; QCI-NEXT: sw s0, 84(a0)
-; QCI-NEXT: sw t2, 80(a0)
-; QCI-NEXT: sw ra, 76(a0)
-; QCI-NEXT: sw s11, 72(a0)
-; QCI-NEXT: sw s10, 68(a0)
-; QCI-NEXT: sw s9, 64(a0)
-; QCI-NEXT: sw s8, 60(a0)
-; QCI-NEXT: sw s7, 56(a0)
-; QCI-NEXT: sw s6, 52(a0)
-; QCI-NEXT: sw s5, 48(a0)
-; QCI-NEXT: sw s4, 44(a0)
-; QCI-NEXT: sw s3, 40(a0)
-; QCI-NEXT: sw s2, 36(a0)
-; QCI-NEXT: sw t6, 32(a0)
-; QCI-NEXT: sw t5, 28(a0)
-; QCI-NEXT: sw t4, 24(a0)
-; QCI-NEXT: sw t3, 20(a0)
+; QCI-NEXT: sw a3, 104(a0)
+; QCI-NEXT: sw a4, 100(a0)
+; QCI-NEXT: sw a5, 96(a0)
+; QCI-NEXT: sw s9, 92(a0)
+; QCI-NEXT: sw s8, 88(a0)
+; QCI-NEXT: sw s7, 84(a0)
+; QCI-NEXT: sw s6, 80(a0)
+; QCI-NEXT: sw s5, 76(a0)
+; QCI-NEXT: sw s4, 72(a0)
+; QCI-NEXT: sw s3, 68(a0)
+; QCI-NEXT: sw s2, 64(a0)
+; QCI-NEXT: sw s1, 60(a0)
+; QCI-NEXT: sw s0, 56(a0)
+; QCI-NEXT: sw t6, 52(a0)
+; QCI-NEXT: sw t5, 48(a0)
+; QCI-NEXT: sw t4, 44(a0)
+; QCI-NEXT: sw t3, 40(a0)
+; QCI-NEXT: sw t2, 36(a0)
+; QCI-NEXT: sw t1, 32(a0)
+; QCI-NEXT: sw t0, 28(a0)
+; QCI-NEXT: sw a7, 24(a0)
+; QCI-NEXT: sw a6, 20(a0)
; QCI-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; QCI-NEXT: sw a1, 16(a0)
; QCI-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
@@ -1877,58 +1877,58 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-FP-NEXT: sw a1, -160(s0) # 4-byte Folded Spill
; QCI-FP-NEXT: lw a1, 20(a0)
; QCI-FP-NEXT: sw a1, -164(s0) # 4-byte Folded Spill
-; QCI-FP-NEXT: lw t4, 24(a0)
-; QCI-FP-NEXT: lw t5, 28(a0)
-; QCI-FP-NEXT: lw t6, 32(a0)
-; QCI-FP-NEXT: lw s2, 36(a0)
-; QCI-FP-NEXT: lw s3, 40(a0)
-; QCI-FP-NEXT: lw s4, 44(a0)
-; QCI-FP-NEXT: lw s5, 48(a0)
-; QCI-FP-NEXT: lw s6, 52(a0)
-; QCI-FP-NEXT: lw s7, 56(a0)
-; QCI-FP-NEXT: lw s8, 60(a0)
-; QCI-FP-NEXT: lw s9, 64(a0)
-; QCI-FP-NEXT: lw s10, 68(a0)
-; QCI-FP-NEXT: lw s11, 72(a0)
-; QCI-FP-NEXT: lw ra, 76(a0)
-; QCI-FP-NEXT: lw s1, 80(a0)
-; QCI-FP-NEXT: lw t3, 84(a0)
-; QCI-FP-NEXT: lw t2, 88(a0)
-; QCI-FP-NEXT: lw t1, 92(a0)
-; QCI-FP-NEXT: lw t0, 112(a0)
-; QCI-FP-NEXT: lw a6, 116(a0)
+; QCI-FP-NEXT: lw a7, 24(a0)
+; QCI-FP-NEXT: lw t0, 28(a0)
+; QCI-FP-NEXT: lw t1, 32(a0)
+; QCI-FP-NEXT: lw t2, 36(a0)
+; QCI-FP-NEXT: lw t3, 40(a0)
+; QCI-FP-NEXT: lw t4, 44(a0)
+; QCI-FP-NEXT: lw t5, 48(a0)
+; QCI-FP-NEXT: lw t6, 52(a0)
+; QCI-FP-NEXT: lw s1, 56(a0)
+; QCI-FP-NEXT: lw s2, 60(a0)
+; QCI-FP-NEXT: lw s3, 64(a0)
+; QCI-FP-NEXT: lw s4, 68(a0)
+; QCI-FP-NEXT: lw s5, 72(a0)
+; QCI-FP-NEXT: lw s6, 76(a0)
+; QCI-FP-NEXT: lw s7, 80(a0)
+; QCI-FP-NEXT: lw s8, 84(a0)
+; QCI-FP-NEXT: lw s9, 88(a0)
+; QCI-FP-NEXT: lw s10, 92(a0)
+; QCI-FP-NEXT: lw s11, 112(a0)
+; QCI-FP-NEXT: lw ra, 116(a0)
; QCI-FP-NEXT: lw a4, 120(a0)
; QCI-FP-NEXT: lw a1, 124(a0)
-; QCI-FP-NEXT: lw a7, 96(a0)
+; QCI-FP-NEXT: lw a6, 96(a0)
; QCI-FP-NEXT: lw a5, 100(a0)
; QCI-FP-NEXT: lw a3, 104(a0)
; QCI-FP-NEXT: lw a2, 108(a0)
; QCI-FP-NEXT: sw a1, 124(a0)
; QCI-FP-NEXT: sw a4, 120(a0)
-; QCI-FP-NEXT: sw a6, 116(a0)
-; QCI-FP-NEXT: sw t0, 112(a0)
+; QCI-FP-NEXT: sw ra, 116(a0)
+; QCI-FP-NEXT: sw s11, 112(a0)
; QCI-FP-NEXT: sw a2, 108(a0)
; QCI-FP-NEXT: sw a3, 104(a0)
; QCI-FP-NEXT: sw a5, 100(a0)
-; QCI-FP-NEXT: sw a7, 96(a0)
-; QCI-FP-NEXT: sw t1, 92(a0)
-; QCI-FP-NEXT: sw t2, 88(a0)
-; QCI-FP-NEXT: sw t3, 84(a0)
-; QCI-FP-NEXT: sw s1, 80(a0)
-; QCI-FP-NEXT: sw ra, 76(a0)
-; QCI-FP-NEXT: sw s11, 72(a0)
-; QCI-FP-NEXT: sw s10, 68(a0)
-; QCI-FP-NEXT: sw s9, 64(a0)
-; QCI-FP-NEXT: sw s8, 60(a0)
-; QCI-FP-NEXT: sw s7, 56(a0)
-; QCI-FP-NEXT: sw s6, 52(a0)
-; QCI-FP-NEXT: sw s5, 48(a0)
-; QCI-FP-NEXT: sw s4, 44(a0)
-; QCI-FP-NEXT: sw s3, 40(a0)
-; QCI-FP-NEXT: sw s2, 36(a0)
-; QCI-FP-NEXT: sw t6, 32(a0)
-; QCI-FP-NEXT: sw t5, 28(a0)
-; QCI-FP-NEXT: sw t4, 24(a0)
+; QCI-FP-NEXT: sw a6, 96(a0)
+; QCI-FP-NEXT: sw s10, 92(a0)
+; QCI-FP-NEXT: sw s9, 88(a0)
+; QCI-FP-NEXT: sw s8, 84(a0)
+; QCI-FP-NEXT: sw s7, 80(a0)
+; QCI-FP-NEXT: sw s6, 76(a0)
+; QCI-FP-NEXT: sw s5, 72(a0)
+; QCI-FP-NEXT: sw s4, 68(a0)
+; QCI-FP-NEXT: sw s3, 64(a0)
+; QCI-FP-NEXT: sw s2, 60(a0)
+; QCI-FP-NEXT: sw s1, 56(a0)
+; QCI-FP-NEXT: sw t6, 52(a0)
+; QCI-FP-NEXT: sw t5, 48(a0)
+; QCI-FP-NEXT: sw t4, 44(a0)
+; QCI-FP-NEXT: sw t3, 40(a0)
+; QCI-FP-NEXT: sw t2, 36(a0)
+; QCI-FP-NEXT: sw t1, 32(a0)
+; QCI-FP-NEXT: sw t0, 28(a0)
+; QCI-FP-NEXT: sw a7, 24(a0)
; QCI-FP-NEXT: lw a1, -164(s0) # 4-byte Folded Reload
; QCI-FP-NEXT: sw a1, 20(a0)
; QCI-FP-NEXT: lw a1, -160(s0) # 4-byte Folded Reload
@@ -2014,60 +2014,60 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-PUSH-POP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; QCI-PUSH-POP-NEXT: lw a1, 16(a0)
; QCI-PUSH-POP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw t3, 20(a0)
-; QCI-PUSH-POP-NEXT: lw t4, 24(a0)
-; QCI-PUSH-POP-NEXT: lw t5, 28(a0)
-; QCI-PUSH-POP-NEXT: lw t6, 32(a0)
-; QCI-PUSH-POP-NEXT: lw s2, 36(a0)
-; QCI-PUSH-POP-NEXT: lw s3, 40(a0)
-; QCI-PUSH-POP-NEXT: lw s4, 44(a0)
-; QCI-PUSH-POP-NEXT: lw s5, 48(a0)
-; QCI-PUSH-POP-NEXT: lw s6, 52(a0)
-; QCI-PUSH-POP-NEXT: lw s7, 56(a0)
-; QCI-PUSH-POP-NEXT: lw s8, 60(a0)
-; QCI-PUSH-POP-NEXT: lw s9, 64(a0)
-; QCI-PUSH-POP-NEXT: lw s10, 68(a0)
-; QCI-PUSH-POP-NEXT: lw s11, 72(a0)
-; QCI-PUSH-POP-NEXT: lw ra, 76(a0)
-; QCI-PUSH-POP-NEXT: lw t2, 80(a0)
-; QCI-PUSH-POP-NEXT: lw s0, 84(a0)
-; QCI-PUSH-POP-NEXT: lw s1, 88(a0)
-; QCI-PUSH-POP-NEXT: lw t1, 92(a0)
-; QCI-PUSH-POP-NEXT: lw t0, 112(a0)
-; QCI-PUSH-POP-NEXT: lw a5, 116(a0)
-; QCI-PUSH-POP-NEXT: lw a3, 120(a0)
+; QCI-PUSH-POP-NEXT: lw a6, 20(a0)
+; QCI-PUSH-POP-NEXT: lw a7, 24(a0)
+; QCI-PUSH-POP-NEXT: lw t0, 28(a0)
+; QCI-PUSH-POP-NEXT: lw t1, 32(a0)
+; QCI-PUSH-POP-NEXT: lw t2, 36(a0)
+; QCI-PUSH-POP-NEXT: lw t3, 40(a0)
+; QCI-PUSH-POP-NEXT: lw t4, 44(a0)
+; QCI-PUSH-POP-NEXT: lw t5, 48(a0)
+; QCI-PUSH-POP-NEXT: lw t6, 52(a0)
+; QCI-PUSH-POP-NEXT: lw s0, 56(a0)
+; QCI-PUSH-POP-NEXT: lw s1, 60(a0)
+; QCI-PUSH-POP-NEXT: lw s2, 64(a0)
+; QCI-PUSH-POP-NEXT: lw s3, 68(a0)
+; QCI-PUSH-POP-NEXT: lw s4, 72(a0)
+; QCI-PUSH-POP-NEXT: lw s5, 76(a0)
+; QCI-PUSH-POP-NEXT: lw s6, 80(a0)
+; QCI-PUSH-POP-NEXT: lw s7, 84(a0)
+; QCI-PUSH-POP-NEXT: lw s8, 88(a0)
+; QCI-PUSH-POP-NEXT: lw s9, 92(a0)
+; QCI-PUSH-POP-NEXT: lw s10, 112(a0)
+; QCI-PUSH-POP-NEXT: lw s11, 116(a0)
+; QCI-PUSH-POP-NEXT: lw ra, 120(a0)
; QCI-PUSH-POP-NEXT: lw a1, 124(a0)
-; QCI-PUSH-POP-NEXT: lw a7, 96(a0)
-; QCI-PUSH-POP-NEXT: lw a6, 100(a0)
-; QCI-PUSH-POP-NEXT: lw a4, 104(a0)
+; QCI-PUSH-POP-NEXT: lw a5, 96(a0)
+; QCI-PUSH-POP-NEXT: lw a4, 100(a0)
+; QCI-PUSH-POP-NEXT: lw a3, 104(a0)
; QCI-PUSH-POP-NEXT: lw a2, 108(a0)
; QCI-PUSH-POP-NEXT: sw a1, 124(a0)
-; QCI-PUSH-POP-NEXT: sw a3, 120(a0)
-; QCI-PUSH-POP-NEXT: sw a5, 116(a0)
-; QCI-PUSH-POP-NEXT: sw t0, 112(a0)
+; QCI-PUSH-POP-NEXT: sw ra, 120(a0)
+; QCI-PUSH-POP-NEXT: sw s11, 116(a0)
+; QCI-PUSH-POP-NEXT: sw s10, 112(a0)
; QCI-PUSH-POP-NEXT: sw a2, 108(a0)
-; QCI-PUSH-POP-NEXT: sw a4, 104(a0)
-; QCI-PUSH-POP-NEXT: sw a6, 100(a0)
-; QCI-PUSH-POP-NEXT: sw a7, 96(a0)
-; QCI-PUSH-POP-NEXT: sw t1, 92(a0)
-; QCI-PUSH-POP-NEXT: sw s1, 88(a0)
-; QCI-PUSH-POP-NEXT: sw s0, 84(a0)
-; QCI-PUSH-POP-NEXT: sw t2, 80(a0)
-; QCI-PUSH-POP-NEXT: sw ra, 76(a0)
-; QCI-PUSH-POP-NEXT: sw s11, 72(a0)
-; QCI-PUSH-POP-NEXT: sw s10, 68(a0)
-; QCI-PUSH-POP-NEXT: sw s9, 64(a0)
-; QCI-PUSH-POP-NEXT: sw s8, 60(a0)
-; QCI-PUSH-POP-NEXT: sw s7, 56(a0)
-; QCI-PUSH-POP-NEXT: sw s6, 52(a0)
-; QCI-PUSH-POP-NEXT: sw s5, 48(a0)
-; QCI-PUSH-POP-NEXT: sw s4, 44(a0)
-; QCI-PUSH-POP-NEXT: sw s3, 40(a0)
-; QCI-PUSH-POP-NEXT: sw s2, 36(a0)
-; QCI-PUSH-POP-NEXT: sw t6, 32(a0)
-; QCI-PUSH-POP-NEXT: sw t5, 28(a0)
-; QCI-PUSH-POP-NEXT: sw t4, 24(a0)
-; QCI-PUSH-POP-NEXT: sw t3, 20(a0)
+; QCI-PUSH-POP-NEXT: sw a3, 104(a0)
+; QCI-PUSH-POP-NEXT: sw a4, 100(a0)
+; QCI-PUSH-POP-NEXT: sw a5, 96(a0)
+; QCI-PUSH-POP-NEXT: sw s9, 92(a0)
+; QCI-PUSH-POP-NEXT: sw s8, 88(a0)
+; QCI-PUSH-POP-NEXT: sw s7, 84(a0)
+; QCI-PUSH-POP-NEXT: sw s6, 80(a0)
+; QCI-PUSH-POP-NEXT: sw s5, 76(a0)
+; QCI-PUSH-POP-NEXT: sw s4, 72(a0)
+; QCI-PUSH-POP-NEXT: sw s3, 68(a0)
+; QCI-PUSH-POP-NEXT: sw s2, 64(a0)
+; QCI-PUSH-POP-NEXT: sw s1, 60(a0)
+; QCI-PUSH-POP-NEXT: sw s0, 56(a0)
+; QCI-PUSH-POP-NEXT: sw t6, 52(a0)
+; QCI-PUSH-POP-NEXT: sw t5, 48(a0)
+; QCI-PUSH-POP-NEXT: sw t4, 44(a0)
+; QCI-PUSH-POP-NEXT: sw t3, 40(a0)
+; QCI-PUSH-POP-NEXT: sw t2, 36(a0)
+; QCI-PUSH-POP-NEXT: sw t1, 32(a0)
+; QCI-PUSH-POP-NEXT: sw t0, 28(a0)
+; QCI-PUSH-POP-NEXT: sw a7, 24(a0)
+; QCI-PUSH-POP-NEXT: sw a6, 20(a0)
; QCI-PUSH-POP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; QCI-PUSH-POP-NEXT: sw a1, 16(a0)
; QCI-PUSH-POP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -2139,60 +2139,60 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 16(a0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw t3, 20(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t4, 24(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t5, 28(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t6, 32(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 36(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 40(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 44(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 48(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 52(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 56(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 60(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 64(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 68(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 72(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw ra, 76(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t2, 80(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s0, 84(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 88(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t1, 92(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw t0, 112(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a5, 116(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a3, 120(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a6, 20(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a7, 24(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t0, 28(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t1, 32(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t2, 36(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t3, 40(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t4, 44(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t5, 48(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw t6, 52(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s0, 56(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 60(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 64(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 68(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 72(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 76(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 80(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 84(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 88(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 92(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 112(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 116(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw ra, 120(a0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 124(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a7, 96(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a6, 100(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw a4, 104(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a5, 96(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a4, 100(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw a3, 104(a0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a2, 108(a0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 124(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a3, 120(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a5, 116(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw ra, 120(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 116(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 112(a0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a2, 108(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a4, 104(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a6, 100(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw a7, 96(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t1, 92(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 88(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s0, 84(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t2, 80(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw ra, 76(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 72(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 68(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 64(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 60(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 56(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 52(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 48(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 44(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 40(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 36(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t6, 32(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t5, 28(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t4, 24(a0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw t3, 20(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a3, 104(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a4, 100(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a5, 96(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 92(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 88(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 84(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 80(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 76(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 72(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 68(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 64(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 60(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s0, 56(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t6, 52(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t5, 48(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t4, 44(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t3, 40(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t2, 36(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t1, 32(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw t0, 28(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a7, 24(a0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw a6, 20(a0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; QCI-QCCMP-PUSH-POP-NEXT: sw a1, 16(a0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -2267,58 +2267,58 @@ define void @test_spill_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -180(s0) # 4-byte Folded Spill
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 20(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, -184(s0) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t4, 24(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t5, 28(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t6, 32(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 36(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 40(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 44(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 48(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s6, 52(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 56(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 60(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 64(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 68(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 72(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw ra, 76(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s1, 80(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t3, 84(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t2, 88(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t1, 92(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t0, 112(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a6, 116(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a7, 24(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t0, 28(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t1, 32(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t2, 36(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t3, 40(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t4, 44(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t5, 48(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw t6, 52(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s1, 56(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s2, 60(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s3, 64(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s4, 68(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s5, 72(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s6, 76(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s7, 80(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s8, 84(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s9, 88(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s10, 92(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw s11, 112(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw ra, 116(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a4, 120(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, 124(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a7, 96(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a6, 96(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a5, 100(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a3, 104(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a2, 108(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 124(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a4, 120(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a6, 116(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t0, 112(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw ra, 116(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 112(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a2, 108(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a3, 104(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a5, 100(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a7, 96(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t1, 92(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t2, 88(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t3, 84(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s1, 80(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw ra, 76(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s11, 72(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 68(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 64(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 60(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 56(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s6, 52(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 48(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 44(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 40(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 36(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t6, 32(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t5, 28(a0)
-; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t4, 24(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a6, 96(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s10, 92(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s9, 88(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s8, 84(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s7, 80(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s6, 76(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s5, 72(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s4, 68(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s3, 64(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s2, 60(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw s1, 56(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t6, 52(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t5, 48(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t4, 44(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t3, 40(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t2, 36(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t1, 32(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw t0, 28(a0)
+; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a7, 24(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -184(s0) # 4-byte Folded Reload
; QCI-QCCMP-PUSH-POP-FP-NEXT: sw a1, 20(a0)
; QCI-QCCMP-PUSH-POP-FP-NEXT: lw a1, -180(s0) # 4-byte Folded Reload
@@ -2441,17 +2441,17 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; QCI-NEXT: lw a0, 80(s0)
; QCI-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw s1, 84(s0)
-; QCI-NEXT: lw s2, 88(s0)
-; QCI-NEXT: lw s3, 92(s0)
-; QCI-NEXT: lw s4, 96(s0)
-; QCI-NEXT: lw s5, 100(s0)
-; QCI-NEXT: lw s6, 104(s0)
-; QCI-NEXT: lw s7, 108(s0)
-; QCI-NEXT: lw s8, 112(s0)
-; QCI-NEXT: lw s9, 116(s0)
-; QCI-NEXT: lw s10, 120(s0)
-; QCI-NEXT: lw s11, 124(s0)
+; QCI-NEXT: lw s11, 84(s0)
+; QCI-NEXT: lw s1, 88(s0)
+; QCI-NEXT: lw s2, 92(s0)
+; QCI-NEXT: lw s3, 96(s0)
+; QCI-NEXT: lw s4, 100(s0)
+; QCI-NEXT: lw s5, 104(s0)
+; QCI-NEXT: lw s6, 108(s0)
+; QCI-NEXT: lw s7, 112(s0)
+; QCI-NEXT: lw s8, 116(s0)
+; QCI-NEXT: lw s9, 120(s0)
+; QCI-NEXT: lw s10, 124(s0)
; QCI-NEXT: li a0, 4
; QCI-NEXT: li a2, 1
; QCI-NEXT: li a4, 2
@@ -2464,17 +2464,17 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-NEXT: li a7, 0
; QCI-NEXT: call function_with_one_stack_arg
; QCI-NEXT: call use_i64
-; QCI-NEXT: sw s11, 124(s0)
-; QCI-NEXT: sw s10, 120(s0)
-; QCI-NEXT: sw s9, 116(s0)
-; QCI-NEXT: sw s8, 112(s0)
-; QCI-NEXT: sw s7, 108(s0)
-; QCI-NEXT: sw s6, 104(s0)
-; QCI-NEXT: sw s5, 100(s0)
-; QCI-NEXT: sw s4, 96(s0)
-; QCI-NEXT: sw s3, 92(s0)
-; QCI-NEXT: sw s2, 88(s0)
-; QCI-NEXT: sw s1, 84(s0)
+; QCI-NEXT: sw s10, 124(s0)
+; QCI-NEXT: sw s9, 120(s0)
+; QCI-NEXT: sw s8, 116(s0)
+; QCI-NEXT: sw s7, 112(s0)
+; QCI-NEXT: sw s6, 108(s0)
+; QCI-NEXT: sw s5, 104(s0)
+; QCI-NEXT: sw s4, 100(s0)
+; QCI-NEXT: sw s3, 96(s0)
+; QCI-NEXT: sw s2, 92(s0)
+; QCI-NEXT: sw s1, 88(s0)
+; QCI-NEXT: sw s11, 84(s0)
; QCI-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
; QCI-NEXT: sw a0, 80(s0)
; QCI-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
@@ -2818,17 +2818,17 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; QCI-PUSH-POP-NEXT: lw a0, 80(s0)
; QCI-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw s1, 84(s0)
-; QCI-PUSH-POP-NEXT: lw s2, 88(s0)
-; QCI-PUSH-POP-NEXT: lw s3, 92(s0)
-; QCI-PUSH-POP-NEXT: lw s4, 96(s0)
-; QCI-PUSH-POP-NEXT: lw s5, 100(s0)
-; QCI-PUSH-POP-NEXT: lw s6, 104(s0)
-; QCI-PUSH-POP-NEXT: lw s7, 108(s0)
-; QCI-PUSH-POP-NEXT: lw s8, 112(s0)
-; QCI-PUSH-POP-NEXT: lw s9, 116(s0)
-; QCI-PUSH-POP-NEXT: lw s10, 120(s0)
-; QCI-PUSH-POP-NEXT: lw s11, 124(s0)
+; QCI-PUSH-POP-NEXT: lw s11, 84(s0)
+; QCI-PUSH-POP-NEXT: lw s1, 88(s0)
+; QCI-PUSH-POP-NEXT: lw s2, 92(s0)
+; QCI-PUSH-POP-NEXT: lw s3, 96(s0)
+; QCI-PUSH-POP-NEXT: lw s4, 100(s0)
+; QCI-PUSH-POP-NEXT: lw s5, 104(s0)
+; QCI-PUSH-POP-NEXT: lw s6, 108(s0)
+; QCI-PUSH-POP-NEXT: lw s7, 112(s0)
+; QCI-PUSH-POP-NEXT: lw s8, 116(s0)
+; QCI-PUSH-POP-NEXT: lw s9, 120(s0)
+; QCI-PUSH-POP-NEXT: lw s10, 124(s0)
; QCI-PUSH-POP-NEXT: li a0, 4
; QCI-PUSH-POP-NEXT: li a2, 1
; QCI-PUSH-POP-NEXT: li a4, 2
@@ -2841,17 +2841,17 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-PUSH-POP-NEXT: li a7, 0
; QCI-PUSH-POP-NEXT: call function_with_one_stack_arg
; QCI-PUSH-POP-NEXT: call use_i64
-; QCI-PUSH-POP-NEXT: sw s11, 124(s0)
-; QCI-PUSH-POP-NEXT: sw s10, 120(s0)
-; QCI-PUSH-POP-NEXT: sw s9, 116(s0)
-; QCI-PUSH-POP-NEXT: sw s8, 112(s0)
-; QCI-PUSH-POP-NEXT: sw s7, 108(s0)
-; QCI-PUSH-POP-NEXT: sw s6, 104(s0)
-; QCI-PUSH-POP-NEXT: sw s5, 100(s0)
-; QCI-PUSH-POP-NEXT: sw s4, 96(s0)
-; QCI-PUSH-POP-NEXT: sw s3, 92(s0)
-; QCI-PUSH-POP-NEXT: sw s2, 88(s0)
-; QCI-PUSH-POP-NEXT: sw s1, 84(s0)
+; QCI-PUSH-POP-NEXT: sw s10, 124(s0)
+; QCI-PUSH-POP-NEXT: sw s9, 120(s0)
+; QCI-PUSH-POP-NEXT: sw s8, 116(s0)
+; QCI-PUSH-POP-NEXT: sw s7, 112(s0)
+; QCI-PUSH-POP-NEXT: sw s6, 108(s0)
+; QCI-PUSH-POP-NEXT: sw s5, 104(s0)
+; QCI-PUSH-POP-NEXT: sw s4, 100(s0)
+; QCI-PUSH-POP-NEXT: sw s3, 96(s0)
+; QCI-PUSH-POP-NEXT: sw s2, 92(s0)
+; QCI-PUSH-POP-NEXT: sw s1, 88(s0)
+; QCI-PUSH-POP-NEXT: sw s11, 84(s0)
; QCI-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; QCI-PUSH-POP-NEXT: sw a0, 80(s0)
; QCI-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
@@ -2991,17 +2991,17 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 80(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 84(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 88(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 92(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 96(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 100(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 104(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 108(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 112(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 116(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 120(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 124(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 84(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 88(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 92(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 96(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 100(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 104(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 108(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 112(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 116(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 120(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 124(s0)
; QCI-QCCMP-PUSH-POP-NEXT: li a0, 4
; QCI-QCCMP-PUSH-POP-NEXT: li a2, 1
; QCI-QCCMP-PUSH-POP-NEXT: li a4, 2
@@ -3014,17 +3014,17 @@ define void @test_spill_call_nest() "interrupt"="qci-nest" {
; QCI-QCCMP-PUSH-POP-NEXT: li a7, 0
; QCI-QCCMP-PUSH-POP-NEXT: call function_with_one_stack_arg
; QCI-QCCMP-PUSH-POP-NEXT: call use_i64
-; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 124(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 120(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 116(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 112(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 108(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 104(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 100(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 96(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 92(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 88(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 84(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 124(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 120(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 116(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 112(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 108(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 104(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 100(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 96(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 92(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 88(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 84(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 80(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
@@ -3357,17 +3357,17 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-NEXT: sw a0, 20(sp) # 4-byte Folded Spill
; QCI-NEXT: lw a0, 80(s0)
; QCI-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
-; QCI-NEXT: lw s1, 84(s0)
-; QCI-NEXT: lw s2, 88(s0)
-; QCI-NEXT: lw s3, 92(s0)
-; QCI-NEXT: lw s4, 96(s0)
-; QCI-NEXT: lw s5, 100(s0)
-; QCI-NEXT: lw s6, 104(s0)
-; QCI-NEXT: lw s7, 108(s0)
-; QCI-NEXT: lw s8, 112(s0)
-; QCI-NEXT: lw s9, 116(s0)
-; QCI-NEXT: lw s10, 120(s0)
-; QCI-NEXT: lw s11, 124(s0)
+; QCI-NEXT: lw s11, 84(s0)
+; QCI-NEXT: lw s1, 88(s0)
+; QCI-NEXT: lw s2, 92(s0)
+; QCI-NEXT: lw s3, 96(s0)
+; QCI-NEXT: lw s4, 100(s0)
+; QCI-NEXT: lw s5, 104(s0)
+; QCI-NEXT: lw s6, 108(s0)
+; QCI-NEXT: lw s7, 112(s0)
+; QCI-NEXT: lw s8, 116(s0)
+; QCI-NEXT: lw s9, 120(s0)
+; QCI-NEXT: lw s10, 124(s0)
; QCI-NEXT: li a0, 4
; QCI-NEXT: li a2, 1
; QCI-NEXT: li a4, 2
@@ -3380,17 +3380,17 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-NEXT: li a7, 0
; QCI-NEXT: call function_with_one_stack_arg
; QCI-NEXT: call use_i64
-; QCI-NEXT: sw s11, 124(s0)
-; QCI-NEXT: sw s10, 120(s0)
-; QCI-NEXT: sw s9, 116(s0)
-; QCI-NEXT: sw s8, 112(s0)
-; QCI-NEXT: sw s7, 108(s0)
-; QCI-NEXT: sw s6, 104(s0)
-; QCI-NEXT: sw s5, 100(s0)
-; QCI-NEXT: sw s4, 96(s0)
-; QCI-NEXT: sw s3, 92(s0)
-; QCI-NEXT: sw s2, 88(s0)
-; QCI-NEXT: sw s1, 84(s0)
+; QCI-NEXT: sw s10, 124(s0)
+; QCI-NEXT: sw s9, 120(s0)
+; QCI-NEXT: sw s8, 116(s0)
+; QCI-NEXT: sw s7, 112(s0)
+; QCI-NEXT: sw s6, 108(s0)
+; QCI-NEXT: sw s5, 104(s0)
+; QCI-NEXT: sw s4, 100(s0)
+; QCI-NEXT: sw s3, 96(s0)
+; QCI-NEXT: sw s2, 92(s0)
+; QCI-NEXT: sw s1, 88(s0)
+; QCI-NEXT: sw s11, 84(s0)
; QCI-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
; QCI-NEXT: sw a0, 80(s0)
; QCI-NEXT: lw a0, 20(sp) # 4-byte Folded Reload
@@ -3734,17 +3734,17 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; QCI-PUSH-POP-NEXT: lw a0, 80(s0)
; QCI-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-PUSH-POP-NEXT: lw s1, 84(s0)
-; QCI-PUSH-POP-NEXT: lw s2, 88(s0)
-; QCI-PUSH-POP-NEXT: lw s3, 92(s0)
-; QCI-PUSH-POP-NEXT: lw s4, 96(s0)
-; QCI-PUSH-POP-NEXT: lw s5, 100(s0)
-; QCI-PUSH-POP-NEXT: lw s6, 104(s0)
-; QCI-PUSH-POP-NEXT: lw s7, 108(s0)
-; QCI-PUSH-POP-NEXT: lw s8, 112(s0)
-; QCI-PUSH-POP-NEXT: lw s9, 116(s0)
-; QCI-PUSH-POP-NEXT: lw s10, 120(s0)
-; QCI-PUSH-POP-NEXT: lw s11, 124(s0)
+; QCI-PUSH-POP-NEXT: lw s11, 84(s0)
+; QCI-PUSH-POP-NEXT: lw s1, 88(s0)
+; QCI-PUSH-POP-NEXT: lw s2, 92(s0)
+; QCI-PUSH-POP-NEXT: lw s3, 96(s0)
+; QCI-PUSH-POP-NEXT: lw s4, 100(s0)
+; QCI-PUSH-POP-NEXT: lw s5, 104(s0)
+; QCI-PUSH-POP-NEXT: lw s6, 108(s0)
+; QCI-PUSH-POP-NEXT: lw s7, 112(s0)
+; QCI-PUSH-POP-NEXT: lw s8, 116(s0)
+; QCI-PUSH-POP-NEXT: lw s9, 120(s0)
+; QCI-PUSH-POP-NEXT: lw s10, 124(s0)
; QCI-PUSH-POP-NEXT: li a0, 4
; QCI-PUSH-POP-NEXT: li a2, 1
; QCI-PUSH-POP-NEXT: li a4, 2
@@ -3757,17 +3757,17 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-PUSH-POP-NEXT: li a7, 0
; QCI-PUSH-POP-NEXT: call function_with_one_stack_arg
; QCI-PUSH-POP-NEXT: call use_i64
-; QCI-PUSH-POP-NEXT: sw s11, 124(s0)
-; QCI-PUSH-POP-NEXT: sw s10, 120(s0)
-; QCI-PUSH-POP-NEXT: sw s9, 116(s0)
-; QCI-PUSH-POP-NEXT: sw s8, 112(s0)
-; QCI-PUSH-POP-NEXT: sw s7, 108(s0)
-; QCI-PUSH-POP-NEXT: sw s6, 104(s0)
-; QCI-PUSH-POP-NEXT: sw s5, 100(s0)
-; QCI-PUSH-POP-NEXT: sw s4, 96(s0)
-; QCI-PUSH-POP-NEXT: sw s3, 92(s0)
-; QCI-PUSH-POP-NEXT: sw s2, 88(s0)
-; QCI-PUSH-POP-NEXT: sw s1, 84(s0)
+; QCI-PUSH-POP-NEXT: sw s10, 124(s0)
+; QCI-PUSH-POP-NEXT: sw s9, 120(s0)
+; QCI-PUSH-POP-NEXT: sw s8, 116(s0)
+; QCI-PUSH-POP-NEXT: sw s7, 112(s0)
+; QCI-PUSH-POP-NEXT: sw s6, 108(s0)
+; QCI-PUSH-POP-NEXT: sw s5, 104(s0)
+; QCI-PUSH-POP-NEXT: sw s4, 100(s0)
+; QCI-PUSH-POP-NEXT: sw s3, 96(s0)
+; QCI-PUSH-POP-NEXT: sw s2, 92(s0)
+; QCI-PUSH-POP-NEXT: sw s1, 88(s0)
+; QCI-PUSH-POP-NEXT: sw s11, 84(s0)
; QCI-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; QCI-PUSH-POP-NEXT: sw a0, 80(s0)
; QCI-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
@@ -3907,17 +3907,17 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 80(s0)
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 84(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 88(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 92(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 96(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 100(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 104(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 108(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 112(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 116(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 120(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 124(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s11, 84(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s1, 88(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s2, 92(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s3, 96(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s4, 100(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s5, 104(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s6, 108(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s7, 112(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s8, 116(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s9, 120(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: lw s10, 124(s0)
; QCI-QCCMP-PUSH-POP-NEXT: li a0, 4
; QCI-QCCMP-PUSH-POP-NEXT: li a2, 1
; QCI-QCCMP-PUSH-POP-NEXT: li a4, 2
@@ -3930,17 +3930,17 @@ define void @test_spill_call_nonest() "interrupt"="qci-nonest" {
; QCI-QCCMP-PUSH-POP-NEXT: li a7, 0
; QCI-QCCMP-PUSH-POP-NEXT: call function_with_one_stack_arg
; QCI-QCCMP-PUSH-POP-NEXT: call use_i64
-; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 124(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 120(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 116(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 112(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 108(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 104(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 100(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 96(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 92(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 88(s0)
-; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 84(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s10, 124(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s9, 120(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s8, 116(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s7, 112(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s6, 108(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s5, 104(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s4, 100(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s3, 96(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s2, 92(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s1, 88(s0)
+; QCI-QCCMP-PUSH-POP-NEXT: sw s11, 84(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; QCI-QCCMP-PUSH-POP-NEXT: sw a0, 80(s0)
; QCI-QCCMP-PUSH-POP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index e04dc58b25d46..42d43d61031b4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -1519,52 +1519,52 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) {
;
; RVA22U64-LABEL: buildvec_v16i8_loads_contigous:
; RVA22U64: # %bb.0:
-; RVA22U64-NEXT: lbu a6, 0(a0)
+; RVA22U64-NEXT: lbu a1, 0(a0)
; RVA22U64-NEXT: lbu a2, 1(a0)
; RVA22U64-NEXT: lbu a3, 2(a0)
; RVA22U64-NEXT: lbu a4, 3(a0)
; RVA22U64-NEXT: lbu a5, 4(a0)
-; RVA22U64-NEXT: lbu a1, 5(a0)
+; RVA22U64-NEXT: lbu a6, 5(a0)
; RVA22U64-NEXT: lbu a7, 6(a0)
; RVA22U64-NEXT: lbu t0, 7(a0)
; RVA22U64-NEXT: slli a2, a2, 8
; RVA22U64-NEXT: slli a3, a3, 16
; RVA22U64-NEXT: slli a4, a4, 24
; RVA22U64-NEXT: slli a5, a5, 32
-; RVA22U64-NEXT: slli a1, a1, 40
-; RVA22U64-NEXT: or a6, a6, a2
-; RVA22U64-NEXT: or t2, a4, a3
-; RVA22U64-NEXT: or t1, a1, a5
+; RVA22U64-NEXT: slli a6, a6, 40
+; RVA22U64-NEXT: or a1, a1, a2
+; RVA22U64-NEXT: or a3, a3, a4
+; RVA22U64-NEXT: or a2, a6, a5
; RVA22U64-NEXT: lbu a4, 8(a0)
; RVA22U64-NEXT: lbu a5, 9(a0)
-; RVA22U64-NEXT: lbu a2, 10(a0)
-; RVA22U64-NEXT: lbu a1, 11(a0)
+; RVA22U64-NEXT: lbu a6, 10(a0)
+; RVA22U64-NEXT: lbu t1, 11(a0)
; RVA22U64-NEXT: slli a7, a7, 48
; RVA22U64-NEXT: slli t0, t0, 56
; RVA22U64-NEXT: slli a5, a5, 8
-; RVA22U64-NEXT: slli a2, a2, 16
-; RVA22U64-NEXT: slli a1, a1, 24
+; RVA22U64-NEXT: slli a6, a6, 16
+; RVA22U64-NEXT: slli t1, t1, 24
; RVA22U64-NEXT: or a7, t0, a7
; RVA22U64-NEXT: or a4, a4, a5
-; RVA22U64-NEXT: or a1, a1, a2
-; RVA22U64-NEXT: lbu a2, 12(a0)
-; RVA22U64-NEXT: lbu a5, 13(a0)
-; RVA22U64-NEXT: lbu a3, 14(a0)
+; RVA22U64-NEXT: or a5, t1, a6
+; RVA22U64-NEXT: lbu a6, 12(a0)
+; RVA22U64-NEXT: lbu t0, 13(a0)
+; RVA22U64-NEXT: lbu t1, 14(a0)
; RVA22U64-NEXT: lbu a0, 15(a0)
-; RVA22U64-NEXT: slli a2, a2, 32
-; RVA22U64-NEXT: slli a5, a5, 40
-; RVA22U64-NEXT: or a2, a2, a5
-; RVA22U64-NEXT: slli a3, a3, 48
+; RVA22U64-NEXT: slli a6, a6, 32
+; RVA22U64-NEXT: slli t0, t0, 40
+; RVA22U64-NEXT: or a6, t0, a6
+; RVA22U64-NEXT: slli t1, t1, 48
; RVA22U64-NEXT: slli a0, a0, 56
-; RVA22U64-NEXT: or a0, a0, a3
-; RVA22U64-NEXT: or a3, a6, t2
-; RVA22U64-NEXT: or a5, a7, t1
-; RVA22U64-NEXT: or a1, a1, a4
-; RVA22U64-NEXT: or a0, a0, a2
-; RVA22U64-NEXT: or a3, a3, a5
-; RVA22U64-NEXT: or a0, a0, a1
+; RVA22U64-NEXT: or a0, a0, t1
+; RVA22U64-NEXT: or a1, a1, a3
+; RVA22U64-NEXT: or a2, a7, a2
+; RVA22U64-NEXT: or a4, a4, a5
+; RVA22U64-NEXT: or a0, a0, a6
+; RVA22U64-NEXT: or a1, a1, a2
+; RVA22U64-NEXT: or a0, a0, a4
; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RVA22U64-NEXT: vmv.v.x v8, a3
+; RVA22U64-NEXT: vmv.v.x v8, a1
; RVA22U64-NEXT: vslide1down.vx v8, v8, a0
; RVA22U64-NEXT: ret
;
@@ -1572,36 +1572,36 @@ define <16 x i8> @buildvec_v16i8_loads_contigous(ptr %p) {
; RVA22U64-PACK: # %bb.0:
; RVA22U64-PACK-NEXT: lbu a1, 0(a0)
; RVA22U64-PACK-NEXT: lbu a2, 1(a0)
-; RVA22U64-PACK-NEXT: lbu a6, 2(a0)
-; RVA22U64-PACK-NEXT: lbu a7, 3(a0)
-; RVA22U64-PACK-NEXT: lbu t0, 4(a0)
-; RVA22U64-PACK-NEXT: lbu a3, 5(a0)
-; RVA22U64-PACK-NEXT: lbu a4, 6(a0)
-; RVA22U64-PACK-NEXT: lbu a5, 7(a0)
-; RVA22U64-PACK-NEXT: packh t1, a1, a2
-; RVA22U64-PACK-NEXT: lbu t2, 8(a0)
-; RVA22U64-PACK-NEXT: lbu t3, 9(a0)
-; RVA22U64-PACK-NEXT: lbu t4, 10(a0)
-; RVA22U64-PACK-NEXT: lbu a1, 11(a0)
-; RVA22U64-PACK-NEXT: packh a6, a6, a7
-; RVA22U64-PACK-NEXT: packh a7, t0, a3
-; RVA22U64-PACK-NEXT: packh t0, a4, a5
-; RVA22U64-PACK-NEXT: lbu a5, 12(a0)
-; RVA22U64-PACK-NEXT: lbu a3, 13(a0)
-; RVA22U64-PACK-NEXT: lbu a2, 14(a0)
+; RVA22U64-PACK-NEXT: lbu a3, 2(a0)
+; RVA22U64-PACK-NEXT: lbu a4, 3(a0)
+; RVA22U64-PACK-NEXT: lbu a5, 4(a0)
+; RVA22U64-PACK-NEXT: lbu a6, 5(a0)
+; RVA22U64-PACK-NEXT: lbu a7, 6(a0)
+; RVA22U64-PACK-NEXT: lbu t0, 7(a0)
+; RVA22U64-PACK-NEXT: packh a1, a1, a2
+; RVA22U64-PACK-NEXT: lbu a2, 8(a0)
+; RVA22U64-PACK-NEXT: lbu t1, 9(a0)
+; RVA22U64-PACK-NEXT: lbu t2, 10(a0)
+; RVA22U64-PACK-NEXT: lbu t3, 11(a0)
+; RVA22U64-PACK-NEXT: packh a3, a3, a4
+; RVA22U64-PACK-NEXT: packh a4, a5, a6
+; RVA22U64-PACK-NEXT: packh a5, a7, t0
+; RVA22U64-PACK-NEXT: lbu a6, 12(a0)
+; RVA22U64-PACK-NEXT: lbu a7, 13(a0)
+; RVA22U64-PACK-NEXT: lbu t0, 14(a0)
; RVA22U64-PACK-NEXT: lbu a0, 15(a0)
-; RVA22U64-PACK-NEXT: packh a4, t2, t3
-; RVA22U64-PACK-NEXT: packh a1, t4, a1
-; RVA22U64-PACK-NEXT: packh a3, a5, a3
-; RVA22U64-PACK-NEXT: packh a0, a2, a0
-; RVA22U64-PACK-NEXT: packw a2, t1, a6
-; RVA22U64-PACK-NEXT: packw a5, a7, t0
-; RVA22U64-PACK-NEXT: packw a1, a4, a1
-; RVA22U64-PACK-NEXT: packw a0, a3, a0
-; RVA22U64-PACK-NEXT: pack a2, a2, a5
-; RVA22U64-PACK-NEXT: pack a0, a1, a0
+; RVA22U64-PACK-NEXT: packh a2, a2, t1
+; RVA22U64-PACK-NEXT: packh t1, t2, t3
+; RVA22U64-PACK-NEXT: packh a6, a6, a7
+; RVA22U64-PACK-NEXT: packh a0, t0, a0
+; RVA22U64-PACK-NEXT: packw a1, a1, a3
+; RVA22U64-PACK-NEXT: packw a3, a4, a5
+; RVA22U64-PACK-NEXT: packw a2, a2, t1
+; RVA22U64-PACK-NEXT: packw a0, a6, a0
+; RVA22U64-PACK-NEXT: pack a1, a1, a3
+; RVA22U64-PACK-NEXT: pack a0, a2, a0
; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RVA22U64-PACK-NEXT: vmv.v.x v8, a2
+; RVA22U64-PACK-NEXT: vmv.v.x v8, a1
; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0
; RVA22U64-PACK-NEXT: ret
;
@@ -1893,98 +1893,90 @@ define <16 x i8> @buildvec_v16i8_loads_gather(ptr %p) {
;
; RVA22U64-LABEL: buildvec_v16i8_loads_gather:
; RVA22U64: # %bb.0:
-; RVA22U64-NEXT: lbu a7, 0(a0)
+; RVA22U64-NEXT: lbu a1, 0(a0)
; RVA22U64-NEXT: lbu a2, 1(a0)
; RVA22U64-NEXT: lbu a3, 22(a0)
; RVA22U64-NEXT: lbu a4, 31(a0)
-; RVA22U64-NEXT: lbu a6, 623(a0)
-; RVA22U64-NEXT: lbu a5, 44(a0)
-; RVA22U64-NEXT: lbu a1, 55(a0)
+; RVA22U64-NEXT: lbu a5, 623(a0)
+; RVA22U64-NEXT: lbu a6, 44(a0)
+; RVA22U64-NEXT: lbu a7, 55(a0)
; RVA22U64-NEXT: lbu t0, 75(a0)
; RVA22U64-NEXT: lbu t1, 82(a0)
; RVA22U64-NEXT: slli a2, a2, 8
; RVA22U64-NEXT: slli a3, a3, 16
; RVA22U64-NEXT: slli a4, a4, 24
-; RVA22U64-NEXT: slli a5, a5, 32
-; RVA22U64-NEXT: slli a1, a1, 40
-; RVA22U64-NEXT: or a7, a7, a2
-; RVA22U64-NEXT: or t3, a4, a3
-; RVA22U64-NEXT: or t2, a1, a5
+; RVA22U64-NEXT: slli a6, a6, 32
+; RVA22U64-NEXT: slli a7, a7, 40
+; RVA22U64-NEXT: or a1, a1, a2
+; RVA22U64-NEXT: or a3, a3, a4
+; RVA22U64-NEXT: or a2, a7, a6
; RVA22U64-NEXT: lbu a4, 93(a0)
-; RVA22U64-NEXT: lbu t4, 105(a0)
-; RVA22U64-NEXT: lbu a2, 124(a0)
-; RVA22U64-NEXT: lbu t5, 144(a0)
-; RVA22U64-NEXT: slli a6, a6, 48
+; RVA22U64-NEXT: lbu a6, 105(a0)
+; RVA22U64-NEXT: lbu a7, 124(a0)
+; RVA22U64-NEXT: lbu t2, 144(a0)
+; RVA22U64-NEXT: slli a5, a5, 48
; RVA22U64-NEXT: slli t0, t0, 56
; RVA22U64-NEXT: slli a4, a4, 8
-; RVA22U64-NEXT: or a3, t0, a6
+; RVA22U64-NEXT: or a5, t0, a5
; RVA22U64-NEXT: or a4, t1, a4
-; RVA22U64-NEXT: lbu a5, 161(a0)
-; RVA22U64-NEXT: lbu a1, 154(a0)
+; RVA22U64-NEXT: lbu t0, 161(a0)
+; RVA22U64-NEXT: lbu t1, 154(a0)
; RVA22U64-NEXT: lbu a0, 163(a0)
-; RVA22U64-NEXT: slli t4, t4, 16
-; RVA22U64-NEXT: slli a5, a5, 24
-; RVA22U64-NEXT: or a5, a5, t4
-; RVA22U64-NEXT: slli a2, a2, 32
+; RVA22U64-NEXT: slli a6, a6, 16
+; RVA22U64-NEXT: slli t0, t0, 24
+; RVA22U64-NEXT: or a6, t0, a6
+; RVA22U64-NEXT: slli a7, a7, 32
; RVA22U64-NEXT: slli a0, a0, 40
-; RVA22U64-NEXT: or a0, a0, a2
-; RVA22U64-NEXT: slli t5, t5, 48
-; RVA22U64-NEXT: slli a1, a1, 56
-; RVA22U64-NEXT: or a1, a1, t5
-; RVA22U64-NEXT: or a2, a7, t3
-; RVA22U64-NEXT: or a3, a3, t2
-; RVA22U64-NEXT: or a4, a4, a5
-; RVA22U64-NEXT: or a0, a0, a1
-; RVA22U64-NEXT: or a2, a2, a3
-; RVA22U64-NEXT: or a0, a0, a4
+; RVA22U64-NEXT: or a0, a0, a7
+; RVA22U64-NEXT: slli t2, t2, 48
+; RVA22U64-NEXT: slli t1, t1, 56
+; RVA22U64-NEXT: or a7, t1, t2
+; RVA22U64-NEXT: or a1, a1, a3
+; RVA22U64-NEXT: or a2, a2, a5
+; RVA22U64-NEXT: or a3, a4, a6
+; RVA22U64-NEXT: or a0, a7, a0
+; RVA22U64-NEXT: or a1, a1, a2
+; RVA22U64-NEXT: or a0, a0, a3
; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RVA22U64-NEXT: vmv.v.x v8, a2
+; RVA22U64-NEXT: vmv.v.x v8, a1
; RVA22U64-NEXT: vslide1down.vx v8, v8, a0
; RVA22U64-NEXT: ret
;
; RVA22U64-PACK-LABEL: buildvec_v16i8_loads_gather:
; RVA22U64-PACK: # %bb.0:
-; RVA22U64-PACK-NEXT: addi sp, sp, -16
-; RVA22U64-PACK-NEXT: .cfi_def_cfa_offset 16
-; RVA22U64-PACK-NEXT: sd s0, 8(sp) # 8-byte Folded Spill
-; RVA22U64-PACK-NEXT: .cfi_offset s0, -8
; RVA22U64-PACK-NEXT: lbu a1, 0(a0)
; RVA22U64-PACK-NEXT: lbu a2, 1(a0)
-; RVA22U64-PACK-NEXT: lbu a6, 22(a0)
-; RVA22U64-PACK-NEXT: lbu a7, 31(a0)
-; RVA22U64-PACK-NEXT: lbu t0, 623(a0)
-; RVA22U64-PACK-NEXT: lbu t3, 44(a0)
-; RVA22U64-PACK-NEXT: lbu t4, 55(a0)
-; RVA22U64-PACK-NEXT: lbu t5, 75(a0)
+; RVA22U64-PACK-NEXT: lbu a3, 22(a0)
+; RVA22U64-PACK-NEXT: lbu a4, 31(a0)
+; RVA22U64-PACK-NEXT: lbu a5, 623(a0)
+; RVA22U64-PACK-NEXT: lbu a6, 44(a0)
+; RVA22U64-PACK-NEXT: lbu a7, 55(a0)
+; RVA22U64-PACK-NEXT: lbu t0, 75(a0)
; RVA22U64-PACK-NEXT: lbu t1, 82(a0)
-; RVA22U64-PACK-NEXT: packh t2, a1, a2
-; RVA22U64-PACK-NEXT: lbu t6, 154(a0)
-; RVA22U64-PACK-NEXT: lbu s0, 161(a0)
-; RVA22U64-PACK-NEXT: lbu a3, 163(a0)
-; RVA22U64-PACK-NEXT: packh a6, a6, a7
-; RVA22U64-PACK-NEXT: packh a7, t3, t4
-; RVA22U64-PACK-NEXT: packh a2, t0, t5
-; RVA22U64-PACK-NEXT: lbu a4, 93(a0)
-; RVA22U64-PACK-NEXT: lbu a5, 105(a0)
-; RVA22U64-PACK-NEXT: lbu a1, 124(a0)
+; RVA22U64-PACK-NEXT: packh a1, a1, a2
+; RVA22U64-PACK-NEXT: lbu a2, 154(a0)
+; RVA22U64-PACK-NEXT: lbu t2, 161(a0)
+; RVA22U64-PACK-NEXT: lbu t3, 163(a0)
+; RVA22U64-PACK-NEXT: packh a3, a3, a4
+; RVA22U64-PACK-NEXT: packh a4, a6, a7
+; RVA22U64-PACK-NEXT: packh a5, a5, t0
+; RVA22U64-PACK-NEXT: lbu a6, 93(a0)
+; RVA22U64-PACK-NEXT: lbu a7, 105(a0)
+; RVA22U64-PACK-NEXT: lbu t0, 124(a0)
; RVA22U64-PACK-NEXT: lbu a0, 144(a0)
-; RVA22U64-PACK-NEXT: packh a4, t1, a4
-; RVA22U64-PACK-NEXT: packh a5, a5, s0
-; RVA22U64-PACK-NEXT: packh a1, a1, a3
-; RVA22U64-PACK-NEXT: packh a0, a0, t6
-; RVA22U64-PACK-NEXT: packw a3, t2, a6
-; RVA22U64-PACK-NEXT: packw a2, a7, a2
-; RVA22U64-PACK-NEXT: packw a4, a4, a5
-; RVA22U64-PACK-NEXT: packw a0, a1, a0
-; RVA22U64-PACK-NEXT: pack a1, a3, a2
-; RVA22U64-PACK-NEXT: pack a0, a4, a0
+; RVA22U64-PACK-NEXT: packh a6, t1, a6
+; RVA22U64-PACK-NEXT: packh a7, a7, t2
+; RVA22U64-PACK-NEXT: packh t0, t0, t3
+; RVA22U64-PACK-NEXT: packh a0, a0, a2
+; RVA22U64-PACK-NEXT: packw a1, a1, a3
+; RVA22U64-PACK-NEXT: packw a2, a4, a5
+; RVA22U64-PACK-NEXT: packw a3, a6, a7
+; RVA22U64-PACK-NEXT: packw a0, t0, a0
+; RVA22U64-PACK-NEXT: pack a1, a1, a2
+; RVA22U64-PACK-NEXT: pack a0, a3, a0
; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVA22U64-PACK-NEXT: vmv.v.x v8, a1
; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0
-; RVA22U64-PACK-NEXT: ld s0, 8(sp) # 8-byte Folded Reload
-; RVA22U64-PACK-NEXT: .cfi_restore s0
-; RVA22U64-PACK-NEXT: addi sp, sp, 16
-; RVA22U64-PACK-NEXT: .cfi_def_cfa_offset 0
; RVA22U64-PACK-NEXT: ret
;
; RV64ZVE32-LABEL: buildvec_v16i8_loads_gather:
@@ -2191,10 +2183,10 @@ define <16 x i8> @buildvec_v16i8_undef_low_half(ptr %p) {
; RVA22U64-NEXT: lbu a3, 105(a0)
; RVA22U64-NEXT: lbu a4, 124(a0)
; RVA22U64-NEXT: slli a1, a1, 8
-; RVA22U64-NEXT: or a6, a2, a1
+; RVA22U64-NEXT: or a1, a1, a2
; RVA22U64-NEXT: lbu a2, 161(a0)
; RVA22U64-NEXT: lbu a5, 144(a0)
-; RVA22U64-NEXT: lbu a1, 154(a0)
+; RVA22U64-NEXT: lbu a6, 154(a0)
; RVA22U64-NEXT: lbu a0, 163(a0)
; RVA22U64-NEXT: slli a3, a3, 16
; RVA22U64-NEXT: slli a2, a2, 24
@@ -2203,11 +2195,11 @@ define <16 x i8> @buildvec_v16i8_undef_low_half(ptr %p) {
; RVA22U64-NEXT: slli a0, a0, 40
; RVA22U64-NEXT: or a0, a0, a4
; RVA22U64-NEXT: slli a5, a5, 48
-; RVA22U64-NEXT: slli a1, a1, 56
-; RVA22U64-NEXT: or a1, a1, a5
-; RVA22U64-NEXT: or a2, a6, a2
+; RVA22U64-NEXT: slli a6, a6, 56
+; RVA22U64-NEXT: or a3, a6, a5
+; RVA22U64-NEXT: or a1, a1, a2
+; RVA22U64-NEXT: or a0, a0, a3
; RVA22U64-NEXT: or a0, a0, a1
-; RVA22U64-NEXT: or a0, a0, a2
; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVA22U64-NEXT: vmv.v.i v8, 0
; RVA22U64-NEXT: vslide1down.vx v8, v8, a0
@@ -2215,26 +2207,26 @@ define <16 x i8> @buildvec_v16i8_undef_low_half(ptr %p) {
;
; RVA22U64-PACK-LABEL: buildvec_v16i8_undef_low_half:
; RVA22U64-PACK: # %bb.0:
-; RVA22U64-PACK-NEXT: lbu a6, 82(a0)
-; RVA22U64-PACK-NEXT: lbu a7, 93(a0)
-; RVA22U64-PACK-NEXT: lbu t0, 105(a0)
+; RVA22U64-PACK-NEXT: lbu a1, 82(a0)
+; RVA22U64-PACK-NEXT: lbu a2, 93(a0)
+; RVA22U64-PACK-NEXT: lbu a3, 105(a0)
; RVA22U64-PACK-NEXT: lbu a4, 124(a0)
; RVA22U64-PACK-NEXT: lbu a5, 161(a0)
-; RVA22U64-PACK-NEXT: lbu a1, 163(a0)
-; RVA22U64-PACK-NEXT: lbu a2, 144(a0)
+; RVA22U64-PACK-NEXT: lbu a6, 163(a0)
+; RVA22U64-PACK-NEXT: lbu a7, 144(a0)
; RVA22U64-PACK-NEXT: lbu a0, 154(a0)
-; RVA22U64-PACK-NEXT: packh a3, a6, a7
-; RVA22U64-PACK-NEXT: packh a5, t0, a5
-; RVA22U64-PACK-NEXT: packh a1, a4, a1
-; RVA22U64-PACK-NEXT: packh a0, a2, a0
-; RVA22U64-PACK-NEXT: packw a2, a3, a5
-; RVA22U64-PACK-NEXT: packh a3, a0, a0
-; RVA22U64-PACK-NEXT: packw a3, a3, a3
-; RVA22U64-PACK-NEXT: pack a3, a3, a3
-; RVA22U64-PACK-NEXT: packw a0, a1, a0
-; RVA22U64-PACK-NEXT: pack a0, a2, a0
+; RVA22U64-PACK-NEXT: packh a1, a1, a2
+; RVA22U64-PACK-NEXT: packh a2, a3, a5
+; RVA22U64-PACK-NEXT: packh a3, a4, a6
+; RVA22U64-PACK-NEXT: packh a0, a7, a0
+; RVA22U64-PACK-NEXT: packw a1, a1, a2
+; RVA22U64-PACK-NEXT: packh a2, a0, a0
+; RVA22U64-PACK-NEXT: packw a2, a2, a2
+; RVA22U64-PACK-NEXT: pack a2, a2, a2
+; RVA22U64-PACK-NEXT: packw a0, a3, a0
+; RVA22U64-PACK-NEXT: pack a0, a1, a0
; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RVA22U64-PACK-NEXT: vmv.v.x v8, a3
+; RVA22U64-PACK-NEXT: vmv.v.x v8, a2
; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0
; RVA22U64-PACK-NEXT: ret
;
@@ -2417,26 +2409,26 @@ define <16 x i8> @buildvec_v16i8_undef_high_half(ptr %p) {
;
; RVA22U64-PACK-LABEL: buildvec_v16i8_undef_high_half:
; RVA22U64-PACK: # %bb.0:
-; RVA22U64-PACK-NEXT: lbu a6, 0(a0)
-; RVA22U64-PACK-NEXT: lbu a7, 1(a0)
-; RVA22U64-PACK-NEXT: lbu t0, 22(a0)
+; RVA22U64-PACK-NEXT: lbu a1, 0(a0)
+; RVA22U64-PACK-NEXT: lbu a2, 1(a0)
+; RVA22U64-PACK-NEXT: lbu a3, 22(a0)
; RVA22U64-PACK-NEXT: lbu a4, 31(a0)
; RVA22U64-PACK-NEXT: lbu a5, 623(a0)
-; RVA22U64-PACK-NEXT: lbu a1, 44(a0)
-; RVA22U64-PACK-NEXT: lbu a2, 55(a0)
+; RVA22U64-PACK-NEXT: lbu a6, 44(a0)
+; RVA22U64-PACK-NEXT: lbu a7, 55(a0)
; RVA22U64-PACK-NEXT: lbu a0, 75(a0)
-; RVA22U64-PACK-NEXT: packh a3, a6, a7
-; RVA22U64-PACK-NEXT: packh a4, t0, a4
; RVA22U64-PACK-NEXT: packh a1, a1, a2
+; RVA22U64-PACK-NEXT: packh a2, a3, a4
+; RVA22U64-PACK-NEXT: packh a3, a6, a7
; RVA22U64-PACK-NEXT: packh a0, a5, a0
-; RVA22U64-PACK-NEXT: packw a2, a3, a4
-; RVA22U64-PACK-NEXT: packh a3, a0, a0
-; RVA22U64-PACK-NEXT: packw a3, a3, a3
-; RVA22U64-PACK-NEXT: packw a0, a1, a0
-; RVA22U64-PACK-NEXT: pack a0, a2, a0
+; RVA22U64-PACK-NEXT: packw a1, a1, a2
+; RVA22U64-PACK-NEXT: packh a2, a0, a0
+; RVA22U64-PACK-NEXT: packw a2, a2, a2
+; RVA22U64-PACK-NEXT: packw a0, a3, a0
+; RVA22U64-PACK-NEXT: pack a0, a1, a0
; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVA22U64-PACK-NEXT: vmv.v.x v8, a0
-; RVA22U64-PACK-NEXT: pack a0, a3, a3
+; RVA22U64-PACK-NEXT: pack a0, a2, a2
; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0
; RVA22U64-PACK-NEXT: ret
;
@@ -2610,7 +2602,7 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
; RVA22U64-NEXT: lbu a1, 623(a0)
; RVA22U64-NEXT: lbu a2, 44(a0)
; RVA22U64-NEXT: lbu a3, 55(a0)
-; RVA22U64-NEXT: lbu a6, 31(a0)
+; RVA22U64-NEXT: lbu a4, 31(a0)
; RVA22U64-NEXT: lbu a5, 75(a0)
; RVA22U64-NEXT: slli a2, a2, 32
; RVA22U64-NEXT: slli a3, a3, 40
@@ -2620,16 +2612,16 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
; RVA22U64-NEXT: or a1, a1, a5
; RVA22U64-NEXT: lbu a3, 93(a0)
; RVA22U64-NEXT: lbu a5, 82(a0)
-; RVA22U64-NEXT: lbu a4, 105(a0)
+; RVA22U64-NEXT: lbu a6, 105(a0)
; RVA22U64-NEXT: lbu a0, 161(a0)
; RVA22U64-NEXT: slli a3, a3, 8
; RVA22U64-NEXT: or a3, a3, a5
-; RVA22U64-NEXT: slli a4, a4, 16
+; RVA22U64-NEXT: slli a6, a6, 16
; RVA22U64-NEXT: slli a0, a0, 24
-; RVA22U64-NEXT: or a0, a0, a4
-; RVA22U64-NEXT: slli a6, a6, 24
+; RVA22U64-NEXT: or a0, a0, a6
+; RVA22U64-NEXT: slli a4, a4, 24
; RVA22U64-NEXT: or a1, a1, a2
-; RVA22U64-NEXT: or a1, a6, a1
+; RVA22U64-NEXT: or a1, a1, a4
; RVA22U64-NEXT: or a0, a0, a3
; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVA22U64-NEXT: vmv.v.x v8, a1
@@ -2638,29 +2630,29 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
;
; RVA22U64-PACK-LABEL: buildvec_v16i8_undef_edges:
; RVA22U64-PACK: # %bb.0:
-; RVA22U64-PACK-NEXT: lbu a7, 623(a0)
-; RVA22U64-PACK-NEXT: lbu a6, 31(a0)
-; RVA22U64-PACK-NEXT: lbu t0, 44(a0)
+; RVA22U64-PACK-NEXT: lbu a1, 623(a0)
+; RVA22U64-PACK-NEXT: lbu a2, 31(a0)
+; RVA22U64-PACK-NEXT: lbu a3, 44(a0)
; RVA22U64-PACK-NEXT: lbu a4, 55(a0)
; RVA22U64-PACK-NEXT: lbu a5, 75(a0)
-; RVA22U64-PACK-NEXT: lbu a2, 82(a0)
-; RVA22U64-PACK-NEXT: lbu a1, 93(a0)
-; RVA22U64-PACK-NEXT: lbu a3, 105(a0)
+; RVA22U64-PACK-NEXT: lbu a6, 82(a0)
+; RVA22U64-PACK-NEXT: lbu a7, 93(a0)
+; RVA22U64-PACK-NEXT: lbu t0, 105(a0)
; RVA22U64-PACK-NEXT: lbu a0, 161(a0)
-; RVA22U64-PACK-NEXT: packh a4, t0, a4
-; RVA22U64-PACK-NEXT: packh a5, a7, a5
-; RVA22U64-PACK-NEXT: packh a1, a2, a1
-; RVA22U64-PACK-NEXT: packh a0, a3, a0
-; RVA22U64-PACK-NEXT: packh a2, a0, a0
-; RVA22U64-PACK-NEXT: packh a3, a0, a6
-; RVA22U64-PACK-NEXT: packw a3, a2, a3
-; RVA22U64-PACK-NEXT: packw a2, a2, a2
-; RVA22U64-PACK-NEXT: packw a4, a4, a5
-; RVA22U64-PACK-NEXT: packw a0, a1, a0
-; RVA22U64-PACK-NEXT: pack a1, a3, a4
+; RVA22U64-PACK-NEXT: packh a3, a3, a4
+; RVA22U64-PACK-NEXT: packh a1, a1, a5
+; RVA22U64-PACK-NEXT: packh a4, a6, a7
+; RVA22U64-PACK-NEXT: packh a0, t0, a0
+; RVA22U64-PACK-NEXT: packh a5, a0, a0
+; RVA22U64-PACK-NEXT: packh a2, a0, a2
+; RVA22U64-PACK-NEXT: packw a2, a5, a2
+; RVA22U64-PACK-NEXT: packw a5, a5, a5
+; RVA22U64-PACK-NEXT: packw a1, a3, a1
+; RVA22U64-PACK-NEXT: packw a0, a4, a0
+; RVA22U64-PACK-NEXT: pack a1, a2, a1
; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVA22U64-PACK-NEXT: vmv.v.x v8, a1
-; RVA22U64-PACK-NEXT: pack a0, a0, a2
+; RVA22U64-PACK-NEXT: pack a0, a0, a5
; RVA22U64-PACK-NEXT: vslide1down.vx v8, v8, a0
; RVA22U64-PACK-NEXT: ret
;
@@ -2858,29 +2850,29 @@ define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) {
; RVA22U64-NEXT: lbu a3, 44(a0)
; RVA22U64-NEXT: lbu a4, 55(a0)
; RVA22U64-NEXT: slli a1, a1, 8
-; RVA22U64-NEXT: or a6, a2, a1
-; RVA22U64-NEXT: lbu a7, 75(a0)
+; RVA22U64-NEXT: or a1, a1, a2
+; RVA22U64-NEXT: lbu a2, 75(a0)
; RVA22U64-NEXT: lbu a5, 82(a0)
-; RVA22U64-NEXT: lbu a1, 93(a0)
-; RVA22U64-NEXT: lbu a2, 124(a0)
+; RVA22U64-NEXT: lbu a6, 93(a0)
+; RVA22U64-NEXT: lbu a7, 124(a0)
; RVA22U64-NEXT: slli a3, a3, 32
; RVA22U64-NEXT: slli a4, a4, 40
; RVA22U64-NEXT: or a3, a3, a4
; RVA22U64-NEXT: lbu a4, 144(a0)
; RVA22U64-NEXT: lbu a0, 154(a0)
-; RVA22U64-NEXT: slli a1, a1, 8
-; RVA22U64-NEXT: or a1, a1, a5
+; RVA22U64-NEXT: slli a6, a6, 8
+; RVA22U64-NEXT: or a5, a5, a6
; RVA22U64-NEXT: slli a4, a4, 48
; RVA22U64-NEXT: slli a0, a0, 56
; RVA22U64-NEXT: or a0, a0, a4
-; RVA22U64-NEXT: slli a7, a7, 56
-; RVA22U64-NEXT: or a3, a7, a3
-; RVA22U64-NEXT: slli a2, a2, 32
-; RVA22U64-NEXT: or a0, a0, a2
-; RVA22U64-NEXT: or a2, a6, a3
-; RVA22U64-NEXT: or a0, a0, a1
+; RVA22U64-NEXT: slli a2, a2, 56
+; RVA22U64-NEXT: or a2, a2, a3
+; RVA22U64-NEXT: slli a7, a7, 32
+; RVA22U64-NEXT: or a0, a0, a7
+; RVA22U64-NEXT: or a1, a1, a2
+; RVA22U64-NEXT: or a0, a0, a5
; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RVA22U64-NEXT: vmv.v.x v8, a2
+; RVA22U64-NEXT: vmv.v.x v8, a1
; RVA22U64-NEXT: vslide1down.vx v8, v8, a0
; RVA22U64-NEXT: ret
;
@@ -2888,26 +2880,26 @@ define <16 x i8> @buildvec_v16i8_loads_undef_scattered(ptr %p) {
; RVA22U64-PACK: # %bb.0:
; RVA22U64-PACK-NEXT: lbu a1, 0(a0)
; RVA22U64-PACK-NEXT: lbu a2, 1(a0)
-; RVA22U64-PACK-NEXT: lbu a6, 44(a0)
-; RVA22U64-PACK-NEXT: lbu a7, 55(a0)
-; RVA22U64-PACK-NEXT: lbu t1, 82(a0)
-; RVA22U64-PACK-NEXT: lbu a3, 93(a0)
-; RVA22U64-PACK-NEXT: packh t0, a1, a2
+; RVA22U64-PACK-NEXT: lbu a3, 44(a0)
+; RVA22U64-PACK-NEXT: lbu a4, 55(a0)
+; RVA22U64-PACK-NEXT: lbu a5, 82(a0)
+; RVA22U64-PACK-NEXT: lbu a6, 93(a0)
+; RVA22U64-PACK-NEXT: packh a1, a1, a2
; RVA22U64-PACK-NEXT: lbu a2, 144(a0)
-; RVA22U64-PACK-NEXT: lbu a4, 154(a0)
-; RVA22U64-PACK-NEXT: packh a1, a6, a7
-; RVA22U64-PACK-NEXT: lbu a5, 75(a0)
+; RVA22U64-PACK-NEXT: lbu a7, 154(a0)
+; RVA22U64-PACK-NEXT: packh a3, a3, a4
+; RVA22U64-PACK-NEXT: lbu a4, 75(a0)
; RVA22U64-PACK-NEXT: lbu a0, 124(a0)
-; RVA22U64-PACK-NEXT: packh a3, t1, a3
-; RVA22U64-PACK-NEXT: packh a2, a2, a4
-; RVA22U64-PACK-NEXT: packh a4, a0, a5
-; RVA22U64-PACK-NEXT: packw a1, a1, a4
+; RVA22U64-PACK-NEXT: packh a5, a5, a6
+; RVA22U64-PACK-NEXT: packh a2, a2, a7
+; RVA22U64-PACK-NEXT: packh a4, a0, a4
+; RVA22U64-PACK-NEXT: packw a3, a3, a4
; RVA22U64-PACK-NEXT: packh a4, a0, a0
; RVA22U64-PACK-NEXT: packh a0, a0, a0
-; RVA22U64-PACK-NEXT: packw a5, t0, a4
+; RVA22U64-PACK-NEXT: packw a1, a1, a4
; RVA22U64-PACK-NEXT: packw a0, a0, a2
-; RVA22U64-PACK-NEXT: packw a2, a3, a4
-; RVA22U64-PACK-NEXT: pack a1, a5, a1
+; RVA22U64-PACK-NEXT: packw a2, a5, a4
+; RVA22U64-PACK-NEXT: pack a1, a1, a3
; RVA22U64-PACK-NEXT: pack a0, a2, a0
; RVA22U64-PACK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVA22U64-PACK-NEXT: vmv.v.x v8, a1
@@ -3069,22 +3061,22 @@ define <8 x i8> @buildvec_v8i8_pack(i8 %e1, i8 %e2, i8 %e3, i8 %e4, i8 %e5, i8 %
;
; RVA22U64-LABEL: buildvec_v8i8_pack:
; RVA22U64: # %bb.0:
-; RVA22U64-NEXT: zext.b t0, a4
+; RVA22U64-NEXT: zext.b a4, a4
; RVA22U64-NEXT: zext.b a5, a5
; RVA22U64-NEXT: slli a7, a7, 56
-; RVA22U64-NEXT: zext.b a4, a6
+; RVA22U64-NEXT: zext.b a6, a6
; RVA22U64-NEXT: zext.b a2, a2
; RVA22U64-NEXT: zext.b a3, a3
; RVA22U64-NEXT: zext.b a0, a0
; RVA22U64-NEXT: zext.b a1, a1
-; RVA22U64-NEXT: slli t0, t0, 32
+; RVA22U64-NEXT: slli a4, a4, 32
; RVA22U64-NEXT: slli a5, a5, 40
-; RVA22U64-NEXT: slli a4, a4, 48
+; RVA22U64-NEXT: slli a6, a6, 48
; RVA22U64-NEXT: slli a2, a2, 16
; RVA22U64-NEXT: slli a3, a3, 24
; RVA22U64-NEXT: slli a1, a1, 8
-; RVA22U64-NEXT: or a5, a5, t0
-; RVA22U64-NEXT: or a4, a7, a4
+; RVA22U64-NEXT: or a4, a4, a5
+; RVA22U64-NEXT: or a5, a7, a6
; RVA22U64-NEXT: or a2, a2, a3
; RVA22U64-NEXT: or a0, a0, a1
; RVA22U64-NEXT: or a4, a4, a5
diff --git a/llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll b/llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
index e84e456f5c2a4..3ecb0af5b0089 100644
--- a/llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/nontemporal-vp-scalable.ll
@@ -29405,17 +29405,17 @@ define <vscale x 32 x i8> @test_nontemporal_vp_gather_nxv32i8_P1(<vscale x 32 x
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a0)
; CHECK-RV64VC-NEXT: slli a4, a1, 3
; CHECK-RV64VC-NEXT: slli a3, a1, 1
-; CHECK-RV64VC-NEXT: add a6, a0, a4
+; CHECK-RV64VC-NEXT: add a4, a4, a0
; CHECK-RV64VC-NEXT: sub a0, a2, a3
; CHECK-RV64VC-NEXT: sltu a5, a2, a0
; CHECK-RV64VC-NEXT: addi a5, a5, -1
; CHECK-RV64VC-NEXT: and a0, a0, a5
; CHECK-RV64VC-NEXT: sub a5, a0, a1
-; CHECK-RV64VC-NEXT: sltu a4, a0, a5
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a5
-; CHECK-RV64VC-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v0, (a6)
+; CHECK-RV64VC-NEXT: sltu a6, a0, a5
+; CHECK-RV64VC-NEXT: addi a6, a6, -1
+; CHECK-RV64VC-NEXT: and a5, a6, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-RV64VC-NEXT: vle64.v v0, (a4)
; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB850_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a0, a1
@@ -29580,17 +29580,17 @@ define <vscale x 32 x i8> @test_nontemporal_vp_gather_nxv32i8_PALL(<vscale x 32
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a0)
; CHECK-RV64VC-NEXT: slli a4, a1, 3
; CHECK-RV64VC-NEXT: slli a3, a1, 1
-; CHECK-RV64VC-NEXT: add a6, a0, a4
+; CHECK-RV64VC-NEXT: add a4, a4, a0
; CHECK-RV64VC-NEXT: sub a0, a2, a3
; CHECK-RV64VC-NEXT: sltu a5, a2, a0
; CHECK-RV64VC-NEXT: addi a5, a5, -1
; CHECK-RV64VC-NEXT: and a0, a0, a5
; CHECK-RV64VC-NEXT: sub a5, a0, a1
-; CHECK-RV64VC-NEXT: sltu a4, a0, a5
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a5
-; CHECK-RV64VC-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v0, (a6)
+; CHECK-RV64VC-NEXT: sltu a6, a0, a5
+; CHECK-RV64VC-NEXT: addi a6, a6, -1
+; CHECK-RV64VC-NEXT: and a5, a6, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-RV64VC-NEXT: vle64.v v0, (a4)
; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB851_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a0, a1
@@ -29755,17 +29755,17 @@ define <vscale x 32 x i8> @test_nontemporal_vp_gather_nxv32i8_S1(<vscale x 32 x
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a0)
; CHECK-RV64VC-NEXT: slli a4, a1, 3
; CHECK-RV64VC-NEXT: slli a3, a1, 1
-; CHECK-RV64VC-NEXT: add a6, a0, a4
+; CHECK-RV64VC-NEXT: add a4, a4, a0
; CHECK-RV64VC-NEXT: sub a0, a2, a3
; CHECK-RV64VC-NEXT: sltu a5, a2, a0
; CHECK-RV64VC-NEXT: addi a5, a5, -1
; CHECK-RV64VC-NEXT: and a0, a0, a5
; CHECK-RV64VC-NEXT: sub a5, a0, a1
-; CHECK-RV64VC-NEXT: sltu a4, a0, a5
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a5
-; CHECK-RV64VC-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v0, (a6)
+; CHECK-RV64VC-NEXT: sltu a6, a0, a5
+; CHECK-RV64VC-NEXT: addi a6, a6, -1
+; CHECK-RV64VC-NEXT: and a5, a6, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-RV64VC-NEXT: vle64.v v0, (a4)
; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB852_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a0, a1
@@ -29930,17 +29930,17 @@ define <vscale x 32 x i8> @test_nontemporal_vp_gather_nxv32i8_ALL(<vscale x 32 x
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a0)
; CHECK-RV64VC-NEXT: slli a4, a1, 3
; CHECK-RV64VC-NEXT: slli a3, a1, 1
-; CHECK-RV64VC-NEXT: add a6, a0, a4
+; CHECK-RV64VC-NEXT: add a4, a4, a0
; CHECK-RV64VC-NEXT: sub a0, a2, a3
; CHECK-RV64VC-NEXT: sltu a5, a2, a0
; CHECK-RV64VC-NEXT: addi a5, a5, -1
; CHECK-RV64VC-NEXT: and a0, a0, a5
; CHECK-RV64VC-NEXT: sub a5, a0, a1
-; CHECK-RV64VC-NEXT: sltu a4, a0, a5
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a5
-; CHECK-RV64VC-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v0, (a6)
+; CHECK-RV64VC-NEXT: sltu a6, a0, a5
+; CHECK-RV64VC-NEXT: addi a6, a6, -1
+; CHECK-RV64VC-NEXT: and a5, a6, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-RV64VC-NEXT: vle64.v v0, (a4)
; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB853_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a0, a1
@@ -30104,17 +30104,17 @@ define <vscale x 32 x i8> @test_nontemporal_vp_gather_nxv32i8_DEFAULT(<vscale x
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a0)
; CHECK-RV64VC-NEXT: slli a4, a1, 3
; CHECK-RV64VC-NEXT: slli a3, a1, 1
-; CHECK-RV64VC-NEXT: add a6, a0, a4
+; CHECK-RV64VC-NEXT: add a4, a4, a0
; CHECK-RV64VC-NEXT: sub a0, a2, a3
; CHECK-RV64VC-NEXT: sltu a5, a2, a0
; CHECK-RV64VC-NEXT: addi a5, a5, -1
; CHECK-RV64VC-NEXT: and a0, a0, a5
; CHECK-RV64VC-NEXT: sub a5, a0, a1
-; CHECK-RV64VC-NEXT: sltu a4, a0, a5
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a5
-; CHECK-RV64VC-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v0, (a6)
+; CHECK-RV64VC-NEXT: sltu a6, a0, a5
+; CHECK-RV64VC-NEXT: addi a6, a6, -1
+; CHECK-RV64VC-NEXT: and a5, a6, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-RV64VC-NEXT: vle64.v v0, (a4)
; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB854_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a0, a1
@@ -30318,26 +30318,26 @@ define void @test_nontemporal_vp_scatter_nxv32i8_P1(<vscale x 32 x i8> %val, <vs
; CHECK-RV64VC-NEXT: addi a1, a1, 16
; CHECK-RV64VC-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a6, a1, 4
+; CHECK-RV64VC-NEXT: slli a5, a1, 4
; CHECK-RV64VC-NEXT: slli a2, a1, 1
-; CHECK-RV64VC-NEXT: slli a5, a1, 3
+; CHECK-RV64VC-NEXT: slli a6, a1, 3
; CHECK-RV64VC-NEXT: mv a4, a3
; CHECK-RV64VC-NEXT: bltu a3, a2, .LBB855_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, a2
; CHECK-RV64VC-NEXT: .LBB855_2:
; CHECK-RV64VC-NEXT: vl8re64.v v0, (a0)
-; CHECK-RV64VC-NEXT: add a6, a6, a0
; CHECK-RV64VC-NEXT: add a5, a5, a0
+; CHECK-RV64VC-NEXT: add a6, a6, a0
; CHECK-RV64VC-NEXT: mv a0, a4
; CHECK-RV64VC-NEXT: bltu a4, a1, .LBB855_4
; CHECK-RV64VC-NEXT: # %bb.3:
; CHECK-RV64VC-NEXT: mv a0, a1
; CHECK-RV64VC-NEXT: .LBB855_4:
-; CHECK-RV64VC-NEXT: vl8re64.v v8, (a6)
-; CHECK-RV64VC-NEXT: addi a6, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; CHECK-RV64VC-NEXT: vl8re64.v v24, (a5)
+; CHECK-RV64VC-NEXT: vl8re64.v v8, (a5)
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v24, (a6)
; CHECK-RV64VC-NEXT: csrr a5, vlenb
; CHECK-RV64VC-NEXT: slli a5, a5, 4
; CHECK-RV64VC-NEXT: add a5, a5, sp
@@ -30555,26 +30555,26 @@ define void @test_nontemporal_vp_scatter_nxv32i8_PALL(<vscale x 32 x i8> %val, <
; CHECK-RV64VC-NEXT: addi a1, a1, 16
; CHECK-RV64VC-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a6, a1, 4
+; CHECK-RV64VC-NEXT: slli a5, a1, 4
; CHECK-RV64VC-NEXT: slli a2, a1, 1
-; CHECK-RV64VC-NEXT: slli a5, a1, 3
+; CHECK-RV64VC-NEXT: slli a6, a1, 3
; CHECK-RV64VC-NEXT: mv a4, a3
; CHECK-RV64VC-NEXT: bltu a3, a2, .LBB856_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, a2
; CHECK-RV64VC-NEXT: .LBB856_2:
; CHECK-RV64VC-NEXT: vl8re64.v v0, (a0)
-; CHECK-RV64VC-NEXT: add a6, a6, a0
; CHECK-RV64VC-NEXT: add a5, a5, a0
+; CHECK-RV64VC-NEXT: add a6, a6, a0
; CHECK-RV64VC-NEXT: mv a0, a4
; CHECK-RV64VC-NEXT: bltu a4, a1, .LBB856_4
; CHECK-RV64VC-NEXT: # %bb.3:
; CHECK-RV64VC-NEXT: mv a0, a1
; CHECK-RV64VC-NEXT: .LBB856_4:
-; CHECK-RV64VC-NEXT: vl8re64.v v8, (a6)
-; CHECK-RV64VC-NEXT: addi a6, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; CHECK-RV64VC-NEXT: vl8re64.v v24, (a5)
+; CHECK-RV64VC-NEXT: vl8re64.v v8, (a5)
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v24, (a6)
; CHECK-RV64VC-NEXT: csrr a5, vlenb
; CHECK-RV64VC-NEXT: slli a5, a5, 4
; CHECK-RV64VC-NEXT: add a5, a5, sp
@@ -30792,26 +30792,26 @@ define void @test_nontemporal_vp_scatter_nxv32i8_S1(<vscale x 32 x i8> %val, <vs
; CHECK-RV64VC-NEXT: addi a1, a1, 16
; CHECK-RV64VC-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a6, a1, 4
+; CHECK-RV64VC-NEXT: slli a5, a1, 4
; CHECK-RV64VC-NEXT: slli a2, a1, 1
-; CHECK-RV64VC-NEXT: slli a5, a1, 3
+; CHECK-RV64VC-NEXT: slli a6, a1, 3
; CHECK-RV64VC-NEXT: mv a4, a3
; CHECK-RV64VC-NEXT: bltu a3, a2, .LBB857_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, a2
; CHECK-RV64VC-NEXT: .LBB857_2:
; CHECK-RV64VC-NEXT: vl8re64.v v0, (a0)
-; CHECK-RV64VC-NEXT: add a6, a6, a0
; CHECK-RV64VC-NEXT: add a5, a5, a0
+; CHECK-RV64VC-NEXT: add a6, a6, a0
; CHECK-RV64VC-NEXT: mv a0, a4
; CHECK-RV64VC-NEXT: bltu a4, a1, .LBB857_4
; CHECK-RV64VC-NEXT: # %bb.3:
; CHECK-RV64VC-NEXT: mv a0, a1
; CHECK-RV64VC-NEXT: .LBB857_4:
-; CHECK-RV64VC-NEXT: vl8re64.v v8, (a6)
-; CHECK-RV64VC-NEXT: addi a6, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; CHECK-RV64VC-NEXT: vl8re64.v v24, (a5)
+; CHECK-RV64VC-NEXT: vl8re64.v v8, (a5)
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v24, (a6)
; CHECK-RV64VC-NEXT: csrr a5, vlenb
; CHECK-RV64VC-NEXT: slli a5, a5, 4
; CHECK-RV64VC-NEXT: add a5, a5, sp
@@ -31029,26 +31029,26 @@ define void @test_nontemporal_vp_scatter_nxv32i8_ALL(<vscale x 32 x i8> %val, <v
; CHECK-RV64VC-NEXT: addi a1, a1, 16
; CHECK-RV64VC-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a6, a1, 4
+; CHECK-RV64VC-NEXT: slli a5, a1, 4
; CHECK-RV64VC-NEXT: slli a2, a1, 1
-; CHECK-RV64VC-NEXT: slli a5, a1, 3
+; CHECK-RV64VC-NEXT: slli a6, a1, 3
; CHECK-RV64VC-NEXT: mv a4, a3
; CHECK-RV64VC-NEXT: bltu a3, a2, .LBB858_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, a2
; CHECK-RV64VC-NEXT: .LBB858_2:
; CHECK-RV64VC-NEXT: vl8re64.v v0, (a0)
-; CHECK-RV64VC-NEXT: add a6, a6, a0
; CHECK-RV64VC-NEXT: add a5, a5, a0
+; CHECK-RV64VC-NEXT: add a6, a6, a0
; CHECK-RV64VC-NEXT: mv a0, a4
; CHECK-RV64VC-NEXT: bltu a4, a1, .LBB858_4
; CHECK-RV64VC-NEXT: # %bb.3:
; CHECK-RV64VC-NEXT: mv a0, a1
; CHECK-RV64VC-NEXT: .LBB858_4:
-; CHECK-RV64VC-NEXT: vl8re64.v v8, (a6)
-; CHECK-RV64VC-NEXT: addi a6, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; CHECK-RV64VC-NEXT: vl8re64.v v24, (a5)
+; CHECK-RV64VC-NEXT: vl8re64.v v8, (a5)
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v24, (a6)
; CHECK-RV64VC-NEXT: csrr a5, vlenb
; CHECK-RV64VC-NEXT: slli a5, a5, 4
; CHECK-RV64VC-NEXT: add a5, a5, sp
@@ -31265,26 +31265,26 @@ define void @test_nontemporal_vp_scatter_nxv32i8_DEFAULT(<vscale x 32 x i8> %val
; CHECK-RV64VC-NEXT: addi a1, a1, 16
; CHECK-RV64VC-NEXT: vs4r.v v8, (a1) # vscale x 32-byte Folded Spill
; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a6, a1, 4
+; CHECK-RV64VC-NEXT: slli a5, a1, 4
; CHECK-RV64VC-NEXT: slli a2, a1, 1
-; CHECK-RV64VC-NEXT: slli a5, a1, 3
+; CHECK-RV64VC-NEXT: slli a6, a1, 3
; CHECK-RV64VC-NEXT: mv a4, a3
; CHECK-RV64VC-NEXT: bltu a3, a2, .LBB859_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, a2
; CHECK-RV64VC-NEXT: .LBB859_2:
; CHECK-RV64VC-NEXT: vl8re64.v v0, (a0)
-; CHECK-RV64VC-NEXT: add a6, a6, a0
; CHECK-RV64VC-NEXT: add a5, a5, a0
+; CHECK-RV64VC-NEXT: add a6, a6, a0
; CHECK-RV64VC-NEXT: mv a0, a4
; CHECK-RV64VC-NEXT: bltu a4, a1, .LBB859_4
; CHECK-RV64VC-NEXT: # %bb.3:
; CHECK-RV64VC-NEXT: mv a0, a1
; CHECK-RV64VC-NEXT: .LBB859_4:
-; CHECK-RV64VC-NEXT: vl8re64.v v8, (a6)
-; CHECK-RV64VC-NEXT: addi a6, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v8, (a6) # vscale x 64-byte Folded Spill
-; CHECK-RV64VC-NEXT: vl8re64.v v24, (a5)
+; CHECK-RV64VC-NEXT: vl8re64.v v8, (a5)
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v8, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v24, (a6)
; CHECK-RV64VC-NEXT: csrr a5, vlenb
; CHECK-RV64VC-NEXT: slli a5, a5, 4
; CHECK-RV64VC-NEXT: add a5, a5, sp
@@ -32119,17 +32119,17 @@ define <vscale x 32 x i16> @test_nontemporal_vp_gather_nxv32i16_P1(<vscale x 32
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a0)
; CHECK-RV64VC-NEXT: slli a4, a1, 3
; CHECK-RV64VC-NEXT: slli a3, a1, 1
-; CHECK-RV64VC-NEXT: add a6, a0, a4
+; CHECK-RV64VC-NEXT: add a4, a4, a0
; CHECK-RV64VC-NEXT: sub a0, a2, a3
; CHECK-RV64VC-NEXT: sltu a5, a2, a0
; CHECK-RV64VC-NEXT: addi a5, a5, -1
; CHECK-RV64VC-NEXT: and a0, a0, a5
; CHECK-RV64VC-NEXT: sub a5, a0, a1
-; CHECK-RV64VC-NEXT: sltu a4, a0, a5
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a5
-; CHECK-RV64VC-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v0, (a6)
+; CHECK-RV64VC-NEXT: sltu a6, a0, a5
+; CHECK-RV64VC-NEXT: addi a6, a6, -1
+; CHECK-RV64VC-NEXT: and a5, a6, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-RV64VC-NEXT: vle64.v v0, (a4)
; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB880_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a0, a1
@@ -32294,17 +32294,17 @@ define <vscale x 32 x i16> @test_nontemporal_vp_gather_nxv32i16_PALL(<vscale x 3
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a0)
; CHECK-RV64VC-NEXT: slli a4, a1, 3
; CHECK-RV64VC-NEXT: slli a3, a1, 1
-; CHECK-RV64VC-NEXT: add a6, a0, a4
+; CHECK-RV64VC-NEXT: add a4, a4, a0
; CHECK-RV64VC-NEXT: sub a0, a2, a3
; CHECK-RV64VC-NEXT: sltu a5, a2, a0
; CHECK-RV64VC-NEXT: addi a5, a5, -1
; CHECK-RV64VC-NEXT: and a0, a0, a5
; CHECK-RV64VC-NEXT: sub a5, a0, a1
-; CHECK-RV64VC-NEXT: sltu a4, a0, a5
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a5
-; CHECK-RV64VC-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v0, (a6)
+; CHECK-RV64VC-NEXT: sltu a6, a0, a5
+; CHECK-RV64VC-NEXT: addi a6, a6, -1
+; CHECK-RV64VC-NEXT: and a5, a6, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-RV64VC-NEXT: vle64.v v0, (a4)
; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB881_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a0, a1
@@ -32469,17 +32469,17 @@ define <vscale x 32 x i16> @test_nontemporal_vp_gather_nxv32i16_S1(<vscale x 32
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a0)
; CHECK-RV64VC-NEXT: slli a4, a1, 3
; CHECK-RV64VC-NEXT: slli a3, a1, 1
-; CHECK-RV64VC-NEXT: add a6, a0, a4
+; CHECK-RV64VC-NEXT: add a4, a4, a0
; CHECK-RV64VC-NEXT: sub a0, a2, a3
; CHECK-RV64VC-NEXT: sltu a5, a2, a0
; CHECK-RV64VC-NEXT: addi a5, a5, -1
; CHECK-RV64VC-NEXT: and a0, a0, a5
; CHECK-RV64VC-NEXT: sub a5, a0, a1
-; CHECK-RV64VC-NEXT: sltu a4, a0, a5
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a5
-; CHECK-RV64VC-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v0, (a6)
+; CHECK-RV64VC-NEXT: sltu a6, a0, a5
+; CHECK-RV64VC-NEXT: addi a6, a6, -1
+; CHECK-RV64VC-NEXT: and a5, a6, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-RV64VC-NEXT: vle64.v v0, (a4)
; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB882_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a0, a1
@@ -32644,17 +32644,17 @@ define <vscale x 32 x i16> @test_nontemporal_vp_gather_nxv32i16_ALL(<vscale x 32
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a0)
; CHECK-RV64VC-NEXT: slli a4, a1, 3
; CHECK-RV64VC-NEXT: slli a3, a1, 1
-; CHECK-RV64VC-NEXT: add a6, a0, a4
+; CHECK-RV64VC-NEXT: add a4, a4, a0
; CHECK-RV64VC-NEXT: sub a0, a2, a3
; CHECK-RV64VC-NEXT: sltu a5, a2, a0
; CHECK-RV64VC-NEXT: addi a5, a5, -1
; CHECK-RV64VC-NEXT: and a0, a0, a5
; CHECK-RV64VC-NEXT: sub a5, a0, a1
-; CHECK-RV64VC-NEXT: sltu a4, a0, a5
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a5
-; CHECK-RV64VC-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v0, (a6)
+; CHECK-RV64VC-NEXT: sltu a6, a0, a5
+; CHECK-RV64VC-NEXT: addi a6, a6, -1
+; CHECK-RV64VC-NEXT: and a5, a6, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-RV64VC-NEXT: vle64.v v0, (a4)
; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB883_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a0, a1
@@ -32818,17 +32818,17 @@ define <vscale x 32 x i16> @test_nontemporal_vp_gather_nxv32i16_DEFAULT(<vscale
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a0)
; CHECK-RV64VC-NEXT: slli a4, a1, 3
; CHECK-RV64VC-NEXT: slli a3, a1, 1
-; CHECK-RV64VC-NEXT: add a6, a0, a4
+; CHECK-RV64VC-NEXT: add a4, a4, a0
; CHECK-RV64VC-NEXT: sub a0, a2, a3
; CHECK-RV64VC-NEXT: sltu a5, a2, a0
; CHECK-RV64VC-NEXT: addi a5, a5, -1
; CHECK-RV64VC-NEXT: and a0, a0, a5
; CHECK-RV64VC-NEXT: sub a5, a0, a1
-; CHECK-RV64VC-NEXT: sltu a4, a0, a5
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a5
-; CHECK-RV64VC-NEXT: vsetvli zero, a4, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v0, (a6)
+; CHECK-RV64VC-NEXT: sltu a6, a0, a5
+; CHECK-RV64VC-NEXT: addi a6, a6, -1
+; CHECK-RV64VC-NEXT: and a5, a6, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a5, e64, m8, ta, ma
+; CHECK-RV64VC-NEXT: vle64.v v0, (a4)
; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB884_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a0, a1
@@ -32987,21 +32987,21 @@ define void @test_nontemporal_vp_scatter_nxv32i16_P1(<vscale x 32 x i16> %val, <
; CHECK-RV64VC-LABEL: test_nontemporal_vp_scatter_nxv32i16_P1:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a6, a1, 4
+; CHECK-RV64VC-NEXT: slli a5, a1, 4
; CHECK-RV64VC-NEXT: slli a2, a1, 1
-; CHECK-RV64VC-NEXT: slli a5, a1, 3
+; CHECK-RV64VC-NEXT: slli a6, a1, 3
; CHECK-RV64VC-NEXT: mv a4, a3
; CHECK-RV64VC-NEXT: bltu a3, a2, .LBB885_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, a2
; CHECK-RV64VC-NEXT: .LBB885_2:
; CHECK-RV64VC-NEXT: vl8re64.v v0, (a0)
-; CHECK-RV64VC-NEXT: add a6, a6, a0
-; CHECK-RV64VC-NEXT: add a0, a0, a5
-; CHECK-RV64VC-NEXT: mv a5, a4
+; CHECK-RV64VC-NEXT: add a5, a5, a0
+; CHECK-RV64VC-NEXT: add a0, a0, a6
+; CHECK-RV64VC-NEXT: mv a6, a4
; CHECK-RV64VC-NEXT: bltu a4, a1, .LBB885_4
; CHECK-RV64VC-NEXT: # %bb.3:
-; CHECK-RV64VC-NEXT: mv a5, a1
+; CHECK-RV64VC-NEXT: mv a6, a1
; CHECK-RV64VC-NEXT: .LBB885_4:
; CHECK-RV64VC-NEXT: addi sp, sp, -16
; CHECK-RV64VC-NEXT: .cfi_def_cfa_offset 16
@@ -33009,11 +33009,11 @@ define void @test_nontemporal_vp_scatter_nxv32i16_P1(<vscale x 32 x i16> %val, <
; CHECK-RV64VC-NEXT: slli a7, a7, 3
; CHECK-RV64VC-NEXT: sub sp, sp, a7
; CHECK-RV64VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-RV64VC-NEXT: vl8re64.v v24, (a6)
-; CHECK-RV64VC-NEXT: addi a6, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v24, (a5)
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: vl8re64.v v24, (a0)
-; CHECK-RV64VC-NEXT: vsetvli zero, a5, e16, m2, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a6, e16, m2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
; CHECK-RV64VC-NEXT: vsoxei64.v v8, (zero), v16
; CHECK-RV64VC-NEXT: sub a0, a4, a1
@@ -33172,21 +33172,21 @@ define void @test_nontemporal_vp_scatter_nxv32i16_PALL(<vscale x 32 x i16> %val,
; CHECK-RV64VC-LABEL: test_nontemporal_vp_scatter_nxv32i16_PALL:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a6, a1, 4
+; CHECK-RV64VC-NEXT: slli a5, a1, 4
; CHECK-RV64VC-NEXT: slli a2, a1, 1
-; CHECK-RV64VC-NEXT: slli a5, a1, 3
+; CHECK-RV64VC-NEXT: slli a6, a1, 3
; CHECK-RV64VC-NEXT: mv a4, a3
; CHECK-RV64VC-NEXT: bltu a3, a2, .LBB886_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, a2
; CHECK-RV64VC-NEXT: .LBB886_2:
; CHECK-RV64VC-NEXT: vl8re64.v v0, (a0)
-; CHECK-RV64VC-NEXT: add a6, a6, a0
-; CHECK-RV64VC-NEXT: add a0, a0, a5
-; CHECK-RV64VC-NEXT: mv a5, a4
+; CHECK-RV64VC-NEXT: add a5, a5, a0
+; CHECK-RV64VC-NEXT: add a0, a0, a6
+; CHECK-RV64VC-NEXT: mv a6, a4
; CHECK-RV64VC-NEXT: bltu a4, a1, .LBB886_4
; CHECK-RV64VC-NEXT: # %bb.3:
-; CHECK-RV64VC-NEXT: mv a5, a1
+; CHECK-RV64VC-NEXT: mv a6, a1
; CHECK-RV64VC-NEXT: .LBB886_4:
; CHECK-RV64VC-NEXT: addi sp, sp, -16
; CHECK-RV64VC-NEXT: .cfi_def_cfa_offset 16
@@ -33194,11 +33194,11 @@ define void @test_nontemporal_vp_scatter_nxv32i16_PALL(<vscale x 32 x i16> %val,
; CHECK-RV64VC-NEXT: slli a7, a7, 3
; CHECK-RV64VC-NEXT: sub sp, sp, a7
; CHECK-RV64VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-RV64VC-NEXT: vl8re64.v v24, (a6)
-; CHECK-RV64VC-NEXT: addi a6, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v24, (a5)
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: vl8re64.v v24, (a0)
-; CHECK-RV64VC-NEXT: vsetvli zero, a5, e16, m2, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a6, e16, m2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
; CHECK-RV64VC-NEXT: vsoxei64.v v8, (zero), v16
; CHECK-RV64VC-NEXT: sub a0, a4, a1
@@ -33357,21 +33357,21 @@ define void @test_nontemporal_vp_scatter_nxv32i16_S1(<vscale x 32 x i16> %val, <
; CHECK-RV64VC-LABEL: test_nontemporal_vp_scatter_nxv32i16_S1:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a6, a1, 4
+; CHECK-RV64VC-NEXT: slli a5, a1, 4
; CHECK-RV64VC-NEXT: slli a2, a1, 1
-; CHECK-RV64VC-NEXT: slli a5, a1, 3
+; CHECK-RV64VC-NEXT: slli a6, a1, 3
; CHECK-RV64VC-NEXT: mv a4, a3
; CHECK-RV64VC-NEXT: bltu a3, a2, .LBB887_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, a2
; CHECK-RV64VC-NEXT: .LBB887_2:
; CHECK-RV64VC-NEXT: vl8re64.v v0, (a0)
-; CHECK-RV64VC-NEXT: add a6, a6, a0
-; CHECK-RV64VC-NEXT: add a0, a0, a5
-; CHECK-RV64VC-NEXT: mv a5, a4
+; CHECK-RV64VC-NEXT: add a5, a5, a0
+; CHECK-RV64VC-NEXT: add a0, a0, a6
+; CHECK-RV64VC-NEXT: mv a6, a4
; CHECK-RV64VC-NEXT: bltu a4, a1, .LBB887_4
; CHECK-RV64VC-NEXT: # %bb.3:
-; CHECK-RV64VC-NEXT: mv a5, a1
+; CHECK-RV64VC-NEXT: mv a6, a1
; CHECK-RV64VC-NEXT: .LBB887_4:
; CHECK-RV64VC-NEXT: addi sp, sp, -16
; CHECK-RV64VC-NEXT: .cfi_def_cfa_offset 16
@@ -33379,11 +33379,11 @@ define void @test_nontemporal_vp_scatter_nxv32i16_S1(<vscale x 32 x i16> %val, <
; CHECK-RV64VC-NEXT: slli a7, a7, 3
; CHECK-RV64VC-NEXT: sub sp, sp, a7
; CHECK-RV64VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-RV64VC-NEXT: vl8re64.v v24, (a6)
-; CHECK-RV64VC-NEXT: addi a6, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v24, (a5)
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: vl8re64.v v24, (a0)
-; CHECK-RV64VC-NEXT: vsetvli zero, a5, e16, m2, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a6, e16, m2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
; CHECK-RV64VC-NEXT: vsoxei64.v v8, (zero), v16
; CHECK-RV64VC-NEXT: sub a0, a4, a1
@@ -33542,21 +33542,21 @@ define void @test_nontemporal_vp_scatter_nxv32i16_ALL(<vscale x 32 x i16> %val,
; CHECK-RV64VC-LABEL: test_nontemporal_vp_scatter_nxv32i16_ALL:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a6, a1, 4
+; CHECK-RV64VC-NEXT: slli a5, a1, 4
; CHECK-RV64VC-NEXT: slli a2, a1, 1
-; CHECK-RV64VC-NEXT: slli a5, a1, 3
+; CHECK-RV64VC-NEXT: slli a6, a1, 3
; CHECK-RV64VC-NEXT: mv a4, a3
; CHECK-RV64VC-NEXT: bltu a3, a2, .LBB888_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, a2
; CHECK-RV64VC-NEXT: .LBB888_2:
; CHECK-RV64VC-NEXT: vl8re64.v v0, (a0)
-; CHECK-RV64VC-NEXT: add a6, a6, a0
-; CHECK-RV64VC-NEXT: add a0, a0, a5
-; CHECK-RV64VC-NEXT: mv a5, a4
+; CHECK-RV64VC-NEXT: add a5, a5, a0
+; CHECK-RV64VC-NEXT: add a0, a0, a6
+; CHECK-RV64VC-NEXT: mv a6, a4
; CHECK-RV64VC-NEXT: bltu a4, a1, .LBB888_4
; CHECK-RV64VC-NEXT: # %bb.3:
-; CHECK-RV64VC-NEXT: mv a5, a1
+; CHECK-RV64VC-NEXT: mv a6, a1
; CHECK-RV64VC-NEXT: .LBB888_4:
; CHECK-RV64VC-NEXT: addi sp, sp, -16
; CHECK-RV64VC-NEXT: .cfi_def_cfa_offset 16
@@ -33564,11 +33564,11 @@ define void @test_nontemporal_vp_scatter_nxv32i16_ALL(<vscale x 32 x i16> %val,
; CHECK-RV64VC-NEXT: slli a7, a7, 3
; CHECK-RV64VC-NEXT: sub sp, sp, a7
; CHECK-RV64VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-RV64VC-NEXT: vl8re64.v v24, (a6)
-; CHECK-RV64VC-NEXT: addi a6, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v24, (a5)
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: vl8re64.v v24, (a0)
-; CHECK-RV64VC-NEXT: vsetvli zero, a5, e16, m2, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a6, e16, m2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v8, (zero), v16
; CHECK-RV64VC-NEXT: sub a0, a4, a1
@@ -33726,21 +33726,21 @@ define void @test_nontemporal_vp_scatter_nxv32i16_DEFAULT(<vscale x 32 x i16> %v
; CHECK-RV64VC-LABEL: test_nontemporal_vp_scatter_nxv32i16_DEFAULT:
; CHECK-RV64VC: # %bb.0:
; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a6, a1, 4
+; CHECK-RV64VC-NEXT: slli a5, a1, 4
; CHECK-RV64VC-NEXT: slli a2, a1, 1
-; CHECK-RV64VC-NEXT: slli a5, a1, 3
+; CHECK-RV64VC-NEXT: slli a6, a1, 3
; CHECK-RV64VC-NEXT: mv a4, a3
; CHECK-RV64VC-NEXT: bltu a3, a2, .LBB889_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, a2
; CHECK-RV64VC-NEXT: .LBB889_2:
; CHECK-RV64VC-NEXT: vl8re64.v v0, (a0)
-; CHECK-RV64VC-NEXT: add a6, a6, a0
-; CHECK-RV64VC-NEXT: add a0, a0, a5
-; CHECK-RV64VC-NEXT: mv a5, a4
+; CHECK-RV64VC-NEXT: add a5, a5, a0
+; CHECK-RV64VC-NEXT: add a0, a0, a6
+; CHECK-RV64VC-NEXT: mv a6, a4
; CHECK-RV64VC-NEXT: bltu a4, a1, .LBB889_4
; CHECK-RV64VC-NEXT: # %bb.3:
-; CHECK-RV64VC-NEXT: mv a5, a1
+; CHECK-RV64VC-NEXT: mv a6, a1
; CHECK-RV64VC-NEXT: .LBB889_4:
; CHECK-RV64VC-NEXT: addi sp, sp, -16
; CHECK-RV64VC-NEXT: .cfi_def_cfa_offset 16
@@ -33748,11 +33748,11 @@ define void @test_nontemporal_vp_scatter_nxv32i16_DEFAULT(<vscale x 32 x i16> %v
; CHECK-RV64VC-NEXT: slli a7, a7, 3
; CHECK-RV64VC-NEXT: sub sp, sp, a7
; CHECK-RV64VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-RV64VC-NEXT: vl8re64.v v24, (a6)
-; CHECK-RV64VC-NEXT: addi a6, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v24, (a5)
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: vl8re64.v v24, (a0)
-; CHECK-RV64VC-NEXT: vsetvli zero, a5, e16, m2, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a6, e16, m2, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v8, (zero), v16
; CHECK-RV64VC-NEXT: sub a0, a4, a1
@@ -34821,63 +34821,63 @@ define <vscale x 64 x i8> @test_nontemporal_vp_gather_nxv64i8_P1(<vscale x 64 x
; CHECK-RV64VC-NEXT: li a1, 40
; CHECK-RV64VC-NEXT: mv a0, s1
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: slli a6, s1, 2
-; CHECK-RV64VC-NEXT: sub a1, s0, a6
-; CHECK-RV64VC-NEXT: sltu a2, s0, a1
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
-; CHECK-RV64VC-NEXT: and a3, a2, a1
+; CHECK-RV64VC-NEXT: slli a2, s1, 2
+; CHECK-RV64VC-NEXT: sub a1, s0, a2
+; CHECK-RV64VC-NEXT: sltu a3, s0, a1
+; CHECK-RV64VC-NEXT: addi a3, a3, -1
+; CHECK-RV64VC-NEXT: and a3, a3, a1
; CHECK-RV64VC-NEXT: slli a1, s1, 1
-; CHECK-RV64VC-NEXT: sub a2, a3, a1
-; CHECK-RV64VC-NEXT: sltu a4, a3, a2
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a2
+; CHECK-RV64VC-NEXT: sub a4, a3, a1
+; CHECK-RV64VC-NEXT: sltu a5, a3, a4
+; CHECK-RV64VC-NEXT: addi a5, a5, -1
+; CHECK-RV64VC-NEXT: and a4, a4, a5
; CHECK-RV64VC-NEXT: sub a5, a4, s1
-; CHECK-RV64VC-NEXT: sltu a2, a4, a5
+; CHECK-RV64VC-NEXT: sltu a7, a4, a5
; CHECK-RV64VC-NEXT: bltu a4, s1, .LBB910_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, s1
; CHECK-RV64VC-NEXT: .LBB910_2:
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
+; CHECK-RV64VC-NEXT: addi a7, a7, -1
; CHECK-RV64VC-NEXT: bltu a3, a1, .LBB910_4
; CHECK-RV64VC-NEXT: # %bb.3:
; CHECK-RV64VC-NEXT: mv a3, a1
; CHECK-RV64VC-NEXT: .LBB910_4:
-; CHECK-RV64VC-NEXT: add a7, s2, a0
-; CHECK-RV64VC-NEXT: and a0, a2, a5
-; CHECK-RV64VC-NEXT: sub a2, a3, s1
-; CHECK-RV64VC-NEXT: sltu a5, a3, a2
-; CHECK-RV64VC-NEXT: addi a5, a5, -1
-; CHECK-RV64VC-NEXT: and a5, a5, a2
+; CHECK-RV64VC-NEXT: add a6, s2, a0
+; CHECK-RV64VC-NEXT: and a0, a7, a5
+; CHECK-RV64VC-NEXT: sub a5, a3, s1
+; CHECK-RV64VC-NEXT: sltu a7, a3, a5
+; CHECK-RV64VC-NEXT: addi a7, a7, -1
+; CHECK-RV64VC-NEXT: and a5, a7, a5
; CHECK-RV64VC-NEXT: bltu a3, s1, .LBB910_6
; CHECK-RV64VC-NEXT: # %bb.5:
; CHECK-RV64VC-NEXT: mv a3, s1
; CHECK-RV64VC-NEXT: .LBB910_6:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v16, (a7)
-; CHECK-RV64VC-NEXT: addi a2, sp, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vle64.v v16, (a6)
+; CHECK-RV64VC-NEXT: addi a6, sp, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a6) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
; CHECK-RV64VC-NEXT: vluxei64.v v14, (zero), v24
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 3
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 3
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a5, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
; CHECK-RV64VC-NEXT: vluxei64.v v13, (zero), v24
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 4
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 4
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
; CHECK-RV64VC-NEXT: vluxei64.v v12, (zero), v24
-; CHECK-RV64VC-NEXT: bltu s0, a6, .LBB910_8
+; CHECK-RV64VC-NEXT: bltu s0, a2, .LBB910_8
; CHECK-RV64VC-NEXT: # %bb.7:
-; CHECK-RV64VC-NEXT: mv s0, a6
+; CHECK-RV64VC-NEXT: mv s0, a2
; CHECK-RV64VC-NEXT: .LBB910_8:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
@@ -34973,18 +34973,18 @@ define <vscale x 64 x i8> @test_nontemporal_vp_gather_nxv64i8_P1(<vscale x 64 x
; CHECK-RV32VC-NEXT: vl8re32.v v16, (a0)
; CHECK-RV32VC-NEXT: slli a3, a4, 3
; CHECK-RV32VC-NEXT: slli a1, a4, 2
-; CHECK-RV32VC-NEXT: add a6, a0, a3
+; CHECK-RV32VC-NEXT: add a5, a0, a3
; CHECK-RV32VC-NEXT: sub a0, a2, a1
; CHECK-RV32VC-NEXT: sltu a3, a2, a0
; CHECK-RV32VC-NEXT: addi a3, a3, -1
; CHECK-RV32VC-NEXT: and a3, a3, a0
; CHECK-RV32VC-NEXT: slli a0, a4, 1
; CHECK-RV32VC-NEXT: sub a4, a3, a0
-; CHECK-RV32VC-NEXT: sltu a5, a3, a4
-; CHECK-RV32VC-NEXT: addi a5, a5, -1
-; CHECK-RV32VC-NEXT: and a4, a4, a5
+; CHECK-RV32VC-NEXT: sltu a6, a3, a4
+; CHECK-RV32VC-NEXT: addi a6, a6, -1
+; CHECK-RV32VC-NEXT: and a4, a6, a4
; CHECK-RV32VC-NEXT: vsetvli zero, a4, e32, m8, ta, ma
-; CHECK-RV32VC-NEXT: vle32.v v0, (a6)
+; CHECK-RV32VC-NEXT: vle32.v v0, (a5)
; CHECK-RV32VC-NEXT: bltu a3, a0, .LBB910_2
; CHECK-RV32VC-NEXT: # %bb.1:
; CHECK-RV32VC-NEXT: mv a3, a0
@@ -35376,63 +35376,63 @@ define <vscale x 64 x i8> @test_nontemporal_vp_gather_nxv64i8_PALL(<vscale x 64
; CHECK-RV64VC-NEXT: li a1, 40
; CHECK-RV64VC-NEXT: mv a0, s1
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: slli a6, s1, 2
-; CHECK-RV64VC-NEXT: sub a1, s0, a6
-; CHECK-RV64VC-NEXT: sltu a2, s0, a1
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
-; CHECK-RV64VC-NEXT: and a3, a2, a1
+; CHECK-RV64VC-NEXT: slli a2, s1, 2
+; CHECK-RV64VC-NEXT: sub a1, s0, a2
+; CHECK-RV64VC-NEXT: sltu a3, s0, a1
+; CHECK-RV64VC-NEXT: addi a3, a3, -1
+; CHECK-RV64VC-NEXT: and a3, a3, a1
; CHECK-RV64VC-NEXT: slli a1, s1, 1
-; CHECK-RV64VC-NEXT: sub a2, a3, a1
-; CHECK-RV64VC-NEXT: sltu a4, a3, a2
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a2
+; CHECK-RV64VC-NEXT: sub a4, a3, a1
+; CHECK-RV64VC-NEXT: sltu a5, a3, a4
+; CHECK-RV64VC-NEXT: addi a5, a5, -1
+; CHECK-RV64VC-NEXT: and a4, a4, a5
; CHECK-RV64VC-NEXT: sub a5, a4, s1
-; CHECK-RV64VC-NEXT: sltu a2, a4, a5
+; CHECK-RV64VC-NEXT: sltu a7, a4, a5
; CHECK-RV64VC-NEXT: bltu a4, s1, .LBB911_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, s1
; CHECK-RV64VC-NEXT: .LBB911_2:
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
+; CHECK-RV64VC-NEXT: addi a7, a7, -1
; CHECK-RV64VC-NEXT: bltu a3, a1, .LBB911_4
; CHECK-RV64VC-NEXT: # %bb.3:
; CHECK-RV64VC-NEXT: mv a3, a1
; CHECK-RV64VC-NEXT: .LBB911_4:
-; CHECK-RV64VC-NEXT: add a7, s2, a0
-; CHECK-RV64VC-NEXT: and a0, a2, a5
-; CHECK-RV64VC-NEXT: sub a2, a3, s1
-; CHECK-RV64VC-NEXT: sltu a5, a3, a2
-; CHECK-RV64VC-NEXT: addi a5, a5, -1
-; CHECK-RV64VC-NEXT: and a5, a5, a2
+; CHECK-RV64VC-NEXT: add a6, s2, a0
+; CHECK-RV64VC-NEXT: and a0, a7, a5
+; CHECK-RV64VC-NEXT: sub a5, a3, s1
+; CHECK-RV64VC-NEXT: sltu a7, a3, a5
+; CHECK-RV64VC-NEXT: addi a7, a7, -1
+; CHECK-RV64VC-NEXT: and a5, a7, a5
; CHECK-RV64VC-NEXT: bltu a3, s1, .LBB911_6
; CHECK-RV64VC-NEXT: # %bb.5:
; CHECK-RV64VC-NEXT: mv a3, s1
; CHECK-RV64VC-NEXT: .LBB911_6:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v16, (a7)
-; CHECK-RV64VC-NEXT: addi a2, sp, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vle64.v v16, (a6)
+; CHECK-RV64VC-NEXT: addi a6, sp, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a6) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
; CHECK-RV64VC-NEXT: vluxei64.v v14, (zero), v24
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 3
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 3
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a5, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
; CHECK-RV64VC-NEXT: vluxei64.v v13, (zero), v24
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 4
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 4
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
; CHECK-RV64VC-NEXT: vluxei64.v v12, (zero), v24
-; CHECK-RV64VC-NEXT: bltu s0, a6, .LBB911_8
+; CHECK-RV64VC-NEXT: bltu s0, a2, .LBB911_8
; CHECK-RV64VC-NEXT: # %bb.7:
-; CHECK-RV64VC-NEXT: mv s0, a6
+; CHECK-RV64VC-NEXT: mv s0, a2
; CHECK-RV64VC-NEXT: .LBB911_8:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
@@ -35528,18 +35528,18 @@ define <vscale x 64 x i8> @test_nontemporal_vp_gather_nxv64i8_PALL(<vscale x 64
; CHECK-RV32VC-NEXT: vl8re32.v v16, (a0)
; CHECK-RV32VC-NEXT: slli a3, a4, 3
; CHECK-RV32VC-NEXT: slli a1, a4, 2
-; CHECK-RV32VC-NEXT: add a6, a0, a3
+; CHECK-RV32VC-NEXT: add a5, a0, a3
; CHECK-RV32VC-NEXT: sub a0, a2, a1
; CHECK-RV32VC-NEXT: sltu a3, a2, a0
; CHECK-RV32VC-NEXT: addi a3, a3, -1
; CHECK-RV32VC-NEXT: and a3, a3, a0
; CHECK-RV32VC-NEXT: slli a0, a4, 1
; CHECK-RV32VC-NEXT: sub a4, a3, a0
-; CHECK-RV32VC-NEXT: sltu a5, a3, a4
-; CHECK-RV32VC-NEXT: addi a5, a5, -1
-; CHECK-RV32VC-NEXT: and a4, a4, a5
+; CHECK-RV32VC-NEXT: sltu a6, a3, a4
+; CHECK-RV32VC-NEXT: addi a6, a6, -1
+; CHECK-RV32VC-NEXT: and a4, a6, a4
; CHECK-RV32VC-NEXT: vsetvli zero, a4, e32, m8, ta, ma
-; CHECK-RV32VC-NEXT: vle32.v v0, (a6)
+; CHECK-RV32VC-NEXT: vle32.v v0, (a5)
; CHECK-RV32VC-NEXT: bltu a3, a0, .LBB911_2
; CHECK-RV32VC-NEXT: # %bb.1:
; CHECK-RV32VC-NEXT: mv a3, a0
@@ -35931,63 +35931,63 @@ define <vscale x 64 x i8> @test_nontemporal_vp_gather_nxv64i8_S1(<vscale x 64 x
; CHECK-RV64VC-NEXT: li a1, 40
; CHECK-RV64VC-NEXT: mv a0, s1
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: slli a6, s1, 2
-; CHECK-RV64VC-NEXT: sub a1, s0, a6
-; CHECK-RV64VC-NEXT: sltu a2, s0, a1
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
-; CHECK-RV64VC-NEXT: and a3, a2, a1
+; CHECK-RV64VC-NEXT: slli a2, s1, 2
+; CHECK-RV64VC-NEXT: sub a1, s0, a2
+; CHECK-RV64VC-NEXT: sltu a3, s0, a1
+; CHECK-RV64VC-NEXT: addi a3, a3, -1
+; CHECK-RV64VC-NEXT: and a3, a3, a1
; CHECK-RV64VC-NEXT: slli a1, s1, 1
-; CHECK-RV64VC-NEXT: sub a2, a3, a1
-; CHECK-RV64VC-NEXT: sltu a4, a3, a2
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a2
+; CHECK-RV64VC-NEXT: sub a4, a3, a1
+; CHECK-RV64VC-NEXT: sltu a5, a3, a4
+; CHECK-RV64VC-NEXT: addi a5, a5, -1
+; CHECK-RV64VC-NEXT: and a4, a4, a5
; CHECK-RV64VC-NEXT: sub a5, a4, s1
-; CHECK-RV64VC-NEXT: sltu a2, a4, a5
+; CHECK-RV64VC-NEXT: sltu a7, a4, a5
; CHECK-RV64VC-NEXT: bltu a4, s1, .LBB912_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, s1
; CHECK-RV64VC-NEXT: .LBB912_2:
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
+; CHECK-RV64VC-NEXT: addi a7, a7, -1
; CHECK-RV64VC-NEXT: bltu a3, a1, .LBB912_4
; CHECK-RV64VC-NEXT: # %bb.3:
; CHECK-RV64VC-NEXT: mv a3, a1
; CHECK-RV64VC-NEXT: .LBB912_4:
-; CHECK-RV64VC-NEXT: add a7, s2, a0
-; CHECK-RV64VC-NEXT: and a0, a2, a5
-; CHECK-RV64VC-NEXT: sub a2, a3, s1
-; CHECK-RV64VC-NEXT: sltu a5, a3, a2
-; CHECK-RV64VC-NEXT: addi a5, a5, -1
-; CHECK-RV64VC-NEXT: and a5, a5, a2
+; CHECK-RV64VC-NEXT: add a6, s2, a0
+; CHECK-RV64VC-NEXT: and a0, a7, a5
+; CHECK-RV64VC-NEXT: sub a5, a3, s1
+; CHECK-RV64VC-NEXT: sltu a7, a3, a5
+; CHECK-RV64VC-NEXT: addi a7, a7, -1
+; CHECK-RV64VC-NEXT: and a5, a7, a5
; CHECK-RV64VC-NEXT: bltu a3, s1, .LBB912_6
; CHECK-RV64VC-NEXT: # %bb.5:
; CHECK-RV64VC-NEXT: mv a3, s1
; CHECK-RV64VC-NEXT: .LBB912_6:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v16, (a7)
-; CHECK-RV64VC-NEXT: addi a2, sp, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vle64.v v16, (a6)
+; CHECK-RV64VC-NEXT: addi a6, sp, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a6) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
; CHECK-RV64VC-NEXT: vluxei64.v v14, (zero), v24
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 3
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 3
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a5, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
; CHECK-RV64VC-NEXT: vluxei64.v v13, (zero), v24
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 4
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 4
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
; CHECK-RV64VC-NEXT: vluxei64.v v12, (zero), v24
-; CHECK-RV64VC-NEXT: bltu s0, a6, .LBB912_8
+; CHECK-RV64VC-NEXT: bltu s0, a2, .LBB912_8
; CHECK-RV64VC-NEXT: # %bb.7:
-; CHECK-RV64VC-NEXT: mv s0, a6
+; CHECK-RV64VC-NEXT: mv s0, a2
; CHECK-RV64VC-NEXT: .LBB912_8:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
@@ -36083,18 +36083,18 @@ define <vscale x 64 x i8> @test_nontemporal_vp_gather_nxv64i8_S1(<vscale x 64 x
; CHECK-RV32VC-NEXT: vl8re32.v v16, (a0)
; CHECK-RV32VC-NEXT: slli a3, a4, 3
; CHECK-RV32VC-NEXT: slli a1, a4, 2
-; CHECK-RV32VC-NEXT: add a6, a0, a3
+; CHECK-RV32VC-NEXT: add a5, a0, a3
; CHECK-RV32VC-NEXT: sub a0, a2, a1
; CHECK-RV32VC-NEXT: sltu a3, a2, a0
; CHECK-RV32VC-NEXT: addi a3, a3, -1
; CHECK-RV32VC-NEXT: and a3, a3, a0
; CHECK-RV32VC-NEXT: slli a0, a4, 1
; CHECK-RV32VC-NEXT: sub a4, a3, a0
-; CHECK-RV32VC-NEXT: sltu a5, a3, a4
-; CHECK-RV32VC-NEXT: addi a5, a5, -1
-; CHECK-RV32VC-NEXT: and a4, a4, a5
+; CHECK-RV32VC-NEXT: sltu a6, a3, a4
+; CHECK-RV32VC-NEXT: addi a6, a6, -1
+; CHECK-RV32VC-NEXT: and a4, a6, a4
; CHECK-RV32VC-NEXT: vsetvli zero, a4, e32, m8, ta, ma
-; CHECK-RV32VC-NEXT: vle32.v v0, (a6)
+; CHECK-RV32VC-NEXT: vle32.v v0, (a5)
; CHECK-RV32VC-NEXT: bltu a3, a0, .LBB912_2
; CHECK-RV32VC-NEXT: # %bb.1:
; CHECK-RV32VC-NEXT: mv a3, a0
@@ -36486,63 +36486,63 @@ define <vscale x 64 x i8> @test_nontemporal_vp_gather_nxv64i8_ALL(<vscale x 64 x
; CHECK-RV64VC-NEXT: li a1, 40
; CHECK-RV64VC-NEXT: mv a0, s1
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: slli a6, s1, 2
-; CHECK-RV64VC-NEXT: sub a1, s0, a6
-; CHECK-RV64VC-NEXT: sltu a2, s0, a1
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
-; CHECK-RV64VC-NEXT: and a3, a2, a1
+; CHECK-RV64VC-NEXT: slli a2, s1, 2
+; CHECK-RV64VC-NEXT: sub a1, s0, a2
+; CHECK-RV64VC-NEXT: sltu a3, s0, a1
+; CHECK-RV64VC-NEXT: addi a3, a3, -1
+; CHECK-RV64VC-NEXT: and a3, a3, a1
; CHECK-RV64VC-NEXT: slli a1, s1, 1
-; CHECK-RV64VC-NEXT: sub a2, a3, a1
-; CHECK-RV64VC-NEXT: sltu a4, a3, a2
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a2
+; CHECK-RV64VC-NEXT: sub a4, a3, a1
+; CHECK-RV64VC-NEXT: sltu a5, a3, a4
+; CHECK-RV64VC-NEXT: addi a5, a5, -1
+; CHECK-RV64VC-NEXT: and a4, a4, a5
; CHECK-RV64VC-NEXT: sub a5, a4, s1
-; CHECK-RV64VC-NEXT: sltu a2, a4, a5
+; CHECK-RV64VC-NEXT: sltu a7, a4, a5
; CHECK-RV64VC-NEXT: bltu a4, s1, .LBB913_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, s1
; CHECK-RV64VC-NEXT: .LBB913_2:
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
+; CHECK-RV64VC-NEXT: addi a7, a7, -1
; CHECK-RV64VC-NEXT: bltu a3, a1, .LBB913_4
; CHECK-RV64VC-NEXT: # %bb.3:
; CHECK-RV64VC-NEXT: mv a3, a1
; CHECK-RV64VC-NEXT: .LBB913_4:
-; CHECK-RV64VC-NEXT: add a7, s2, a0
-; CHECK-RV64VC-NEXT: and a0, a2, a5
-; CHECK-RV64VC-NEXT: sub a2, a3, s1
-; CHECK-RV64VC-NEXT: sltu a5, a3, a2
-; CHECK-RV64VC-NEXT: addi a5, a5, -1
-; CHECK-RV64VC-NEXT: and a5, a5, a2
+; CHECK-RV64VC-NEXT: add a6, s2, a0
+; CHECK-RV64VC-NEXT: and a0, a7, a5
+; CHECK-RV64VC-NEXT: sub a5, a3, s1
+; CHECK-RV64VC-NEXT: sltu a7, a3, a5
+; CHECK-RV64VC-NEXT: addi a7, a7, -1
+; CHECK-RV64VC-NEXT: and a5, a7, a5
; CHECK-RV64VC-NEXT: bltu a3, s1, .LBB913_6
; CHECK-RV64VC-NEXT: # %bb.5:
; CHECK-RV64VC-NEXT: mv a3, s1
; CHECK-RV64VC-NEXT: .LBB913_6:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v16, (a7)
-; CHECK-RV64VC-NEXT: addi a2, sp, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vle64.v v16, (a6)
+; CHECK-RV64VC-NEXT: addi a6, sp, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a6) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vluxei64.v v14, (zero), v24
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 3
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 3
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a5, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vluxei64.v v13, (zero), v24
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 4
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 4
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vluxei64.v v12, (zero), v24
-; CHECK-RV64VC-NEXT: bltu s0, a6, .LBB913_8
+; CHECK-RV64VC-NEXT: bltu s0, a2, .LBB913_8
; CHECK-RV64VC-NEXT: # %bb.7:
-; CHECK-RV64VC-NEXT: mv s0, a6
+; CHECK-RV64VC-NEXT: mv s0, a2
; CHECK-RV64VC-NEXT: .LBB913_8:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
@@ -36638,18 +36638,18 @@ define <vscale x 64 x i8> @test_nontemporal_vp_gather_nxv64i8_ALL(<vscale x 64 x
; CHECK-RV32VC-NEXT: vl8re32.v v16, (a0)
; CHECK-RV32VC-NEXT: slli a3, a4, 3
; CHECK-RV32VC-NEXT: slli a1, a4, 2
-; CHECK-RV32VC-NEXT: add a6, a0, a3
+; CHECK-RV32VC-NEXT: add a5, a0, a3
; CHECK-RV32VC-NEXT: sub a0, a2, a1
; CHECK-RV32VC-NEXT: sltu a3, a2, a0
; CHECK-RV32VC-NEXT: addi a3, a3, -1
; CHECK-RV32VC-NEXT: and a3, a3, a0
; CHECK-RV32VC-NEXT: slli a0, a4, 1
; CHECK-RV32VC-NEXT: sub a4, a3, a0
-; CHECK-RV32VC-NEXT: sltu a5, a3, a4
-; CHECK-RV32VC-NEXT: addi a5, a5, -1
-; CHECK-RV32VC-NEXT: and a4, a4, a5
+; CHECK-RV32VC-NEXT: sltu a6, a3, a4
+; CHECK-RV32VC-NEXT: addi a6, a6, -1
+; CHECK-RV32VC-NEXT: and a4, a6, a4
; CHECK-RV32VC-NEXT: vsetvli zero, a4, e32, m8, ta, ma
-; CHECK-RV32VC-NEXT: vle32.v v0, (a6)
+; CHECK-RV32VC-NEXT: vle32.v v0, (a5)
; CHECK-RV32VC-NEXT: bltu a3, a0, .LBB913_2
; CHECK-RV32VC-NEXT: # %bb.1:
; CHECK-RV32VC-NEXT: mv a3, a0
@@ -37040,63 +37040,63 @@ define <vscale x 64 x i8> @test_nontemporal_vp_gather_nxv64i8_DEFAULT(<vscale x
; CHECK-RV64VC-NEXT: li a1, 40
; CHECK-RV64VC-NEXT: mv a0, s1
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: slli a6, s1, 2
-; CHECK-RV64VC-NEXT: sub a1, s0, a6
-; CHECK-RV64VC-NEXT: sltu a2, s0, a1
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
-; CHECK-RV64VC-NEXT: and a3, a2, a1
+; CHECK-RV64VC-NEXT: slli a2, s1, 2
+; CHECK-RV64VC-NEXT: sub a1, s0, a2
+; CHECK-RV64VC-NEXT: sltu a3, s0, a1
+; CHECK-RV64VC-NEXT: addi a3, a3, -1
+; CHECK-RV64VC-NEXT: and a3, a3, a1
; CHECK-RV64VC-NEXT: slli a1, s1, 1
-; CHECK-RV64VC-NEXT: sub a2, a3, a1
-; CHECK-RV64VC-NEXT: sltu a4, a3, a2
-; CHECK-RV64VC-NEXT: addi a4, a4, -1
-; CHECK-RV64VC-NEXT: and a4, a4, a2
+; CHECK-RV64VC-NEXT: sub a4, a3, a1
+; CHECK-RV64VC-NEXT: sltu a5, a3, a4
+; CHECK-RV64VC-NEXT: addi a5, a5, -1
+; CHECK-RV64VC-NEXT: and a4, a4, a5
; CHECK-RV64VC-NEXT: sub a5, a4, s1
-; CHECK-RV64VC-NEXT: sltu a2, a4, a5
+; CHECK-RV64VC-NEXT: sltu a7, a4, a5
; CHECK-RV64VC-NEXT: bltu a4, s1, .LBB914_2
; CHECK-RV64VC-NEXT: # %bb.1:
; CHECK-RV64VC-NEXT: mv a4, s1
; CHECK-RV64VC-NEXT: .LBB914_2:
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
+; CHECK-RV64VC-NEXT: addi a7, a7, -1
; CHECK-RV64VC-NEXT: bltu a3, a1, .LBB914_4
; CHECK-RV64VC-NEXT: # %bb.3:
; CHECK-RV64VC-NEXT: mv a3, a1
; CHECK-RV64VC-NEXT: .LBB914_4:
-; CHECK-RV64VC-NEXT: add a7, s2, a0
-; CHECK-RV64VC-NEXT: and a0, a2, a5
-; CHECK-RV64VC-NEXT: sub a2, a3, s1
-; CHECK-RV64VC-NEXT: sltu a5, a3, a2
-; CHECK-RV64VC-NEXT: addi a5, a5, -1
-; CHECK-RV64VC-NEXT: and a5, a5, a2
+; CHECK-RV64VC-NEXT: add a6, s2, a0
+; CHECK-RV64VC-NEXT: and a0, a7, a5
+; CHECK-RV64VC-NEXT: sub a5, a3, s1
+; CHECK-RV64VC-NEXT: sltu a7, a3, a5
+; CHECK-RV64VC-NEXT: addi a7, a7, -1
+; CHECK-RV64VC-NEXT: and a5, a7, a5
; CHECK-RV64VC-NEXT: bltu a3, s1, .LBB914_6
; CHECK-RV64VC-NEXT: # %bb.5:
; CHECK-RV64VC-NEXT: mv a3, s1
; CHECK-RV64VC-NEXT: .LBB914_6:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e64, m8, ta, ma
-; CHECK-RV64VC-NEXT: vle64.v v16, (a7)
-; CHECK-RV64VC-NEXT: addi a2, sp, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vle64.v v16, (a6)
+; CHECK-RV64VC-NEXT: addi a6, sp, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a6) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vluxei64.v v14, (zero), v24
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 3
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 3
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a5, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vluxei64.v v13, (zero), v24
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 4
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a2) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 4
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a4) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vluxei64.v v12, (zero), v24
-; CHECK-RV64VC-NEXT: bltu s0, a6, .LBB914_8
+; CHECK-RV64VC-NEXT: bltu s0, a2, .LBB914_8
; CHECK-RV64VC-NEXT: # %bb.7:
-; CHECK-RV64VC-NEXT: mv s0, a6
+; CHECK-RV64VC-NEXT: mv s0, a2
; CHECK-RV64VC-NEXT: .LBB914_8:
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
@@ -37192,18 +37192,18 @@ define <vscale x 64 x i8> @test_nontemporal_vp_gather_nxv64i8_DEFAULT(<vscale x
; CHECK-RV32VC-NEXT: vl8re32.v v16, (a0)
; CHECK-RV32VC-NEXT: slli a3, a4, 3
; CHECK-RV32VC-NEXT: slli a1, a4, 2
-; CHECK-RV32VC-NEXT: add a6, a0, a3
+; CHECK-RV32VC-NEXT: add a5, a0, a3
; CHECK-RV32VC-NEXT: sub a0, a2, a1
; CHECK-RV32VC-NEXT: sltu a3, a2, a0
; CHECK-RV32VC-NEXT: addi a3, a3, -1
; CHECK-RV32VC-NEXT: and a3, a3, a0
; CHECK-RV32VC-NEXT: slli a0, a4, 1
; CHECK-RV32VC-NEXT: sub a4, a3, a0
-; CHECK-RV32VC-NEXT: sltu a5, a3, a4
-; CHECK-RV32VC-NEXT: addi a5, a5, -1
-; CHECK-RV32VC-NEXT: and a4, a4, a5
+; CHECK-RV32VC-NEXT: sltu a6, a3, a4
+; CHECK-RV32VC-NEXT: addi a6, a6, -1
+; CHECK-RV32VC-NEXT: and a4, a6, a4
; CHECK-RV32VC-NEXT: vsetvli zero, a4, e32, m8, ta, ma
-; CHECK-RV32VC-NEXT: vle32.v v0, (a6)
+; CHECK-RV32VC-NEXT: vle32.v v0, (a5)
; CHECK-RV32VC-NEXT: bltu a3, a0, .LBB914_2
; CHECK-RV32VC-NEXT: # %bb.1:
; CHECK-RV32VC-NEXT: mv a3, a0
@@ -37579,8 +37579,8 @@ define void @test_nontemporal_vp_scatter_nxv64i8_P1(<vscale x 64 x i8> %val, <vs
; CHECK-RV64VC-NEXT: add a1, a1, a2
; CHECK-RV64VC-NEXT: sub sp, sp, a1
; CHECK-RV64VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 56 * vlenb
-; CHECK-RV64VC-NEXT: mv s2, a7
-; CHECK-RV64VC-NEXT: mv s1, a0
+; CHECK-RV64VC-NEXT: mv s1, a7
+; CHECK-RV64VC-NEXT: mv s2, a0
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 4
; CHECK-RV64VC-NEXT: add a0, a0, sp
@@ -37598,7 +37598,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_P1(<vscale x 64 x i8> %val, <vs
; CHECK-RV64VC-NEXT: li a1, 48
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 3
@@ -37611,7 +37611,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_P1(<vscale x 64 x i8> %val, <vs
; CHECK-RV64VC-NEXT: li a1, 40
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 5
@@ -37619,7 +37619,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_P1(<vscale x 64 x i8> %val, <vs
; CHECK-RV64VC-NEXT: addi a0, a0, 16
; CHECK-RV64VC-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: slli a0, s0, 5
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 3
@@ -37632,122 +37632,122 @@ define void @test_nontemporal_vp_scatter_nxv64i8_P1(<vscale x 64 x i8> %val, <vs
; CHECK-RV64VC-NEXT: li a1, 24
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: slli a6, s0, 2
-; CHECK-RV64VC-NEXT: mv a3, s2
-; CHECK-RV64VC-NEXT: bltu s2, a6, .LBB915_2
+; CHECK-RV64VC-NEXT: slli a2, s0, 2
+; CHECK-RV64VC-NEXT: mv a3, s1
+; CHECK-RV64VC-NEXT: bltu s1, a2, .LBB915_2
; CHECK-RV64VC-NEXT: # %bb.1:
-; CHECK-RV64VC-NEXT: mv a3, a6
+; CHECK-RV64VC-NEXT: mv a3, a2
; CHECK-RV64VC-NEXT: .LBB915_2:
; CHECK-RV64VC-NEXT: slli a5, s0, 4
-; CHECK-RV64VC-NEXT: slli a7, s0, 1
-; CHECK-RV64VC-NEXT: slli a2, s0, 3
+; CHECK-RV64VC-NEXT: slli a1, s0, 1
+; CHECK-RV64VC-NEXT: slli a6, s0, 3
; CHECK-RV64VC-NEXT: mv a4, a3
-; CHECK-RV64VC-NEXT: bltu a3, a7, .LBB915_4
+; CHECK-RV64VC-NEXT: bltu a3, a1, .LBB915_4
; CHECK-RV64VC-NEXT: # %bb.3:
-; CHECK-RV64VC-NEXT: mv a4, a7
+; CHECK-RV64VC-NEXT: mv a4, a1
; CHECK-RV64VC-NEXT: .LBB915_4:
-; CHECK-RV64VC-NEXT: vl8re64.v v8, (s1)
-; CHECK-RV64VC-NEXT: add a1, s1, a0
-; CHECK-RV64VC-NEXT: add a5, a5, s1
-; CHECK-RV64VC-NEXT: add a2, a2, s1
+; CHECK-RV64VC-NEXT: vl8re64.v v8, (s2)
+; CHECK-RV64VC-NEXT: add a7, s2, a0
+; CHECK-RV64VC-NEXT: add a5, a5, s2
+; CHECK-RV64VC-NEXT: add a6, a6, s2
; CHECK-RV64VC-NEXT: mv a0, a4
; CHECK-RV64VC-NEXT: bltu a4, s0, .LBB915_6
; CHECK-RV64VC-NEXT: # %bb.5:
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: .LBB915_6:
-; CHECK-RV64VC-NEXT: vl8re64.v v16, (a1)
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 3
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v16, (a7)
+; CHECK-RV64VC-NEXT: csrr a7, vlenb
+; CHECK-RV64VC-NEXT: slli a7, a7, 3
+; CHECK-RV64VC-NEXT: add a7, a7, sp
+; CHECK-RV64VC-NEXT: addi a7, a7, 16
+; CHECK-RV64VC-NEXT: vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a5)
-; CHECK-RV64VC-NEXT: addi a1, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-RV64VC-NEXT: vl8re64.v v0, (a2)
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 4
-; CHECK-RV64VC-NEXT: mv a2, a1
-; CHECK-RV64VC-NEXT: slli a1, a1, 1
-; CHECK-RV64VC-NEXT: add a1, a1, a2
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 4
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v0, (a6)
+; CHECK-RV64VC-NEXT: csrr a5, vlenb
+; CHECK-RV64VC-NEXT: slli a5, a5, 4
+; CHECK-RV64VC-NEXT: mv a6, a5
+; CHECK-RV64VC-NEXT: slli a5, a5, 1
+; CHECK-RV64VC-NEXT: add a5, a5, a6
+; CHECK-RV64VC-NEXT: add a5, a5, sp
+; CHECK-RV64VC-NEXT: addi a5, a5, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a5, vlenb
+; CHECK-RV64VC-NEXT: slli a5, a5, 4
+; CHECK-RV64VC-NEXT: add a5, a5, sp
+; CHECK-RV64VC-NEXT: addi a5, a5, 16
+; CHECK-RV64VC-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
; CHECK-RV64VC-NEXT: vsoxei64.v v24, (zero), v16
; CHECK-RV64VC-NEXT: sub a0, a4, s0
-; CHECK-RV64VC-NEXT: sub a1, a3, a7
-; CHECK-RV64VC-NEXT: sltu a2, a4, a0
-; CHECK-RV64VC-NEXT: sltu a3, a3, a1
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
+; CHECK-RV64VC-NEXT: sub a5, a3, a1
+; CHECK-RV64VC-NEXT: sltu a4, a4, a0
+; CHECK-RV64VC-NEXT: sltu a3, a3, a5
+; CHECK-RV64VC-NEXT: addi a4, a4, -1
; CHECK-RV64VC-NEXT: addi a3, a3, -1
-; CHECK-RV64VC-NEXT: and a2, a2, a0
-; CHECK-RV64VC-NEXT: and a0, a3, a1
-; CHECK-RV64VC-NEXT: vsetvli zero, a2, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: and a4, a4, a0
+; CHECK-RV64VC-NEXT: and a0, a3, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
; CHECK-RV64VC-NEXT: vsoxei64.v v25, (zero), v8
-; CHECK-RV64VC-NEXT: mv a1, a0
+; CHECK-RV64VC-NEXT: mv a3, a0
; CHECK-RV64VC-NEXT: bltu a0, s0, .LBB915_8
; CHECK-RV64VC-NEXT: # %bb.7:
-; CHECK-RV64VC-NEXT: mv a1, s0
+; CHECK-RV64VC-NEXT: mv a3, s0
; CHECK-RV64VC-NEXT: .LBB915_8:
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
; CHECK-RV64VC-NEXT: vsoxei64.v v26, (zero), v0
-; CHECK-RV64VC-NEXT: sub a1, a0, s0
-; CHECK-RV64VC-NEXT: sub a2, s2, a6
-; CHECK-RV64VC-NEXT: sltu a0, a0, a1
-; CHECK-RV64VC-NEXT: sltu a3, s2, a2
+; CHECK-RV64VC-NEXT: sub a3, a0, s0
+; CHECK-RV64VC-NEXT: sub a2, s1, a2
+; CHECK-RV64VC-NEXT: sltu a0, a0, a3
+; CHECK-RV64VC-NEXT: sltu a4, s1, a2
; CHECK-RV64VC-NEXT: addi a0, a0, -1
-; CHECK-RV64VC-NEXT: addi a3, a3, -1
-; CHECK-RV64VC-NEXT: and a1, a1, a0
-; CHECK-RV64VC-NEXT: and a0, a3, a2
+; CHECK-RV64VC-NEXT: addi a4, a4, -1
+; CHECK-RV64VC-NEXT: and a3, a3, a0
+; CHECK-RV64VC-NEXT: and a0, a4, a2
; CHECK-RV64VC-NEXT: addi a2, sp, 16
; CHECK-RV64VC-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
; CHECK-RV64VC-NEXT: vsoxei64.v v27, (zero), v8
; CHECK-RV64VC-NEXT: mv a2, a0
-; CHECK-RV64VC-NEXT: bltu a0, a7, .LBB915_10
+; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB915_10
; CHECK-RV64VC-NEXT: # %bb.9:
-; CHECK-RV64VC-NEXT: mv a2, a7
+; CHECK-RV64VC-NEXT: mv a2, a1
; CHECK-RV64VC-NEXT: .LBB915_10:
-; CHECK-RV64VC-NEXT: mv a1, a2
+; CHECK-RV64VC-NEXT: mv a3, a2
; CHECK-RV64VC-NEXT: bltu a2, s0, .LBB915_12
; CHECK-RV64VC-NEXT: # %bb.11:
-; CHECK-RV64VC-NEXT: mv a1, s0
+; CHECK-RV64VC-NEXT: mv a3, s0
; CHECK-RV64VC-NEXT: .LBB915_12:
-; CHECK-RV64VC-NEXT: csrr a3, vlenb
-; CHECK-RV64VC-NEXT: slli a3, a3, 3
-; CHECK-RV64VC-NEXT: add a3, a3, sp
-; CHECK-RV64VC-NEXT: addi a3, a3, 16
-; CHECK-RV64VC-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 3
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
; CHECK-RV64VC-NEXT: vsoxei64.v v28, (zero), v8
-; CHECK-RV64VC-NEXT: sub a1, a2, s0
-; CHECK-RV64VC-NEXT: sub a3, a0, a7
-; CHECK-RV64VC-NEXT: sltu a2, a2, a1
-; CHECK-RV64VC-NEXT: sltu a0, a0, a3
+; CHECK-RV64VC-NEXT: sub a3, a2, s0
+; CHECK-RV64VC-NEXT: sub a1, a0, a1
+; CHECK-RV64VC-NEXT: sltu a2, a2, a3
+; CHECK-RV64VC-NEXT: sltu a0, a0, a1
; CHECK-RV64VC-NEXT: addi a2, a2, -1
; CHECK-RV64VC-NEXT: addi a0, a0, -1
-; CHECK-RV64VC-NEXT: and a1, a1, a2
-; CHECK-RV64VC-NEXT: and a0, a0, a3
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 3
-; CHECK-RV64VC-NEXT: mv a3, a2
-; CHECK-RV64VC-NEXT: slli a2, a2, 1
-; CHECK-RV64VC-NEXT: add a2, a2, a3
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: and a2, a2, a3
+; CHECK-RV64VC-NEXT: and a0, a0, a1
+; CHECK-RV64VC-NEXT: csrr a1, vlenb
+; CHECK-RV64VC-NEXT: slli a1, a1, 3
+; CHECK-RV64VC-NEXT: mv a3, a1
+; CHECK-RV64VC-NEXT: slli a1, a1, 1
+; CHECK-RV64VC-NEXT: add a1, a1, a3
+; CHECK-RV64VC-NEXT: add a1, a1, sp
+; CHECK-RV64VC-NEXT: addi a1, a1, 16
+; CHECK-RV64VC-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vsetvli zero, a2, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.p1
; CHECK-RV64VC-NEXT: vsoxei64.v v29, (zero), v8
; CHECK-RV64VC-NEXT: mv a1, a0
@@ -37802,22 +37802,22 @@ define void @test_nontemporal_vp_scatter_nxv64i8_P1(<vscale x 64 x i8> %val, <vs
; CHECK-RV32VC-LABEL: test_nontemporal_vp_scatter_nxv64i8_P1:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: csrr a1, vlenb
-; CHECK-RV32VC-NEXT: slli a6, a1, 4
+; CHECK-RV32VC-NEXT: slli a5, a1, 4
; CHECK-RV32VC-NEXT: slli a2, a1, 2
-; CHECK-RV32VC-NEXT: slli a5, a1, 3
+; CHECK-RV32VC-NEXT: slli a6, a1, 3
; CHECK-RV32VC-NEXT: mv a4, a3
; CHECK-RV32VC-NEXT: bltu a3, a2, .LBB915_2
; CHECK-RV32VC-NEXT: # %bb.1:
; CHECK-RV32VC-NEXT: mv a4, a2
; CHECK-RV32VC-NEXT: .LBB915_2:
; CHECK-RV32VC-NEXT: vl8re32.v v0, (a0)
-; CHECK-RV32VC-NEXT: add a6, a6, a0
+; CHECK-RV32VC-NEXT: add a5, a5, a0
; CHECK-RV32VC-NEXT: slli a1, a1, 1
-; CHECK-RV32VC-NEXT: add a0, a0, a5
-; CHECK-RV32VC-NEXT: mv a5, a4
+; CHECK-RV32VC-NEXT: add a0, a0, a6
+; CHECK-RV32VC-NEXT: mv a6, a4
; CHECK-RV32VC-NEXT: bltu a4, a1, .LBB915_4
; CHECK-RV32VC-NEXT: # %bb.3:
-; CHECK-RV32VC-NEXT: mv a5, a1
+; CHECK-RV32VC-NEXT: mv a6, a1
; CHECK-RV32VC-NEXT: .LBB915_4:
; CHECK-RV32VC-NEXT: addi sp, sp, -16
; CHECK-RV32VC-NEXT: .cfi_def_cfa_offset 16
@@ -37825,11 +37825,11 @@ define void @test_nontemporal_vp_scatter_nxv64i8_P1(<vscale x 64 x i8> %val, <vs
; CHECK-RV32VC-NEXT: slli a7, a7, 3
; CHECK-RV32VC-NEXT: sub sp, sp, a7
; CHECK-RV32VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-RV32VC-NEXT: vl8re32.v v24, (a6)
-; CHECK-RV32VC-NEXT: addi a6, sp, 16
-; CHECK-RV32VC-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV32VC-NEXT: vl8re32.v v24, (a5)
+; CHECK-RV32VC-NEXT: addi a5, sp, 16
+; CHECK-RV32VC-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV32VC-NEXT: vl8re32.v v24, (a0)
-; CHECK-RV32VC-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; CHECK-RV32VC-NEXT: vsetvli zero, a6, e8, m2, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.p1
; CHECK-RV32VC-NEXT: vsoxei32.v v8, (zero), v16
; CHECK-RV32VC-NEXT: sub a0, a4, a1
@@ -38204,8 +38204,8 @@ define void @test_nontemporal_vp_scatter_nxv64i8_PALL(<vscale x 64 x i8> %val, <
; CHECK-RV64VC-NEXT: add a1, a1, a2
; CHECK-RV64VC-NEXT: sub sp, sp, a1
; CHECK-RV64VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 56 * vlenb
-; CHECK-RV64VC-NEXT: mv s2, a7
-; CHECK-RV64VC-NEXT: mv s1, a0
+; CHECK-RV64VC-NEXT: mv s1, a7
+; CHECK-RV64VC-NEXT: mv s2, a0
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 4
; CHECK-RV64VC-NEXT: add a0, a0, sp
@@ -38223,7 +38223,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_PALL(<vscale x 64 x i8> %val, <
; CHECK-RV64VC-NEXT: li a1, 48
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 3
@@ -38236,7 +38236,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_PALL(<vscale x 64 x i8> %val, <
; CHECK-RV64VC-NEXT: li a1, 40
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 5
@@ -38244,7 +38244,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_PALL(<vscale x 64 x i8> %val, <
; CHECK-RV64VC-NEXT: addi a0, a0, 16
; CHECK-RV64VC-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: slli a0, s0, 5
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 3
@@ -38257,122 +38257,122 @@ define void @test_nontemporal_vp_scatter_nxv64i8_PALL(<vscale x 64 x i8> %val, <
; CHECK-RV64VC-NEXT: li a1, 24
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: slli a6, s0, 2
-; CHECK-RV64VC-NEXT: mv a3, s2
-; CHECK-RV64VC-NEXT: bltu s2, a6, .LBB916_2
+; CHECK-RV64VC-NEXT: slli a2, s0, 2
+; CHECK-RV64VC-NEXT: mv a3, s1
+; CHECK-RV64VC-NEXT: bltu s1, a2, .LBB916_2
; CHECK-RV64VC-NEXT: # %bb.1:
-; CHECK-RV64VC-NEXT: mv a3, a6
+; CHECK-RV64VC-NEXT: mv a3, a2
; CHECK-RV64VC-NEXT: .LBB916_2:
; CHECK-RV64VC-NEXT: slli a5, s0, 4
-; CHECK-RV64VC-NEXT: slli a7, s0, 1
-; CHECK-RV64VC-NEXT: slli a2, s0, 3
+; CHECK-RV64VC-NEXT: slli a1, s0, 1
+; CHECK-RV64VC-NEXT: slli a6, s0, 3
; CHECK-RV64VC-NEXT: mv a4, a3
-; CHECK-RV64VC-NEXT: bltu a3, a7, .LBB916_4
+; CHECK-RV64VC-NEXT: bltu a3, a1, .LBB916_4
; CHECK-RV64VC-NEXT: # %bb.3:
-; CHECK-RV64VC-NEXT: mv a4, a7
+; CHECK-RV64VC-NEXT: mv a4, a1
; CHECK-RV64VC-NEXT: .LBB916_4:
-; CHECK-RV64VC-NEXT: vl8re64.v v8, (s1)
-; CHECK-RV64VC-NEXT: add a1, s1, a0
-; CHECK-RV64VC-NEXT: add a5, a5, s1
-; CHECK-RV64VC-NEXT: add a2, a2, s1
+; CHECK-RV64VC-NEXT: vl8re64.v v8, (s2)
+; CHECK-RV64VC-NEXT: add a7, s2, a0
+; CHECK-RV64VC-NEXT: add a5, a5, s2
+; CHECK-RV64VC-NEXT: add a6, a6, s2
; CHECK-RV64VC-NEXT: mv a0, a4
; CHECK-RV64VC-NEXT: bltu a4, s0, .LBB916_6
; CHECK-RV64VC-NEXT: # %bb.5:
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: .LBB916_6:
-; CHECK-RV64VC-NEXT: vl8re64.v v16, (a1)
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 3
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v16, (a7)
+; CHECK-RV64VC-NEXT: csrr a7, vlenb
+; CHECK-RV64VC-NEXT: slli a7, a7, 3
+; CHECK-RV64VC-NEXT: add a7, a7, sp
+; CHECK-RV64VC-NEXT: addi a7, a7, 16
+; CHECK-RV64VC-NEXT: vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a5)
-; CHECK-RV64VC-NEXT: addi a1, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-RV64VC-NEXT: vl8re64.v v0, (a2)
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 4
-; CHECK-RV64VC-NEXT: mv a2, a1
-; CHECK-RV64VC-NEXT: slli a1, a1, 1
-; CHECK-RV64VC-NEXT: add a1, a1, a2
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 4
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v0, (a6)
+; CHECK-RV64VC-NEXT: csrr a5, vlenb
+; CHECK-RV64VC-NEXT: slli a5, a5, 4
+; CHECK-RV64VC-NEXT: mv a6, a5
+; CHECK-RV64VC-NEXT: slli a5, a5, 1
+; CHECK-RV64VC-NEXT: add a5, a5, a6
+; CHECK-RV64VC-NEXT: add a5, a5, sp
+; CHECK-RV64VC-NEXT: addi a5, a5, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a5, vlenb
+; CHECK-RV64VC-NEXT: slli a5, a5, 4
+; CHECK-RV64VC-NEXT: add a5, a5, sp
+; CHECK-RV64VC-NEXT: addi a5, a5, 16
+; CHECK-RV64VC-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
; CHECK-RV64VC-NEXT: vsoxei64.v v24, (zero), v16
; CHECK-RV64VC-NEXT: sub a0, a4, s0
-; CHECK-RV64VC-NEXT: sub a1, a3, a7
-; CHECK-RV64VC-NEXT: sltu a2, a4, a0
-; CHECK-RV64VC-NEXT: sltu a3, a3, a1
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
+; CHECK-RV64VC-NEXT: sub a5, a3, a1
+; CHECK-RV64VC-NEXT: sltu a4, a4, a0
+; CHECK-RV64VC-NEXT: sltu a3, a3, a5
+; CHECK-RV64VC-NEXT: addi a4, a4, -1
; CHECK-RV64VC-NEXT: addi a3, a3, -1
-; CHECK-RV64VC-NEXT: and a2, a2, a0
-; CHECK-RV64VC-NEXT: and a0, a3, a1
-; CHECK-RV64VC-NEXT: vsetvli zero, a2, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: and a4, a4, a0
+; CHECK-RV64VC-NEXT: and a0, a3, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
; CHECK-RV64VC-NEXT: vsoxei64.v v25, (zero), v8
-; CHECK-RV64VC-NEXT: mv a1, a0
+; CHECK-RV64VC-NEXT: mv a3, a0
; CHECK-RV64VC-NEXT: bltu a0, s0, .LBB916_8
; CHECK-RV64VC-NEXT: # %bb.7:
-; CHECK-RV64VC-NEXT: mv a1, s0
+; CHECK-RV64VC-NEXT: mv a3, s0
; CHECK-RV64VC-NEXT: .LBB916_8:
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
; CHECK-RV64VC-NEXT: vsoxei64.v v26, (zero), v0
-; CHECK-RV64VC-NEXT: sub a1, a0, s0
-; CHECK-RV64VC-NEXT: sub a2, s2, a6
-; CHECK-RV64VC-NEXT: sltu a0, a0, a1
-; CHECK-RV64VC-NEXT: sltu a3, s2, a2
+; CHECK-RV64VC-NEXT: sub a3, a0, s0
+; CHECK-RV64VC-NEXT: sub a2, s1, a2
+; CHECK-RV64VC-NEXT: sltu a0, a0, a3
+; CHECK-RV64VC-NEXT: sltu a4, s1, a2
; CHECK-RV64VC-NEXT: addi a0, a0, -1
-; CHECK-RV64VC-NEXT: addi a3, a3, -1
-; CHECK-RV64VC-NEXT: and a1, a1, a0
-; CHECK-RV64VC-NEXT: and a0, a3, a2
+; CHECK-RV64VC-NEXT: addi a4, a4, -1
+; CHECK-RV64VC-NEXT: and a3, a3, a0
+; CHECK-RV64VC-NEXT: and a0, a4, a2
; CHECK-RV64VC-NEXT: addi a2, sp, 16
; CHECK-RV64VC-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
; CHECK-RV64VC-NEXT: vsoxei64.v v27, (zero), v8
; CHECK-RV64VC-NEXT: mv a2, a0
-; CHECK-RV64VC-NEXT: bltu a0, a7, .LBB916_10
+; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB916_10
; CHECK-RV64VC-NEXT: # %bb.9:
-; CHECK-RV64VC-NEXT: mv a2, a7
+; CHECK-RV64VC-NEXT: mv a2, a1
; CHECK-RV64VC-NEXT: .LBB916_10:
-; CHECK-RV64VC-NEXT: mv a1, a2
+; CHECK-RV64VC-NEXT: mv a3, a2
; CHECK-RV64VC-NEXT: bltu a2, s0, .LBB916_12
; CHECK-RV64VC-NEXT: # %bb.11:
-; CHECK-RV64VC-NEXT: mv a1, s0
+; CHECK-RV64VC-NEXT: mv a3, s0
; CHECK-RV64VC-NEXT: .LBB916_12:
-; CHECK-RV64VC-NEXT: csrr a3, vlenb
-; CHECK-RV64VC-NEXT: slli a3, a3, 3
-; CHECK-RV64VC-NEXT: add a3, a3, sp
-; CHECK-RV64VC-NEXT: addi a3, a3, 16
-; CHECK-RV64VC-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 3
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
; CHECK-RV64VC-NEXT: vsoxei64.v v28, (zero), v8
-; CHECK-RV64VC-NEXT: sub a1, a2, s0
-; CHECK-RV64VC-NEXT: sub a3, a0, a7
-; CHECK-RV64VC-NEXT: sltu a2, a2, a1
-; CHECK-RV64VC-NEXT: sltu a0, a0, a3
+; CHECK-RV64VC-NEXT: sub a3, a2, s0
+; CHECK-RV64VC-NEXT: sub a1, a0, a1
+; CHECK-RV64VC-NEXT: sltu a2, a2, a3
+; CHECK-RV64VC-NEXT: sltu a0, a0, a1
; CHECK-RV64VC-NEXT: addi a2, a2, -1
; CHECK-RV64VC-NEXT: addi a0, a0, -1
-; CHECK-RV64VC-NEXT: and a1, a1, a2
-; CHECK-RV64VC-NEXT: and a0, a0, a3
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 3
-; CHECK-RV64VC-NEXT: mv a3, a2
-; CHECK-RV64VC-NEXT: slli a2, a2, 1
-; CHECK-RV64VC-NEXT: add a2, a2, a3
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: and a2, a2, a3
+; CHECK-RV64VC-NEXT: and a0, a0, a1
+; CHECK-RV64VC-NEXT: csrr a1, vlenb
+; CHECK-RV64VC-NEXT: slli a1, a1, 3
+; CHECK-RV64VC-NEXT: mv a3, a1
+; CHECK-RV64VC-NEXT: slli a1, a1, 1
+; CHECK-RV64VC-NEXT: add a1, a1, a3
+; CHECK-RV64VC-NEXT: add a1, a1, sp
+; CHECK-RV64VC-NEXT: addi a1, a1, 16
+; CHECK-RV64VC-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vsetvli zero, a2, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.pall
; CHECK-RV64VC-NEXT: vsoxei64.v v29, (zero), v8
; CHECK-RV64VC-NEXT: mv a1, a0
@@ -38427,22 +38427,22 @@ define void @test_nontemporal_vp_scatter_nxv64i8_PALL(<vscale x 64 x i8> %val, <
; CHECK-RV32VC-LABEL: test_nontemporal_vp_scatter_nxv64i8_PALL:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: csrr a1, vlenb
-; CHECK-RV32VC-NEXT: slli a6, a1, 4
+; CHECK-RV32VC-NEXT: slli a5, a1, 4
; CHECK-RV32VC-NEXT: slli a2, a1, 2
-; CHECK-RV32VC-NEXT: slli a5, a1, 3
+; CHECK-RV32VC-NEXT: slli a6, a1, 3
; CHECK-RV32VC-NEXT: mv a4, a3
; CHECK-RV32VC-NEXT: bltu a3, a2, .LBB916_2
; CHECK-RV32VC-NEXT: # %bb.1:
; CHECK-RV32VC-NEXT: mv a4, a2
; CHECK-RV32VC-NEXT: .LBB916_2:
; CHECK-RV32VC-NEXT: vl8re32.v v0, (a0)
-; CHECK-RV32VC-NEXT: add a6, a6, a0
+; CHECK-RV32VC-NEXT: add a5, a5, a0
; CHECK-RV32VC-NEXT: slli a1, a1, 1
-; CHECK-RV32VC-NEXT: add a0, a0, a5
-; CHECK-RV32VC-NEXT: mv a5, a4
+; CHECK-RV32VC-NEXT: add a0, a0, a6
+; CHECK-RV32VC-NEXT: mv a6, a4
; CHECK-RV32VC-NEXT: bltu a4, a1, .LBB916_4
; CHECK-RV32VC-NEXT: # %bb.3:
-; CHECK-RV32VC-NEXT: mv a5, a1
+; CHECK-RV32VC-NEXT: mv a6, a1
; CHECK-RV32VC-NEXT: .LBB916_4:
; CHECK-RV32VC-NEXT: addi sp, sp, -16
; CHECK-RV32VC-NEXT: .cfi_def_cfa_offset 16
@@ -38450,11 +38450,11 @@ define void @test_nontemporal_vp_scatter_nxv64i8_PALL(<vscale x 64 x i8> %val, <
; CHECK-RV32VC-NEXT: slli a7, a7, 3
; CHECK-RV32VC-NEXT: sub sp, sp, a7
; CHECK-RV32VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-RV32VC-NEXT: vl8re32.v v24, (a6)
-; CHECK-RV32VC-NEXT: addi a6, sp, 16
-; CHECK-RV32VC-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV32VC-NEXT: vl8re32.v v24, (a5)
+; CHECK-RV32VC-NEXT: addi a5, sp, 16
+; CHECK-RV32VC-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV32VC-NEXT: vl8re32.v v24, (a0)
-; CHECK-RV32VC-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; CHECK-RV32VC-NEXT: vsetvli zero, a6, e8, m2, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.pall
; CHECK-RV32VC-NEXT: vsoxei32.v v8, (zero), v16
; CHECK-RV32VC-NEXT: sub a0, a4, a1
@@ -38829,8 +38829,8 @@ define void @test_nontemporal_vp_scatter_nxv64i8_S1(<vscale x 64 x i8> %val, <vs
; CHECK-RV64VC-NEXT: add a1, a1, a2
; CHECK-RV64VC-NEXT: sub sp, sp, a1
; CHECK-RV64VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 56 * vlenb
-; CHECK-RV64VC-NEXT: mv s2, a7
-; CHECK-RV64VC-NEXT: mv s1, a0
+; CHECK-RV64VC-NEXT: mv s1, a7
+; CHECK-RV64VC-NEXT: mv s2, a0
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 4
; CHECK-RV64VC-NEXT: add a0, a0, sp
@@ -38848,7 +38848,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_S1(<vscale x 64 x i8> %val, <vs
; CHECK-RV64VC-NEXT: li a1, 48
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 3
@@ -38861,7 +38861,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_S1(<vscale x 64 x i8> %val, <vs
; CHECK-RV64VC-NEXT: li a1, 40
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 5
@@ -38869,7 +38869,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_S1(<vscale x 64 x i8> %val, <vs
; CHECK-RV64VC-NEXT: addi a0, a0, 16
; CHECK-RV64VC-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: slli a0, s0, 5
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 3
@@ -38882,122 +38882,122 @@ define void @test_nontemporal_vp_scatter_nxv64i8_S1(<vscale x 64 x i8> %val, <vs
; CHECK-RV64VC-NEXT: li a1, 24
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: slli a6, s0, 2
-; CHECK-RV64VC-NEXT: mv a3, s2
-; CHECK-RV64VC-NEXT: bltu s2, a6, .LBB917_2
+; CHECK-RV64VC-NEXT: slli a2, s0, 2
+; CHECK-RV64VC-NEXT: mv a3, s1
+; CHECK-RV64VC-NEXT: bltu s1, a2, .LBB917_2
; CHECK-RV64VC-NEXT: # %bb.1:
-; CHECK-RV64VC-NEXT: mv a3, a6
+; CHECK-RV64VC-NEXT: mv a3, a2
; CHECK-RV64VC-NEXT: .LBB917_2:
; CHECK-RV64VC-NEXT: slli a5, s0, 4
-; CHECK-RV64VC-NEXT: slli a7, s0, 1
-; CHECK-RV64VC-NEXT: slli a2, s0, 3
+; CHECK-RV64VC-NEXT: slli a1, s0, 1
+; CHECK-RV64VC-NEXT: slli a6, s0, 3
; CHECK-RV64VC-NEXT: mv a4, a3
-; CHECK-RV64VC-NEXT: bltu a3, a7, .LBB917_4
+; CHECK-RV64VC-NEXT: bltu a3, a1, .LBB917_4
; CHECK-RV64VC-NEXT: # %bb.3:
-; CHECK-RV64VC-NEXT: mv a4, a7
+; CHECK-RV64VC-NEXT: mv a4, a1
; CHECK-RV64VC-NEXT: .LBB917_4:
-; CHECK-RV64VC-NEXT: vl8re64.v v8, (s1)
-; CHECK-RV64VC-NEXT: add a1, s1, a0
-; CHECK-RV64VC-NEXT: add a5, a5, s1
-; CHECK-RV64VC-NEXT: add a2, a2, s1
+; CHECK-RV64VC-NEXT: vl8re64.v v8, (s2)
+; CHECK-RV64VC-NEXT: add a7, s2, a0
+; CHECK-RV64VC-NEXT: add a5, a5, s2
+; CHECK-RV64VC-NEXT: add a6, a6, s2
; CHECK-RV64VC-NEXT: mv a0, a4
; CHECK-RV64VC-NEXT: bltu a4, s0, .LBB917_6
; CHECK-RV64VC-NEXT: # %bb.5:
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: .LBB917_6:
-; CHECK-RV64VC-NEXT: vl8re64.v v16, (a1)
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 3
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v16, (a7)
+; CHECK-RV64VC-NEXT: csrr a7, vlenb
+; CHECK-RV64VC-NEXT: slli a7, a7, 3
+; CHECK-RV64VC-NEXT: add a7, a7, sp
+; CHECK-RV64VC-NEXT: addi a7, a7, 16
+; CHECK-RV64VC-NEXT: vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a5)
-; CHECK-RV64VC-NEXT: addi a1, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-RV64VC-NEXT: vl8re64.v v0, (a2)
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 4
-; CHECK-RV64VC-NEXT: mv a2, a1
-; CHECK-RV64VC-NEXT: slli a1, a1, 1
-; CHECK-RV64VC-NEXT: add a1, a1, a2
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 4
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v0, (a6)
+; CHECK-RV64VC-NEXT: csrr a5, vlenb
+; CHECK-RV64VC-NEXT: slli a5, a5, 4
+; CHECK-RV64VC-NEXT: mv a6, a5
+; CHECK-RV64VC-NEXT: slli a5, a5, 1
+; CHECK-RV64VC-NEXT: add a5, a5, a6
+; CHECK-RV64VC-NEXT: add a5, a5, sp
+; CHECK-RV64VC-NEXT: addi a5, a5, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a5, vlenb
+; CHECK-RV64VC-NEXT: slli a5, a5, 4
+; CHECK-RV64VC-NEXT: add a5, a5, sp
+; CHECK-RV64VC-NEXT: addi a5, a5, 16
+; CHECK-RV64VC-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
; CHECK-RV64VC-NEXT: vsoxei64.v v24, (zero), v16
; CHECK-RV64VC-NEXT: sub a0, a4, s0
-; CHECK-RV64VC-NEXT: sub a1, a3, a7
-; CHECK-RV64VC-NEXT: sltu a2, a4, a0
-; CHECK-RV64VC-NEXT: sltu a3, a3, a1
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
+; CHECK-RV64VC-NEXT: sub a5, a3, a1
+; CHECK-RV64VC-NEXT: sltu a4, a4, a0
+; CHECK-RV64VC-NEXT: sltu a3, a3, a5
+; CHECK-RV64VC-NEXT: addi a4, a4, -1
; CHECK-RV64VC-NEXT: addi a3, a3, -1
-; CHECK-RV64VC-NEXT: and a2, a2, a0
-; CHECK-RV64VC-NEXT: and a0, a3, a1
-; CHECK-RV64VC-NEXT: vsetvli zero, a2, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: and a4, a4, a0
+; CHECK-RV64VC-NEXT: and a0, a3, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
; CHECK-RV64VC-NEXT: vsoxei64.v v25, (zero), v8
-; CHECK-RV64VC-NEXT: mv a1, a0
+; CHECK-RV64VC-NEXT: mv a3, a0
; CHECK-RV64VC-NEXT: bltu a0, s0, .LBB917_8
; CHECK-RV64VC-NEXT: # %bb.7:
-; CHECK-RV64VC-NEXT: mv a1, s0
+; CHECK-RV64VC-NEXT: mv a3, s0
; CHECK-RV64VC-NEXT: .LBB917_8:
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
; CHECK-RV64VC-NEXT: vsoxei64.v v26, (zero), v0
-; CHECK-RV64VC-NEXT: sub a1, a0, s0
-; CHECK-RV64VC-NEXT: sub a2, s2, a6
-; CHECK-RV64VC-NEXT: sltu a0, a0, a1
-; CHECK-RV64VC-NEXT: sltu a3, s2, a2
+; CHECK-RV64VC-NEXT: sub a3, a0, s0
+; CHECK-RV64VC-NEXT: sub a2, s1, a2
+; CHECK-RV64VC-NEXT: sltu a0, a0, a3
+; CHECK-RV64VC-NEXT: sltu a4, s1, a2
; CHECK-RV64VC-NEXT: addi a0, a0, -1
-; CHECK-RV64VC-NEXT: addi a3, a3, -1
-; CHECK-RV64VC-NEXT: and a1, a1, a0
-; CHECK-RV64VC-NEXT: and a0, a3, a2
+; CHECK-RV64VC-NEXT: addi a4, a4, -1
+; CHECK-RV64VC-NEXT: and a3, a3, a0
+; CHECK-RV64VC-NEXT: and a0, a4, a2
; CHECK-RV64VC-NEXT: addi a2, sp, 16
; CHECK-RV64VC-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
; CHECK-RV64VC-NEXT: vsoxei64.v v27, (zero), v8
; CHECK-RV64VC-NEXT: mv a2, a0
-; CHECK-RV64VC-NEXT: bltu a0, a7, .LBB917_10
+; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB917_10
; CHECK-RV64VC-NEXT: # %bb.9:
-; CHECK-RV64VC-NEXT: mv a2, a7
+; CHECK-RV64VC-NEXT: mv a2, a1
; CHECK-RV64VC-NEXT: .LBB917_10:
-; CHECK-RV64VC-NEXT: mv a1, a2
+; CHECK-RV64VC-NEXT: mv a3, a2
; CHECK-RV64VC-NEXT: bltu a2, s0, .LBB917_12
; CHECK-RV64VC-NEXT: # %bb.11:
-; CHECK-RV64VC-NEXT: mv a1, s0
+; CHECK-RV64VC-NEXT: mv a3, s0
; CHECK-RV64VC-NEXT: .LBB917_12:
-; CHECK-RV64VC-NEXT: csrr a3, vlenb
-; CHECK-RV64VC-NEXT: slli a3, a3, 3
-; CHECK-RV64VC-NEXT: add a3, a3, sp
-; CHECK-RV64VC-NEXT: addi a3, a3, 16
-; CHECK-RV64VC-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 3
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
; CHECK-RV64VC-NEXT: vsoxei64.v v28, (zero), v8
-; CHECK-RV64VC-NEXT: sub a1, a2, s0
-; CHECK-RV64VC-NEXT: sub a3, a0, a7
-; CHECK-RV64VC-NEXT: sltu a2, a2, a1
-; CHECK-RV64VC-NEXT: sltu a0, a0, a3
+; CHECK-RV64VC-NEXT: sub a3, a2, s0
+; CHECK-RV64VC-NEXT: sub a1, a0, a1
+; CHECK-RV64VC-NEXT: sltu a2, a2, a3
+; CHECK-RV64VC-NEXT: sltu a0, a0, a1
; CHECK-RV64VC-NEXT: addi a2, a2, -1
; CHECK-RV64VC-NEXT: addi a0, a0, -1
-; CHECK-RV64VC-NEXT: and a1, a1, a2
-; CHECK-RV64VC-NEXT: and a0, a0, a3
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 3
-; CHECK-RV64VC-NEXT: mv a3, a2
-; CHECK-RV64VC-NEXT: slli a2, a2, 1
-; CHECK-RV64VC-NEXT: add a2, a2, a3
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: and a2, a2, a3
+; CHECK-RV64VC-NEXT: and a0, a0, a1
+; CHECK-RV64VC-NEXT: csrr a1, vlenb
+; CHECK-RV64VC-NEXT: slli a1, a1, 3
+; CHECK-RV64VC-NEXT: mv a3, a1
+; CHECK-RV64VC-NEXT: slli a1, a1, 1
+; CHECK-RV64VC-NEXT: add a1, a1, a3
+; CHECK-RV64VC-NEXT: add a1, a1, sp
+; CHECK-RV64VC-NEXT: addi a1, a1, 16
+; CHECK-RV64VC-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vsetvli zero, a2, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.s1
; CHECK-RV64VC-NEXT: vsoxei64.v v29, (zero), v8
; CHECK-RV64VC-NEXT: mv a1, a0
@@ -39052,22 +39052,22 @@ define void @test_nontemporal_vp_scatter_nxv64i8_S1(<vscale x 64 x i8> %val, <vs
; CHECK-RV32VC-LABEL: test_nontemporal_vp_scatter_nxv64i8_S1:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: csrr a1, vlenb
-; CHECK-RV32VC-NEXT: slli a6, a1, 4
+; CHECK-RV32VC-NEXT: slli a5, a1, 4
; CHECK-RV32VC-NEXT: slli a2, a1, 2
-; CHECK-RV32VC-NEXT: slli a5, a1, 3
+; CHECK-RV32VC-NEXT: slli a6, a1, 3
; CHECK-RV32VC-NEXT: mv a4, a3
; CHECK-RV32VC-NEXT: bltu a3, a2, .LBB917_2
; CHECK-RV32VC-NEXT: # %bb.1:
; CHECK-RV32VC-NEXT: mv a4, a2
; CHECK-RV32VC-NEXT: .LBB917_2:
; CHECK-RV32VC-NEXT: vl8re32.v v0, (a0)
-; CHECK-RV32VC-NEXT: add a6, a6, a0
+; CHECK-RV32VC-NEXT: add a5, a5, a0
; CHECK-RV32VC-NEXT: slli a1, a1, 1
-; CHECK-RV32VC-NEXT: add a0, a0, a5
-; CHECK-RV32VC-NEXT: mv a5, a4
+; CHECK-RV32VC-NEXT: add a0, a0, a6
+; CHECK-RV32VC-NEXT: mv a6, a4
; CHECK-RV32VC-NEXT: bltu a4, a1, .LBB917_4
; CHECK-RV32VC-NEXT: # %bb.3:
-; CHECK-RV32VC-NEXT: mv a5, a1
+; CHECK-RV32VC-NEXT: mv a6, a1
; CHECK-RV32VC-NEXT: .LBB917_4:
; CHECK-RV32VC-NEXT: addi sp, sp, -16
; CHECK-RV32VC-NEXT: .cfi_def_cfa_offset 16
@@ -39075,11 +39075,11 @@ define void @test_nontemporal_vp_scatter_nxv64i8_S1(<vscale x 64 x i8> %val, <vs
; CHECK-RV32VC-NEXT: slli a7, a7, 3
; CHECK-RV32VC-NEXT: sub sp, sp, a7
; CHECK-RV32VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-RV32VC-NEXT: vl8re32.v v24, (a6)
-; CHECK-RV32VC-NEXT: addi a6, sp, 16
-; CHECK-RV32VC-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV32VC-NEXT: vl8re32.v v24, (a5)
+; CHECK-RV32VC-NEXT: addi a5, sp, 16
+; CHECK-RV32VC-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV32VC-NEXT: vl8re32.v v24, (a0)
-; CHECK-RV32VC-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; CHECK-RV32VC-NEXT: vsetvli zero, a6, e8, m2, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.s1
; CHECK-RV32VC-NEXT: vsoxei32.v v8, (zero), v16
; CHECK-RV32VC-NEXT: sub a0, a4, a1
@@ -39454,8 +39454,8 @@ define void @test_nontemporal_vp_scatter_nxv64i8_ALL(<vscale x 64 x i8> %val, <v
; CHECK-RV64VC-NEXT: add a1, a1, a2
; CHECK-RV64VC-NEXT: sub sp, sp, a1
; CHECK-RV64VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 56 * vlenb
-; CHECK-RV64VC-NEXT: mv s2, a7
-; CHECK-RV64VC-NEXT: mv s1, a0
+; CHECK-RV64VC-NEXT: mv s1, a7
+; CHECK-RV64VC-NEXT: mv s2, a0
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 4
; CHECK-RV64VC-NEXT: add a0, a0, sp
@@ -39473,7 +39473,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_ALL(<vscale x 64 x i8> %val, <v
; CHECK-RV64VC-NEXT: li a1, 48
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 3
@@ -39486,7 +39486,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_ALL(<vscale x 64 x i8> %val, <v
; CHECK-RV64VC-NEXT: li a1, 40
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 5
@@ -39494,7 +39494,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_ALL(<vscale x 64 x i8> %val, <v
; CHECK-RV64VC-NEXT: addi a0, a0, 16
; CHECK-RV64VC-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: slli a0, s0, 5
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 3
@@ -39507,122 +39507,122 @@ define void @test_nontemporal_vp_scatter_nxv64i8_ALL(<vscale x 64 x i8> %val, <v
; CHECK-RV64VC-NEXT: li a1, 24
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: slli a6, s0, 2
-; CHECK-RV64VC-NEXT: mv a3, s2
-; CHECK-RV64VC-NEXT: bltu s2, a6, .LBB918_2
+; CHECK-RV64VC-NEXT: slli a2, s0, 2
+; CHECK-RV64VC-NEXT: mv a3, s1
+; CHECK-RV64VC-NEXT: bltu s1, a2, .LBB918_2
; CHECK-RV64VC-NEXT: # %bb.1:
-; CHECK-RV64VC-NEXT: mv a3, a6
+; CHECK-RV64VC-NEXT: mv a3, a2
; CHECK-RV64VC-NEXT: .LBB918_2:
; CHECK-RV64VC-NEXT: slli a5, s0, 4
-; CHECK-RV64VC-NEXT: slli a7, s0, 1
-; CHECK-RV64VC-NEXT: slli a2, s0, 3
+; CHECK-RV64VC-NEXT: slli a1, s0, 1
+; CHECK-RV64VC-NEXT: slli a6, s0, 3
; CHECK-RV64VC-NEXT: mv a4, a3
-; CHECK-RV64VC-NEXT: bltu a3, a7, .LBB918_4
+; CHECK-RV64VC-NEXT: bltu a3, a1, .LBB918_4
; CHECK-RV64VC-NEXT: # %bb.3:
-; CHECK-RV64VC-NEXT: mv a4, a7
+; CHECK-RV64VC-NEXT: mv a4, a1
; CHECK-RV64VC-NEXT: .LBB918_4:
-; CHECK-RV64VC-NEXT: vl8re64.v v8, (s1)
-; CHECK-RV64VC-NEXT: add a1, s1, a0
-; CHECK-RV64VC-NEXT: add a5, a5, s1
-; CHECK-RV64VC-NEXT: add a2, a2, s1
+; CHECK-RV64VC-NEXT: vl8re64.v v8, (s2)
+; CHECK-RV64VC-NEXT: add a7, s2, a0
+; CHECK-RV64VC-NEXT: add a5, a5, s2
+; CHECK-RV64VC-NEXT: add a6, a6, s2
; CHECK-RV64VC-NEXT: mv a0, a4
; CHECK-RV64VC-NEXT: bltu a4, s0, .LBB918_6
; CHECK-RV64VC-NEXT: # %bb.5:
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: .LBB918_6:
-; CHECK-RV64VC-NEXT: vl8re64.v v16, (a1)
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 3
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v16, (a7)
+; CHECK-RV64VC-NEXT: csrr a7, vlenb
+; CHECK-RV64VC-NEXT: slli a7, a7, 3
+; CHECK-RV64VC-NEXT: add a7, a7, sp
+; CHECK-RV64VC-NEXT: addi a7, a7, 16
+; CHECK-RV64VC-NEXT: vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a5)
-; CHECK-RV64VC-NEXT: addi a1, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-RV64VC-NEXT: vl8re64.v v0, (a2)
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 4
-; CHECK-RV64VC-NEXT: mv a2, a1
-; CHECK-RV64VC-NEXT: slli a1, a1, 1
-; CHECK-RV64VC-NEXT: add a1, a1, a2
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 4
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v0, (a6)
+; CHECK-RV64VC-NEXT: csrr a5, vlenb
+; CHECK-RV64VC-NEXT: slli a5, a5, 4
+; CHECK-RV64VC-NEXT: mv a6, a5
+; CHECK-RV64VC-NEXT: slli a5, a5, 1
+; CHECK-RV64VC-NEXT: add a5, a5, a6
+; CHECK-RV64VC-NEXT: add a5, a5, sp
+; CHECK-RV64VC-NEXT: addi a5, a5, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a5, vlenb
+; CHECK-RV64VC-NEXT: slli a5, a5, 4
+; CHECK-RV64VC-NEXT: add a5, a5, sp
+; CHECK-RV64VC-NEXT: addi a5, a5, 16
+; CHECK-RV64VC-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v24, (zero), v16
; CHECK-RV64VC-NEXT: sub a0, a4, s0
-; CHECK-RV64VC-NEXT: sub a1, a3, a7
-; CHECK-RV64VC-NEXT: sltu a2, a4, a0
-; CHECK-RV64VC-NEXT: sltu a3, a3, a1
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
+; CHECK-RV64VC-NEXT: sub a5, a3, a1
+; CHECK-RV64VC-NEXT: sltu a4, a4, a0
+; CHECK-RV64VC-NEXT: sltu a3, a3, a5
+; CHECK-RV64VC-NEXT: addi a4, a4, -1
; CHECK-RV64VC-NEXT: addi a3, a3, -1
-; CHECK-RV64VC-NEXT: and a2, a2, a0
-; CHECK-RV64VC-NEXT: and a0, a3, a1
-; CHECK-RV64VC-NEXT: vsetvli zero, a2, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: and a4, a4, a0
+; CHECK-RV64VC-NEXT: and a0, a3, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v25, (zero), v8
-; CHECK-RV64VC-NEXT: mv a1, a0
+; CHECK-RV64VC-NEXT: mv a3, a0
; CHECK-RV64VC-NEXT: bltu a0, s0, .LBB918_8
; CHECK-RV64VC-NEXT: # %bb.7:
-; CHECK-RV64VC-NEXT: mv a1, s0
+; CHECK-RV64VC-NEXT: mv a3, s0
; CHECK-RV64VC-NEXT: .LBB918_8:
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v26, (zero), v0
-; CHECK-RV64VC-NEXT: sub a1, a0, s0
-; CHECK-RV64VC-NEXT: sub a2, s2, a6
-; CHECK-RV64VC-NEXT: sltu a0, a0, a1
-; CHECK-RV64VC-NEXT: sltu a3, s2, a2
+; CHECK-RV64VC-NEXT: sub a3, a0, s0
+; CHECK-RV64VC-NEXT: sub a2, s1, a2
+; CHECK-RV64VC-NEXT: sltu a0, a0, a3
+; CHECK-RV64VC-NEXT: sltu a4, s1, a2
; CHECK-RV64VC-NEXT: addi a0, a0, -1
-; CHECK-RV64VC-NEXT: addi a3, a3, -1
-; CHECK-RV64VC-NEXT: and a1, a1, a0
-; CHECK-RV64VC-NEXT: and a0, a3, a2
+; CHECK-RV64VC-NEXT: addi a4, a4, -1
+; CHECK-RV64VC-NEXT: and a3, a3, a0
+; CHECK-RV64VC-NEXT: and a0, a4, a2
; CHECK-RV64VC-NEXT: addi a2, sp, 16
; CHECK-RV64VC-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v27, (zero), v8
; CHECK-RV64VC-NEXT: mv a2, a0
-; CHECK-RV64VC-NEXT: bltu a0, a7, .LBB918_10
+; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB918_10
; CHECK-RV64VC-NEXT: # %bb.9:
-; CHECK-RV64VC-NEXT: mv a2, a7
+; CHECK-RV64VC-NEXT: mv a2, a1
; CHECK-RV64VC-NEXT: .LBB918_10:
-; CHECK-RV64VC-NEXT: mv a1, a2
+; CHECK-RV64VC-NEXT: mv a3, a2
; CHECK-RV64VC-NEXT: bltu a2, s0, .LBB918_12
; CHECK-RV64VC-NEXT: # %bb.11:
-; CHECK-RV64VC-NEXT: mv a1, s0
+; CHECK-RV64VC-NEXT: mv a3, s0
; CHECK-RV64VC-NEXT: .LBB918_12:
-; CHECK-RV64VC-NEXT: csrr a3, vlenb
-; CHECK-RV64VC-NEXT: slli a3, a3, 3
-; CHECK-RV64VC-NEXT: add a3, a3, sp
-; CHECK-RV64VC-NEXT: addi a3, a3, 16
-; CHECK-RV64VC-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 3
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v28, (zero), v8
-; CHECK-RV64VC-NEXT: sub a1, a2, s0
-; CHECK-RV64VC-NEXT: sub a3, a0, a7
-; CHECK-RV64VC-NEXT: sltu a2, a2, a1
-; CHECK-RV64VC-NEXT: sltu a0, a0, a3
+; CHECK-RV64VC-NEXT: sub a3, a2, s0
+; CHECK-RV64VC-NEXT: sub a1, a0, a1
+; CHECK-RV64VC-NEXT: sltu a2, a2, a3
+; CHECK-RV64VC-NEXT: sltu a0, a0, a1
; CHECK-RV64VC-NEXT: addi a2, a2, -1
; CHECK-RV64VC-NEXT: addi a0, a0, -1
-; CHECK-RV64VC-NEXT: and a1, a1, a2
-; CHECK-RV64VC-NEXT: and a0, a0, a3
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 3
-; CHECK-RV64VC-NEXT: mv a3, a2
-; CHECK-RV64VC-NEXT: slli a2, a2, 1
-; CHECK-RV64VC-NEXT: add a2, a2, a3
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: and a2, a2, a3
+; CHECK-RV64VC-NEXT: and a0, a0, a1
+; CHECK-RV64VC-NEXT: csrr a1, vlenb
+; CHECK-RV64VC-NEXT: slli a1, a1, 3
+; CHECK-RV64VC-NEXT: mv a3, a1
+; CHECK-RV64VC-NEXT: slli a1, a1, 1
+; CHECK-RV64VC-NEXT: add a1, a1, a3
+; CHECK-RV64VC-NEXT: add a1, a1, sp
+; CHECK-RV64VC-NEXT: addi a1, a1, 16
+; CHECK-RV64VC-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vsetvli zero, a2, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v29, (zero), v8
; CHECK-RV64VC-NEXT: mv a1, a0
@@ -39677,22 +39677,22 @@ define void @test_nontemporal_vp_scatter_nxv64i8_ALL(<vscale x 64 x i8> %val, <v
; CHECK-RV32VC-LABEL: test_nontemporal_vp_scatter_nxv64i8_ALL:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: csrr a1, vlenb
-; CHECK-RV32VC-NEXT: slli a6, a1, 4
+; CHECK-RV32VC-NEXT: slli a5, a1, 4
; CHECK-RV32VC-NEXT: slli a2, a1, 2
-; CHECK-RV32VC-NEXT: slli a5, a1, 3
+; CHECK-RV32VC-NEXT: slli a6, a1, 3
; CHECK-RV32VC-NEXT: mv a4, a3
; CHECK-RV32VC-NEXT: bltu a3, a2, .LBB918_2
; CHECK-RV32VC-NEXT: # %bb.1:
; CHECK-RV32VC-NEXT: mv a4, a2
; CHECK-RV32VC-NEXT: .LBB918_2:
; CHECK-RV32VC-NEXT: vl8re32.v v0, (a0)
-; CHECK-RV32VC-NEXT: add a6, a6, a0
+; CHECK-RV32VC-NEXT: add a5, a5, a0
; CHECK-RV32VC-NEXT: slli a1, a1, 1
-; CHECK-RV32VC-NEXT: add a0, a0, a5
-; CHECK-RV32VC-NEXT: mv a5, a4
+; CHECK-RV32VC-NEXT: add a0, a0, a6
+; CHECK-RV32VC-NEXT: mv a6, a4
; CHECK-RV32VC-NEXT: bltu a4, a1, .LBB918_4
; CHECK-RV32VC-NEXT: # %bb.3:
-; CHECK-RV32VC-NEXT: mv a5, a1
+; CHECK-RV32VC-NEXT: mv a6, a1
; CHECK-RV32VC-NEXT: .LBB918_4:
; CHECK-RV32VC-NEXT: addi sp, sp, -16
; CHECK-RV32VC-NEXT: .cfi_def_cfa_offset 16
@@ -39700,11 +39700,11 @@ define void @test_nontemporal_vp_scatter_nxv64i8_ALL(<vscale x 64 x i8> %val, <v
; CHECK-RV32VC-NEXT: slli a7, a7, 3
; CHECK-RV32VC-NEXT: sub sp, sp, a7
; CHECK-RV32VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-RV32VC-NEXT: vl8re32.v v24, (a6)
-; CHECK-RV32VC-NEXT: addi a6, sp, 16
-; CHECK-RV32VC-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV32VC-NEXT: vl8re32.v v24, (a5)
+; CHECK-RV32VC-NEXT: addi a5, sp, 16
+; CHECK-RV32VC-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV32VC-NEXT: vl8re32.v v24, (a0)
-; CHECK-RV32VC-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; CHECK-RV32VC-NEXT: vsetvli zero, a6, e8, m2, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.all
; CHECK-RV32VC-NEXT: vsoxei32.v v8, (zero), v16
; CHECK-RV32VC-NEXT: sub a0, a4, a1
@@ -40078,8 +40078,8 @@ define void @test_nontemporal_vp_scatter_nxv64i8_DEFAULT(<vscale x 64 x i8> %val
; CHECK-RV64VC-NEXT: add a1, a1, a2
; CHECK-RV64VC-NEXT: sub sp, sp, a1
; CHECK-RV64VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 56 * vlenb
-; CHECK-RV64VC-NEXT: mv s2, a7
-; CHECK-RV64VC-NEXT: mv s1, a0
+; CHECK-RV64VC-NEXT: mv s1, a7
+; CHECK-RV64VC-NEXT: mv s2, a0
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 4
; CHECK-RV64VC-NEXT: add a0, a0, sp
@@ -40097,7 +40097,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_DEFAULT(<vscale x 64 x i8> %val
; CHECK-RV64VC-NEXT: li a1, 48
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 3
@@ -40110,7 +40110,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_DEFAULT(<vscale x 64 x i8> %val
; CHECK-RV64VC-NEXT: li a1, 40
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 5
@@ -40118,7 +40118,7 @@ define void @test_nontemporal_vp_scatter_nxv64i8_DEFAULT(<vscale x 64 x i8> %val
; CHECK-RV64VC-NEXT: addi a0, a0, 16
; CHECK-RV64VC-NEXT: vs8r.v v8, (a0) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: slli a0, s0, 5
-; CHECK-RV64VC-NEXT: add a0, a0, s1
+; CHECK-RV64VC-NEXT: add a0, a0, s2
; CHECK-RV64VC-NEXT: vl8re64.v v8, (a0)
; CHECK-RV64VC-NEXT: csrr a0, vlenb
; CHECK-RV64VC-NEXT: slli a0, a0, 3
@@ -40131,122 +40131,122 @@ define void @test_nontemporal_vp_scatter_nxv64i8_DEFAULT(<vscale x 64 x i8> %val
; CHECK-RV64VC-NEXT: li a1, 24
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: call __muldi3
-; CHECK-RV64VC-NEXT: slli a6, s0, 2
-; CHECK-RV64VC-NEXT: mv a3, s2
-; CHECK-RV64VC-NEXT: bltu s2, a6, .LBB919_2
+; CHECK-RV64VC-NEXT: slli a2, s0, 2
+; CHECK-RV64VC-NEXT: mv a3, s1
+; CHECK-RV64VC-NEXT: bltu s1, a2, .LBB919_2
; CHECK-RV64VC-NEXT: # %bb.1:
-; CHECK-RV64VC-NEXT: mv a3, a6
+; CHECK-RV64VC-NEXT: mv a3, a2
; CHECK-RV64VC-NEXT: .LBB919_2:
; CHECK-RV64VC-NEXT: slli a5, s0, 4
-; CHECK-RV64VC-NEXT: slli a7, s0, 1
-; CHECK-RV64VC-NEXT: slli a2, s0, 3
+; CHECK-RV64VC-NEXT: slli a1, s0, 1
+; CHECK-RV64VC-NEXT: slli a6, s0, 3
; CHECK-RV64VC-NEXT: mv a4, a3
-; CHECK-RV64VC-NEXT: bltu a3, a7, .LBB919_4
+; CHECK-RV64VC-NEXT: bltu a3, a1, .LBB919_4
; CHECK-RV64VC-NEXT: # %bb.3:
-; CHECK-RV64VC-NEXT: mv a4, a7
+; CHECK-RV64VC-NEXT: mv a4, a1
; CHECK-RV64VC-NEXT: .LBB919_4:
-; CHECK-RV64VC-NEXT: vl8re64.v v8, (s1)
-; CHECK-RV64VC-NEXT: add a1, s1, a0
-; CHECK-RV64VC-NEXT: add a5, a5, s1
-; CHECK-RV64VC-NEXT: add a2, a2, s1
+; CHECK-RV64VC-NEXT: vl8re64.v v8, (s2)
+; CHECK-RV64VC-NEXT: add a7, s2, a0
+; CHECK-RV64VC-NEXT: add a5, a5, s2
+; CHECK-RV64VC-NEXT: add a6, a6, s2
; CHECK-RV64VC-NEXT: mv a0, a4
; CHECK-RV64VC-NEXT: bltu a4, s0, .LBB919_6
; CHECK-RV64VC-NEXT: # %bb.5:
; CHECK-RV64VC-NEXT: mv a0, s0
; CHECK-RV64VC-NEXT: .LBB919_6:
-; CHECK-RV64VC-NEXT: vl8re64.v v16, (a1)
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 3
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v16, (a7)
+; CHECK-RV64VC-NEXT: csrr a7, vlenb
+; CHECK-RV64VC-NEXT: slli a7, a7, 3
+; CHECK-RV64VC-NEXT: add a7, a7, sp
+; CHECK-RV64VC-NEXT: addi a7, a7, 16
+; CHECK-RV64VC-NEXT: vs8r.v v16, (a7) # vscale x 64-byte Folded Spill
; CHECK-RV64VC-NEXT: vl8re64.v v16, (a5)
-; CHECK-RV64VC-NEXT: addi a1, sp, 16
-; CHECK-RV64VC-NEXT: vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
-; CHECK-RV64VC-NEXT: vl8re64.v v0, (a2)
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 4
-; CHECK-RV64VC-NEXT: mv a2, a1
-; CHECK-RV64VC-NEXT: slli a1, a1, 1
-; CHECK-RV64VC-NEXT: add a1, a1, a2
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vl8r.v v24, (a1) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: csrr a1, vlenb
-; CHECK-RV64VC-NEXT: slli a1, a1, 4
-; CHECK-RV64VC-NEXT: add a1, a1, sp
-; CHECK-RV64VC-NEXT: addi a1, a1, 16
-; CHECK-RV64VC-NEXT: vl8r.v v16, (a1) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: addi a5, sp, 16
+; CHECK-RV64VC-NEXT: vs8r.v v16, (a5) # vscale x 64-byte Folded Spill
+; CHECK-RV64VC-NEXT: vl8re64.v v0, (a6)
+; CHECK-RV64VC-NEXT: csrr a5, vlenb
+; CHECK-RV64VC-NEXT: slli a5, a5, 4
+; CHECK-RV64VC-NEXT: mv a6, a5
+; CHECK-RV64VC-NEXT: slli a5, a5, 1
+; CHECK-RV64VC-NEXT: add a5, a5, a6
+; CHECK-RV64VC-NEXT: add a5, a5, sp
+; CHECK-RV64VC-NEXT: addi a5, a5, 16
+; CHECK-RV64VC-NEXT: vl8r.v v24, (a5) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: csrr a5, vlenb
+; CHECK-RV64VC-NEXT: slli a5, a5, 4
+; CHECK-RV64VC-NEXT: add a5, a5, sp
+; CHECK-RV64VC-NEXT: addi a5, a5, 16
+; CHECK-RV64VC-NEXT: vl8r.v v16, (a5) # vscale x 64-byte Folded Reload
; CHECK-RV64VC-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v24, (zero), v16
; CHECK-RV64VC-NEXT: sub a0, a4, s0
-; CHECK-RV64VC-NEXT: sub a1, a3, a7
-; CHECK-RV64VC-NEXT: sltu a2, a4, a0
-; CHECK-RV64VC-NEXT: sltu a3, a3, a1
-; CHECK-RV64VC-NEXT: addi a2, a2, -1
+; CHECK-RV64VC-NEXT: sub a5, a3, a1
+; CHECK-RV64VC-NEXT: sltu a4, a4, a0
+; CHECK-RV64VC-NEXT: sltu a3, a3, a5
+; CHECK-RV64VC-NEXT: addi a4, a4, -1
; CHECK-RV64VC-NEXT: addi a3, a3, -1
-; CHECK-RV64VC-NEXT: and a2, a2, a0
-; CHECK-RV64VC-NEXT: and a0, a3, a1
-; CHECK-RV64VC-NEXT: vsetvli zero, a2, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: and a4, a4, a0
+; CHECK-RV64VC-NEXT: and a0, a3, a5
+; CHECK-RV64VC-NEXT: vsetvli zero, a4, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v25, (zero), v8
-; CHECK-RV64VC-NEXT: mv a1, a0
+; CHECK-RV64VC-NEXT: mv a3, a0
; CHECK-RV64VC-NEXT: bltu a0, s0, .LBB919_8
; CHECK-RV64VC-NEXT: # %bb.7:
-; CHECK-RV64VC-NEXT: mv a1, s0
+; CHECK-RV64VC-NEXT: mv a3, s0
; CHECK-RV64VC-NEXT: .LBB919_8:
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v26, (zero), v0
-; CHECK-RV64VC-NEXT: sub a1, a0, s0
-; CHECK-RV64VC-NEXT: sub a2, s2, a6
-; CHECK-RV64VC-NEXT: sltu a0, a0, a1
-; CHECK-RV64VC-NEXT: sltu a3, s2, a2
+; CHECK-RV64VC-NEXT: sub a3, a0, s0
+; CHECK-RV64VC-NEXT: sub a2, s1, a2
+; CHECK-RV64VC-NEXT: sltu a0, a0, a3
+; CHECK-RV64VC-NEXT: sltu a4, s1, a2
; CHECK-RV64VC-NEXT: addi a0, a0, -1
-; CHECK-RV64VC-NEXT: addi a3, a3, -1
-; CHECK-RV64VC-NEXT: and a1, a1, a0
-; CHECK-RV64VC-NEXT: and a0, a3, a2
+; CHECK-RV64VC-NEXT: addi a4, a4, -1
+; CHECK-RV64VC-NEXT: and a3, a3, a0
+; CHECK-RV64VC-NEXT: and a0, a4, a2
; CHECK-RV64VC-NEXT: addi a2, sp, 16
; CHECK-RV64VC-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v27, (zero), v8
; CHECK-RV64VC-NEXT: mv a2, a0
-; CHECK-RV64VC-NEXT: bltu a0, a7, .LBB919_10
+; CHECK-RV64VC-NEXT: bltu a0, a1, .LBB919_10
; CHECK-RV64VC-NEXT: # %bb.9:
-; CHECK-RV64VC-NEXT: mv a2, a7
+; CHECK-RV64VC-NEXT: mv a2, a1
; CHECK-RV64VC-NEXT: .LBB919_10:
-; CHECK-RV64VC-NEXT: mv a1, a2
+; CHECK-RV64VC-NEXT: mv a3, a2
; CHECK-RV64VC-NEXT: bltu a2, s0, .LBB919_12
; CHECK-RV64VC-NEXT: # %bb.11:
-; CHECK-RV64VC-NEXT: mv a1, s0
+; CHECK-RV64VC-NEXT: mv a3, s0
; CHECK-RV64VC-NEXT: .LBB919_12:
-; CHECK-RV64VC-NEXT: csrr a3, vlenb
-; CHECK-RV64VC-NEXT: slli a3, a3, 3
-; CHECK-RV64VC-NEXT: add a3, a3, sp
-; CHECK-RV64VC-NEXT: addi a3, a3, 16
-; CHECK-RV64VC-NEXT: vl8r.v v8, (a3) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: csrr a4, vlenb
+; CHECK-RV64VC-NEXT: slli a4, a4, 3
+; CHECK-RV64VC-NEXT: add a4, a4, sp
+; CHECK-RV64VC-NEXT: addi a4, a4, 16
+; CHECK-RV64VC-NEXT: vl8r.v v8, (a4) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v28, (zero), v8
-; CHECK-RV64VC-NEXT: sub a1, a2, s0
-; CHECK-RV64VC-NEXT: sub a3, a0, a7
-; CHECK-RV64VC-NEXT: sltu a2, a2, a1
-; CHECK-RV64VC-NEXT: sltu a0, a0, a3
+; CHECK-RV64VC-NEXT: sub a3, a2, s0
+; CHECK-RV64VC-NEXT: sub a1, a0, a1
+; CHECK-RV64VC-NEXT: sltu a2, a2, a3
+; CHECK-RV64VC-NEXT: sltu a0, a0, a1
; CHECK-RV64VC-NEXT: addi a2, a2, -1
; CHECK-RV64VC-NEXT: addi a0, a0, -1
-; CHECK-RV64VC-NEXT: and a1, a1, a2
-; CHECK-RV64VC-NEXT: and a0, a0, a3
-; CHECK-RV64VC-NEXT: csrr a2, vlenb
-; CHECK-RV64VC-NEXT: slli a2, a2, 3
-; CHECK-RV64VC-NEXT: mv a3, a2
-; CHECK-RV64VC-NEXT: slli a2, a2, 1
-; CHECK-RV64VC-NEXT: add a2, a2, a3
-; CHECK-RV64VC-NEXT: add a2, a2, sp
-; CHECK-RV64VC-NEXT: addi a2, a2, 16
-; CHECK-RV64VC-NEXT: vl8r.v v8, (a2) # vscale x 64-byte Folded Reload
-; CHECK-RV64VC-NEXT: vsetvli zero, a1, e8, m1, ta, ma
+; CHECK-RV64VC-NEXT: and a2, a2, a3
+; CHECK-RV64VC-NEXT: and a0, a0, a1
+; CHECK-RV64VC-NEXT: csrr a1, vlenb
+; CHECK-RV64VC-NEXT: slli a1, a1, 3
+; CHECK-RV64VC-NEXT: mv a3, a1
+; CHECK-RV64VC-NEXT: slli a1, a1, 1
+; CHECK-RV64VC-NEXT: add a1, a1, a3
+; CHECK-RV64VC-NEXT: add a1, a1, sp
+; CHECK-RV64VC-NEXT: addi a1, a1, 16
+; CHECK-RV64VC-NEXT: vl8r.v v8, (a1) # vscale x 64-byte Folded Reload
+; CHECK-RV64VC-NEXT: vsetvli zero, a2, e8, m1, ta, ma
; CHECK-RV64VC-NEXT: c.ntl.all
; CHECK-RV64VC-NEXT: vsoxei64.v v29, (zero), v8
; CHECK-RV64VC-NEXT: mv a1, a0
@@ -40301,22 +40301,22 @@ define void @test_nontemporal_vp_scatter_nxv64i8_DEFAULT(<vscale x 64 x i8> %val
; CHECK-RV32VC-LABEL: test_nontemporal_vp_scatter_nxv64i8_DEFAULT:
; CHECK-RV32VC: # %bb.0:
; CHECK-RV32VC-NEXT: csrr a1, vlenb
-; CHECK-RV32VC-NEXT: slli a6, a1, 4
+; CHECK-RV32VC-NEXT: slli a5, a1, 4
; CHECK-RV32VC-NEXT: slli a2, a1, 2
-; CHECK-RV32VC-NEXT: slli a5, a1, 3
+; CHECK-RV32VC-NEXT: slli a6, a1, 3
; CHECK-RV32VC-NEXT: mv a4, a3
; CHECK-RV32VC-NEXT: bltu a3, a2, .LBB919_2
; CHECK-RV32VC-NEXT: # %bb.1:
; CHECK-RV32VC-NEXT: mv a4, a2
; CHECK-RV32VC-NEXT: .LBB919_2:
; CHECK-RV32VC-NEXT: vl8re32.v v0, (a0)
-; CHECK-RV32VC-NEXT: add a6, a6, a0
+; CHECK-RV32VC-NEXT: add a5, a5, a0
; CHECK-RV32VC-NEXT: slli a1, a1, 1
-; CHECK-RV32VC-NEXT: add a0, a0, a5
-; CHECK-RV32VC-NEXT: mv a5, a4
+; CHECK-RV32VC-NEXT: add a0, a0, a6
+; CHECK-RV32VC-NEXT: mv a6, a4
; CHECK-RV32VC-NEXT: bltu a4, a1, .LBB919_4
; CHECK-RV32VC-NEXT: # %bb.3:
-; CHECK-RV32VC-NEXT: mv a5, a1
+; CHECK-RV32VC-NEXT: mv a6, a1
; CHECK-RV32VC-NEXT: .LBB919_4:
; CHECK-RV32VC-NEXT: addi sp, sp, -16
; CHECK-RV32VC-NEXT: .cfi_def_cfa_offset 16
@@ -40324,11 +40324,11 @@ define void @test_nontemporal_vp_scatter_nxv64i8_DEFAULT(<vscale x 64 x i8> %val
; CHECK-RV32VC-NEXT: slli a7, a7, 3
; CHECK-RV32VC-NEXT: sub sp, sp, a7
; CHECK-RV32VC-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
-; CHECK-RV32VC-NEXT: vl8re32.v v24, (a6)
-; CHECK-RV32VC-NEXT: addi a6, sp, 16
-; CHECK-RV32VC-NEXT: vs8r.v v24, (a6) # vscale x 64-byte Folded Spill
+; CHECK-RV32VC-NEXT: vl8re32.v v24, (a5)
+; CHECK-RV32VC-NEXT: addi a5, sp, 16
+; CHECK-RV32VC-NEXT: vs8r.v v24, (a5) # vscale x 64-byte Folded Spill
; CHECK-RV32VC-NEXT: vl8re32.v v24, (a0)
-; CHECK-RV32VC-NEXT: vsetvli zero, a5, e8, m2, ta, ma
+; CHECK-RV32VC-NEXT: vsetvli zero, a6, e8, m2, ta, ma
; CHECK-RV32VC-NEXT: c.ntl.all
; CHECK-RV32VC-NEXT: vsoxei32.v v8, (zero), v16
; CHECK-RV32VC-NEXT: sub a0, a4, a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr95865.ll b/llvm/test/CodeGen/RISCV/rvv/pr95865.ll
index 01d66b344ec2e..b6d8e06609e4e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/pr95865.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pr95865.ll
@@ -35,113 +35,113 @@ define i32 @main(i1 %arg.1, i64 %arg.2, i1 %arg.3, i64 %arg.4, i1 %arg.5, <vscal
; CHECK-NEXT: .cfi_offset s9, -88
; CHECK-NEXT: .cfi_offset s10, -96
; CHECK-NEXT: .cfi_offset s11, -104
-; CHECK-NEXT: li a6, 0
-; CHECK-NEXT: li s2, 8
-; CHECK-NEXT: li t0, 12
-; CHECK-NEXT: li s0, 4
-; CHECK-NEXT: li t1, 20
+; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: li a3, 8
+; CHECK-NEXT: li a5, 12
+; CHECK-NEXT: li a6, 4
+; CHECK-NEXT: li a7, 20
+; CHECK-NEXT: ld s0, 112(sp)
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
-; CHECK-NEXT: andi t3, a4, 1
-; CHECK-NEXT: li t2, 4
+; CHECK-NEXT: andi a4, a4, 1
+; CHECK-NEXT: li t0, 4
; CHECK-NEXT: .LBB0_1: # %for.cond1.preheader.i
; CHECK-NEXT: # =>This Loop Header: Depth=1
; CHECK-NEXT: # Child Loop BB0_2 Depth 2
; CHECK-NEXT: # Child Loop BB0_3 Depth 3
; CHECK-NEXT: # Child Loop BB0_4 Depth 4
; CHECK-NEXT: # Child Loop BB0_5 Depth 5
-; CHECK-NEXT: mv t4, t1
-; CHECK-NEXT: mv t5, t2
-; CHECK-NEXT: mv t6, t0
-; CHECK-NEXT: mv a7, s2
-; CHECK-NEXT: mv s4, a6
+; CHECK-NEXT: mv t1, a7
+; CHECK-NEXT: mv t2, t0
+; CHECK-NEXT: mv t3, a5
+; CHECK-NEXT: mv t4, a3
+; CHECK-NEXT: mv t5, a1
; CHECK-NEXT: .LBB0_2: # %for.cond5.preheader.i
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
; CHECK-NEXT: # => This Loop Header: Depth=2
; CHECK-NEXT: # Child Loop BB0_3 Depth 3
; CHECK-NEXT: # Child Loop BB0_4 Depth 4
; CHECK-NEXT: # Child Loop BB0_5 Depth 5
-; CHECK-NEXT: mv s5, t4
-; CHECK-NEXT: mv s6, t5
-; CHECK-NEXT: mv s7, t6
-; CHECK-NEXT: mv s3, a7
-; CHECK-NEXT: mv s9, s4
+; CHECK-NEXT: mv t6, t1
+; CHECK-NEXT: mv s1, t2
+; CHECK-NEXT: mv s2, t3
+; CHECK-NEXT: mv s3, t4
+; CHECK-NEXT: mv s4, t5
; CHECK-NEXT: .LBB0_3: # %for.cond9.preheader.i
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
; CHECK-NEXT: # Parent Loop BB0_2 Depth=2
; CHECK-NEXT: # => This Loop Header: Depth=3
; CHECK-NEXT: # Child Loop BB0_4 Depth 4
; CHECK-NEXT: # Child Loop BB0_5 Depth 5
-; CHECK-NEXT: mv s11, s5
-; CHECK-NEXT: mv a3, s6
-; CHECK-NEXT: mv ra, s7
-; CHECK-NEXT: mv s8, s3
-; CHECK-NEXT: mv s1, s9
+; CHECK-NEXT: mv s6, t6
+; CHECK-NEXT: mv s7, s1
+; CHECK-NEXT: mv s8, s2
+; CHECK-NEXT: mv s9, s3
+; CHECK-NEXT: mv s10, s4
; CHECK-NEXT: .LBB0_4: # %vector.ph.i
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
; CHECK-NEXT: # Parent Loop BB0_2 Depth=2
; CHECK-NEXT: # Parent Loop BB0_3 Depth=3
; CHECK-NEXT: # => This Loop Header: Depth=4
; CHECK-NEXT: # Child Loop BB0_5 Depth 5
-; CHECK-NEXT: li a1, 0
+; CHECK-NEXT: li s5, 0
; CHECK-NEXT: .LBB0_5: # %vector.body.i
; CHECK-NEXT: # Parent Loop BB0_1 Depth=1
; CHECK-NEXT: # Parent Loop BB0_2 Depth=2
; CHECK-NEXT: # Parent Loop BB0_3 Depth=3
; CHECK-NEXT: # Parent Loop BB0_4 Depth=4
; CHECK-NEXT: # => This Inner Loop Header: Depth=5
-; CHECK-NEXT: addi a5, a1, 4
-; CHECK-NEXT: add a4, s8, a1
-; CHECK-NEXT: add a1, a1, a3
-; CHECK-NEXT: vse32.v v8, (a4), v0.t
-; CHECK-NEXT: vse32.v v8, (a1), v0.t
-; CHECK-NEXT: mv a1, a5
-; CHECK-NEXT: bne a5, s0, .LBB0_5
+; CHECK-NEXT: addi s11, s5, 4
+; CHECK-NEXT: add ra, s9, s5
+; CHECK-NEXT: add s5, s5, s7
+; CHECK-NEXT: vse32.v v8, (ra), v0.t
+; CHECK-NEXT: vse32.v v8, (s5), v0.t
+; CHECK-NEXT: mv s5, s11
+; CHECK-NEXT: bne s11, a6, .LBB0_5
; CHECK-NEXT: # %bb.6: # %for.cond.cleanup15.i
; CHECK-NEXT: # in Loop: Header=BB0_4 Depth=4
-; CHECK-NEXT: addi s1, s1, 4
+; CHECK-NEXT: addi s10, s10, 4
+; CHECK-NEXT: addi s9, s9, 4
; CHECK-NEXT: addi s8, s8, 4
-; CHECK-NEXT: addi ra, ra, 4
-; CHECK-NEXT: addi a3, a3, 4
-; CHECK-NEXT: andi s10, a0, 1
-; CHECK-NEXT: addi s11, s11, 4
-; CHECK-NEXT: beqz s10, .LBB0_4
+; CHECK-NEXT: addi s7, s7, 4
+; CHECK-NEXT: andi s5, a0, 1
+; CHECK-NEXT: addi s6, s6, 4
+; CHECK-NEXT: beqz s5, .LBB0_4
; CHECK-NEXT: # %bb.7: # %for.cond.cleanup11.i
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=3
-; CHECK-NEXT: addi s9, s9, 4
+; CHECK-NEXT: addi s4, s4, 4
; CHECK-NEXT: addi s3, s3, 4
-; CHECK-NEXT: addi s7, s7, 4
-; CHECK-NEXT: addi s6, s6, 4
-; CHECK-NEXT: andi a1, a2, 1
-; CHECK-NEXT: addi s5, s5, 4
-; CHECK-NEXT: beqz a1, .LBB0_3
+; CHECK-NEXT: addi s2, s2, 4
+; CHECK-NEXT: addi s1, s1, 4
+; CHECK-NEXT: andi s6, a2, 1
+; CHECK-NEXT: addi t6, t6, 4
+; CHECK-NEXT: beqz s6, .LBB0_3
; CHECK-NEXT: # %bb.8: # %for.cond.cleanup7.i
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=2
-; CHECK-NEXT: addi s4, s4, 4
-; CHECK-NEXT: addi a7, a7, 4
-; CHECK-NEXT: addi t6, t6, 4
; CHECK-NEXT: addi t5, t5, 4
; CHECK-NEXT: addi t4, t4, 4
-; CHECK-NEXT: beqz t3, .LBB0_2
+; CHECK-NEXT: addi t3, t3, 4
+; CHECK-NEXT: addi t2, t2, 4
+; CHECK-NEXT: addi t1, t1, 4
+; CHECK-NEXT: beqz a4, .LBB0_2
; CHECK-NEXT: # %bb.9: # %for.cond.cleanup3.i
; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1
-; CHECK-NEXT: addi a6, a6, 4
-; CHECK-NEXT: addi s2, s2, 4
+; CHECK-NEXT: addi a1, a1, 4
+; CHECK-NEXT: addi a3, a3, 4
+; CHECK-NEXT: addi a5, a5, 4
; CHECK-NEXT: addi t0, t0, 4
-; CHECK-NEXT: addi t2, t2, 4
-; CHECK-NEXT: addi t1, t1, 4
-; CHECK-NEXT: beqz a1, .LBB0_1
+; CHECK-NEXT: addi a7, a7, 4
+; CHECK-NEXT: beqz s6, .LBB0_1
; CHECK-NEXT: # %bb.10: # %l.exit
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: jalr a0
-; CHECK-NEXT: beqz s10, .LBB0_12
+; CHECK-NEXT: beqz s5, .LBB0_12
; CHECK-NEXT: .LBB0_11: # %for.body7.us.14
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: j .LBB0_11
; CHECK-NEXT: .LBB0_12: # %for.body7.us.19
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-NEXT: ld a0, 112(sp)
-; CHECK-NEXT: vmv.s.x v16, a0
+; CHECK-NEXT: vmv.s.x v16, s0
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; CHECK-NEXT: vslideup.vi v8, v16, 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
index 60a291402b551..d5fe40ba558e4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
@@ -609,18 +609,18 @@ define void @vlmax(i64 %N, ptr %c, ptr %a, ptr %b) {
; CHECK-NEXT: blez a0, .LBB12_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: li a4, 0
-; CHECK-NEXT: vsetvli a6, zero, e64, m1, ta, ma
-; CHECK-NEXT: slli a5, a6, 3
+; CHECK-NEXT: vsetvli a5, zero, e64, m1, ta, ma
+; CHECK-NEXT: slli a6, a5, 3
; CHECK-NEXT: .LBB12_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vle64.v v8, (a2)
; CHECK-NEXT: vle64.v v9, (a3)
-; CHECK-NEXT: add a4, a4, a6
-; CHECK-NEXT: add a3, a3, a5
+; CHECK-NEXT: add a4, a4, a5
+; CHECK-NEXT: add a3, a3, a6
; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: vse64.v v8, (a1)
-; CHECK-NEXT: add a1, a1, a5
-; CHECK-NEXT: add a2, a2, a5
+; CHECK-NEXT: add a1, a1, a6
+; CHECK-NEXT: add a2, a2, a6
; CHECK-NEXT: blt a4, a0, .LBB12_2
; CHECK-NEXT: .LBB12_3: # %for.end
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
index 854d76c2d8544..2d0dcaa995bf1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert-out-of-loop.ll
@@ -171,40 +171,40 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV64P670-NEXT: .cfi_offset s2, -24
; RV64P670-NEXT: .cfi_offset s3, -32
; RV64P670-NEXT: .cfi_offset s4, -40
-; RV64P670-NEXT: addi s1, a7, -1
-; RV64P670-NEXT: add s0, a0, a6
+; RV64P670-NEXT: addi t2, a7, -1
+; RV64P670-NEXT: add t4, a0, a6
+; RV64P670-NEXT: add t5, a2, a6
; RV64P670-NEXT: li t0, 0
+; RV64P670-NEXT: zext.w t2, t2
; RV64P670-NEXT: li t1, 0
-; RV64P670-NEXT: zext.w s1, s1
-; RV64P670-NEXT: mul t2, a1, s1
-; RV64P670-NEXT: add t4, s0, t2
-; RV64P670-NEXT: mul t2, a3, s1
-; RV64P670-NEXT: add s0, a2, a6
-; RV64P670-NEXT: mul s1, a5, s1
-; RV64P670-NEXT: add t3, s0, t2
-; RV64P670-NEXT: add s0, a4, a6
+; RV64P670-NEXT: mul t3, a1, t2
+; RV64P670-NEXT: add t4, t4, t3
+; RV64P670-NEXT: mul t3, a3, t2
+; RV64P670-NEXT: mul t2, a5, t2
+; RV64P670-NEXT: sltu t6, a2, t4
+; RV64P670-NEXT: sltu t4, a4, t4
+; RV64P670-NEXT: add t3, t3, t5
+; RV64P670-NEXT: add t5, a4, a6
+; RV64P670-NEXT: add t5, t5, t2
+; RV64P670-NEXT: sltu t3, a0, t3
; RV64P670-NEXT: csrr t2, vlenb
-; RV64P670-NEXT: add t5, s0, s1
-; RV64P670-NEXT: sltu s1, a0, t3
-; RV64P670-NEXT: sltu s0, a2, t4
+; RV64P670-NEXT: sltu t5, a0, t5
+; RV64P670-NEXT: and t3, t3, t6
+; RV64P670-NEXT: or t6, a1, a3
+; RV64P670-NEXT: and t4, t5, t4
+; RV64P670-NEXT: or t5, a1, a5
+; RV64P670-NEXT: srli t6, t6, 63
+; RV64P670-NEXT: srli t5, t5, 63
+; RV64P670-NEXT: or t6, t3, t6
; RV64P670-NEXT: slli t3, t2, 1
-; RV64P670-NEXT: and s0, s0, s1
-; RV64P670-NEXT: or s1, a1, a3
-; RV64P670-NEXT: srli s1, s1, 63
-; RV64P670-NEXT: or t6, s0, s1
-; RV64P670-NEXT: sltu s1, a0, t5
-; RV64P670-NEXT: sltu s0, a4, t4
+; RV64P670-NEXT: or t4, t4, t5
+; RV64P670-NEXT: li t5, 32
+; RV64P670-NEXT: maxu t5, t3, t5
+; RV64P670-NEXT: or t6, t6, t4
; RV64P670-NEXT: add t4, a0, a6
-; RV64P670-NEXT: and s0, s0, s1
-; RV64P670-NEXT: or s1, a1, a5
-; RV64P670-NEXT: srli s1, s1, 63
-; RV64P670-NEXT: or s0, s0, s1
-; RV64P670-NEXT: li s1, 32
-; RV64P670-NEXT: maxu s1, t3, s1
-; RV64P670-NEXT: or s0, t6, s0
-; RV64P670-NEXT: sltu s1, a6, s1
-; RV64P670-NEXT: or s0, s0, s1
-; RV64P670-NEXT: andi t5, s0, 1
+; RV64P670-NEXT: sltu t5, a6, t5
+; RV64P670-NEXT: or t5, t5, t6
+; RV64P670-NEXT: andi t5, t5, 1
; RV64P670-NEXT: j .LBB0_4
; RV64P670-NEXT: .LBB0_3: # %for.cond1.for.cond.cleanup3_crit_edge.us
; RV64P670-NEXT: # in Loop: Header=BB0_4 Depth=1
@@ -224,49 +224,49 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV64P670-NEXT: j .LBB0_9
; RV64P670-NEXT: .LBB0_6: # %vector.ph
; RV64P670-NEXT: # in Loop: Header=BB0_4 Depth=1
-; RV64P670-NEXT: slli s1, t2, 28
-; RV64P670-NEXT: mv s2, a2
-; RV64P670-NEXT: mv s3, a4
-; RV64P670-NEXT: mv s4, a0
-; RV64P670-NEXT: sub s1, s1, t3
-; RV64P670-NEXT: vsetvli s0, zero, e8, m2, ta, ma
-; RV64P670-NEXT: and t6, s1, a6
-; RV64P670-NEXT: mv s1, t6
+; RV64P670-NEXT: slli t6, t2, 28
+; RV64P670-NEXT: mv s0, a2
+; RV64P670-NEXT: mv s1, a4
+; RV64P670-NEXT: mv s2, a0
+; RV64P670-NEXT: sub t6, t6, t3
+; RV64P670-NEXT: vsetvli s4, zero, e8, m2, ta, ma
+; RV64P670-NEXT: and t6, t6, a6
+; RV64P670-NEXT: mv s3, t6
; RV64P670-NEXT: .LBB0_7: # %vector.body
; RV64P670-NEXT: # Parent Loop BB0_4 Depth=1
; RV64P670-NEXT: # => This Inner Loop Header: Depth=2
-; RV64P670-NEXT: vl2r.v v8, (s2)
-; RV64P670-NEXT: sub s1, s1, t3
-; RV64P670-NEXT: add s2, s2, t3
-; RV64P670-NEXT: vl2r.v v10, (s3)
-; RV64P670-NEXT: add s3, s3, t3
+; RV64P670-NEXT: vl2r.v v8, (s0)
+; RV64P670-NEXT: sub s3, s3, t3
+; RV64P670-NEXT: add s0, s0, t3
+; RV64P670-NEXT: vl2r.v v10, (s1)
+; RV64P670-NEXT: add s1, s1, t3
; RV64P670-NEXT: vaaddu.vv v8, v8, v10
-; RV64P670-NEXT: vs2r.v v8, (s4)
-; RV64P670-NEXT: add s4, s4, t3
-; RV64P670-NEXT: bnez s1, .LBB0_7
+; RV64P670-NEXT: vs2r.v v8, (s2)
+; RV64P670-NEXT: add s2, s2, t3
+; RV64P670-NEXT: bnez s3, .LBB0_7
; RV64P670-NEXT: # %bb.8: # %middle.block
; RV64P670-NEXT: # in Loop: Header=BB0_4 Depth=1
; RV64P670-NEXT: beq t6, a6, .LBB0_3
; RV64P670-NEXT: .LBB0_9: # %for.body4.us.preheader
; RV64P670-NEXT: # in Loop: Header=BB0_4 Depth=1
-; RV64P670-NEXT: mul s2, a1, t0
+; RV64P670-NEXT: mul s0, a1, t0
; RV64P670-NEXT: add s1, a0, t6
-; RV64P670-NEXT: add s4, a4, t6
+; RV64P670-NEXT: add s2, a4, t6
; RV64P670-NEXT: add t6, t6, a2
-; RV64P670-NEXT: add s2, s2, t4
+; RV64P670-NEXT: add s0, s0, t4
; RV64P670-NEXT: .LBB0_10: # %for.body4.us
; RV64P670-NEXT: # Parent Loop BB0_4 Depth=1
; RV64P670-NEXT: # => This Inner Loop Header: Depth=2
; RV64P670-NEXT: lbu s3, 0(t6)
-; RV64P670-NEXT: lbu s0, 0(s4)
-; RV64P670-NEXT: addi s4, s4, 1
+; RV64P670-NEXT: lbu s4, 0(s2)
+; RV64P670-NEXT: addi s2, s2, 1
; RV64P670-NEXT: addi t6, t6, 1
-; RV64P670-NEXT: add s0, s0, s3
-; RV64P670-NEXT: addi s0, s0, 1
-; RV64P670-NEXT: srli s0, s0, 1
-; RV64P670-NEXT: sb s0, 0(s1)
+; RV64P670-NEXT: add s3, s3, s4
+; RV64P670-NEXT: addi s3, s3, 1
+; RV64P670-NEXT: srli s3, s3, 1
+; RV64P670-NEXT: sb s3, 0(s1)
; RV64P670-NEXT: addi s1, s1, 1
-; RV64P670-NEXT: bne s1, s2, .LBB0_10
+; RV64P670-NEXT: bne s1, s0, .LBB0_10
; RV64P670-NEXT: j .LBB0_3
; RV64P670-NEXT: .LBB0_11:
; RV64P670-NEXT: ld s0, 40(sp) # 8-byte Folded Reload
@@ -305,38 +305,38 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV64X60-NEXT: .cfi_offset s0, -8
; RV64X60-NEXT: li t0, 0
; RV64X60-NEXT: li t1, 0
-; RV64X60-NEXT: addi s1, a7, -1
-; RV64X60-NEXT: zext.w s1, s1
-; RV64X60-NEXT: mul t3, a1, s1
-; RV64X60-NEXT: mul t5, a3, s1
-; RV64X60-NEXT: mul t4, a5, s1
-; RV64X60-NEXT: add s1, a0, a6
+; RV64X60-NEXT: addi t2, a7, -1
+; RV64X60-NEXT: zext.w t2, t2
+; RV64X60-NEXT: mul t3, a1, t2
+; RV64X60-NEXT: mul t4, a3, t2
+; RV64X60-NEXT: mul t5, a5, t2
+; RV64X60-NEXT: add t6, a0, a6
; RV64X60-NEXT: csrr t2, vlenb
; RV64X60-NEXT: add s0, a2, a6
-; RV64X60-NEXT: add s2, s1, t3
+; RV64X60-NEXT: add t6, t6, t3
; RV64X60-NEXT: add t3, a4, a6
-; RV64X60-NEXT: add t5, t5, s0
-; RV64X60-NEXT: or t6, a1, a3
-; RV64X60-NEXT: add t4, t4, t3
-; RV64X60-NEXT: sltu s0, a0, t5
-; RV64X60-NEXT: sltu s1, a2, s2
-; RV64X60-NEXT: and t5, s0, s1
+; RV64X60-NEXT: add t4, t4, s0
+; RV64X60-NEXT: or s0, a1, a3
+; RV64X60-NEXT: add t5, t5, t3
+; RV64X60-NEXT: sltu t3, a0, t4
+; RV64X60-NEXT: sltu t4, a2, t6
+; RV64X60-NEXT: and t4, t3, t4
; RV64X60-NEXT: slli t3, t2, 1
-; RV64X60-NEXT: sltu t4, a0, t4
-; RV64X60-NEXT: sltu s0, a4, s2
-; RV64X60-NEXT: srli s1, t6, 63
-; RV64X60-NEXT: and s0, t4, s0
-; RV64X60-NEXT: or t4, t5, s1
-; RV64X60-NEXT: or s1, a1, a5
-; RV64X60-NEXT: li t5, 32
-; RV64X60-NEXT: srli s1, s1, 63
-; RV64X60-NEXT: or s0, s0, s1
-; RV64X60-NEXT: maxu s1, t3, t5
-; RV64X60-NEXT: or s0, t4, s0
-; RV64X60-NEXT: sltu s1, a6, s1
-; RV64X60-NEXT: or s0, s0, s1
+; RV64X60-NEXT: sltu t5, a0, t5
+; RV64X60-NEXT: sltu t6, a4, t6
+; RV64X60-NEXT: srli s0, s0, 63
+; RV64X60-NEXT: and t5, t5, t6
+; RV64X60-NEXT: or t4, t4, s0
+; RV64X60-NEXT: or t6, a1, a5
+; RV64X60-NEXT: li s0, 32
+; RV64X60-NEXT: srli t6, t6, 63
+; RV64X60-NEXT: or t5, t5, t6
+; RV64X60-NEXT: maxu t6, t3, s0
+; RV64X60-NEXT: or t4, t4, t5
+; RV64X60-NEXT: sltu t5, a6, t6
+; RV64X60-NEXT: or t5, t5, t4
; RV64X60-NEXT: add t4, a0, a6
-; RV64X60-NEXT: andi t5, s0, 1
+; RV64X60-NEXT: andi t5, t5, 1
; RV64X60-NEXT: j .LBB0_4
; RV64X60-NEXT: .LBB0_3: # %for.cond1.for.cond.cleanup3_crit_edge.us
; RV64X60-NEXT: # in Loop: Header=BB0_4 Depth=1
@@ -356,49 +356,49 @@ define void @test1(ptr nocapture noundef writeonly %dst, i32 noundef signext %i_
; RV64X60-NEXT: j .LBB0_9
; RV64X60-NEXT: .LBB0_6: # %vector.ph
; RV64X60-NEXT: # in Loop: Header=BB0_4 Depth=1
-; RV64X60-NEXT: slli s1, t2, 28
-; RV64X60-NEXT: sub s1, s1, t3
-; RV64X60-NEXT: and t6, s1, a6
-; RV64X60-NEXT: mv s2, a2
-; RV64X60-NEXT: mv s3, a4
-; RV64X60-NEXT: mv s4, a0
-; RV64X60-NEXT: mv s1, t6
-; RV64X60-NEXT: vsetvli s0, zero, e8, m2, ta, ma
+; RV64X60-NEXT: slli t6, t2, 28
+; RV64X60-NEXT: sub t6, t6, t3
+; RV64X60-NEXT: and t6, t6, a6
+; RV64X60-NEXT: mv s0, a2
+; RV64X60-NEXT: mv s1, a4
+; RV64X60-NEXT: mv s2, a0
+; RV64X60-NEXT: mv s3, t6
+; RV64X60-NEXT: vsetvli s4, zero, e8, m2, ta, ma
; RV64X60-NEXT: .LBB0_7: # %vector.body
; RV64X60-NEXT: # Parent Loop BB0_4 Depth=1
; RV64X60-NEXT: # => This Inner Loop Header: Depth=2
-; RV64X60-NEXT: vl2r.v v8, (s2)
-; RV64X60-NEXT: vl2r.v v10, (s3)
+; RV64X60-NEXT: vl2r.v v8, (s0)
+; RV64X60-NEXT: vl2r.v v10, (s1)
; RV64X60-NEXT: vaaddu.vv v8, v8, v10
-; RV64X60-NEXT: sub s1, s1, t3
-; RV64X60-NEXT: vs2r.v v8, (s4)
-; RV64X60-NEXT: add s4, s4, t3
-; RV64X60-NEXT: add s3, s3, t3
+; RV64X60-NEXT: sub s3, s3, t3
+; RV64X60-NEXT: vs2r.v v8, (s2)
; RV64X60-NEXT: add s2, s2, t3
-; RV64X60-NEXT: bnez s1, .LBB0_7
+; RV64X60-NEXT: add s1, s1, t3
+; RV64X60-NEXT: add s0, s0, t3
+; RV64X60-NEXT: bnez s3, .LBB0_7
; RV64X60-NEXT: # %bb.8: # %middle.block
; RV64X60-NEXT: # in Loop: Header=BB0_4 Depth=1
; RV64X60-NEXT: beq t6, a6, .LBB0_3
; RV64X60-NEXT: .LBB0_9: # %for.body4.us.preheader
; RV64X60-NEXT: # in Loop: Header=BB0_4 Depth=1
-; RV64X60-NEXT: mul s2, a1, t0
+; RV64X60-NEXT: mul s1, a1, t0
; RV64X60-NEXT: add s0, a0, t6
-; RV64X60-NEXT: add s2, s2, t4
-; RV64X60-NEXT: add s4, a4, t6
+; RV64X60-NEXT: add s1, s1, t4
+; RV64X60-NEXT: add s2, a4, t6
; RV64X60-NEXT: add t6, t6, a2
; RV64X60-NEXT: .LBB0_10: # %for.body4.us
; RV64X60-NEXT: # Parent Loop BB0_4 Depth=1
; RV64X60-NEXT: # => This Inner Loop Header: Depth=2
; RV64X60-NEXT: lbu s3, 0(t6)
-; RV64X60-NEXT: lbu s1, 0(s4)
-; RV64X60-NEXT: add s1, s1, s3
-; RV64X60-NEXT: addi s1, s1, 1
-; RV64X60-NEXT: srli s1, s1, 1
-; RV64X60-NEXT: sb s1, 0(s0)
+; RV64X60-NEXT: lbu s4, 0(s2)
+; RV64X60-NEXT: add s3, s3, s4
+; RV64X60-NEXT: addi s3, s3, 1
+; RV64X60-NEXT: srli s3, s3, 1
+; RV64X60-NEXT: sb s3, 0(s0)
; RV64X60-NEXT: addi s0, s0, 1
-; RV64X60-NEXT: addi s4, s4, 1
+; RV64X60-NEXT: addi s2, s2, 1
; RV64X60-NEXT: addi t6, t6, 1
-; RV64X60-NEXT: bne s0, s2, .LBB0_10
+; RV64X60-NEXT: bne s0, s1, .LBB0_10
; RV64X60-NEXT: j .LBB0_3
; RV64X60-NEXT: .LBB0_11:
; RV64X60-NEXT: ld s4, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
index 299fe89a05328..2a6965084bba7 100644
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -466,12 +466,12 @@ define i64 @select_sge_int32min(i64 %x, i64 %y, i64 %z) {
;
; RV32IXQCI-LABEL: select_sge_int32min:
; RV32IXQCI: # %bb.0:
-; RV32IXQCI-NEXT: srli a6, a0, 31
-; RV32IXQCI-NEXT: srli a0, a1, 31
-; RV32IXQCI-NEXT: xori a0, a0, 1
-; RV32IXQCI-NEXT: qc.mveqi a0, a1, -1, a6
-; RV32IXQCI-NEXT: qc.mveqi a2, a0, 0, a4
-; RV32IXQCI-NEXT: qc.mveqi a3, a0, 0, a5
+; RV32IXQCI-NEXT: srli a0, a0, 31
+; RV32IXQCI-NEXT: srli a6, a1, 31
+; RV32IXQCI-NEXT: xori a6, a6, 1
+; RV32IXQCI-NEXT: qc.mveqi a6, a1, -1, a0
+; RV32IXQCI-NEXT: qc.mveqi a2, a6, 0, a4
+; RV32IXQCI-NEXT: qc.mveqi a3, a6, 0, a5
; RV32IXQCI-NEXT: mv a0, a2
; RV32IXQCI-NEXT: mv a1, a3
; RV32IXQCI-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll b/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
index 595bd49d578ee..480acf4ae0f53 100644
--- a/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
+++ b/llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
@@ -43,60 +43,60 @@ define void @callee() {
; RV32IXQCCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; RV32IXQCCMP-NEXT: lw a1, 16(a0)
; RV32IXQCCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw t3, 20(a0)
-; RV32IXQCCMP-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-NEXT: lw t6, 32(a0)
-; RV32IXQCCMP-NEXT: lw s2, 36(a0)
-; RV32IXQCCMP-NEXT: lw s3, 40(a0)
-; RV32IXQCCMP-NEXT: lw s4, 44(a0)
-; RV32IXQCCMP-NEXT: lw s5, 48(a0)
-; RV32IXQCCMP-NEXT: lw s6, 52(a0)
-; RV32IXQCCMP-NEXT: lw s7, 56(a0)
-; RV32IXQCCMP-NEXT: lw s8, 60(a0)
-; RV32IXQCCMP-NEXT: lw s9, 64(a0)
-; RV32IXQCCMP-NEXT: lw s10, 68(a0)
-; RV32IXQCCMP-NEXT: lw s11, 72(a0)
-; RV32IXQCCMP-NEXT: lw ra, 76(a0)
-; RV32IXQCCMP-NEXT: lw t2, 80(a0)
-; RV32IXQCCMP-NEXT: lw s0, 84(a0)
-; RV32IXQCCMP-NEXT: lw s1, 88(a0)
-; RV32IXQCCMP-NEXT: lw t1, 92(a0)
-; RV32IXQCCMP-NEXT: lw t0, 112(a0)
-; RV32IXQCCMP-NEXT: lw a5, 116(a0)
-; RV32IXQCCMP-NEXT: lw a3, 120(a0)
+; RV32IXQCCMP-NEXT: lw a6, 20(a0)
+; RV32IXQCCMP-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-NEXT: lw t1, 32(a0)
+; RV32IXQCCMP-NEXT: lw t2, 36(a0)
+; RV32IXQCCMP-NEXT: lw t3, 40(a0)
+; RV32IXQCCMP-NEXT: lw t4, 44(a0)
+; RV32IXQCCMP-NEXT: lw t5, 48(a0)
+; RV32IXQCCMP-NEXT: lw t6, 52(a0)
+; RV32IXQCCMP-NEXT: lw s0, 56(a0)
+; RV32IXQCCMP-NEXT: lw s1, 60(a0)
+; RV32IXQCCMP-NEXT: lw s2, 64(a0)
+; RV32IXQCCMP-NEXT: lw s3, 68(a0)
+; RV32IXQCCMP-NEXT: lw s4, 72(a0)
+; RV32IXQCCMP-NEXT: lw s5, 76(a0)
+; RV32IXQCCMP-NEXT: lw s6, 80(a0)
+; RV32IXQCCMP-NEXT: lw s7, 84(a0)
+; RV32IXQCCMP-NEXT: lw s8, 88(a0)
+; RV32IXQCCMP-NEXT: lw s9, 92(a0)
+; RV32IXQCCMP-NEXT: lw s10, 112(a0)
+; RV32IXQCCMP-NEXT: lw s11, 116(a0)
+; RV32IXQCCMP-NEXT: lw ra, 120(a0)
; RV32IXQCCMP-NEXT: lw a1, 124(a0)
-; RV32IXQCCMP-NEXT: lw a7, 96(a0)
-; RV32IXQCCMP-NEXT: lw a6, 100(a0)
-; RV32IXQCCMP-NEXT: lw a4, 104(a0)
+; RV32IXQCCMP-NEXT: lw a5, 96(a0)
+; RV32IXQCCMP-NEXT: lw a4, 100(a0)
+; RV32IXQCCMP-NEXT: lw a3, 104(a0)
; RV32IXQCCMP-NEXT: lw a2, 108(a0)
; RV32IXQCCMP-NEXT: sw a1, 124(a0)
-; RV32IXQCCMP-NEXT: sw a3, 120(a0)
-; RV32IXQCCMP-NEXT: sw a5, 116(a0)
-; RV32IXQCCMP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-NEXT: sw ra, 120(a0)
+; RV32IXQCCMP-NEXT: sw s11, 116(a0)
+; RV32IXQCCMP-NEXT: sw s10, 112(a0)
; RV32IXQCCMP-NEXT: sw a2, 108(a0)
-; RV32IXQCCMP-NEXT: sw a4, 104(a0)
-; RV32IXQCCMP-NEXT: sw a6, 100(a0)
-; RV32IXQCCMP-NEXT: sw a7, 96(a0)
-; RV32IXQCCMP-NEXT: sw t1, 92(a0)
-; RV32IXQCCMP-NEXT: sw s1, 88(a0)
-; RV32IXQCCMP-NEXT: sw s0, 84(a0)
-; RV32IXQCCMP-NEXT: sw t2, 80(a0)
-; RV32IXQCCMP-NEXT: sw ra, 76(a0)
-; RV32IXQCCMP-NEXT: sw s11, 72(a0)
-; RV32IXQCCMP-NEXT: sw s10, 68(a0)
-; RV32IXQCCMP-NEXT: sw s9, 64(a0)
-; RV32IXQCCMP-NEXT: sw s8, 60(a0)
-; RV32IXQCCMP-NEXT: sw s7, 56(a0)
-; RV32IXQCCMP-NEXT: sw s6, 52(a0)
-; RV32IXQCCMP-NEXT: sw s5, 48(a0)
-; RV32IXQCCMP-NEXT: sw s4, 44(a0)
-; RV32IXQCCMP-NEXT: sw s3, 40(a0)
-; RV32IXQCCMP-NEXT: sw s2, 36(a0)
-; RV32IXQCCMP-NEXT: sw t6, 32(a0)
-; RV32IXQCCMP-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-NEXT: sw t4, 24(a0)
-; RV32IXQCCMP-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-NEXT: sw a3, 104(a0)
+; RV32IXQCCMP-NEXT: sw a4, 100(a0)
+; RV32IXQCCMP-NEXT: sw a5, 96(a0)
+; RV32IXQCCMP-NEXT: sw s9, 92(a0)
+; RV32IXQCCMP-NEXT: sw s8, 88(a0)
+; RV32IXQCCMP-NEXT: sw s7, 84(a0)
+; RV32IXQCCMP-NEXT: sw s6, 80(a0)
+; RV32IXQCCMP-NEXT: sw s5, 76(a0)
+; RV32IXQCCMP-NEXT: sw s4, 72(a0)
+; RV32IXQCCMP-NEXT: sw s3, 68(a0)
+; RV32IXQCCMP-NEXT: sw s2, 64(a0)
+; RV32IXQCCMP-NEXT: sw s1, 60(a0)
+; RV32IXQCCMP-NEXT: sw s0, 56(a0)
+; RV32IXQCCMP-NEXT: sw t6, 52(a0)
+; RV32IXQCCMP-NEXT: sw t5, 48(a0)
+; RV32IXQCCMP-NEXT: sw t4, 44(a0)
+; RV32IXQCCMP-NEXT: sw t3, 40(a0)
+; RV32IXQCCMP-NEXT: sw t2, 36(a0)
+; RV32IXQCCMP-NEXT: sw t1, 32(a0)
+; RV32IXQCCMP-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-NEXT: sw a7, 24(a0)
+; RV32IXQCCMP-NEXT: sw a6, 20(a0)
; RV32IXQCCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; RV32IXQCCMP-NEXT: sw a1, 16(a0)
; RV32IXQCCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -141,58 +141,58 @@ define void @callee() {
; RV32IXQCCMP-WITH-FP-NEXT: sw a1, -84(s0) # 4-byte Folded Spill
; RV32IXQCCMP-WITH-FP-NEXT: lw a1, 20(a0)
; RV32IXQCCMP-WITH-FP-NEXT: sw a1, -88(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-WITH-FP-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t6, 32(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s2, 36(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s3, 40(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s4, 44(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s5, 48(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s6, 52(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s7, 56(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s8, 60(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s9, 64(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s10, 68(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s11, 72(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw ra, 76(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw s1, 80(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t3, 84(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t2, 88(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t1, 92(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw t0, 112(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a6, 116(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t1, 32(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t2, 36(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t3, 40(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t4, 44(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t5, 48(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw t6, 52(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s1, 56(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s2, 60(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s3, 64(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s4, 68(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s5, 72(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s6, 76(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s7, 80(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s8, 84(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s9, 88(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s10, 92(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw s11, 112(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw ra, 116(a0)
; RV32IXQCCMP-WITH-FP-NEXT: lw a4, 120(a0)
; RV32IXQCCMP-WITH-FP-NEXT: lw a1, 124(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: lw a6, 96(a0)
; RV32IXQCCMP-WITH-FP-NEXT: lw a5, 100(a0)
; RV32IXQCCMP-WITH-FP-NEXT: lw a3, 104(a0)
; RV32IXQCCMP-WITH-FP-NEXT: lw a2, 108(a0)
; RV32IXQCCMP-WITH-FP-NEXT: sw a1, 124(a0)
; RV32IXQCCMP-WITH-FP-NEXT: sw a4, 120(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a6, 116(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw ra, 116(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s11, 112(a0)
; RV32IXQCCMP-WITH-FP-NEXT: sw a2, 108(a0)
; RV32IXQCCMP-WITH-FP-NEXT: sw a3, 104(a0)
; RV32IXQCCMP-WITH-FP-NEXT: sw a5, 100(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw a7, 96(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t1, 92(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t2, 88(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t3, 84(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s1, 80(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw ra, 76(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s11, 72(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s10, 68(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s9, 64(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s8, 60(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s7, 56(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s6, 52(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s5, 48(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s4, 44(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s3, 40(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw s2, 36(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t6, 32(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-WITH-FP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a6, 96(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s10, 92(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s9, 88(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s8, 84(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s7, 80(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s6, 76(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s5, 72(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s4, 68(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s3, 64(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s2, 60(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw s1, 56(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t6, 52(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t5, 48(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t4, 44(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t3, 40(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t2, 36(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t1, 32(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-WITH-FP-NEXT: sw a7, 24(a0)
; RV32IXQCCMP-WITH-FP-NEXT: lw a1, -88(s0) # 4-byte Folded Reload
; RV32IXQCCMP-WITH-FP-NEXT: sw a1, 20(a0)
; RV32IXQCCMP-WITH-FP-NEXT: lw a1, -84(s0) # 4-byte Folded Reload
@@ -237,60 +237,60 @@ define void @callee() {
; RV64IXQCCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
; RV64IXQCCMP-NEXT: lw a1, 16(a0)
; RV64IXQCCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw t3, 20(a0)
-; RV64IXQCCMP-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-NEXT: lw t6, 32(a0)
-; RV64IXQCCMP-NEXT: lw s2, 36(a0)
-; RV64IXQCCMP-NEXT: lw s3, 40(a0)
-; RV64IXQCCMP-NEXT: lw s4, 44(a0)
-; RV64IXQCCMP-NEXT: lw s5, 48(a0)
-; RV64IXQCCMP-NEXT: lw s6, 52(a0)
-; RV64IXQCCMP-NEXT: lw s7, 56(a0)
-; RV64IXQCCMP-NEXT: lw s8, 60(a0)
-; RV64IXQCCMP-NEXT: lw s9, 64(a0)
-; RV64IXQCCMP-NEXT: lw s10, 68(a0)
-; RV64IXQCCMP-NEXT: lw s11, 72(a0)
-; RV64IXQCCMP-NEXT: lw ra, 76(a0)
-; RV64IXQCCMP-NEXT: lw t2, 80(a0)
-; RV64IXQCCMP-NEXT: lw s0, 84(a0)
-; RV64IXQCCMP-NEXT: lw s1, 88(a0)
-; RV64IXQCCMP-NEXT: lw t1, 92(a0)
-; RV64IXQCCMP-NEXT: lw t0, 112(a0)
-; RV64IXQCCMP-NEXT: lw a5, 116(a0)
-; RV64IXQCCMP-NEXT: lw a3, 120(a0)
+; RV64IXQCCMP-NEXT: lw a6, 20(a0)
+; RV64IXQCCMP-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-NEXT: lw t1, 32(a0)
+; RV64IXQCCMP-NEXT: lw t2, 36(a0)
+; RV64IXQCCMP-NEXT: lw t3, 40(a0)
+; RV64IXQCCMP-NEXT: lw t4, 44(a0)
+; RV64IXQCCMP-NEXT: lw t5, 48(a0)
+; RV64IXQCCMP-NEXT: lw t6, 52(a0)
+; RV64IXQCCMP-NEXT: lw s0, 56(a0)
+; RV64IXQCCMP-NEXT: lw s1, 60(a0)
+; RV64IXQCCMP-NEXT: lw s2, 64(a0)
+; RV64IXQCCMP-NEXT: lw s3, 68(a0)
+; RV64IXQCCMP-NEXT: lw s4, 72(a0)
+; RV64IXQCCMP-NEXT: lw s5, 76(a0)
+; RV64IXQCCMP-NEXT: lw s6, 80(a0)
+; RV64IXQCCMP-NEXT: lw s7, 84(a0)
+; RV64IXQCCMP-NEXT: lw s8, 88(a0)
+; RV64IXQCCMP-NEXT: lw s9, 92(a0)
+; RV64IXQCCMP-NEXT: lw s10, 112(a0)
+; RV64IXQCCMP-NEXT: lw s11, 116(a0)
+; RV64IXQCCMP-NEXT: lw ra, 120(a0)
; RV64IXQCCMP-NEXT: lw a1, 124(a0)
-; RV64IXQCCMP-NEXT: lw a7, 96(a0)
-; RV64IXQCCMP-NEXT: lw a6, 100(a0)
-; RV64IXQCCMP-NEXT: lw a4, 104(a0)
+; RV64IXQCCMP-NEXT: lw a5, 96(a0)
+; RV64IXQCCMP-NEXT: lw a4, 100(a0)
+; RV64IXQCCMP-NEXT: lw a3, 104(a0)
; RV64IXQCCMP-NEXT: lw a2, 108(a0)
; RV64IXQCCMP-NEXT: sw a1, 124(a0)
-; RV64IXQCCMP-NEXT: sw a3, 120(a0)
-; RV64IXQCCMP-NEXT: sw a5, 116(a0)
-; RV64IXQCCMP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-NEXT: sw ra, 120(a0)
+; RV64IXQCCMP-NEXT: sw s11, 116(a0)
+; RV64IXQCCMP-NEXT: sw s10, 112(a0)
; RV64IXQCCMP-NEXT: sw a2, 108(a0)
-; RV64IXQCCMP-NEXT: sw a4, 104(a0)
-; RV64IXQCCMP-NEXT: sw a6, 100(a0)
-; RV64IXQCCMP-NEXT: sw a7, 96(a0)
-; RV64IXQCCMP-NEXT: sw t1, 92(a0)
-; RV64IXQCCMP-NEXT: sw s1, 88(a0)
-; RV64IXQCCMP-NEXT: sw s0, 84(a0)
-; RV64IXQCCMP-NEXT: sw t2, 80(a0)
-; RV64IXQCCMP-NEXT: sw ra, 76(a0)
-; RV64IXQCCMP-NEXT: sw s11, 72(a0)
-; RV64IXQCCMP-NEXT: sw s10, 68(a0)
-; RV64IXQCCMP-NEXT: sw s9, 64(a0)
-; RV64IXQCCMP-NEXT: sw s8, 60(a0)
-; RV64IXQCCMP-NEXT: sw s7, 56(a0)
-; RV64IXQCCMP-NEXT: sw s6, 52(a0)
-; RV64IXQCCMP-NEXT: sw s5, 48(a0)
-; RV64IXQCCMP-NEXT: sw s4, 44(a0)
-; RV64IXQCCMP-NEXT: sw s3, 40(a0)
-; RV64IXQCCMP-NEXT: sw s2, 36(a0)
-; RV64IXQCCMP-NEXT: sw t6, 32(a0)
-; RV64IXQCCMP-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-NEXT: sw t4, 24(a0)
-; RV64IXQCCMP-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-NEXT: sw a3, 104(a0)
+; RV64IXQCCMP-NEXT: sw a4, 100(a0)
+; RV64IXQCCMP-NEXT: sw a5, 96(a0)
+; RV64IXQCCMP-NEXT: sw s9, 92(a0)
+; RV64IXQCCMP-NEXT: sw s8, 88(a0)
+; RV64IXQCCMP-NEXT: sw s7, 84(a0)
+; RV64IXQCCMP-NEXT: sw s6, 80(a0)
+; RV64IXQCCMP-NEXT: sw s5, 76(a0)
+; RV64IXQCCMP-NEXT: sw s4, 72(a0)
+; RV64IXQCCMP-NEXT: sw s3, 68(a0)
+; RV64IXQCCMP-NEXT: sw s2, 64(a0)
+; RV64IXQCCMP-NEXT: sw s1, 60(a0)
+; RV64IXQCCMP-NEXT: sw s0, 56(a0)
+; RV64IXQCCMP-NEXT: sw t6, 52(a0)
+; RV64IXQCCMP-NEXT: sw t5, 48(a0)
+; RV64IXQCCMP-NEXT: sw t4, 44(a0)
+; RV64IXQCCMP-NEXT: sw t3, 40(a0)
+; RV64IXQCCMP-NEXT: sw t2, 36(a0)
+; RV64IXQCCMP-NEXT: sw t1, 32(a0)
+; RV64IXQCCMP-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-NEXT: sw a7, 24(a0)
+; RV64IXQCCMP-NEXT: sw a6, 20(a0)
; RV64IXQCCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
; RV64IXQCCMP-NEXT: sw a1, 16(a0)
; RV64IXQCCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
@@ -335,58 +335,58 @@ define void @callee() {
; RV64IXQCCMP-WITH-FP-NEXT: sd a1, -152(s0) # 8-byte Folded Spill
; RV64IXQCCMP-WITH-FP-NEXT: lw a1, 20(a0)
; RV64IXQCCMP-WITH-FP-NEXT: sd a1, -160(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-WITH-FP-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t6, 32(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s2, 36(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s3, 40(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s4, 44(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s5, 48(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s6, 52(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s7, 56(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s8, 60(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s9, 64(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s10, 68(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s11, 72(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw ra, 76(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw s1, 80(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t3, 84(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t2, 88(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t1, 92(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw t0, 112(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a6, 116(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t1, 32(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t2, 36(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t3, 40(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t4, 44(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t5, 48(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw t6, 52(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s1, 56(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s2, 60(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s3, 64(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s4, 68(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s5, 72(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s6, 76(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s7, 80(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s8, 84(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s9, 88(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s10, 92(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw s11, 112(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw ra, 116(a0)
; RV64IXQCCMP-WITH-FP-NEXT: lw a4, 120(a0)
; RV64IXQCCMP-WITH-FP-NEXT: lw a1, 124(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: lw a6, 96(a0)
; RV64IXQCCMP-WITH-FP-NEXT: lw a5, 100(a0)
; RV64IXQCCMP-WITH-FP-NEXT: lw a3, 104(a0)
; RV64IXQCCMP-WITH-FP-NEXT: lw a2, 108(a0)
; RV64IXQCCMP-WITH-FP-NEXT: sw a1, 124(a0)
; RV64IXQCCMP-WITH-FP-NEXT: sw a4, 120(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw a6, 116(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw ra, 116(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s11, 112(a0)
; RV64IXQCCMP-WITH-FP-NEXT: sw a2, 108(a0)
; RV64IXQCCMP-WITH-FP-NEXT: sw a3, 104(a0)
; RV64IXQCCMP-WITH-FP-NEXT: sw a5, 100(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw a7, 96(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t1, 92(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t2, 88(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t3, 84(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s1, 80(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw ra, 76(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s11, 72(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s10, 68(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s9, 64(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s8, 60(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s7, 56(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s6, 52(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s5, 48(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s4, 44(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s3, 40(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw s2, 36(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t6, 32(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-WITH-FP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a6, 96(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s10, 92(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s9, 88(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s8, 84(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s7, 80(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s6, 76(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s5, 72(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s4, 68(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s3, 64(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s2, 60(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw s1, 56(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t6, 52(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t5, 48(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t4, 44(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t3, 40(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t2, 36(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t1, 32(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-WITH-FP-NEXT: sw a7, 24(a0)
; RV64IXQCCMP-WITH-FP-NEXT: ld a1, -160(s0) # 8-byte Folded Reload
; RV64IXQCCMP-WITH-FP-NEXT: sw a1, 20(a0)
; RV64IXQCCMP-WITH-FP-NEXT: ld a1, -152(s0) # 8-byte Folded Reload
@@ -473,29 +473,29 @@ define void @caller() {
; RV32IXQCCMP-NEXT: sw a0, 16(sp) # 4-byte Folded Spill
; RV32IXQCCMP-NEXT: lw a0, 80(s0)
; RV32IXQCCMP-NEXT: sw a0, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw s1, 84(s0)
-; RV32IXQCCMP-NEXT: lw s2, 88(s0)
-; RV32IXQCCMP-NEXT: lw s3, 92(s0)
-; RV32IXQCCMP-NEXT: lw s4, 96(s0)
-; RV32IXQCCMP-NEXT: lw s5, 100(s0)
-; RV32IXQCCMP-NEXT: lw s6, 104(s0)
-; RV32IXQCCMP-NEXT: lw s7, 108(s0)
-; RV32IXQCCMP-NEXT: lw s8, 112(s0)
-; RV32IXQCCMP-NEXT: lw s9, 116(s0)
-; RV32IXQCCMP-NEXT: lw s10, 120(s0)
-; RV32IXQCCMP-NEXT: lw s11, 124(s0)
+; RV32IXQCCMP-NEXT: lw s11, 84(s0)
+; RV32IXQCCMP-NEXT: lw s1, 88(s0)
+; RV32IXQCCMP-NEXT: lw s2, 92(s0)
+; RV32IXQCCMP-NEXT: lw s3, 96(s0)
+; RV32IXQCCMP-NEXT: lw s4, 100(s0)
+; RV32IXQCCMP-NEXT: lw s5, 104(s0)
+; RV32IXQCCMP-NEXT: lw s6, 108(s0)
+; RV32IXQCCMP-NEXT: lw s7, 112(s0)
+; RV32IXQCCMP-NEXT: lw s8, 116(s0)
+; RV32IXQCCMP-NEXT: lw s9, 120(s0)
+; RV32IXQCCMP-NEXT: lw s10, 124(s0)
; RV32IXQCCMP-NEXT: call callee
-; RV32IXQCCMP-NEXT: sw s11, 124(s0)
-; RV32IXQCCMP-NEXT: sw s10, 120(s0)
-; RV32IXQCCMP-NEXT: sw s9, 116(s0)
-; RV32IXQCCMP-NEXT: sw s8, 112(s0)
-; RV32IXQCCMP-NEXT: sw s7, 108(s0)
-; RV32IXQCCMP-NEXT: sw s6, 104(s0)
-; RV32IXQCCMP-NEXT: sw s5, 100(s0)
-; RV32IXQCCMP-NEXT: sw s4, 96(s0)
-; RV32IXQCCMP-NEXT: sw s3, 92(s0)
-; RV32IXQCCMP-NEXT: sw s2, 88(s0)
-; RV32IXQCCMP-NEXT: sw s1, 84(s0)
+; RV32IXQCCMP-NEXT: sw s10, 124(s0)
+; RV32IXQCCMP-NEXT: sw s9, 120(s0)
+; RV32IXQCCMP-NEXT: sw s8, 116(s0)
+; RV32IXQCCMP-NEXT: sw s7, 112(s0)
+; RV32IXQCCMP-NEXT: sw s6, 108(s0)
+; RV32IXQCCMP-NEXT: sw s5, 104(s0)
+; RV32IXQCCMP-NEXT: sw s4, 100(s0)
+; RV32IXQCCMP-NEXT: sw s3, 96(s0)
+; RV32IXQCCMP-NEXT: sw s2, 92(s0)
+; RV32IXQCCMP-NEXT: sw s1, 88(s0)
+; RV32IXQCCMP-NEXT: sw s11, 84(s0)
; RV32IXQCCMP-NEXT: lw a0, 12(sp) # 4-byte Folded Reload
; RV32IXQCCMP-NEXT: sw a0, 80(s0)
; RV32IXQCCMP-NEXT: lw a0, 16(sp) # 4-byte Folded Reload
@@ -741,29 +741,29 @@ define void @caller() {
; RV64IXQCCMP-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
; RV64IXQCCMP-NEXT: lw a0, 80(s0)
; RV64IXQCCMP-NEXT: sd a0, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw s1, 84(s0)
-; RV64IXQCCMP-NEXT: lw s2, 88(s0)
-; RV64IXQCCMP-NEXT: lw s3, 92(s0)
-; RV64IXQCCMP-NEXT: lw s4, 96(s0)
-; RV64IXQCCMP-NEXT: lw s5, 100(s0)
-; RV64IXQCCMP-NEXT: lw s6, 104(s0)
-; RV64IXQCCMP-NEXT: lw s7, 108(s0)
-; RV64IXQCCMP-NEXT: lw s8, 112(s0)
-; RV64IXQCCMP-NEXT: lw s9, 116(s0)
-; RV64IXQCCMP-NEXT: lw s10, 120(s0)
-; RV64IXQCCMP-NEXT: lw s11, 124(s0)
+; RV64IXQCCMP-NEXT: lw s11, 84(s0)
+; RV64IXQCCMP-NEXT: lw s1, 88(s0)
+; RV64IXQCCMP-NEXT: lw s2, 92(s0)
+; RV64IXQCCMP-NEXT: lw s3, 96(s0)
+; RV64IXQCCMP-NEXT: lw s4, 100(s0)
+; RV64IXQCCMP-NEXT: lw s5, 104(s0)
+; RV64IXQCCMP-NEXT: lw s6, 108(s0)
+; RV64IXQCCMP-NEXT: lw s7, 112(s0)
+; RV64IXQCCMP-NEXT: lw s8, 116(s0)
+; RV64IXQCCMP-NEXT: lw s9, 120(s0)
+; RV64IXQCCMP-NEXT: lw s10, 124(s0)
; RV64IXQCCMP-NEXT: call callee
-; RV64IXQCCMP-NEXT: sw s11, 124(s0)
-; RV64IXQCCMP-NEXT: sw s10, 120(s0)
-; RV64IXQCCMP-NEXT: sw s9, 116(s0)
-; RV64IXQCCMP-NEXT: sw s8, 112(s0)
-; RV64IXQCCMP-NEXT: sw s7, 108(s0)
-; RV64IXQCCMP-NEXT: sw s6, 104(s0)
-; RV64IXQCCMP-NEXT: sw s5, 100(s0)
-; RV64IXQCCMP-NEXT: sw s4, 96(s0)
-; RV64IXQCCMP-NEXT: sw s3, 92(s0)
-; RV64IXQCCMP-NEXT: sw s2, 88(s0)
-; RV64IXQCCMP-NEXT: sw s1, 84(s0)
+; RV64IXQCCMP-NEXT: sw s10, 124(s0)
+; RV64IXQCCMP-NEXT: sw s9, 120(s0)
+; RV64IXQCCMP-NEXT: sw s8, 116(s0)
+; RV64IXQCCMP-NEXT: sw s7, 112(s0)
+; RV64IXQCCMP-NEXT: sw s6, 108(s0)
+; RV64IXQCCMP-NEXT: sw s5, 104(s0)
+; RV64IXQCCMP-NEXT: sw s4, 100(s0)
+; RV64IXQCCMP-NEXT: sw s3, 96(s0)
+; RV64IXQCCMP-NEXT: sw s2, 92(s0)
+; RV64IXQCCMP-NEXT: sw s1, 88(s0)
+; RV64IXQCCMP-NEXT: sw s11, 84(s0)
; RV64IXQCCMP-NEXT: ld a0, 8(sp) # 8-byte Folded Reload
; RV64IXQCCMP-NEXT: sw a0, 80(s0)
; RV64IXQCCMP-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll b/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
index 607143ce24a30..4c3429c8b927a 100644
--- a/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
+++ b/llvm/test/CodeGen/RISCV/xqccmp-push-pop-popret.ll
@@ -700,23 +700,23 @@ define i32 @nocompress(i32 signext %size) {
; RV32IXQCCMP-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-NEXT: addi a0, a0, 15
; RV32IXQCCMP-NEXT: andi a0, a0, -16
-; RV32IXQCCMP-NEXT: sub s2, sp, a0
-; RV32IXQCCMP-NEXT: mv sp, s2
-; RV32IXQCCMP-NEXT: lui s1, %hi(var)
-; RV32IXQCCMP-NEXT: addi s1, s1, %lo(var)
-; RV32IXQCCMP-NEXT: lw s3, 0(s1)
-; RV32IXQCCMP-NEXT: lw s4, 4(s1)
-; RV32IXQCCMP-NEXT: lw s5, 8(s1)
-; RV32IXQCCMP-NEXT: lw s6, 12(s1)
-; RV32IXQCCMP-NEXT: lw s7, 16(s1)
-; RV32IXQCCMP-NEXT: mv a0, s2
+; RV32IXQCCMP-NEXT: sub s1, sp, a0
+; RV32IXQCCMP-NEXT: mv sp, s1
+; RV32IXQCCMP-NEXT: lui s2, %hi(var)
+; RV32IXQCCMP-NEXT: addi s2, s2, %lo(var)
+; RV32IXQCCMP-NEXT: lw s3, 0(s2)
+; RV32IXQCCMP-NEXT: lw s4, 4(s2)
+; RV32IXQCCMP-NEXT: lw s5, 8(s2)
+; RV32IXQCCMP-NEXT: lw s6, 12(s2)
+; RV32IXQCCMP-NEXT: lw s7, 16(s2)
+; RV32IXQCCMP-NEXT: mv a0, s1
; RV32IXQCCMP-NEXT: call callee_void
-; RV32IXQCCMP-NEXT: sw s7, 16(s1)
-; RV32IXQCCMP-NEXT: sw s6, 12(s1)
-; RV32IXQCCMP-NEXT: sw s5, 8(s1)
-; RV32IXQCCMP-NEXT: sw s4, 4(s1)
-; RV32IXQCCMP-NEXT: sw s3, 0(s1)
-; RV32IXQCCMP-NEXT: mv a0, s2
+; RV32IXQCCMP-NEXT: sw s7, 16(s2)
+; RV32IXQCCMP-NEXT: sw s6, 12(s2)
+; RV32IXQCCMP-NEXT: sw s5, 8(s2)
+; RV32IXQCCMP-NEXT: sw s4, 4(s2)
+; RV32IXQCCMP-NEXT: sw s3, 0(s2)
+; RV32IXQCCMP-NEXT: mv a0, s1
; RV32IXQCCMP-NEXT: addi sp, s0, -48
; RV32IXQCCMP-NEXT: .cfi_def_cfa sp, 48
; RV32IXQCCMP-NEXT: qc.cm.pop {ra, s0-s7}, 48
@@ -750,23 +750,23 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-NEXT: srli a0, a0, 32
; RV64IXQCCMP-NEXT: addi a0, a0, 15
; RV64IXQCCMP-NEXT: andi a0, a0, -16
-; RV64IXQCCMP-NEXT: sub s2, sp, a0
-; RV64IXQCCMP-NEXT: mv sp, s2
-; RV64IXQCCMP-NEXT: lui s1, %hi(var)
-; RV64IXQCCMP-NEXT: addi s1, s1, %lo(var)
-; RV64IXQCCMP-NEXT: lw s3, 0(s1)
-; RV64IXQCCMP-NEXT: lw s4, 4(s1)
-; RV64IXQCCMP-NEXT: lw s5, 8(s1)
-; RV64IXQCCMP-NEXT: lw s6, 12(s1)
-; RV64IXQCCMP-NEXT: lw s7, 16(s1)
-; RV64IXQCCMP-NEXT: mv a0, s2
+; RV64IXQCCMP-NEXT: sub s1, sp, a0
+; RV64IXQCCMP-NEXT: mv sp, s1
+; RV64IXQCCMP-NEXT: lui s2, %hi(var)
+; RV64IXQCCMP-NEXT: addi s2, s2, %lo(var)
+; RV64IXQCCMP-NEXT: lw s3, 0(s2)
+; RV64IXQCCMP-NEXT: lw s4, 4(s2)
+; RV64IXQCCMP-NEXT: lw s5, 8(s2)
+; RV64IXQCCMP-NEXT: lw s6, 12(s2)
+; RV64IXQCCMP-NEXT: lw s7, 16(s2)
+; RV64IXQCCMP-NEXT: mv a0, s1
; RV64IXQCCMP-NEXT: call callee_void
-; RV64IXQCCMP-NEXT: sw s7, 16(s1)
-; RV64IXQCCMP-NEXT: sw s6, 12(s1)
-; RV64IXQCCMP-NEXT: sw s5, 8(s1)
-; RV64IXQCCMP-NEXT: sw s4, 4(s1)
-; RV64IXQCCMP-NEXT: sw s3, 0(s1)
-; RV64IXQCCMP-NEXT: mv a0, s2
+; RV64IXQCCMP-NEXT: sw s7, 16(s2)
+; RV64IXQCCMP-NEXT: sw s6, 12(s2)
+; RV64IXQCCMP-NEXT: sw s5, 8(s2)
+; RV64IXQCCMP-NEXT: sw s4, 4(s2)
+; RV64IXQCCMP-NEXT: sw s3, 0(s2)
+; RV64IXQCCMP-NEXT: mv a0, s1
; RV64IXQCCMP-NEXT: addi sp, s0, -80
; RV64IXQCCMP-NEXT: .cfi_def_cfa sp, 80
; RV64IXQCCMP-NEXT: qc.cm.pop {ra, s0-s7}, 80
@@ -798,23 +798,23 @@ define i32 @nocompress(i32 signext %size) {
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-FP-NEXT: addi a0, a0, 15
; RV32IXQCCMP-FP-NEXT: andi a0, a0, -16
-; RV32IXQCCMP-FP-NEXT: sub s2, sp, a0
-; RV32IXQCCMP-FP-NEXT: mv sp, s2
-; RV32IXQCCMP-FP-NEXT: lui s1, %hi(var)
-; RV32IXQCCMP-FP-NEXT: addi s1, s1, %lo(var)
-; RV32IXQCCMP-FP-NEXT: lw s3, 0(s1)
-; RV32IXQCCMP-FP-NEXT: lw s4, 4(s1)
-; RV32IXQCCMP-FP-NEXT: lw s5, 8(s1)
-; RV32IXQCCMP-FP-NEXT: lw s6, 12(s1)
-; RV32IXQCCMP-FP-NEXT: lw s7, 16(s1)
-; RV32IXQCCMP-FP-NEXT: mv a0, s2
+; RV32IXQCCMP-FP-NEXT: sub s1, sp, a0
+; RV32IXQCCMP-FP-NEXT: mv sp, s1
+; RV32IXQCCMP-FP-NEXT: lui s2, %hi(var)
+; RV32IXQCCMP-FP-NEXT: addi s2, s2, %lo(var)
+; RV32IXQCCMP-FP-NEXT: lw s3, 0(s2)
+; RV32IXQCCMP-FP-NEXT: lw s4, 4(s2)
+; RV32IXQCCMP-FP-NEXT: lw s5, 8(s2)
+; RV32IXQCCMP-FP-NEXT: lw s6, 12(s2)
+; RV32IXQCCMP-FP-NEXT: lw s7, 16(s2)
+; RV32IXQCCMP-FP-NEXT: mv a0, s1
; RV32IXQCCMP-FP-NEXT: call callee_void
-; RV32IXQCCMP-FP-NEXT: sw s7, 16(s1)
-; RV32IXQCCMP-FP-NEXT: sw s6, 12(s1)
-; RV32IXQCCMP-FP-NEXT: sw s5, 8(s1)
-; RV32IXQCCMP-FP-NEXT: sw s4, 4(s1)
-; RV32IXQCCMP-FP-NEXT: sw s3, 0(s1)
-; RV32IXQCCMP-FP-NEXT: mv a0, s2
+; RV32IXQCCMP-FP-NEXT: sw s7, 16(s2)
+; RV32IXQCCMP-FP-NEXT: sw s6, 12(s2)
+; RV32IXQCCMP-FP-NEXT: sw s5, 8(s2)
+; RV32IXQCCMP-FP-NEXT: sw s4, 4(s2)
+; RV32IXQCCMP-FP-NEXT: sw s3, 0(s2)
+; RV32IXQCCMP-FP-NEXT: mv a0, s1
; RV32IXQCCMP-FP-NEXT: addi sp, s0, -48
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 48
; RV32IXQCCMP-FP-NEXT: qc.cm.pop {ra, s0-s7}, 48
@@ -848,23 +848,23 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-FP-NEXT: srli a0, a0, 32
; RV64IXQCCMP-FP-NEXT: addi a0, a0, 15
; RV64IXQCCMP-FP-NEXT: andi a0, a0, -16
-; RV64IXQCCMP-FP-NEXT: sub s2, sp, a0
-; RV64IXQCCMP-FP-NEXT: mv sp, s2
-; RV64IXQCCMP-FP-NEXT: lui s1, %hi(var)
-; RV64IXQCCMP-FP-NEXT: addi s1, s1, %lo(var)
-; RV64IXQCCMP-FP-NEXT: lw s3, 0(s1)
-; RV64IXQCCMP-FP-NEXT: lw s4, 4(s1)
-; RV64IXQCCMP-FP-NEXT: lw s5, 8(s1)
-; RV64IXQCCMP-FP-NEXT: lw s6, 12(s1)
-; RV64IXQCCMP-FP-NEXT: lw s7, 16(s1)
-; RV64IXQCCMP-FP-NEXT: mv a0, s2
+; RV64IXQCCMP-FP-NEXT: sub s1, sp, a0
+; RV64IXQCCMP-FP-NEXT: mv sp, s1
+; RV64IXQCCMP-FP-NEXT: lui s2, %hi(var)
+; RV64IXQCCMP-FP-NEXT: addi s2, s2, %lo(var)
+; RV64IXQCCMP-FP-NEXT: lw s3, 0(s2)
+; RV64IXQCCMP-FP-NEXT: lw s4, 4(s2)
+; RV64IXQCCMP-FP-NEXT: lw s5, 8(s2)
+; RV64IXQCCMP-FP-NEXT: lw s6, 12(s2)
+; RV64IXQCCMP-FP-NEXT: lw s7, 16(s2)
+; RV64IXQCCMP-FP-NEXT: mv a0, s1
; RV64IXQCCMP-FP-NEXT: call callee_void
-; RV64IXQCCMP-FP-NEXT: sw s7, 16(s1)
-; RV64IXQCCMP-FP-NEXT: sw s6, 12(s1)
-; RV64IXQCCMP-FP-NEXT: sw s5, 8(s1)
-; RV64IXQCCMP-FP-NEXT: sw s4, 4(s1)
-; RV64IXQCCMP-FP-NEXT: sw s3, 0(s1)
-; RV64IXQCCMP-FP-NEXT: mv a0, s2
+; RV64IXQCCMP-FP-NEXT: sw s7, 16(s2)
+; RV64IXQCCMP-FP-NEXT: sw s6, 12(s2)
+; RV64IXQCCMP-FP-NEXT: sw s5, 8(s2)
+; RV64IXQCCMP-FP-NEXT: sw s4, 4(s2)
+; RV64IXQCCMP-FP-NEXT: sw s3, 0(s2)
+; RV64IXQCCMP-FP-NEXT: mv a0, s1
; RV64IXQCCMP-FP-NEXT: addi sp, s0, -80
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 80
; RV64IXQCCMP-FP-NEXT: qc.cm.pop {ra, s0-s7}, 80
@@ -896,23 +896,23 @@ define i32 @nocompress(i32 signext %size) {
; RV32IXQCCMP-SR-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-SR-NEXT: addi a0, a0, 15
; RV32IXQCCMP-SR-NEXT: andi a0, a0, -16
-; RV32IXQCCMP-SR-NEXT: sub s2, sp, a0
-; RV32IXQCCMP-SR-NEXT: mv sp, s2
-; RV32IXQCCMP-SR-NEXT: lui s1, %hi(var)
-; RV32IXQCCMP-SR-NEXT: addi s1, s1, %lo(var)
-; RV32IXQCCMP-SR-NEXT: lw s3, 0(s1)
-; RV32IXQCCMP-SR-NEXT: lw s4, 4(s1)
-; RV32IXQCCMP-SR-NEXT: lw s5, 8(s1)
-; RV32IXQCCMP-SR-NEXT: lw s6, 12(s1)
-; RV32IXQCCMP-SR-NEXT: lw s7, 16(s1)
-; RV32IXQCCMP-SR-NEXT: mv a0, s2
+; RV32IXQCCMP-SR-NEXT: sub s1, sp, a0
+; RV32IXQCCMP-SR-NEXT: mv sp, s1
+; RV32IXQCCMP-SR-NEXT: lui s2, %hi(var)
+; RV32IXQCCMP-SR-NEXT: addi s2, s2, %lo(var)
+; RV32IXQCCMP-SR-NEXT: lw s3, 0(s2)
+; RV32IXQCCMP-SR-NEXT: lw s4, 4(s2)
+; RV32IXQCCMP-SR-NEXT: lw s5, 8(s2)
+; RV32IXQCCMP-SR-NEXT: lw s6, 12(s2)
+; RV32IXQCCMP-SR-NEXT: lw s7, 16(s2)
+; RV32IXQCCMP-SR-NEXT: mv a0, s1
; RV32IXQCCMP-SR-NEXT: call callee_void
-; RV32IXQCCMP-SR-NEXT: sw s7, 16(s1)
-; RV32IXQCCMP-SR-NEXT: sw s6, 12(s1)
-; RV32IXQCCMP-SR-NEXT: sw s5, 8(s1)
-; RV32IXQCCMP-SR-NEXT: sw s4, 4(s1)
-; RV32IXQCCMP-SR-NEXT: sw s3, 0(s1)
-; RV32IXQCCMP-SR-NEXT: mv a0, s2
+; RV32IXQCCMP-SR-NEXT: sw s7, 16(s2)
+; RV32IXQCCMP-SR-NEXT: sw s6, 12(s2)
+; RV32IXQCCMP-SR-NEXT: sw s5, 8(s2)
+; RV32IXQCCMP-SR-NEXT: sw s4, 4(s2)
+; RV32IXQCCMP-SR-NEXT: sw s3, 0(s2)
+; RV32IXQCCMP-SR-NEXT: mv a0, s1
; RV32IXQCCMP-SR-NEXT: addi sp, s0, -48
; RV32IXQCCMP-SR-NEXT: .cfi_def_cfa sp, 48
; RV32IXQCCMP-SR-NEXT: qc.cm.pop {ra, s0-s7}, 48
@@ -946,23 +946,23 @@ define i32 @nocompress(i32 signext %size) {
; RV64IXQCCMP-SR-NEXT: srli a0, a0, 32
; RV64IXQCCMP-SR-NEXT: addi a0, a0, 15
; RV64IXQCCMP-SR-NEXT: andi a0, a0, -16
-; RV64IXQCCMP-SR-NEXT: sub s2, sp, a0
-; RV64IXQCCMP-SR-NEXT: mv sp, s2
-; RV64IXQCCMP-SR-NEXT: lui s1, %hi(var)
-; RV64IXQCCMP-SR-NEXT: addi s1, s1, %lo(var)
-; RV64IXQCCMP-SR-NEXT: lw s3, 0(s1)
-; RV64IXQCCMP-SR-NEXT: lw s4, 4(s1)
-; RV64IXQCCMP-SR-NEXT: lw s5, 8(s1)
-; RV64IXQCCMP-SR-NEXT: lw s6, 12(s1)
-; RV64IXQCCMP-SR-NEXT: lw s7, 16(s1)
-; RV64IXQCCMP-SR-NEXT: mv a0, s2
+; RV64IXQCCMP-SR-NEXT: sub s1, sp, a0
+; RV64IXQCCMP-SR-NEXT: mv sp, s1
+; RV64IXQCCMP-SR-NEXT: lui s2, %hi(var)
+; RV64IXQCCMP-SR-NEXT: addi s2, s2, %lo(var)
+; RV64IXQCCMP-SR-NEXT: lw s3, 0(s2)
+; RV64IXQCCMP-SR-NEXT: lw s4, 4(s2)
+; RV64IXQCCMP-SR-NEXT: lw s5, 8(s2)
+; RV64IXQCCMP-SR-NEXT: lw s6, 12(s2)
+; RV64IXQCCMP-SR-NEXT: lw s7, 16(s2)
+; RV64IXQCCMP-SR-NEXT: mv a0, s1
; RV64IXQCCMP-SR-NEXT: call callee_void
-; RV64IXQCCMP-SR-NEXT: sw s7, 16(s1)
-; RV64IXQCCMP-SR-NEXT: sw s6, 12(s1)
-; RV64IXQCCMP-SR-NEXT: sw s5, 8(s1)
-; RV64IXQCCMP-SR-NEXT: sw s4, 4(s1)
-; RV64IXQCCMP-SR-NEXT: sw s3, 0(s1)
-; RV64IXQCCMP-SR-NEXT: mv a0, s2
+; RV64IXQCCMP-SR-NEXT: sw s7, 16(s2)
+; RV64IXQCCMP-SR-NEXT: sw s6, 12(s2)
+; RV64IXQCCMP-SR-NEXT: sw s5, 8(s2)
+; RV64IXQCCMP-SR-NEXT: sw s4, 4(s2)
+; RV64IXQCCMP-SR-NEXT: sw s3, 0(s2)
+; RV64IXQCCMP-SR-NEXT: mv a0, s1
; RV64IXQCCMP-SR-NEXT: addi sp, s0, -80
; RV64IXQCCMP-SR-NEXT: .cfi_def_cfa sp, 80
; RV64IXQCCMP-SR-NEXT: qc.cm.pop {ra, s0-s7}, 80
@@ -1141,42 +1141,42 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV32IXQCCMP-NEXT: .cfi_offset s3, -20
; RV32IXQCCMP-NEXT: lui a0, %hi(var0)
; RV32IXQCCMP-NEXT: addi a0, a0, %lo(var0)
-; RV32IXQCCMP-NEXT: lw a6, 0(a0)
-; RV32IXQCCMP-NEXT: lw a7, 4(a0)
-; RV32IXQCCMP-NEXT: lw t0, 8(a0)
-; RV32IXQCCMP-NEXT: lw t1, 12(a0)
-; RV32IXQCCMP-NEXT: lw t2, 16(a0)
-; RV32IXQCCMP-NEXT: lw t3, 20(a0)
-; RV32IXQCCMP-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-NEXT: lw t6, 48(a0)
-; RV32IXQCCMP-NEXT: lw s2, 52(a0)
-; RV32IXQCCMP-NEXT: lw a1, 56(a0)
-; RV32IXQCCMP-NEXT: lw a2, 60(a0)
-; RV32IXQCCMP-NEXT: lw a3, 64(a0)
-; RV32IXQCCMP-NEXT: lw a4, 68(a0)
-; RV32IXQCCMP-NEXT: lw s3, 32(a0)
+; RV32IXQCCMP-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-NEXT: lw a2, 4(a0)
+; RV32IXQCCMP-NEXT: lw a3, 8(a0)
+; RV32IXQCCMP-NEXT: lw a4, 12(a0)
+; RV32IXQCCMP-NEXT: lw a5, 16(a0)
+; RV32IXQCCMP-NEXT: lw a6, 20(a0)
+; RV32IXQCCMP-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-NEXT: lw t1, 48(a0)
+; RV32IXQCCMP-NEXT: lw t2, 52(a0)
+; RV32IXQCCMP-NEXT: lw t3, 56(a0)
+; RV32IXQCCMP-NEXT: lw t4, 60(a0)
+; RV32IXQCCMP-NEXT: lw t5, 64(a0)
+; RV32IXQCCMP-NEXT: lw t6, 68(a0)
+; RV32IXQCCMP-NEXT: lw s0, 32(a0)
; RV32IXQCCMP-NEXT: lw s1, 36(a0)
-; RV32IXQCCMP-NEXT: lw a5, 40(a0)
-; RV32IXQCCMP-NEXT: lw s0, 44(a0)
-; RV32IXQCCMP-NEXT: sw a4, 68(a0)
-; RV32IXQCCMP-NEXT: sw a3, 64(a0)
-; RV32IXQCCMP-NEXT: sw a2, 60(a0)
-; RV32IXQCCMP-NEXT: sw a1, 56(a0)
-; RV32IXQCCMP-NEXT: sw s2, 52(a0)
-; RV32IXQCCMP-NEXT: sw t6, 48(a0)
-; RV32IXQCCMP-NEXT: sw s0, 44(a0)
-; RV32IXQCCMP-NEXT: sw a5, 40(a0)
+; RV32IXQCCMP-NEXT: lw s2, 40(a0)
+; RV32IXQCCMP-NEXT: lw s3, 44(a0)
+; RV32IXQCCMP-NEXT: sw t6, 68(a0)
+; RV32IXQCCMP-NEXT: sw t5, 64(a0)
+; RV32IXQCCMP-NEXT: sw t4, 60(a0)
+; RV32IXQCCMP-NEXT: sw t3, 56(a0)
+; RV32IXQCCMP-NEXT: sw t2, 52(a0)
+; RV32IXQCCMP-NEXT: sw t1, 48(a0)
+; RV32IXQCCMP-NEXT: sw s3, 44(a0)
+; RV32IXQCCMP-NEXT: sw s2, 40(a0)
; RV32IXQCCMP-NEXT: sw s1, 36(a0)
-; RV32IXQCCMP-NEXT: sw s3, 32(a0)
-; RV32IXQCCMP-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-NEXT: sw t4, 24(a0)
-; RV32IXQCCMP-NEXT: sw t3, 20(a0)
-; RV32IXQCCMP-NEXT: sw t2, 16(a0)
-; RV32IXQCCMP-NEXT: sw t1, 12(a0)
-; RV32IXQCCMP-NEXT: sw t0, 8(a0)
-; RV32IXQCCMP-NEXT: sw a7, 4(a0)
-; RV32IXQCCMP-NEXT: sw a6, 0(a0)
+; RV32IXQCCMP-NEXT: sw s0, 32(a0)
+; RV32IXQCCMP-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-NEXT: sw a7, 24(a0)
+; RV32IXQCCMP-NEXT: sw a6, 20(a0)
+; RV32IXQCCMP-NEXT: sw a5, 16(a0)
+; RV32IXQCCMP-NEXT: sw a4, 12(a0)
+; RV32IXQCCMP-NEXT: sw a3, 8(a0)
+; RV32IXQCCMP-NEXT: sw a2, 4(a0)
+; RV32IXQCCMP-NEXT: sw a1, 0(a0)
; RV32IXQCCMP-NEXT: qc.cm.popret {ra, s0-s3}, 32
;
; RV64IXQCCMP-LABEL: many_args:
@@ -1189,42 +1189,42 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV64IXQCCMP-NEXT: .cfi_offset s3, -40
; RV64IXQCCMP-NEXT: lui a0, %hi(var0)
; RV64IXQCCMP-NEXT: addi a0, a0, %lo(var0)
-; RV64IXQCCMP-NEXT: lw a6, 0(a0)
-; RV64IXQCCMP-NEXT: lw a7, 4(a0)
-; RV64IXQCCMP-NEXT: lw t0, 8(a0)
-; RV64IXQCCMP-NEXT: lw t1, 12(a0)
-; RV64IXQCCMP-NEXT: lw t2, 16(a0)
-; RV64IXQCCMP-NEXT: lw t3, 20(a0)
-; RV64IXQCCMP-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-NEXT: lw t6, 48(a0)
-; RV64IXQCCMP-NEXT: lw s2, 52(a0)
-; RV64IXQCCMP-NEXT: lw a1, 56(a0)
-; RV64IXQCCMP-NEXT: lw a2, 60(a0)
-; RV64IXQCCMP-NEXT: lw a3, 64(a0)
-; RV64IXQCCMP-NEXT: lw a4, 68(a0)
-; RV64IXQCCMP-NEXT: lw s3, 32(a0)
+; RV64IXQCCMP-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-NEXT: lw a2, 4(a0)
+; RV64IXQCCMP-NEXT: lw a3, 8(a0)
+; RV64IXQCCMP-NEXT: lw a4, 12(a0)
+; RV64IXQCCMP-NEXT: lw a5, 16(a0)
+; RV64IXQCCMP-NEXT: lw a6, 20(a0)
+; RV64IXQCCMP-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-NEXT: lw t1, 48(a0)
+; RV64IXQCCMP-NEXT: lw t2, 52(a0)
+; RV64IXQCCMP-NEXT: lw t3, 56(a0)
+; RV64IXQCCMP-NEXT: lw t4, 60(a0)
+; RV64IXQCCMP-NEXT: lw t5, 64(a0)
+; RV64IXQCCMP-NEXT: lw t6, 68(a0)
+; RV64IXQCCMP-NEXT: lw s0, 32(a0)
; RV64IXQCCMP-NEXT: lw s1, 36(a0)
-; RV64IXQCCMP-NEXT: lw a5, 40(a0)
-; RV64IXQCCMP-NEXT: lw s0, 44(a0)
-; RV64IXQCCMP-NEXT: sw a4, 68(a0)
-; RV64IXQCCMP-NEXT: sw a3, 64(a0)
-; RV64IXQCCMP-NEXT: sw a2, 60(a0)
-; RV64IXQCCMP-NEXT: sw a1, 56(a0)
-; RV64IXQCCMP-NEXT: sw s2, 52(a0)
-; RV64IXQCCMP-NEXT: sw t6, 48(a0)
-; RV64IXQCCMP-NEXT: sw s0, 44(a0)
-; RV64IXQCCMP-NEXT: sw a5, 40(a0)
+; RV64IXQCCMP-NEXT: lw s2, 40(a0)
+; RV64IXQCCMP-NEXT: lw s3, 44(a0)
+; RV64IXQCCMP-NEXT: sw t6, 68(a0)
+; RV64IXQCCMP-NEXT: sw t5, 64(a0)
+; RV64IXQCCMP-NEXT: sw t4, 60(a0)
+; RV64IXQCCMP-NEXT: sw t3, 56(a0)
+; RV64IXQCCMP-NEXT: sw t2, 52(a0)
+; RV64IXQCCMP-NEXT: sw t1, 48(a0)
+; RV64IXQCCMP-NEXT: sw s3, 44(a0)
+; RV64IXQCCMP-NEXT: sw s2, 40(a0)
; RV64IXQCCMP-NEXT: sw s1, 36(a0)
-; RV64IXQCCMP-NEXT: sw s3, 32(a0)
-; RV64IXQCCMP-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-NEXT: sw t4, 24(a0)
-; RV64IXQCCMP-NEXT: sw t3, 20(a0)
-; RV64IXQCCMP-NEXT: sw t2, 16(a0)
-; RV64IXQCCMP-NEXT: sw t1, 12(a0)
-; RV64IXQCCMP-NEXT: sw t0, 8(a0)
-; RV64IXQCCMP-NEXT: sw a7, 4(a0)
-; RV64IXQCCMP-NEXT: sw a6, 0(a0)
+; RV64IXQCCMP-NEXT: sw s0, 32(a0)
+; RV64IXQCCMP-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-NEXT: sw a7, 24(a0)
+; RV64IXQCCMP-NEXT: sw a6, 20(a0)
+; RV64IXQCCMP-NEXT: sw a5, 16(a0)
+; RV64IXQCCMP-NEXT: sw a4, 12(a0)
+; RV64IXQCCMP-NEXT: sw a3, 8(a0)
+; RV64IXQCCMP-NEXT: sw a2, 4(a0)
+; RV64IXQCCMP-NEXT: sw a1, 0(a0)
; RV64IXQCCMP-NEXT: qc.cm.popret {ra, s0-s3}, 48
;
; RV32IXQCCMP-FP-LABEL: many_args:
@@ -1240,42 +1240,42 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-FP-NEXT: lui a0, %hi(var0)
; RV32IXQCCMP-FP-NEXT: addi a0, a0, %lo(var0)
-; RV32IXQCCMP-FP-NEXT: lw a6, 0(a0)
-; RV32IXQCCMP-FP-NEXT: lw a7, 4(a0)
-; RV32IXQCCMP-FP-NEXT: lw t0, 8(a0)
-; RV32IXQCCMP-FP-NEXT: lw t1, 12(a0)
-; RV32IXQCCMP-FP-NEXT: lw t2, 16(a0)
-; RV32IXQCCMP-FP-NEXT: lw t3, 20(a0)
-; RV32IXQCCMP-FP-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-FP-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-FP-NEXT: lw t6, 48(a0)
-; RV32IXQCCMP-FP-NEXT: lw s2, 52(a0)
-; RV32IXQCCMP-FP-NEXT: lw s4, 56(a0)
-; RV32IXQCCMP-FP-NEXT: lw a2, 60(a0)
-; RV32IXQCCMP-FP-NEXT: lw a3, 64(a0)
-; RV32IXQCCMP-FP-NEXT: lw a4, 68(a0)
-; RV32IXQCCMP-FP-NEXT: lw s3, 32(a0)
-; RV32IXQCCMP-FP-NEXT: lw a5, 36(a0)
-; RV32IXQCCMP-FP-NEXT: lw s1, 40(a0)
-; RV32IXQCCMP-FP-NEXT: lw a1, 44(a0)
-; RV32IXQCCMP-FP-NEXT: sw a4, 68(a0)
-; RV32IXQCCMP-FP-NEXT: sw a3, 64(a0)
-; RV32IXQCCMP-FP-NEXT: sw a2, 60(a0)
-; RV32IXQCCMP-FP-NEXT: sw s4, 56(a0)
-; RV32IXQCCMP-FP-NEXT: sw s2, 52(a0)
-; RV32IXQCCMP-FP-NEXT: sw t6, 48(a0)
-; RV32IXQCCMP-FP-NEXT: sw a1, 44(a0)
-; RV32IXQCCMP-FP-NEXT: sw s1, 40(a0)
-; RV32IXQCCMP-FP-NEXT: sw a5, 36(a0)
-; RV32IXQCCMP-FP-NEXT: sw s3, 32(a0)
-; RV32IXQCCMP-FP-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-FP-NEXT: sw t4, 24(a0)
-; RV32IXQCCMP-FP-NEXT: sw t3, 20(a0)
-; RV32IXQCCMP-FP-NEXT: sw t2, 16(a0)
-; RV32IXQCCMP-FP-NEXT: sw t1, 12(a0)
-; RV32IXQCCMP-FP-NEXT: sw t0, 8(a0)
-; RV32IXQCCMP-FP-NEXT: sw a7, 4(a0)
-; RV32IXQCCMP-FP-NEXT: sw a6, 0(a0)
+; RV32IXQCCMP-FP-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-FP-NEXT: lw a2, 4(a0)
+; RV32IXQCCMP-FP-NEXT: lw a3, 8(a0)
+; RV32IXQCCMP-FP-NEXT: lw a4, 12(a0)
+; RV32IXQCCMP-FP-NEXT: lw a5, 16(a0)
+; RV32IXQCCMP-FP-NEXT: lw a6, 20(a0)
+; RV32IXQCCMP-FP-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-FP-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-FP-NEXT: lw t1, 48(a0)
+; RV32IXQCCMP-FP-NEXT: lw t2, 52(a0)
+; RV32IXQCCMP-FP-NEXT: lw t3, 56(a0)
+; RV32IXQCCMP-FP-NEXT: lw t4, 60(a0)
+; RV32IXQCCMP-FP-NEXT: lw t5, 64(a0)
+; RV32IXQCCMP-FP-NEXT: lw t6, 68(a0)
+; RV32IXQCCMP-FP-NEXT: lw s1, 32(a0)
+; RV32IXQCCMP-FP-NEXT: lw s2, 36(a0)
+; RV32IXQCCMP-FP-NEXT: lw s3, 40(a0)
+; RV32IXQCCMP-FP-NEXT: lw s4, 44(a0)
+; RV32IXQCCMP-FP-NEXT: sw t6, 68(a0)
+; RV32IXQCCMP-FP-NEXT: sw t5, 64(a0)
+; RV32IXQCCMP-FP-NEXT: sw t4, 60(a0)
+; RV32IXQCCMP-FP-NEXT: sw t3, 56(a0)
+; RV32IXQCCMP-FP-NEXT: sw t2, 52(a0)
+; RV32IXQCCMP-FP-NEXT: sw t1, 48(a0)
+; RV32IXQCCMP-FP-NEXT: sw s4, 44(a0)
+; RV32IXQCCMP-FP-NEXT: sw s3, 40(a0)
+; RV32IXQCCMP-FP-NEXT: sw s2, 36(a0)
+; RV32IXQCCMP-FP-NEXT: sw s1, 32(a0)
+; RV32IXQCCMP-FP-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-FP-NEXT: sw a7, 24(a0)
+; RV32IXQCCMP-FP-NEXT: sw a6, 20(a0)
+; RV32IXQCCMP-FP-NEXT: sw a5, 16(a0)
+; RV32IXQCCMP-FP-NEXT: sw a4, 12(a0)
+; RV32IXQCCMP-FP-NEXT: sw a3, 8(a0)
+; RV32IXQCCMP-FP-NEXT: sw a2, 4(a0)
+; RV32IXQCCMP-FP-NEXT: sw a1, 0(a0)
; RV32IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 32
; RV32IXQCCMP-FP-NEXT: qc.cm.popret {ra, s0-s4}, 32
;
@@ -1292,42 +1292,42 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa s0, 0
; RV64IXQCCMP-FP-NEXT: lui a0, %hi(var0)
; RV64IXQCCMP-FP-NEXT: addi a0, a0, %lo(var0)
-; RV64IXQCCMP-FP-NEXT: lw a6, 0(a0)
-; RV64IXQCCMP-FP-NEXT: lw a7, 4(a0)
-; RV64IXQCCMP-FP-NEXT: lw t0, 8(a0)
-; RV64IXQCCMP-FP-NEXT: lw t1, 12(a0)
-; RV64IXQCCMP-FP-NEXT: lw t2, 16(a0)
-; RV64IXQCCMP-FP-NEXT: lw t3, 20(a0)
-; RV64IXQCCMP-FP-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-FP-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-FP-NEXT: lw t6, 48(a0)
-; RV64IXQCCMP-FP-NEXT: lw s2, 52(a0)
-; RV64IXQCCMP-FP-NEXT: lw s4, 56(a0)
-; RV64IXQCCMP-FP-NEXT: lw a2, 60(a0)
-; RV64IXQCCMP-FP-NEXT: lw a3, 64(a0)
-; RV64IXQCCMP-FP-NEXT: lw a4, 68(a0)
-; RV64IXQCCMP-FP-NEXT: lw s3, 32(a0)
-; RV64IXQCCMP-FP-NEXT: lw a5, 36(a0)
-; RV64IXQCCMP-FP-NEXT: lw s1, 40(a0)
-; RV64IXQCCMP-FP-NEXT: lw a1, 44(a0)
-; RV64IXQCCMP-FP-NEXT: sw a4, 68(a0)
-; RV64IXQCCMP-FP-NEXT: sw a3, 64(a0)
-; RV64IXQCCMP-FP-NEXT: sw a2, 60(a0)
-; RV64IXQCCMP-FP-NEXT: sw s4, 56(a0)
-; RV64IXQCCMP-FP-NEXT: sw s2, 52(a0)
-; RV64IXQCCMP-FP-NEXT: sw t6, 48(a0)
-; RV64IXQCCMP-FP-NEXT: sw a1, 44(a0)
-; RV64IXQCCMP-FP-NEXT: sw s1, 40(a0)
-; RV64IXQCCMP-FP-NEXT: sw a5, 36(a0)
-; RV64IXQCCMP-FP-NEXT: sw s3, 32(a0)
-; RV64IXQCCMP-FP-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-FP-NEXT: sw t4, 24(a0)
-; RV64IXQCCMP-FP-NEXT: sw t3, 20(a0)
-; RV64IXQCCMP-FP-NEXT: sw t2, 16(a0)
-; RV64IXQCCMP-FP-NEXT: sw t1, 12(a0)
-; RV64IXQCCMP-FP-NEXT: sw t0, 8(a0)
-; RV64IXQCCMP-FP-NEXT: sw a7, 4(a0)
-; RV64IXQCCMP-FP-NEXT: sw a6, 0(a0)
+; RV64IXQCCMP-FP-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-FP-NEXT: lw a2, 4(a0)
+; RV64IXQCCMP-FP-NEXT: lw a3, 8(a0)
+; RV64IXQCCMP-FP-NEXT: lw a4, 12(a0)
+; RV64IXQCCMP-FP-NEXT: lw a5, 16(a0)
+; RV64IXQCCMP-FP-NEXT: lw a6, 20(a0)
+; RV64IXQCCMP-FP-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-FP-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-FP-NEXT: lw t1, 48(a0)
+; RV64IXQCCMP-FP-NEXT: lw t2, 52(a0)
+; RV64IXQCCMP-FP-NEXT: lw t3, 56(a0)
+; RV64IXQCCMP-FP-NEXT: lw t4, 60(a0)
+; RV64IXQCCMP-FP-NEXT: lw t5, 64(a0)
+; RV64IXQCCMP-FP-NEXT: lw t6, 68(a0)
+; RV64IXQCCMP-FP-NEXT: lw s1, 32(a0)
+; RV64IXQCCMP-FP-NEXT: lw s2, 36(a0)
+; RV64IXQCCMP-FP-NEXT: lw s3, 40(a0)
+; RV64IXQCCMP-FP-NEXT: lw s4, 44(a0)
+; RV64IXQCCMP-FP-NEXT: sw t6, 68(a0)
+; RV64IXQCCMP-FP-NEXT: sw t5, 64(a0)
+; RV64IXQCCMP-FP-NEXT: sw t4, 60(a0)
+; RV64IXQCCMP-FP-NEXT: sw t3, 56(a0)
+; RV64IXQCCMP-FP-NEXT: sw t2, 52(a0)
+; RV64IXQCCMP-FP-NEXT: sw t1, 48(a0)
+; RV64IXQCCMP-FP-NEXT: sw s4, 44(a0)
+; RV64IXQCCMP-FP-NEXT: sw s3, 40(a0)
+; RV64IXQCCMP-FP-NEXT: sw s2, 36(a0)
+; RV64IXQCCMP-FP-NEXT: sw s1, 32(a0)
+; RV64IXQCCMP-FP-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-FP-NEXT: sw a7, 24(a0)
+; RV64IXQCCMP-FP-NEXT: sw a6, 20(a0)
+; RV64IXQCCMP-FP-NEXT: sw a5, 16(a0)
+; RV64IXQCCMP-FP-NEXT: sw a4, 12(a0)
+; RV64IXQCCMP-FP-NEXT: sw a3, 8(a0)
+; RV64IXQCCMP-FP-NEXT: sw a2, 4(a0)
+; RV64IXQCCMP-FP-NEXT: sw a1, 0(a0)
; RV64IXQCCMP-FP-NEXT: .cfi_def_cfa sp, 48
; RV64IXQCCMP-FP-NEXT: qc.cm.popret {ra, s0-s4}, 48
;
@@ -1341,42 +1341,42 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV32IXQCCMP-SR-NEXT: .cfi_offset s3, -20
; RV32IXQCCMP-SR-NEXT: lui a0, %hi(var0)
; RV32IXQCCMP-SR-NEXT: addi a0, a0, %lo(var0)
-; RV32IXQCCMP-SR-NEXT: lw a6, 0(a0)
-; RV32IXQCCMP-SR-NEXT: lw a7, 4(a0)
-; RV32IXQCCMP-SR-NEXT: lw t0, 8(a0)
-; RV32IXQCCMP-SR-NEXT: lw t1, 12(a0)
-; RV32IXQCCMP-SR-NEXT: lw t2, 16(a0)
-; RV32IXQCCMP-SR-NEXT: lw t3, 20(a0)
-; RV32IXQCCMP-SR-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-SR-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-SR-NEXT: lw t6, 48(a0)
-; RV32IXQCCMP-SR-NEXT: lw s2, 52(a0)
-; RV32IXQCCMP-SR-NEXT: lw a1, 56(a0)
-; RV32IXQCCMP-SR-NEXT: lw a2, 60(a0)
-; RV32IXQCCMP-SR-NEXT: lw a3, 64(a0)
-; RV32IXQCCMP-SR-NEXT: lw a4, 68(a0)
-; RV32IXQCCMP-SR-NEXT: lw s3, 32(a0)
+; RV32IXQCCMP-SR-NEXT: lw a1, 0(a0)
+; RV32IXQCCMP-SR-NEXT: lw a2, 4(a0)
+; RV32IXQCCMP-SR-NEXT: lw a3, 8(a0)
+; RV32IXQCCMP-SR-NEXT: lw a4, 12(a0)
+; RV32IXQCCMP-SR-NEXT: lw a5, 16(a0)
+; RV32IXQCCMP-SR-NEXT: lw a6, 20(a0)
+; RV32IXQCCMP-SR-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-SR-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-SR-NEXT: lw t1, 48(a0)
+; RV32IXQCCMP-SR-NEXT: lw t2, 52(a0)
+; RV32IXQCCMP-SR-NEXT: lw t3, 56(a0)
+; RV32IXQCCMP-SR-NEXT: lw t4, 60(a0)
+; RV32IXQCCMP-SR-NEXT: lw t5, 64(a0)
+; RV32IXQCCMP-SR-NEXT: lw t6, 68(a0)
+; RV32IXQCCMP-SR-NEXT: lw s0, 32(a0)
; RV32IXQCCMP-SR-NEXT: lw s1, 36(a0)
-; RV32IXQCCMP-SR-NEXT: lw a5, 40(a0)
-; RV32IXQCCMP-SR-NEXT: lw s0, 44(a0)
-; RV32IXQCCMP-SR-NEXT: sw a4, 68(a0)
-; RV32IXQCCMP-SR-NEXT: sw a3, 64(a0)
-; RV32IXQCCMP-SR-NEXT: sw a2, 60(a0)
-; RV32IXQCCMP-SR-NEXT: sw a1, 56(a0)
-; RV32IXQCCMP-SR-NEXT: sw s2, 52(a0)
-; RV32IXQCCMP-SR-NEXT: sw t6, 48(a0)
-; RV32IXQCCMP-SR-NEXT: sw s0, 44(a0)
-; RV32IXQCCMP-SR-NEXT: sw a5, 40(a0)
+; RV32IXQCCMP-SR-NEXT: lw s2, 40(a0)
+; RV32IXQCCMP-SR-NEXT: lw s3, 44(a0)
+; RV32IXQCCMP-SR-NEXT: sw t6, 68(a0)
+; RV32IXQCCMP-SR-NEXT: sw t5, 64(a0)
+; RV32IXQCCMP-SR-NEXT: sw t4, 60(a0)
+; RV32IXQCCMP-SR-NEXT: sw t3, 56(a0)
+; RV32IXQCCMP-SR-NEXT: sw t2, 52(a0)
+; RV32IXQCCMP-SR-NEXT: sw t1, 48(a0)
+; RV32IXQCCMP-SR-NEXT: sw s3, 44(a0)
+; RV32IXQCCMP-SR-NEXT: sw s2, 40(a0)
; RV32IXQCCMP-SR-NEXT: sw s1, 36(a0)
-; RV32IXQCCMP-SR-NEXT: sw s3, 32(a0)
-; RV32IXQCCMP-SR-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-SR-NEXT: sw t4, 24(a0)
-; RV32IXQCCMP-SR-NEXT: sw t3, 20(a0)
-; RV32IXQCCMP-SR-NEXT: sw t2, 16(a0)
-; RV32IXQCCMP-SR-NEXT: sw t1, 12(a0)
-; RV32IXQCCMP-SR-NEXT: sw t0, 8(a0)
-; RV32IXQCCMP-SR-NEXT: sw a7, 4(a0)
-; RV32IXQCCMP-SR-NEXT: sw a6, 0(a0)
+; RV32IXQCCMP-SR-NEXT: sw s0, 32(a0)
+; RV32IXQCCMP-SR-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-SR-NEXT: sw a7, 24(a0)
+; RV32IXQCCMP-SR-NEXT: sw a6, 20(a0)
+; RV32IXQCCMP-SR-NEXT: sw a5, 16(a0)
+; RV32IXQCCMP-SR-NEXT: sw a4, 12(a0)
+; RV32IXQCCMP-SR-NEXT: sw a3, 8(a0)
+; RV32IXQCCMP-SR-NEXT: sw a2, 4(a0)
+; RV32IXQCCMP-SR-NEXT: sw a1, 0(a0)
; RV32IXQCCMP-SR-NEXT: qc.cm.popret {ra, s0-s3}, 32
;
; RV64IXQCCMP-SR-LABEL: many_args:
@@ -1389,42 +1389,42 @@ define void @many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32) {
; RV64IXQCCMP-SR-NEXT: .cfi_offset s3, -40
; RV64IXQCCMP-SR-NEXT: lui a0, %hi(var0)
; RV64IXQCCMP-SR-NEXT: addi a0, a0, %lo(var0)
-; RV64IXQCCMP-SR-NEXT: lw a6, 0(a0)
-; RV64IXQCCMP-SR-NEXT: lw a7, 4(a0)
-; RV64IXQCCMP-SR-NEXT: lw t0, 8(a0)
-; RV64IXQCCMP-SR-NEXT: lw t1, 12(a0)
-; RV64IXQCCMP-SR-NEXT: lw t2, 16(a0)
-; RV64IXQCCMP-SR-NEXT: lw t3, 20(a0)
-; RV64IXQCCMP-SR-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-SR-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-SR-NEXT: lw t6, 48(a0)
-; RV64IXQCCMP-SR-NEXT: lw s2, 52(a0)
-; RV64IXQCCMP-SR-NEXT: lw a1, 56(a0)
-; RV64IXQCCMP-SR-NEXT: lw a2, 60(a0)
-; RV64IXQCCMP-SR-NEXT: lw a3, 64(a0)
-; RV64IXQCCMP-SR-NEXT: lw a4, 68(a0)
-; RV64IXQCCMP-SR-NEXT: lw s3, 32(a0)
+; RV64IXQCCMP-SR-NEXT: lw a1, 0(a0)
+; RV64IXQCCMP-SR-NEXT: lw a2, 4(a0)
+; RV64IXQCCMP-SR-NEXT: lw a3, 8(a0)
+; RV64IXQCCMP-SR-NEXT: lw a4, 12(a0)
+; RV64IXQCCMP-SR-NEXT: lw a5, 16(a0)
+; RV64IXQCCMP-SR-NEXT: lw a6, 20(a0)
+; RV64IXQCCMP-SR-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-SR-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-SR-NEXT: lw t1, 48(a0)
+; RV64IXQCCMP-SR-NEXT: lw t2, 52(a0)
+; RV64IXQCCMP-SR-NEXT: lw t3, 56(a0)
+; RV64IXQCCMP-SR-NEXT: lw t4, 60(a0)
+; RV64IXQCCMP-SR-NEXT: lw t5, 64(a0)
+; RV64IXQCCMP-SR-NEXT: lw t6, 68(a0)
+; RV64IXQCCMP-SR-NEXT: lw s0, 32(a0)
; RV64IXQCCMP-SR-NEXT: lw s1, 36(a0)
-; RV64IXQCCMP-SR-NEXT: lw a5, 40(a0)
-; RV64IXQCCMP-SR-NEXT: lw s0, 44(a0)
-; RV64IXQCCMP-SR-NEXT: sw a4, 68(a0)
-; RV64IXQCCMP-SR-NEXT: sw a3, 64(a0)
-; RV64IXQCCMP-SR-NEXT: sw a2, 60(a0)
-; RV64IXQCCMP-SR-NEXT: sw a1, 56(a0)
-; RV64IXQCCMP-SR-NEXT: sw s2, 52(a0)
-; RV64IXQCCMP-SR-NEXT: sw t6, 48(a0)
-; RV64IXQCCMP-SR-NEXT: sw s0, 44(a0)
-; RV64IXQCCMP-SR-NEXT: sw a5, 40(a0)
+; RV64IXQCCMP-SR-NEXT: lw s2, 40(a0)
+; RV64IXQCCMP-SR-NEXT: lw s3, 44(a0)
+; RV64IXQCCMP-SR-NEXT: sw t6, 68(a0)
+; RV64IXQCCMP-SR-NEXT: sw t5, 64(a0)
+; RV64IXQCCMP-SR-NEXT: sw t4, 60(a0)
+; RV64IXQCCMP-SR-NEXT: sw t3, 56(a0)
+; RV64IXQCCMP-SR-NEXT: sw t2, 52(a0)
+; RV64IXQCCMP-SR-NEXT: sw t1, 48(a0)
+; RV64IXQCCMP-SR-NEXT: sw s3, 44(a0)
+; RV64IXQCCMP-SR-NEXT: sw s2, 40(a0)
; RV64IXQCCMP-SR-NEXT: sw s1, 36(a0)
-; RV64IXQCCMP-SR-NEXT: sw s3, 32(a0)
-; RV64IXQCCMP-SR-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-SR-NEXT: sw t4, 24(a0)
-; RV64IXQCCMP-SR-NEXT: sw t3, 20(a0)
-; RV64IXQCCMP-SR-NEXT: sw t2, 16(a0)
-; RV64IXQCCMP-SR-NEXT: sw t1, 12(a0)
-; RV64IXQCCMP-SR-NEXT: sw t0, 8(a0)
-; RV64IXQCCMP-SR-NEXT: sw a7, 4(a0)
-; RV64IXQCCMP-SR-NEXT: sw a6, 0(a0)
+; RV64IXQCCMP-SR-NEXT: sw s0, 32(a0)
+; RV64IXQCCMP-SR-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-SR-NEXT: sw a7, 24(a0)
+; RV64IXQCCMP-SR-NEXT: sw a6, 20(a0)
+; RV64IXQCCMP-SR-NEXT: sw a5, 16(a0)
+; RV64IXQCCMP-SR-NEXT: sw a4, 12(a0)
+; RV64IXQCCMP-SR-NEXT: sw a3, 8(a0)
+; RV64IXQCCMP-SR-NEXT: sw a2, 4(a0)
+; RV64IXQCCMP-SR-NEXT: sw a1, 0(a0)
; RV64IXQCCMP-SR-NEXT: qc.cm.popret {ra, s0-s3}, 48
entry:
%val = load [18 x i32], ptr @var0
@@ -2148,60 +2148,60 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IXQCCMP-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; RV32IXQCCMP-NEXT: lw a1, 16(a0)
; RV32IXQCCMP-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw t3, 20(a0)
-; RV32IXQCCMP-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-NEXT: lw t6, 32(a0)
-; RV32IXQCCMP-NEXT: lw s2, 36(a0)
-; RV32IXQCCMP-NEXT: lw s3, 40(a0)
-; RV32IXQCCMP-NEXT: lw s4, 44(a0)
-; RV32IXQCCMP-NEXT: lw s5, 48(a0)
-; RV32IXQCCMP-NEXT: lw s6, 52(a0)
-; RV32IXQCCMP-NEXT: lw s7, 56(a0)
-; RV32IXQCCMP-NEXT: lw s8, 60(a0)
-; RV32IXQCCMP-NEXT: lw s9, 64(a0)
-; RV32IXQCCMP-NEXT: lw s10, 68(a0)
-; RV32IXQCCMP-NEXT: lw s11, 72(a0)
-; RV32IXQCCMP-NEXT: lw ra, 76(a0)
-; RV32IXQCCMP-NEXT: lw t2, 80(a0)
-; RV32IXQCCMP-NEXT: lw s0, 84(a0)
-; RV32IXQCCMP-NEXT: lw s1, 88(a0)
-; RV32IXQCCMP-NEXT: lw t1, 92(a0)
-; RV32IXQCCMP-NEXT: lw t0, 112(a0)
-; RV32IXQCCMP-NEXT: lw a5, 116(a0)
-; RV32IXQCCMP-NEXT: lw a3, 120(a0)
+; RV32IXQCCMP-NEXT: lw a6, 20(a0)
+; RV32IXQCCMP-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-NEXT: lw t1, 32(a0)
+; RV32IXQCCMP-NEXT: lw t2, 36(a0)
+; RV32IXQCCMP-NEXT: lw t3, 40(a0)
+; RV32IXQCCMP-NEXT: lw t4, 44(a0)
+; RV32IXQCCMP-NEXT: lw t5, 48(a0)
+; RV32IXQCCMP-NEXT: lw t6, 52(a0)
+; RV32IXQCCMP-NEXT: lw s0, 56(a0)
+; RV32IXQCCMP-NEXT: lw s1, 60(a0)
+; RV32IXQCCMP-NEXT: lw s2, 64(a0)
+; RV32IXQCCMP-NEXT: lw s3, 68(a0)
+; RV32IXQCCMP-NEXT: lw s4, 72(a0)
+; RV32IXQCCMP-NEXT: lw s5, 76(a0)
+; RV32IXQCCMP-NEXT: lw s6, 80(a0)
+; RV32IXQCCMP-NEXT: lw s7, 84(a0)
+; RV32IXQCCMP-NEXT: lw s8, 88(a0)
+; RV32IXQCCMP-NEXT: lw s9, 92(a0)
+; RV32IXQCCMP-NEXT: lw s10, 112(a0)
+; RV32IXQCCMP-NEXT: lw s11, 116(a0)
+; RV32IXQCCMP-NEXT: lw ra, 120(a0)
; RV32IXQCCMP-NEXT: lw a1, 124(a0)
-; RV32IXQCCMP-NEXT: lw a7, 96(a0)
-; RV32IXQCCMP-NEXT: lw a6, 100(a0)
-; RV32IXQCCMP-NEXT: lw a4, 104(a0)
+; RV32IXQCCMP-NEXT: lw a5, 96(a0)
+; RV32IXQCCMP-NEXT: lw a4, 100(a0)
+; RV32IXQCCMP-NEXT: lw a3, 104(a0)
; RV32IXQCCMP-NEXT: lw a2, 108(a0)
; RV32IXQCCMP-NEXT: sw a1, 124(a0)
-; RV32IXQCCMP-NEXT: sw a3, 120(a0)
-; RV32IXQCCMP-NEXT: sw a5, 116(a0)
-; RV32IXQCCMP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-NEXT: sw ra, 120(a0)
+; RV32IXQCCMP-NEXT: sw s11, 116(a0)
+; RV32IXQCCMP-NEXT: sw s10, 112(a0)
; RV32IXQCCMP-NEXT: sw a2, 108(a0)
-; RV32IXQCCMP-NEXT: sw a4, 104(a0)
-; RV32IXQCCMP-NEXT: sw a6, 100(a0)
-; RV32IXQCCMP-NEXT: sw a7, 96(a0)
-; RV32IXQCCMP-NEXT: sw t1, 92(a0)
-; RV32IXQCCMP-NEXT: sw s1, 88(a0)
-; RV32IXQCCMP-NEXT: sw s0, 84(a0)
-; RV32IXQCCMP-NEXT: sw t2, 80(a0)
-; RV32IXQCCMP-NEXT: sw ra, 76(a0)
-; RV32IXQCCMP-NEXT: sw s11, 72(a0)
-; RV32IXQCCMP-NEXT: sw s10, 68(a0)
-; RV32IXQCCMP-NEXT: sw s9, 64(a0)
-; RV32IXQCCMP-NEXT: sw s8, 60(a0)
-; RV32IXQCCMP-NEXT: sw s7, 56(a0)
-; RV32IXQCCMP-NEXT: sw s6, 52(a0)
-; RV32IXQCCMP-NEXT: sw s5, 48(a0)
-; RV32IXQCCMP-NEXT: sw s4, 44(a0)
-; RV32IXQCCMP-NEXT: sw s3, 40(a0)
-; RV32IXQCCMP-NEXT: sw s2, 36(a0)
-; RV32IXQCCMP-NEXT: sw t6, 32(a0)
-; RV32IXQCCMP-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-NEXT: sw t4, 24(a0)
-; RV32IXQCCMP-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-NEXT: sw a3, 104(a0)
+; RV32IXQCCMP-NEXT: sw a4, 100(a0)
+; RV32IXQCCMP-NEXT: sw a5, 96(a0)
+; RV32IXQCCMP-NEXT: sw s9, 92(a0)
+; RV32IXQCCMP-NEXT: sw s8, 88(a0)
+; RV32IXQCCMP-NEXT: sw s7, 84(a0)
+; RV32IXQCCMP-NEXT: sw s6, 80(a0)
+; RV32IXQCCMP-NEXT: sw s5, 76(a0)
+; RV32IXQCCMP-NEXT: sw s4, 72(a0)
+; RV32IXQCCMP-NEXT: sw s3, 68(a0)
+; RV32IXQCCMP-NEXT: sw s2, 64(a0)
+; RV32IXQCCMP-NEXT: sw s1, 60(a0)
+; RV32IXQCCMP-NEXT: sw s0, 56(a0)
+; RV32IXQCCMP-NEXT: sw t6, 52(a0)
+; RV32IXQCCMP-NEXT: sw t5, 48(a0)
+; RV32IXQCCMP-NEXT: sw t4, 44(a0)
+; RV32IXQCCMP-NEXT: sw t3, 40(a0)
+; RV32IXQCCMP-NEXT: sw t2, 36(a0)
+; RV32IXQCCMP-NEXT: sw t1, 32(a0)
+; RV32IXQCCMP-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-NEXT: sw a7, 24(a0)
+; RV32IXQCCMP-NEXT: sw a6, 20(a0)
; RV32IXQCCMP-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; RV32IXQCCMP-NEXT: sw a1, 16(a0)
; RV32IXQCCMP-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
@@ -2322,60 +2322,60 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IXQCCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
; RV64IXQCCMP-NEXT: lw a1, 16(a0)
; RV64IXQCCMP-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw t3, 20(a0)
-; RV64IXQCCMP-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-NEXT: lw t6, 32(a0)
-; RV64IXQCCMP-NEXT: lw s2, 36(a0)
-; RV64IXQCCMP-NEXT: lw s3, 40(a0)
-; RV64IXQCCMP-NEXT: lw s4, 44(a0)
-; RV64IXQCCMP-NEXT: lw s5, 48(a0)
-; RV64IXQCCMP-NEXT: lw s6, 52(a0)
-; RV64IXQCCMP-NEXT: lw s7, 56(a0)
-; RV64IXQCCMP-NEXT: lw s8, 60(a0)
-; RV64IXQCCMP-NEXT: lw s9, 64(a0)
-; RV64IXQCCMP-NEXT: lw s10, 68(a0)
-; RV64IXQCCMP-NEXT: lw s11, 72(a0)
-; RV64IXQCCMP-NEXT: lw ra, 76(a0)
-; RV64IXQCCMP-NEXT: lw t2, 80(a0)
-; RV64IXQCCMP-NEXT: lw s0, 84(a0)
-; RV64IXQCCMP-NEXT: lw s1, 88(a0)
-; RV64IXQCCMP-NEXT: lw t1, 92(a0)
-; RV64IXQCCMP-NEXT: lw t0, 112(a0)
-; RV64IXQCCMP-NEXT: lw a5, 116(a0)
-; RV64IXQCCMP-NEXT: lw a3, 120(a0)
+; RV64IXQCCMP-NEXT: lw a6, 20(a0)
+; RV64IXQCCMP-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-NEXT: lw t1, 32(a0)
+; RV64IXQCCMP-NEXT: lw t2, 36(a0)
+; RV64IXQCCMP-NEXT: lw t3, 40(a0)
+; RV64IXQCCMP-NEXT: lw t4, 44(a0)
+; RV64IXQCCMP-NEXT: lw t5, 48(a0)
+; RV64IXQCCMP-NEXT: lw t6, 52(a0)
+; RV64IXQCCMP-NEXT: lw s0, 56(a0)
+; RV64IXQCCMP-NEXT: lw s1, 60(a0)
+; RV64IXQCCMP-NEXT: lw s2, 64(a0)
+; RV64IXQCCMP-NEXT: lw s3, 68(a0)
+; RV64IXQCCMP-NEXT: lw s4, 72(a0)
+; RV64IXQCCMP-NEXT: lw s5, 76(a0)
+; RV64IXQCCMP-NEXT: lw s6, 80(a0)
+; RV64IXQCCMP-NEXT: lw s7, 84(a0)
+; RV64IXQCCMP-NEXT: lw s8, 88(a0)
+; RV64IXQCCMP-NEXT: lw s9, 92(a0)
+; RV64IXQCCMP-NEXT: lw s10, 112(a0)
+; RV64IXQCCMP-NEXT: lw s11, 116(a0)
+; RV64IXQCCMP-NEXT: lw ra, 120(a0)
; RV64IXQCCMP-NEXT: lw a1, 124(a0)
-; RV64IXQCCMP-NEXT: lw a7, 96(a0)
-; RV64IXQCCMP-NEXT: lw a6, 100(a0)
-; RV64IXQCCMP-NEXT: lw a4, 104(a0)
+; RV64IXQCCMP-NEXT: lw a5, 96(a0)
+; RV64IXQCCMP-NEXT: lw a4, 100(a0)
+; RV64IXQCCMP-NEXT: lw a3, 104(a0)
; RV64IXQCCMP-NEXT: lw a2, 108(a0)
; RV64IXQCCMP-NEXT: sw a1, 124(a0)
-; RV64IXQCCMP-NEXT: sw a3, 120(a0)
-; RV64IXQCCMP-NEXT: sw a5, 116(a0)
-; RV64IXQCCMP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-NEXT: sw ra, 120(a0)
+; RV64IXQCCMP-NEXT: sw s11, 116(a0)
+; RV64IXQCCMP-NEXT: sw s10, 112(a0)
; RV64IXQCCMP-NEXT: sw a2, 108(a0)
-; RV64IXQCCMP-NEXT: sw a4, 104(a0)
-; RV64IXQCCMP-NEXT: sw a6, 100(a0)
-; RV64IXQCCMP-NEXT: sw a7, 96(a0)
-; RV64IXQCCMP-NEXT: sw t1, 92(a0)
-; RV64IXQCCMP-NEXT: sw s1, 88(a0)
-; RV64IXQCCMP-NEXT: sw s0, 84(a0)
-; RV64IXQCCMP-NEXT: sw t2, 80(a0)
-; RV64IXQCCMP-NEXT: sw ra, 76(a0)
-; RV64IXQCCMP-NEXT: sw s11, 72(a0)
-; RV64IXQCCMP-NEXT: sw s10, 68(a0)
-; RV64IXQCCMP-NEXT: sw s9, 64(a0)
-; RV64IXQCCMP-NEXT: sw s8, 60(a0)
-; RV64IXQCCMP-NEXT: sw s7, 56(a0)
-; RV64IXQCCMP-NEXT: sw s6, 52(a0)
-; RV64IXQCCMP-NEXT: sw s5, 48(a0)
-; RV64IXQCCMP-NEXT: sw s4, 44(a0)
-; RV64IXQCCMP-NEXT: sw s3, 40(a0)
-; RV64IXQCCMP-NEXT: sw s2, 36(a0)
-; RV64IXQCCMP-NEXT: sw t6, 32(a0)
-; RV64IXQCCMP-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-NEXT: sw t4, 24(a0)
-; RV64IXQCCMP-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-NEXT: sw a3, 104(a0)
+; RV64IXQCCMP-NEXT: sw a4, 100(a0)
+; RV64IXQCCMP-NEXT: sw a5, 96(a0)
+; RV64IXQCCMP-NEXT: sw s9, 92(a0)
+; RV64IXQCCMP-NEXT: sw s8, 88(a0)
+; RV64IXQCCMP-NEXT: sw s7, 84(a0)
+; RV64IXQCCMP-NEXT: sw s6, 80(a0)
+; RV64IXQCCMP-NEXT: sw s5, 76(a0)
+; RV64IXQCCMP-NEXT: sw s4, 72(a0)
+; RV64IXQCCMP-NEXT: sw s3, 68(a0)
+; RV64IXQCCMP-NEXT: sw s2, 64(a0)
+; RV64IXQCCMP-NEXT: sw s1, 60(a0)
+; RV64IXQCCMP-NEXT: sw s0, 56(a0)
+; RV64IXQCCMP-NEXT: sw t6, 52(a0)
+; RV64IXQCCMP-NEXT: sw t5, 48(a0)
+; RV64IXQCCMP-NEXT: sw t4, 44(a0)
+; RV64IXQCCMP-NEXT: sw t3, 40(a0)
+; RV64IXQCCMP-NEXT: sw t2, 36(a0)
+; RV64IXQCCMP-NEXT: sw t1, 32(a0)
+; RV64IXQCCMP-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-NEXT: sw a7, 24(a0)
+; RV64IXQCCMP-NEXT: sw a6, 20(a0)
; RV64IXQCCMP-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
; RV64IXQCCMP-NEXT: sw a1, 16(a0)
; RV64IXQCCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
@@ -2499,58 +2499,58 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IXQCCMP-FP-NEXT: sw a1, -144(s0) # 4-byte Folded Spill
; RV32IXQCCMP-FP-NEXT: lw a1, 20(a0)
; RV32IXQCCMP-FP-NEXT: sw a1, -148(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-FP-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-FP-NEXT: lw t6, 32(a0)
-; RV32IXQCCMP-FP-NEXT: lw s2, 36(a0)
-; RV32IXQCCMP-FP-NEXT: lw s3, 40(a0)
-; RV32IXQCCMP-FP-NEXT: lw s4, 44(a0)
-; RV32IXQCCMP-FP-NEXT: lw s5, 48(a0)
-; RV32IXQCCMP-FP-NEXT: lw s6, 52(a0)
-; RV32IXQCCMP-FP-NEXT: lw s7, 56(a0)
-; RV32IXQCCMP-FP-NEXT: lw s8, 60(a0)
-; RV32IXQCCMP-FP-NEXT: lw s9, 64(a0)
-; RV32IXQCCMP-FP-NEXT: lw s10, 68(a0)
-; RV32IXQCCMP-FP-NEXT: lw s11, 72(a0)
-; RV32IXQCCMP-FP-NEXT: lw ra, 76(a0)
-; RV32IXQCCMP-FP-NEXT: lw s1, 80(a0)
-; RV32IXQCCMP-FP-NEXT: lw t3, 84(a0)
-; RV32IXQCCMP-FP-NEXT: lw t2, 88(a0)
-; RV32IXQCCMP-FP-NEXT: lw t1, 92(a0)
-; RV32IXQCCMP-FP-NEXT: lw t0, 112(a0)
-; RV32IXQCCMP-FP-NEXT: lw a6, 116(a0)
+; RV32IXQCCMP-FP-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-FP-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-FP-NEXT: lw t1, 32(a0)
+; RV32IXQCCMP-FP-NEXT: lw t2, 36(a0)
+; RV32IXQCCMP-FP-NEXT: lw t3, 40(a0)
+; RV32IXQCCMP-FP-NEXT: lw t4, 44(a0)
+; RV32IXQCCMP-FP-NEXT: lw t5, 48(a0)
+; RV32IXQCCMP-FP-NEXT: lw t6, 52(a0)
+; RV32IXQCCMP-FP-NEXT: lw s1, 56(a0)
+; RV32IXQCCMP-FP-NEXT: lw s2, 60(a0)
+; RV32IXQCCMP-FP-NEXT: lw s3, 64(a0)
+; RV32IXQCCMP-FP-NEXT: lw s4, 68(a0)
+; RV32IXQCCMP-FP-NEXT: lw s5, 72(a0)
+; RV32IXQCCMP-FP-NEXT: lw s6, 76(a0)
+; RV32IXQCCMP-FP-NEXT: lw s7, 80(a0)
+; RV32IXQCCMP-FP-NEXT: lw s8, 84(a0)
+; RV32IXQCCMP-FP-NEXT: lw s9, 88(a0)
+; RV32IXQCCMP-FP-NEXT: lw s10, 92(a0)
+; RV32IXQCCMP-FP-NEXT: lw s11, 112(a0)
+; RV32IXQCCMP-FP-NEXT: lw ra, 116(a0)
; RV32IXQCCMP-FP-NEXT: lw a4, 120(a0)
; RV32IXQCCMP-FP-NEXT: lw a1, 124(a0)
-; RV32IXQCCMP-FP-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-FP-NEXT: lw a6, 96(a0)
; RV32IXQCCMP-FP-NEXT: lw a5, 100(a0)
; RV32IXQCCMP-FP-NEXT: lw a3, 104(a0)
; RV32IXQCCMP-FP-NEXT: lw a2, 108(a0)
; RV32IXQCCMP-FP-NEXT: sw a1, 124(a0)
; RV32IXQCCMP-FP-NEXT: sw a4, 120(a0)
-; RV32IXQCCMP-FP-NEXT: sw a6, 116(a0)
-; RV32IXQCCMP-FP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-FP-NEXT: sw ra, 116(a0)
+; RV32IXQCCMP-FP-NEXT: sw s11, 112(a0)
; RV32IXQCCMP-FP-NEXT: sw a2, 108(a0)
; RV32IXQCCMP-FP-NEXT: sw a3, 104(a0)
; RV32IXQCCMP-FP-NEXT: sw a5, 100(a0)
-; RV32IXQCCMP-FP-NEXT: sw a7, 96(a0)
-; RV32IXQCCMP-FP-NEXT: sw t1, 92(a0)
-; RV32IXQCCMP-FP-NEXT: sw t2, 88(a0)
-; RV32IXQCCMP-FP-NEXT: sw t3, 84(a0)
-; RV32IXQCCMP-FP-NEXT: sw s1, 80(a0)
-; RV32IXQCCMP-FP-NEXT: sw ra, 76(a0)
-; RV32IXQCCMP-FP-NEXT: sw s11, 72(a0)
-; RV32IXQCCMP-FP-NEXT: sw s10, 68(a0)
-; RV32IXQCCMP-FP-NEXT: sw s9, 64(a0)
-; RV32IXQCCMP-FP-NEXT: sw s8, 60(a0)
-; RV32IXQCCMP-FP-NEXT: sw s7, 56(a0)
-; RV32IXQCCMP-FP-NEXT: sw s6, 52(a0)
-; RV32IXQCCMP-FP-NEXT: sw s5, 48(a0)
-; RV32IXQCCMP-FP-NEXT: sw s4, 44(a0)
-; RV32IXQCCMP-FP-NEXT: sw s3, 40(a0)
-; RV32IXQCCMP-FP-NEXT: sw s2, 36(a0)
-; RV32IXQCCMP-FP-NEXT: sw t6, 32(a0)
-; RV32IXQCCMP-FP-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-FP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-FP-NEXT: sw a6, 96(a0)
+; RV32IXQCCMP-FP-NEXT: sw s10, 92(a0)
+; RV32IXQCCMP-FP-NEXT: sw s9, 88(a0)
+; RV32IXQCCMP-FP-NEXT: sw s8, 84(a0)
+; RV32IXQCCMP-FP-NEXT: sw s7, 80(a0)
+; RV32IXQCCMP-FP-NEXT: sw s6, 76(a0)
+; RV32IXQCCMP-FP-NEXT: sw s5, 72(a0)
+; RV32IXQCCMP-FP-NEXT: sw s4, 68(a0)
+; RV32IXQCCMP-FP-NEXT: sw s3, 64(a0)
+; RV32IXQCCMP-FP-NEXT: sw s2, 60(a0)
+; RV32IXQCCMP-FP-NEXT: sw s1, 56(a0)
+; RV32IXQCCMP-FP-NEXT: sw t6, 52(a0)
+; RV32IXQCCMP-FP-NEXT: sw t5, 48(a0)
+; RV32IXQCCMP-FP-NEXT: sw t4, 44(a0)
+; RV32IXQCCMP-FP-NEXT: sw t3, 40(a0)
+; RV32IXQCCMP-FP-NEXT: sw t2, 36(a0)
+; RV32IXQCCMP-FP-NEXT: sw t1, 32(a0)
+; RV32IXQCCMP-FP-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-FP-NEXT: sw a7, 24(a0)
; RV32IXQCCMP-FP-NEXT: lw a1, -148(s0) # 4-byte Folded Reload
; RV32IXQCCMP-FP-NEXT: sw a1, 20(a0)
; RV32IXQCCMP-FP-NEXT: lw a1, -144(s0) # 4-byte Folded Reload
@@ -2677,58 +2677,58 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IXQCCMP-FP-NEXT: sd a1, -272(s0) # 8-byte Folded Spill
; RV64IXQCCMP-FP-NEXT: lw a1, 20(a0)
; RV64IXQCCMP-FP-NEXT: sd a1, -280(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-FP-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-FP-NEXT: lw t6, 32(a0)
-; RV64IXQCCMP-FP-NEXT: lw s2, 36(a0)
-; RV64IXQCCMP-FP-NEXT: lw s3, 40(a0)
-; RV64IXQCCMP-FP-NEXT: lw s4, 44(a0)
-; RV64IXQCCMP-FP-NEXT: lw s5, 48(a0)
-; RV64IXQCCMP-FP-NEXT: lw s6, 52(a0)
-; RV64IXQCCMP-FP-NEXT: lw s7, 56(a0)
-; RV64IXQCCMP-FP-NEXT: lw s8, 60(a0)
-; RV64IXQCCMP-FP-NEXT: lw s9, 64(a0)
-; RV64IXQCCMP-FP-NEXT: lw s10, 68(a0)
-; RV64IXQCCMP-FP-NEXT: lw s11, 72(a0)
-; RV64IXQCCMP-FP-NEXT: lw ra, 76(a0)
-; RV64IXQCCMP-FP-NEXT: lw s1, 80(a0)
-; RV64IXQCCMP-FP-NEXT: lw t3, 84(a0)
-; RV64IXQCCMP-FP-NEXT: lw t2, 88(a0)
-; RV64IXQCCMP-FP-NEXT: lw t1, 92(a0)
-; RV64IXQCCMP-FP-NEXT: lw t0, 112(a0)
-; RV64IXQCCMP-FP-NEXT: lw a6, 116(a0)
+; RV64IXQCCMP-FP-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-FP-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-FP-NEXT: lw t1, 32(a0)
+; RV64IXQCCMP-FP-NEXT: lw t2, 36(a0)
+; RV64IXQCCMP-FP-NEXT: lw t3, 40(a0)
+; RV64IXQCCMP-FP-NEXT: lw t4, 44(a0)
+; RV64IXQCCMP-FP-NEXT: lw t5, 48(a0)
+; RV64IXQCCMP-FP-NEXT: lw t6, 52(a0)
+; RV64IXQCCMP-FP-NEXT: lw s1, 56(a0)
+; RV64IXQCCMP-FP-NEXT: lw s2, 60(a0)
+; RV64IXQCCMP-FP-NEXT: lw s3, 64(a0)
+; RV64IXQCCMP-FP-NEXT: lw s4, 68(a0)
+; RV64IXQCCMP-FP-NEXT: lw s5, 72(a0)
+; RV64IXQCCMP-FP-NEXT: lw s6, 76(a0)
+; RV64IXQCCMP-FP-NEXT: lw s7, 80(a0)
+; RV64IXQCCMP-FP-NEXT: lw s8, 84(a0)
+; RV64IXQCCMP-FP-NEXT: lw s9, 88(a0)
+; RV64IXQCCMP-FP-NEXT: lw s10, 92(a0)
+; RV64IXQCCMP-FP-NEXT: lw s11, 112(a0)
+; RV64IXQCCMP-FP-NEXT: lw ra, 116(a0)
; RV64IXQCCMP-FP-NEXT: lw a4, 120(a0)
; RV64IXQCCMP-FP-NEXT: lw a1, 124(a0)
-; RV64IXQCCMP-FP-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-FP-NEXT: lw a6, 96(a0)
; RV64IXQCCMP-FP-NEXT: lw a5, 100(a0)
; RV64IXQCCMP-FP-NEXT: lw a3, 104(a0)
; RV64IXQCCMP-FP-NEXT: lw a2, 108(a0)
; RV64IXQCCMP-FP-NEXT: sw a1, 124(a0)
; RV64IXQCCMP-FP-NEXT: sw a4, 120(a0)
-; RV64IXQCCMP-FP-NEXT: sw a6, 116(a0)
-; RV64IXQCCMP-FP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-FP-NEXT: sw ra, 116(a0)
+; RV64IXQCCMP-FP-NEXT: sw s11, 112(a0)
; RV64IXQCCMP-FP-NEXT: sw a2, 108(a0)
; RV64IXQCCMP-FP-NEXT: sw a3, 104(a0)
; RV64IXQCCMP-FP-NEXT: sw a5, 100(a0)
-; RV64IXQCCMP-FP-NEXT: sw a7, 96(a0)
-; RV64IXQCCMP-FP-NEXT: sw t1, 92(a0)
-; RV64IXQCCMP-FP-NEXT: sw t2, 88(a0)
-; RV64IXQCCMP-FP-NEXT: sw t3, 84(a0)
-; RV64IXQCCMP-FP-NEXT: sw s1, 80(a0)
-; RV64IXQCCMP-FP-NEXT: sw ra, 76(a0)
-; RV64IXQCCMP-FP-NEXT: sw s11, 72(a0)
-; RV64IXQCCMP-FP-NEXT: sw s10, 68(a0)
-; RV64IXQCCMP-FP-NEXT: sw s9, 64(a0)
-; RV64IXQCCMP-FP-NEXT: sw s8, 60(a0)
-; RV64IXQCCMP-FP-NEXT: sw s7, 56(a0)
-; RV64IXQCCMP-FP-NEXT: sw s6, 52(a0)
-; RV64IXQCCMP-FP-NEXT: sw s5, 48(a0)
-; RV64IXQCCMP-FP-NEXT: sw s4, 44(a0)
-; RV64IXQCCMP-FP-NEXT: sw s3, 40(a0)
-; RV64IXQCCMP-FP-NEXT: sw s2, 36(a0)
-; RV64IXQCCMP-FP-NEXT: sw t6, 32(a0)
-; RV64IXQCCMP-FP-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-FP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-FP-NEXT: sw a6, 96(a0)
+; RV64IXQCCMP-FP-NEXT: sw s10, 92(a0)
+; RV64IXQCCMP-FP-NEXT: sw s9, 88(a0)
+; RV64IXQCCMP-FP-NEXT: sw s8, 84(a0)
+; RV64IXQCCMP-FP-NEXT: sw s7, 80(a0)
+; RV64IXQCCMP-FP-NEXT: sw s6, 76(a0)
+; RV64IXQCCMP-FP-NEXT: sw s5, 72(a0)
+; RV64IXQCCMP-FP-NEXT: sw s4, 68(a0)
+; RV64IXQCCMP-FP-NEXT: sw s3, 64(a0)
+; RV64IXQCCMP-FP-NEXT: sw s2, 60(a0)
+; RV64IXQCCMP-FP-NEXT: sw s1, 56(a0)
+; RV64IXQCCMP-FP-NEXT: sw t6, 52(a0)
+; RV64IXQCCMP-FP-NEXT: sw t5, 48(a0)
+; RV64IXQCCMP-FP-NEXT: sw t4, 44(a0)
+; RV64IXQCCMP-FP-NEXT: sw t3, 40(a0)
+; RV64IXQCCMP-FP-NEXT: sw t2, 36(a0)
+; RV64IXQCCMP-FP-NEXT: sw t1, 32(a0)
+; RV64IXQCCMP-FP-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-FP-NEXT: sw a7, 24(a0)
; RV64IXQCCMP-FP-NEXT: ld a1, -280(s0) # 8-byte Folded Reload
; RV64IXQCCMP-FP-NEXT: sw a1, 20(a0)
; RV64IXQCCMP-FP-NEXT: ld a1, -272(s0) # 8-byte Folded Reload
@@ -2852,60 +2852,60 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV32IXQCCMP-SR-NEXT: sw a1, 4(sp) # 4-byte Folded Spill
; RV32IXQCCMP-SR-NEXT: lw a1, 16(a0)
; RV32IXQCCMP-SR-NEXT: sw a1, 0(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw t3, 20(a0)
-; RV32IXQCCMP-SR-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-SR-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-SR-NEXT: lw t6, 32(a0)
-; RV32IXQCCMP-SR-NEXT: lw s2, 36(a0)
-; RV32IXQCCMP-SR-NEXT: lw s3, 40(a0)
-; RV32IXQCCMP-SR-NEXT: lw s4, 44(a0)
-; RV32IXQCCMP-SR-NEXT: lw s5, 48(a0)
-; RV32IXQCCMP-SR-NEXT: lw s6, 52(a0)
-; RV32IXQCCMP-SR-NEXT: lw s7, 56(a0)
-; RV32IXQCCMP-SR-NEXT: lw s8, 60(a0)
-; RV32IXQCCMP-SR-NEXT: lw s9, 64(a0)
-; RV32IXQCCMP-SR-NEXT: lw s10, 68(a0)
-; RV32IXQCCMP-SR-NEXT: lw s11, 72(a0)
-; RV32IXQCCMP-SR-NEXT: lw ra, 76(a0)
-; RV32IXQCCMP-SR-NEXT: lw t2, 80(a0)
-; RV32IXQCCMP-SR-NEXT: lw s0, 84(a0)
-; RV32IXQCCMP-SR-NEXT: lw s1, 88(a0)
-; RV32IXQCCMP-SR-NEXT: lw t1, 92(a0)
-; RV32IXQCCMP-SR-NEXT: lw t0, 112(a0)
-; RV32IXQCCMP-SR-NEXT: lw a5, 116(a0)
-; RV32IXQCCMP-SR-NEXT: lw a3, 120(a0)
+; RV32IXQCCMP-SR-NEXT: lw a6, 20(a0)
+; RV32IXQCCMP-SR-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-SR-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-SR-NEXT: lw t1, 32(a0)
+; RV32IXQCCMP-SR-NEXT: lw t2, 36(a0)
+; RV32IXQCCMP-SR-NEXT: lw t3, 40(a0)
+; RV32IXQCCMP-SR-NEXT: lw t4, 44(a0)
+; RV32IXQCCMP-SR-NEXT: lw t5, 48(a0)
+; RV32IXQCCMP-SR-NEXT: lw t6, 52(a0)
+; RV32IXQCCMP-SR-NEXT: lw s0, 56(a0)
+; RV32IXQCCMP-SR-NEXT: lw s1, 60(a0)
+; RV32IXQCCMP-SR-NEXT: lw s2, 64(a0)
+; RV32IXQCCMP-SR-NEXT: lw s3, 68(a0)
+; RV32IXQCCMP-SR-NEXT: lw s4, 72(a0)
+; RV32IXQCCMP-SR-NEXT: lw s5, 76(a0)
+; RV32IXQCCMP-SR-NEXT: lw s6, 80(a0)
+; RV32IXQCCMP-SR-NEXT: lw s7, 84(a0)
+; RV32IXQCCMP-SR-NEXT: lw s8, 88(a0)
+; RV32IXQCCMP-SR-NEXT: lw s9, 92(a0)
+; RV32IXQCCMP-SR-NEXT: lw s10, 112(a0)
+; RV32IXQCCMP-SR-NEXT: lw s11, 116(a0)
+; RV32IXQCCMP-SR-NEXT: lw ra, 120(a0)
; RV32IXQCCMP-SR-NEXT: lw a1, 124(a0)
-; RV32IXQCCMP-SR-NEXT: lw a7, 96(a0)
-; RV32IXQCCMP-SR-NEXT: lw a6, 100(a0)
-; RV32IXQCCMP-SR-NEXT: lw a4, 104(a0)
+; RV32IXQCCMP-SR-NEXT: lw a5, 96(a0)
+; RV32IXQCCMP-SR-NEXT: lw a4, 100(a0)
+; RV32IXQCCMP-SR-NEXT: lw a3, 104(a0)
; RV32IXQCCMP-SR-NEXT: lw a2, 108(a0)
; RV32IXQCCMP-SR-NEXT: sw a1, 124(a0)
-; RV32IXQCCMP-SR-NEXT: sw a3, 120(a0)
-; RV32IXQCCMP-SR-NEXT: sw a5, 116(a0)
-; RV32IXQCCMP-SR-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-SR-NEXT: sw ra, 120(a0)
+; RV32IXQCCMP-SR-NEXT: sw s11, 116(a0)
+; RV32IXQCCMP-SR-NEXT: sw s10, 112(a0)
; RV32IXQCCMP-SR-NEXT: sw a2, 108(a0)
-; RV32IXQCCMP-SR-NEXT: sw a4, 104(a0)
-; RV32IXQCCMP-SR-NEXT: sw a6, 100(a0)
-; RV32IXQCCMP-SR-NEXT: sw a7, 96(a0)
-; RV32IXQCCMP-SR-NEXT: sw t1, 92(a0)
-; RV32IXQCCMP-SR-NEXT: sw s1, 88(a0)
-; RV32IXQCCMP-SR-NEXT: sw s0, 84(a0)
-; RV32IXQCCMP-SR-NEXT: sw t2, 80(a0)
-; RV32IXQCCMP-SR-NEXT: sw ra, 76(a0)
-; RV32IXQCCMP-SR-NEXT: sw s11, 72(a0)
-; RV32IXQCCMP-SR-NEXT: sw s10, 68(a0)
-; RV32IXQCCMP-SR-NEXT: sw s9, 64(a0)
-; RV32IXQCCMP-SR-NEXT: sw s8, 60(a0)
-; RV32IXQCCMP-SR-NEXT: sw s7, 56(a0)
-; RV32IXQCCMP-SR-NEXT: sw s6, 52(a0)
-; RV32IXQCCMP-SR-NEXT: sw s5, 48(a0)
-; RV32IXQCCMP-SR-NEXT: sw s4, 44(a0)
-; RV32IXQCCMP-SR-NEXT: sw s3, 40(a0)
-; RV32IXQCCMP-SR-NEXT: sw s2, 36(a0)
-; RV32IXQCCMP-SR-NEXT: sw t6, 32(a0)
-; RV32IXQCCMP-SR-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-SR-NEXT: sw t4, 24(a0)
-; RV32IXQCCMP-SR-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-SR-NEXT: sw a3, 104(a0)
+; RV32IXQCCMP-SR-NEXT: sw a4, 100(a0)
+; RV32IXQCCMP-SR-NEXT: sw a5, 96(a0)
+; RV32IXQCCMP-SR-NEXT: sw s9, 92(a0)
+; RV32IXQCCMP-SR-NEXT: sw s8, 88(a0)
+; RV32IXQCCMP-SR-NEXT: sw s7, 84(a0)
+; RV32IXQCCMP-SR-NEXT: sw s6, 80(a0)
+; RV32IXQCCMP-SR-NEXT: sw s5, 76(a0)
+; RV32IXQCCMP-SR-NEXT: sw s4, 72(a0)
+; RV32IXQCCMP-SR-NEXT: sw s3, 68(a0)
+; RV32IXQCCMP-SR-NEXT: sw s2, 64(a0)
+; RV32IXQCCMP-SR-NEXT: sw s1, 60(a0)
+; RV32IXQCCMP-SR-NEXT: sw s0, 56(a0)
+; RV32IXQCCMP-SR-NEXT: sw t6, 52(a0)
+; RV32IXQCCMP-SR-NEXT: sw t5, 48(a0)
+; RV32IXQCCMP-SR-NEXT: sw t4, 44(a0)
+; RV32IXQCCMP-SR-NEXT: sw t3, 40(a0)
+; RV32IXQCCMP-SR-NEXT: sw t2, 36(a0)
+; RV32IXQCCMP-SR-NEXT: sw t1, 32(a0)
+; RV32IXQCCMP-SR-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-SR-NEXT: sw a7, 24(a0)
+; RV32IXQCCMP-SR-NEXT: sw a6, 20(a0)
; RV32IXQCCMP-SR-NEXT: lw a1, 0(sp) # 4-byte Folded Reload
; RV32IXQCCMP-SR-NEXT: sw a1, 16(a0)
; RV32IXQCCMP-SR-NEXT: lw a1, 4(sp) # 4-byte Folded Reload
@@ -3026,60 +3026,60 @@ define void @callee_with_irq() "interrupt"="machine" {
; RV64IXQCCMP-SR-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
; RV64IXQCCMP-SR-NEXT: lw a1, 16(a0)
; RV64IXQCCMP-SR-NEXT: sd a1, 0(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw t3, 20(a0)
-; RV64IXQCCMP-SR-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-SR-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-SR-NEXT: lw t6, 32(a0)
-; RV64IXQCCMP-SR-NEXT: lw s2, 36(a0)
-; RV64IXQCCMP-SR-NEXT: lw s3, 40(a0)
-; RV64IXQCCMP-SR-NEXT: lw s4, 44(a0)
-; RV64IXQCCMP-SR-NEXT: lw s5, 48(a0)
-; RV64IXQCCMP-SR-NEXT: lw s6, 52(a0)
-; RV64IXQCCMP-SR-NEXT: lw s7, 56(a0)
-; RV64IXQCCMP-SR-NEXT: lw s8, 60(a0)
-; RV64IXQCCMP-SR-NEXT: lw s9, 64(a0)
-; RV64IXQCCMP-SR-NEXT: lw s10, 68(a0)
-; RV64IXQCCMP-SR-NEXT: lw s11, 72(a0)
-; RV64IXQCCMP-SR-NEXT: lw ra, 76(a0)
-; RV64IXQCCMP-SR-NEXT: lw t2, 80(a0)
-; RV64IXQCCMP-SR-NEXT: lw s0, 84(a0)
-; RV64IXQCCMP-SR-NEXT: lw s1, 88(a0)
-; RV64IXQCCMP-SR-NEXT: lw t1, 92(a0)
-; RV64IXQCCMP-SR-NEXT: lw t0, 112(a0)
-; RV64IXQCCMP-SR-NEXT: lw a5, 116(a0)
-; RV64IXQCCMP-SR-NEXT: lw a3, 120(a0)
+; RV64IXQCCMP-SR-NEXT: lw a6, 20(a0)
+; RV64IXQCCMP-SR-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-SR-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-SR-NEXT: lw t1, 32(a0)
+; RV64IXQCCMP-SR-NEXT: lw t2, 36(a0)
+; RV64IXQCCMP-SR-NEXT: lw t3, 40(a0)
+; RV64IXQCCMP-SR-NEXT: lw t4, 44(a0)
+; RV64IXQCCMP-SR-NEXT: lw t5, 48(a0)
+; RV64IXQCCMP-SR-NEXT: lw t6, 52(a0)
+; RV64IXQCCMP-SR-NEXT: lw s0, 56(a0)
+; RV64IXQCCMP-SR-NEXT: lw s1, 60(a0)
+; RV64IXQCCMP-SR-NEXT: lw s2, 64(a0)
+; RV64IXQCCMP-SR-NEXT: lw s3, 68(a0)
+; RV64IXQCCMP-SR-NEXT: lw s4, 72(a0)
+; RV64IXQCCMP-SR-NEXT: lw s5, 76(a0)
+; RV64IXQCCMP-SR-NEXT: lw s6, 80(a0)
+; RV64IXQCCMP-SR-NEXT: lw s7, 84(a0)
+; RV64IXQCCMP-SR-NEXT: lw s8, 88(a0)
+; RV64IXQCCMP-SR-NEXT: lw s9, 92(a0)
+; RV64IXQCCMP-SR-NEXT: lw s10, 112(a0)
+; RV64IXQCCMP-SR-NEXT: lw s11, 116(a0)
+; RV64IXQCCMP-SR-NEXT: lw ra, 120(a0)
; RV64IXQCCMP-SR-NEXT: lw a1, 124(a0)
-; RV64IXQCCMP-SR-NEXT: lw a7, 96(a0)
-; RV64IXQCCMP-SR-NEXT: lw a6, 100(a0)
-; RV64IXQCCMP-SR-NEXT: lw a4, 104(a0)
+; RV64IXQCCMP-SR-NEXT: lw a5, 96(a0)
+; RV64IXQCCMP-SR-NEXT: lw a4, 100(a0)
+; RV64IXQCCMP-SR-NEXT: lw a3, 104(a0)
; RV64IXQCCMP-SR-NEXT: lw a2, 108(a0)
; RV64IXQCCMP-SR-NEXT: sw a1, 124(a0)
-; RV64IXQCCMP-SR-NEXT: sw a3, 120(a0)
-; RV64IXQCCMP-SR-NEXT: sw a5, 116(a0)
-; RV64IXQCCMP-SR-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-SR-NEXT: sw ra, 120(a0)
+; RV64IXQCCMP-SR-NEXT: sw s11, 116(a0)
+; RV64IXQCCMP-SR-NEXT: sw s10, 112(a0)
; RV64IXQCCMP-SR-NEXT: sw a2, 108(a0)
-; RV64IXQCCMP-SR-NEXT: sw a4, 104(a0)
-; RV64IXQCCMP-SR-NEXT: sw a6, 100(a0)
-; RV64IXQCCMP-SR-NEXT: sw a7, 96(a0)
-; RV64IXQCCMP-SR-NEXT: sw t1, 92(a0)
-; RV64IXQCCMP-SR-NEXT: sw s1, 88(a0)
-; RV64IXQCCMP-SR-NEXT: sw s0, 84(a0)
-; RV64IXQCCMP-SR-NEXT: sw t2, 80(a0)
-; RV64IXQCCMP-SR-NEXT: sw ra, 76(a0)
-; RV64IXQCCMP-SR-NEXT: sw s11, 72(a0)
-; RV64IXQCCMP-SR-NEXT: sw s10, 68(a0)
-; RV64IXQCCMP-SR-NEXT: sw s9, 64(a0)
-; RV64IXQCCMP-SR-NEXT: sw s8, 60(a0)
-; RV64IXQCCMP-SR-NEXT: sw s7, 56(a0)
-; RV64IXQCCMP-SR-NEXT: sw s6, 52(a0)
-; RV64IXQCCMP-SR-NEXT: sw s5, 48(a0)
-; RV64IXQCCMP-SR-NEXT: sw s4, 44(a0)
-; RV64IXQCCMP-SR-NEXT: sw s3, 40(a0)
-; RV64IXQCCMP-SR-NEXT: sw s2, 36(a0)
-; RV64IXQCCMP-SR-NEXT: sw t6, 32(a0)
-; RV64IXQCCMP-SR-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-SR-NEXT: sw t4, 24(a0)
-; RV64IXQCCMP-SR-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-SR-NEXT: sw a3, 104(a0)
+; RV64IXQCCMP-SR-NEXT: sw a4, 100(a0)
+; RV64IXQCCMP-SR-NEXT: sw a5, 96(a0)
+; RV64IXQCCMP-SR-NEXT: sw s9, 92(a0)
+; RV64IXQCCMP-SR-NEXT: sw s8, 88(a0)
+; RV64IXQCCMP-SR-NEXT: sw s7, 84(a0)
+; RV64IXQCCMP-SR-NEXT: sw s6, 80(a0)
+; RV64IXQCCMP-SR-NEXT: sw s5, 76(a0)
+; RV64IXQCCMP-SR-NEXT: sw s4, 72(a0)
+; RV64IXQCCMP-SR-NEXT: sw s3, 68(a0)
+; RV64IXQCCMP-SR-NEXT: sw s2, 64(a0)
+; RV64IXQCCMP-SR-NEXT: sw s1, 60(a0)
+; RV64IXQCCMP-SR-NEXT: sw s0, 56(a0)
+; RV64IXQCCMP-SR-NEXT: sw t6, 52(a0)
+; RV64IXQCCMP-SR-NEXT: sw t5, 48(a0)
+; RV64IXQCCMP-SR-NEXT: sw t4, 44(a0)
+; RV64IXQCCMP-SR-NEXT: sw t3, 40(a0)
+; RV64IXQCCMP-SR-NEXT: sw t2, 36(a0)
+; RV64IXQCCMP-SR-NEXT: sw t1, 32(a0)
+; RV64IXQCCMP-SR-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-SR-NEXT: sw a7, 24(a0)
+; RV64IXQCCMP-SR-NEXT: sw a6, 20(a0)
; RV64IXQCCMP-SR-NEXT: ld a1, 0(sp) # 8-byte Folded Reload
; RV64IXQCCMP-SR-NEXT: sw a1, 16(a0)
; RV64IXQCCMP-SR-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
@@ -3173,60 +3173,60 @@ define void @callee_no_irq() {
; RV32IXQCCMP-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; RV32IXQCCMP-NEXT: lw a1, 16(a0)
; RV32IXQCCMP-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-NEXT: lw t3, 20(a0)
-; RV32IXQCCMP-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-NEXT: lw t6, 32(a0)
-; RV32IXQCCMP-NEXT: lw s2, 36(a0)
-; RV32IXQCCMP-NEXT: lw s3, 40(a0)
-; RV32IXQCCMP-NEXT: lw s4, 44(a0)
-; RV32IXQCCMP-NEXT: lw s5, 48(a0)
-; RV32IXQCCMP-NEXT: lw s6, 52(a0)
-; RV32IXQCCMP-NEXT: lw s7, 56(a0)
-; RV32IXQCCMP-NEXT: lw s8, 60(a0)
-; RV32IXQCCMP-NEXT: lw s9, 64(a0)
-; RV32IXQCCMP-NEXT: lw s10, 68(a0)
-; RV32IXQCCMP-NEXT: lw s11, 72(a0)
-; RV32IXQCCMP-NEXT: lw ra, 76(a0)
-; RV32IXQCCMP-NEXT: lw t2, 80(a0)
-; RV32IXQCCMP-NEXT: lw s0, 84(a0)
-; RV32IXQCCMP-NEXT: lw s1, 88(a0)
-; RV32IXQCCMP-NEXT: lw t1, 92(a0)
-; RV32IXQCCMP-NEXT: lw t0, 112(a0)
-; RV32IXQCCMP-NEXT: lw a5, 116(a0)
-; RV32IXQCCMP-NEXT: lw a3, 120(a0)
+; RV32IXQCCMP-NEXT: lw a6, 20(a0)
+; RV32IXQCCMP-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-NEXT: lw t1, 32(a0)
+; RV32IXQCCMP-NEXT: lw t2, 36(a0)
+; RV32IXQCCMP-NEXT: lw t3, 40(a0)
+; RV32IXQCCMP-NEXT: lw t4, 44(a0)
+; RV32IXQCCMP-NEXT: lw t5, 48(a0)
+; RV32IXQCCMP-NEXT: lw t6, 52(a0)
+; RV32IXQCCMP-NEXT: lw s0, 56(a0)
+; RV32IXQCCMP-NEXT: lw s1, 60(a0)
+; RV32IXQCCMP-NEXT: lw s2, 64(a0)
+; RV32IXQCCMP-NEXT: lw s3, 68(a0)
+; RV32IXQCCMP-NEXT: lw s4, 72(a0)
+; RV32IXQCCMP-NEXT: lw s5, 76(a0)
+; RV32IXQCCMP-NEXT: lw s6, 80(a0)
+; RV32IXQCCMP-NEXT: lw s7, 84(a0)
+; RV32IXQCCMP-NEXT: lw s8, 88(a0)
+; RV32IXQCCMP-NEXT: lw s9, 92(a0)
+; RV32IXQCCMP-NEXT: lw s10, 112(a0)
+; RV32IXQCCMP-NEXT: lw s11, 116(a0)
+; RV32IXQCCMP-NEXT: lw ra, 120(a0)
; RV32IXQCCMP-NEXT: lw a1, 124(a0)
-; RV32IXQCCMP-NEXT: lw a7, 96(a0)
-; RV32IXQCCMP-NEXT: lw a6, 100(a0)
-; RV32IXQCCMP-NEXT: lw a4, 104(a0)
+; RV32IXQCCMP-NEXT: lw a5, 96(a0)
+; RV32IXQCCMP-NEXT: lw a4, 100(a0)
+; RV32IXQCCMP-NEXT: lw a3, 104(a0)
; RV32IXQCCMP-NEXT: lw a2, 108(a0)
; RV32IXQCCMP-NEXT: sw a1, 124(a0)
-; RV32IXQCCMP-NEXT: sw a3, 120(a0)
-; RV32IXQCCMP-NEXT: sw a5, 116(a0)
-; RV32IXQCCMP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-NEXT: sw ra, 120(a0)
+; RV32IXQCCMP-NEXT: sw s11, 116(a0)
+; RV32IXQCCMP-NEXT: sw s10, 112(a0)
; RV32IXQCCMP-NEXT: sw a2, 108(a0)
-; RV32IXQCCMP-NEXT: sw a4, 104(a0)
-; RV32IXQCCMP-NEXT: sw a6, 100(a0)
-; RV32IXQCCMP-NEXT: sw a7, 96(a0)
-; RV32IXQCCMP-NEXT: sw t1, 92(a0)
-; RV32IXQCCMP-NEXT: sw s1, 88(a0)
-; RV32IXQCCMP-NEXT: sw s0, 84(a0)
-; RV32IXQCCMP-NEXT: sw t2, 80(a0)
-; RV32IXQCCMP-NEXT: sw ra, 76(a0)
-; RV32IXQCCMP-NEXT: sw s11, 72(a0)
-; RV32IXQCCMP-NEXT: sw s10, 68(a0)
-; RV32IXQCCMP-NEXT: sw s9, 64(a0)
-; RV32IXQCCMP-NEXT: sw s8, 60(a0)
-; RV32IXQCCMP-NEXT: sw s7, 56(a0)
-; RV32IXQCCMP-NEXT: sw s6, 52(a0)
-; RV32IXQCCMP-NEXT: sw s5, 48(a0)
-; RV32IXQCCMP-NEXT: sw s4, 44(a0)
-; RV32IXQCCMP-NEXT: sw s3, 40(a0)
-; RV32IXQCCMP-NEXT: sw s2, 36(a0)
-; RV32IXQCCMP-NEXT: sw t6, 32(a0)
-; RV32IXQCCMP-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-NEXT: sw t4, 24(a0)
-; RV32IXQCCMP-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-NEXT: sw a3, 104(a0)
+; RV32IXQCCMP-NEXT: sw a4, 100(a0)
+; RV32IXQCCMP-NEXT: sw a5, 96(a0)
+; RV32IXQCCMP-NEXT: sw s9, 92(a0)
+; RV32IXQCCMP-NEXT: sw s8, 88(a0)
+; RV32IXQCCMP-NEXT: sw s7, 84(a0)
+; RV32IXQCCMP-NEXT: sw s6, 80(a0)
+; RV32IXQCCMP-NEXT: sw s5, 76(a0)
+; RV32IXQCCMP-NEXT: sw s4, 72(a0)
+; RV32IXQCCMP-NEXT: sw s3, 68(a0)
+; RV32IXQCCMP-NEXT: sw s2, 64(a0)
+; RV32IXQCCMP-NEXT: sw s1, 60(a0)
+; RV32IXQCCMP-NEXT: sw s0, 56(a0)
+; RV32IXQCCMP-NEXT: sw t6, 52(a0)
+; RV32IXQCCMP-NEXT: sw t5, 48(a0)
+; RV32IXQCCMP-NEXT: sw t4, 44(a0)
+; RV32IXQCCMP-NEXT: sw t3, 40(a0)
+; RV32IXQCCMP-NEXT: sw t2, 36(a0)
+; RV32IXQCCMP-NEXT: sw t1, 32(a0)
+; RV32IXQCCMP-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-NEXT: sw a7, 24(a0)
+; RV32IXQCCMP-NEXT: sw a6, 20(a0)
; RV32IXQCCMP-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; RV32IXQCCMP-NEXT: sw a1, 16(a0)
; RV32IXQCCMP-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -3268,60 +3268,60 @@ define void @callee_no_irq() {
; RV64IXQCCMP-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
; RV64IXQCCMP-NEXT: lw a1, 16(a0)
; RV64IXQCCMP-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-NEXT: lw t3, 20(a0)
-; RV64IXQCCMP-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-NEXT: lw t6, 32(a0)
-; RV64IXQCCMP-NEXT: lw s2, 36(a0)
-; RV64IXQCCMP-NEXT: lw s3, 40(a0)
-; RV64IXQCCMP-NEXT: lw s4, 44(a0)
-; RV64IXQCCMP-NEXT: lw s5, 48(a0)
-; RV64IXQCCMP-NEXT: lw s6, 52(a0)
-; RV64IXQCCMP-NEXT: lw s7, 56(a0)
-; RV64IXQCCMP-NEXT: lw s8, 60(a0)
-; RV64IXQCCMP-NEXT: lw s9, 64(a0)
-; RV64IXQCCMP-NEXT: lw s10, 68(a0)
-; RV64IXQCCMP-NEXT: lw s11, 72(a0)
-; RV64IXQCCMP-NEXT: lw ra, 76(a0)
-; RV64IXQCCMP-NEXT: lw t2, 80(a0)
-; RV64IXQCCMP-NEXT: lw s0, 84(a0)
-; RV64IXQCCMP-NEXT: lw s1, 88(a0)
-; RV64IXQCCMP-NEXT: lw t1, 92(a0)
-; RV64IXQCCMP-NEXT: lw t0, 112(a0)
-; RV64IXQCCMP-NEXT: lw a5, 116(a0)
-; RV64IXQCCMP-NEXT: lw a3, 120(a0)
+; RV64IXQCCMP-NEXT: lw a6, 20(a0)
+; RV64IXQCCMP-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-NEXT: lw t1, 32(a0)
+; RV64IXQCCMP-NEXT: lw t2, 36(a0)
+; RV64IXQCCMP-NEXT: lw t3, 40(a0)
+; RV64IXQCCMP-NEXT: lw t4, 44(a0)
+; RV64IXQCCMP-NEXT: lw t5, 48(a0)
+; RV64IXQCCMP-NEXT: lw t6, 52(a0)
+; RV64IXQCCMP-NEXT: lw s0, 56(a0)
+; RV64IXQCCMP-NEXT: lw s1, 60(a0)
+; RV64IXQCCMP-NEXT: lw s2, 64(a0)
+; RV64IXQCCMP-NEXT: lw s3, 68(a0)
+; RV64IXQCCMP-NEXT: lw s4, 72(a0)
+; RV64IXQCCMP-NEXT: lw s5, 76(a0)
+; RV64IXQCCMP-NEXT: lw s6, 80(a0)
+; RV64IXQCCMP-NEXT: lw s7, 84(a0)
+; RV64IXQCCMP-NEXT: lw s8, 88(a0)
+; RV64IXQCCMP-NEXT: lw s9, 92(a0)
+; RV64IXQCCMP-NEXT: lw s10, 112(a0)
+; RV64IXQCCMP-NEXT: lw s11, 116(a0)
+; RV64IXQCCMP-NEXT: lw ra, 120(a0)
; RV64IXQCCMP-NEXT: lw a1, 124(a0)
-; RV64IXQCCMP-NEXT: lw a7, 96(a0)
-; RV64IXQCCMP-NEXT: lw a6, 100(a0)
-; RV64IXQCCMP-NEXT: lw a4, 104(a0)
+; RV64IXQCCMP-NEXT: lw a5, 96(a0)
+; RV64IXQCCMP-NEXT: lw a4, 100(a0)
+; RV64IXQCCMP-NEXT: lw a3, 104(a0)
; RV64IXQCCMP-NEXT: lw a2, 108(a0)
; RV64IXQCCMP-NEXT: sw a1, 124(a0)
-; RV64IXQCCMP-NEXT: sw a3, 120(a0)
-; RV64IXQCCMP-NEXT: sw a5, 116(a0)
-; RV64IXQCCMP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-NEXT: sw ra, 120(a0)
+; RV64IXQCCMP-NEXT: sw s11, 116(a0)
+; RV64IXQCCMP-NEXT: sw s10, 112(a0)
; RV64IXQCCMP-NEXT: sw a2, 108(a0)
-; RV64IXQCCMP-NEXT: sw a4, 104(a0)
-; RV64IXQCCMP-NEXT: sw a6, 100(a0)
-; RV64IXQCCMP-NEXT: sw a7, 96(a0)
-; RV64IXQCCMP-NEXT: sw t1, 92(a0)
-; RV64IXQCCMP-NEXT: sw s1, 88(a0)
-; RV64IXQCCMP-NEXT: sw s0, 84(a0)
-; RV64IXQCCMP-NEXT: sw t2, 80(a0)
-; RV64IXQCCMP-NEXT: sw ra, 76(a0)
-; RV64IXQCCMP-NEXT: sw s11, 72(a0)
-; RV64IXQCCMP-NEXT: sw s10, 68(a0)
-; RV64IXQCCMP-NEXT: sw s9, 64(a0)
-; RV64IXQCCMP-NEXT: sw s8, 60(a0)
-; RV64IXQCCMP-NEXT: sw s7, 56(a0)
-; RV64IXQCCMP-NEXT: sw s6, 52(a0)
-; RV64IXQCCMP-NEXT: sw s5, 48(a0)
-; RV64IXQCCMP-NEXT: sw s4, 44(a0)
-; RV64IXQCCMP-NEXT: sw s3, 40(a0)
-; RV64IXQCCMP-NEXT: sw s2, 36(a0)
-; RV64IXQCCMP-NEXT: sw t6, 32(a0)
-; RV64IXQCCMP-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-NEXT: sw t4, 24(a0)
-; RV64IXQCCMP-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-NEXT: sw a3, 104(a0)
+; RV64IXQCCMP-NEXT: sw a4, 100(a0)
+; RV64IXQCCMP-NEXT: sw a5, 96(a0)
+; RV64IXQCCMP-NEXT: sw s9, 92(a0)
+; RV64IXQCCMP-NEXT: sw s8, 88(a0)
+; RV64IXQCCMP-NEXT: sw s7, 84(a0)
+; RV64IXQCCMP-NEXT: sw s6, 80(a0)
+; RV64IXQCCMP-NEXT: sw s5, 76(a0)
+; RV64IXQCCMP-NEXT: sw s4, 72(a0)
+; RV64IXQCCMP-NEXT: sw s3, 68(a0)
+; RV64IXQCCMP-NEXT: sw s2, 64(a0)
+; RV64IXQCCMP-NEXT: sw s1, 60(a0)
+; RV64IXQCCMP-NEXT: sw s0, 56(a0)
+; RV64IXQCCMP-NEXT: sw t6, 52(a0)
+; RV64IXQCCMP-NEXT: sw t5, 48(a0)
+; RV64IXQCCMP-NEXT: sw t4, 44(a0)
+; RV64IXQCCMP-NEXT: sw t3, 40(a0)
+; RV64IXQCCMP-NEXT: sw t2, 36(a0)
+; RV64IXQCCMP-NEXT: sw t1, 32(a0)
+; RV64IXQCCMP-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-NEXT: sw a7, 24(a0)
+; RV64IXQCCMP-NEXT: sw a6, 20(a0)
; RV64IXQCCMP-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
; RV64IXQCCMP-NEXT: sw a1, 16(a0)
; RV64IXQCCMP-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
@@ -3366,58 +3366,58 @@ define void @callee_no_irq() {
; RV32IXQCCMP-FP-NEXT: sw a1, -84(s0) # 4-byte Folded Spill
; RV32IXQCCMP-FP-NEXT: lw a1, 20(a0)
; RV32IXQCCMP-FP-NEXT: sw a1, -88(s0) # 4-byte Folded Spill
-; RV32IXQCCMP-FP-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-FP-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-FP-NEXT: lw t6, 32(a0)
-; RV32IXQCCMP-FP-NEXT: lw s2, 36(a0)
-; RV32IXQCCMP-FP-NEXT: lw s3, 40(a0)
-; RV32IXQCCMP-FP-NEXT: lw s4, 44(a0)
-; RV32IXQCCMP-FP-NEXT: lw s5, 48(a0)
-; RV32IXQCCMP-FP-NEXT: lw s6, 52(a0)
-; RV32IXQCCMP-FP-NEXT: lw s7, 56(a0)
-; RV32IXQCCMP-FP-NEXT: lw s8, 60(a0)
-; RV32IXQCCMP-FP-NEXT: lw s9, 64(a0)
-; RV32IXQCCMP-FP-NEXT: lw s10, 68(a0)
-; RV32IXQCCMP-FP-NEXT: lw s11, 72(a0)
-; RV32IXQCCMP-FP-NEXT: lw ra, 76(a0)
-; RV32IXQCCMP-FP-NEXT: lw s1, 80(a0)
-; RV32IXQCCMP-FP-NEXT: lw t3, 84(a0)
-; RV32IXQCCMP-FP-NEXT: lw t2, 88(a0)
-; RV32IXQCCMP-FP-NEXT: lw t1, 92(a0)
-; RV32IXQCCMP-FP-NEXT: lw t0, 112(a0)
-; RV32IXQCCMP-FP-NEXT: lw a6, 116(a0)
+; RV32IXQCCMP-FP-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-FP-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-FP-NEXT: lw t1, 32(a0)
+; RV32IXQCCMP-FP-NEXT: lw t2, 36(a0)
+; RV32IXQCCMP-FP-NEXT: lw t3, 40(a0)
+; RV32IXQCCMP-FP-NEXT: lw t4, 44(a0)
+; RV32IXQCCMP-FP-NEXT: lw t5, 48(a0)
+; RV32IXQCCMP-FP-NEXT: lw t6, 52(a0)
+; RV32IXQCCMP-FP-NEXT: lw s1, 56(a0)
+; RV32IXQCCMP-FP-NEXT: lw s2, 60(a0)
+; RV32IXQCCMP-FP-NEXT: lw s3, 64(a0)
+; RV32IXQCCMP-FP-NEXT: lw s4, 68(a0)
+; RV32IXQCCMP-FP-NEXT: lw s5, 72(a0)
+; RV32IXQCCMP-FP-NEXT: lw s6, 76(a0)
+; RV32IXQCCMP-FP-NEXT: lw s7, 80(a0)
+; RV32IXQCCMP-FP-NEXT: lw s8, 84(a0)
+; RV32IXQCCMP-FP-NEXT: lw s9, 88(a0)
+; RV32IXQCCMP-FP-NEXT: lw s10, 92(a0)
+; RV32IXQCCMP-FP-NEXT: lw s11, 112(a0)
+; RV32IXQCCMP-FP-NEXT: lw ra, 116(a0)
; RV32IXQCCMP-FP-NEXT: lw a4, 120(a0)
; RV32IXQCCMP-FP-NEXT: lw a1, 124(a0)
-; RV32IXQCCMP-FP-NEXT: lw a7, 96(a0)
+; RV32IXQCCMP-FP-NEXT: lw a6, 96(a0)
; RV32IXQCCMP-FP-NEXT: lw a5, 100(a0)
; RV32IXQCCMP-FP-NEXT: lw a3, 104(a0)
; RV32IXQCCMP-FP-NEXT: lw a2, 108(a0)
; RV32IXQCCMP-FP-NEXT: sw a1, 124(a0)
; RV32IXQCCMP-FP-NEXT: sw a4, 120(a0)
-; RV32IXQCCMP-FP-NEXT: sw a6, 116(a0)
-; RV32IXQCCMP-FP-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-FP-NEXT: sw ra, 116(a0)
+; RV32IXQCCMP-FP-NEXT: sw s11, 112(a0)
; RV32IXQCCMP-FP-NEXT: sw a2, 108(a0)
; RV32IXQCCMP-FP-NEXT: sw a3, 104(a0)
; RV32IXQCCMP-FP-NEXT: sw a5, 100(a0)
-; RV32IXQCCMP-FP-NEXT: sw a7, 96(a0)
-; RV32IXQCCMP-FP-NEXT: sw t1, 92(a0)
-; RV32IXQCCMP-FP-NEXT: sw t2, 88(a0)
-; RV32IXQCCMP-FP-NEXT: sw t3, 84(a0)
-; RV32IXQCCMP-FP-NEXT: sw s1, 80(a0)
-; RV32IXQCCMP-FP-NEXT: sw ra, 76(a0)
-; RV32IXQCCMP-FP-NEXT: sw s11, 72(a0)
-; RV32IXQCCMP-FP-NEXT: sw s10, 68(a0)
-; RV32IXQCCMP-FP-NEXT: sw s9, 64(a0)
-; RV32IXQCCMP-FP-NEXT: sw s8, 60(a0)
-; RV32IXQCCMP-FP-NEXT: sw s7, 56(a0)
-; RV32IXQCCMP-FP-NEXT: sw s6, 52(a0)
-; RV32IXQCCMP-FP-NEXT: sw s5, 48(a0)
-; RV32IXQCCMP-FP-NEXT: sw s4, 44(a0)
-; RV32IXQCCMP-FP-NEXT: sw s3, 40(a0)
-; RV32IXQCCMP-FP-NEXT: sw s2, 36(a0)
-; RV32IXQCCMP-FP-NEXT: sw t6, 32(a0)
-; RV32IXQCCMP-FP-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-FP-NEXT: sw t4, 24(a0)
+; RV32IXQCCMP-FP-NEXT: sw a6, 96(a0)
+; RV32IXQCCMP-FP-NEXT: sw s10, 92(a0)
+; RV32IXQCCMP-FP-NEXT: sw s9, 88(a0)
+; RV32IXQCCMP-FP-NEXT: sw s8, 84(a0)
+; RV32IXQCCMP-FP-NEXT: sw s7, 80(a0)
+; RV32IXQCCMP-FP-NEXT: sw s6, 76(a0)
+; RV32IXQCCMP-FP-NEXT: sw s5, 72(a0)
+; RV32IXQCCMP-FP-NEXT: sw s4, 68(a0)
+; RV32IXQCCMP-FP-NEXT: sw s3, 64(a0)
+; RV32IXQCCMP-FP-NEXT: sw s2, 60(a0)
+; RV32IXQCCMP-FP-NEXT: sw s1, 56(a0)
+; RV32IXQCCMP-FP-NEXT: sw t6, 52(a0)
+; RV32IXQCCMP-FP-NEXT: sw t5, 48(a0)
+; RV32IXQCCMP-FP-NEXT: sw t4, 44(a0)
+; RV32IXQCCMP-FP-NEXT: sw t3, 40(a0)
+; RV32IXQCCMP-FP-NEXT: sw t2, 36(a0)
+; RV32IXQCCMP-FP-NEXT: sw t1, 32(a0)
+; RV32IXQCCMP-FP-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-FP-NEXT: sw a7, 24(a0)
; RV32IXQCCMP-FP-NEXT: lw a1, -88(s0) # 4-byte Folded Reload
; RV32IXQCCMP-FP-NEXT: sw a1, 20(a0)
; RV32IXQCCMP-FP-NEXT: lw a1, -84(s0) # 4-byte Folded Reload
@@ -3465,58 +3465,58 @@ define void @callee_no_irq() {
; RV64IXQCCMP-FP-NEXT: sd a1, -152(s0) # 8-byte Folded Spill
; RV64IXQCCMP-FP-NEXT: lw a1, 20(a0)
; RV64IXQCCMP-FP-NEXT: sd a1, -160(s0) # 8-byte Folded Spill
-; RV64IXQCCMP-FP-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-FP-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-FP-NEXT: lw t6, 32(a0)
-; RV64IXQCCMP-FP-NEXT: lw s2, 36(a0)
-; RV64IXQCCMP-FP-NEXT: lw s3, 40(a0)
-; RV64IXQCCMP-FP-NEXT: lw s4, 44(a0)
-; RV64IXQCCMP-FP-NEXT: lw s5, 48(a0)
-; RV64IXQCCMP-FP-NEXT: lw s6, 52(a0)
-; RV64IXQCCMP-FP-NEXT: lw s7, 56(a0)
-; RV64IXQCCMP-FP-NEXT: lw s8, 60(a0)
-; RV64IXQCCMP-FP-NEXT: lw s9, 64(a0)
-; RV64IXQCCMP-FP-NEXT: lw s10, 68(a0)
-; RV64IXQCCMP-FP-NEXT: lw s11, 72(a0)
-; RV64IXQCCMP-FP-NEXT: lw ra, 76(a0)
-; RV64IXQCCMP-FP-NEXT: lw s1, 80(a0)
-; RV64IXQCCMP-FP-NEXT: lw t3, 84(a0)
-; RV64IXQCCMP-FP-NEXT: lw t2, 88(a0)
-; RV64IXQCCMP-FP-NEXT: lw t1, 92(a0)
-; RV64IXQCCMP-FP-NEXT: lw t0, 112(a0)
-; RV64IXQCCMP-FP-NEXT: lw a6, 116(a0)
+; RV64IXQCCMP-FP-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-FP-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-FP-NEXT: lw t1, 32(a0)
+; RV64IXQCCMP-FP-NEXT: lw t2, 36(a0)
+; RV64IXQCCMP-FP-NEXT: lw t3, 40(a0)
+; RV64IXQCCMP-FP-NEXT: lw t4, 44(a0)
+; RV64IXQCCMP-FP-NEXT: lw t5, 48(a0)
+; RV64IXQCCMP-FP-NEXT: lw t6, 52(a0)
+; RV64IXQCCMP-FP-NEXT: lw s1, 56(a0)
+; RV64IXQCCMP-FP-NEXT: lw s2, 60(a0)
+; RV64IXQCCMP-FP-NEXT: lw s3, 64(a0)
+; RV64IXQCCMP-FP-NEXT: lw s4, 68(a0)
+; RV64IXQCCMP-FP-NEXT: lw s5, 72(a0)
+; RV64IXQCCMP-FP-NEXT: lw s6, 76(a0)
+; RV64IXQCCMP-FP-NEXT: lw s7, 80(a0)
+; RV64IXQCCMP-FP-NEXT: lw s8, 84(a0)
+; RV64IXQCCMP-FP-NEXT: lw s9, 88(a0)
+; RV64IXQCCMP-FP-NEXT: lw s10, 92(a0)
+; RV64IXQCCMP-FP-NEXT: lw s11, 112(a0)
+; RV64IXQCCMP-FP-NEXT: lw ra, 116(a0)
; RV64IXQCCMP-FP-NEXT: lw a4, 120(a0)
; RV64IXQCCMP-FP-NEXT: lw a1, 124(a0)
-; RV64IXQCCMP-FP-NEXT: lw a7, 96(a0)
+; RV64IXQCCMP-FP-NEXT: lw a6, 96(a0)
; RV64IXQCCMP-FP-NEXT: lw a5, 100(a0)
; RV64IXQCCMP-FP-NEXT: lw a3, 104(a0)
; RV64IXQCCMP-FP-NEXT: lw a2, 108(a0)
; RV64IXQCCMP-FP-NEXT: sw a1, 124(a0)
; RV64IXQCCMP-FP-NEXT: sw a4, 120(a0)
-; RV64IXQCCMP-FP-NEXT: sw a6, 116(a0)
-; RV64IXQCCMP-FP-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-FP-NEXT: sw ra, 116(a0)
+; RV64IXQCCMP-FP-NEXT: sw s11, 112(a0)
; RV64IXQCCMP-FP-NEXT: sw a2, 108(a0)
; RV64IXQCCMP-FP-NEXT: sw a3, 104(a0)
; RV64IXQCCMP-FP-NEXT: sw a5, 100(a0)
-; RV64IXQCCMP-FP-NEXT: sw a7, 96(a0)
-; RV64IXQCCMP-FP-NEXT: sw t1, 92(a0)
-; RV64IXQCCMP-FP-NEXT: sw t2, 88(a0)
-; RV64IXQCCMP-FP-NEXT: sw t3, 84(a0)
-; RV64IXQCCMP-FP-NEXT: sw s1, 80(a0)
-; RV64IXQCCMP-FP-NEXT: sw ra, 76(a0)
-; RV64IXQCCMP-FP-NEXT: sw s11, 72(a0)
-; RV64IXQCCMP-FP-NEXT: sw s10, 68(a0)
-; RV64IXQCCMP-FP-NEXT: sw s9, 64(a0)
-; RV64IXQCCMP-FP-NEXT: sw s8, 60(a0)
-; RV64IXQCCMP-FP-NEXT: sw s7, 56(a0)
-; RV64IXQCCMP-FP-NEXT: sw s6, 52(a0)
-; RV64IXQCCMP-FP-NEXT: sw s5, 48(a0)
-; RV64IXQCCMP-FP-NEXT: sw s4, 44(a0)
-; RV64IXQCCMP-FP-NEXT: sw s3, 40(a0)
-; RV64IXQCCMP-FP-NEXT: sw s2, 36(a0)
-; RV64IXQCCMP-FP-NEXT: sw t6, 32(a0)
-; RV64IXQCCMP-FP-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-FP-NEXT: sw t4, 24(a0)
+; RV64IXQCCMP-FP-NEXT: sw a6, 96(a0)
+; RV64IXQCCMP-FP-NEXT: sw s10, 92(a0)
+; RV64IXQCCMP-FP-NEXT: sw s9, 88(a0)
+; RV64IXQCCMP-FP-NEXT: sw s8, 84(a0)
+; RV64IXQCCMP-FP-NEXT: sw s7, 80(a0)
+; RV64IXQCCMP-FP-NEXT: sw s6, 76(a0)
+; RV64IXQCCMP-FP-NEXT: sw s5, 72(a0)
+; RV64IXQCCMP-FP-NEXT: sw s4, 68(a0)
+; RV64IXQCCMP-FP-NEXT: sw s3, 64(a0)
+; RV64IXQCCMP-FP-NEXT: sw s2, 60(a0)
+; RV64IXQCCMP-FP-NEXT: sw s1, 56(a0)
+; RV64IXQCCMP-FP-NEXT: sw t6, 52(a0)
+; RV64IXQCCMP-FP-NEXT: sw t5, 48(a0)
+; RV64IXQCCMP-FP-NEXT: sw t4, 44(a0)
+; RV64IXQCCMP-FP-NEXT: sw t3, 40(a0)
+; RV64IXQCCMP-FP-NEXT: sw t2, 36(a0)
+; RV64IXQCCMP-FP-NEXT: sw t1, 32(a0)
+; RV64IXQCCMP-FP-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-FP-NEXT: sw a7, 24(a0)
; RV64IXQCCMP-FP-NEXT: ld a1, -160(s0) # 8-byte Folded Reload
; RV64IXQCCMP-FP-NEXT: sw a1, 20(a0)
; RV64IXQCCMP-FP-NEXT: ld a1, -152(s0) # 8-byte Folded Reload
@@ -3561,60 +3561,60 @@ define void @callee_no_irq() {
; RV32IXQCCMP-SR-NEXT: sw a1, 16(sp) # 4-byte Folded Spill
; RV32IXQCCMP-SR-NEXT: lw a1, 16(a0)
; RV32IXQCCMP-SR-NEXT: sw a1, 12(sp) # 4-byte Folded Spill
-; RV32IXQCCMP-SR-NEXT: lw t3, 20(a0)
-; RV32IXQCCMP-SR-NEXT: lw t4, 24(a0)
-; RV32IXQCCMP-SR-NEXT: lw t5, 28(a0)
-; RV32IXQCCMP-SR-NEXT: lw t6, 32(a0)
-; RV32IXQCCMP-SR-NEXT: lw s2, 36(a0)
-; RV32IXQCCMP-SR-NEXT: lw s3, 40(a0)
-; RV32IXQCCMP-SR-NEXT: lw s4, 44(a0)
-; RV32IXQCCMP-SR-NEXT: lw s5, 48(a0)
-; RV32IXQCCMP-SR-NEXT: lw s6, 52(a0)
-; RV32IXQCCMP-SR-NEXT: lw s7, 56(a0)
-; RV32IXQCCMP-SR-NEXT: lw s8, 60(a0)
-; RV32IXQCCMP-SR-NEXT: lw s9, 64(a0)
-; RV32IXQCCMP-SR-NEXT: lw s10, 68(a0)
-; RV32IXQCCMP-SR-NEXT: lw s11, 72(a0)
-; RV32IXQCCMP-SR-NEXT: lw ra, 76(a0)
-; RV32IXQCCMP-SR-NEXT: lw t2, 80(a0)
-; RV32IXQCCMP-SR-NEXT: lw s0, 84(a0)
-; RV32IXQCCMP-SR-NEXT: lw s1, 88(a0)
-; RV32IXQCCMP-SR-NEXT: lw t1, 92(a0)
-; RV32IXQCCMP-SR-NEXT: lw t0, 112(a0)
-; RV32IXQCCMP-SR-NEXT: lw a5, 116(a0)
-; RV32IXQCCMP-SR-NEXT: lw a3, 120(a0)
+; RV32IXQCCMP-SR-NEXT: lw a6, 20(a0)
+; RV32IXQCCMP-SR-NEXT: lw a7, 24(a0)
+; RV32IXQCCMP-SR-NEXT: lw t0, 28(a0)
+; RV32IXQCCMP-SR-NEXT: lw t1, 32(a0)
+; RV32IXQCCMP-SR-NEXT: lw t2, 36(a0)
+; RV32IXQCCMP-SR-NEXT: lw t3, 40(a0)
+; RV32IXQCCMP-SR-NEXT: lw t4, 44(a0)
+; RV32IXQCCMP-SR-NEXT: lw t5, 48(a0)
+; RV32IXQCCMP-SR-NEXT: lw t6, 52(a0)
+; RV32IXQCCMP-SR-NEXT: lw s0, 56(a0)
+; RV32IXQCCMP-SR-NEXT: lw s1, 60(a0)
+; RV32IXQCCMP-SR-NEXT: lw s2, 64(a0)
+; RV32IXQCCMP-SR-NEXT: lw s3, 68(a0)
+; RV32IXQCCMP-SR-NEXT: lw s4, 72(a0)
+; RV32IXQCCMP-SR-NEXT: lw s5, 76(a0)
+; RV32IXQCCMP-SR-NEXT: lw s6, 80(a0)
+; RV32IXQCCMP-SR-NEXT: lw s7, 84(a0)
+; RV32IXQCCMP-SR-NEXT: lw s8, 88(a0)
+; RV32IXQCCMP-SR-NEXT: lw s9, 92(a0)
+; RV32IXQCCMP-SR-NEXT: lw s10, 112(a0)
+; RV32IXQCCMP-SR-NEXT: lw s11, 116(a0)
+; RV32IXQCCMP-SR-NEXT: lw ra, 120(a0)
; RV32IXQCCMP-SR-NEXT: lw a1, 124(a0)
-; RV32IXQCCMP-SR-NEXT: lw a7, 96(a0)
-; RV32IXQCCMP-SR-NEXT: lw a6, 100(a0)
-; RV32IXQCCMP-SR-NEXT: lw a4, 104(a0)
+; RV32IXQCCMP-SR-NEXT: lw a5, 96(a0)
+; RV32IXQCCMP-SR-NEXT: lw a4, 100(a0)
+; RV32IXQCCMP-SR-NEXT: lw a3, 104(a0)
; RV32IXQCCMP-SR-NEXT: lw a2, 108(a0)
; RV32IXQCCMP-SR-NEXT: sw a1, 124(a0)
-; RV32IXQCCMP-SR-NEXT: sw a3, 120(a0)
-; RV32IXQCCMP-SR-NEXT: sw a5, 116(a0)
-; RV32IXQCCMP-SR-NEXT: sw t0, 112(a0)
+; RV32IXQCCMP-SR-NEXT: sw ra, 120(a0)
+; RV32IXQCCMP-SR-NEXT: sw s11, 116(a0)
+; RV32IXQCCMP-SR-NEXT: sw s10, 112(a0)
; RV32IXQCCMP-SR-NEXT: sw a2, 108(a0)
-; RV32IXQCCMP-SR-NEXT: sw a4, 104(a0)
-; RV32IXQCCMP-SR-NEXT: sw a6, 100(a0)
-; RV32IXQCCMP-SR-NEXT: sw a7, 96(a0)
-; RV32IXQCCMP-SR-NEXT: sw t1, 92(a0)
-; RV32IXQCCMP-SR-NEXT: sw s1, 88(a0)
-; RV32IXQCCMP-SR-NEXT: sw s0, 84(a0)
-; RV32IXQCCMP-SR-NEXT: sw t2, 80(a0)
-; RV32IXQCCMP-SR-NEXT: sw ra, 76(a0)
-; RV32IXQCCMP-SR-NEXT: sw s11, 72(a0)
-; RV32IXQCCMP-SR-NEXT: sw s10, 68(a0)
-; RV32IXQCCMP-SR-NEXT: sw s9, 64(a0)
-; RV32IXQCCMP-SR-NEXT: sw s8, 60(a0)
-; RV32IXQCCMP-SR-NEXT: sw s7, 56(a0)
-; RV32IXQCCMP-SR-NEXT: sw s6, 52(a0)
-; RV32IXQCCMP-SR-NEXT: sw s5, 48(a0)
-; RV32IXQCCMP-SR-NEXT: sw s4, 44(a0)
-; RV32IXQCCMP-SR-NEXT: sw s3, 40(a0)
-; RV32IXQCCMP-SR-NEXT: sw s2, 36(a0)
-; RV32IXQCCMP-SR-NEXT: sw t6, 32(a0)
-; RV32IXQCCMP-SR-NEXT: sw t5, 28(a0)
-; RV32IXQCCMP-SR-NEXT: sw t4, 24(a0)
-; RV32IXQCCMP-SR-NEXT: sw t3, 20(a0)
+; RV32IXQCCMP-SR-NEXT: sw a3, 104(a0)
+; RV32IXQCCMP-SR-NEXT: sw a4, 100(a0)
+; RV32IXQCCMP-SR-NEXT: sw a5, 96(a0)
+; RV32IXQCCMP-SR-NEXT: sw s9, 92(a0)
+; RV32IXQCCMP-SR-NEXT: sw s8, 88(a0)
+; RV32IXQCCMP-SR-NEXT: sw s7, 84(a0)
+; RV32IXQCCMP-SR-NEXT: sw s6, 80(a0)
+; RV32IXQCCMP-SR-NEXT: sw s5, 76(a0)
+; RV32IXQCCMP-SR-NEXT: sw s4, 72(a0)
+; RV32IXQCCMP-SR-NEXT: sw s3, 68(a0)
+; RV32IXQCCMP-SR-NEXT: sw s2, 64(a0)
+; RV32IXQCCMP-SR-NEXT: sw s1, 60(a0)
+; RV32IXQCCMP-SR-NEXT: sw s0, 56(a0)
+; RV32IXQCCMP-SR-NEXT: sw t6, 52(a0)
+; RV32IXQCCMP-SR-NEXT: sw t5, 48(a0)
+; RV32IXQCCMP-SR-NEXT: sw t4, 44(a0)
+; RV32IXQCCMP-SR-NEXT: sw t3, 40(a0)
+; RV32IXQCCMP-SR-NEXT: sw t2, 36(a0)
+; RV32IXQCCMP-SR-NEXT: sw t1, 32(a0)
+; RV32IXQCCMP-SR-NEXT: sw t0, 28(a0)
+; RV32IXQCCMP-SR-NEXT: sw a7, 24(a0)
+; RV32IXQCCMP-SR-NEXT: sw a6, 20(a0)
; RV32IXQCCMP-SR-NEXT: lw a1, 12(sp) # 4-byte Folded Reload
; RV32IXQCCMP-SR-NEXT: sw a1, 16(a0)
; RV32IXQCCMP-SR-NEXT: lw a1, 16(sp) # 4-byte Folded Reload
@@ -3656,60 +3656,60 @@ define void @callee_no_irq() {
; RV64IXQCCMP-SR-NEXT: sd a1, 16(sp) # 8-byte Folded Spill
; RV64IXQCCMP-SR-NEXT: lw a1, 16(a0)
; RV64IXQCCMP-SR-NEXT: sd a1, 8(sp) # 8-byte Folded Spill
-; RV64IXQCCMP-SR-NEXT: lw t3, 20(a0)
-; RV64IXQCCMP-SR-NEXT: lw t4, 24(a0)
-; RV64IXQCCMP-SR-NEXT: lw t5, 28(a0)
-; RV64IXQCCMP-SR-NEXT: lw t6, 32(a0)
-; RV64IXQCCMP-SR-NEXT: lw s2, 36(a0)
-; RV64IXQCCMP-SR-NEXT: lw s3, 40(a0)
-; RV64IXQCCMP-SR-NEXT: lw s4, 44(a0)
-; RV64IXQCCMP-SR-NEXT: lw s5, 48(a0)
-; RV64IXQCCMP-SR-NEXT: lw s6, 52(a0)
-; RV64IXQCCMP-SR-NEXT: lw s7, 56(a0)
-; RV64IXQCCMP-SR-NEXT: lw s8, 60(a0)
-; RV64IXQCCMP-SR-NEXT: lw s9, 64(a0)
-; RV64IXQCCMP-SR-NEXT: lw s10, 68(a0)
-; RV64IXQCCMP-SR-NEXT: lw s11, 72(a0)
-; RV64IXQCCMP-SR-NEXT: lw ra, 76(a0)
-; RV64IXQCCMP-SR-NEXT: lw t2, 80(a0)
-; RV64IXQCCMP-SR-NEXT: lw s0, 84(a0)
-; RV64IXQCCMP-SR-NEXT: lw s1, 88(a0)
-; RV64IXQCCMP-SR-NEXT: lw t1, 92(a0)
-; RV64IXQCCMP-SR-NEXT: lw t0, 112(a0)
-; RV64IXQCCMP-SR-NEXT: lw a5, 116(a0)
-; RV64IXQCCMP-SR-NEXT: lw a3, 120(a0)
+; RV64IXQCCMP-SR-NEXT: lw a6, 20(a0)
+; RV64IXQCCMP-SR-NEXT: lw a7, 24(a0)
+; RV64IXQCCMP-SR-NEXT: lw t0, 28(a0)
+; RV64IXQCCMP-SR-NEXT: lw t1, 32(a0)
+; RV64IXQCCMP-SR-NEXT: lw t2, 36(a0)
+; RV64IXQCCMP-SR-NEXT: lw t3, 40(a0)
+; RV64IXQCCMP-SR-NEXT: lw t4, 44(a0)
+; RV64IXQCCMP-SR-NEXT: lw t5, 48(a0)
+; RV64IXQCCMP-SR-NEXT: lw t6, 52(a0)
+; RV64IXQCCMP-SR-NEXT: lw s0, 56(a0)
+; RV64IXQCCMP-SR-NEXT: lw s1, 60(a0)
+; RV64IXQCCMP-SR-NEXT: lw s2, 64(a0)
+; RV64IXQCCMP-SR-NEXT: lw s3, 68(a0)
+; RV64IXQCCMP-SR-NEXT: lw s4, 72(a0)
+; RV64IXQCCMP-SR-NEXT: lw s5, 76(a0)
+; RV64IXQCCMP-SR-NEXT: lw s6, 80(a0)
+; RV64IXQCCMP-SR-NEXT: lw s7, 84(a0)
+; RV64IXQCCMP-SR-NEXT: lw s8, 88(a0)
+; RV64IXQCCMP-SR-NEXT: lw s9, 92(a0)
+; RV64IXQCCMP-SR-NEXT: lw s10, 112(a0)
+; RV64IXQCCMP-SR-NEXT: lw s11, 116(a0)
+; RV64IXQCCMP-SR-NEXT: lw ra, 120(a0)
; RV64IXQCCMP-SR-NEXT: lw a1, 124(a0)
-; RV64IXQCCMP-SR-NEXT: lw a7, 96(a0)
-; RV64IXQCCMP-SR-NEXT: lw a6, 100(a0)
-; RV64IXQCCMP-SR-NEXT: lw a4, 104(a0)
+; RV64IXQCCMP-SR-NEXT: lw a5, 96(a0)
+; RV64IXQCCMP-SR-NEXT: lw a4, 100(a0)
+; RV64IXQCCMP-SR-NEXT: lw a3, 104(a0)
; RV64IXQCCMP-SR-NEXT: lw a2, 108(a0)
; RV64IXQCCMP-SR-NEXT: sw a1, 124(a0)
-; RV64IXQCCMP-SR-NEXT: sw a3, 120(a0)
-; RV64IXQCCMP-SR-NEXT: sw a5, 116(a0)
-; RV64IXQCCMP-SR-NEXT: sw t0, 112(a0)
+; RV64IXQCCMP-SR-NEXT: sw ra, 120(a0)
+; RV64IXQCCMP-SR-NEXT: sw s11, 116(a0)
+; RV64IXQCCMP-SR-NEXT: sw s10, 112(a0)
; RV64IXQCCMP-SR-NEXT: sw a2, 108(a0)
-; RV64IXQCCMP-SR-NEXT: sw a4, 104(a0)
-; RV64IXQCCMP-SR-NEXT: sw a6, 100(a0)
-; RV64IXQCCMP-SR-NEXT: sw a7, 96(a0)
-; RV64IXQCCMP-SR-NEXT: sw t1, 92(a0)
-; RV64IXQCCMP-SR-NEXT: sw s1, 88(a0)
-; RV64IXQCCMP-SR-NEXT: sw s0, 84(a0)
-; RV64IXQCCMP-SR-NEXT: sw t2, 80(a0)
-; RV64IXQCCMP-SR-NEXT: sw ra, 76(a0)
-; RV64IXQCCMP-SR-NEXT: sw s11, 72(a0)
-; RV64IXQCCMP-SR-NEXT: sw s10, 68(a0)
-; RV64IXQCCMP-SR-NEXT: sw s9, 64(a0)
-; RV64IXQCCMP-SR-NEXT: sw s8, 60(a0)
-; RV64IXQCCMP-SR-NEXT: sw s7, 56(a0)
-; RV64IXQCCMP-SR-NEXT: sw s6, 52(a0)
-; RV64IXQCCMP-SR-NEXT: sw s5, 48(a0)
-; RV64IXQCCMP-SR-NEXT: sw s4, 44(a0)
-; RV64IXQCCMP-SR-NEXT: sw s3, 40(a0)
-; RV64IXQCCMP-SR-NEXT: sw s2, 36(a0)
-; RV64IXQCCMP-SR-NEXT: sw t6, 32(a0)
-; RV64IXQCCMP-SR-NEXT: sw t5, 28(a0)
-; RV64IXQCCMP-SR-NEXT: sw t4, 24(a0)
-; RV64IXQCCMP-SR-NEXT: sw t3, 20(a0)
+; RV64IXQCCMP-SR-NEXT: sw a3, 104(a0)
+; RV64IXQCCMP-SR-NEXT: sw a4, 100(a0)
+; RV64IXQCCMP-SR-NEXT: sw a5, 96(a0)
+; RV64IXQCCMP-SR-NEXT: sw s9, 92(a0)
+; RV64IXQCCMP-SR-NEXT: sw s8, 88(a0)
+; RV64IXQCCMP-SR-NEXT: sw s7, 84(a0)
+; RV64IXQCCMP-SR-NEXT: sw s6, 80(a0)
+; RV64IXQCCMP-SR-NEXT: sw s5, 76(a0)
+; RV64IXQCCMP-SR-NEXT: sw s4, 72(a0)
+; RV64IXQCCMP-SR-NEXT: sw s3, 68(a0)
+; RV64IXQCCMP-SR-NEXT: sw s2, 64(a0)
+; RV64IXQCCMP-SR-NEXT: sw s1, 60(a0)
+; RV64IXQCCMP-SR-NEXT: sw s0, 56(a0)
+; RV64IXQCCMP-SR-NEXT: sw t6, 52(a0)
+; RV64IXQCCMP-SR-NEXT: sw t5, 48(a0)
+; RV64IXQCCMP-SR-NEXT: sw t4, 44(a0)
+; RV64IXQCCMP-SR-NEXT: sw t3, 40(a0)
+; RV64IXQCCMP-SR-NEXT: sw t2, 36(a0)
+; RV64IXQCCMP-SR-NEXT: sw t1, 32(a0)
+; RV64IXQCCMP-SR-NEXT: sw t0, 28(a0)
+; RV64IXQCCMP-SR-NEXT: sw a7, 24(a0)
+; RV64IXQCCMP-SR-NEXT: sw a6, 20(a0)
; RV64IXQCCMP-SR-NEXT: ld a1, 8(sp) # 8-byte Folded Reload
; RV64IXQCCMP-SR-NEXT: sw a1, 16(a0)
; RV64IXQCCMP-SR-NEXT: ld a1, 16(sp) # 8-byte Folded Reload
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