[llvm] [AMDGPU] Fold isnan+fptosi select to fptosi (PR #200960)

[Adel Ejjeh via llvm-commits]

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@@ -18412,6 +18412,41 @@ SDValue SITargetLowering::performSelectCombine(SDNode *N,
   SDValue RHS = Cond.getOperand(1);
   ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
 
+  // Fold: select (setcc X, NonNaN, SETUO), 0, (fp_to_sint X) -> fp_to_sint X
+  // Fold: select (setcc X, NonNaN, SETO), (fp_to_sint X), 0 -> fp_to_sint X
+  // Also look through an AND mask on the fp_to_sint result.
+  // V_CVT_I32_F32, V_CVT_U32_F32, V_CVT_I32_F64, V_CVT_U32_F64 already
+  // return 0 for NaN inputs, so the isnan guard is redundant.
+  {
+    // Identify the guarded value and the zero constant based on SETUO/SETO.
+    SDValue GuardedVal;
+    if (CC == ISD::SETUO && isNullConstant(TrueVal))
+      GuardedVal = FalseVal;
+    else if (CC == ISD::SETO && isNullConstant(FalseVal))
+      GuardedVal = TrueVal;
+
+    if (GuardedVal) {
+      // RHS of the comparison must be a known non-NaN value or equal to LHS
+      // (fcmp uno X, X). SETUO is true when either operand is NaN, so we
+      // must ensure RHS cannot independently be NaN.
+      bool RHSSafe =
+          RHS == LHS || isNullFPConstant(RHS) ||
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adelejjeh wrote:

Fixed

https://github.com/llvm/llvm-project/pull/200960