[llvm] [AMDGPU] Fold isnan+fptosi select to fptosi (PR #200960)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/SIISelLowering.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index d7ddf4992..ffc0f91cc 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -18412,9 +18412,9 @@ SDValue SITargetLowering::performSelectCombine(SDNode *N,
   SDValue RHS = Cond.getOperand(1);
   ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
 
-  // Fold: select (setcc X, NonNaN, SETUO), 0, (fp_to_sint X) -> fp_to_sint_sat X
-  // Fold: select (setcc X, NonNaN, SETO), (fp_to_sint X), 0 -> fp_to_sint_sat X
-  // Also look through an AND mask on the fp_to_sint result.
+  // Fold: select (setcc X, NonNaN, SETUO), 0, (fp_to_sint X) -> fp_to_sint_sat
+  // X Fold: select (setcc X, NonNaN, SETO), (fp_to_sint X), 0 -> fp_to_sint_sat
+  // X Also look through an AND mask on the fp_to_sint result.
   {
     // Identify the guarded value and the zero constant based on SETUO/SETO.
     SDValue GuardedVal;
@@ -18427,9 +18427,8 @@ SDValue SITargetLowering::performSelectCombine(SDNode *N,
       // RHS of the comparison must be a known non-NaN value or equal to LHS
       // (fcmp uno X, X). SETUO is true when either operand is NaN, so we
       // must ensure RHS cannot independently be NaN.
-      bool RHSSafe =
-          RHS == LHS ||
-          (isa<ConstantFPSDNode>(RHS) && !cast<ConstantFPSDNode>(RHS)->isNaN());
+      bool RHSSafe = RHS == LHS || (isa<ConstantFPSDNode>(RHS) &&
+                                    !cast<ConstantFPSDNode>(RHS)->isNaN());
 
       if (RHSSafe) {
         // Generate the new node (ISD::FP_TO_[SU]INT_SAT) to replace the select.
@@ -18438,23 +18437,27 @@ SDValue SITargetLowering::performSelectCombine(SDNode *N,
         // Look through an AND mask to find the fp_to_sint/uint underneath.
         SDValue Conv = GuardedVal;
         bool HasAndMask = false;
-        if (Conv.getOpcode() == ISD::AND) {  
+        if (Conv.getOpcode() == ISD::AND) {
           Conv = Conv.getOperand(0);
           HasAndMask = true;
         }
 
         if (Conv.getOperand(0) == LHS && Conv.getValueType() == MVT::i32) {
           if (Conv.getOpcode() == ISD::FP_TO_SINT)
-            NewNode = DCI.DAG.getNode(ISD::FP_TO_SINT_SAT, SDLoc(N), MVT::i32, LHS, DCI.DAG.getValueType(MVT::i32));
+            NewNode = DCI.DAG.getNode(ISD::FP_TO_SINT_SAT, SDLoc(N), MVT::i32,
+                                      LHS, DCI.DAG.getValueType(MVT::i32));
           if (Conv.getOpcode() == ISD::FP_TO_UINT)
-            NewNode = DCI.DAG.getNode(ISD::FP_TO_UINT_SAT, SDLoc(N), MVT::i32, LHS, DCI.DAG.getValueType(MVT::i32));
+            NewNode = DCI.DAG.getNode(ISD::FP_TO_UINT_SAT, SDLoc(N), MVT::i32,
+                                      LHS, DCI.DAG.getValueType(MVT::i32));
         }
 
         // Replace the node if we created a new one
         if (NewNode) {
           // If there was an AND mask, reapply it to the new node.
           if (HasAndMask)
-            NewNode = DCI.DAG.getNode(ISD::AND, SDLoc(N), GuardedVal.getValueType(), NewNode, GuardedVal.getOperand(1));
+            NewNode =
+                DCI.DAG.getNode(ISD::AND, SDLoc(N), GuardedVal.getValueType(),
+                                NewNode, GuardedVal.getOperand(1));
           return NewNode;
         }
       }

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https://github.com/llvm/llvm-project/pull/200960