[clang] [llvm] [AArch64] Add 9.7 CVT data processing intrinsics (PR #186807)

[via llvm-commits]

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@@ -997,6 +997,33 @@ def SVCVTLT_Z_F32_F16  : SInst<"svcvtlt_f32[_f16]", "dPh", "f", MergeZeroExp, "a
 def SVCVTLT_Z_F64_F32  : SInst<"svcvtlt_f64[_f32]", "dPh", "d", MergeZeroExp, "aarch64_sve_fcvtlt_f64f32",  [IsOverloadNone, VerifyRuntimeMode]>;
 
 }
+
+let SVETargetGuard = "sve2p3|sme2p3", SMETargetGuard = "sve2p3|sme2p3" in {
+def SVCVTZN_S8_F16  : SInst<"svcvtzn_s8[_f16_x2]",  "d2.O", "c", MergeNone, "aarch64_sve_fcvtzsn_x2", [IsOverloadWhileOrMultiVecCvt, VerifyRuntimeMode]>;
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Lukacma wrote:

This can be made more concise similarly to my lower comment. Also not sure why  _s8 and so on are mandatory. Here I cannot imagine any 4-way narrowing as it wouldn't fill whole vector. 

https://github.com/llvm/llvm-project/pull/186807