[llvm] [AMDGPU] Post-RA Peephole for latency-hiding and hazard-avoidance bet… (PR #191319)

[Zeng Wu via llvm-commits]

zwu-2025 wrote:

> This doesn't really belong in this pass. This also needs an end to end IR test justification

For pass to do the change from `buffer_load --> (n x mfma)` into `mfma -->buffer_load --> (n - 1) x mfma`, especially in a loop,
- before `ISel`
  The only place I can find is the DAG scheduling in the end of `ISel` and my concern is that the changes could be messed up in the following `machine-scheduler`.
- after `ISel`
  - The `Optimize Loads`  in Pre-RA `peephole-opt`, but it requires the `load` has `MCID::FoldableAsLoad` but it seems not used in our table-gen.
  - `AMDGPUIGroupLP`, which does some mfma scheduling over `machine-sched` but it is not turned on in the default pipeline so if I use it, I am not sure the impact on others. The same concern for `modulo-scheduling`.
  - Change `machine-scheduler`;

Finally, changing `machine-scheduler` is the only viable option and could you give some comments on this?


https://github.com/llvm/llvm-project/pull/191319